Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy

Silicon Heterostructure Handbook Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Lay...

Author: John D. Cressler

59 downloads 868 Views 37MB Size Report

This content was uploaded by our users and we assume good faith they have the permission to share this book. If you own the copyright to this book and it is wrongfully on our website, we offer a simple DMCA procedure to remove your content from our site. Start by pressing the button below!

Report copyright / DMCA form

DOWNLOAD PDF

Silicon Heterostructure Handbook Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy

© 2006 by Taylor & Francis Group, LLC

Silicon Heterostructure Handbook Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy

Edited by

John D. Cressler

Boca Raton London New York

A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc.

© 2006 by Taylor & Francis Group, LLC

Published in 2006 by CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2006 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-10: 0-8493-3559-0 (Hardcover) International Standard Book Number-13: 978-0-8493-3559-4 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Catalog record is available from the Library of Congress

Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com Taylor & Francis Group is the Academic Division of T&F Informa plc.

© 2006 by Taylor & Francis Group, LLC

and the CRC Press Web site at http://www.crcpress.com

For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success. I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings. And . . . For Maria: My beautiful wife, best friend, and soul mate for these 22 years. For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts. May your journey of discovery never end.

© 2006 by Taylor & Francis Group, LLC

He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth. Plato ¯Œ ı Ø Ø łı ı `ª ªØÆ Ł ŒÆØ `º ŁØ Æ, ŒÆØ Ø `Œ Ł ªØÆ , ‚Æ Ø ¢ æÆ æ ø ºº Æ ŒØ ŒłØ `ŁÆ ŒÆØ ¨, ¯ æØŁ `ºŁØÆ. Pl atvna§

© 2006 by Taylor & Francis Group, LLC

Preface

While the idea of cleverly using silicon–germanium (SiGe) and silicon (Si) strained-layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality. The final success of creating novel Si heterostructure transistors with performance far superior to their Si-only homojunction cousins, while maintaining strict compatibility with the massive economy-of-scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world. In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications. As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations. This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this handbook are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty-first century. While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings-it-all-together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applications. Each chapter is written by a leading international expert, ensuring adequate depth of coverage, up-to-date research results, and a comprehensive list of seminal references. A novel aspect of this handbook is that it also contains ‘‘snap-shot’’ views of the industrial ‘‘state-of-the-art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry. So who should buy this 1,200þ page beast? The Silicon Heterostructure Handbook is intended for a number of different audiences and venues. It should prove to be a useful resource as: 1. A hands-on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications 2. A hands-on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting-edge integrated circuit technologies vii © 2006 by Taylor & Francis Group, LLC

viii

Preface

3. A textbook for use in graduate-level instruction in this field or 4. A reference for technical managers and even technical support/technical sales personnel in the semiconductor industry. It is assumed that the reader has some modest background in semiconductor physics and semiconductor devices (at the advanced undergraduate level), but each chapter is self-contained in its treatment. In this age of extreme activity, in which we are all seriously pressed for time and overworked, my success in getting such a large collection of rather famous people to commit their precious time to my vision for this project was immensely satisfying. I am happy to say that my authors made the process quite painless, and I am extremely grateful for their help. The list of contributors to this handbook actually reads like a global ‘‘who’s who’’ of the silicon heterostructure field, and is impressive by any standard. I would like to formally thank each of my colleagues for their hard work and dedication to executing my vision of producing a lasting Si heterostructure ‘‘bible.’’ In order of appearance, the ‘‘gurus’’ of our field include: Bernard S. Meyerson, IBM Systems and Technology Group, USA Bernd Tillack, IHP, Germany Peter Zaumseil, IHP, Germany Didier Dutartre, ST Microelectronics, France F. Dele´glise, ST Microelectronics, France C. Fellous, ST Microelectronics, France L. Rubaldo, ST Microelectronics, France A. Talbot, ST Microelectronics, France Michael Oehme, University of Stuttgart, Germany Erich Kasper, University of Stuttgart, Germany Thomas N. Adam, IBM Microelectronics, USA Anthony R. Peaker, University of Manchester, United Kingdom V.P. Markevich, University of Manchester, United Kingdom Armin Fischer, IHP, Germany Judy L. Hoyt, Massachusetts Institute of Technology, USA H. Jo¨rg Osten, University of Hanover, Germany C.K. Maiti, Indian Institute of Technology, Kharagpur, India S. Monfray, ST Microelectronics, France S. Borel, CEA-LETI, France Thomas Skotnicki, ST Microelectronics, France David L. Harame, IBM Microelectronics, USA Jin Cai, IBM Thomas J. Watson Research Center, USA Tak H. Ning, IBM Thomas J. Watson Research Center, USA Joachim N. Burghartz, Delft University of Technology, The Netherlands Alvin J. Joseph, IBM Microelectronics, USA James S. Dunn, IBM Microelectronics, USA Paul H.G. Kempf, Jazz Semiconductor, USA Katsuyoshi Washio, Hitachi, Japan Thomas F. Meister, Infineon, Germany H. Scha¨fer, Infineon, Germany W. Perndl, Infineon, Germany J. Bo¨ck, Infineon, Germany Dieter Knoll, IHP, Germany Alain Chantre, ST Microelectronics, France M. Laurens, ST Microelectronics, France B. Szelag, ST Microelectronics, France

© 2006 by Taylor & Francis Group, LLC

Preface

ix

H. Baudry, ST Microelectronics, France P. Chevalier, ST Microelectronics, France J. Mourier, ST Microelectronics, France G. Troillard, ST Microelectronics, France B. Martinet, ST Microelectronics, France M. Marty, ST Microelectronics, France A. Monroy, ST Microelectronics, France Badih El-Kareh, Texas Instruments, USA Scott Balster, Texas Instruments, USA P. Steinmann, Texas Instruments, USA Hiroshi Yasuda, Texas Instruments, USA Roy Colclaser, Philips Semiconductors, USA Peter Deixler, Philips Semiconductors, USA Guofu Niu, Auburn University, USA David R. Greenberg, IBM Thomas J. Watson Research Center, USA Jae-Sung Rieh, Korea University, Korea Greg Freeman, IBM Microelectronics, USA Andres Stricker, IBM Microelectronics, USA Kem Ken (Rim) IBM Thomas J. Watson Research Center, USA Scott E. Thompson, University of Florida, USA Sanjay Banerjee, University of Texas at Austin, USA Soichiro Tsujino, Paul Scherrer Institute, Switzerland Detlev Gru¨tzmacher, Paul Scherrer Institute, Switzerland Ulf Gennser, CNRS-LPN, France Eugene A. Fitzgerald, Massachusetts Institute of Technology, USA Robert Hull, University of Virginia, USA Kang L. Wang, University of California at Los Angeles, USA S. Tong, University of California at Los Angeles, USA H.J. Kim, University of California at Los Angeles, USA Lorenzo Colace, University ‘‘Roma Tre’’, Italy Gianlorenzo Masini, University ‘‘Roma Tre’’, Italy Gaetano Assanto, University ‘‘Roma Tre’’, Italy Wei-Xin Ni, Linko¨ping University, Sweden Anders Elfving, Linko¨ping University, Sweden Douglas J. Paul, University of Cambridge, United Kingdom Robert A. Groves, IBM Microelectronics, USA David C. Sheridan, IBM Microelectronics, USA Jeffrey B. Johnson, IBM Microelectronics, USA Rajendran Krishnasamy, IBM Microelectronics, USA Michael Schro¨ter, University of California at San Diego, USA Slobodan Mijalkovic´, Delft University of Technology, The Netherlands Sue E. Strang, IBM Microelectronics, USA Raminderpal Singh, IBM Systems and Technology Group, USA Youri V. Tretiakov, RF Micro Devices, USA Qingqing Liang, Georgia Institute of Technology, USA Lawrence E. Larson, University of California at San Diego, USA Donald Y.C. Lie, Dynamic Research Corporation and University of California at San Diego, USA Leo C.N. de Vreede, Delft University of Technology, The Netherlands Mark P. van der Heijden, Delft University of Technology, The Netherlands Hermann Schumacher, University of Ulm, Germany Johann-Friedrich Luy, DaimlerChrysler, Germany

© 2006 by Taylor & Francis Group, LLC

x

Preface

John R. Long, Delft University of Technology, The Netherlands Sudipto Chakraborty, Georgia Institute of Technology, USA Joy Laskar, Georgia Institute of Technology, USA John Papapolymerou, Georgia Institute of Technology, USA Manos Tentzeris, Georgia Institute of Technology, USA Rong Lin Li, Georgia Institute of Technology, USA Kyutae Lim, Georgia Institute of Technology, USA Stephane Pinel, Georgia Institute of Technology, USA Daniel A. Friedman, IBM Thomas J. Watson Research Center, USA Mounir Meghelli, IBM Thomas J. Watson Research Center, USA Didier Belot, ST Microelectronics, France Ramana M. Malladi, IBM Microelectronics, USA I would also like to thank my graduate students and post-docs, past and present, for their dedication and tireless work in this fascinating field. I rest on their shoulders. They include: David Richey, Alvin Joseph, Bill Ansley, Juan Rolda´n, Stacey Salmon, Lakshmi Vempati, Jeff Babcock, Suraj Mathew, Kartik Jayanaraynan, Greg Bradford, Usha Gogineni, Gaurab Banerjee, Shiming Zhang, Krish Shivaram, Dave Sheridan, Gang Zhang, Ying Li, Zhenrong Jin, Qingqing Liang, Ram Krithivasan, Yun Luo, Tianbing Chen, Enhai Zhao, Yuan Lu, Chendong Zhu, Jon Comeau, Jarle Johansen, Joel Andrews, Lance Kuo, Xiangtao Li, Bhaskar Banerjee, Curtis Grens, Akil Sutton, Adnan Ahmed, Becca Haugerud, Mustayeen Nayeem, Mustansir Pratapgarhwala, Guofu Niu, Emery Chen, Jongsoo Lee, and Gnana Prakash. Finally, I am grateful to Tai Soda at Marcel Dekker (now Taylor & Francis) for talking me into this project, and supporting me along the way. I would also like to thank the production team at Taylor & Francis for their able assistance (and patience!), especially Jessica Vakili, Kavitha Kuttikan, Joanne Blake, Jim McGovern, Irina Eirush, Jacqueline Callahan, and David Grubbs. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. In the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life on planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay attention. It has been immensely satisfying to see both the dream of Si/SiGe bandgap engineering, and this handbook, come to fruition. I hope our efforts please you. Enjoy!

John D. Cressler Editor

© 2006 by Taylor & Francis Group, LLC

Foreword

Progress in a given field of technology is both desired and expected to follow a stable and predictable long-term trajectory. Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound. Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades. One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long-term prospects for the continuance of device density scaling itself. New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely. Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future. This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path. The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry. Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor-operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies. However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors. Bipolar junction transistor (BJT) technology, dominant in high-end computing applications during the mid-1980s, was being aggressively scaled to provide the requisite performance for future systems. By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions. This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day. Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20–30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant. Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage. This was due to the onset of band-to-band tunneling between heavily doped emitter and base regions, rendering such devices unreliable. This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence. Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing. A revolution in bipolar fabrication methodology, moving xi © 2006 by Taylor & Francis Group, LLC

xii

Foreword

from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon-based bipolar transistor performance to levels never anticipated. It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz. A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition. The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate ecosystem to enable its effective creation and utilization. This text is meant to describe the eco-system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented. Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development. Rapid device progress that followed drove silicon-based technology (recall that SiGe technology is still a silicon-based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques. As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control. Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe-based HEMTs, tunneling devices, mobilityenhanced CMOS, optical detectors, and more to come. Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling. Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level. Access to high-performance SiGe technology has spurred a rich diversity of exploratory and commercial circuit applications, many elaborated in this text. Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high-performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS. These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions. In its transition from scientific curiosity to pervasive technology, SiGe-based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed.

Bernard S. Meyerson IBM Systems and Technology Group

© 2006 by Taylor & Francis Group, LLC

The Editor

John D. Cressler received a B.S. in Physics from the Georgia Institute of Technology (Georgia Tech), Atlanta, Georgia, in 1984, and an M.S. in 1987 and Ph.D. in Applied Physics in 1990 from Columbia University, New York. From 1984 to 1992 he was on the research staff at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York, working on high-speed Si and SiGe bipolar devices and technology. In 1992 Dr. Cressler left IBM Research to join the faculty at Auburn University, Auburn, Alabama, where he served until 2002. At the time of his leaving Auburn University, he was Philpott–Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and Director of the Alabama Microelectronics Science and Technology Center. In 2002, Dr. Cressler joined the faculty at Georgia Tech, where he is currently Byers Professor of Electrical and Computer Engineering. His research interests include SiGe devices and technology; Si-based RF/ microwave/millimeter-wave devices and circuits; radiation effects; device-circuit interactions; noise and linearity; cryogenic electronics; SiC devices; reliability physics; extreme environment electronics, 2-D/3-D device-level simulation; and compact circuit modeling. He has published more than 300 technical papers related to his research, and is author of the books Silicon–Germanium Heterojunction Bipolar Transistors (with Guofu Niu, Artech House, 2003), and Reinventing Teenagers: The Gentle Art of Instilling Character in Our Young People (Xlibris, 2004) (a slightly different genre!). Dr. Cressler was Associate Editor of the IEEE Journal of Solid-State Circuits (1998–2001), and is currently Associate Editor of the IEEE Transactions on Nuclear Science (2003–2006). He served on the technical program committees of the IEEE International Solid-State Circuits Conference (1992–1998, 1999–2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995–1999), the IEEE International Electron Devices Meeting (1996–1997), and the IEEE Nuclear and Space Radiation Effects Conference (1999–2000, 2002–2004). He currently serves on the executive steering committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as international program advisor for the IEEE European Workshop on Low-Temperature Electronics, on the technical program committee for the IEEE International SiGe Technology and Device Meeting, and as subcommittee chair of the 2004 Electrochemical Society Symposium of SiGe: Materials, Processing, and Devices. He was the Technical Program Chair of the 1998 IEEE International Solid-State Circuits Conference, and the Conference Co-Chair of the 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Dr. Cressler was appointed an IEEE Electron Device Society Distinguished Lecturer in 1994 and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program. He received the 1996 C. Holmes MacDonald National Outstanding Teacher Award by Eta Kappa Nu, xiii © 2006 by Taylor & Francis Group, LLC

xiv

Foreword

the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, and an IEEE Third Millennium Medal in 2000. He is an IEEE Fellow. On a more personal note, John’s hobbies include hiking, gardening, bonsai, all things Italian, collecting (and drinking!) fine wines, cooking, history, and carving walking sticks, not necessarily in that order. He considers teaching to be his vocation. John has been married to Maria, his best friend and soul mate, for 22+ years, and is the proud father of three budding scholars: Matt (21), Christina (19), and Jo-Jo (16).

© 2006 by Taylor & Francis Group, LLC

Table of Contents

1 1.1 1.2

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

Introduction The Big Picture ........................................................................................................................ 1.1-3 J.D. Cressler A Brief History of the Field .................................................................................................. 1.2-15 J.D. Cressler

SiGe and Si Strained-Layer Epitaxy Overview: SiGe and Si Strained-Layer Epitaxy ................................................................... 2.1-31 J.D. Cressler Strained SiGe and Si Epitaxy ................................................................................................ 2.2-33 B. Tillack and P. Zaumseil Si/SiGe(C) Eptiaxy by RTCVD.............................................................................................. 2.3-45 D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot MBE Growth Techniques ...................................................................................................... 2.4-85 M. Oehme and E. Kasper UHV/CVD Growth Techniques ............................................................................................ 2.5-95 T.N. Adam Defects and Diffusion in SiGe and Strained Si ................................................................. 2.6-107 A.R. Peaker and V. Markevich Stability Constraints in SiGe Epitaxy................................................................................. 2.7-127 A. Fischer Electronic Properties of Strained Si/SiGe and Si1yCy Alloys.......................................... 2.8-143 J.L. Hoyt Carbon Doping of SiGe....................................................................................................... 2.9-157 H.J. Osten Contact Metallization on Silicon–Germanium................................................................ 2.10-171 C.K. Maiti Selective Etching Techniques for SiGe/Si......................................................................... 2.11-187 S. Monfray, S. Borel, and T. Skotnicki

xv © 2006 by Taylor & Francis Group, LLC

xvi

3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

3.11 3.12

4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Table of Contents

Fabrication of SiGe HBT BiCMOS Technology Overview: Fabrication of SiGe HBT BiCMOS Technology .............................................. 3.1-213 J.D. Cressler Device Structures and BiCMOS Integration ..................................................................... 3.2-215 D.L. Harame SiGe HBTs on CMOS-Compatible SOI .............................................................................. 3.3-233 J. Cai and T.H. Ning Passive Components ............................................................................................................ 3.4-249 J.N. Burghartz Industry Examples at State-of-the-Art: IBM ..................................................................... 3.5-265 A.J. Joseph and J.S. Dunn Industry Examples at State-of-the-Art: Jazz...................................................................... 3.6-283 P.H.G. Kempf Industry Examples at State-of-the-Art: Hitachi ................................................................ 3.7-295 K. Washio Industry Examples at State-of-the-Art: Infineon .............................................................. 3.8-307 T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck Industry Examples at State-of-the-Art: IHP...................................................................... 3.9-321 D. Knoll Industry Examples at State-of-the-Art: ST ...................................................................... 3.10-343 A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy Industry Examples at State-of-the-Art: Texas Instruments ........................................... 3.11-357 B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda Industry Examples at State-of-the-Art: Philips............................................................... 3.12-371 R. Colclaser and P. Deixler

SiGe HBTs Overview: SiGe HBTs .......................................................................................................... 4.1-389 J.D. Cressler Device Physics...................................................................................................................... 4.2-391 J.D. Cressler Second-Order Effects........................................................................................................... 4.3-411 J.D. Cressler Low-Frequency Noise .......................................................................................................... 4.4-427 G. Niu Broadband Noise ................................................................................................................. 4.5-439 D.R. Greenberg Microscopic Noise Simulation ............................................................................................ 4.6-459 G. Niu Linearity ............................................................................................................................... 4.7-475 G. Niu pnp SiGe HBTs..................................................................................................................... 4.8-489 J.D. Cressler

© 2006 by Taylor & Francis Group, LLC

Table of Contents

4.9 4.10 4.11 4.12 4.13 4.14

5

xvii

Temperature Effects............................................................................................................. 4.9-497 J.D. Cressler Radiation Effects................................................................................................................ 4.10-511 J.D. Cressler Reliability Issues ................................................................................................................ 4.11-525 J.D. Cressler Self-Heating and Thermal Effects .................................................................................... 4.12-539 J.-S. Rieh Device-Level Simulation.................................................................................................... 4.13-553 G. Niu SiGe HBT Performance Limits ......................................................................................... 4.14-571 G. Freeman, A. Stricker, J.-S. Rieh, and D.R. Greenberg

Heterostructure FETs

5.1

Overview: Heterostructure FETs ........................................................................................ 5.1-585 J.D. Cressler 5.2 Biaxial Strained Si CMOS ................................................................................................... 5.2-587 K. Rim 5.3 Uniaxial Stressed Si MOSFET............................................................................................. 5.3-601 S.E. Thompson 5.4 SiGe-Channel HFETs ........................................................................................................... 5.4-615 S. Banerjee 5.5 Industry Examples at State-of-the-Art: Intel’s 90 nm Logic Technologies ..................... 5.5-629 S.E. Thompson

6

Other Heterostructure Devices

6.1

Overview: Other Heterostructure Devices ........................................................................ 6.1-645 J.D. Cressler 6.2 Resonant Tunneling Devices............................................................................................... 6.2-647 S. Tsujino, D. Gru¨tzmacher, and U. Gennser 6.3 IMPATT Diodes ................................................................................................................... 6.3-661 E. Kasper and M. Oehme 6.4 Engineered Substrates for Electronic and Optoelectronic Systems................................. 6.4-679 E.A. Fitzgerald 6.5 Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy .......................................... 6.5-699 R. Hull

7 7.1 7.2

Optoelectronic Components Overview: Optoelectronic Components............................................................................. 7.1-717 J.D. Cressler Si–SiGe LEDs........................................................................................................................ 7.2-719 K.L. Wang, S. Tong, and H.J. Kim

© 2006 by Taylor & Francis Group, LLC

xviii

Table of Contents

7.3

Near-Infrared Detectors ...................................................................................................... 7.3-731 L. Colace, G. Masini, and G. Assanto 7.4 Si-based Photonic Transistors for Integrated Optoelectronics ........................................ 7.4-751 W.X. Ni and A. Elfving 7.5 Si–SiGe Quantum Cascade Emitters .................................................................................. 7.5-763 D.J. Paul

8 8.1 8.2 8.3 8.4 8.5 8.6 8.7

8.8 8.9

9 9.1 9.2 9.3 9.4 9.5 9.6 9.7

Measurement and Modeling Overview: Measurement and Modeling ............................................................................. 8.1-779 J.D. Cressler Best-Practice AC Measurement Techniques ...................................................................... 8.2-781 R.A. Groves Industrial Application of TCAD for SiGe Development .................................................. 8.3-793 D.C. Sheridan, J.B. Johnson, and R. Krishnasamy Compact Modeling of SiGe HBTs: HICUM....................................................................... 8.4-807 M. Schro¨ter Compact Modeling of SiGe HBTs: MEXTRAM................................................................. 8.5-825 S. Mijalkovic CAD Tools and Design Kits ................................................................................................ 8.6-847 S.E. Strang Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs ......................................................................................... 8.7-859 R. Singh Transmission Lines on Si .................................................................................................... 8.8-871 Y.V. Tretiakov Improved De-Embedding Techniques................................................................................ 8.9-883 Q. Liang

Circuits and Applications Overview: Circuits and Applications ................................................................................. 9.1-899 J.D. Cressler SiGe as an Enabler for Wireless Communications Systems............................................. 9.2-901 L.E. Larson and D.Y.C. Lie LNA Optimization Strategies.............................................................................................. 9.3-923 Q. Liang Linearization Techniques .................................................................................................... 9.4-937 L.C.N. de Vreede and M.P. van der Heijden SiGe MMICs ......................................................................................................................... 9.5-979 H. Schumacher SiGe Millimeter-Wave ICs................................................................................................... 9.6-997 J.-F. Luy Wireless Building Blocks Using SiGe HBTs .................................................................... 9.7-1007 J.R. Long

© 2006 by Taylor & Francis Group, LLC

Table of Contents

xix

9.8

Direct Conversion Architectures for SiGe Radios .......................................................... 9.8-1049 S. Chakraborty and J. Laskar 9.9 RF MEMS Techniques in Si/SiGe ..................................................................................... 9.9-1075 J. Papapolymerou 9.10 Wideband Antennas on Silicon ...................................................................................... 9.10-1099 M.M. Tentzeris and R.L. Li 9.11 Packaging Issues for SiGe Circuits................................................................................. 9.11-1119 K. Lim, S. Pinel, and J. Laskar 9.12 Industry Examples at State-of-the-Art: IBM ................................................................. 9.12-1127 D.J. Friedman and M. Meghelli 9.13 Industry Examples at State-of-the-Art: Hitachi ............................................................ 9.13-1145 K. Washio 9.14 Industry Examples at State-of-the-Art: ST .................................................................... 9.14-1155 D. Belot

Appendices A.1 Properties of Silicon and Germanium ............................................................................ A.1-1177 J.D. Cressler A.2 The Generalized Moll-Ross Relations ............................................................................. A.2-1181 J.D. Cressler A.3 Integral Charge-Control Relations .................................................................................. A.3-1187 M. Schro¨ter A.4 Sample SiGe HBT Compact Model Parameters ............................................................. A.4-1201 R.M. Malladi

© 2006 by Taylor & Francis Group, LLC

1 Introduction 1.1

The Big Picture J.D. Cressler......................................................................................... 1.1-3 The Communications Revolution . Bandgap Engineering in the Silicon Material System . Terminology and Definitions . The Application Space . Performance Limits and Future Directions

1.2

A Brief History of the Field J.D. Cressler.................................................................. 1.2-15 Si–SiGe Strained Layer Epitaxy . SiGe HBTs . SiGe–Strained Si FETs and Other SiGe Devices

1.1-1 © 2006 by Taylor & Francis Group, LLC

1.1 The Big Picture 1.1.1 1.1.2

John D. Cressler Georgia Institute of Technology

1.1.3 1.1.4 1.1.5

The Communications Revolution................................ 1.1-3 Bandgap Engineering in the Silicon Material System ............................................................. 1.1-5 Terminology and Definitions ....................................... 1.1-6 The Application Space .................................................. 1.1-7 Performance Limits and Future Directions .............. 1.1-11

1.1.1 The Communications Revolution We are at a unique juncture in the history of humankind, a juncture that amazingly we engineers and scientists have dreamed up and essentially created on our own. This pivotal event can be aptly termed the ‘‘Communications Revolution,’’ and the twenty-first century, our century, will be the era of human history in which this revolution plays itself out. This communications revolution can be functionally defined and characterized by the pervasive acquisition, manipulation, storage, transformation, and transmission of ‘‘information’’ on a global scale. This information, or more generally, knowledge, in its infinitely varied forms and levels of complexity, is gathered from our analog sensory world, transformed in very clever ways into logical ‘‘1’’s and ‘‘0’’s for ease of manipulation, storage, and transmission, and subsequently regenerated into analog sensory output for our use and appreciation. In 2005, this planetary communication of information is occurring at a truly mind-numbing rate, estimates of which are on the order of 80 Tera-bits/sec (1012) of data transfer across the globe in 2005 solely in wired and wireless voice and data transmission, 24 hours a day, 7 days a week, and growing exponentially. The world is quite literally abuzz with information flow — communication.* It is for the birth of the Communications Revolution that we humans likely will be remembered for 1000 years hence. Given that this revolution is happening during the working careers of most of us, I find it a wonderful time to be alive, a fact of which I remind my students often. Here is my point. No matter how one slices it, at the most fundamental level, it is semiconductor devices that are powering this communications revolution. Skeptical? Imagine for a moment that one could flip a switch and instantly remove all of the integrated circuits (ICs) from planet Earth. A moment’s reflection will convince you that there is not a single field of human endeavor that would not come to a grinding halt, be it commerce, or agriculture, or education, or medicine, or entertainment. Life as we in the first world know it in 2005 would simply cease to exist. And yet, remarkably, the same result would not have been true 50 years ago; even 20 years ago. Given the fact that we humans have been on planet Earth in our present form for at least 1 million years, and within communities

*I have often joked with my students that it would be truly entertaining if the human retina was sensitive to longer wavelengths of electromagnetic radiation, such that we could ‘‘see’’ all the wireless communications signals constantly bathing the planet (say, in greens and blues!). It might change our feelings regarding our ubiquitous cell phones!

1.1-3 © 2006 by Taylor & Francis Group, LLC

1.1-4

The Silicon Heterostructure Handbook

having entrenched cultural traditions for at least 15,000 years, this is truly a remarkable fact of history. A unique juncture indeed. Okay, hold on tight. It is an easy case to make that the semiconductor silicon (Si) has single-handedly enabled this communications revolution.** I have previously extolled at length the remarkable virtues of this rather unglamorous looking silver-grey element [1], and I will not repeat that discussion here, but suffice it to say that Si represents an extremely unique material system that has, almost on its own, enabled the conception and evolving execution of this communications revolution. The most compelling attribute, by far, of Si lies in the economy-of-scale it facilitates, culminating in the modern IC fabrication facility, effectively enabling the production of gazillions of low-cost, very highly integrated, remarkably powerful ICs, each containing millions of transistors; ICs that can then be affordably placed into widgets of remarkably varied form and function.y So what does this have to do with the book you hold in your hands? To feed the emerging infrastructure required to support this communications revolution, IC designers must work tirelessly to support increasingly higher data rates, at increasingly higher carrier frequencies, all in the design space of decreasing form factor, exponentially increasing functionality, and at ever-decreasing cost. And by the way, the world is going portable and wireless, using the same old wimpy batteries. Clearly, satisfying the near-insatiable appetite of the requisite communications infrastructure is no small task. Think of it as job security! For long-term success, this quest for more powerful ICs must be conducted within the confines of conventional Si IC fabrication, so that the massive economy-of-scale of the global Si IC industry can be brought to bear. Therein lies the fundamental motivation for the field of Si heterostructures, and thus this book. Can one use clever nanoscale engineering techniques to custom-tailor the energy bandgap of fairly conventional Si-based transistors to: (a) improve their performance dramatically and thereby ease the circuit and system design constraints facing IC designers, while (b) performing this feat without throwing away all the compelling economy-of-scale virtues of Si manufacturing? The answer to this important question is a resounding ‘‘YES!’’ That said, getting there took time, vision, as well as dedication and hard work of literally thousands of scientists and engineers across the globe. In the electronics domain, the fruit of that global effort is silicon–germanium heterojunction bipolar transistor (SiGe HBT) bipolar complementary metal oxide semiconductor (BiCMOS) technology, and is in commercial manufacturing worldwide and is rapidly finding a number of important circuit and system applications. In 2004, the SiGe ICs, by themselves, are expected to generate US$1 billion in revenue globally, with perhaps US$30 billion in downstream products. This US$1 billion figure is projected to rise to US$2.09 billion by 2006 [2], representing a growth rate of roughly 42% per year, a remarkable figure by any economic standard. The biggest single market driver remains the cellular industry, but applications in optical networking, hard disk drives for storage, and automotive collisionavoidance radar systems are expected to represent future high growth areas for SiGe. And yet, in the beginning of 1987, only 18 years ago, there was no such thing as a SiGe HBT. It had not been demonstrated as a viable concept. An amazing fact. In parallel with the highly successful development of SiGe HBT technology, a wide class of ‘‘transport enhanced’’ field effect transistor topologies (e.g., strained Si CMOS) have been developed as a means to boost the performance of the CMOS side of Si IC coin, and such technologies have also recently begun **The lone exception to this bold claim lies in the generation and detection of coherent light, which requires direct bandgap III–V semiconductor devices (e.g., GaAs of InP), and without which long-haul fiber communications systems would not be viable, at least for the moment. y Consider: it has been estimated that in 2005 there are roughly 20,000,000,000,000,000,000 (2 1019) transistors on planet Earth. While this sounds like a large number, let us compare it to some other large numbers: (1) the universe is roughly 4.2 1017sec old (13.7 billion years), (2) there are about 1 1021 stars in the universe, and (3) the universe is about 4 1023 miles across (15 billion light-years)! Given the fact that all 2 1020 of these transistors have been produced since December 23, 1947 (following the invention of the point-contact transistor by Bardeen, Brattain, and Shockley), this is a truly remarkable feat of human ingenuity.

© 2006 by Taylor & Francis Group, LLC

The Big Picture

1.1-5

to enter the marketplace as enhancements to conventional core CMOS technologies. The commercial success enjoyed in the electronics arena has very naturally also spawned successful forays into the optoelectronics and even nanoelectronics fields, with potential for a host of important downstream applications. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of our twenty-first century. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. As I have argued, in the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life of planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay close attention.

1.1.2 Bandgap Engineering in the Silicon Material System As wonderful as Si is from a fabrication viewpoint, from a device or circuit designer’s perspective, it is hardly the ideal semiconductor. The carrier mobility for both electrons and holes in Si is comparatively small compared to their III–V cousins, and the maximum velocity that these carriers can attain under high electric fields is limited to about 1 107 cm/sec under normal conditions, relatively ‘‘slow.’’ Since the speed of a transistor ultimately depends on how fast the carriers can be transported through the device under sustainable operating voltages, Si can thus be regarded as a somewhat ‘‘meager’’ semiconductor. In addition, because Si is an indirect gap semiconductor, light emission is fairly inefficient, making active optical devices such as diode lasers impractical (at least for the present). Many of the III–V compound semiconductors (e.g., GaAs or InP), on the other hand, enjoy far higher mobilities and saturation velocities, and because of their direct gap nature, generally make efficient optical generation and detection devices. In addition, III–V devices, by virtue of the way they are grown, can be compositionally altered for a specific need or application (e.g., to tune the light output of a diode laser to a specific wavelength). This atomic-level custom tailoring of a semiconductor is called bandgap engineering, and yields a large performance advantage for III–V technologies over Si [3]. Unfortunately, these benefits commonly associated with III–V semiconductors pale in comparison to the practical deficiencies associated with making highly integrated, low-cost ICs from these materials. There is no robust thermally grown oxide for GaAs or InP, for instance, and wafers are smaller with much higher defect densities, are more prone to breakage, and are poorer heat conductors (the list could go on). These deficiencies translate into generally lower levels of integration, more difficult fabrication, lower yield, and ultimately higher cost. In truth, of course, III–V materials such as GaAs and InP fill important niche markets today (e.g., GaAs metal semiconductor field effect transistor (MESFETs) and HBTs for cell phone power amplifiers, AlGaAs- or InP-based lasers, efficient long wavelength photodetectors, etc.), and will for the foreseeable future, but III–V semiconductor technologies will never become mainstream in the infrastructure of the communications revolution if Si-based technologies can do the job. While Si ICs are well suited to high-transistor-count, high-volume microprocessors and memory applications, RF, microwave, and even millimeter-wave (mm-wave) electronic circuit applications, which by definition operate at significantly higher frequencies, generally place much more restrictive performance demands on the transistor building blocks. In this regime, the poorer intrinsic speed of Si devices becomes problematic. That is, even if Si ICs are cheap, they must deliver the required device and circuit performance to produce a competitive system at a given frequency. If not, the higher-priced but faster III–V technologies will dominate (as they indeed have until very recently in the RF and microwave markets). The fundamental question then becomes simple and eminently practical: is it possible to improve the performance of Si transistors enough to be competitive with III–V devices for high-performance applications, while preserving the enormous yield, cost, and manufacturing advantages associated with conventional Si fabrication? The answer is clearly ‘‘yes,’’ and this book addresses the many nuances

© 2006 by Taylor & Francis Group, LLC

1.1-6

The Silicon Heterostructure Handbook

associated with using SiGe and Si-strained layer epitaxy to practice bandgap engineering in the Si material system, a process culminating in, among other things, the SiGe HBT and strained Si CMOS, as well as a variety of other interesting electronic and optoelectronic devices built from these materials. This totality can be termed the ‘‘Si heterostructures’’ field.

1.1.3 Terminology and Definitions A few notes on modern usage and pronunciation in this field are in order (really!). It is technically correct to refer to silicon–germanium alloys according to their chemical composition, Si1xGex , where x is the Ge mole fraction. Following standard usage, such alloys are generally referred to as ‘‘SiGe’’ alloys. Note, however, that it is common in the material science community to also refer to such materials as ‘‘Ge:Si’’ alloys. A SiGe film that is carbon doped (e.g., less than 0.20% C) in an attempt to suppress subsequent boron out-diffusion (e.g., in HBTs) is properly referred to as a SiGe:C alloy, or simply SiGeC (pronounced ‘‘silicon germanium carbon,’’ not ‘‘silicon germanium carbide’’). This class of SiGe alloys should be viewed as optimized SiGe alloys, and are distinct from SiGe films with a much higher C content (e.g., 2% to 3% C) that might be used, for instance, to lattice-match SiGeC alloys to Si. Believe it or not, this field also has its own set of slang pronunciations. The colloquial usage of the pronunciation \’sig-ee\ to refer to ‘‘silicon–germanium’’ (begun at IBM in the late 1990s) has come into vogue (heck, it may make it to the dictionary soon!), and has even entered the mainstream IC engineers’s slang; pervasively.z In the electronics domain, it is important to be able to distinguish between the various SiGe technologies as they evolve, both for CMOS (strained Si) and bipolar (SiGe HBT). Relevant questions in this context include: Is company X’s SiGe technology more advanced than company Y’s SiGe technology? For physical as well as historical reasons, one almost universally defines CMOS technology (Si, strained Si, or SiGe), a lateral transport device, by the drawn lithographic gate length (the CMOS technology ‘‘node’’), regardless of the resultant intrinsic device performance. Thus, a ‘‘90-nm’’ CMOS node has a drawn gate length of roughly 90 nm. For bipolar devices (i.e., the SiGe HBT), however, this is not so straightforward, since it is a vertical transport device whose speed is not nearly as closely linked to lithographic dimensions. In the case of the SiGe HBT it is useful to distinguish between different technology generations according to their resultant ac performance (e.g., peak common-emitter, unity gain cutoff frequency (fT), which is (a) easily measured and unambiguously compared technology to technology, and yet is (b) a very strong function of the transistor vertical doping and Ge profile and hence nicely reflects the degree of sophistication in device structural design, overall thermal cycle, epi growth, etc.) [1]. The peak fT generally nicely reflects the ‘‘aggressiveness,’’ if you will, of the transistor scaling which has been applied to a given SiGe technology. A higher level of comparative sophistication can be attained by also invoking the maximum oscillation frequency ( fmax), a parameter which is well correlated to both intrinsic profile and device parasitics, and hence a bit higher on the ladder of device performance metrics, and thus more representative of actual large-scale circuit performance. The difficulty in this case is that fmax is far more ambiguous than fT , in the sense that it can be inferred from various gain definitions (e.g., U vs. MAG), and in practice power gain data are often far less ideal in its behavior over frequency, more sensitive to accurate deembedding, and ripe with extraction ‘‘issues.’’ We thus term a SiGe technology having a SiGe HBT with a peak fT in the range of 50 GHz as ‘‘first generation;’’ that with a peak fT in the range of 100 GHz as ‘‘second generation;’’ that with a peak fT in the range of 200 GHz as ‘‘third generation;’’ and that with a peak fT in the range of 300 GHz as ‘‘fourth generation.’’ These are loose definitions to be sure, but nonetheless useful for comparison purposes.

z

I remain a stalwart holdout against this snowballing trend and stubbornly cling to the longer but far more satisfying ‘‘silicon–germanium.’’

© 2006 by Taylor & Francis Group, LLC

1.1-7

The Big Picture

SiGe HBT BiCMOS technology evolution by generation

CMOS gate length

90 nm

4th

3rd

0.12 µm

0.18 µm

2nd

0.25 µm

1st 50 GHz

100 GHz

200 GHz

300 GHz

SiGe HBT peak cutoff frequency FIGURE 1.1.1 Evolution of SiGe HBT BiCMOS technology generations, as measured by the peak cutoff frequency of the SiGe HBT, and the CMOS gate length.

A complicating factor in SiGe technology terminology results from the fact that most, if not all, commercial SiGe HBT technologies today also contain standard Si CMOS devices (i.e., SiGe HBT BiCMOS technology) to realize high levels of integration and functionality on a single die (e.g., singlechip radios complete with RF front-end, data converters, and DSP). One can then speak of a given generation of SiGe HBT BiCMOS technology as the most appropriate intersection of both the SiGe HBT peak fT and the CMOS technology node (Figure 1.1.1). For example, for several commercially important SiGe HBT technologies available via foundry services, we have: . . . . . .

IBM SiGe 5HP — 50 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) IBM SiGe 7HP — 120 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IBM SiGe 8HP — 200 GHz peak fT SiGe HBT þ 0.13 mm Si CMOS (third generation) Jazz SiGe 60 — 60 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) Jazz SiGe 120 — 150 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IHP SiGe SGC25B — 120 GHz peak fT SiGe HBT þ 0.25 mm Si CMOS (second generation)

All SiGe HBT BiCMOS technologies can thus be roughly classified in this manner. It should also be understood that multiple transistor design points typically exist in such BiCMOS technologies (multiple breakdown voltages for the SiGe HBT and multiple threshold or breakdown voltages for the CMOS), and hence the reference to a given technology generation implicitly refers to the most aggressively scaled device within that specific technology platform.

1.1.4 The Application Space It goes without saying in our field of semiconductor IC technology that no matter how clever or cool a new idea appears at first glance, its long-term impact will ultimately be judged by its marketplace ‘‘legs’’ (sad, but true). That is, was the idea good for a few journal papers and an award or two, or did someone actually build something and sell some useful derivative products from it? The sad reality is that the semiconductor field (and we are by no means exceptional) is rife with examples of cool new devices that

© 2006 by Taylor & Francis Group, LLC

1.1-8

The Silicon Heterostructure Handbook

never made it past the pages of the IEDM digest! The ultimate test, then, is one of stamina. And sweat. Did the idea make it out of the research laboratory and into the hands of the manufacturing lines? Did it pass the qualification-checkered flag, have design kits built around it, and get delivered to real circuit designers who built ICs, fabricated them, and tested them? Ultimately, were the derivative ICs inserted into real systems — widgets — to garner leverage in this or that system metric, and hence make the products more appealing in the marketplace? Given the extremely wide scope of the semiconductor infrastructure fueling the communications revolution, and the sheer volume of widget possibilities, electronic to photonic to optoelectronic, it is useful here to briefly explore the intended application space of Si heterostructure technologies as we peer out into the future. Clearly I possess no crystal ball, but nevertheless some interesting and likely lasting themes are beginning to emerge from the fog. SiGe HBT BiCMOS is the obvious ground-breaker of the Si heterostructures application space in terms of moving the ideas of our field into viable products for the marketplace. The field is young, but the signs are very encouraging. As can be seen in Figure 1.1.2, there are at present count 25 þ SiGe HBT industrial fabrication facilities on line in 2005 around the world, and growing steadily. This trend points to an obvious recognition that SiGe technology will play an important role in the emerging electronics infrastructure of the twenty-first century. Indeed, as I often point out, the fact that virtually every major player in the communications electronics field either: (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers, is a remarkable fact, and very encouraging in the grand scheme of things. As indicated above, projections put SiGe ICs at a US$2.0 billion level by 2006, small by percentage perhaps compared to the near trillion dollar global electronics market, but growing rapidly. The intended application target? That obviously depends on the company, but the simple answer is, gulp, a little bit of everything! As depicted in Figure 1.1.3 and Figure 1.1.4, the global communications landscape is exceptionally diverse, ranging from low-frequency wireless (2.4 GHz cellular) to the fastest high-speed wireline systems (10 and 40 Gbit/sec synchronous optical network (SONET)). Core CMOS technologies are increasingly being pushed into the lower frequency wireless space, but the compelling drive to higher carrier frequencies over time will increasingly favor SiGe technologies. At present, SiGe ICs are making inroads into: the cellular industry for handsets [global system for mobile communications — GSM, code division multiple access (CDMA), wideband CDMA (W-CDMA), etc.], even for power amplifiers; various wireless local area networks (WLAN) building blocks, from components to fully integrated systems ranging from 2.4 to 60 GHz and up; ultrawide band (UWB) components; global positioning systems (GPS); wireless base stations; a variety of wireline networking products, from 2.5 to 40 Gbit/sec (and higher); data converters (D/A and A/D); highspeed memories; a variety of instrumentation electronics; read-channel memory storage products; core analog functions (op amps, etc.); high-speed digital circuits of various flavors; radiation detector

Industrial fabrication facilities

25 20

SiGe HBT BiCMOS Strained–Si CMOS

15 10 5 0 1993

1995

1997

1999 Year

2001

2003

FIGURE 1.1.2 Number of industrial SiGe and strained Si fabrication facilities.

© 2006 by Taylor & Francis Group, LLC

2005

1.1-9

The Big Picture

FIGURE 1.1.3 The global communications landscape, broken down by the various communications standards, and spanning the range of: wireless to wireline; fixed to mobile; copper to fiber; low data rate to broadband; and local area to wide area networks. WAN is wide area network, MAN is metropolitan area network, the so-called ‘‘last mile’’ access network, LAN is local area network, and PAN is personal area network, the emerging in-home network. (Used with the permission of Kyutae Lim.) Some application bands for SiGe ICs Defense Radar

Radar Navigation

GPS

Radar Automotive Collision avoidance

Polling

Cellular / PCS / Satellite / UWB

Communications WLAN

Bands: L 1

2

S

C

3

5

W

Ka

X

Ku

10

20 30

ISM

50

100

Frequency (GHz)

FIGURE 1.1.4 Some application frequency bands for SiGe integrated circuits.

electronics; radar systems (from 3 to 77 GHz and up); a variety space-based electronics components; and various niche extreme environment components (e.g., cryogenic (77 K) hybrid superconductor–semiconductor systems). The list is long and exceptionally varied — this is encouraging. Clearly, however, some of these components of ‘‘everything’’ are more important than others, and this will take time to shake out. The strength of the BiCMOS twist to SiGe ICs cannot be overemphasized. Having both the high-speed SiGe HBT together on-chip with aggressively scaled CMOS allows one great flexibility in system design, the depths of which is just beginning to be plumbed. While debates still rage with respect to the most cost-effective partitioning at the chip and package level (system-on-a-chip versus system-in-a-package,

© 2006 by Taylor & Francis Group, LLC

1.1-10

The Silicon Heterostructure Handbook

etc.), clearly increased integration is viewed as a good thing in most camps (it is just a question of how much), and SiGe HBT BiCMOS is well positioned to address such needs across a broad market sector. The envisioned high-growth areas for SiGe ICs over the new few years include: the cellular industry, optical networking, disk drives, and radar systems. In addition, potential high-payoff market areas span the emerging mm-wave space (e.g., the 60 GHz ISM band WLAN) for short range, but very high data rate (Gbit/sec) wireless systems. A SiGe 60 GHz single-chip/package transceiver (see Figure 1.1.5 for IBM’s vision of such a beast) could prove to be the ‘‘killer app’’ for the emerging broadband multimedia market. Laughable? No. The building blocks for such systems have already been demonstrated using third-generation SiGe technology [4], and fully integrated transceivers are under development. The rest of the potential market opportunities within the Si heterostructures field can be leveraged by successes in the SiGe IC field, both directly and indirectly. On the strained Si CMOS front, there are existent proofs now that strained Si is likely to become a mainstream component of conventional CMOS scaling at the 90-nm node and beyond (witness the early success of Intel’s 90-nm logic technology built around uniaxially strained Si CMOS; other companies are close behind). Strained Si would seem to represent yet another clever technology twist that CMOS device technologists are pulling from their bag of tricks to keep the industry on a Moore’s law growth path. This was not an obvious development (to me anyway) even a couple of years back. A wide variety of ‘‘transport enhanced’’ Si-heterostructure-based FETs have been demonstrated (SiGe-channel FETs, Si-based high electron mobility transistors (HEMTs), as well as both uniaxially and biaxially strained FETs, etc). Most of these devices, however, require complex substrate engineering that would have seemed to preclude giga-scale integration level needs for microprocessor-level integration. Apparently not so. The notion of using Si heterostructures (either

Radiation

Vision of a 60 GHz SiGe wireless transceiver Package mold

Wirebond pad

Wirebond C4-Balls

Tx/Rx flip-Antenna

Mix

Filter structure

Q-signal

90 VCO I-signal

Underfill

Su

bs

tra

te

Mix Mix Q-signal LNA

I/Q

90 VCO I-signal

PLL

Mix

I/Q

QFN-package Package pin

FIGURE 1.1.5 Vision for a single-chip SiGe mm-wave transceiver system. (Used with the permission of Ullrich Pfeiffer.)

© 2006 by Taylor & Francis Group, LLC

1.1-11

The Big Picture

uniaxial or biaxial strain or both) to boost conventional CMOS performance appears to be an appealing path for the future, a natural merging point I suspect for SiGe strained layers found in SiGe HBT BiCMOS (which to date contains only conventional Si CMOS) and strained Si CMOS. From the optoelectronics camp, things are clearly far less evolved, but no less interesting. A number of functional optoelectronic devices have been demonstrated in research laboratories. Near-term successes in the short wavelength detector arena and light emitting diodes (LEDs) are beginning to be realized. The achievement of successful coherent light emission in the Si heterostructure system (e.g., via quantum cascade techniques perhaps) would appear to be the ‘‘killer app’’ in this arena, and research in this area is in progress. More work is needed.

1.1.5 Performance Limits and Future Directions We begin with device performance limits. Just how fast will SiGe HBTs be 5 years from now? Transistorlevel performance in SiGe HBTs continues to rise at a truly dizzying pace, and each major conference seems to bear witness to a new performance record (Figure 1.1.6). Both first- and second-generation SiGe HBT BiCMOS technology is widely available in 2005 (who would have thought even 3 years ago that fully integrated 100þ GHz Si-based devices would be ‘‘routine’’ on 200 mm wafers?), and even at the 200 GHz (third-generation) performance level, six companies (at last count) have achieved initial technology demonstrations, including IBM (Chapter 3.5), Jazz (Chapter 3.6), IHP (Chapter 3.9), ST Microelectronics (Chapter 3.10), Hitachi (Chapter 3.7), and Infineon (Chapter 3.8). Several are now either available in manufacturing, or are very close (e.g., [5]). At press time, the most impressive new stake-in-the-ground is the report (June 2004) of the newly optimized ‘‘SiGe 9T’’ technology, which simultaneously achieves 302 GHz peak fT and 306 GHz peak fmax, a clear record for any Si-based transistor, from IBM (Figure 1.1.7) [6]. This level of ac performance was achieved at a BVCEO of 1.6 V, a BVCBO of 5.5 V, and a current gain of 660. Noise measurements on these devices yielded NFmin/Gassoc of 0.45 dB/14 dB and 1.4 dB/8 dB at 10 and 25 GHz, respectively. Measurements of earlier (unoptimized) fourth-generation IBM SiGe HBTs have yielded record values of 375 GHz peak fT [7] at 300 K and above 500 GHz peak fT at 85 K. Simulations suggest that THz-level (1000 GHz) intrinsic transistor performance is not a laughable proposition in SiGe HBTs (Chapter 4.14). This fact still amazes even me, the eternal optimist of SiGe performance! I, for one, firmly believe that we will see SiGe HBTs

400 4th

Cutoff frequency (GHz)

350 300 250 3rd 200 150

2nd

100 50 0 0.1

1st

1.0 10 Collector current density (mA/mm2)

100

FIGURE 1.1.6 Measured cutoff frequency as a function of bias current density for four different SiGe HBT technology generations.

© 2006 by Taylor & Francis Group, LLC

1.1-12

The Silicon Heterostructure Handbook

400 f T + f max = 400 GHz

Peak f max (GHz)

350

600 GHz f T = f max

300 250 200 GHz

200 150 100

SiGe+SiGe: C HBT 300 K

50 0

0

50

100

150

200

250

300

350

400

Peak f T (GHz)

FIGURE 1.1.7 Measured maximum oscillation frequency versus cutoff frequency for a variety of generations of SiGe HBT BiCMOS technology shown in Figure 1.1.1.

above-500 GHz peak fT and fmax fully integrated with nanometer-scale (90 nm and below) Si CMOS (possibly strained Si CMOS) within the next 3 to 5 years. One might logically ask, particularly within the confines of the above discussion on ultimate market relevance, why one would even attempt to build 500 GHz SiGe HBTs, other than to win a best-paper award, or to trumpet that ‘‘because-it’s-there’’ Mount Everest mentality we engineers and scientists love so dearly. This said, if the future ‘‘killer app’’ turns out to be single-chip mm-wave transceiver systems with on-board DSP for broadband multimedia, radar, etc., then the ability of highly scaled, highly integrated, very high performance SiGe HBTs to dramatically enlarge the circuit/system design space of the requisite mm-wave building blocks may well prove to be a fruitful (and marketable) path. Other interesting themes are emerging in the SiGe HBT BiCMOS technology space. One is the very recent emergence of complementary SiGe (C-SiGe) HBT processes (npn þ pnp SiGe HBTs). While very early pnp SiGe HBT prototypes were demonstrated in the early 1990s, only in the last 2 years or so have fully complementary SiGe processes been developed, the most mature of which to date is the IHP SGC25C process, which has 200 GHz npn SiGe HBTs and 80 GHz pnp SiGe HBTs (Chapter 3.9). Having very high-speed pnp SiGe HBTs on-board presents a fascinating array of design opportunities aimed particularly at the analog/mixed-signal circuit space. In fact, an additional emerging trend in the SiGe field, particularly for companies with historical pure analog circuit roots, is to target lower peak fT , but higher breakdown voltages, while simultaneously optimizing the device for core analog applications (e.g., op amps, line drivers, data converters, etc.), designs which might, for instance, target better noise performance, and higher current gain-Early voltage product than mainstream SiGe technologies. One might even choose to park that SiGe HBT platform on top of thick film SOI for better isolation properties (Chapter 3.11). Another interesting option is the migration of high-speed vertical SiGe HBTs with very thin film CMOS-compatible SOI (Chapter 3.3). This technology path would clearly favor the eventual integration of SiGe HBTs with strained Si CMOS, all on SOI, a seemingly natural migratory path. If one accepts the tenet that integration is a good thing from a system-level perspective, the Holy Grail in the Si heterostructure field would, in the end, appear to be the integration of SiGe HBTs for RF through mm-wave circuitry (e.g., single-chip mm-wave transceivers complete with on-chip antennae), strained Si CMOS for all DSP and memory functionality, both perhaps on SOI, Si-based light emitters, SiGe HBT modulator electronics, and detectors for such light sources, together with on-chip waveguides to steer the light, realized all on one Si wafer to produce a ‘‘Si-based optoelectronic superchip’’ [8], that could do-it-all. These diverse blocks would be optional plug-in modules around a core SiGe

© 2006 by Taylor & Francis Group, LLC

The Big Picture

1.1-13

HBT þ strained Si CMOS IC technology platform, perhaps with flip-chip (or other) packaging techniques to join different sub-die to the main superchip (e.g., for a Si-based detector or laser). I know, I know. It is not obvious that even if each of these blocks could be realized, that it would make economic sense to do so for real systems. I have no quarrel with that. I think such a Si-based superchip is a useful paradigm, however, to bind together all of the clever objects we wish to ultimately build with Si heterostructures, from electronic to photonic, and maintain the vision of the one overarching constraint that guides us as we look forward — keep whatever you do compatible with high-volume manufacturing in Si fabrication facilities if you want to shape the path of the ensuing communications revolution. This Si-based superchip clearly remains a dream at present. A realizable dream? And if realizable, commercially viable? Who knows? Only time will tell. But it is fun to think about. As you peruse this book you hold in your hands, which spans the whole Si heterostructure research and development space, from materials, to devices, to circuit and system applications, I think you will be amazed at both the vision, cleverness, and smashing successes of the many scientists and engineers who make up our field. Do not count us out! We are the new architects of an oh-so-very-interesting future.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. ‘‘SiGe devices market to hit $2 billion in 2006,’’ article featured on CompoundSemicoductor.net, http://compoundsemiconductor.net/articles/news/8/3/22/1 3. F Capasso. Band-gap engineering: from physics and materials to new semiconductor devices. Science 235:172–176, 1987. 4. S Reynolds, B Floyd, U Pfeiffer, and T. Zwick. 60 GHz transciever circuits in SiGe bipolar technology. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp 442–443. 5. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp 180–182. 6. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeter-wave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp 395–398. 7. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cutoff frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp 771–774. 8. R Soref. Silicon-based photonic devices. Technical Digest of the IEEE International Solid-State Circuits Conference, 1995, pp 66–67.

© 2006 by Taylor & Francis Group, LLC

1.2 A Brief History of the Field John D. Cressler Georgia Institute of Technology

1.2.1 1.2.2 1.2.3

Si–SiGe Strained Layer Epitaxy.................................. 1.2-15 SiGe HBTs .................................................................... 1.2-17 SiGe–Strained Si FETs and Other SiGe Devices ....... 1.2-20

In the historical record of any field of human endeavor, being ‘‘first’’ is everything. It is often said that ‘‘hindsight is 20–20,’’ and it is tempting in many cases to ascribe this or that pivotal event as ‘‘obvious’’ or ‘‘easy’’ once the answer is known. Anyone intimately involved in a creative enterprise knows, however, that it is never easy being first, and often requires more than a little luck and maneuvering. Thus the triumphs of human creativity, the ‘‘firsts,’’ should be appropriately celebrated. Still, later chroniclers often gloss over, and then eventually ignore, important (and sometimes very interesting) twists and turns, starts and stops, of the winners as well as the second and third place finishers, who in the end may in fact have influenced the paths of the winners, sometimes dramatically. The history of our field, for instance, is replete with interesting competitive battles, unusual personalities and egos, no small amount of luck, and various other fascinating historical nuances. There is no concise history of our field available, and while the present chapter is not intended to be either exhaustive or definitive, it represents my firm conviction that the history of any field is both instructive and important for those who follow in the footsteps of the pioneers. Hopefully this brief history does not contain too many oversights or errors, and is offered as a step in the right direction for a history of pivotal events that helped shape the Si heterostructures field.

1.2.1 Si–SiGe Strained Layer Epitaxy The field of Si-based heterostructures solidly rests on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor ‘‘black arts’’ associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. What may seem routine today was not always so. The Si heterostructure story necessarily begins with materials, and circuit designers would do well to remember that much of what they take for granted in transistor performance owes a great debt to the smelters of the crystalline world. Table 1.2.1 summarizes the key steps in the development of SiGe–Si strained layer epitaxy. Given that Ge was the earliest and predominant semiconductor pursued by the Bell Laboratories transistor team, with a focus on the more difficult to purify Si to come slightly later, it is perhaps not surprising that the first study of SiGe alloys, albeit unstrained bulk alloys, occurred as early as 1958 [1]. It was recognized around 1960 [2] that semiconductor epitaxy* would enable more robust and controllable transistor fabrication. Once the move to Si-based processing occurred, the field of Si epitaxy was

*The word ‘‘epitaxy’’ (or just ‘‘epi’’) is derived from the Greek word epi, meaning ‘‘upon’’ or ‘‘over.’’

1.2-15 © 2006 by Taylor & Francis Group, LLC

1.2-16

The Silicon Heterostructure Handbook TABLE 1.2.1

Milestones in the Development of SiGe–Si Strained Layer Epitaxy

Historical Event

Year

Ref.

First investigation of the bandgap of unstrained SiGe alloys First epitaxially grown layer to be used in a transistor First investigation of high-temperature Si epitaxy Concept of critical thickness for epitaxial strained layers Energy minimization approach for critical thickness Force-balance approach for critical thickness First growth of SiGe strained layers First growth of SiGe epitaxy by MBE First stability calculations of SiGe strained layers First measurements of energy bandgap in SiGe strained layers First growth of Si epitaxy by LRP-CVD First 2D electron gas in the SiGe system First growth of Si epitaxy by UHV/CVD First measurements of band alignments in SiGe–Si First growth of SiGe epitaxy by UHV/CVD First step-graded relaxed SiGe substrate First growth of SiGe epitaxy by LRP-CVD First growth of Si epitaxy by AP-CVD First 2D hole gas in the SiGe system First growth of SiGe epitaxy by AP-CVD First majority hole mobility measurements in SiGe First minority electron mobility measurements in SiGe First growth of lattice-matched SiGeC alloys First growth of SiGe layers with carbon doping First stability calculations to include a Si cap layer

1958 1960 1963 1963 1963 1974 1975 1984 1985 1985 1985 1985 1986 1986 1988 1988 1989 1989 1989 1991 1991 1992 1992 1994 2000

[1] [2] [3] [4] [5] [6] [7] [8] [9] [10,11] [12] [13] [14] [15] [16] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]

launched, the first serious investigation of which was reported in 1963 [3]. Early Si epitaxy was exclusively conducted under high-temperature processing conditions, in the range of 11008C, a temperature required to obtain a chemically pure and pristine growth interface on the Si host substrate for the soon-to-be-grown crystalline Si epi. High-temperature Si epi has been routinely used in basically this same form for over 40 years now, and represents a mature fabrication technique that is still widely practiced for many types of Si devices (e.g., high-speed bipolar transistors and various power devices). Device engineers have long recognized the benefits of marrying the many virtues of Si as a host material for manufacturing electronic devices, with the bandgap engineering principles routinely practiced in the III–V system. Ultimately this requires a means by which one can perform epitaxial deposition of thin Si layers on large Si substrates, for both p- and n-type doping of arbitrary abruptness, with very high precision, across large wafers, and doping control at high dynamic range. Only a moment’s reflection is required to appreciate that this means the deposition of the Si epi must occur at very low growth temperatures, say 5008C to 6008C (not ‘‘low’’ per se, but low compared to the requisite temperatures needed for solid-state diffusion of dopants in Si). Such a low-temperature Si epi would then facilitate the effective marriage of Si and Ge, two chemically compatible elements with differing bandgaps, and enable the doping of such layers with high precision, just what is needed for device realizations. Clearly the key to Si-based bandgap engineering, Si-heterostructures, our field, is the realization of device quality, low-temperature Si epi (and hence SiGe epi), grown pseudomorphically** on large Si host substrates. Conquering this task proved to be remarkably elusive and time consuming. In the III–V semiconductor world, where very low processing temperatures are much easier to attain, and hence more common than for Si, the deposition of multiple semiconductors on top of one another proved quite feasible (e.g., GaAs on InP), as needed to practice bandgap engineering, for instance, **The word ‘‘pseudo’’ is derived from the Greek word pseude¯s, meaning ‘‘false,’’ and the word ‘‘morphic’’ is derived from the Greek word morphe¯, meaning ‘‘form.’’ Hence, pseudomorphic literally means false-form.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-17

resulting in complex material composites having differing lattice constants in intimate physical contact. To accommodate the differing lattice constants while maintaining the crystallinity of the underlying films, strain is necessarily induced in the composite film, and the notion of a film ‘‘critical thickness,’’ beyond which strain relaxation occurs via fundamental thermodynamic driving forces, was defined as early as 1963 [4], as were the energy minimization techniques needed for calculating such critical thicknesses [5]. Alternative ‘‘force-balance’’ techniques for addressing the so-called stability issues in strained layer epitaxy came from the III–V world in 1974, and were applied to SiGe strained layer epitaxy in 1985 [9]. Interestingly, however, research continues today on stability in complicated (e.g., compositionally graded) SiGe films, and only very recently have reasonably complete theories been offered which seem to match well with experiment [25]. The first reported growth of SiGe strained layers was in 1975 in Germany [7], but the field did not begin to seriously heat up until the early 1980s, when several teams pioneered the application of molecular beam epitaxy (MBE) to facilitate materials studies of device-quality strained SiGe on Si in 1984 [8]. Optical studies on these films resulted in encouraging findings concerning the beneficial effects of strain on the band-edge properties of SiGe [10, 11], paving the way for serious contemplation of devices built from such materials. Parallel paths toward other low-temperature Si epi growth techniques centered on the ubiquitous chemical vapor deposition (CVD) approach were simultaneously pursued, culminating in the so-called limited-reaction-processing CVD (LRP-CVD) technique (Si epi in 1985 [12], and SiGe epi in 1989 [17]), the ultrahigh-vacuum CVD (UHV/CVD) technique (Si epi in 1986 [14] and SiGe epi in 1988 [16]), and various atmospheric pressure CVD (AP-CVD) techniques (e.g., Si epi in 1989 [18], and SiGe epi in 1991 [20]). These latter two techniques, in particular, survive to this day, and are widely used in the SiGe heterojunction bipolar transistor (HBT) industry. Device-quality SiGe–Si films enabled a host of important discoveries to occur, which have important bearing on device derivatives, including the demonstration of both two-dimensional electron and hole gases [13, 19], and the fortuitous observation that step-graded SiGe buffer layers could be used to produce device-quality strained Si on SiGe, with its consequent conduction band offsets [16]. This latter discovery proved important in the development of SiGe–Si heterostructure-based FETs. Both majority and minority carrier mobility measurements occurred in the early 1990s [21, 22], although reliable data, particularly involving minority carriers, remain sparse in the literature. Also in the early 1990s, experiments using high C content as a means to relieve strain in SiGe and potentially broaden the bandgap engineering space by lattice-matching SiGe:C materials to Si substrates (a path that has to date not borne much fruit, unfortunately), while others began studying efficacy of C-doping of SiGe, a result that ultimately culminated in the wide use today of C-doping for dopant diffusion suppression in SiGe:C HBTs [23, 24]. The Si–SiGe materials field continues to evolve. Commercial single wafer (AP-CVD) and batch wafer (UHV/CVD) Si–SiGe epi growth tools compatible with 200 mm (and soon 300 mm) Si wafers exist in literally dozens of industrial fabrication facilities around the world, and SiGe growth can almost be considered routine today in the ease in which it can be integrated into CMOS-compatible fabrication processes. It was clearly of paramount importance in the ultimate success of our field that some of the ‘‘black magic’’ associated with robust SiGe film growth be removed, and this, thankfully, is the case in 2005.

1.2.2 SiGe HBTs Transistor action was first demonstrated by Bardeen and Brattain in late December of 1947 using a point contact device [26]. Given all that has transpired since, culminating in the Communications Revolution, which defines our modern world (refer to the discussion in Chapter 1.1), this pivotal event surely ranks as one of the most significant in the course of human history — bold words, but nevertheless true. This demonstration of a solid-state device exhibiting the key property of amplification (power gain) is also unique in the historical record for the precision with which we can locate it in time — December 23,

© 2006 by Taylor & Francis Group, LLC

1.2-18

The Silicon Heterostructure Handbook

1947, at about 5 p.m. Not to be outdone, Shockley rapidly developed a theoretical basis for explaining how this clever object worked, and went on to demonstrate the first true bipolar junction transistor (BJT) in 1951 [27]. The first BJT was made, ironically in the present context, from Ge. The first silicon BJT was made by Teal in 1954 using grown junction techniques. The first diffused silicon BJT was demonstrated in 1956 [28], and the first epitaxially grown silicon BJT was reported in 1960, see Ref. [2]. The concept of the HBT is surprisingly an old one, dating in fact to the fundamental BJT patents filed by Shockley in 1948 [29]. Given that the first bipolar transistor was built from Ge, and III–V semiconductors were not yet on the scene, it seems clear that Shockley envisioned the combination of Si (wide bandgap emitter) and Ge (narrow bandgap base) to form a SiGe HBT. The basic formulation and operational theory of the HBT, for both the traditional wide bandgap emitter plus narrow bandgap base approach found in most III–V HBTs, as well as the drift-base (graded) approach used in SiGe HBTs today, was pioneered by Kroemer, and was largely in place by 1957 [30–32]. It is ironic that Kroemer in fact worked hard early on to realize a SiGe HBT, without success, ultimately pushing him toward the III–V material systems for his heterostructure studies, a path that proved in the end to be quite fruitful for him, since he shared the Nobel Prize in physics in 2000 for his work in (III–V) bandgap engineering for electronic and photonic applications [33]. While III–V HBT (e.g., AlGaAs–GaAs) demonstrations began appearing in the 1970s, driven largely by the needs for active microwave components in the defense industry, reducing the SiGe HBT to practical reality took 30 years after the basic theory was in place due to material growth limitations. As pointed out [34] the semiconductor device field is quite unique in the scope of human history because ‘‘science’’ (theoretical understanding) preceded the ‘‘art’’ (engineering and subsequent technological advancement). Once device-quality SiGe films were finally achieved in the mid-1980s, however, progress was quite rapid. Table 1.2.2 summarizes the key steps in the evolution of SiGe HBTs. The first functional SiGe HBT was demonstrated by an IBM team in December 1987 at the IEDM [35]. The pioneering result showed a SiGe HBT with functional, albeit leaky, dc characteristics; but it was a SiGe HBT, it worked (barely), and it was the first.y It is an often overlooked historical point, however, that at least four independent groups were simultaneously racing to demonstrate the first functional SiGe HBT, all using the MBE growth technique: the IBM team [35], a Japanese team [62], a Bell Laboratories team [63], and a Linko¨ping University team [64]. The IBM team is fairly credited with the victory, since it presented (and published) its results in early December of 1987 at the IEDM (it would have been submitted to the conference for review in the summer 1987) [35]. Even for the published journal articles, the IBM team was the first to submit its paper for review (on November 17, 1987) [65]. All four papers appeared in print in the spring of 1988. Other groups soon followed with more SiGe HBT demonstrations. The first SiGe HBT demonstrated using (the ultimately more manufacturable) CVD growth technique followed shortly thereafter, in 1989, first using LRP-CVD [17], and then with UHV/CVD [36]. Worldwide attention became squarely focused on SiGe technology, however, in June 1990 at the IEEE VLSI Technology Symposium with the demonstration of a non-self-aligned UHV/CVD SiGe HBT with a peak cutoff frequency of 75 GHz [37, 38]. At that time, this SiGe HBT result was roughly twice the performance of state-of-the-art Si BJTs, and clearly demonstrated the future performance potential of the technology (doubling of transistor performance is a rare enough event that it does not escape significant attention!). Eyebrows were raised, and work to develop SiGe HBTs for practical circuit applications began in earnest in a large number of industrial and university laboratories around the world.} The feasibility of implementing pnp SiGe HBTs was also demonstrated in June 1990 [40]. In December 1990, the simplest digital circuit, an emitter-coupled-logic (ECL) ring oscillator, using selfy

An interesting historical perspective of early SiGe HBT development at IBM is contained in Ref. [61]. A variety of zero-Dt, mesa-isolated, III–V-like high-speed SiGe HBTs were reported in the early 1990s (e.g., Ref. [66]), but we focus here on fully integrated, CMOS-compatible SiGe HBT technologies, because they are inherently more manufacturable, and hence they are the only ones left standing today, for obvious reasons. }

© 2006 by Taylor & Francis Group, LLC

1.2-19

A Brief History of the Field TABLE 1.2.2 Milestones in the Development of SiGe HBTs Historical Event

Year

Ref.

First demonstration of transistor action Basic HBT concept First demonstration of a bipolar junction transistor First demonstration of a silicon bipolar transistor Drift-base HBT concept Fundamental HBT theory First epitaxial silicon transistors First SiGe HBT First ideal SiGe HBT grown by CVD First SiGe HBT grown by UHV/CVD First high-performance SiGe HBT First self-aligned SiGe HBT First SiGe HBT ECL ring oscillator First pnp SiGe HBT First operation of SiGe HBTs at cryogenic temperatures First SiGe HBT BiCMOS technology First LSI SiGe HBT integrated circuit First SiGe HBT with peak fT above 100 GHz First SiGe HBT technology in 200-mm manufacturing First SiGe HBT technology optimized for 77 K First radiation tolerance investigation of SiGe HBTs First report of low-frequency noise in SiGe HBTs First SiGe:C HBT First high-power SiGe HBTs First sub-10 psec SiGe HBT ECL circuits First high-performance SiGe:C HBT technology First SiGe HBT with peak fT above 200 GHz First SiGe HBT with peak fT above 300 GHz First complementary (npn þ pnp) SiGe HBT technology First C-SiGe technology with npn and pnp fT above 100 GHz First vertical SiGe HBT on thin film (CMOS compatible) SOI First SiGe HBT with both fT and fmax above 300 GHz

1947 1948 1951 1956 1954 1957 1960 1987 1989 1989 1990 1990 1990 1990 1990 1992 1993 1993 1994 1994 1995 1995 1996 1996 1997 1999 2001 2002 2003 2003 2003 2004

[26] [29] [27] [28] [30] [31, 32] [2] [35] [17] [36] [37, 38] [39] [39] [40] [41] [42] [43] [44, 45] [46] [47] [48] [49] [50] [51, 52] [53] [54] [55] [56] [57] [58] [59] [60]

aligned, fully integrated SiGe HBTs was produced [39]. The first SiGe BiCMOS technology (SiGe HBT þ Si CMOS) was reported in December 1992 [42]. Theoretical predictions of the inherent ability of SiGe HBTs to operate successfully at cryogenic temperatures (in contrast to Si BJTs) were first confirmed in 1990 [41], and SiGe HBT profiles optimized for the liquid nitrogen temperature environment (77 K) were reported in 1994 [48]. The first LSI SiGe HBT circuit (a 1.2 Gsample/sec 12-bit digital-to-analog converter — DAC) was demonstrated in December 1993 [43]. The first SiGe HBTs with frequency response greater than 100 GHz were described in December 1993 by two independent teams [44, 45], and the first SiGe HBT technology entered commercial production on 200-mm wafers in December 1994 [46]. The first report of the effects of ionizing radiation on advanced SiGe HBTs was made in 1995 [48]. Due to the natural tolerance of epitaxial-base bipolar structures to conventional radiation-induced damage mechanisms without any additional radiation-hardening process changes, SiGe HBTs are potentially very important for space-based and planetary communication systems applications, spawning an important new sub-discipline for SiGe technology. The first demonstration that epitaxial SiGe strained layers do not degrade the superior low-frequency noise performance of bipolar transistors occurred in 1995, opening the way for very low-phase noise frequency sources [49]. Carbon-doping of epitaxial SiGe layers as a means to effectively suppress boron out-diffusion during fabrication has rapidly become the preferred approach for commercial SiGe technologies, particularly those above first-generation performance levels. Carbon-doping of SiGe HBTs has its own interesting

© 2006 by Taylor & Francis Group, LLC

1.2-20

The Silicon Heterostructure Handbook

history, dating back to the serendipitous discovery [50] in 1996 that incorporating small amounts of C into a SiGe epi layer strongly retards (by an order of magnitude) the diffusion of the boron (B) base layer during subsequent thermal cycles. Given that maintaining a thin base profile during fabrication is perhaps the most challenging aspect of building a manufacturable SiGe technology, it is somewhat surprising that it took so long for the general adoption of C-doping as a key technology element. I think it is fair to say that most SiGe practitioners at that time viewed C-doping with more than a small amount of skepticism, given that C can act as a deep trap in Si, and C contamination is generally avoided at all costs in Si epi processes, particularly for minority carrier devices such as the HBT. At the time of the discovery of C-doping of SiGe in 1996, most companies were focused on simply bringing up a SiGe process and qualifying it, relegating the potential use of C to the back burner. In fairness, most felt that C-doping was not necessary to achieve first-generation SiGe HBT performance levels. The lone visionary group to solidly embrace C-doping of SiGe HBTs at the onset was the IHP team in Germany, whose pioneering work eventually paid off and began to convince the skeptics of the merits of C-doping. The minimum required C concentration for effective out-diffusion suppression of B was empirically established to be in the vicinity of 0.1% to 0.2% C (i.e., around 1 1020 cm3). Early on, much debate ensued on the physical mechanism of how C impedes the B diffusion process, but general agreement for the most part now exists and is discussed in Chapter 2.9. The first high-performance, fully integrated SiGe:C HBT technology was reported in 1999 [54]. The first ‘‘high-power’’ SiGe HBTs (S band, with multiwatt output power) were reported in 1996 using thick collector doping profiles [51, 52]. The 10-psec ECL circuit performance barrier was broken in 1997 [53]. The 200-GHz peak fT performance barrier was broken in November 2001 for a nonself-aligned device [55], and for a self-aligned device in February 2002 [67]. By 2004, a total of six industrial laboratories had achieved 200 GHz performance levels. A SiGe HBT technology with a peak fT of 350 GHz (375 GHz values were reported in the IEDM presentation) was presented in December 2002 [56], and this 375 GHz fT value remains a record for room temperature operation (it is above 500 GHz at cryogenic temperatures), and an optimized version with both fT and fmax above 300 GHz was achieved in June 2004 [60]. This combined level of 300þ GHz for both fT and fmax remains a solid record for any Si-based semiconductor device. Other recent and interesting developments in the SiGe HBT field include the first report of a complementary (npn þ pnp) SiGe HBT (C-SiGe) technology in 2003 [57], rapidly followed by a C–SiGe technology with fT for both the npn and pnp SiGe HBTs above 100 GHz [58]. In addition, a novel vertical npn SiGe HBT has been implemented in thin-film (120 nm) CMOS-compatible SOI [59]. Besides further transistor performance enhancements, other logical developments to anticipate in this field include the integration of SiGe HBTs with strained-Si CMOS for a true all-Si-heterostructure technology. Not surprisingly, research and development activity involving SiGe HBTs, circuits built from these devices, and various SiGe HBT technologies, in both industry and at universities worldwide, has grown very rapidly since the first demonstration of a functional SiGe HBT in 1987, only 18 years in the past.

1.2.3 SiGe–Strained Si FETs and Other SiGe Devices The basic idea of using an electric field to modify the surface properties of materials, and hence construct a ‘‘field-effect’’ device, is remarkably old (1926 and 1935), predating even the quest for a solid-state amplifier [68]. Given the sweeping dominance of CMOS technology in the grand scheme of the electronics industry today, it is ironic that the practical demonstration of the BJT preceded that of the MOSFET by 9 years. This time lag from idea to realization was largely a matter of dealing with the many perils associated with obtaining decent dielectric materials in the Si system — doubly ironic given that Si has such a huge natural advantage over all other semiconductors in this regard. Bread-and-butter notions of ionic contamination, de-ionized water, fixed oxide charge, surface state passivation, and clean-room techniques in semiconductor fabrication had to be learned the hard way. Once devicequality SiO2 was obtained in the late 1950s, and a robust gate dielectric could thus be fabricated, it was

© 2006 by Taylor & Francis Group, LLC

1.2-21

A Brief History of the Field

not long until the first functional MOSFET was demonstrated in 1960 [69]. The seemingly trivial (remember, however, that hindsight is 20–20!) connection of n-channel and p-channel MOSFETs to form low-power CMOS in 1963 [70] paved the way (eventually) to the high-volume, low-cost, highly integrated microprocessor, and the enormous variety of computational engines that exist today as a result. Like their cousin, the SiGe HBT, SiGe–strained Si FETs did not get off the ground until the means for accomplishing the low-temperature growth of Si epitaxy could be realized. Once that occurred in the mid-1980s the field literally exploded. Table 1.2.3 summarizes the milestones in the evolution of SiGe– strained Si FETs, as well as a veritable menagerie of other electronic and optoelectronic components built from SiGe–strained Si epitaxy. It was discovered as early as 1971 that direct oxidation of SiGe was a bad idea for building gate dielectrics [71]. Given that gate oxide quality, low-temperature deposited oxides, did not exist in the mid-1980s, the earliest FET demonstrations were modulation-doped, Schottky-gated, FETs, and both n-channel and p-channel SiGe MODFETs were pioneered as early as 1986 using MBE-grown material [72, 73]. Before the SiGe MOSFET field got into high gear in the 1990s, a variety of other novel device demonstrations occurred, including: the first SiGe superlattice photodetector [74], the first SiGe Schottky barrier diodes (SBD) in 1988 [75], the first SiGe hole-transport resonant tunneling diode (RTD) in 1988 [76], and the first SiGe bipolar inversion channel FET (BiCFET) in 1989, a now-extinct dinosaur [77]. Meanwhile, early studies using SiGe in conventional CMOS gate stacks to minimize dopant depletion effects and tailor work functions, a fairly common practice in CMOS today, occurred in 1990 [78], and the first SiGe waveguides on Si substrates were produced in 1990 [79]. The first functional SiGe channel pMOSFET was published in 1991, and shortly thereafter, a wide variety of other approaches aimed at obtaining the best SiGe pMOSFETs (see, for instance, Refs. [93–95]). The first electron-transport RTD was demonstrated in 1991 [81], and the first LED in SiGe

TABLE 1.2.3 Milestones in the Development of SiGe–Strained Si FETs and Other Devices Historical Event

Year

Ref.

Field effect device concept First Si MOSFET First Si CMOS First oxidation study of SiGe First SiGe nMODFET First SiGe pMODFET First SiGe photodetector First SiGe SBD First SiGe hole RTD First SiGe BiCFET First SiGe gate CMOS technology First SiGe waveguide First SiGe pMOSFET First SiGe electron RTD First SiGe LED First SiGe solar cell First a-SiGe phototransistor First SiGe pMOSFET on SOI First strained Si pMOSFET First strained Si nMOSFET First SiGe:C pMOSFET First SiGe pFET on SOS First submicron strained Si MOSFET First vertical SiGe pFET First strained Si CMOS technology

1926 1960 1963 1971 1986 1986 1986 1988 1988 1989 1990 1990 1991 1991 1991 1992 1993 1993 1993 1994 1996 1997 1998 1998 2002

[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92]

© 2006 by Taylor & Francis Group, LLC

1.2-22

The Silicon Heterostructure Handbook

also in 1991 (a busy year for our field). In 1992, the first a-SiGe solar cell was discussed [83], and in 1993, the first high-gain a-SiGe phototransistor [84]. The first SiGe pMOSFETs using alternate substrate materials were demonstrated, first in SOI in 1993 [85], and then on sapphire in 1997 [88], the first SiGe:C channel pMOSFET was demonstrated in 1996 [89], and the first vertical SiGe FET was published in 1998 [92]. Because of the desire to use Si-based bandgap engineering to improve not only the p-channel MOSFET, but also the n-channel MOSFET, research in the early- to mid-1990s in the FET field began to focus on strained Si MOSFETs on relaxed SiGe layers, with its consequent improvement in both electron and hole transport properties. This work culminated in the first strained Si pMOSFET in 1993 [87], and the first stained Si nMOSFET in 1994 [88], and remains an intensely active research field today. Key to the eventual success of strained Si CMOS approaches was that significant mobility enhancement could be achieved in both nFETs and pFETs down to very short (sub-micron) gate lengths, and this was first demonstrated in 1998 [90]. Strained Si CMOS at the 90-nm node and below is rapidly becoming mainstream for most serious CMOS companies, and the first commercial 90 nm strained Si CMOS technology platform was demonstrated by Intel in 2002 [91]. At last count, there were upwards of a halfdozen companies (e.g., Texas Instruments and IBM) also rapidly pushing toward 90 nm (and below) strained Si CMOS technologies, utilizing a variety of straining techniques, and thus it would appear that strained Si CMOS will be a mainstream IC technology in the near future, joining SiGe HBT BiCMOS technology. This is clearly outstanding news for our field. The merger of SiGe HBTs with strained Si CMOS would be a near-term logical extension.

References 1. R Braunstein, AR Moore, and F Herman. Intrinsic optical absorption in germanium–silicon alloys. Physical Review B 32:1405–1408, 1958. 2. HC Theuerer, JJ Kleimack, HH Loar, and H Christensen. Epitaxial diffused transistors. Proceedings of the IRE 48:1642–1643, 1960. 3. BA Joyce and RR Bradley. Epitaxial growth of silicon from the pyrolysis of monosilane on silicon substrates. Journal of the Electrochemical Society 110:1235–1240, 1963. 4. JH van der Merwe. Crystal interfaces. Part I. Semi-infinite crystals. Journal of Applied Physics 34:117–125, 1963. 5. JH van der Merwe. Crystal interfaces. Part II. Finite overgrowths. Journal of Applied Physics 34:123–127, 1963. 6. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations in layers. Journal of Crystal Growth 27:118–125, 1974. 7. E Kasper, HJ Herzog, and H Kibbel. A one-dimensional SiGe superlattice grown by UHV epitaxy. Journal of Applied Physics 8:1541–1548, 1975. 8. JC Bean, TT Sheng, LC Feldman, AT Fiory, and RT Lynch. Pseudomorphic growth of GexSi1x on silicon by molecular beam epitaxy. Applied Physics Letters 44:102–104, 1984. 9. R People and JC Bean. Calculation of critical layer thickness versus lattice mismatch for GexSi1x/Si strained layer heterostructures. Applied Physics Letters 47:322–324, 1985. 10. R People. Indirect bandgap of coherently strained Si1xGex bulk alloys on h0 0 1i silicon substrates. Physical Review B 32:1405–1408, 1985. 11. DV Lang, R People, JC Bean, and AM Sergent. Measurement of the bandgap of GexSi1x/Si strainedlayer heterostructures. Applied Physics Letters 47:1333–1335, 1985. 12. JF Gibbons, CM Gronet, and KE Williams. Limited reaction processing: silicon epitaxy. Applied Physics Letters 47:721–723, 1985. 13. G Abstreiter, H Brugger, T Wolf, H Joke, and HJ Kerzog. Strain-induced two-dimensional electron gas in selectively doped Si/SixGe1x superlattices. Physical Review 54:2441–2444, 1985. 14. BS Meyerson. Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition. Applied Physics Letters 48:797–799, 1986.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-23

15. R People and JC Bean. Band alignments of coherently strained GexSi1x/Si heterostructures on h0 0 1i GeySi1y substrates. Applied Physics Letters 48:538–540, 1986. 16. BS Meyerson, KJ Uram, and FK LeGoues. Cooperative phenomena is silicon/germanium low temperature epitaxy. Applied Physics Letters 53:2555–2557, 1988. 17. CA King, JL Hoyt, CM Gronet, JF Gibbons, MP Scott, and J Turner. Si/Si1x/Gex heterojunction bipolar transistors produced by limited reaction processing. IEEE Electron Device Letters 10:52–54, 1989. 18. TO Sedgwick, M Berkenbilt, and TS Kuan. Low-temperature selective epitaxial growth of silicon at atmospheric pressure. Applied Physics Letters 54:2689–2691, 1989. 19. PJ Wang, FF Fang, BS Meyerson, J Mocera, and B Parker. Two-dimensional hole gas in Si/Si0.85Ge0.15 modulation doped heterostructures. Applied Physics Letters 54:2701–2703, 1989. 20. P Agnello, TO Sedgwick, MS Goorsky, J Ott, TS Kuan, and G Scilla. Selective growth of silicon– germanium alloys by atmospheric-pressure chemical vapor deposition at low temperatures. Applied Physics Letters 59:1479–1481, 1991. 21. T Manku and A Nathan. Lattice mobility of holes in strained and unstrained Si1xGex alloys. IEEE Electron Device Letters 12:704–706, 1991. 22. T Manku and A Nathan. Electron drift mobility model for devices based on unstrained and coherently strained Si1xGex grown on h0 0 1i silicon subtrate. IEEE Transactions on Electron Devices 39:2082–2089, 1992. 23. K Erbel, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Applied Physics Letters 60:3033–3035, 1992. 24. HJ Osten, E Bugiel, and P Zaumseil. Growth of inverse tetragonal distorted SiGe layer on Si(0 0 1) by adding small amounts of carbon. Applied Physics Letters 64:3440–3442, 1994. 25. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 26. J Bardeen and WH Brattain. The transistor, a semi-conductor triode. Physical Review 71:230–231, 1947. 27. W Shockley, M Sparks, and GK Teal. p–n junction transistors. Physical Review 83:151–162, 1951. 28. M Tanenbaum and DE Thomas. Diffused emitter and base silicon transistors. Bell System Technical Journal 35:23–34, 1956. 29. See, for instance, W Shockley. U.S. Patents 2,502,488, 2,524,035, and 2,569,347. 30. H Kroemer. Zur theorie des diffusions und des drifttransistors. Part III. Archiv der Elektrischen Ubertragungstechnik 8:499–504, 1954. 31. H Kroemer. Quasielectric and quasimagnetic fields in nonuniform semiconductors. RCA Review 18:332–342, 1957. 32. H Kroemer. Theory of a wide-gap emitter for transistors. Proceedings of the IRE 45:1535–1537, 1957. 33. B Brar, GJ Sullivan, and PM Asbeck. Herb’s bipolar transistors. IEEE Transactions on Electron Devices 48:2473–2476, 2001. 34. RM Warner. Microelectronics: Its unusual origin and personality. IEEE Transactions on Electron Devices 48:2457–2467, 2001. 35. SS Iyer, GL Patton, SL Delage, S Tiwari, and J.M.C. Stork. Silicon–germanium base heterojunction bipolar transistors by molecular beam epitaxy. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 874–876. 36. GL Patton, DL Harame, JMC Stork, BS Meyerson, GJ Scilla, and E Ganin. Graded-SiGe-base, polyemitter heterojunction bipolar transistors. IEEE Electron Device Letters 10:534–536, 1989. 37. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 63-75 GHz fT SiGe-base heterojunction-bipolar technology. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 49–50. 38. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, GJ Scilla, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 75 GHz fT SiGe base heterojunction bipolar transistors. IEEE Electron Device Letters 11:171–173, 1990.

© 2006 by Taylor & Francis Group, LLC

1.2-24

The Silicon Heterostructure Handbook

39. JH Comfort, GL Patton, JD Cressler, W Lee, EF Crabbe´, BS Meyerson, JY-C Sun, JMC Stork, P-F Lu, JN Burghartz, J Warnock, K Kenkins, K-Y Toh, M D’Agostino, and G Scilla. Profile leverage in a selfaligned epitaxial Si or SiGe-base bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 21–24. 40. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base PNP transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 41. EF Crabbee´, GL Patton, JMC Stork, BS Meyerson, and JY-C Sun. Low temperature operation of Si and SiGe bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20. 42. DL Harame, EF Crabbe´, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, J Malinowski, and AJ Dally. A high-performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1992, pp. 19–22. 43. DL Harame, JMC Stork, BS Meyerson, KY-J Hsu, J Cotte, KA Jenkins, JD Cressler, P Restle, EF Crabbe´, S Subbanna, TE Tice, BW Scharf, and JA Yasaitis. Optimization of SiGe HBT technology for high speed analog and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 71–74. 44. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Techncial Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 79–81. 45. EF Crabbe´, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 46. DL Harame, K Schonenberg, M Gilbert, D Nguyen-Ngoc, J Malinowski, S-J Jeng, BS Meyerson, JD Cressler, R Groves, G Berg, K Tallman, K Stein, G Hueckel, C Kermarrec, T Tice, G Fitzgibbons, K Walter, D Colavito, T Houghton, N Greco, T Kebede, B Cunningham, S Subbanna, JH Comfort, and EF Crabbe´. A 200 mm SiGe-HBT technology for wireless and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, Washington, 1994, pp. 437–440. 47. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter cap SiGebase bipolar technology for liquid nitrogen temperature operation. IEEE Electron Device Letters 15:472–474, 1994. 48. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Transactions on Nuclear Science 42:1558–1566, 1995. 49. LS Vempati, JD Cressler, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minnneapolis, 1995, pp. 129–132. 50. L Lanzerotti, A St Amour, CW Liu, JC Sturm, JK Watanabe, and ND Theodore. Si/Si1xyGexCy /Si heterojunction bipolar transistors. IEEE Electron Device Letters 17:334–337, 1996. 51. A Schu¨ppen, S Gerlach, H Dietrich, D Wandrei, U Seiler, and U Ko¨nig. 1-W SiGe power HBTs for mobile communications. IEEE Microwave and Guided Wave Letters 6:341–343, 1996. 52. PA Potyraj, KJ Petrosky, KD Hobart, FJ Kub, and PE Thompson. A 230-Watt S-band SiGe heterojunction junction bipolar transistor. IEEE Transactions on Microwave Theory and Techniques 44:2392–2397, 1996. 53. K Washio, E Ohue, K Oda, M Tanabe, H Shimamoto, and T Onai. A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-Gate Delay. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1997, pp. 795–798. 54. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-25

55. SJ Jeng, B Jagannathan, J-S Rieh, J Johnson, KT Schonenberg, D Greenberg, A Stricker, H Chen, M Khater, D Ahlgren, G Freeman, K Stein, and S Subbanna. A 210-GHz fT SiGe HBT with nonself-aligned structure. IEEE Electron Device Letters 22:542–544, 2001. 56. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz.Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 57. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M. Waitschull, JW Weijtmans, and C Willis. A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 211–214. 58. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 59. J Cai, M Kumar, M Steigerwalt, H Ko, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 215–218. 60. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeterwave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp. 395–398. 61. DL Harame and BS Meyerson. The early history of IBM’s SiGe mixed signal technology. IEEE Transactions on Electron Devices 48:2555–2567, 2001. 62. T Tatsumi, H Hirayama, and N Aizaki. Si/Ge0.3Si0.7 heterojunction bipolar transistor made with Si molecular beam epitaxy. Applied Physics Letters 52:895–897, 1988. 63. H Temkin, JC Bean, A Antreasyan, and R Leibenguth. GexSi1x strained-layer heterostructure bipolar transistors. Applied Physics Letters 52:1089–1091, 1988. 64. D-X Xu, G-D Shen, M Willander, W-X Ni, and GV Hansson. n-Si/p-Si1x /n-Si double-heterojunction bipolar transistors. Applied Physics Letters 52:2239–2241, 1988. 65. GL Patton, SS Iyer, SL Delage, S Tiwari, and JMC Stork. Silicon–germanium-base heterojunction bipolar transistors by molecular beam epitaxy. IEEE Electron Device Letters 9:165–167, 1988. 66. A Gruhle, H Kibbel, U Ko¨nig, U Erben, and E Kasper. MBE-Grown Si/SiGe HBTs with high b, fT, and fmax. IEEE Electron Device Letters 13:206–208, 1992. 67. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 68. H. Lilienfeld Patent, 1926; O. Heil, British patent number 439,457, 1935. 69. D Khang and MM Atalla. Silicon–silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, 1960. 70. FM Wanlass and CT Sah. Nanowatt logic using field-effect metal-oxide-semiconductor triodes (MOSTs). IEEE International Solid-State Circuits Conference, Philadelphia, 1963, pp. 32–33. 71. P Balk. Surface properties of oxidized germanium-doped silicon. Journal of the Electrochemical Society 118:494–495, 1971. 72. H Daembkes, H-J Herzog, H Jorke, H. Kibbel, and E Kasper. The n-channel SiGe/Si modulation doped field-effect transistor. IEEE Transactions on Electron Devices 33:633–638, 1986.

© 2006 by Taylor & Francis Group, LLC

1.2-26

The Silicon Heterostructure Handbook

73. TP Pearsall and JC Bean. Enhancement and depletion-mode p-channel GexSi1x modulation-doped field effect transistor. IEEE Electron Device Letters 7:308–310, 1986. 74. H Temkin, TP Pearsall, JC Bean, RA Logan, and S. Luryi. GexSi1x strained-layer superlattice waveguide photodetectors operating near 1.3 mm. Applied Physics Letters 48:963–965, 1986. 75. RD Thompson, KN Tu, J Angillelo, S Delage, and SS Iyer. Interfacial reaction between Ni and MBE grown SiGe alloys. Journal of the Electrochemical Society 135:3161–3163, 1988. 76. HC Liu, D Landheer, M Buchmann, and DC Houghton. Resonant tunneling diode in the Si1xGex system. Applied Physics Letters 52:1809–1811, 1988. 77. RC Taft, JD Plummer, and SS Iyer. Demonstration of a p-channel BiCFET in the GexSi1x /Si system. IEEE Electron Device Letters 10:14 –16, 1989. 78. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 253–256. 79. RA Soref, F Namavar, and JP Lorenzo. Optical waveguiding in a single-crystal layer of germanium– silicon grown on silicon. Optics Letters 15:270–272, 1990. 80. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. Enhancement-mode quantum-well GexSi1x PMOS. IEEE Electron Device Letters 12:154–156, 1991. 81. K Ismail, BS Meyerson, and PJ Wang. Electron resonant tunneling in Si/SiGe double barrier diodes. Applied Physics Letters 59:973–975, 1991. 82. DC Houghton, JP Noel, and NL Rowell. Electroluminescence and photoluminesence from SiGe alloys grown on (1 0 0) silicon by MBE. Materials Science and Engineering B 9:237–244, 1991. 83. DS Chen, JP Conde, V Chu, S Aljishi, JZ Liu, and S Wagner. Amorphous silicon–germanium thinfilm photodetector array. IEEE Electron Device Letters 13:5–7, 1992. 84. S-B Hwang, YK Fang, K-H Chen, C-R Liu, J-D Hwang, and M-H Chou. An a-Si:H/a-Si, Ge:H bulk barrier phototransistor with a-SiC:H barrier enhancement layer for high-gain IR optical detector. IEEE Transactions on Electron Devices 40:721–726, 1993. 85. DK Nayak, JCS Woo, GK Yabiku, KP MacWilliams, JS Park, and KL Wang. High mobility GeSi PMOS on SIMOX. IEEE Electron Device Letters 14:520–522, 1993. 86. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. High-mobility p-channel metal-oxide semiconductor field-effect transistor on strained Si. Applied Physics Letters 62:2853–2855, 1993. 87. J Welser, JL Hoyt, and JF Gibbons. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Device Letters 15:100–102, 1994. 88. SK Ray, S John, S Oswal, and SK Banerjee. Novel SiGeC channel heterojunction pMOSFET. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1996, pp. 261–264. 89. SJ Mathew, WE Ansley, WB Dubbelday, JD Cressler, JA Ott, JO Chu, PM Mooney, KL Vavanagh, BS Meyerson, and I Lagnado. Effect of Ge profile on the frequency response of a SiGe pFET on sapphire technology. Technical Digest of the IEEE Device Research Conference, Boulder, 1997, pp. 130–131. 90. K Rim, JL Hoyt, and JF Gibbons. Transconductance enhancement in deep submicron strained-Si n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1998, pp. 707–710. 91. KC Liu, SK Ray, SK Oswal, and SK Banerjee. Si1xGex /Si vertical pMOSFET fabricated by Ge ion implantation. IEEE Electron Device Letters 19:13–15, 1998. 92. S Thompson, N. Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, J Bielefeld, R Bigwood, J Brandenburg, M Buehler, S Cea, V Chikarmane, C Choi, R Frankovic, T Ghani, G Glass, W Han, T Hoffmann, M Hussein, P Jacob, A Jain, C Jan, S Joshi, C Kenyon, J Klaus, S Klopcic, J Luce, Z Ma, B McIntyre, K Mistry, A Murthy, P Nguyen, H Pearson, T Sandford, R Schweinfurth, R Shaheed, S Sivakumar, M Taylor, B Tufts, C Wallace, P Wang, C Weber, and M Bohr. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm2 SRAM Cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-27

93. VP Kesan, S Subbanna, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, and JA Ott. High performance 0.25 mm p-MOSFETs with silicon–germanium channels for 300 K and 77 K operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 25–28, 1991. 94. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, AC Megdanis, CL Stanis, AA Bright, GMW Kroesen, and AC Warren. High-mobility modulation-doped, graded SiGe-channel p-MOSFETs. IEEE Electron Device Letters 12:447–449, 1991. 95. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Transactions on Electron Devices 41:90–102, 1994.

© 2006 by Taylor & Francis Group, LLC

2 SiGe and Si Strained-Layer Epitaxy 2.1

Overview: SiGe and Si Strained-Layer Epitaxy J.D. Cressler.................................. 2.1-31

2.2

Strained SiGe and Si Epitaxy B. Tillack and P. Zaumseil ........................................ 2.2-33 Introduction . Heteroepitaxy of SiGe and SiGe:C on Si . Characterization of Strained SiGe and Si Layers . Growth of Strained SiGe on Si . Summary

2.3

Si/SiGe(C) Epitaxy by RTCVD D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot.............................................................................................. 2.3-45 Introduction . Rapid Thermal Chemical Vapor Deposition . Epitaxy Processes . Epitaxy Integration . Recent Applications . Summary

2.4

MBE Growth Techniques M. Oehme and E. Kasper................................................. 2.4-85 Introduction . Requirements on an SiGe MBE System . UHV Conditions . Sources of Atomic and Molecular Beams . Substrate Heating and Cleaning . In Situ Analysis . Summary

2.5

UHV/CVD Growth Techniques T.N. Adam ............................................................. 2.5-95 Introduction . Chemistry . Low Temperature and Low Pressure . Alloys, Doping, and Selective Epitaxial Growth . Substrate Cleaning . Reactors

2.6

Defects and Diffusion in SiGe and Strained Si A.R. Peaker and V.P. Markevich.................................................................................. 2.6-107 Introduction . Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge . Effects of SiGe Alloy Composition and Strain on Defect Characteristics . Specific Defects in SiGe . Diffusion . Dislocations . Summary

2.7

Stability Constraints in SiGe Epitaxy A. Fischer ................................................... 2.7-127 Introduction . Image-Force Method for Strained Layer Relaxation . Surface Relaxation Stress . Interaction between Internal Stress and External Stress . Critical Thickness and Film Stress of SiGe/Si Layers . Plastic Deformation and Work Hardening in SiGe/Si . Force Balance Model for Buried SiGe Strained Layers . Summary

2.1-29 © 2006 by Taylor & Francis Group, LLC

2.1-30

The Silicon Heterostructure Handbook

2.8

Electronic Properties of Strained Si/SiGe and Si1-yCy Alloys J.L. Hoyt ........... 2.8-143 Introduction . Strain and its Impact on Energy Bands . Measurements of Energy Band Lineups . Introduction to Transport Properties . Summary

2.9

Carbon Doping of SiGe H.J. Osten........................................................................ 2.9-157 Introduction . Basic Considerations . Growth of C-Containing Alloys . Control of Dopant Diffusion by Adding Carbon . Strain Manipulation in Si1 x yGexCy Layers . Microscopic Structure of SiGeC Layers . Strain-Stabilized Layers with High C Concentration . Thermal Stability . Impact of Carbon on Electrical Layer Properties . Summary

2.10

Contact Metallization on Silicon–Germanium C.K. Maiti .............................. 2.10-171 Introduction . Contact Metallization: Current Status . Contact Metallization: Challenges . Poly-SiGe Gate Technology . Silicidation of SiGe . Silicidation of SiGeC . Summary

2.11

Selective Etching Techniques for SiGe/Si S. Monfray, S. Borel, and T. Skotnicki......................................................................................... 2.11-187 Introduction . Process Development for Industrial Applications . Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology . Summary

© 2006 by Taylor & Francis Group, LLC

2.1 Overview: SiGe and Si Strained-Layer Epitaxy

John D. Cressler Georgia Institute of Technology

The field of silicon heterostructures necessarily begins with materials, and the crystal growers of our field have learned through much hard work how to practice modern miracles in their growth of near defectfree, nanoscale films of Si and SiGe strained-layer epitaxy, which are compatible with conventional highvolume silicon integrated circuit manufacturing. Section 2 of this book tells the materials side of the story, and details the many advances in the Si–SiGe strained-layer epitaxy for device applications. Chapter 2.2, ‘‘Strained SiGe and Si Epitaxy,’’ by B. Tillack of IHP, reviews the underlying materials science of Si–SiGe epitaxy, while Chapters 2.3 to 2.5 discuss modern SiGe epitaxial growth techniques: RTCVD in Chapter 2.3, ‘‘SiGe:C Eiptaxy by RTCVD,’’ by D. Dutartre of ST Microelectronics, MBE in Chapter 2.4, ‘‘MBE Growth Techniques,’’ by M. Oehme and E. Kaspar of the University of Stuttgart, and UHV/CVD in Chapter 2.5, ‘‘UHV/CVD Growth Techniques,’’ by T. Adam of IBM. The complexity of epi defects and the dopant diffusion characteristics in such films are discussed by A. Peaker of the University of Manchester in Chapter 2.6, ‘‘Defects and Diffusion in Strained SiGe and Si,’’ and the most recent (and robust) stability theory is covered in Chapter 2.7, ‘‘Stability Constraints in SiGe Epitaxy,’’ by A. Fischer of IHP. The electrical transport properties of SiGe, strained Si, and Si–C alloys are detailed by J. Hoyt of MIT in Chapter 2.8, ‘‘Electronic Properties of Strained Si–SiGe and Si1 yCy alloys.’’ The basic mechanisms underlying the now-pervasive use of Cdoping in SiGe HBTs as a boron-doping diffusion inhibitor are reviewed in Chapter 2.9, ‘‘Carbon Doping of SiGe,’’ by J. Osten of the University of Hanover, and Chapter 2.10, ‘‘Contact Metallization on SiGe,’’ by C. Maiti of IIT, covers ohmic and Schottky contacts to SiGe and strained Si. Finally, Chapter 2.11, ‘‘Selective Etching Techniques for SiGe–Si,’’ by S. Monfray of ST Microelectronics, discusses the use of SiGe for selective etching in various emerging MEMS applications. In addition to this material, and the numerous references contained in each chapter, a number of review articles and books on SiGe–strained Si materials exist, including Refs. [1–6].

References 1. R People. Physics and applications of GexSi1 Quantum Electronics 22:1696–1710, 1986.

x /Si

strained layer heterostructures. IEEE Journal of

2.1-31 © 2006 by Taylor & Francis Group, LLC

2.1-32

The Silicon Heterostructure Handbook

2. JC Bean. Silicon-based semiconductor heterostructures: column IV bandgap engineering. Proceedings of the IEEE 80:571–587, 1992. 3. B Meyerson. UHV/CVD growth of Si and SiGe alloys: chemistry, physics, and device applications. Proceedings of the IEEE 80:1592–1608, 1992. 4. SC Jain. Germanium–Silicon Strained Layers and Heterostructures. New York, NY: Academic Press, 1994. 5. E Kaspar. Properties of Strained and Relaxed Silicon Germanium. London: INSPEC, EMIS Datareviews Series No. 12, 1995. 6. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. London: The Institute of Electrical Engineers, 2001.

© 2006 by Taylor & Francis Group, LLC

2.2 Strained SiGe and Si Epitaxy 2.2.1 2.2.2 2.2.3

Bernd Tillack and Peter Zaumseil IHP

2.2.4 2.2.5

Introduction................................................................. 2.2-33 Heteroepitaxy of SiGe and SiGe:C on Si................... 2.2-33 Characterization of Strained SiGe and Si Layers ....................................................................... 2.2-36 Growth of Strained SiGe on Si .................................. 2.2-39 Summary ...................................................................... 2.2-42

2.2.1 Introduction By adding Ge to Si new properties of the material can be created, which offer applications in a wide range of electronic devices. In this way the capability of Si electronics is widened. The SiGe heterojunction bipolar transistor (SiGe HBT), which makes use of SiGe bandgap engineering and strain, has reached industrial level (see Refs. [1, 2]) with increasing market potential. For future CMOS technologies SiGe and Si strained layers are becoming increasingly important, for instance, for higher mobility channel material [3, 4]. After the first report on growth of epitaxial SiGe layers dating back to 1962 [5], the pioneering work of Kasper (see, e.g., Ref. [6]) and Meyerson (see, e.g., Ref. [7]) became important milestones for the development of SiGe strained-layer epitaxy. After demonstrating the stability and high-volume production capability of SiGe strained-layer epitaxy for HBT base deposition using ultrahigh vacuum CVD (UHV CVD) [8] and low-pressure CVD (LP CVD) [9] the low-temperature epitaxial deposition of SiGe by CVD was ready to be used in manufacturing. Especially, the demonstration of the ability to grow device-quality SiGe layers without using UHV deposition techniques [10–14] has greatly influenced the development of strained-layer deposition process technology and tools. Adding C to SiGe has extended the capability of the material and has been another important step in the success story of SiGe:C strained-layer epitaxy for HBT application [15, 16]. C can significantly suppress B diffusion without negative impact on device parameters [16, 17]. The first BiCMOS technology using SiGe:C HBTs was demonstrated by IHP in 1999 [18]. As an example, Figure 2.2.1 shows a transmission electron microscopy (TEM) cross section of an HBT with SiGe:C base layer deposited by CVD. In this chapter, we will review the basic considerations regarding SiGe heteroepitaxy (Section 2.2.2) and strain relaxation. Moreover, characterization of SiGe layers (Section 2.2.3) and process aspects of growth of strained SiGe and SiGe:C on Si (Section 2.2.4) will be discussed.

2.2.2 Heteroepitaxy of SiGe and SiGe:C on Si Silicon and germanium have the same crystallographic structure. Both materials can be alloyed as Si1xGex with any value of 0 x 1. The lattice constant of Ge is 4.18% larger than that of Si, and 2.2-33 © 2006 by Taylor & Francis Group, LLC

2.2-34

The Silicon Heterostructure Handbook

SiGe:C Base

100 nm

FIGURE 2.2.1

TEM cross section of HBT with pseudomorphic SiGe:C on Si (IHP’s first SiGe:C HBT generation).

for a Si1xGex alloy it does not exactly follow Vegard’s law. The relative change of the lattice constant is given by [19] «¼

aSiGe aSi ¼ 0:00501x 2 þ 0:03675x: aSi

Growing a Si1xGex layer with x > 0 on a Si substrate means that the layer is under compressive stress. A perfect epitaxial growth of such a strained heteroepitaxial layer is only possible as long as its thickness does not exceed a critical thickness of stability [20]. Above this value, the strain is relaxed through the formation of misfit dislocations. The dislocation-free (pseudomorphic) SiGe layer on a 001 Si substrate surface shows a tetragonally distorted unit cell (see also Figure 2.2.2) with in-plane (ak) and perpendicular (a?) lattice constants given by ak ¼ aSi ;

a? ¼ aSi (1 þ k«);

with k ¼1þ

2C12 ﬃ 1:75: C11

In this case, the degree of relaxation is zero. For a fully relaxed layer the lattice constants ak and a? are equal:

© 2006 by Taylor & Francis Group, LLC

2.2-35

Strained SiGe and Si Epitaxy

a|| a⊥

SiGe

Si

(a)

(b)

FIGURE 2.2.2 Structural scheme of pseudomorphic (a) and fully relaxed (b) SiGe layer grown on Si substrate.

ak ¼ a? ¼ aSi (1 þ «): For a partly relaxed layer the lattice constants depend on both the Ge content and the degree of relaxation [21]. The consequence is that always ak and a? must be measured to determine the Ge content (and the degree of relaxation) as long as it is not definitely clear that a SiGe layer is either pseudomorphic or fully relaxed. Experimentally it was found that using low deposition temperatures (5508C and lower) it was possible to deposit pseudomorphic SiGe layers with thicknesses exceeding the critical thickness value [22, 23]. In these cases films are metastable. Nevertheless, by capping metastable SiGe films with Si, stabilization could be obtained resulting in SiGe–Si stacks that withstand thermal treatment during device processing (see Chapter 2.7, ‘‘Stability Constraints in SiGe Epitaxy’’). The strain situation is completely different for Si1yCy layers. Carbon atoms are much smaller than Si atoms, and in consequence the lattice constant of Si1yCy is smaller than that of silicon. Here, a deviation from Vegard’s law was also found [24]: «¼

aSiC aSi ¼ 0:10504y 2 0:44909y: aSi

A Si1xyGexCy layer can be treated in first approximation as a mixture of a Si1xGex and a Si1–yCy layer. The compressive strain of the SiGe can be (partly) compensated by the tensile strain of the added C, which will be demonstrated in detail in Section 2.2.3. Different modes were found during heteroepitaxy depending on the strain in the heteroepitaxial film and the growth conditions (mainly growth temperature) (Figure 2.2.3). Which growth mode for the epitaxial deposition is taking place is determined by the free energy of the interfaces and the lattice mismatch of the heteroepitaxial system. For most of the applications layer-by-layer growth (two-dimensional growth) is desired. In this case, the pseudomorphic films are obtained if the strain in the film does not exceed the critical thickness limitation or if the films are metastable, and partly relaxed films are obtained if the strain is relaxed by misfit dislocation formation [20, 25]. The mode can change from two-dimensional to three-dimensional (island growth) during growth if the strain increases or for high deposition temperatures (Stranski–Krastanow growth). Dislocation-free Stranski–Krastanow growth in particular has been investigated (e.g., Ref. [26]) because of its capability for optical applications. For selective heteroepitaxial growth it was found that the dislocation density depends on the area of the deposited films [27]. The dislocation density decreases with decreasing area. Even dislocation-free films with thicknesses above the critical thickness are possible for small areas.

© 2006 by Taylor & Francis Group, LLC

2.2-36

The Silicon Heterostructure Handbook

(a) Layer-by-layer growth

(b) Island growth

(Frank−van der Merwe)

(Volmer−Weber)

(c) Layer-by-layer followed by island growth (Stransky−Krastranow)

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

FIGURE 2.2.3 Growth modes for heteroepitaxial systems. (From JW Matthews and AE Blakeslee. Defects in epitaxial multilayers. III. Preparation of almost perfect layers. J Cryst Growth 32:265–273, 1976; JH Van der Merwe. Crystal interfaces. Part II. Finite overgrowth. J Appl Phys 34:123–127, 1963; L Vescan, W Ja¨ger, C Dieker, K Schmidt, A Hartmann, and H Lu¨th. Formation of heterogeneous thickness modulations during epitaxial growth of LPCVDSi1xGex /Si quantum well structures. MRS Symposium Proceedings, Vol. 263, Mechanism of Heteroepitaxial Growth Symposium, 1992, pp. 23–28. With permission.)

2.2.3 Characterization of Strained SiGe and Si Layers One of the main structural features of SiGe or SiGe:C layers is the difference in its lattice constant relative to the silicon substrate, which was already mentioned in Section 2.2.2. This difference in lattice constant, or strain, which correlates in the case of a pseudomorphically grown SiGe layer directly to the Ge content, offers the possibility of an easy characterization by X-ray diffractometry (XRD), where the lattice constant is transferred to a measurable diffraction angle via Bragg’s law 2d sin Q ¼ nl: In the following, we will discuss the application of XRD to characterize SiGe and SiGe:C structures. Later on, we will compare the results obtained by XRD with those obtained by other techniques, and give an outlook to further developments. Here, we restrict our discussion to pseudomorphic structures; fully or partly relaxed structures will be discussed elsewhere. The typical XRD arrangement consists of the X-ray source, a monochromator or collimator, the sample, and the detector. In the simple case, the collimator consists of a perfect Si crystal of the same orientation as the sample (Figure 2.2.4). Modern diffractometers often use the so-called Bartel’s monochromators and additional mirrors as collimator to make the arrangement more flexible. For some applications, an additional analyzer crystal is used in front of the detector. A rocking curve is measured by rotating the sample around a substrate diffraction peak DQ (typically of the netplanes parallel to the surface) and correcting the detector position in such a way that the diffracted beam enters the detector window at the same position always (Q/2Q scan). How the diffractometer arrangement influences the measured rocking curve of a SiGe structure was demonstrated in Ref. [28]. Figure 2.2.5 shows as an example the CuKa-400-diffraction of a 117 nm thick Si0.8Ge0.2 layer with a 56 nm thick Si cap layer on top. For such a relatively simple structure, the Ge content can be directly obtained from the angular distance between Si and SiGe peak. The width of the SiGe peak is a direct measure of the SiGe layer thickness. But, the comparison with the calculated curve without the Si cap layer shows that it is difficult to estimate the thickness of the cap layer from the diffraction pattern directly. The situation becomes even worse for more complicated structures, for example, structures with graded SiGe layers (see below). The determination of the depth profile of such structures is only possible by creating a reasonable layer model, simulation of the diffraction curve of this model, and fitting the simulated curve to the experimental one by modification of free parameters.

© 2006 by Taylor & Francis Group, LLC

2.2-37

Strained SiGe and Si Epitaxy

Detector

Collimator

2 ∆Q X-ray source

∆Q

Sample

FIGURE 2.2.4 Scheme of a double crystal diffractometer arrangement.

10−1 10−2

exp.: 56 nm Si /117 nm Si0.8Ge0.2 /Si sim.: no cap/117 nm Si0.8Ge0.2 /Si

x

Reflectivity

10−3

dSiGe

10−4

10−6 10−7 −3000

−2500

−2000 −1500 −1000 −500 Delta theta (arcsec)

Si substrate

SiGe layer

10−5

0

500

FIGURE 2.2.5 Experimental diffraction curve of a SiGe layer with a Si cap layer on top and a simulated curve without the cap layer; CuKa radiation, 400 reflection. The simulated curve is shifted by one order of magnitude relative to the experimental one.

For Si1yCy layers, the diffraction curve would be similar but with the Si1yCy peak on the right-hand side of the Si substrate peak (high angle side). A Si1xyGexCy layer can be treated in first approximation as a mixture of a Si1xGex and a Si1–yCy layer. The compressive strain of the SiGe can be (partly) compensated by the tensile strain of the SiC. Figure 2.2.6 shows an XRD measurement with calculated rocking curves of a 100-nm thick SiGeC layer with 20% Ge. The SiGeC peak shift as a function of the C content indicates strain compensation by adding C to SiGe. Since XRD measures primarily the strain of the layer relative to the substrate, and for Si1xyGexCy this strain is the sum of two components, it is impossible to determine the Ge and the C content without independent information about one of the components. Usually, to get the C content of a SiGeC layer we deposit a SiGe layer with the same Ge deposition parameters for comparison. Then the Ge content is measured at the SiGe sample, and assuming the same for the SiGeC sample the C content can be obtained. To characterize an HBT structure under conditions of a routine process control, the following requirements must be fulfilled: the depth resolution should be in the order of about 1 nm; the accuracy of the absolute Ge content should be better than 0.5%; it must be nondestructive, fast, and reliable. This is a real challenge for XRD, especially when the Ge content is not constant over the layer thickness as in typical HBT structures.

© 2006 by Taylor & Francis Group, LLC

2.2-38

The Silicon Heterostructure Handbook

10−1 Carbon content

Reflectivity

10−2 10−3

0%

0.5% 1% 1.5% 0.25% 0.75% 1.25%

1.75%

10−4 10−5 10−6 10−7 −2500 −2000 −1500 −1000 −500

0

500

Delta theta (arcsec)

FIGURE 2.2.6 Calculated rocking curves of a 100 nm thick SiGeC layer with 20% Ge and increasing carbon content; CuKa radiation, 400 reflection.

100

(b)

xmax = 20.9 ± 0.5 %

20 Ge content (%)

Reflectivity

10−1

25 exp. sim.

(a)

10−2 10−3 10−4 10−5

15 10

10−6 −3000

−2000 −1000 0 Delta theta (arcsec)

0 1000

dSiGe (nm)

dSi cap (nm) 59.6 ± 1.2

5

0

20

40

45.9 ± 0.6 60

80

100

120

140

Depth (nm)

FIGURE 2.2.7 XRD rocking curve (a) of a SiGe HBT structure. The full line represents the best-fitted simulated curve. The Ge depth profile is shown in (b).

Figure 2.2.7 shows as an example the characterization of an HBT structure. Due to the gradient part of the Ge profile, the rocking curve (a) shows less details compared to the simple layer structure (Figure 2.2.5). Here, it is absolutely necessary to simulate curves with a suited model and to fit this in a trial-anderror procedure to the experimental one, since it is practically impossible to get any direct information from the rocking curve. The depth profile of Ge content that gave the best fit of the rocking curve is shown in Figure 2.2.7b. The gradient part of the Ge profile is divided into 11 lamellae of constant strain. Since the thickness of each lamella is a free parameter in the fitting process, the shape of this profile part need not be linear. It should fit to the real shape within the sensitivity limits of this technique. The accuracy depends on the stability of the fitting procedure, supposing the model used describes the real situation in a proper way [29]. This is mainly influenced by the statistical intensity fluctuations (noise) in the RC range far away from the Si substrate peak. Following this, the accuracy is given by the intensity of the X-ray source used or the measuring time. For similar structures to that shown in Figure 2.2.7, an error in the layer thickness of 0.4 to 1.0 nm and of less than 0.4% of the maximum Ge content is typically achievable with an intensity of about 500 kcps in the incident beam and a measuring time of less than 1 h.

© 2006 by Taylor & Francis Group, LLC

2.2-39

Strained SiGe and Si Epitaxy TABLE 2.2.1

Summary of Main Features of Investigated Techniques for HBT Stack Characterization

Technique

Destructive

XRD XRR SE AES SIMS TEM

No No No Yes Yes Yes

Accuracy of Measurement

Area

2

>0.5 0.5 mm (cm) 14 28 mm2 0.1 0.1 mm2 60 60 mm2 (mm)

IF Roughness

dSi cap (nm)

dSiGe (nm)

xmax(%)

1.0 0.5 1.0 — 3.0 1.0

0.6 0.5 1.0 5.0 3.0 1.0

0.5 3–6 1 1–3 3–5 —

() þþ (þ)

Besides XRD, there are many other analytical techniques available to study SiGe or SiGe:C HBT structures. In Ref. [30], the capabilities of six different techniques are discussed; three nondestructive methods: XRD, X-ray reflectometry (XRR), and spectroscopic ellipsometry (SE); and three destructive methods: Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS), and TEM. The main result was that every technique has its advantages and disadvantages, and they all can be used successfully either in process development, failure analysis, or in-line monitoring of the epitaxy process. Within the error limits of each technique, the HBT parameters obtained agreed quite well. Table 2.2.1 summarizes the main features of these techniques. XRD plays an outstanding role, since this technique was used to calibrate other techniques, such as SE, AES, and SIMS, with suitable simple SiGe layer structures. The main disadvantage of XRD for an inline routine application is its limited lateral resolution. A minimum spot size for laboratory devices of about 0.5 0.5 mm2 is sufficient to measure on monitoring areas of the same size [31] but far too large for measurements on real device structures. The alternative for future use is SE. This method allows measurements in micrometer areas; it is fast and well established in microelectronics technology. The procedure [32] includes the creation of databases for the refractive index dispersion of all components of HBT stacks using simple one-layer structures with thickness and composition calibrated by XRD. Then these databases (e.g., SiGe:C optical constants versus Ge-content) can be applied for thickness and composition determination of graded HBTs with different shapes of profiles. The achievable accuracy in layer thickness and Ge content determination is comparable to XRD.

2.2.4 Growth of Strained SiGe on Si The critical thickness limitation and the thermal stability (metastable layers) of strained SiGe films on Si cause severe limitations for the integration into Si process technology. The deposition of pseudomorphic SiGe layers itself requires low-temperature process technique. For the integration into CMOS or BiCMOS technologies the impact of the thermal budget of the deposition process on existing structures as well as the interaction of thermal treatment of the processing with the deposited SiGe layer has to be considered. The low temperature requirement for the deposition techniques has different aspects: 1. For low-temperature deposition the moisture and oxygen level in the reaction chamber is more critical compared to high temperature. 2. The low-temperature deposition process is controlled by the kinetics, which means that process conditions, especially process temperature and partial pressures of source gases, are essentially impacting the parameters of the deposited films like deposition rate, incorporation of Ge, C, and dopants. To grow films according to manufacturing requirements with uniform thickness, composition, and dopant distribution, the temperature has to be controlled during the process and across the wafer very accurately.

© 2006 by Taylor & Francis Group, LLC

2.2-40

The Silicon Heterostructure Handbook

3. For the integration of SiGe into CMOS or BiCMOS low thermal budget deposition is required. The thermal budget of SiGe heteroepitaxy using CVD techniques is mainly determined by the H2 prebake before deposition to clean the substrate surface at temperatures typically between 9508C and 10008C. Different low-temperature deposition techniques have been developed for strained SiGe epitaxy on Si. Today, heteroepitaxy by CVD is in production with proven stability and manufacturability. In the following part, key aspects, requirements, and challenges for SiGe CVD epitaxy will be discussed. For the deposition of epitaxial SiGe layers with low defect densities a clean substrate surface with low contamination level is essential. Cleaning of the substrate is achieved by combination of ex situ wet chemical treatment and in situ H2 prebake in the reaction chamber before epitaxial deposition [33, 34]. The cleaning effect of the prebake improves with increasing temperature. However, it has to be compromised with the demand of a minimum thermal budget necessary for process integration into CMOS and BiCMOS. The kind of surface passivation after wet chemical treatment impacts the minimum H2 prebake temperature necessary for effective contamination removal. An oxide passivation was achieved by a final SC-2 treatment at standard conditions (HCl þ H2O2 þ H2O at 758C to 858C). The chemically grown oxide during SC-2 has to be removed during the prebake, resulting in higher bake temperatures of about 8908C. By applying hydrogen passivation generated by final DHF dip followed by a DI water rinse in combination with an optimized bake regime (maximum temperature for about 3 sec, with a ramp rate of higher than 708C/sec) the bake temperature could be lowered to temperatures below 8008C [33]. Figure 2.2.8 demonstrates, by means of SIMS, the effect of the prebake temperature on the O and C concentrations at the interface between substrate and epitaxial layer for oxygen-passivated surface (Figure 2.2.8a) and hydrogen-passivated surface (Figure 2.2.8b). The impact of defects caused by insufficient H2 prebake during the growth of the epitaxial Si–SiGe–Si layer stack on HBT leakage currents was shown in Ref. [34].

8908 C

1021

7608C

1021

Si epitaxy | substr.

Si epitaxy | substr. 1020

1019 O C

1018 1017

8608 C Si epitaxy | substr.

1021 1020

O, C Concentration (cm-3)

O, C Concentration (cm-3)

1020

C

1018

O

1017 7308C

1021

Si epitaxy | substr. 1020 1019

1019 O C

1018 1017

1019

C

1018

O

1017 0

(a)

50 100 150 200 250 Depth (nm)

0 (b)

50 100 150 200 250 Depth (nm)

FIGURE 2.2.8 SIMS profiles illustrating the oxygen and carbon removal at the epitaxy substrate interface for (a) oxygen passivated (standard RCA cleaning), and (b) hydrogen passivated surface (DHF treatment) with corresponding hydrogen prebake temperatures.

© 2006 by Taylor & Francis Group, LLC

2.2-41

Strained SiGe and Si Epitaxy

After cleaning of the Si surface by H2 prebake the SiGe (or SiGe:C) heteroepitaxy is performed at temperatures typically between 5008C and 7008C depending on the target layer parameters, especially the Ge content. In this temperature range the growth is kinetically controlled. Figure 2.2.9 shows the growth rate as a function of the reciprocal temperature for different GeH4 partial pressures at constant SiH4 partial pressure. GeH4 and SiH4 are the sources for the SiGe layer growth. Hydrogen is used as carrier gas. The activation energies determined from the plots in Figure 2.2.9 are decreasing with increasing GeH4 partial pressure (increasing Ge concentration). For the lowest GeH4 partial pressure, the activation energy is 1.9 eV, which is close to the value obtained for pure Si deposition and discussed as the activated energy of the desorption of H from the Si surface. Adding GeH4 is supporting the desorption of H, resulting in lower activation energies. Deposition pressures between low-pressure conditions (typical 1 to 2 Torr) to atmospheric pressure have been used. The most common tools are working in the reduced pressure range of about 100 Torr for the deposition. The Ge concentration in the SiGe layer is controlled by the GeH4 partial pressure for constant SiH4 partial pressure and temperature (Figure 2.2.10). The incorporation of Ge is impacted by the growth

0.4 Pa 0.24 Pa 0.14 Pa 0.06 Pa

Rate (nm/min)

100

10

EA 1,31 ± 0.01 eV

1 1,65 ± 0.05 eV 1,81 ± 0.08 eV

0.1 1.05

1,90 ± 0.11 eV

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1000/T (K-1)

FIGURE 2.2.9 SiGe deposition rate as function of the reciprocal temperature for different GeH4 partial pressures, constant SiH4 pressure and H2 as carrier gas, and resulting activation energies.

Ge concentration (at.%)

40

30

20 500 C 550 C 600 C 650 C 700 C

10

0 0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

GeH4 /SiH4

FIGURE 2.2.10

Ge concentration in SiGe as a function of the GeH4 to SiH4 ratio for different growth temperatures.

© 2006 by Taylor & Francis Group, LLC

2.2-42

The Silicon Heterostructure Handbook

temperature. The Ge content in the SiGe layer decreases with increasing temperature for constant GeH4 and SiH4 partial pressure. Therefore, for higher Ge content lower growth temperatures have to be applied. Moreover, for SiGe layers with high Ge content grown at high temperature, island growth and relaxation are more likely. In the case of SiGe:C epitaxy the growth temperature is impacting the incorporation of C into SiGe. Lower growth temperatures are beneficial for incorporation of C on substitutional sites. At high growth temperature (and high C content), C tends to be incorporated interstitially degrading the crystalline and electrical properties of the layers.

2.2.5 Summary Today SiGe-strained epitaxy is meeting manufacturing requirements and it is a proven process in microelectronics technology for bipolar (HBT) and CMOS (strained Si) applications. There is still a great potential of SiGe, Si, and Ge layers for future devices and technologies. Despite the fact that strained-layer epitaxy is managed very well using commercially available deposition tools there is room for further improvement, for example, in low-temperature processing and increase in throughput. A very interesting topic for further development of epitaxy is the atomic layer processing approach for atomic level control of doping and deposition [35–37].

Acknowledgment The authors would like to thank the IHP technology team for support and for the preparation of the SiGe–SiGe:C layers and HBT processing.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. R Singh, DL Harame, and MM Oprysko. Silicon Germanium Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 3. S Verdonckt-Vanderbroek, F Crabbe, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe channel heterojunction p-MOSFET’s. IEEE Trans Electron Dev 41:90–101, 1994. 4. T Ghani, M Armstrong, C Auth, M Bost, P Charvat, G Glass, T Hoffmann, K Johnson, C Kenyon, J Klaus, B McIntyre, K Mistry, A Murthy, J Sandford, M Siberstein, S Sivakumar, P Smith, K Zawadzki, S Thompson, and M Bohr. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 978–980. 5. KJ Miller and MJ Grieco. Epitaxial silicon-germanium alloy films on silicon substrates. J Electrochem Soc 109:70–71, 1962. 6. E Kasper and HJ Herzog. Elastic strain and misfit dislocation density in Si0.92Ge0.08 films on silicon substrates. Thin Solid Films 44:357–370, 1977. 7. BS Meyerson. UHV/CVD growth of Si and Si:Ge alloys: Chemistry, physics, and device applications. Proc IEEE 80:1592–1608, 1992. 8. DC Ahlgren, M Gilbert, D Greenberg, SJ Jeng, J Malikowski, D Nguyen-Ngoc, K Schonenberg, K Stein, R Groves, K Walter, G Hueckel, D Colavito, G Freeman, D Sunderland, DL Harame, and B Meyerson. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1996, pp. 859–862. 9. B Tillack, D Bolze, G Fischer, G Kissinger, D Knoll, G Ritter, P Schley, and D Wolansky. SiGe heteroepitaxy for high frequency circuits. MRS Symposium Proceedings, Vol. 525, Rapid Thermal and Integrated Processing VII, 1998, pp. 379–384.

© 2006 by Taylor & Francis Group, LLC

Strained SiGe and Si Epitaxy

2.2-43

10. G Ritter, B Tillack, and D Knoll. Successful preparation of high frequency HBT by integrated RTCVD processes. MRS Symposium Proceedings, Vol. 387, Rapid Thermal and Integrated Processing IV, 1995, pp. 341–346. 11. D Dutartre, P Warren, I Berbezier, and P Perret. Low temperature silicon and Si1xGex epitaxy by rapid thermal chemical vapour deposition using hydrides. Thin Solid Films 222:52–56, 1992. 12. JC Sturm, PV Schwartz, EJ Prinz, and H Manoharan, Growth of Si1xGex by rapid thermal chemical vapor deposition and application to heterojunction bipolar transisitors. J Vac Sci Technol B 9:2011– 2016, 1991. 13. WB de Boer and DJ Meyer. Low temperature chemical vapor deposition of epitaxial Si and SiGe layers at atmospheric pressure. Appl Phys Lett 58:1286–1288, 1991. 14. CA King, JL Hoyt, DB Noble, CM Gronet, JF Gibbons, MP Scott, SS Laderman, TI Kamins, and J Turner. Epitaxial growth of Si1xGex /Si heterostructures by limited reaction processing for minority carrier device applications. MRS Symposium Proceedings, Vol. 146, Rapid Thermal Annealing /Chemical Vapor Deposition and Integrated Processing Symposium, 1989, pp. 71–82. 15. B Heinemann, D Knoll, G Fischer, D Kru¨ger, G Lippert, HJ Osten, H Ru¨cker, W Ro¨pke, P Schley, and B Tillack. Control of steep boron profiles in Si/SiGe heterojunction bipolar transistors. ESSDERC: Proceedings of the 27th European Solid-State Device Research Conference, Stuttgart, 1997, pp. 544–547. 16. HJ Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe heterobipolar transistor performance and process margin. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1997, pp. 803–806. 17. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillack, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 18. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116. 19. JP Dismukes, L Ekstrom, and RI Paff. Lattice parameter and density in germanium–silicon alloys. J Phys Chem 68:3021–3027, 1964. 20. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers. III. Preparation of almost perfect layers. J Cryst Growth 32:265–273, 1976. 21. P Zaumseil. A fast X-ray method to determine Ge content and relaxation of partly relaxed Si1xGex layers on silicon substrates. Phys Stat Sol (a) 141:155–161, 1994. 22. R People, and J Bean. Erratum: calculation of critical layer thickness versus lattice mismatch for GexSi1x /Si strained-layer heterostructures. Appl Phys Lett 49:229, 1986. 23. E Kasper, A Schuh, G Bauer, B Holla¨nder, and H Kibbel. Test of Vegard’s Law in thin epitaxial SiGe layers. J Cryst Growth 157:68–72, 1995. 24. F Berti, D De Salvador, A V Drigo, F Romanato, J Stangl, S Zerlauth, F Scha¨ffler, and G Bauer, Lattice parameter in Si1yCy epilayers: deviation from Vegard’s rule. Appl Phys Lett 72:1602–1604, 1998. 25. JH Van der Merwe. Crystal interfaces. Part II. Finite overgrowth. J Appl Phys 34:123–127, 1963. 26. L Vescan, W Ja¨ger, C Dieker, K Schmidt, A Hartmann, and H Lu¨th, Formation of heterogeneous thickness modulations during epitaxial growth of LPCVD-Si1xGex /Si quantum well structures. MRS Symposium Proceedings, Vol. 263, Mechanism of Heteroepitaxial Growth Symposium, 1992, pp. 23–28. 27. T Stoica and L Vescan. Misfit dislocations in finite lateral size Si1xGex films grown by selective epitaxy. J Cryst Growth 131:32–40, 1993. 28. P Zaumseil. A comparison of different multiple-crystal diffractometer arrangements to measure the reflection curve of SiGe layers on Si substrates. Cryst Res Technol 31:529–537, 1996. 29. P Zaumseil. High resolution determination of the Ge depth profile in SiGe heterobipolar transistor structures by X-ray diffractometry. Phys Stat Sol (a) 165:195–204, 1998.

© 2006 by Taylor & Francis Group, LLC

2.2-44

The Silicon Heterostructure Handbook

30. P Zaumseil, D Kru¨ger, R Kurps, O Fursenko, and P Formanek. Precise measurement of Ge depth profiles in SiGe HBT’s — a comparison of different methods. Solid State Phenomena 95–96:473–482, 2004. 31. P Zaumseil, TA Lafford, and M Taylor. Inline characterization of SiGe structures on 8-inch Si wafers using the Bede QC200 X-ray diffractometer. J Phys D Appl Phys 34:A52–A56, 2001. 32. O Fursenko, J Bauer, P Zaumseil, D Kru¨ger, A Goryachko, Y Yamamoto, K Ko¨pke, and B. Tillack. Spectroscopic ellipsometry for in-line process control of SiGe:C HBT. Proceedings of the Second International SiGe Technology and Device Meeting, ISTDM 2004, Frankfurt(Oder), Germany, 2004, pp. 53–54. 33. D Wolansky, B Tillack, K Blum, KD Bolze, KD Glowatzki, K Ko¨pke, D Kru¨ger, R Kurps, G Ritter, and P Schley. Low temperature clean for Si/SiGe epitaxy for CMOS integration of HBTs. Electrochem Soc Proc 98-1:812–821, 1998. 34. D Wolansky, GG Fischer, D Knoll, D Bolze, B Tillack, P Schley, and Y Yamamoto. Impact of defects on the leakage currents of Si/SiGe/Si heterojunction bipolar transistors. Solid State Phenomena 95–96:249–254, 2004. 35. J Murota, M Sakuraba, and B Tillack. Atomically controlled technology for future Si-based devices. Solid State Phenomena 95–96:607–616, 2004. 36. B Tillack, Y Yamamoto, D Knoll, B Heinemann, P Schley, B Senapati, and D Kru¨ger. High performance SiGe:C HBTs using atomic layer base doping. Appl Surf Sci 224:55–58, 2004. 37. B Tillack, B Heinemann, and D Knoll. Atomic layer doping of SiGe — fundamentals and device applications. Thin Solid Films 369:189–194, 2000.

© 2006 by Taylor & Francis Group, LLC

2.3 Si–SiGe(C) Epitaxy by RTCVD 2.3.1 2.3.2

Introduction................................................................. 2.3-45 Rapid Thermal Chemical Vapor Deposition ............ 2.3-46 Background . Equipments . Process Capabilities Pros and Cons

2.3.3

.

Epitaxy Processes......................................................... 2.3-49 Surface Preparation . Low-Temperature Epi . Germanium Incorporation . Carbon Incorporation . Selective Epitaxy

2.3.4

Epitaxy Integration...................................................... 2.3-63 Thermal Budget Limitation . Loading Effects . Deposition Morphology . Pattern-Induced Defectivity

D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot

2.3.5

Recent Applications..................................................... 2.3-74

ST Microelectronics

2.3.6

Summary ...................................................................... 2.3-80

SEG-Based Bipolar . Double Gate MOS . FD-SOI

2.3.1 Introduction At this time, about 15 to 20 years after a real breakthrough in Si1xGex (SiGe) growth, it is of interest to reflect upon developments and progress made in this field. On the one hand, Si-based alloys, namely Si1xy GexCy (SiGeC), are well known to be key materials for extending the capabilities of the silicon technology that is very dominant in electronics. These alloys, indeed, are fully compatible with this technology and have various characteristics (electronic, chemical, mechanical, and optical) that can be used for a number of proven and potential applications as detailed throughout this book. On the other hand, the development of SiGe growth techniques has been highly competitive, it is probably unique that the deposition of a material was simultaneously studied over the complete pressure domain available, from 108 Torr by molecular beam epitaxy to 760 Torr by chemical vapor deposition (CVD), and using a variety of CVD techniques like ultrahigh vacuum (UHV), very low pressure, low pressure, reduced pressure, atmospheric and plasma-enhanced CVD, chemical beam epitaxy, etc. However, rapid thermal chemical vapor deposition (RTCVD), first invented and developed in homemade tools or in prototypes, made rapid and impressive progresses, especially in low-temperature SiGe epitaxy (epi), and was rapidly introduced in industrial tools. Finally, this technique took the leadership for SiGe epi. Today, one can say that RTCVD and SiGe(C) epitaxy have been married for the better: RTCVD has been demonstrated to be a very effective technique for growing SiGe epitaxial layers and SiGe a powerful booster for RTCVD. Thus, blanket epitaxies of SiGe on full-sheet silicon wafers, and after SiGeC ones, were rapidly demonstrated in pioneer RTCVD studies. However, epitaxial depositions that are required today may

2.3-45 © 2006 by Taylor & Francis Group, LLC

2.3-46

The Silicon Heterostructure Handbook

be much more complex, and have in most cases to be integrated in advanced technologies: i.e., on wafers patterned with very fine structures and with drastic thermal budget limitations. This chapter focuses on the current developments of SiGe and SiGeC epitaxies by RTCVD and their integration in complex technologies. Section 2.3.2 presents the RTCVD technique in terms of equipments and process capabilities for SiGe epi. This technique is also compared to the other important epi techniques and our conclusion at the advantage of RTCVD is in accordance with the success of this technique. Section 2.3.3 details the important points of the Si-based alloy epitaxy: surface preparation, low-temperature epi (LTE), germanium and carbon incorporation, and selective epi. LTE is usually obtained with hydrides like silane- or chlorides-like dichlorosilane (for selective epi). Both systems are considered and surface reactions that are known to play a major role are reviewed. On the other hand, the main features of strained SiGe epi and of carbon incorporation are reported and discussed. Section 2.3.4 is devoted to the integration issues. Among the huge number of possible points, we chose those that are actually met by the process engineer who has to manage epi for the creation of devices in modern technologies. Note that some of these points, pattern-induced defectivity as an example, are not so frequently reported in literature. Finally, Section 2.3.5 illustrates the RTCVD capabilities giving a few examples of current applications developed at STMicroelectronics. As a number of applications will be detailed in following chapters, the selection is very limited: epitaxial base of heterojunction bipolar transistor, epi for gate-all-around MOS and epi on ultrathin silicon on insulator films. Examples were chosen in order to give a certain panorama of applications and of epi issues.

2.3.2 Rapid Thermal Chemical Vapor Deposition Background CVD consists in the deposition of a solid film on a substrate by the reaction of vapor-phase reactants (precursors). The substrate temperature provides the energy to activate the chemical reactions. As illustrated in Figure 2.3.1, the sequential steps of this process are the following: . . . . .

Transport of precursor gas into reactor by forced convection Diffusion to surface and adsorption of precursor molecules on surface Surface reactions (decomposition and recombination) and incorporation into solid film Desorption of by-product molecules and diffusion into the gas phase Evacuation of gaseous by-products from reactor

RTCVD is defined as a CVD technique capable of a rapid switching of the process temperature. This technique is very interesting as the temperature agility allows the thermal budget to be minimized and different films to be grown using different ‘‘adapted’’ temperatures. Gibbons et al. [1] first reported such a technique, and referred it as ‘‘limited reaction processing’’ (LRP); a stable gas flow was established with the wafer at low temperature and deposition was switched on and off by rapidly heating and cooling the

(e) Product evacuation

(a) Precursor transport

(d) Product desorption

(b) Gas diffusion Adsorption

(c) Surface reactions

Nuclei

Growth

Substrate

FIGURE 2.3.1 Generic steps of a CVD process: (a) reactant transport, (b) reactant diffusion, (c) surface reactions, (d) by-product desorption, and (e) by-product evacuation.

© 2006 by Taylor & Francis Group, LLC

2.3-47

Si–SiGe(C) Epitaxy by RTCVD

wafer. This technique was demonstrated to be very effective for some processes, Si epitaxy as an example, but it also presents important drawbacks especially in terms of process control. Thus, the majority of investigators preferred to use gas flow switching rather than temperature to control growth, and then the technique has been more often referred as RTCVD. On the other hand, RTCVD has been found to significantly relax the stringent temperature or cleanliness conditions for epitaxial growth; and within a few years, a considerable amount of research was devoted to the application of this technique to the silicon and SiGe epi. The present contribution will be restricted to these applications.

Equipments Beyond the pioneer work, various reactors were developed and important refinements were introduced: infrared pyrometer for temperature control and loadlock for moisture contamination reduction [2, 3]. Basically, the minimal common features of these systems were: single-wafer susceptor-less configuration, lamp heating, cold walls, and low pressure (a few Torr). Rapidly, using relatively simple tools, very impressive material demonstrations were made in the domain of Si–SiGe epi: high structural quality epi (proved by excitonic emission) [4, 5], functional HBTstructures [6], ultra-abrupt dopant profiles [7], etc. However, in the majority of RTCVD reactors, as a consequence of poor temperature control and gas flow design, the deposition uniformity was not good enough for industrial applications. Around 1990, for the first time a new production epitaxy reactor, the ‘‘Epsilon One’’ from ASM company [8], included some above-mentioned features for RTCVD: single-wafer, lamp heating, loadlock, etc., but it also used a susceptor and substrate rotation for better temperature control and uniformity improvement. More recently, ‘‘Applied Materials’’ also introduced the ‘‘Centura-HTF’’ reactor, which is a similar system. Despite the temperature ramps are slowed down by the presence of a rotating susceptor, in the author’s opinion these tools have been considered as RTCVD epi reactors. The schematics of these modern vapor-phase epitaxy (VPE) systems typically consists of four modules: the process module, the transfer module, the gas control box, and automation. These systems are fully automatic and 25 or 50 wafers can be processed either using a given recipe, in production mode, or various recipes, for research and development (R&D); a variety of process parameters and hardware configurations can also be controlled. The gas distribution system is designed with ultrapurity standards and allows precise gas injection onto the wafer with short (<1 sec) switching transients. The transfer module, preferably at reduced pressure, isolates the process chamber from any atmospheric contamination at each loading or unloading of wafers. These systems process a single wafer at a time in a low-profile, horizontal deposition chamber that is shown schematically in Figure 2.3.2. The chamber walls are made of fused quartz, and air-cooling allows the quartz to remain at moderate temperatures, about half the wafer temperature (in Celsius). Any stainless steel part is outside of the chamber or protected by quartz liners, and is water-cooled,

Quartz wall Radiative emission

Radiative heating

Heat conduction

Process gas flow

Wafer

Ring

Susceptor Rotation

FIGURE 2.3.2 Schematic cross section of a typical RTCVD reactor. The process gases make a single pass over the rotating wafer and susceptor assembly that are heated from top and bottom by tungsten halogen lamps.

© 2006 by Taylor & Francis Group, LLC

2.3-48

The Silicon Heterostructure Handbook

this way any metal corrosion by chloride is minimized. For process, the wafer is placed on a SiC-coated graphite susceptor and both parts are radiantly heated from both sides by external tungsten halogen lamps. The top and bottom heating allow the temperature difference between the wafer and the susceptor to be minimized, then improving control and uniformity of temperature (see ‘‘Low-Temperature Epi’’). In the same way, the radiative heating can be adjusted along the wafer radius to tune the radial uniformity. For control, temperature is measured either by a pyrometer (Applied Materials) or a thermocouple (ASM). A process gas enters from the right of the figure and makes a single pass over the wafer. Finally, the chamber is evacuated by combination of a high-capacity Roots blower with a mechanical dry pump, and processes can be run in a large pressure range (1 to 760 Torr).

Process Capabilities Let us start with temperature agility, the first characteristic of RTCVD. In susceptor-less lamp-heated systems, the time constant, related to the thermal inertia of wafer, like in rapid thermal annealing tools, is in the range 1 to 4 sec. That roughly corresponds to the time of ramp up and down between a process temperature and a temperature significantly lower (a temperature at which the kinetics of important physical mechanisms has decreased by a decade). Unfortunately, the systems with the highest level of development do have a susceptor. In this case, the time constant is less aggressive, between 10 and 30 sec as a function of system and process. This characteristic is nevertheless useful to facilitate and make some processes more effective, including epi. A rapid hydrogen bake is possible, 30 sec at 9008C for example, and the epi temperature can be adapted to the epi deposition or even to the different parts of a complex stack. As seen below, silicon epi requires higher temperatures, as compared to SiGe epi. On the other hand, the temperature control, maybe the most critical point as it is not as perfect as desired, will be discussed in ‘‘Low-Temperature Epi.’’ Considering the chamber design, we believe that the low-profile horizontal geometry is important. In most of the experimental conditions, it induces first a laminar flow beneficial in terms of uniformity and particles, and second a relatively high chemical efficiency as precursor molecules have to pass close to the wafer. On the other hand, the susceptor rotation, with a significant speed (10 to 50 rpm), is useful to smooth temperature variations and to level the flow and depletion of reactants. In addition, as the two industrial tools mentioned present the capability of reduced pressure, the residence time of precursors in chamber can be then reduced by an important (10 to 100) factor. This reduced time, together with a limited hot volume because of the cold walls, will eliminate or minimize the possibility of homogeneous gas-phase nucleation. Thus, it appears that RTCVD is a technique well adapted for the utilization of very reactive precursor gases. Typical processes and some process details will be given in the next section. However, the major advantages of this important technique can be summarized as follows: . . . . . . . . .

Temperature agility Cold walls (at least significantly colder than the substrate) External heater Cleanliness of gases Process flexibility (temperature and pressure range) Chemistry flexibility (hydrides and chlorides) Ability to work in both deposition regimes (surface or mass transport-limited kinetics) In situ chamber cleaning (usually with HCl at high temperature) Mature and industrial technique

as well as the main drawbacks: . . .

Complex temperature uniformity and temperature control Complexity of CVD growth kinetics Productivity of low-temperature and growth rate processes

© 2006 by Taylor & Francis Group, LLC

2.3-49

Si–SiGe(C) Epitaxy by RTCVD TABLE 2.3.1

Performances of Current Epitaxy Techniques for Si and SiGe(C) Applications

Process Capabilities

Technique PECVD (single)

Epi domain Thin films Thick films Temperature domain High T Low T Ultralow T Process domain Surface-limited Mass transport Selective epi (against Si3N4) Crystal quality Low defectivity: particle-induced High chemical purity Process flexibility (P, T, etc.) Memory effect elimination In situ chamber etch Chemistry flexibility Temperature agility (T change) Repeatability Uniformity (all elements) Productivity (>6 w/h) Industrial tool (8/12 in.)

MBE (single)

CBE (single)

UHVCVD (batch)

LPCVD (batch)

RTCVD (single)

Y Y?

Y N

Y N

Y N

Y N

Y Y

N Y Ya

N? Y Ya

N? Y N

N Y N

N Y N

Y Y N

? Y N Y? Y? Y? Some Y? Y Y? N Y? Y? Y Y?

Y? Y N Y Y? N?c Some N N Yd N N N? N N

Y? Y Y? Y Yb Y Some Y? N Y Y? Y Yf N? N

Y N N Y Y? Y Some N? N N Ne Y ? Y N

Y N N? Y Y? Y Some N? N? N Ne Y ? Y Y

Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

?, questionable. a Questionable crystal quality. b Y if H2 bake possible. c Metal contamination often observed [9]. d In terms of atoms or evaporated radicals. e Difficult. f Not proved for any element.

Pros and Cons In order to complete the picture, RTCVD is compared to the other existing techniques in Table 2.3.1. In comparing these pros and cons to those of other techniques, the balance is clearly in favor of RTCVD. That certainly explains the extensive development and success of these equipments. Today, they are sold in large numbers for conventional epitaxies in manufacturing plants, as well as for advanced epitaxies and R&D at major semiconductor suppliers and institutes.

2.3.3 Epitaxy Processes Today, epitaxy technology is facing new challenges, which come from the continuous progress of silicon technology, namely smaller geometries and new epi applications in devices (epitaxial base of HBTs as an example). In addition, as technology and devices, especially CMOS transistors, approach their theoretical limits (optical lithography limit, tunnel current through the gate oxide, etc.), great efforts are made in order to improve or exchange device architecture. For these applications, epitaxial deposition of new materials like Si-based alloys is very desirable, and in most cases it has to be run in the course of device fabrication.

© 2006 by Taylor & Francis Group, LLC

2.3-50

The Silicon Heterostructure Handbook

Most of the well-established epi processes in production today are carried out by CVD with a silicon precursor diluted in hydrogen; they are run in the very front end of technology at high temperatures (1000 to 11008C). However, as soon as a substantial amount of the device is present on the wafer and strained or metastable materials are concerned, conventional epitaxy processes with high thermal budgets can no longer be used. This section presents and discusses the important issues that are specific to Si and SiGeC processes required by new epi applications and new devices in Si technology.

Surface Preparation Epitaxy essence is that the growing material forms a monocrystal that prolongs the substrate lattice. That is to say that the presence of an amorphous film on the surface cannot be tolerated; the typical example is the native oxide that naturally exists on silicon substrates. In the same way, to achieve high-quality epi, it is essential to remove any particles and contamination from the substrate surface prior deposition initiation. Contaminants would prevent surface migration of silicon atoms and form precipitates, generating lattice defects. Thus, the perfection of the epitaxial growth on silicon substrates relies critically upon the surface preparation, and all the following conditions are required: . . . .

No oxide on the surface A good crystal quality (etching or implant may have been used in previous operations) No precipitates of dopant or other impurities No surface contamination or particles

In conventional epi processes carried out at high temperature, the silicon surface preparation relies on both a wet ex situ clean and an in situ hydrogen bake. The ex situ clean generally consists of an RCA cleaning procedure [10] that eliminates particles, native oxide, organics, metal and carbon, and repassivates the reactive silicon surface with a thin (0.6 nm) layer of suboxide that is hydrophilic, stable, not highly reactive and relatively easily removed in situ. The substrate is then submitted to a hightemperature hydrogen bake (above 10008C) to remove the RCA-regrown oxide before epi deposition. It is admitted that this oxide is reduced via the two following reactions: SiO2 (solid) þ Si(solid) ! 2SiO(gas)

(2:3:1)

SiO2 (solid) þ H2 (gas) ! SiO(gas) þ H2 O(gas)

(2:3:2)

Since reaction (2.3.1) is very effective each time a silicon–oxide interface is in direct contact with vapor and the RCA oxide is somewhat porous, the author supposes that it is the most effective in the case of pre-epi bake. The hydrogen bake that is also capable to anneal eventual crystal imperfections, to dissolve or diffuse eventual high dopant concentrations or contamination, and to dissolve or evaporate most of small particles is very beneficial to the epi. Thus, this combination of ex situ and in situ cleanups, usually carried out on ‘‘full-sheet’’ silicon wafer, is very effective in producing high-quality epi. In the domain of LTE, there are two very different situations. In a first situation, epitaxy has to be run at low temperature because metastable films (strained, SiGeC, etc.) or sharp dopant profiles have to be created, but the substrate is resistant enough to high temperatures. This corresponds to processes placed at the very front end of the technology, or used for R&D structures basically deposited on full-sheet wafers. In this case, a conventional surface preparation is used and very low defect densities (a few defects per wafer) are achieved. In a second situation, which is more frequent, as sensitive structures are already present, the substrate cannot withstand high temperatures. In this case, the strategy of surface preparation has to be changed. Indeed, at moderate temperatures (below 9008C), reactions (2.3.1) and (2.3.2) responsible for the oxide reduction are not effective enough to remove the superficial oxide. It is admitted that a 6-A˚ thick chemical oxide as prepared by RCA

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-51

cleaning requires a hydrogen bake above 10008C to be fully removed and to leave a perfectly clean surface suited for high-quality epi. The best solution would be to use etch processes, carried out directly in the epitaxy chamber or in an clustered annex, that would remove effectively the chemical oxide at low temperatures. Various treatments have been proposed. Low-energy plasmas (hydrogen, argon, etc.) have been investigated. Encouraging results have been obtained but these solutions were not developed at an industrial level [11]. However, as the interest for low thermal budgets becomes stronger and stronger these treatments may come back on the scene. Vapor-phase HF cleaning has also been developed and more or less integrated in epi tools. However, this chemistry presents some difficulties: the oxide etch rate from anhydrous HFbased process is unstable and the process control difficult, and maybe more tricky is the fact that hydrocarbons on the oxide surface block the adsorption of the species that are required for etching [12]. All these new chemistries, carried out in prototype reactors, are not yet common. Consequently, most researchers today adopt a strategy based on the more conventional ‘‘HF-last’’ clean. The HF bath removes the oxide from the wafer surface and passivates the silicon surface with atomic hydrogen. The UHV/CVD growth process reported by Meyerson is based on such a HF-last clean [13]. Originally, the wafers were etched in diluted HF just prior to loading, without any water rinse. However, this procedure presents two major difficulties: (i) transport and manipulation of the wafers coming from HF acid without any rinse are very critical and (ii) removal of the residual HF is very difficult when hydrophilic patterns are present on the wafer surface. Because of these difficulties, a possible and more widely used surface preparation procedure is: RCA clean þ HF last þ water rinse þ IPA dry þ loading in the epi tool þ in situ hydrogen bake (8008C to 9008C for about 1 min). Of course, a wet clean using an ‘‘in situ’’ rinse, made by displacing an extremely diluted HF solution with DI water in the same tank, is recommended because it eliminates the transfer of hydrophobic wafers from the HF to the DI-water bath. On the other hand, clustering this precleaning with the epitaxy tool would also be preferable [14]. In the author’s opinion, this type of surface preparation allows high-quality epitaxies to be grown: typically, no oxygen or carbon is visible by SIMS at the interface (detection limit around 1 1012 atoms/ cm2), and defect densities are in the range of 0.1 to 10 defects /cm2 (light point defect > 0.16 mm), depending on precise experimental conditions. Such low values measured on silicon full-sheets are also expected on patterned wafers. On the other hand, some operations, such as dry-etch or implant, can cause the silicon at the surface and in the subsurface region to be highly defective and not compatible with a high-quality epitaxial growth. In these cases, the processes of these operations require modifications in order to respect the crystalline quality of the silicon (for example, by adding a soft-etch step to an etch recipe), or a sacrificial oxide, typically 10 to 20 nm thick, can be grown (and removed) for damage removal before epitaxy.

Low-Temperature Epi Silicon epi can be deposited using SiCl4 (sil tet), SiHCl3 (TCS), SiH2Cl2 (DCS), SiH4, Si2H6, or even Si3H8 as precursors. Growth rate (GR) depends on several parameters: reactor geometry, temperature, gas source, flow rate, deposition pressure, and concentrations. According to the gas source, for similar conditions it is admitted that the deposition kinetics increases when Cl atoms are reduced and Si atoms increased in the molecule, namely from SiCl4 to Si3H8. However, as the reactivity increases, the stability decreases, and these molecules are increasingly subject to thermal decomposition and gas-phase nucleation. Thus, hydrides have to be used at lower temperatures and smaller partial pressures, as compared to chlorides. Thus, as a function of their properties, each precursor is attractive for particular film specifications and deposition conditions; today, chlorides are used for thick epi at high temperature, usually above 10008C, and hydrides for thin epi at lower temperatures, below 9008C. In pioneer RTCVD reports, DCS [15], silane [16], and to a less extent disilane [17] were studied for low-temperature applications. As an illustration, Figure 2.3.3 reports the Arrhenius plots of Si growth rate obtained with DCS and silane. First, we note that each system exhibits two deposition regimes.

© 2006 by Taylor & Francis Group, LLC

2.3-52

The Silicon Heterostructure Handbook

Growth rate (A/min)

10,000

Ea = 2.1 eV 1000

100 Ea = 3 eV

SiH4 SiH2Cl2 10 7.5

8

8.5

9 9.5 10,000/T (K−1)

10

10.5

11

FIGURE 2.3.3 Arrhenius plot for silicon growth rate from silane and dichlorosilane in similar conditions. In the low-temperature domain, silane chemistry presents a smaller activation energy and a much higher kinetics compared to dichlorosilane.

At high temperatures, the growth rate is almost insensitive to temperature and, in most cases, is controlled by precursor gas-phase mass transport. At low temperatures, the growth rate is strongly dependent on temperature, and the variation is attributed to a thermally activated process. As this process is supposed to take place on the wafer surface, this domain is often referred to as ‘‘surface ratelimited.’’ Second, as the curves correspond to deposition carried out in a given reactor and with similar conditions of gas flow, we conclude that the silane deposition kinetics is much faster than that of DCS, and with a smaller activation energy. The advantage of silane corresponds to more than one decade in terms of growth rate, or 100 K in temperature, and to a less temperature-sensitive process. These significant changes will enable the process to be more easily controlled and the thermal budget, which could be capital in some applications, to be reduced. As a consequence, DCS is often used for selective depositions because Cl atoms help at selectivity, as discussed in ‘‘Selective Epitaxy’’ but today silane is preferred and has been adopted for most of the nonselective epitaxies. Considering the epi kinetics from silane at low temperature, the Arrhenius plot given in Figure 2.3.3 reveals an exponential dependence of GR with an activation energy of about 46 kcal /mol, which is in accordance with the majority of values reported in the literature for various experimental conditions [16, 18–20]. This value also accords very well with the activation energy for hydrogen desorption from a Sih1 0 0i surface (47 kcal /mol) [21]. Thus, growth kinetics is supposed to be correlated with equilibrium hydrogen surface coverage as depicted in Figure 2.3.4: the reactive adsorption of silane molecules produces adsorbed hydrogen atoms whose desorption is not immediate; this hydrogen surface coverage regulates further SiH4 adsorption [18]. Consequently, hydrogen desorption is the mechanism that limits the growth rate (via silane adsorption), which is ultimately independent of silane pressure. Initially developed in a domain of very low pressure, this model was then applied in a number of experiments. It was also further refined; for example, taking the adsorption of molecular hydrogen quantitatively into account [16]. Finally, these calculations agree extremely well with experimental data covering a wide range of pressures and temperatures, suggesting a high level of understanding in the growth kinetics of silicon epitaxy using silane. A simplified form of reaction pathway can be written as

© 2006 by Taylor & Francis Group, LLC

SiH4 þ 2 ! Si þ 2H þ H2

(2:3:3)

H* þ H ! H2 þ 2

(2:3:4)

H2 þ 2 ! 2H

(2:3:5)

2.3-53

Si–SiGe(C) Epitaxy by RTCVD

SiH4

H

H2

H

H

H

H

Si

H

H2 H

H

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

FIGURE 2.3.4 Schematic of low-temperature silane-based epitaxy. Silane molecules are supposed to adsorb on two Si sites leaving two adsorbed H atoms that passivate the surface. Growth kinetic corresponds then to the balance between silane adsorption and hydrogen desorption.

where _ denotes a site that is available for adsorption, X a specie that is adsorbed, H* corresponds to an excited state of hydrogen (following Ref. [21] hydrogen desorption is first-order relative to atomic adsorbed hydrogen) and no difference is made between the Si on surface and in bulk. On the other hand, there are some precautions to be taken when using silane. First, the presence of impurities in the gas phase, even at very small concentrations, will not be purged in a compressed gas (silane) in the same way they are in a liquid (DCS). Second, the low stability of silane molecules makes it susceptible to gas-phase nucleation of particles, which can ‘‘rain down’’ and become incorporated in the growing film. However, this limitation is not so severe since silane is chosen for thin epi and low processing temperatures. In conclusion, it should be noted that this hydrogen coverage of the silicon surface during lowtemperature growth is of considerable importance. It will control or directly influence a number of epitaxy characteristics such as: dopant incorporation, film morphology, differential poly or mono growth, and the structural quality of epitaxy, etc. The author also considers this phenomenon, which has an important surfactant-like effect, to be the main differentiation between CVD and MBE techniques (to the advantage of CVD).

Germanium Incorporation Solid Si and Ge have both the diamond crystal structure, and they form a solid solution that is almost ideal (negligible mixing enthalpy) and stable in the entire composition domain. These SixGe1x alloys have a lattice parameter that varies almost linearly with the Ge content from 5.431 A˚ (aSi) to 5.667 A˚ (aGe) when described by the diamond cubic lattice: aSi1x Gex ¼ aSi þ x(aGe aSi )

(2:3:6)

At the same time, the incorporation of Ge in the Si lattice leads to a significant bandgap narrowing. This bandgap narrowing is of interest for the creation of devices based on bandgap variations or energy band offsets. Thus, SiGe alloys opened the way of bandgap engineering and strained heterostructures to the silicon technology. On a more general point of view, SiGe alloys present a variety of properties and characteristics that can be used in silicon technology. One can list: bandgap variations, band offsets, dopant diffusion reduction, chemical properties (selective etching), dopant activation improvement, strain management, optical properties, etc. SiGe epitaxies receive then an impressive attention for all their possible applications. Effect on Kinetics In RTCVD, SiGe alloys are deposited using either DCS, SiH4, Si2H6, or even Si3H8 as the Si precursor and almost exclusively GeH4 as the Ge precursor. Like in Si epitaxy, and for the same reasons, it is admitted that the deposition kinetics increases from DCS to Si3H8. And these precursors with different

© 2006 by Taylor & Francis Group, LLC

2.3-54

The Silicon Heterostructure Handbook

reactivities give rise to a variety of epi domains. Thus, SiH4 is the standard gas for NSEG and DCS for SEG. The disilane and, more recently, the trisilane are considered for very low thermal budget applications [22]. The GeH4 molecule that exists as a compressed gas, stable enough (more than 1 year in a cylinder), and reactive enough to allow significant (>10 nm /min) deposition kinetics at low temperature (below 5008C) [12] is really convenient for epi via CVD. GeH4, even expensive, is then commercially available and widely used in industry. As a consequence, other molecules as GeCl4 did not receive much attention up to now. In terms of kinetics, the main characteristic of SiGe alloy deposition is the dramatic increase of growth rate, as compared to pure silicon. This effect is illustrated in Figure 2.3.2 where the kinetics of SiGe and Si depositions from SiH4–GeH4–H2 chemistry at reduced pressure have been plotted as Arrhenius plots. In the low-temperature domain (5508C to 7508C) the SiGe deposition is thermally activated, with kinetics much higher than that of Si, about one decade around 6008C, and much lower apparent activation energy. At this point, one has to note that the SiGe kinetics reported in Figure 2.3.5 corresponds to a fixed germane /silane ratio but not to a constant solid composition. Indeed, increasing the temperature while fixing the germane and silane partial pressures causes a decrease in the Ge content of the alloy. In such a case, the kinetics limitation cannot be considered as a single and simple mechanism, and then the curve does not strictly correspond to an Arrhenius law. As it will provide some important ‘‘keys’’ for the epi engineer, it is interesting to look little more closely at this kinetics enhancement. In gas phase, germane is supposed to behave like silane, and to undergo a similar reactive adsorption on two neighboring sites (same notations as Equations (2.3.3) to (2.3.5)) GeH4 þ 2 ! Ge þ 2H þ H2

(2:3:7)

In fact GeH4 molecules are much more reactive than SiH4molecules, and Equation (2.3.7) is more rapid and corresponds to a higher (5) ‘‘sticking’’ coefficient as compared to Equation (2.3.3). This results in a deposition that is much more Ge-rich than the gas mixture. As soon as Ge atoms are incorporated in solid, they act as preferential desorption sites for H atoms. This comes from the fact that Ge H bonds are less robust than those of Si H (smaller binding energy). In case of SiGe deposition, Equation (2.3.4) is then more rapid and less limiting for the subsequent deposition as compared to silicon case. Note also that the easy H desorption from Ge is consistent with the very small activation energy of the Ge deposition kinetics reported in Ref. [12]. Other mechanisms like sticking coefficient variations, Ge

GR (A/min)

1050 10,000

900

T (⬚C) 800

700

600

Si0.88Ge0.12

1000

100 Si

10 7.5

8.5

9.5 10.5 10,000/T (K−1)

11.5

FIGURE 2.3.5 Pseudo-Arrhenius plot for SiGe growth rate from silane–germane–hydrogen compared to Si growth rate obtained in similar conditions. In the low-temperature domain, SiGe deposition presents a smaller apparent energy of activation and a much higher kinetics compared to silicon.

© 2006 by Taylor & Francis Group, LLC

2.3-55

300 nm

Si–SiGe(C) Epitaxy by RTCVD

105 3 µm

FIGURE 2.3.6 undulations.

Stranski–Krastanov growth mode in SiGe–Si epitaxy observed by AFM. Note the h1 0 0i-aligned

segregation, H-atom site exchanges (from Si to Ge), etc. may also take place but are not essential to get a good picture of SiGe deposition. Strain Effects Because of the lattice parameter variation given in Equation (2.3.6), SiGe epitaxies that are grown pseudomorphically on silicon substrates exhibit a large biaxial compressive stress (negative strain). The mechanical energy of these films increases (as the product thickness *x 2Ge ), and if critical values of xGe and thickness are exceeded, the film quality can be degraded by Stranski–Krastanov (SK) growth or misfit dislocations. Figure 2.3.6 illustrates the surface morphology specific to the SK growth mode. This mode exhibits quasiperiodic undulations that grow exponentially with time–film thickness, and very rapidly with 6 8 –xGe function of the stress–xGe; very simple models demonstrate that their amplitude has to grow as xGe model simplifications. These surface undulations are generated without any extended crystalline defects like dislocations or stacking faults, and are aligned along the two h1 0 0i directions on a (0 0 1) Si surface. It is a kind of elastic relaxation: the top of the undulations has released a part of its stress and the mechanical energy of the system has been reduced. The plastic relaxation corresponds to the nucleation and propagation of misfit dislocations. As illustrated in the Figure 2.3.7 (top view), misfit dislocations are easily identified as they usually glide in {1 1 1} crystalline planes. They usually lie near the SiGe–Si interface and allow the above-lying SiGe film to be relaxed. However, since the dislocation core corresponds to some excess energy, dislocations can extend only when the relaxation gain is larger than the dislocation loss. This energy balance corresponds to the well-known critical thickness for stability against dislocation formation due to the lattice mismatch. For a single Si0.80Ge0.20 layer (without any silicon capping layer), the equilibrium critical thickness is less than 20 nm. Films with thickness smaller than this value are stable; films with larger thickness are metastable, relaxation can occur if they are exposed to high temperatures, especially if efficient dislocation sources are present in the film. The relative severity of the two relaxation mechanisms depends on the nature of the film (xGe) and experimental conditions of deposition (temperature and chemistry). However, for both mechanisms, the lower the temperature, the larger the xGe–thickness process window. At this point, it is important to note that the dramatic kinetics increase induced by the Ge incorporation allows keeping a certain process window against these mechanisms: the growth of Ge-rich films requires lower temperatures, and lower temperatures can be used owing to the Ge-catalyzed kinetics.

© 2006 by Taylor & Francis Group, LLC

2.3-56

The Silicon Heterostructure Handbook

FIGURE 2.3.7 Top view of misfit dislocations observed by optical microscopy after chemical decoration.

Carbon Incorporation Background Solid carbon presents different crystalline structures: diamond, graphite, etc. And even if the diamond structure is similar to that of silicon, the lattice parameter presents a large size offset, aSi /adiamond ¼ 1.52. On the other hand, according to the SiC phase diagram, there is a compound that is very stable, stochiometric SiC, and the carbon solubility in solid silicon is very low, a few 1017 atoms /cm3 at melting temperature. Consequently, the incorporation of carbon in Si or SiGe crystal is more complex than that of germanium in Si, and its incorporation in substitutional sites is by nature a nonequilibrium process. However, it was demonstrated that, by using low-temperature (<6508C) depositions, it is possible to incorporate significant amounts (percent range) of substitutional carbon in silicon lattice [23] to form metastable Si1yCy and Si1xyGexCy epitaxies. The incorporation of carbon in silicon and SiGe layers was first investigated to extend the capabilities of the SiGe system. Indeed, in the previous section, pseudomorphic SiGe layers on Si were found to have fortuitous properties that made them very successful. They however suffer from significant limitations. First, the concept of critical thickness is not really compatible with applications that would require thick nondislocated SiGe layers on silicon, for light emission or detection as examples. Second, almost the entire bandgap offset was reported in the valence band, the SiGe–Si structures do not exhibit any significant conduction band offset and electron modulation is impossible in simple structures. In the case of substitutional carbon incorporation, the lattice parameter of SiGeC material can be estimated using the following equation: aSi1xy Gex Cy ¼ aSi þ x(aGe aSi ) þ y(aC aSi )

(2:3:8)

Equation (2.3.8) is a first estimation, and nonlinear variations may have to be taken into account. Nevertheless, it shows that the incorporation of C atoms, smaller than Si, can serve to reduce or even eliminate the strain in SiGe layers. Calculations as well as experiments show that carbon atom roughly compensates for about ten germanium atoms. It means that if x /y ratio is fixed at this value the ternary layer is perfectly matched to the silicon, and the critical thickness is no more a limitation. Carbon incorporation is also of particular interest as it leads to significant conduction-band offset and to strain effects that are reverse to the Ge-induced ones.

© 2006 by Taylor & Francis Group, LLC

2.3-57

Si–SiGe(C) Epitaxy by RTCVD

On the other hand, the presence of substitutional carbon atoms at relatively low concentrations, as low as 0.1%, has been found to dramatically reduce both diffusion and transient-enhanced diffusion of impurities like boron in Si and SiGe [24]. This fortuitous effect is widely used to fabricate highly borondoped bipolar bases that are very thin. Note that this effect could or should be used in CMOS transistor for channel doping or shallow junction control as well. Incorporation Kinetics In RTCVD, the most common chemistry used for SiGeC epitaxy is SiH4–GeH4–SiCH6 diluted in H2 at reduced pressure. Other carbon precursors like C2H4 were also found to be effective, to a less extent, in producing substitutional carbon incorporation [25], but single alkanes like CH4 that seem to not decompose the right way are not well suited for this application. Other silicon sources like disilane or trisilane seem attractive, but they are not currently used because of some difficulties such as cost, molecule stability, liquid source control, etc., as compared to silane. Figure 2.3.8 presents an example of carbon incorporation in Si and SiGe layers [26]. The total carbon concentration [Ctot] measured by SIMS is given as a function of the methylsilane (MS)/silane flow ratio for a variety of process conditions like different silane flows, Ge contents, and deposition temperatures. Note that the gas flow ratio corresponds to the flows through the mass flow controllers and do not correspond exactly to the partial pressures above the wafer surface. One observes that all the experimental points roughly follow a proportional variation with the gas flow ratio. This proportionality in a large experimental domain suggests that MS would undergo a surface-sorption similar to that of silane that requires two adjacent available sites (see Equation (2.3.3)). The fact that the carbon concentration in solid is smaller than the gas ratio also suggests that MS would have a sticking coefficient slightly smaller than silane. Note that it has also been reported that the carbon incorporation increases when the total pressure is decreased and when the temperature is increased [12]. Such trends that are opposite to the germane behavior are also expected from a molecule with a smaller sticking coefficient (germane coefficient is higher). On the other hand, contrarily to the effect of germane, the presence of MS partial pressure does not have significant effect on the deposition kinetics; accurate measurements allowed us to detect only a small growth rate reduction and a negligible xGe variations in the experimental conditions explored [26]. Nature of Incorporation Contrarily to Ge, and for the basic reasons given above, carbon atoms are not necessarily incorporated in substitutional sites. They can easily form interstitial complexes or even react with silicon to form stochiometric SiC precipitates.

[C total]/[Si] (%)

3

2

1 620⬚C 680⬚C 0 0

0.02

0.04

0.06

MS/silane (%)

FIGURE 2.3.8 Total carbon incorporation as a function of the methylsilane–silane flow ratio for a variety of process conditions: different silane flows, germanium contents, and deposition temperatures.

© 2006 by Taylor & Francis Group, LLC

2.3-58

The Silicon Heterostructure Handbook

Intensity (cps)

For a long time, carbon contamination on a silicon wafer surface has been known to cause a large defectivity in epi. Indeed, at high temperature, during the hydrogen bake for example, carbon atoms form nanoprecipitates of SiC that induce dislocations or stacking faults. For the same reason, highquality SiGeC epitaxies require relatively low deposition temperatures (well below 9008C): too high temperatures would allow the carbon precursor to react with the silicon surface to form SiC nuclei. In addition, even if such SiC precipitates are not formed, there is still an important challenge, that is to incorporate the carbon in substitutional sites; i.e., to avoid or minimize the incorporation of carbon in interstitial sites, as well as the formation of interstitial complexes or any other microdefects. Substitutional carbon concentration can be easily quantified from its influence on the lattice parameter. Figure 2.3.9 shows the typical X-ray diffraction (XRD) rocking curves from pseudomorphic SiGeC grown on Si (1 0 0). The present diagrams correspond to layers grown with increasing MS/silane gas ratios, all other conditions being constant. The angular shift between the Si substrate peak and the SiGeC layer peak is a direct measure of the lattice mismatch of the epitaxy. And, as the presence of MS in the gas phase does not induce significant changes in Si and Ge deposition kinetics, the shift is directly related to the content of substitutional carbon. In the present case, we observe that the compressive stress induced by a Ge content of 14% is reduced by carbon incorporation in substitutional sites, or even eliminated when the C content is around 1.5%. In the same way, similar incorporation of carbon in pure silicon would have induced important tensile stresses. The crystalline perfection of SiGeC epitaxies is an important concern in a number of applications. The experimental domain where high-quality epitaxies can be achieved is then of great interest, it has to be determined and optimized. As a first approach, XRD is a convenient, and routinely used, technique to determine the crystal quality of pseudomorphic layers on silicon. This way, the maximal carbon incorporation in terms of crystal quality has been explored as a function of temperature and germanium content, and the results obtained at 6208C and 6808C are given as examples in Figure 2.3.10a and b, respectively. In the figure, high-quality epitaxies (closed symbols) and poor-quality epitaxies (open symbols) are represented in the plane (xc, xGe); the quality criterion being the discrepancy between measured XRD diagram and theoretical simulations (a significant broadening of the main SiGeC peak or the disappearance of the higher order oscillations). At each temperature, there are two domains, a ‘‘good quality’’ one at the bottom left and a ‘‘poor quality’’ one at the top right. It is observed that, for given experimental conditions, there is a maximal carbon concentration beyond which the epitaxial quality is not maintained, and this maximal limit is found to be reduced as the xGe is increased. The comparison of the two figures also indicates that the good-quality domain is enlarged by a temperature reduction. In other words, the lower the temperature, the larger the process window. Such a trend is also valid in other techniques like MBE and in various experimental conditions. 1⫻107

0% Ctotal

1⫻106

0.1% Ctotal

1⫻105

0.15% Ctotal 0.3% Ctotal

1⫻104

0.6% Ctotal 1⫻103

0.9% Ctotal

1⫻102

1.2% Ctotal

1⫻101

1.5% Ctotal

1 0

500

1000

1500

2000

2500

3000

Diffraction angle offset (arcsec)

FIGURE 2.3.9 X-ray rocking curves from pseudomorphic SiGeC grown on Si (1 0 0). Diagrams correspond to layers with a fixed Ge content (about 14%) and C contents increasing from 0% to 1.5%. They show the reduction of the lattice parameter induced by substitutional carbon incorporation.

© 2006 by Taylor & Francis Group, LLC

2.3-59

Si–SiGe(C) Epitaxy by RTCVD

Total carbon (%)

3 Bad quality

620⬚C Good quality

2

1

0 0

10

20

30

XGe (%)

(a)

Total carbon (%)

3 Bad quality 2 Good quality 1 680⬚C 0 0

10

(b)

20 XGe (%)

30

FIGURE 2.3.10 Quality of SiGeC epitaxies deposited by RTCVD as a function of germanium and carbon contents: (a) 6208C and (b) 6808C. Low temperatures lead to larger process windows in term of carbon incorporation.

1.2

680⬚C, XGe = 6% 680⬚C, XGe = 9% 680⬚C, XGe = 13% 620⬚C, XGe = 13% 620⬚C, XGe = 31%

Csub/Ctotal

1 0.8 0.6 0.4 0.2 0 0.000

0.010

0.020

0.030

0.040

Ctotal (%)

FIGURE 2.3.11 Proportion of substitutional carbon as a function of the carbon content in SiGeC epi grown at 6808C and 6208C.

Another important challenge of SiGeC epitaxy is how to minimize the number of interstitial atoms and to incorporate all carbon atoms in substitutional sites. The presence of interstitial atoms is indeed not desirable as they are admitted to induce detrimental effects in a number of material characteristics like minority carrier lifetime, mobility, and maybe impurity diffusion, etc. It is then crucial to know the variation of the Csubtitutional /Ctotal ratio as a function of the main growth parameters such as growth temperature, partial pressures, etc. The most important trends are illustrated in Figure 2.3.11 that gives the evolution of the ratio in RTCVD epitaxies as a function of the total carbon incorporation, and for different temperatures and different germanium contents. The substitutional carbon was deduced from XRD measurement and total concentration from SIMS. It is observed that whatever the temperature, the

© 2006 by Taylor & Francis Group, LLC

2.3-60

The Silicon Heterostructure Handbook

ratio of substitutional carbon decreases with increasing total carbon incorporation, and that the substitutional carbon increases with decreasing deposition temperature and with decreasing Ge content. All these trends are well admitted and have been qualitatively reported for different techniques. They have even been modeled in the case of MBE with simple first-order kinetics of thermally activated interstitial incorporation [27]. However, if we compare the present results with MBE results, we note an important difference. In MBE, substitutional incorporation requires deposition temperatures below 5508C, 4508C preferred, whereas in RTCVD, a significant substitutional ratio is obtained with temperatures as high as 6808C to 7008C. In the opinion of the author, this dramatic change has to be attributed to the presence of an important hydrogen surface coverage that blocks the movement of carbon atoms or eventually improves the stability of the substitutional position. One has also to note that such a crucial role of surface coverage, sometimes referred as a surfactant-like effect, is consistent with all the trends reported above.

Selective Epitaxy Selective epitaxial growth (SEG) is very desirable because, as a fully self-aligned process, it leads to fully self-aligned device architectures that are simpler, or even to novel device structures (see Section 2.3.4). By essence, SEG has to be run on patterned wafers, and the epi characteristics depend on the process and on the precise nature of the patterned wafers as well. Namely, we can list: epitaxy perfection, selectivity limit, thickness and doping in the different windows, and exact morphology of deposition (mainly faceting at the edge of deposition). As a consequence, in addition to complex process developments, SEG process may also present important integration problems, and some of them are discussed in Section 2.3.3. The concept of SEG is based on the fact that silicon has to undergo a nucleation step before deposition over a dielectric and not over silicon. This nucleation step corresponds to a certain amount of energy, and the barrier is large enough to produce selective deposition if the process is well chosen. Various SEG processes have been published via RTCVD, but the most common ones are based on the DCS–HCl–H2 chemistry. Apart from the DCS choice, the addition of a certain flow of HCl is generally required to totally inhibit any deposition on the dielectric, especially when using Si3N4 and utilizing an industrial reactor working at pressures exceeding a few Torr. As such, DCS-based epitaxy and DCS–HCl-based SEG are presented below. DCS chemistry is widely used in conventional epitaxy and has been studied for SiGe deposition at low temperature. As such, experimental data on kinetics are available in literature, however the modeling and understanding of this process is not as clear as for silane. Following the Arrhenius plot of the DCS–H2 epitaxy kinetics given in Figure 2.3.3, for temperature of interest here (<8508C) deposition is kinetically limited. Although they are supposedly predominant, surface reactions are still uncertain. It is supposed that DCS molecules adsorb directly on the silicon surface and undergo a reactive dissociation into Si, H, and Cl, and that these species can desorb, depending on the temperature, as H2, HCl, or SiCl2. A simplified form of the reaction pathway proposed first by Coon et al. [27] may be written as follows: SiH2 Cl2 þ 4 ! Si þ 2H þ 2Cl

(2:3:9)

H* þ H ! H2 þ 2

(2:3:4)

H þ Cl ! HCl þ 2

(2:3:10)

2Cl ! Cl2 þ 2

(2:3:11)

Si þ 2Cl ! SiCl2 þ 2

(2:3:12)

(same notations as Equation (2.3.3) to Equation (2.3.5)). However, as epi is often performed in hydrogen ambient, and as hydrogen is known to increase the GR of silicon compared to Ar, N2, or He, we prefer to include its influence with the following reaction suggested in [28]:

© 2006 by Taylor & Francis Group, LLC

2.3-61

Si–SiGe(C) Epitaxy by RTCVD

2Cl þ H2 ! 2HCl þ 2

(2:3:13)

The apparent activation energy of DCS–H2 kinetics given in Figure 2.3.3 is about 70 kcal /mol; a value very similar to the activation energies of the desorption reactions (2.3.10) and (2.3.13) that are supposed to be the limiting steps. Kinetics limitations in DCS–H2 system are reported in Figure 4 of Ref. [29]. Silicon growth rate has been plotted as a function of DCS flow (or partial pressure) for different temperatures, all other parameters being constant. For low DCS flows, GR is proportional to the flow, but above a given flow, GR exhibits a very clear saturation indicating that reactions (2.3.10) and (2.3.13) would be very effective. At 7508C, for example, GR is roughly constant (about 13 nm /min) for DCS pressures exceeding 0.05 Torr. Thus, the surface coverage would regulate DCS adsorption and growth rate. And based on Hierlemann calculations [27], chlorine coverage would dominate in most of the experimental conditions, bringing about an important variation as compared to silane chemistry. Silicon SEG based on DCS–HCl–H2 chemistry has given rise to a large amount of work, but SEG is a complex process with a number of parameters (any comparison is very difficult as experimental conditions are different); no (or almost no) conclusive attempts have been made to relate the SEG process to the underlying surface reaction physics. Reactions (2.3.9) to (2.3.13) are still valid but a significant HCl adsorption, with reactions reverse to reactions (2.3.10) and (2.3.13), has to be taken into account. And consequently, the growth rate is depressed because of an increased Cl surface coverage, and reaction (2.3.12) is much more effective in removing Si adatoms from the dielectric surface, compared to the DCS–H2 chemistry. A perfect selectivity against dielectrics like SiO2 or Si3N4 can be then obtained in the DCS–HCl–H2 system by HCl flow adjustment. This is illustrated in Figure 2.3.12, where the nucleus density on full-sheet Si3N4 CVD films on 200 mm wafers has been plotted as a function of the HCl flow. Deposition process was carried out in a commercial epitaxy reactor, and nuclei were measured with an optical inspection tool that enables the full wafer to be scanned. We observe a relatively abrupt selectivity threshold (a 10% variation in HCl flow changes the level of defects by 2 to 3 decades) and a very high degree of selectivity (not published to the author’s knowledge) as nucleus densities or defectivity lower than 0.1/cm2 are measured. To conclude the silicon SEG part, and as discussed in Ref. [29], we can draw the following general rule: the HCl flow requested to obtain full selectivity has to be increased with any of the following parameters: DCS flow (but the ratio DCS–HCl can be decreased), temperature, pressure, doping level (boron), and Si coverage. Germanium and carbon can be incorporated in selective epi via the addition of GeH4 and MS in the previous chemistry.

Nucleus density (cm−2)

100 H2 /DCS/HCl chemistry T = 850⬚C 10

1

0.1 0

100

200

300

HCl flow (sccm)

FIGURE 2.3.12 Selectivity threshold of silicon deposition on CVD Si3N4. The nucleus density was measured as light point defects using a Surfscan that allows the entire 200 mm wafer to be inspected. In the present conditions, a perfect selectivity is obtained when using 140 sccm of HCl and more. Note that the points located on the bottom and top axes correspond to densities below 0.1 and above 100 LPD/cm2.

© 2006 by Taylor & Francis Group, LLC

2.3-62

The Silicon Heterostructure Handbook

In terms of kinetics, the main characteristic of SiGe alloy deposition is the dramatic increase of growth rate, as compared to pure silicon. As for hydrogen, it is supposed that the much lower Cl Ge binding energy, as compared to Cl Si, facilitates the Cl desorption and allows much more rapid kinetics. Note that a part of this kinetic enhancement may also come from a chemical reduction of DCS radicals by atomic hydrogen that is produced by GeH4 decomposition. However, up to now, these mechanisms were not properly modeled. Indeed, the kinetics, already not so simple for pure Si, becomes much more complex, especially in the low-temperature domain where a number of surface reactions should be taken into account. On the other hand, as xGe (new parameter) has a high influence on kinetics, the deposition domain becomes very extended and the number of experiments to explore it very huge. As an example of SiGe SEG kinetic, Figure 2.3.13 gives the variations of GR and germanium content as functions of the DCS partial pressure, all other conditions being constant. We observe that when the GeH4 /DCS gas ratio is reduced by a factor of 5 via a DCS increase, the germanium content roughly decreases from 25% to 20% and the GR decreases from 17.5 to 11 nm /sec. In other words, the germanium content follows a really nonlinear variation, and the GR variation is opposite to the main active gas (DCS) partial pressure change: dependencies that are not straightforward for xGe or even counterintuitive for the GR. In terms of selectivity, the germanium incorporation plays a very positive role. It is observed that SiGe deposition is much more selective as compared to pure silicon. Whatever the dielectric, SiO2 or Si3N4, the Ge-rich epi, the more selective. Different possible explanations were proposed in literature, but none of them is really convincing. In the opinion of the author, this increased selectivity would come from the interface–surface energies larger for SiGe and then less favorable to nucleation, as compared to Si (this is still under experimentation). Indeed, a larger SiO2–SiGe interfacial energy (and to a less extent a larger SiGe surface energy) would induce a much higher nucleation barrier and then would lead to an easier intrinsic selectivity. On the other hand, substitutional carbon incorporation in chloride chemistry is more delicate as this incorporation requires low temperatures and chloride kinetics higher deposition temperatures, as compared to silane. However, some interesting compromises do exist as selective SiGeC epi were already reported in the literature [30, 31]. In both cases, the depositions allowed to fabricate high-performance HBTs, and this point will be illustrated in Section 2.3.5.

50

200

HCl = 0 sccm

HCl = 0 sccm HCl = 40 sccm

120 80

HCl = 80 sccm

30 20 10

40 0

HCl = 40 sccm

40

HCl = 80 sccm XGe (%)

Growth rate (A/min)

160

0 0

0.01

0.02

0.03

DCS pressure (Torr)

0.04

0.05

0

0.01

0.02

0.03

0.04

0.05

DCS pressure (Torr)

FIGURE 2.3.13 SiGe SEG kinetics as a function of the DCS partial pressure (flow). Note that the nonlinear variation of xGe and the counterintuitive variation of GR that decreases with increasing active gas (DCS) flows.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-63

2.3.4 Epitaxy Integration Compared to standard high-temperature blanket epi, new epi processes are facing new challenges. Some difficulties come from the properties of the epitaxial layer that has to be deposited: metastable-strained layers (SiGe), nonstable materials (substitutional carbon), etc. and have been discussed previously. Others difficulties come from the device application requirements, and from integration in modern technologies. On one hand, new devices like the base of HBTs require very complex stacks that correspond up to 8 to 18 parameters that have to be controlled. In addition, as the base is an active part of the device that is very critical, it has to be well controlled. On the other hand, as a part of the devices is already present, the global thermal budget of epi is strictly limited and the epi has to be run on patterned wafers. Today, new (established or potential) applications are very numerous, and all of them are not precisely specified. Thus, it is difficult to detail all possible issues in an exhaustive way. However, the major ones can be tentatively listed as: . . . . . . . . . . . . . . . . .

Very limited thermal budget (H2 bake) Low deposition temperature (complex kinetics and structural quality problem) Abrupt dopant profiles (at the nanometer scale) Strained epitaxies: SiGe, SiGeC Metastable materials: SiGeC Different doping types and levels Cleaning of structured substrates Deposition on structured substrates (very different as compared to prime Si wafers) Epitaxy in presence of various materials: TEOS, Si3N4, SiO2, poly or amorphous silicon, etc. Epitaxy in very complex structures Epitaxy after etching and implant steps Selective epitaxy: Si, SiGe, SiGeC, etc. Control of facets or poly–epitaxy interfaces Local or global loading effects (LE) Complex film stacks Differential epi or poly growth rate Control of poly roughness in nonselective epitaxy

In the following, we discuss some general difficulties that are present in LTE by RTCVD for new applications, namely, thermal budget limitation, LE, deposition morphology, and pattern-induced defectivity.

Thermal Budget Limitation As a very general approach, one could consider that the thermal budget has to be reduced at each technology node according to the design size reduction and to the gradients required. Based on the boron diffusion that is a limitative mechanism in a number of applications, the thermal budget reduction from one technology node to the next one can be estimated to 158C to 208C (Dboron /2 or diffusion length 0.7). This rule holds for established epi applications that would follow a constant integration scheme. For a new application, the thermal limitation can be even more demanding and severe. As there is no reference, any request is possible; the general trend being the more advanced the technology and the later (in the process flow) the epi integration, the lower the allowed thermal budget. This way, in most recent applications we had to move from the ‘‘RCA þ high-temperature H2 bake’’ clean strategy to the ‘‘HF-last þ moderate-temperature H2 bake’’. Taking the bipolar transistor that is demanding in terms of epi quality as an example, collectors (buried layers) are grown with the first strategy for decades, whereas the more recent epitaxial bases of HBTs are generally deposited using the second one. Note also that in some

© 2006 by Taylor & Francis Group, LLC

2.3-64

The Silicon Heterostructure Handbook

cases, the process flow, and then the device architecture, has to be designed taking into account for epi limitations. In the case of HBTs in BiCMOS, the epi base is usually run before CMOS S/D implantation. This way a significant thermal budget can be used to optimize the surface cleaning and epitaxial deposition perfection. In some other applications like the deposition of elevated S/D in the most advanced CMOS or SOICMOS technologies (65 to 45 nm node and below), as a function of the process flow we may have to go to the ‘‘HF-last þ low-temperature H2 bake’’ strategy. For very demanding applications, even the deposition temperature has to be reduced and SiGe depositions may be preferred to silicon epi because of their much higher kinetics. As an example, hydride chemistry at 6008C with fixed conditions gives typical GR of 1, 10, and 50 nm /min for germanium contents of 0%, 13%, and 26%, respectively. Thus, SiGe depositions can be considered for industrial applications, with significant throughputs, at temperatures much lower than 6008C. In such a case of thermal budget reduction, we have to keep in mind that, as stated previously, the surface cleaning may be not efficient enough, and any surface imperfection can induce important epi defectivity. Indeed, any particle or precipitate will not be eliminated and can be the source of crystalline defects, especially in strained epi. Figure 2.3.14 gives an example of such a high defectivity observed in Si–SiGe epi deposited with a low thermal budget. The image of the epitaxial zone (800 800 mm2) has been obtained by room temperature photoluminescence [32]: dark areas outside the box are due to polycrystal deposition, and dislocations randomly appear in the box as dark lines and points. In this case, a poor surface preparation associated with a low-temperature H2 bake has left a high density of defects such as particles or precipitates that have induced crystalline defects and misfit dislocations. On the other hand, the deposition temperature reduction may also affect the quality of the epitaxy. Indeed, as soon as the partial pressure of active gases is increased and the temperature decreased, minority carrier transport and photoluminescence properties are usually affected, supposedly because of punctual defects. At the limit, if the deposition conditions are pushed further, we may even cross the amorphous or crystalline deposition transition. As a conclusion, the epi process that determines the film quality has to be chosen in proper accordance with the application requirements. And, as an example, epitaxial bases of HBT and elevated S/D of CMOS with different requirements probably should have to be deposited with different conditions.

FIGURE 2.3.14 Room temperature photoluminescence image of a Si–SiGe epitaxial structure. Dark areas outside the box are due to polycrystal deposition, and dislocations appear in box as dark lines or points. The important defect density is due to an improper surface preparation associated with a low-temperature H2 bake.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-65

Loading Effects In RTCVD, the growth rate of Si (or SiGeC) in the active areas of patterned wafer usually depends on the pattern. Differences that are observed by changing the absolute size of exposed silicon areas on a given substrate are referred to as ‘‘local loading.’’ Differences from one wafer to the other, due to the total exposed silicon surface or to any other wafer change, is referred to as ‘‘global loading.’’ It means that a fixed process recipe (chemistry, temperature target, pressure, etc.) does give different depositions on different substrates or in different locations. These LE are an important difficulty in industrial applications where epi depositions have to be precisely (specifications smaller than a few percentages) controlled in any devices and on any wafer. On the other hand, as a function of the root cause of these differences, temperature variations or chemical changes (most probably in the gas-phase composition), one usually classifies the effects as ‘‘thermal’’ LE or ‘‘chemical’’ LE. At the origin, LE referred almost exclusively to thickness variations found in Si SEG as these ones were strong and easily detected. Such a view is, however, too restrictive and has to be enlarged: the LE concept is valid, and has to be considered, for the incorporation of any element that is present in deposit. This way, LE may affect thickness but also other parameters like germanium content, carbon incorporation, and dopant level. In addition, as it is not yet reported in literature, it is important to note here that LE may also induce growth rates and dopant incorporations that are not constant within the film thickness. Thermal Loading In existing RTCVD epi tool, the wafer rests on a SiC-coated graphite susceptor and both pieces are lampheated inside a cold-wall chamber possibly under low hydrogen pressure. As temperature measurements on wafers with patterns and complex film stacks are very delicate, only the susceptor temperature is used to control the process. However, in such equipment, which do not follow the blackbody emission, the actual temperature of an object is a function of its absorptance or emissivity. As a consequence, the wafer temperature T does not match exactly the susceptor temperature Tsusc, and a temperature offset DT can be written as [29]: 4 3 K2 (Tsusc 298)]=(8«sTsusc þ K1 þ K2 ) DT ¼ [«lamp P «sTsusc

(2:3:14)

where DT ¼ T Tsusc, «lamp is the emissivity of wafer corresponding to the lamp wavelengths, P, the radiative power density from lamps, «, the silicon emissivity corresponding to its own emission, K1, the constant of heat conduction between the wafer and the susceptor backside, K2, the conduction coupling between the wafer and the chamber, and the other letters have their usual meaning. Note that susceptor 3 , and emissivity was taken to unity. In practical cases, we have relations : K1 >> K2 and K1 >> 8«sTsusc Equation (2.3.14) can then be simplified as 4 K2 (Tsusc 298)]=K1 DT ¼ [«lamp P «sTsusc

ð2:3:15Þ

During epi process, Tsusc is well controlled and can be considered as constant and repeatable. However, as DT is not necessarily equal to zero, Equation (2.3.14) and Equation (2.3.15) establish that, in a general way, the precise temperature of process T varies with wafer emissivity, top and bottom lamp power repartition (via P), susceptor design and gas conductivity (via K1). Note that, in equipments, which use thermocouple placed at the susceptor bottom for temperature control, the situation is even worse as an additional temperature offset, between susceptor and thermocouple, is introduced. As a consequence, a fixed process (chemistry, temperature target, pressure, etc.) does not give the same deposition on different substrates. Figure 2.3.15 gives the SiGe growth kinetics as a function of the germane gas flow, measured on blanket Si wafers and on typical product wafers. The comparison shows clearly that growth rate is lower when using structured substrates compared to full-sheet wafers. Basically, this change can be attributed to two different causes: a global ‘‘thermal’’ LE or a global ‘‘chemical’’ LE. The actual causes of the GR

© 2006 by Taylor & Francis Group, LLC

2.3-66

The Silicon Heterostructure Handbook

1500

25

Fullsheet Patterned

1000 15 Fullsheet Patterned

XGe

GR (A/min)

20

10 500 5 0

0

0 0.02

0.04 0.06 GeH4/SiH4

0.08

0

0.02

0.04 0.06 GeH4/SiH4

0.08

FIGURE 2.3.15 SiGe growth kinetics as a function of the germane–silane flow ratio for silicon full-sheet and device wafers. In the present conditions, growth rate variations are mainly due to thermal loading effects.

variations presented in Figure 2.3.15 have been studied in detail [33]. In these specific conditions, it was clearly established that: .

.

Silicon deposition did not present any significant chemical LE and the observed GR variation is due to the thermal effect (about 68C). SiGe growth did present both a thermal LE (to the same extent in Celsius than the silicon one), and a chemical LE that is smaller.

The present results are specific to the conditions used for deposition. Nevertheless, they demonstrate that, in a general way, the deposition on device wafers is different from an eventual calibration using full-sheet wafers. Because of the presence of polycrystalline silicon on field oxide, the emissivity of product wafers is significantly smaller than that of blanket wafers, and the first term of Equation (2.3.14) and Equation (2.3.15) is decreased more significantly than the second one. Thus, the wafer temperature is decreased as compared to prime wafers, in agreement with the result of Figure 2.3.15. Note that the thermal LE are supposed to vary during deposition as wafer emissivity varies with the poly thickness. Finally, despite severe simplifications made, Equation (2.3.14) and Equation (2.3.15) explain perfectly how the actual process temperature varies with the wafer optical properties, giving rise to the thermal LE. On the other hand, thermal LE reported in Figure 2.3.15 correspond to global effects. However, local thermal LE play a certain role each time that important surface emissivity nonuniformities are present on the wafer at large lateral scales (greater than a few mm); any lateral thermal gradient at smaller scales is effectively smoothed by the high thermal conductivity of the silicon substrate. It is also interesting to note that thermal LE, illustrated here for NSEG, are operative for any process, and that LE reported for SEG as chemical LE usually are in fact a mix between thermal and chemical effects. Chemical Loading Chemical LE, often referred as ‘‘loading effects,’’ are reported for a long time in silicon SEG. They are, however, almost not modeled even in the case of pure silicon deposition, as the kinetics with DCS–HCl– H2 chemistry is not perfectly understood. Because of the additional parameters, namely the silicon surface coverage and the size of the windows, complex variations may be found as a function of silicon coverage or HCl partial pressure (see as an example Figure 10 of Ref. [29]). Indeed, in different experimental conditions, LE may present opposite variations, a behavior attributed to the fact that the kinetics is dominated by DCS or HCl molecules.

© 2006 by Taylor & Francis Group, LLC

2.3-67

Si–SiGe(C) Epitaxy by RTCVD

T (⬚C) 700 650

750

600

650

600

30

1000

25 Ge content (%)

Growth rate (A/min)

T (⬚C) 700

750

100

10

1 9.5

Si area = 1% Si area = 23% Si area = 100% 10.0

10.5 11.0 10,000/T (K−1)

20 15 10 5

11.5

0 9.5

Si area = 1% Si area = 23% Si area = 100% 10.0

10.5 10,000/T

11.0

11.5

(K−1)

FIGURE 2.3.16 Global loading effect in DCS–GeH4–HCl–H2-based SiGe SEG. Growth rates are plotted as a function of reciprocal temperature for wafers with silicon coverages of 1%, 23%, and 100%.

In the case of SiGe or SiGeC deposition, the situation is even more complex as the deposition domain is enlarged very much by the addition of parameters (germane or MS partial pressures). Figure 2.3.16 gives the growth rate of SiGe SEG as a function of reciprocal temperature on wafers with different silicon coverages. The DCS–GeH4–HCl–H2 chemistry was used and the deposition conditions were chosen close to the selectivity threshold. In such a case, the kinetics and LE are dominated by DCS and germane (and not HCl), and we observe that whatever the deposition temperature, the smaller the silicon coverage, the higher the growth rate. In the same way, we also observed that the smaller the silicon coverage, the higher the Ge content. In these experiments, special care has been taken in order to eliminate any thermal contribution of the different patterned or blanket wafers resulting from the optical properties of wafers and the results only report the actual chemical LE [34]. The present interpretation is that the germane depletion (that increases with the silicon coverage) with the subsequent Ge content reduction is the main cause for the significant GR decrease (a factor of 3 to 4). Note at this point that a more important global LE would be expected with smaller Ge contents as the relative germane depletion would increase and as the kinetics would be more sensitive to xGe. Local LE are also observed in these deposition conditions. Figure 2.3.17 gives the growth rate and Ge content of SiGe SEG as a function of the silicon window area [34]. We observe that the smaller the window, the higher the growth rate and the Ge content. In the same way as for global LE, a local germane depletion would induce locally both the GR and xGe decreases. We also note that for smaller and smaller silicon windows, the GR and xGe seem to saturate. This trend has been confirmed by SEM cross sections where no significant offset was found between submicron and larger windows. It means that optical measurements carried out in windows as large as several tens of microns are representative of epi in submicron devices. At this point, we have to note that the results are reported as a function of the window area. However, this parameter is fundamental only for isolated windows, and in a more general design all the surrounding patterns will play a role and have to be taken into account. In this section, chemical LE were presented in the case of SiGe SEG. For the sake of simplicity, we have presented simple variations that are obtained in an experimental domain properly chosen. However, we have to keep in mind that the volume of the experimental domain, with a number of parameters, is huge, and that more complex variations of global and local LE are usually found in larger or not wellchosen domains. On the other hand, even if often neglected, NSEG also present chemical LE that can be important. As an example, boron doping presents both local and global LE in Si or SiGe epi as a consequence of an important ‘‘differential’’ incorporation (a ratio of 2) between polycrystalline and epitaxial deposition.

© 2006 by Taylor & Francis Group, LLC

2.3-68

The Silicon Heterostructure Handbook

140

36

120

32

80 60

30 GR-650⬚C

40

%Ge-650⬚C

Ge content (%)

Growth rate (A/min)

34 100

28

20 0 10

100

1000

10,000

100,000

26 1,000,000

Si window area (µm2)

FIGURE 2.3.17 Local loading effect in DCS–GeH4–HCl–H2-based SiGe SEG. Growth rate and Ge content are plotted as a function of the silicon window area (silicon coverage of wafer was about 1% of the total surface).

Deposition Morphology The epi morphology of blanket depositions can be usually described in a simple way: thickness being usually the unique parameter. Only in a few cases, when exhibiting a Stranski–Krastanov growth mode for example, a more complete description is required. On patterned wafer, the situation is different and epitaxial films always present a morphology that is more or less complex. This point is illustrated in the following. In SEG, LE can induce depositions that vary from one epi window to the other, or from the window edge to the center; these effects were discussed previously. On the other hand, facets that are well-known problems are usually observed. They come in the form of flat surfaces that correspond to certain atomic plans. They are caused by the important variations of the growth rate as a function of crystal orientation. Indeed, dense atomic planes like {1 1 1}, {3 1 1}, {1 1 0}, etc., which may present significant nucleation barriers, exhibit slower GR as compared to {1 0 0}, and become apparent in convex-growing zones just like in a Wulf construction. In fact, facets do not correspond to a minimization of the crystal energy but are rather the crystal response, dominated by kinetics effects, to a certain environment. As a consequence, their development depends on several dominant factors that are: . . . . .

Structure conformation: orientations of dielectric edge and surface, etc. Nature of dielectric: SiO2, Si3N4, etc. Crystal orientation: {1 0 0} Si wafers are usual Nature of deposition (Si, SiGe, etc.) Process conditions (T, P, gas flows, etc.)

These factors can be combined to give rise to a huge number of different possibilities. All of them cannot be detailed or discussed here, and only the effects of the process conditions and of deposit nature will be illustrated in the following. Figure 2.3.18 illustrates the influence of temperature on the morphology of silicon SEG grown between SiO2 walls. In both cases, epi was carried out by RTCVD using the SiH2Cl2–HCl–H2 chemistry. SiGe markers were introduced in epi and chemically decorated for X-SEM observation in order to analyze the growth surface evolution. These markers were chosen thin and with a low Ge content in order to minimize their influence on the growth. On the left picture (Si epi at 8508C) we observe very clear {3 1 1} facets, defined by an angle of 25.28 with the (0 0 1) plane, that appear at the beginning of the growth. Such experiments also allow to estimate a growth rate ratio between {3 1 1} and {1 0 0} planes of

© 2006 by Taylor & Francis Group, LLC

2.3-69

Si–SiGe(C) Epitaxy by RTCVD

SiO2 Mono Si 400nm

(a)

SiO2

Mono Si

200nm

(b)

FIGURE 2.3.18 SEM cross sections of Si SEG grown at 8508C (a) and 7508C (b) with the SiH2Cl2–HCl–H2 chemistry and between SiO2 walls. Thin SiGe markers were introduced and chemically etched (dark) in order to visualize the growth surface evolution.

about 0.53, close to the values reported in the literature. On the contrary, no facet can be detected inside the oxide walls on the right picture that corresponds to a Si epi at 7508C. In our opinion, faceting is eliminated because the growth rate ratio (between {3 1 1} and {1 0 0} planes) is significantly increased (as a consequence of the different activation energies), and may be also because of the dramatic surface diffusion decrease due to the lower temperature and the subsequent Cl surface coverage. Figure 2.3.19 shows the morphology of SiGe SEG grown at 7508C in conditions similar to those of Figure 2.3.18 except that germane was added. In this case, Si markers (bright on the picture) were used to visualize to growth morphology. Compared to the silicon growth, SiGe behaves differently. Two systems of facets are clearly visible: the h1 0 0i growth is bordered by {3 1 1} facets, and {1 1 1} facets are present alongside the SiO2 walls. By an important temperature reduction, the authors were able to avoid first (T around 6508C) the {3 1 1} planes and further (T around 6008C) the {1 1 1} ones [35]. In another way, from these conditions it is also possible to delay the facet formation by modifying the surrounding environment and the condition process [35, 36]. As an example, with the integration of nitride instead of oxide and with HCl partial pressure reduction, facets do not appear at the beginning of the growth but after 1000 A˚ or more. In such a case, for applications that are based on films thinner than that, faceting would be no more an issue. When NSEG is carried out on patterned wafers, a technique also referred as ‘‘differential deposition,’’ polycrystalline material is grown on top of dielectric (or polysilicon if present) and epi is grown on the

© 2006 by Taylor & Francis Group, LLC

2.3-70

The Silicon Heterostructure Handbook

monocrystalline Si regions. In this case, in addition to the epi thickness, a number of parameters like the thickness of poly, its nature (grain size and texture), roughness, and the shape or orientation of the poly or mono interface are of interest. Indeed, the poly deposition very often plays a role in the structure and its characteristics have to be taken into account for the application. As an example, in the most common HBT structure that is based on NSEG, the Si–SiGeC poly is a part of the extrinsic base and some of its properties (resistivity, thickness, proclivity to form salicide, etc.) are crucial for the device performances. The poly–epi thickness ratio is an important parameter of a differential deposition. Indeed, once the epi characteristics (thickness, dopant profiles, etc.) are chosen, usually in accordance with the device performances, this ratio determines the thickness of the simultaneously deposited poly. The variation of this poly–epi ratio is given as a function of the deposition temperature for the SiH4–H2 chemistry and given experimental conditions in Figure 2.3.20 [37]. We observe that the ratio as high as 2.4 in the lowtemperature domain decreases down to values close to 1. This variation is supposed to be correlated with the deposition structure that transits from an amorphous nature to a crystalline one. It means that, for a fixed epitaxial structure, the poly thickness (and structure) can be adjusted within a certain domain by a proper choice of deposition conditions.

100%

2.6

80%

2.2

60% 1.8 40% 20%

1.4

Amo content

Poly/epi GR ratio

Amorphous content

FIGURE 2.3.19 SEM cross section of SiGe SEG grown at 7508C with SiH2Cl2–GeH4–HCl–H2 chemistry and between SiO2 walls. Thin Si markers were introduced and chemically decorated (bright) in order to visualize the growth surface evolution.

Growth rate ratio

0% 570

1 620

670 T (⬚C)

720

FIGURE 2.3.20 ‘‘Poly’’–epi growth rate ratio and amorphous content in ‘‘poly’’ as a function of growth temperature. ‘‘Differential deposition’’ was carried out on Si–SiO2 patterns by RTCVD and with the SiH4–H2 chemistry.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-71

On the other hand, we also believe that this ratio plays an important role in the morphology or orientation of the poly–epi interface. When the poly or amo growth rate is much higher than that of epi, the poly growth will push the poly–epi interface toward the epi region to produce a very inclined interface. This interface usually looks like a facet, and in some cases it may correspond or be very close to well-defined facets like the {3 1 1} ones. When the ratio is around 1, the development of the two parts will be more balanced and the interface will be more vertical (perpendicular to the surface). As an illustration, Figure 2.3.21 gives two very different developments of poly–epi interface. At low temperature, with a large growth rate ratio, the poly–epi interface is indeed very inclined. At a higher temperature, the interface is less inclined. And with optimized conditions at 8208C, the interface is almost vertical (not reported here). Between the two extreme conditions (5908C and 8208C), the rule would be: the higher the ratio, the more inclined the poly–epi interface. At this point, we have to note that among the different characteristics of the differential deposition, we preferred to discuss this poly–epi interface orientation because it is a very important characteristic although almost never reported in literature, and also because we are convinced it is somewhat related to the previously discussed faceting effect observed in SEG.

FIGURE 2.3.21 SEM cross sections of silicon NSEG (differential deposition) grown at 5908C (left) and 7208C (right) with SiH4–H2 chemistry (PSiH4 ¼ 0.85 Torr). Dark lines correspond to thin Si0.9Ge0.1 markers submitted to a chemical decoration.

© 2006 by Taylor & Francis Group, LLC

2.3-72

The Silicon Heterostructure Handbook

Pattern-Induced Defectivity As compared to full-sheet, patterns can generate additional epi defectivity via several mechanisms: . . . . .

Possible outgassing from the different materials present on the surface Growth surface can be forced in nonfavorable planes, {3 1 1}, {1 1 1}, etc. Stress field induced by dielectric patterns (STI, etc.) Presence of edges (facets or poly–epi interfaces) causing local shear stress Presence of edges as effective sources of defects

Let us review briefly these points, and note that they may be effective at the same time. As materials and dielectrics present on the surface are deposited increasingly at low temperatures, one may get a significant outgassing of species, like H2O from TEOS films for example, that are capable of oxidizing the silicon surface (during the moderate temperature bake or temperature stabilization) and to induce crystalline defects. This mechanism is even supposed to be more severe in batch systems where the outgassing surface is larger and time longer, and especially in UHVCVD system because the silicon surface may be more sensitive, as compared to single-wafer systems. On the other hand, in some configurations, the epitaxial growth may have to progress via low-kinetics crystalline orientations. As an example, if high aspect-ratio trenches have to be filled on a h1 0 0 i wafer, the epi may have to grow via facets, {3 1 1} or {1 1 1} as a function of the material or conditions (see Figure 2.3.18 and Figure 2.3.19). In such a case, crystalline defects like stacking fault, etc., or even polycrystalline deposition are more easily generated, at least in nonoptimized deposition conditions. These two first points are met in any epi, for pure silicon, for SiGeC alloys as for any other semiconductor materials as well. On the contrary, the two last mechanisms of the list are more specific to strained epi like SiGe or SiGeC on silicon. Indeed, as explained previously, in strained epi there is a strong tendency to relax the mechanical energy of the film by generation and development of misfit dislocations. This behavior has been extensively studied in SiGe–Si blanket wafers and has led to the concept of critical thickness. This concept is twofold. There is the critical thickness that borders the stability domain, a domain that corresponds to the balance between the energy required to extend a misfit segment and the mechanical energy saved by this extension. In practice, one can grow strained epi beyond this limit, and another critical thickness is often defined as the limit of the metastable domain. Note that this limit is not unique and depends on the epi process, especially on the thermal budget. In this domain, it is well established that once nucleated, one misfit is capable to extend on long distances, i.e., the wafer size in some cases. However, there is still one point that is not so clear: where and how the misfit dislocations are generated? In high-quality epi, defects that are not present cannot be supposed to nucleate dislocations, and then wafer edges that are more defective and that present shear stress are supposed to play a major role. In Gerich epi, dislocation loops generations, possibly favored by a SK growth if any, may occur. In the case of patterned wafers, the situation is dramatically changed. Patterns are necessarily associated with edges that correspond to poly–epi interfaces in case of NSEG or to facets in case of SEG, and in both cases the edges will play an important role in dislocation generation. As an example, Figure 2.3.22 gives a photoluminescence image of a Si–SiGe NSEG measured in a 800 800 mm2 window. The Ge content is 22% and the thickness is well above the critical thickness. We observe that all the dislocations (propagating along {1 1 0} directions) are connected to the pattern boundary. Our interpretation is that all dislocations were generated at the epi–poly interface and the poly has then to be considered as an efficient misfit source. As a consequence, in case of NSEG the critical thickness corresponding to the metastable domain is reduced on patterned wafers as compared to full-sheets. It also means that, for a given thickness, patterns will increase the probability to a higher extent to find a misfit in a given epi surface. In SEG, the epi edges certainly also play an important role. However, as their nature is fundamentally different as compared to NSEG, a different behavior can be expected. The NSEG–SEG comparison in terms of misfit dislocation apparition and stress relaxation has been done in certain RTCVD conditions [38]. Figure 2.3.23 reports the density of misfit dislocations for both types of deposition as a function of the film thickness and that summarizes the results. It appears that a significant dislocation density

© 2006 by Taylor & Francis Group, LLC

2.3-73

Si–SiGe(C) Epitaxy by RTCVD

Misfit dislocation

FIGURE 2.3.22 Polycrystal-induced misfit dislocations in SiGe epi observed by room temperature photoluminescence (box area ¼ 800 800 mm2).

Dislocations density (cm−1)

1⫻104

1⫻103

1⫻102

1⫻101

SEG NSEG

1⫻100

0

1000

2000

3000 Thickness (Å)

4000

5000

6000

FIGURE 2.3.23 Dislocation density observed in SiGe layers as a function of epi thickness: comparison between NSEG and SEG. Despite a higher deposition temperature, SEG is more robust than NSEG against misfit dislocations.

(50 dislocations/cm) is obtained for <100 nm in case of NSEG and for about 400 nm in case of SEG. Thus, despite a higher deposition temperature (by about 1008C), SEG is much more robust that NSEG in terms of misfit dislocation generation and plastic relaxation. This dramatic change can be attributed to the different morphology that would give rise to a smaller shear stress (as a consequence of faceting?) and to the absence of poly that would be a dislocation source. This way, SEG is generally observed to provide much larger critical thickness as compared to NSEG. At this point, we have to note that the third point of the list (stress field in substrate) can also play a role in the dislocation appearance, and that it is often mixed with the two last ones in practical applications. However, in the experiments reported above, both epi types were carried out on similar structures and the variations observed have to be attributed then only to the nature of the border, facet or poly. On the other hand, misfit dislocations can also nucleate and propagate during the subsequent operations of the technology as soon as crystalline defects, additional stress or thermal budget are provided. And SEG is expected to be more resistant also against this relaxation.

© 2006 by Taylor & Francis Group, LLC

2.3-74

The Silicon Heterostructure Handbook

2.3.5 Recent Applications At this point, it is interesting to illustrate the possibilities of SiGeC epi by RTCVD with the description of some actual applications of RTCVD. It should help the reader in keeping in mind where and how LTE can be used in practice in electronics. However, as this section contributes to a material chapter, it will be very short. A more complete discussion can be found in Ref. [29]. On the other hand, a number of applications will be detailed in the following chapters. For these reasons, we chose to briefly present only three recent applications we worked on.

SEG-Based Bipolar SiGe LTE has become an accepted technique for the fabrication of the bipolar bases. Initially, HBT technologies were based on SiGe NSEG whereby the epi grown on single-crystal regions forms the intrinsic base and a part of extrinsic base, and the polycrystal deposited on top of dielectric forms a part of the base electrode. More recently, SiGeC was substituted to SiGe for the base formation in order to block boron diffusion during the subsequent thermal budgets. As an illustration of this boron-blocking effect, Figure 2.3.24 reports the SIMS boron profiles of different samples before and after annealing (10008C for 30 sec). Samples were grown with a 10-nm thick boron-doped layer and with different carbon contents, keeping all the other growth parameters constant. The sample measured as-deposited (e) is for control and for SIMS transfer function estimation, and the sample of pure SiGe, without C, measured after annealing (a) gives a reference for diffusion. As compared to pure SiGe, there is dramatically less diffusion in SiGeC samples: in the present conditions the higher the C concentration, the lower the B diffusion. This way, npn HBTs with thinner bases and higher performances have been developed and integrated in complex technologies. And today, all major semiconductor companies already offer a collection of SiGeC-based BiCMOS technologies (see Chapter 3). In addition to carbon incorporation, fully self-aligned (FSA) emitter–base structures are a further step toward high performances. SEG, well suited for the fabrication of a FSA-emitter–base structure [39], has been studied for a long time at STMicroelectronics, first with SiGe epi and more recently with SiGeC [30]. Figure 2.3.25 shows a TEM cross section of such a self-aligned SEG-based SiGeC HBT. The SiGeC epi was grown by RTCVD in a commercially available reactor (Applied Material Centuray), and, in the

1⫻1020

[B] (at/cm3)

1⫻1019

1⫻1018 (b) (a) 1⫻1017

(e) (d) (c) (a) [C] = 0 (b) [C] = C1 (c) [C] = 2*C1 (d) [C] = 4*C1 (e) As-dep

1⫻1016

1⫻1015 0

50 Depth (nm)

100

FIGURE 2.3.24 Boron SIMS profiles after a 30 sec annealing at 10008C in different SiGeC films.

© 2006 by Taylor & Francis Group, LLC

2.3-75

Si–SiGe(C) Epitaxy by RTCVD

FIGURE 2.3.25 TEM cross section of a SiGeC SEG-based HBT.

1⫻10−2

Ic

1⫻10−4

(b)

1⫻10−6

Ib, Ic (A)

Ib

(a) Non-ideal I b

1⫻10−8 1⫻10−10 (a)

1⫻10−12 0

(b) 0.5 Vbe (V)

1

FIGURE 2.3.26 Gummel characteristics of a SiGeC SEG-based HBT: (a) before and (b) after epi optimization.

picture, we note the absence of defects in the base, a smooth epi, and a good link between the epi and the polycrystal. The main difficulty of SiGeC SEG comes from the higher thermal budget, as compared to NSEG. Indeed, if carbon is introduced in too large contents or in improper conditions, significant amounts of carbon atoms will be incorporated in nonsubstitutional sites (interstitial, clusters, etc.) and the epitaxial base will then have poor electronic properties. The first detrimental effect usually detected is an excess base current due to increased recombination. This effect is illustrated by Figure 2.3.26, which reports HBT Gummel plots before and after selective SiGeC epi optimization. When using nonoptimized epi process, the base current at low levels deviates very much from its ideal variation: interstitial carbons or SiC clusters induce more recombination, especially if they are present in the depleted emitter–base region [30]. On the other hand, base current below 1011 A /mm2 at Vbe ¼ 0.5 V can be achieved with optimized base epitaxy. High-frequency measurements of HBT are another way to characterize our SiGeC SEG process in terms of boron diffusion, as well as to test the validity of the FSA structure in terms of parasitics.

© 2006 by Taylor & Francis Group, LLC

2.3-76

The Silicon Heterostructure Handbook

217.2 217.2 215.8 219.3

Min 206.6

FIGURE 2.3.27

219.0 213.5 208.8 209.5 210.1 210.6

207.6 215.4 213.2 207.9 209.3 209.3 209.8 213.3 Max 220.0

212.3 215.5 212.6 209.0 207.5 209.3 208.5 213.5

214.5 217.8 208.4 206.6 207.7 208.3 210.7 212.5 Mean 212.1

218.7 215.5 206.7 206.8 208.7 211.8

220.0 215.8 212.3 213.1

Stdev 3.9

fT cartography (GHz) of a 0.17 3.6 mm2 bipolar at VCB ¼ 0.5 V and VBE ¼ 0.92 V.

The results obtained for fT (220 GHz) and fmax (240 GHz) [40], and other DC characteristics not reported here, demonstrated that the neutral electrical base was very thin and kept inside SiGe. Thus, despite the significant activation annealing used for CMOS compatibility, the boron diffusion was effectively blocked in the selectively deposited SiGeC base. In addition, the simultaneous high values of fT and fmax demonstrate the low parasitic components of this architecture. On the other hand, SEG processes are often feared for their micro- or macroloading effects even though they can be efficiently solved. Indeed, the fT cartography presented in Figure 2.3.27 shows a standard deviation of less than 2% (4.8% for fmax). These values demonstrate that any process uniformity or macro-LE issue has been solved in the present process. In the same manner other results showed that it does not suffer from micro-LE as well. Thus, no blocking point was detected toward industrialization.

Double Gate MOS Double gate MOS (DG-MOS) transistors present important potential advantages: excellent Ion /Ioff trade-off, good control of short-channel effects (SCE) and drain-induced barrier lowering (DIBL), and higher channel conductivity. They may be the alternative device structure for the ultimate CMOS nodes. The DG devices presented here have been processed in a planar configuration owing to the utilization of the silicon-on-nothing (SON) process and the main operations are detailed in Chapter 2.10. After classical STI formation, a two-step epitaxy is done: a selective epi of SiGe (20 to 40 nm) followed by a thin NSEG of silicon. This Si NSEG leads to a mono-Si layer on active zones with a well-controlled thickness of the conduction channel, and to a poly-Si deposition on STI areas. Then, after source–drain– channel definition by photolithography and etching, the underlying SiGe is selectively etched, thanks to a specific isotropic plasma processing, leaving a silicon bridge (future DG-MOS channel) over the active zone. The SEM view given in Figure 2.3.28 illustrates the situation. One major advantage of this structure on some others reported in literature is related to the fact that the thickness of the silicon channel is defined by epitaxy that is capable of nanometric thickness with excellent uniformity. The remaining silicon bridge is oxidized to form a 20-A˚ thick gate oxide. In situ phosphorus-doped polysilicon is deposited all around the silicon bridge, and top gate and bottom gate are patterned by standard RIE gate etching. After the formation of spacers, extensions are implanted, and because thin Si films are used, elevated S/D were formed by Si SEG before standard 8 nm Co salicidation. A TEM cross section of a finished device with Lgate ¼ 40 nm and TSi ¼ 15 nm is presented in Figure 2.3.29. This picture shows that the morphology of the device is well controlled, whereas additional high-resolution TEM observations proved that the Si channel was a perfect monocrystal. We can also note that we optimized the cleaning step before elevated S/D in order to minimize the TEOS consumption under the offset spacer (as located by the white circle), and that the elevated S/D SEG exhibited some faceting but without any detrimental effect on electrical device characteristics.

© 2006 by Taylor & Francis Group, LLC

2.3-77

Si–SiGe(C) Epitaxy by RTCVD

Poly Si Mono Si

50 nm

FIGURE 2.3.28 Silicon bridge over active zone after SiGe selective etching.

Top gate Spacer Conduction channel Epitaxial raised S/D

S

Bottom gate

D

100 nm

FIGURE 2.3.29 Along-channel TEM cross section of final DG device, Lgate ¼ 40 nm, TSi ¼ 15 nm.

Electrical results confirm that the DG architecture improves considerably the device performances with very high drain currents (more than a factor of 2 as compared to conventional pMOS), small SCE, well-controlled DIBL, and subthreshold slope almost ideal [41]. The best results in terms of drive currents were obtained for a 70 nm gate length coupled with a 30 nm TSi with Ion ¼ 1954 mA /mm (Ioff ¼ 283 nA /mm) for nMOSFETs (more detailed results are reported in Ref. [41]). On the other hand, the geometry of DG devices provides an excellent electrostatic integrity. This effect is illustrated in Figure 2.3.30, which reports the variation of DIBL as function of the gate length and for different silicon channel thicknesses. We observe that the thinner the channel, the lower the DIBL, and that DIBL is excellent as soon as the channel thickness does not exceed a third of the gate length. Ultrathin Si films (10 nm), which can be controlled by epi deposition in the present technology, are thus mandatory for future CMOS technologies with short (32 to 45 nm) gates.

© 2006 by Taylor & Francis Group, LLC

2.3-78

The Silicon Heterostructure Handbook

Tsi 20 nm

80

Tsi 15 nm

70

Tsi 30 nm

DIBL (mV)

100 90

60 50 40 30 20 10 0 0

FIGURE 2.3.30

50 100 150 Largeur de grille (nm)

200

Drain-induced barrier lowering (DIBL) measured for different SOI thicknesses.

FD-SOI Silicon on insulator (SOI) substrates have some traditional advantages like reduced junction capacitance, lower power consumption, and higher RF performances, as compared to bulk silicon. In addition to that, ultrathin SOI with an improved electrostatic integrity should dramatically improve SCE that are important issues in advanced digital CMOS with ultrashort channels. Thus, ultrathin film (UTF) approach is very suited to achieve future CMOS and these substrates may become a standard for these applications. When fabricating CMOS on thin SOI films, the formation of S/D requires that these regions have been thickened. During salicidation, a certain excess of silicon is indeed necessary to insure good channel– silicide continuity. Elevated S/D deposited by SEG are then mandatory, and the situation is illustrated by Figure 2.3.31 that gives the cross section of such a FD-MOS fabricated on thin SOI. However, the manipulation of UTF requires special attention, as they are not stable with temperature. The difficulty is illustrated in Figure 2.3.32a, where a 6-nm-thick SOI film has been submitted to a

Tox

Epitaxy

1.4 nm

25 nm

Lg 60 nm Tsi 17 nm BOX 145 nm

FIGURE 2.3.31 Along-channel TEM cross section of final FD-SOI device with elevated S/D: Lgate ¼ 60 nm, TSi ¼ 15 nm, S/D elevation ¼ 25 nm.

© 2006 by Taylor & Francis Group, LLC

2.3-79

Si–SiGe(C) Epitaxy by RTCVD

Silicon reduction

Gate

Oxide

1µm (a)

Oxide

SOI

Gate No silicon reduction

0.5 µm (b)

FIGURE 2.3.32 SEM top view of a 40-nm thick SEG on ultrathin (6 nm) FD-SOI films: (a) standard process and (b) improved process.

standard Si SEG process. In this case, the H2 bake was carried out at a moderate temperature (<8508C) and selective deposition at 7508C with DCS–HCl chemistry, and we observe an important lateral constriction (about 50 nm) of SOI in active areas, as indicated in white circle. Some experiments were undertaken to examine or quantify if the missing SOI part was removed or displaced by evaporation (Equation (2.3.1) may be effective) or by agglomeration. On the other hand, via a dramatic thermal budget reduction we managed to carry out a 40-nm-thick Si SEG without any film restriction, as shown in Figure 2.3.32b. By further process optimization, we even demonstrated Si SEG on SOI films as thin as 3 nm, results not reported here.

© 2006 by Taylor & Francis Group, LLC

2.3-80

The Silicon Heterostructure Handbook

This application is well illustrative of future material developments that will concern excessively thin films and that will present new issues.

2.3.6 Summary SiGe(C) materials and low-temperature epitaxy are today expanding the capabilities and applications of Si technologies. They have already pushed the Si bipolar technologies to tremendous performances, the fT/fmax values (220 GHz /240 GHz) above-mentioned and obtained in a fully industrial environment, and even more aggressive values reported in literature. On the other hand, LTE is entering the CMOS fabrication domain to give important improvements of MOS performances, using strained channels as an example [42], as well as to develop new innovative architectures like the DG-SON architecture illustrated in the previous section. SiGe(C) materials make the concept of bandgap engineering available in Si technologies. In association with other techniques like the selective etching (see Chapter 2.11), these materials also give a number of new device architectures possible. As a consequence, their (potential) applications are numerous and different. Thus, rather than try an exhaustive list of these applications, an almost impossible task, we prefer to detect what are the main trends in epi science. In our opinion, the most pressing requests are: new metastable materials (epitaxial SiGeC bases of HBT, highly doped epi, strained CMOS channels, etc.), complex stacks of very thin elementary epi films (base–emitter structure of HBTs), and extremely low thermal budgets (elevated source–drains in future CMOS, etc.). These materials requests can be translated into equipment or process requirements. .

.

.

.

.

.

Low deposition temperatures: this may be achieved by a very smart process or technology optimization, but new chemistries or new precursors would be welcome. Advanced gas panel functionality: new processes require a number of gases in the same time or in sequence; the gas panel has to be able to flow every gas needed in a step while it prepares or purges those required for the next step. Efficient gas control: as the elementary films are thinner and thinner, with deposition times possibly short, any lag time in gas flow has to be minimized. The gas pressure of the different gas panel parts has to be matched, and the gas panel design has to be compact with minimal dead volumes. High-temperature agility: with metastable materials and with very sensitive structures, temperature stabilization time may be detrimental and has to be minimized. Low-temperature cleaning: hydrogen bake cannot be carried out on very temperature-sensitive structures; integrated pre-clean (wet, plasma, new chemistries, etc.) will be mandatory if highquality epi is required. Efficient tool: LTE will have to be less expensive for mass production, reactors have then to present robust cleanliness, no memory effect and high uptime.

Note that we do not include the quality of process gases and of reactor atmosphere because the author believes that, although the epi temperature will have to be decreased, these criteria already fulfilled today will not be much more severe in future. As a final note, we believe that LTE will be a key technique to pass the very important roadblocks that are present on the silicon technology roadmap. And, for these reasons and as predicted [29], the present decade is very exciting, especially in SiGeC epi by RTCVD.

Acknowledgments We wish to thank the many people of ST Crolles who made this contribution possible, especially the persons involved in epitaxy: P. Ribot, L. Georjon, T. Ouptier, N. Loubet, and F. Brossard; and those in advanced device applications: H. Baudry, A. Chantre, P. Chevalier, C. Fenouillet, M. Laurens, M. Marty, S. Monfray, A. Monroy, J. Mourier, T. Skotnicki, B. Szelag, G. Troillard, and A. Vandooren.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-81

References 1. J.F. Gibbons, C.M. Gronet, and K.E. Williams. Limited reaction processing: silicon epitaxy. Appl. Phys. Lett. 47, 721, 1985. 2. J.C. Sturm, P.V. Schwartz, E.J. Prinz, and H. Manohara. Growth of Si1xGex by rapid thermal chemical vapor deposition and application to heterojunction bipolar transistors. J. Vac. Sci. Technol. B 9, 2011, 1991. 3. FUV4 from Jipelec — France. See for example: Thin Solid Films 222, 52, 1992. 4. J.C. Sturm, H. Manoharan, L.C. Lenchyshyn, M.L.W. Thewalt, N.L. Rowel, and D.C. Houghton. Well-resolved band-edge photoluminescence of excitons confined in strained Si1xGex quantum wells. Phys. Rev. Lett. 66, 1362, 1991. 5. D. Dutartre, G. Bremond, A. Souifi, and T. Benyattou. Excitonic photoluminescence from Si-capped strained Si1xGex layers. Phys. Rev. B 44, 11525, 1991. 6. C.A. King, J.L. Hoyt, C.M. Gronet, J.F. Gibbons, M.P. Scott, and J. Turner. Si/Si1xGex heterunction bipolar transistor produced by limited reaction processing. IEEE Electron Dev. Lett. 10, 52, 1989. 7. D. Dutartre, P. Warren, I. Sagnes, P.A. Badoz, J.C. Dupuis, G. Prudon, and A. Perio. Epitaxy and doping of Si and Si1xGex at low temperature by rapid thermal chemical vapour deposition. J. Vac. Sci. Technol. B 11, 1134, 1993. 8. McD. Robinson and L.H. Lawrence. Characterization of high growth rate epitaxial silicon from a new single wafer reactor. In Semiconductor Fabrication: Technology and Metrology, ASTM STP 990, Dinesh C. Gupta, Ed. American Society for Testing and Materials, Philadelphia, 1989. 9. J.C. Bean. Growth techniques and procedures. In Germanium Silicon: Physics and Properties, Semiconductors and Semimetals, Vol. 56, R. Hull and J.C. Bean, Eds. Academic Press, San Diego, CA, 1998, p. 8. 10. W. Kern and D.A. Puotinen. Cleaning solution based on hydrogen peroxide for use in semiconductor technology. RCA Rev. 31, 187, 1970. 11. T. Hsu, B. Anthony, R. Qian, J. Irby, D. Kinosky, A. Mahajan, S. Banerjee, C. Magee, and A. Tash. Defect microstructure in low temperature epitaxial silicon grown by RPCVD. J. Electron. Mater. 19, 4, 1990. 12. D.J. Meyer. Si-based alloys: SiGe and SiGe:C. In Silicon Epitaxy, Semiconductors and Semimetals, Vol. 72. D. Crippa, D.L. Rode, and M. Masi, Eds. Academic Press, New York, 2001, pp. 345–395. 13. B.S. Meyerson. Low-temperature silicon epitaxy by ultrahigh vacuum /chemical vapour deposition. Appl. Phys. Lett. 48, 797, 1990. 14. See for example the integrated wet clean referred as ‘‘OASIS CleanTM,’’ AMAT Inc, 2003. 15. J.C. Sturm, P.V. Schwartz, E.J. Prinz, and H. Manoharan. Growth of Si1xGex by rapid thermal chemical vapour deposition and application to heterojunction bipolar transistors. J. Vac. Sci. Technol. B 9, 2011–2016, 1991. 16. D. Dutartre, P. Warren, I. Berbezier, and P. Perret. Low temperature silicon and Si1xGex epitaxy by rapid thermal chemical vapour deposition using hydrides. Thin Solid Films 222, 52, 1992. 17. G. Pares, J.L. Regolini, J. Mercier, D. Dutartre, and D. Bensahel. Kinetics aspects of epitaxial silicon growth using disilane in a rapid thermal processing system. J. Appl. Phys. 68, 4885, 1990. 18. M. Lier, C.M. Greelief, S.R. Kasi, and M. Offenberg. Kinetics of silicon epitaxy using SiH4 in a rapid thermal chemical vapor deposition reactor. Appl. Phys. Lett. 56, 629, 1990. 19. M. Racanelli and D.W. Greve. Temperature dependance of growth of Si1xGex by ultra high vacuum chemical vapor deposition. Appl. Phys. Lett. 56, 2524, 1990. 20. D.J. Robbins, J.L. Glasper, A.G. Cullis, and W.Y. Leong. A model of heterogeneous growth of Si1xGex films from hydrides. J. Appl. Phys. 69, 3729, 1991. 21. K. Sinniah, M. Sherman, L. Lewis, W. Weinberg, J. Yates Jr, and K.C. Janda. New mechanism for hydrogen desorption from covalent surfaces: the monohydride phase on Si (1 0 0). Phys. Rev. Lett. 62, 567, 1989.

© 2006 by Taylor & Francis Group, LLC

2.3-82

The Silicon Heterostructure Handbook

22. M. Todd and D. Weeks. Low temperature, high growth rate epitaxial silicon and SiGe alloy films. First International SiGe Technology and Device Meeting, ISTDM2003, Nagoya, Japan, 2003, p. 153. 23. J.P. Posthill, R.A. Rudder, S.V. Hattangady, C.G. Fountain, and R.J. Markunas. On the feasibility of growing dilute CxSi1x epitaxial alloys. Appl. Phys. Lett. 56, 734, 1990. 24. L.D. Lanzerotti, J.C. Sturm, E. Stach, R. Hull, T. Buyuklimanli, and C. Magee. Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation. 1996 IEDM Tech. Digest, 1996, p. 249. 25. P.S. Chen, S.W. Li, Y.H. Liu, M.H. Lee, M.J. Tsai, and C.W. Liu. UHVCVD of hetero-epitaxial SiGe:C and SiC thin films on Si(1 0 0) with ethylene (C2H4) precursor as a carbon source. Second International SiGe Technology and Device Meeting, ISTDM2004, Frankfurt /Oder, Germany, 2004, p. 196. 26. F. Deleglise, C. Fellous, and D. Dutartre. Carbon incorporation study for SiGeC epitaxy optimization in RTCVD. First International SiGe Technology and Device Meeting, ISTDM2003, Nagoya, Japan, 2003, p. 151. 27. P.A. Coon, P. Gupta, M.L. Wise, and S.M. George. Adsorption and desorption kinetics for SiH2Cl2 on Si (1 1 1) 7 7. J. Vac. Sci. Technol. A 10, 324, 1993. 28. M. Hierlemann, A. Kersch, C. Werner, and H. Schaefer. A gas-phase and surface kinetics model for silicon epitaxial growth with SiH2Cl2 in a RTCVD reactor. J. Electrochem. Soc. 142(1), 259. 1995. 29. D. Dutartre. Silicon epitaxy: new applications. In Silicon Epitaxy, Semiconductors and Semimetals, Vol. 72, D. Crippa, D.L. Rode, and M. Masi, Eds. Academic Press, New York, 2001, pp. 397–457. 30. C. Fellous, F. Deleglise, A. Talbot, and D. Dutartre. Selective SiGeC epitaxy by RTCVD for high performance self-aligned HBT. 33rd European Solid-State Device Research Conference, Estoril, Portugal, 2003, p. 481. 31. H. Schaefer, J. Boeck, R. Stengl, H. Knapp, K. Aufinger, M. Wurzer, S. Boguth, M. Rest, R. Schreiter, and T.F. Meister. Selective epitaxial growth of SiGe:C for high speed HBTs. Appl. Surf. Sci. 224, 18, 2004. 32. N. Laurent, C. Fellous, and D. Dutartre. Non-destructive defect inspection in SiGe HBT using room temperature photoluminescence. Second International SiGe Technology and Device Meeting Proceedings, 2004, Frankfurt /Oder, Germany, 2004, p. 49. 33. C. Fellous, F. Romagna, and D. Dutartre. Thermal and chemical loading effects in non selective Si / SiGe epitaxy. Mater. Sci. Eng. B 89(1), 323, 2002. 34. P. Ribot and D. Dutartre. Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD. Mater. Sci. Eng. B 89(1), 306, 2002. 35. A. Talbot, J. Arcamone, C. Fellous, F. Deleglise, and D. Dutartre. Investigation of facet formation in RTCVD Si /SiGe selective epitaxie. In SiGe Materials, Processing and Devices, ECS 2004, Honolulu, Hawaii, p. 601. 36. R. Loo and M. Caymax. Avoiding loading effects and facet growth: key parameters for successful implementation of selective epitaxial SiGe deposition for HBT-BiCMOS and high-mobility heterochannel pMOS devices. Appl. Surf. Sci. 224, 24, 2004. 37. A. Talbot, J. Arcamone, C. Fellous, F. Deleglise, and D. Dutartre. Study of the poly/epi kinetics ratio in SiH4-RTCVD for new CMOS architectures. Second International SiGe Technology and Device Meeting, ISTDM2004, Frankfurt /Oder, Germany, 2004, p. 200. 38. C. Fellous, F. Romagna, and D. Dutartre. Comparison of dislocation generation in selective and non-selective SiGe epitaxy. Fifteenth International Symposium on Chemical Vapor Deposition (CVD-XV), May 14–19, 2000, Toronto, Canada, 2000, p. 442. 39. F. Sato, T. Hashimoto, T. Tasumi, H. Kitahata, and T. Tashiro. Sub 20 ps ECL circuits with 50 GHz fmax self-aligned SiGe HBTs. IEDM 1992. Tech. Digest, 1992, p. 397. 40. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C.T. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Bartalat, R. Beerkens, N. Zerounian, F. Aniel, and A. Chantre. Accepted to the 2004 Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, Canada, September 13–14, 2004.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-83

41. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Julian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, MP. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteannu, J-L. Autran, and T. Skotnicki. Highly performant double gate MOSFET realized with SON process. IEDM 2003. Tech. Digest, 2003, p. 449. 42. K. Mistry, M. Armstron, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadski, K. Zhang, S. Thompson, and M. Bohr. Delaying Forever: Uniaxial Strained Silicon Transistor in a 90 nm CMOS Technology. 2004 Symposium on VLSI Technology, Hawaii, Honolulu, 2004, p. 50.

© 2006 by Taylor & Francis Group, LLC

2.4 MBE Growth Techniques

Michael Oehme and Erich Kasper University of Stuttgart

2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7

Introduction................................................................. 2.4-85 Requirements on an SiGe MBE System .................... 2.4-85 UHV Conditions ......................................................... 2.4-86 Sources of Atomic and Molecular Beams ................. 2.4-88 Substrate Heating and Cleaning ................................ 2.4-91 In Situ Analysis ............................................................ 2.4-92 Summary ...................................................................... 2.4-93

2.4.1 Introduction In the past few years, the development of modern semiconductor devices utilizing structures with atomic dimensions has been advanced by vertical design. Layer structures with nanometer dimensions featuring quantum effects have become dominant. This would be applicable in some SiGe semiconductor devices such as in the resonant tunneling diode [1] or high electron mobility transistor (HEMT) [2]. Modern epitaxy techniques like the molecular beam epitaxy (MBE) method [3, 4] allow the growth of very thin crystalline silicon germanium layers with well-defined dopants by very low growth temperatures. In this temperature regime volume diffusion is negligible. Furthermore, the critical thickness of SiGe heterostructures is increasing. However, in this low-temperature growth regime, surface segregation of dopant or alloy atoms has turned out to be a dominant mechanism for profile smearing. Knowledge of segregation behavior is necessary for device design and realization based on low-temperature epitaxy. Especially in the case of SiGe MBE surface segregation is observed for alloy atoms and dopants like boron, phosphorus, or antimony [5]. The purpose of this chapter is to describe the SiGe MBE growth techniques with the individual technical components such as the ultrahigh vacuum (UHV) system, the evaporation sources, the substrate heating, and the in situ monitoring of the process.

2.4.2 Requirements on an SiGe MBE System Epitaxy describes the oriented growth of a single crystalline film on a substrate. The growing layer follows the orientation of the substrate. The driving force for the crystalline growth is minimizing of energy because the perfect crystal is the energetically favorable solid. A requirement for epitaxy is a clean substrate surface, otherwise the information about orientation of the substrate is disordered or even destroyed and the consequences are crystalline defects up to polycrystalline or amorphous growth. MBE growth is carried out under conditions far from thermodynamic equilibrium and is dominated mainly by the kinetics of the surface processes occurring when the impinging beams react with the top atomic layer of the substrate.

2.4-85 © 2006 by Taylor & Francis Group, LLC

2.4-86

The Silicon Heterostructure Handbook

An MBE machine involves the generation of molecular beams of matrix material such as silicon or germanium and doping species and their interaction with the substrate surface to form a single-crystal deposit under UHV conditions. The atomic or molecular fluxes of elemental constituents are evaporated or sublimated in special electron beam evaporators (EBEs) or in radiatively heated effusion cells. For a precise control of the beam fluxes over the substrate all sources exhibit rapidly acting mechanical shutters, and the flux of the deposition materials can be measured directly with a flux monitor, for example, a quadrupole mass spectrometer (QMS) or indirectly over the effusion cell temperature (after calibration). This enabled the growth of SiGe layers with controlled Ge content between 0% and 100% with an arbitrary doping structure. Another advantage is the growth of very sharp doping transitions over several decades with special doping strategies. The quality of the vacuum conditions and the purity of the constituent fluxes are fundamental specification of the MBE because the semiconductor properties are sensitive to impurities. Crystal quality and defect density are drastically limited by insufficient partial pressure [6]. For the growth of epitaxial layers with high-purity and crystalline perfection UHV equipment with a basis pressure less than 1 1010 mbar is needed. Really important are the vacuum conditions during the layer growth, where very hot components in the reactor need special materials with a low vapor pressure such as tantalum or molybdenum. From the above discussion, the essential features of an SiGe MBE system are 1. 2. 3. 4.

UHV conditions during growth Clean Sources of atomic and molecular beams Substrate-cleaning scheme with low thermal budget In situ analysis of process conditions and real-time monitoring for close-loop control

In the following sections, we discuss these topics with emphasis on technological aspects. Figure 2.4.1 shows a picture of a commercial 200 mm SiGe MBE equipment (with permission of DCA instruments). The machine can be upgraded to wafers with 300 mm diameter.

2.4.3 UHV Conditions In order to overcome the exchange between air and UHV, an MBE machine consists of at least two chambers, a growth chamber and a load lock. According to different application needs, designs of MBE systems with two [7], three [8], or more [9] chambers are known. A schematic view of the basic unit is shown in

FIGURE 2.4.1 Picture of a commercial 200 mm SiGe MBE equipment (with permission of DCA instruments). The machine can be upgraded to wafers with 300 mm diameter.

© 2006 by Taylor & Francis Group, LLC

2.4-87

MBE Growth Techniques

Figure 2.4.2. It consists of two independently pumped UHV chambers connected with a UHV gate valve. At the left side there is the load lock with the wafer-transfer mechanism. This chamber accommodates a cassette-type magazine for silicon wafers. In modern MBE systems this magazine meets an industrial standard for 25 wafers with diameters of 150 or 200 mm. The load lock is pumped rapidly with a turbomolecular pump or with a cryopump. A typical system achieves a pressure in the range of 108 mbar within 90 min. The wafer transport between the storage chamber and growth chamber is computer controlled, and performed completely under UHV conditions. To minimize the contamination during transfer of a substrate from the load lock into the deposition chamber, multiple wafer loading is often used. These wafers are transferred into a parking stage within a central chamber for storage under UHV with a pressure in the range of 1010 mbar. Figure 2.4.2 (right side) shows a schematic view of a growth chamber. This chamber accommodates all the installations necessary for MBE growth. These are substrate holder, substrate heater, and substrate rotation; evaporation sources for matrix materials and dopants; and monitoring and analyzing facilities. Typically, the growth chamber is evacuated with a pumping cascade existing of an oil-free prevacuum pump, a turbomolecular pump, and a high-speed sorption pump, e.g., a sublimation pump cooled with liquid nitrogen. The growth chamber is always under UHV except for maintenance work or source refilling. After venting the chamber, a conditioning of the MBE system requires bakeout up to 3008C over more than 24 h. For this heater elements in a jacket are welded to the chamber walls from outside. For a minimum of preparation time to the start of bakeout, a layer of thermal isolation fiber is permanently sandwiched between the chamber wall and an aluminum cover. Under growth conditions, cooling water pipes welded to the chamber walls effectively reduce outgassing. Also, all effusion cells exhibit cooled walls to reduce the thermal radiation.

Substrate rotation RGA

Loadlock with transfer mechanism Gate valve QMS

Heater

RHEED

Substrate

Shutter

Si Ge-beam evaporator Effusion cell

Pyrometer

FIGURE 2.4.2 Schematic illustration of an SiGe MBE system; the pumping system is not shown.

© 2006 by Taylor & Francis Group, LLC

2.4-88

The Silicon Heterostructure Handbook

H2 Ion current (arbitrary units)

Total pressure 10−9 mbar Basis pressure (<10−10 mbar)

N2/CO

CO2 0 0

10

20

30

40

50

Mass number

FIGURE 2.4.3 Residual gas spectrum of well-conditioned MBE chamber before (basis pressure <10–10 mbar) and during (total pressure 109 mbar) the growth of an SiGe layer.

The outgassing of equipment materials and surfaces limits the vacuum pressure. Figure 2.4.3 shows a typical residual gas spectrum of a well-conditioned MBE system before and during the growth of an SiGe layer. Hydrogen (H2) is the main detectable residual species in the UHV. Small increases in the heights of CO, and CO2 occur during growth, but the pressure is also dominated by H2. residual H2O, N2

2.4.4 Sources of Atomic and Molecular Beams For typical Si growth rates of the order of nanometers per second flux densities in the range of 5 1014 to 5 1015 cm2 sec1 are required. Si temperatures of about 17008C are necessary when these flux densities are generated by evaporation from a Si-source distance of about 30 cm from the substrate. At such temperatures, molten Si is very reactive and it would cause excessive contamination from the crucible material [10]. A solution for this problem is heating of Si with an electron beam. Figure 2.4.4 shows a schematic view of the major components of a Si EBE. Tungsten filament emits electrons and these are accelerated in an electric field (electron gun) with typical energies between 4 and 12 keV. In a magnetostatic field, the electrons are deflected to an angle of 2708 to avoid contamination by tungsten atoms, which emitted from the filament, as metallic impurities are undesirable in the molten Si. The high-energy electrons impinge on a single-crystal, high-purity (resistivity > 1000 V cm1) Si ingot, which is placed in a water-cooled Cu-crucible. The focused electron beam is partially melting the Si surface. The electron beam can be scanned over the whole crucible. Due to the thermal properties of Si, the molten region is restricted to the area directly heated by the electron beam. Several problems result from the EBE application; electron- and ion-beam-stimulated desorption of gas molecules adsorbed on the system walls and cold shrouds, damage of the grown film by impinging electrons and ions and interference with in situ monitoring instruments. In order to minimize these problems, the EBE is screened by cold walls with defined aperture, which limit the beam cone and reduce the thermal load of the chamber walls. All metal surfaces are covered with high-purity Si plates to reduce the risk of interaction with electrons and ions. The flux monitoring of Si is performed by a QMS. The QMS measures the intensity of the Si isotope, with the mass number 30, directly in the Si molecular beam because this mass is free of fragments of other residual species. The QMS signal is proportional to the flux, respectively the growth rate on the substrate surface.

© 2006 by Taylor & Francis Group, LLC

2.4-89

MBE Growth Techniques

Si-molecular beam

Accelerated electron beam

Magnetic deflection element

Molten Si

Si-crucible

Watercooled Cu-hearth Electron gun

FIGURE 2.4.4 Schematic view of the major components of an Si electron beam evaporator.

The Si EBE is also a source for silicon ions. In the area above the silicon melt, the flux of evaporated atoms is ionized partially by the interaction with the electron beam. A potential up to several kV can be applied to the isolated substrate holder to focus and accelerate the Si ions. Thus, it is possible to use special growth strategies such as doping by secondary ions (DPI) [11], generation of point defects [12], or dislocation annihilation [13]. For the evaporation of Ge there are two possibilities, with an EBE or a single effusion cell. The construction of Ge-EBE is similar to the Si-EBE. However, the turbulence in Ge is much more severe as in Si, because Ge has much smaller thermal conductivity than Si, resulting in complete melting of the Ge reservoir. Contact of the molten Ge with the water-cooled Cu crucible triggers heavy turbulence. To overcome this problem, a liner made from high-purity, single-crystal Si is used. Possible enrichment of Si in the Ge reservoir is acceptable, since usually SiGe layers are grown and both fluxes are monitored simultaneously by a mass spectrometer. The other possibility is the Ge evaporation from a single effusion cell [14]. The particular property of this cell is the co-evaporation of Ge and carbon with a flux ratio of roughly 1000, because the crucible consists of pyrolithical carbon. Carbon is partly dissolved in molten germanium up to the saturation limit. Saturation is obtained by heating the crucible with the germanium–carbon ingot above the melting point. Dissolved carbon evaporates much easier and the germanium /carbon ratio is reduced to three orders of magnitude, which is exactly the right ratio for SiGe-HBT applications with suppressed boron out-diffusion [15]. A technical solution is shown in Figure 2.4.5. Ge is melting in a graphite crucible with a large area opening (4 cm2). The crucible and the graphite support are specially designed to withstand the strong tensile forces exerted by the increase of Ge volume during solidification. The diamond lattice is an open structure with a considerable volume increase both for Si and Ge during solidification. The electrical current heater surrounds the crucible, the outward heat flux is shielded by a graphite cage, tantalum- and Si-shields, and a cold wall. A thermocouple is mounted near the bottom of the crucible. A clear problem of this source after long-time operation seems to be the formation of a thin carbon film, which covers part of the molten germanium like a skin. This carbon skin is probably created by carbon precipitation during cooling down the melt from the operating temperature (typically 13008C) to the standby temperature chosen slightly above the Ge melting point of 9388C. This carbon skin reduces with time the effective area for evaporation for both germanium and carbon. (Remember:

© 2006 by Taylor & Francis Group, LLC

2.4-90

The Silicon Heterostructure Handbook

QMS

Ge-molecular beam with C-atoms

Shutter Si aperture Graphite crucible

Tantalium shields Graphite

Heater

Germanium

Cold wall

Thermocouple Current control

FIGURE 2.4.5

Effusion cell for Ge C co-evaporation with quadrupole mass spectrometer (QMS) flux control.

The evaporation from carbon itself is negligible at the source temperatures.) The source, therefore, cannot be operated at the usual mode of an effusion cell with thermocouple control. Instead a flux control with a QMS is necessary for power regulation. The single effusion cell for germanium evaporation will considerably reduce the effort of carbon doping of MBE-grown HBT structures. In nanoelectronic devices based on Si or SiGe, carbon doping plays an important role for two reasons. First, carbon doping delivers a heterostructure barrier for electrons [16] and may be used for quantum wells with electron confinement. Second, the retarded boron diffusion [17] is utilized in SiGe-HBTs with improved process stability. The sublimation of carbon requires very high temperatures up to 23008C. Special high-temperature sublimation cells achieve C concentrations up to several percent in Si1xyGexCy layers [18]. p-Type and n-type doping over a wide range of concentration and with abrupt doping transitions is necessary for novel device structures. High and moderate levels of dopants of both types are needed to grow devices. In an SiGe MBE several doping techniques are used. Boron is commonly used for p-type doping as it has a larger equilibrium solid solubility and a very low surface segregation. In modern SiGe MBE systems, boron is evaporated using a high-temperature source with special graphite crucibles. Temperatures between 15008C and 20008C are required to achieve doping levels of 1015 cm3 up to several 1020 cm3. n-Type doping during SiGe MBE growth is problematic because of low sticking coefficients and surface segregation. Thus, a limited range of dopant concentrations is available. In an SiGe MBE antimony and phosphorus can be used.

© 2006 by Taylor & Francis Group, LLC

2.4-91

MBE Growth Techniques

Antimony is the more attractive n-type doping material because it can be directly co-evaporated from a controlled source during the growth. However, the extreme temperature sensitivity of surface segregation requires special doping strategies such as prebuildup, flash-off techniques [19], or the DSI [20]. DSI allows doped SiGe layers with very sharp doping transitions over few decades. Elemental phosphorus cannot be used due to its high vapor pressure, which gives rise to high background contamination in an MBE system. For P-doping special sources exist. Possible realizations of such a source are an arch made of phosphorus-doped Si [21] or the doping from a GaP source [22]. Comparison with Sb-doping shows that the segregation behavior in the lower temperature regime is surprisingly similar. In the higher temperature regime, however, surface segregation of Sb is much stronger [5].

2.4.5 Substrate Heating and Cleaning The substrate temperature is one of the most important growth parameters because it influences all adatom processes of the surface, the crystalline growth, the surface morphology, the abruptness of doping transitions, and the relaxation processes in heterostructures. In an SiGe MBE, the substrate is heated radiatively from the backside by a current-powered meander. A typical construction is shown in Figure 2.4.6. The heater is made of meander-shaped pyrolytical graphite. A reflector ring under the substrate and the thickness profiling of the heater element guarantee a homogenous temperature distribution between room temperature and 10008C. A radiation shield of pyrolytical graphite minimizes the thermal losses. This construction is mounted in a water-cooled steel case with a tantalum heat shield in the inner part. The temperature of the graphite meander Tth is monitored by a thermocouple behind the heater. The substrate temperature is measured with a near-infrared pyrometer. The pyrometer measurement is used to calibrate the heater temperature. However, at the typical growth temperatures, only a small overlap of the spectral emission of the radiative heater and the spectral absorption of silicon is given. At 7008C, the maximum of the thermal radiation for a black emitter has a wavelength of 3 mm. In this wavelength range intrinsic silicon is transparent. The heating of substrate is caused mainly by radiative absorption of the free charge carrier. Figure 2.4.7 shows the temperature dependency of a high- and a low-doped substrate as a function of heater temperature measured with a pyrometer. For temperatures above 6508C no differences for this two types of substrates can be seen because the intrinsic carrier concentration in Si is 1018 cm3 at 7008C [23]. However, at lower heater temperatures, the temperature difference between high- and low-doped

Graphite meander Thermocouple

Radiation shields Substrate Reflector ring

FIGURE 2.4.6 Schematic view of a typical radiative heater system.

© 2006 by Taylor & Francis Group, LLC

2.4-92

The Silicon Heterostructure Handbook

Substrate temperature (⬚C)

900

800

700 p+−substrate 600

500 p−−substrate

400 400

500

600

700

800

900

1000

1100

Thermocouple temperature (⬚C)

FIGURE 2.4.7 Temperature dependency of a high- and low-doped substrate as a function of heater temperature measured with a pyrometer.

substrates increases. At Tth ¼ 5008C the difference is 40 K. The consequence is that different calibration curves for high- and low-doped substrates have to be used. High-quality growth needs interfaces with low contamination levels [24]; otherwise strain fields, dislocations, stacking faults, unintentional doping, and reduced carrier lifetimes may result. A very NH4OH and H2O2 HCl (RCA etch) common cleaning scheme employs an ex situ etch with H2O2 followed by an in situ heating at 8608C to 9008C. The thin protective oxide (SiO2) is desorbed as SiO after the reaction Si þ SiO2 ! 2SiO [25] has taken place during heating. Wafer manufacturers deliver their substrates already covered with the thin protective oxide. In an SiGe MBE system, the SiO2 layer is completely desorbed at substrate temperatures above 9008C [8]. If it is possible, the growth starts with an intrinsic Si buffer, which overgrows residual contaminations at the substrate interface such as carbon or SiC cluster.

2.4.6 In Situ Analysis Current process parameters are determined in an MBE system with different in situ analyzing methods such us vacuum monitoring, temperature monitoring and controlling, flux calibration and controlling, or the measurement of layer thickness. These parameters are used for process control or for regulating sources and substrate temperatures. High-temperature compatible thermocouples are used for measuring and controlling the temperatures of the effusion sources and the substrate. For the partial pressure analyzing a residual gas analyzer (RGA) is integrated in the growth chamber. This system consists of a QMS with multiplier. The RGA allows the monitoring of different residual species during the complete growth process. In modern SiGe systems, in situ flux monitoring of the matrix materials like Si and Ge can be performed by a mass spectrometer with Faraday cup detector. After calibration, the mass spectrometer signal gives directly the flux of the matrix materials and is used as a feedback parameter for controlling the EBEs. A multiplexer allows the control of the fluxes of two or more different masses simultaneously, for example, the mass number 30 for Si and 74 for Ge, which is used for the growth of Si SiGe structures. The flux measurement can also be performed with other methods such as quartz crystal resonators or electron-induced emission spectroscopy [26, 27].

© 2006 by Taylor & Francis Group, LLC

MBE Growth Techniques

2.4-93

Silicon ions from the EBE can be measured with a special ion detector [28]. This monitoring system measures the distribution of ion and electron densities over the substrate depending on the substrate voltage. Standard pyrometric measurements cannot be applied during film growth, since interference effects create artifacts and obscure the evaluation via Planck’s law. A combination of a pyrometer and a reflectometer will result in a real-time correction of emissivity «, thus allowing the determination of temperatures even for arbitrary multilayer stacks. This measurement method is called reflectionsupported pyrometric interferometry (RSPI) [29]. RSPI has been proven to be capable of providing in situ real-time information concerning temperature and film thickness for numerous applications in semiconductor manufacturing. Temperature measurements range from around 4508C to over 9008C with a resolution of about 0.18C. In the very low temperature regime (1508C to 4508C) the heater is calibrated with a Pt PtRh thermocouple incorporated in the substrate, and then operated with fixed heater power [30]. Reflection high-energy electron diffraction (RHEED) is an electron diffraction technique that can yield information on surface structure, cleanliness, smoothness, and growth rate [4]. It is particularly useful in MBE because of the determination of surface reconstruction, a re-ordering of the top atomic layer of the crystal by reducing the energy of the free surface.

2.4.7 Summary This chapter has presented an overview of topical SiGe MBE growth techniques. A wide substrate temperature regime (typically 1508C to 6008C) with low thermal budget, a simple in situ cleaning procedure, precise control of doping fluxes, doped heterostructures with abrupt profiles, and sophisticated in situ process monitoring are the main advantages of MBE. Several technical problems also have been discussed, for example, the influence of the epitaxial growth by the quality of the vacuum conditions or the dependence of substrate temperature from the substrate doping. A single Ge C source for MBE growth of C-doped SiGe base layers was presented. This source will considerably reduce the effort for carbon doping of MBE-grown HBT structures.

References 1. K. Eberl, R. Duschl, O. G. Schmidt, U. Denker, and R. Haug. J. Cryst. Growth 227 770 (2001). 2. F. Schaeffler. Semicond. Sci. Technol. 12 1515 (1997). 3. R.A.A. Kubiak, E.H.C. Parker, and S.S. Iyer. In Silicon Molecular Beam Epitaxy, E. Kasper and J.C. Bean, Eds. CRC Press, Boca Raton, FL (1988), p. 5. 4. M.A. Herman and H. Sitter. Molecular Beam Epitaxy. Springer-Verlag, Berlin (1996). 5. H. Jorke. In Properties of Silicon Germanium and SiGe:Carbon, E. Kasper and K. Lyutovich, Eds. INSPEC, Institution of Electrical Engineers, London, 2000, p. 287. 6. E. Kasper and H. Kibbel. Vac. Technol. 33 13 (1983). 7. E. Kasper, H. Kibbel, and F. Schaeffler. J. Electrochem. Soc. 136 1154 (1989). 8. E. Kasper, M. Bauer, and M. Oehme. Thin Solid Films 321 148 (1998). 9. T. Rupp, J. Messarosch, and I. Eisele. J. Cryst. Growth 183 99 (1998). 10. C.W. Pearce. In VLSI Technology, chapter 1, S.M. Sze, Ed. McGraw-Hill, Singapore (1983). 11. H. Jorke, H.-J. Herzog, and H. Kibbel. Appl. Phys. Lett. 47 511 (1985). 12. W.-X. Ni, G.V. Hannson, I.A. Buyanova, A. Henry, W.M. Chen and B. Momemar. Appl. Phys. Lett. 68 238 (1996). 13. M. Bauer, M. Oehme, K. Lyutovich, and E. Kasper. Thin Solid Films 336 104 (1998). 14. M. Oehme, M. Bauer, and E. Kasper. Mater. Sci. Eng. B89 332 (2002). 15. H. Ru¨cker, B. Heinemann, W. Ro¨pke, G. Fischer, G. Lippert, H.J. Osten, and R. Krups. Technical Digest, International Conference Simulates on Semiconductor Processes and Devices, IEEE, Piscataway, NJ, 1997, p. 281.

© 2006 by Taylor & Francis Group, LLC

2.4-94

The Silicon Heterostructure Handbook

16. R. Duschl, O.G. Schmidt, and K. Eberl. In Properties of Silicon Germanium and SiGe:Carbon, E. Kasper and K. Lyutovich, Eds. INSPEC, Institution of Electrical Engineers, London (2000), p. 158. 17. H.J. Osten, G. Lippert, P. Gaworzewski, and R. Sorge. Appl. Phys. Lett. 71 1522 (1997). 18. K. Eberl, S.S. Iyer, S. Zollner, J.C. Tsang, and F.K. Legoues. Appl. Phys. Lett. 60 3033 (1992). 19. S.S. Iyer, R.A. Metzger, and F.G. Allen. J. Appl. Phys. 52 5608 (1981). 20. H. Jorke and H. Kibbel. J. Electrochem. Soc. 133 774 (1986). 21. E. Friess, J. Nu¨tzel, and G. Abstreiter. Appl. Phys. Lett. 60 2237 (1992). 22. R. Duschl, O.G. Schmidt, G. Reitemann, E. Kasper, and K. Eberl. Electron. Lett. 35 1111 (1999). 23. S.M. Sze. Physics of Semiconductor Devices. Wiley Interscience, New York (1969), p. 28. 24. P.J. Grunthaner. Thin Solid Films 183 197 (1989). 25. S.T. Ahn, H.W. Kennel, W.A. Tiller, and J.D. Plummer. J. Appl. Phys. 65 2957 (1989). 26. C.A. Gogol and C. Cipro. Electrochem. Soc. Proc. 85 415 (1985). 27. R.A. Kubiak, S.M. Newstead, A.R. Powell, E.H.C. Parker, T.E. Whall, T. Naylor, and K. Bowen. J. Vac. Sci. Technol. 9 2423 (1991). 28. G. Eifler, E. Kasper, Kh. Ashurov, and S. Morozov. J. Vac. Sci. Technol. A 20 945 (2002). 29. H. Mo¨ller, F.G. Bo¨bel, B. Hertel, T. Lindenberg, and G. Ritter. J. Cryst. Growth 157 327 (1995). 30. M. Bauer, M. Oehme, M. Sauter, G. Eifler, and E. Kasper. Thin Solid Films 369 228 (2000).

© 2006 by Taylor & Francis Group, LLC

2.5 UHV/CVD Growth Techniques 2.5.1 2.5.2 2.5.3 2.5.4

Thomas N. Adam IBM Semiconductor Research and Development Center

2.5.5 2.5.6

Introduction................................................................. 2.5-95 Chemistry..................................................................... 2.5-96 Low Temperature and Low Pressure ......................... 2.5-98 Alloys, Doping, and Selective Epitaxial Growth ......................................................................... 2.5-99 Substrate Cleaning..................................................... 2.5-101 Reactors ...................................................................... 2.5-103

2.5.1 Introduction The aggressive scaling of silicon-based high-performance integrated circuits [1] has led to device dimensions and junction depths that require ultralow thermal processing budgets. For example, stateof-the-art CMOS gate lengths have shrunk below 100 nm over the past few decades. The current International Technology Roadmap for Semiconductors (ITRS) projects physical gate lengths in microprocessors and ASICs of 40 nm in the near future and 10 nm beyond 2015. Without considering suppression and enhancement effects, such as substitutional carbon or transients, the classical pﬃﬃﬃﬃﬃﬃ dopant diffusion alone (e.g., boron: D0 0.67 cm2/sec, EA 3.46 eV [2]) exhibits comparable 2 Dt values at 9008C for minute-scale durations. Growth techniques that employ low temperatures (7008C) for homo- and hetero-epitaxy are necessary to maintain abrupt doping profiles and prevent, nearly eliminate, dopant and alloy diffusion, especially in high-performance BiCMOS integration schemes. In particular, pseudomorphically grown silicon–germanium has emerged as an important alloy due to its bandgap properties and strain-induced effects on carrier mobility [3]. Among others, substratecompliant epitaxial SiGe is utilized in the fabrication of heterojunction diodes [4], resonant tunneling diodes [5], heterojunction bipolar transistors [6], modulation-doped field-effect transistors [7], MOS field-effect transistors [8], and photodetectors [9]. Today, the most commonly employed lowtemperature epitaxial deposition methods are molecular beam epitaxy (MBE) [10], gas-source MBE (GSMBE) [11], and chemical vapor deposition (CVD) [12]. The deposition using chemical vapors is practical in a commercial manufacturing environment because it offers high wafer-throughputs by batch processing, outstanding film uniformities, excellent control over alloy composition and dopant concentration, and selective epitaxial growth. However, chemical vapor deposition at atmospheric pressures and in low vacuum was traditionally restricted to high substrate temperatures. Although improvements in gas purity, chamber cleanliness and design, precursor chemistry, and interface cleanliness soon enabled further temperature reductions, only a concurrent and significant reduction in deposition pressure provided the key to defect-free low-temperature epitaxy and manufacturing-friendly batch processing of silicon and silicon–germanium [13, 14]. In this chapter, ultrahigh vacuum chemical vapor deposition (UHV/CVD) is compared to other silicon and silicon–germanium epitaxial deposition methods with emphasis on the ultralow temperature 2.5-95 © 2006 by Taylor & Francis Group, LLC

2.5-96

The Silicon Heterostructure Handbook

regime below 7008C and on 200 to 300 mm substrate size. Substrate surface cleaning and advantages and drawbacks of UHV/CVD are discussed.

2.5.2 Chemistry The deposition of Si and SiGe from chemical vapors is based on the thermal decomposition of appropriate precursors (pyrolysis), most commonly silanes (SiH4, Si2H6, Si3H8, etc.) or chlorosilanes, and germanes (GeH4, Ge2H6, etc.) or chlorogermanes. Diluted (He, H2, or N2 [15]) or undiluted precursors are introduced into a closed system via gas injectors to form a well-controlled gas stream with flow dynamics that are engineered to prevent turbulences and uniformly deliver precursors. The wafer is placed into the gas stream and heated to temperatures at which chemical reactions occur with the transported gas molecules. In general, a reactor may be of batch-type (boat, barrel, platen, etc.) or single-wafer design, while the process of CVD is traditionally divided into pressure regimes, such as atmospheric-pressure CVD (APCVD: 760 Torr), reduced-pressure CVD (RPCVD: 1 to 100 Torr), lowpressure CVD (LPCVD: 100 mTorr to 1 Torr), and UHV/CVD (102 to 104 Torr). Wafer heating is achieved by lamp arrangements or resistive coils, and samples are placed either on flat susceptors, pins, or in boats. Doping is realized by adding gaseous dopant compounds, such as diborane, phosphine, arsine, etc. to the precursor–carrier-gas mix. The overall reaction is commonly described in steps: (a) decomposition of precursors in the gas phase, (b) mass transport of precursors and by-products from the gas stream to the substrate surface, (c) adsorption at the surface, (d) surface diffusion, (e) dissociation, reaction, and bonding with surface atoms, and (f) desorption of by-products and excess precursors into the gas stream. Depending on the process pressure, substrate temperature, reactor design, and choice of precursor mixture, different steps may emerge as the rate-limiting mechanism. In the remainder of the chapter, the UHV low-temperature reaction-limited silane (disilane) deposition characteristics are discussed in detail. In this low-pressure, low-temperature extreme, gas-phase reactions can be neglected. An excellent introduction to UHV/CVD and its applications can be found in Refs. [12, 13]. During the thermal decomposition of silanes on single-crystalline silicon surfaces, various reaction pathways are feasible, involving different simple and multistep hydrogen and group dissociations and trapping. A description of the exact reaction kinetics is beyond the scope of this chapter and the reader is referred to published theories such as the transition state theory (TST) [16], Rice–Ramsperger–Kassel– Marcus (RRKM) [17], or quantum-Ramsperger–Kassel–Marcus (QRKM) theory [18]. Competing temperature and pressure-dependent adsorption, decomposition, and desorption rates of precursor and intermediate molecules complicate an accurate prediction of growth rate and morphology. However, various research groups have found that the primary adsorption species upon exposure of Si (1 0 0) H, with small amounts of SiH2 [19], while Si2H6 adsorbs to SiH4 at low temperatures were SiH3 and Si and reacts mainly by breaking the Si Si bond to form SiH3 fragments, which readily bond to the surface sites [20, 21]. low T

2SiH4 ðgasÞ ! 2SiH3 (ads) þ 2H(ads) for silane low T

Si2 H6 ðgasÞ ! 2SiH3 (ads) for disilane low T

2SiH3 ðadsÞ ! [ H Si Si H ] þ 2H2 (gas)

(2:5:1) (2:5:2) (2:5:3)

In Equations (2.5.1) to (2.5.3), ‘‘ads’’ denotes adsorption, while / and \ indicate bonds to the bulk silicon. As lumped into Equation (2.5.3), the pyrolysis of silane and disilane can be conceptionalized as a series of detachments of atomic hydrogen from the precursor molecule adsorbing on dangling bonds, and H coadsorption, with eventual release of molecular hydrogen. The individual reactions can be traced in vacuum by temperature-programmed desorption (TPD), spectroscopy, RHEED observations, STM, or

© 2006 by Taylor & Francis Group, LLC

2.5-97

UHV/CVD Growth Techniques

ellipsometry. It was shown on an atomic scale by real-time STM that, upon heat treatment, the two nearest neighboring atoms of a clean hydrogen-terminated (1 0 0) silicon surface pair up under hydrogen desorption to form monohydride dimers (bracketed term in Equation (2.5.3)). Dimerization was found to reduce the number of dangling bonds and surface energy [22], giving rise to threedimensional growth. Additionally, this pairing materialized in a well-defined row configuration [23] with rows terminated where atomic steps occurred. As a consequence of the tetragonal bonding nature of silicon, the subsequent atomic layer has dimer rows oriented perpendicular to the previous set of rows. Epitaxy from silanes on monohydride dimer surfaces at low temperatures requires breaking the dimer bond to supply the necessary number of dangling bonds. STM studies revealed different growth modes in the low-temperature regime depending on the exact substrate temperature and amount of precursor exposure, although in most of these studies, disilane rather than silane was used due to a higher sticking coefficient [21]. The reduction of adatom surface mobility at low temperatures suppressed step-flow growth and caused island nucleation and partial passivation, although multilayer growth was still observed [24]. The findings suggest that very low temperatures (<5008C) not only cause drastically reduced growth rates but also result in increased film disorder and roughness, a concern for ultralow temperature epitaxy. The desorption of hydrogen — the primary reaction by-product — from the surface silicon bonds is thermally activated with energies reported between 2.04 and 2.47 eV [16, 25, 26], while the precursor bond-dissociation energies of Si Si, Si C, Si H, and Si Cl bonds were measured ranging between 2.95 eV (Si4H10) and 4.81 eV (SiCl4) [27]. The adsorption (‘‘sticking’’) coefficients of silane, disilane, and trisilane molecules under UHV conditions were found to be dissimilar but only weakly temperaturedependent [28]. It is therefore generally accepted that the desorption of hydrogen is the rate-limiting step at sufficiently low temperatures. This yields the well-observed linear relationship between logarithmic growth rate and inverse temperature in a classical Arrhenius plot, such as depicted in Figure 2.5.1. Epitaxial silicon deposition rates are plotted for RPCVD, LPCVD, and UHV/CVD compiled from published silane data with the remarkable result, that independent of process pressure, precursor dilution, and reactor design, the hydrogen desorption is the apparent absolute limitation in growth rate. Care was taken to compare only true crystalline epitaxial growth. As published by Beers and Bloem

Epitaxial silicon growth rate (Å/min)

800

700

T(⬚C) 600

500 LEPE

103 6 mTorr 102 3 mTorr 0.3 mTorr

101 RP 100

10−1 9

LP 10

11 12 1/T (10,000/K)

13

14

FIGURE 2.5.1 Arrhenius plot of the epitaxial silicon deposition rate as a function of inverse temperature. Only single-crystalline film growth based on diluted and undiluted silane is compared. Representative values published for RPCVD ( [15], " [52]), LPCVD (& — batch-type hot-wall reactor, data provided by A. Little (Kokusai USA, www.ksec.com) and M. Miyamoto (Japan, www.h-kokusai.com) — personal communication), UHV/CVD ( , * [26], [35], $ [37], ^ [40], and ~ [64]), and low-energy plasma-enhanced (LEPE) CVD ( [31]) are included as closed symbols and dotted lines. Open circles denote values obtained employing a UHV/CVD batch reactor.

© 2006 by Taylor & Francis Group, LLC

2.5-98

The Silicon Heterostructure Handbook

[29], silane pyrolysis can be driven into higher deposition rate regimes, but the deposited films were polycrystalline or amorphous. It is understood that this may be due to insufficient surface diffusion of the adsorbed SiHx species to find energetically favorable bonding positions at high deposition rates. UV assistance [30] and more recently, plasma enhancement [31] were demonstrated to boost growth rates while retaining crystallinity due to enhanced precursor gas-phase dissociation, stimulated surface migration, and promoted hydrogen desorption.

2.5.3 Low Temperature and Low Pressure As invented by Meyerson [14], UHV/CVD is performed at pressures of 102 to 104 Torr, while maintaining background pressures of less than 108 Torr. To achieve ultimate background pressures in the UHV range, prevent hydrocarbon backstreaming, and allow unthrottled pressure equilibration in the low-milliTorr range for typical process gas flows (below 200 sccm); the use of turbopumps backed by a stack of rootsblower and mechanical pumps is typically required. If necessary, higher deposition pressures can be accomplished using a throttle valve coupled to a closed-loop pressure control circuit. The use of low process pressures has various favorable consequences. The rate of precursor gas-phase decomposition in the heated reactor volume is significantly reduced, as it is linearly dependent on precursor pressure below 10 Torr [13]. Therefore, thickness nonuniformities originating from spatial variations in silane concentration (and its fragments) are prevented. Undiluted and carrier-gas-free precursors are typically used, which reduces gaseous contamination, such as water vapor, unintentionally introduced by large amounts of carrier gases in other pressure regimes. Of course, contamination is also present in precursors but their partial pressure is well below the values detrimental for epitaxy [32, 33]. It is interesting to note that for a given temperature, precursor-to-layer conversion efficiencies in UHV/CVD, i.e., the number of Si atoms deposited (including tube and boat) per number of silane molecules admitted per minute, remain comparable to those of optimized carrier-gas-based regimes, such as RP or LPCVD. Furthermore, the mean-free path of the precursor molecules at 102 to 104 Torr is tens of centimeters and compared to higher pressure regimes, gas-flow dynamics are simple and without convectional effects. Combined with a small sticking coefficient of silane and long reactor residence times, this results in a homogeneous precursor delivery to all exposed vacuum surfaces and holds great potential for uniform deposition rates in batch-type reactors. Contamination originating from the reactor’s inner periphery is minimized by evacuating the chamber to UHV pressures. Some contamination of the wafer surface from a finite vacuum is unavoidable but can be mitigated by flushing with inert gases during wafer loading and unloading, provided that the reactor leak rate is larger than the rate at which contamination is introduced by the flush gas. The value of necessary background pressure before growth is governed by required minimum partial pressures of O2 and H2O at the target growth rate and temperature [32, 33]. Typically, chamber pressures in the mid-109 Torr range were sufficient for a wide range of substrate temperatures as partial pressures of contaminants were then in the 1011 Torr range, measured using a residual gas analyzer. Pressures in the mid-108 Torr range proved satisfactory for higher temperatures and faster growing SiGe. The clean reactor environment, in turn, enables an extended range of growth temperatures. Very low growth rates of silicon and silicon–germanium (below 1 A˚/min) at ultralow temperatures are thus feasible. Temperatures as low as 4508C were demonstrated to yield clean epitaxial silicon films employing purified silane [26]. However, without substrate rotation and modified gas injection systems, temperatures in excess of 6008C to 6508C can cause substantially degraded thickness uniformities due to gas depletion in the reactor (transport-limited regime). As depicted in Figure 2.5.2 for different substrate temperatures, a saturation of silane-based growth rate occurs in UHV/CVD reactors at low temperatures and pressures, and at lowest temperatures only slightly increasing growth rates were observed with increasing silane pressures. In contrast, no saturation was observed for comparable partial pressures of silane at much higher total pressures. A strong dependence on flow rate (or pressure) is indicative of gas depletion across the reactor, boat, and wafer and results in degraded within-wafer and

© 2006 by Taylor & Francis Group, LLC

2.5-99

UHV/CVD Growth Techniques

104

103

,9 0

0⬚ C

494

2T

750⬚C

102

470

600⬚C

T, 6

510⬚C

00

⬚C

550⬚C 101

40

Epitaxial silicon growth rate (A/min)

Boat

100

10−5

10−4 10−3 10−2 10−1 Silane pressure (Torr)

Top 100

FIGURE 2.5.2 Epitaxial silicon growth rate as function of (partial) silane pressure in UHV/CVD (solid lines: & [36,37], * [37], and ^ [65]) and RPCVD reactors (dotted lines: ~ [15], ! [66]). Steep lines indicate a strong dependence on partial pressure and are undesirable for batch-type configurations. Gas depletion over the wafer and boat can spatially modify the precursor partial pressure, and thus, create deposition inhomogeneities. Best uniformities are obtained using lowest temperatures and undiluted precursors.

−100−80 −60 −40 −20 0 20 40 60 80 100 x (mm)

FIGURE 2.5.3 Silicon thickness contour plot of the center wafer deposited in a low-temperature UHV/ CVD batch reactor. The target thickness was 500 A˚ and local maximum and minimum values are included (in A˚). A total temperature variation of 2.888C across the wafer (2 mm edge exclusion) was inferred from thickness variations obtained using spectroscopic ellipsometry. The orientation of the wafer inside the reactor, i.e., top and bottom (boat), is indicated. The small offset between the wafer and measurement grid was caused by automated stepping with disabled pattern recognition.

within-boat thickness uniformities (transport-limited operation). Operating the reactor in saturation (reaction-limited deposition) ensures excellent uniformities, and one-sigma wafer-to-wafer, withinwafer, run-to-run, and tool-to-tool variations of germanium fractions in SiGe within the range of 3% to 4% and of combined Si and SiGe thicknesses within the range of 1% to 3% are typically achieved in 200 mm UHV/CVD batch reactors. However, intrinsic silicon thickness maps of the center wafer, as displayed in Figure 2.5.3 revealed radially increasing values that were eccentric relative to the wafer and wafer-boat geometry but concentric relative to the reactor–heater axis, in addition to locally modified thicknesses in the vicinity of the structural support from the boat, totaling 6.1% variation. Combined with the measured activation energy and preexponential factor of silane-based silicon epitaxy in the same reactor (1.74 eV and 7.5 1011 A˚ /min), a total temperature variation across the center wafer of 1.888C was inferred from these measurements. It is apparent that good thickness uniformities and repeatability in UHV/CVD reactors therefore require superior temperature uniformities and stabilities as they are exponentially connected, while precursor delivery is intrinsically simple and noncritical. In contrast, uniformity in mass-transport-limited silicon epitaxy at higher substrate temperatures (most APCVD, RPCVD, and LPCVD reactors) is strongly dependent on even precursor delivery.

2.5.4 Alloys, Doping, and Selective Epitaxial Growth Pseudomorphic alloys of silicon with other group IV elements, such as germanium and carbon, have gained much attention due to bandgap engineering, strain effects, and suppression of dopant diffusion. Epitaxial UHV/CVD of SiGe is typically achieved by adding diluted germane or digermane to the precursor gas flow. However, as depicted in the inset of Figure 2.5.4, the germanium fraction and SiGe deposition rate are nontrivial functions of flow rate (pressure) and substrate temperature, although the Ge fraction appears less sensitive to temperature changes. For batch reactors, the values of listed wafer

© 2006 by Taylor & Francis Group, LLC

2.5-100

The Silicon Heterostructure Handbook

1020

1018 1017 1016 1015 0.1

40 30 20 10 0 0

1 2 3 4 5 Flow of GeH4 (%)

Log. rate (A/min)

1019

Ge (%)

Boron concentration (cm−3)

1021

1 10 Diborane flow (sccm)

FIGURE 2.5.4 Boron concentration in films of silicon ( ) and SiGe ( ) as a function of B2H6 flow (1000 ppm in He) in a UHV/CVD batch reactor, determined by SIMS measurements. The inset depicts the germanium fraction and logarithmic SiGe growth rate in the same batch-reactor as a function of germane flow percentage in SiH4 þ GeH4 þ He for 5258C (dotted lines and diamonds) [40] and 5108C (solid lines and circles). Germanium fractions and layer thicknesses were extracted using XRD, SIMS, Auger, and spectroscopic ellipsometry. Ge fractions between 0% and 25 % appear much less sensitive to temperature variations.

temperature are somewhat arbitrary as large errors may be caused by sensing the vessel temperature using spring-loaded thermocouples. Even if the reactor wall temperature was known with sufficient accuracy, actual wafer temperatures are expected to be several degrees lower. Absolute temperature calibration to growth rates using standard silane flows and pressures should be employed to establish grounds for comparison and repeatability. In single-wafer tools, thermocouples can be placed in direct contact to or within the immediate vicinity of the wafer. Furthermore, eutectic reactions, such as with Au, may be observed through view ports in order to calibrate to the true wafer surface temperature. In general, the addition of GeH4 increases the growth rate [13, 34]. This is believed to occur due to a reduced hydrogen desorption activation energy for Ge H (1.6 eV) as compared to Si H (2.0 eV), and a lower binding energy of Ge H (3.1 eV) compared to Si H (3.4 eV) [16]. Depending on the substrate temperature, the growth rate of SiGe may reach values that are several times larger than that of silicon. As a consequence, care must be taken to avoid gas-depletion effects at low process pressures, i.e., silane flows. In principle, Si1–xGex with compositions between x ¼ 0% and 100% are attainable by adjusting the flows of silane and germane. However, for increasing germanium fractions, both the apparent and metastable critical thicknesses reduce accordingly [40]. The use of low temperatures during growth, as enabled by UHV/CVD, is expected to result in better alloy metastability because relaxation (dislocation nucleation and glide) exhibits stronger thermally activated behavior as compared to growth (EA 4.2 to 4.75 eV [35]). Low deposition rates also ensure exceptional profile control, repeatability, and atomic abruptness while at the same time, yielding excellent uniformities in batch-type reactors. Sophisticated germanium, carbon, and dopant profiles, such as polynomial or exponential ramps, can be obtained by dynamic (time-dependent) programming of massflow controllers. Typical n-type (p-type) dopants for silicon- and silicon–germanium-based devices are phosphorous, arsenic, and antimony (boron and gallium). B2H6, PH3, AsH3, and also SbH3 are dopant compounds that are employed in chemical vapor deposition. It is generally accepted that the use of low temperatures (<6008C) results in (nearly) complete dopant activation in as-grown films over a wide range of concentrations, eliminating the need for high-temperature annealing steps. Furthermore, dopant diffusivities in both silicon and silicon dioxide are strongly dependent on temperature, with activation energies (3.4 to 4.2 eV in c-Si, 2.4 to 3.9 eV in poly-Si, and 1.3 to 4.7 eV in SiO2 [2]) that are generally much larger than that of epitaxial growth (1.5 to 2.1 eV for silane-based growth [13, 26, 36] and 1.5 eV

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-101

for disilane-based growth [30, 37]). Therefore, dopant diffusion is nearly eliminated for growth temperatures below 6008C and typical deposition durations. However, the incorporation of dopants is dependent on various factors, such as temperature, precursor, chamber environment, and of course gas flow. Not all gaseous dopant sources allow abrupt profiles and high concentrations, even at low substrate temperatures. For example, PH3 and AsH3 have been shown to be unstable at high concentrations during silicon epitaxy [13, 38] and concentration transients after switching the gas flow were detected in RPCVD, LPCVD, and UHV/CVD during silane-based growth. Segregation and surface poisoning were observed for these dopant sources. Phosphine stabilized in SiGe, and also, by using a Cl-containing chemistry that was argued to be caused by an enhanced desorption of P from the surface and formation of volatile phosphorous chlorides at higher temperatures. In addition, when disilane rather than silane was used, the surface saturation and doping transition effects were mitigated [37] possibly due to a higher reactivity and sticking coefficient of Si2H6. A small growth rate reduction was observed for phosphorous-doping in silane and disilane. In contrast, boron incorporation is abrupt and stable at low deposition temperatures [39]. No change of concentration over time was observed during growth, except when boron was incorporated into SiGe. Although no ‘‘memory effect’’ was detected, a steady increase of concentration in SiGe and subsequent decrease in Si were observed by Lafontaine et al. [40]. The authors argued that this may be due to increased boron adsorption in the presence of germane. No noticeable change in growth rate was observed when adding B2H6 to silane [39] while disilane-based boron-doping exhibited a considerable enhancement of growth rate [37]. As depicted in Figure 2.5.4, high boron concentrations and large dynamic doping ranges are achievable in UHV/CVD. Selective epitaxial growth (SEG) during CVD is achieved by adding an appropriate amount of hydrochloric acid to the precursor mixture, which prevents nucleation on oxide and nitride by etching. This method enables the selective intrinsic and in situ doped Si and SiGe epitaxy for arbitrary thicknesses. However, temperatures in excess of 7008C are typically required because the addition of HCl suppresses Si and SiGe growth rates [41]. More recently, low-temperature thickness-limited incubation-time-based SEG has regained attention due to less required total thicknesses and stricter thermal processing budgets in high-performance integration schemes. Kiyota et al. demonstrated SEG at temperatures as low as 6608C using dichlorosilane in LPCVD [42]. Up to 3000 A˚ of Si–SiGe were selectively deposited employing the incubation period of poly-Si–SiGe on SiO2. The authors postulated that the chlorine content in SiH2Cl2 was still somewhat responsible for nuclei etching. Later, the concept of nucleation delay was extended to UHV/CVD in order to further reduce deposition temperatures. Typically, several hundred angstroms of SEG can be achieved in UHV/CVD using Cl-free silane or disilane precursor mixtures, and temperatures as low as 5508C have been demonstrated thus far for an 850 A˚ epi-base in self-aligned HBTs [43]. However, this process is not expected to be 100% selective, and small and isolated nuclei may be found on oxide and nitride areas.

2.5.5 Substrate Cleaning An oxygen- and carbon-free substrate surface is essential for smooth, single-crystalline, and defect-free epitaxy. As much as one monolayer of residual surface oxide can cause polycrystalline or amorphous rather than single-crystalline film growth. Interface contamination gives rise to increased film surface roughness and various crystal defects. Although the exact mechanism is unclear, it is argued that surface contamination reduces the diffusivity of adsorbed SiHx species [44], thus resulting in an increased initial three-dimensional growth. Boron surface contamination commonly occurs as a result of wafer handling in air, while oxide forms by reacting with oxygen and H2O vapor during transport in air and water rinses. Carbon is found as contamination in native oxide and processing liquids, such as hydrofluoric acid or DI-water. ‘‘Backstreaming’’ hydrocarbons originating from hot and turbulent pump oils can cause significant accumulation of carbon on silicon substrates processed in vacuum equipment. Other organic and metal impurities are typically found on the wafer surface after polishing steps, lithography, storage in plastic containers, and handling in air [45].

© 2006 by Taylor & Francis Group, LLC

2.5-102

The Silicon Heterostructure Handbook

Nayak et al. [44] have observed with in situ RHEED and AFM that islands evolve which grow in size during the initial stages of low-temperature growth on contaminated silicon surfaces. Upon further growth, these three-dimensional structures coalesce, and proceed as a disordered 2 1 reconstruction, but free of contamination. They concluded that cleaner interfaces yield smoother and more ordered film growth. Particularly, the pseudomorphic growth of strained layers (SiGe on Si, Si on relaxed SiGe) is affected by interfacial contamination due to enhanced dislocation nucleation [46] and threedimensional growth, visible under the microscope as haze, pitting, or islands. In the past, traditional substrate cleaning involved a combination of ex situ wet chemical etching and in situ high-temperature bake. In a production environment, the ex situ wet chemical clean typically employs an RCA-type procedure [47, 48]. Briefly, a solvating and oxidizing base mixture removes organic, particle, and some metals contamination. It is followed by an oxidizing acid-based solution in which metal contaminants are converted to soluble complexes. After rinsing, the wafers are then immersed in an HF solution to remove the surface oxide and terminate dangling silicon bonds with atomic hydrogen. This procedure has proven to result in a surface that is stable in air against re-oxidation for several minutes [13], with less than 1% coverage with residual oxygen, carbon, and boron (typical interface doses in the mid1012 cm2). The surface can be purified further employing in situ cleans. Most commonly, hightemperature bakes in a reducing atmosphere or vacuum are used. Hydrogen bakes have been reported to be effective only at temperatures above 7508C [41, 49–52] for durations of 30 sec to several minutes. HCl-based etching produces clean and smooth surfaces employing comparable temperatures [45, 53]. Vacuum bakes are typically performed in two steps. A first step at temperatures of 2508C to 2758C desorbs carbon [54], while a subsequent high-temperature bake at 6308C to 13508C for 30 sec to several minutes removes surface oxide [11, 21, 24, 28, 32]. High-temperature in situ precleans of this type are based on the reduction of SiO2 to volatile SiOx compounds. In vacuum bakes, this reduction is achieved by thermal diffusion of oxygen into the underlying substrate, while hydrogen atmosphere also promotes the reduction of the surface oxide to suboxide and water vapor. Lower substrate cleaning temperatures have been achieved employing controlled exposures to Ga molecular beams, where volatile mixed-oxide compounds were formed, which desorbed at temperatures as low as 8008C. Although clean surfaces were produced [55], applicability is limited to MBE or other ultrahigh vacuum single-wafer deposition methods. Morar et al. have shown that a submonolayer coverage of germanium yielded nonstoichiometric germanium-oxides, which desorbed at temperatures as low as 6258C [56], and proposed a low-temperature CVD batch-compatible oxide removal based on brief germane exposures. Similarly, the addition of small amounts of disilane during thermal annealing accelerates the surface oxide decomposition, and annealing temperatures as low as 7808C were successfully demonstrated [57]. Recently, ultralow temperature in situ cleans were developed, such as HF-vapor [58], downstream [59], or plasma-based cleaning. Hydrogen ECR cleaning was demonstrated to be effective in reducing interfacial contaminants at temperatures between room temperature and 6008C [60], while low-energy argon [61] and argon–hydrogen [31] ion bombardment at temperatures below 3008C and 1008C, respectively, yielded defect-free crystalline growth and proved successful in removing molecular contamination. However, higher ion energies, though more effective in removing contamination, resulted in increased surface roughness and argon incorporation [62]. Ma et al. suggested the use of broadband UV radiation in combination with O2 and Cl2 to react adsorbed hydrocarbons and metal contamination to carbon dioxide, water vapor, and volatile metal chlorides, at temperatures below 2508C [63]. The choice of a particular substrate cleaning method is dependent on various process parameters, such as allowable thermal budget, type of available reactor, or tolerable interface dose and surface roughness. For example, a production-environment hot-wall batch-type low-temperature UHV/CVD system cannot be thermally cycled due to time constraints and long-term tube integrity concerns. Therefore, high-temperature in situ precleans are not feasible, unless arranged in a cluster configuration. However, single-wafer UHV/CVD reactors can be equipped with a variety of cleaning accessories.

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-103

2.5.6 Reactors As discussed in the previous section, the use of low processing pressures and substrate temperatures during UHV/CVD permits excellent uniformities in Si and SiGe layer thickness and composition, reduces thermal dopant diffusion, and maximizes as-grown dopant electrical activation. Autodoping is minimized so that ultra-shallow and hyperabrupt junctions and alloy profiles can be formed without growth interruption. Among others, applications include high-performance SiGe heterojunction bipolar transistors, tunneling diodes, and quantum wells. To date, a variety of single-wafer and batch-type reactors are available for substrates up to 200 mm in size. They are generally constructed of stainless steel (cold-wall) or quartz-glass (hot-wall) chambers, which are evacuated to UHV pressures (<108 Torr) by turbopumps and a combination of rootsblower and mechanical pumps. In order to preserve a clean growth environment, the reactors are equipped with UHV-capable load locks and ultrapure precursor, doping, and flush gases are introduced using massflow controllers. Currently, 300 mm tools are predominantly of single-wafer type. Besides cost-related issues, incorrigible temperature gradients across the wafer and excessive chamber sizes may complicate the development of 300 mm reactors to batch-type systems. Single-wafer systems are appropriate for research and development purposes and various aspects are attractive for a manufacturing environment. For example, in situ wafer and chamber precleaning, wafer temperature sensing and uniformity by heater zoning, dynamic temperature control, substrate rotation, in situ film measurements (ellipsometry, interferometry, or spectroscopy), and advanced gas injection systems promise better repeatability, control, and tool failure rates. However, large-scale manufacturing generally requires wafer throughput values that cannot be matched using single-wafer platforms, unless profit margins allow the purchase and operation of multiple tools.

Acknowledgments I would like to acknowledge the team of scientists, engineers, analysts, and technicians at IBM for their open and interdepartmental support. In particular, I would like to thank Paul Ronsheim, Andy Turansky, Harry Hovel, and Anita Madan for outstanding analytical work and leading edge film characterization, and Joseph Kocis and David Rockwell for processing support. Furthermore, I am grateful to Toshiaki Yanagisawa, Huajie Chen, Basanth Jagannathan, Jack Chu, Kevin Chan, Ryan Wuthrich, and Wade Hodge for technical assistance and many fruitful discussions on the various details of UHV/CVD. I wish to thank my colleagues in the BiCMOS and SiGe Technology Development department for help and encouragement, and Dave Ahlgren and Ken Stein for managerial support.

References 1. J.S. Dunn, D.C. Ahlgren, D.D. Coolbaugh, N.B. Feilchenfeld, G. Freeman, D.R. Greenberg, R.A. Groves, F.J. Guarı´n, Y. Hammad, A.J. Joseph, L.D. Lanzerotti, S.A. St.Onge, B.A. Orner, J.-S. Rieh, K.J. Stein, S.H. Voldman, P.-C. Wang, M.J. Zierak, S. Subbanna, D.L. Harame, D.A. Herman Jr., and B.S. Meyerson. IBM J Res Dev 47: 101–139, 2003. 2. S.M. Sze. VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988. 3. P.M. Garone, V. Venkataraman, and J.C. Sturm. IEEE Electron Dev Lett 13: 56–58, 1993. 4. T.G. Jung, C.Y. Chang, C.S. Liu, T.C. Chang, H.C. Lin, W.C. Tsai, G.W. Huang, and L.P. Chen. J Appl Phys 76: 4921–4923, 1994. 5. L.-E. Wernersson, S. Kabeer, V. Zela, E. Lind, J. Zhang, W. Seifert, T. Kosel, and A. Seabaugh. Electron Lett 40: 83–85, 2004. 6. P.S. Chen, Y.T. Tseng, M.-J. Tsai, and C.W. Liu. Semiconductor Manufacturing Technology Workshop, December 10–11, 2002, pp. 145–148. 7. W. Lu, A. Kuliev, S.J. Koester, X.-W. Wang, J.O. Chu, T.-P. Ma, and I. Adesida. IEEE Trans Electron Devices 47: 1645–1652, 2000.

© 2006 by Taylor & Francis Group, LLC

2.5-104

The Silicon Heterostructure Handbook

8. Y.M. Lin, S.L. Wu, S.J. Chang, S. Koh, and Y. Shiraki. IEEE Electron Dev Lett 24: 69–71, 2003. 9. A. Gupta, S.P. Levitan, L. Selavo, and D.M. Chiarulli. Proceedings of 17th International Conference on VLSI Design, 2004, pp. 957–960. 10. J. Kolodzey, P.R. Berger, B.A. Orner, D. Hits, F. Chen, A. Khan, X. Shao, M.M. Waite, S.I. Shah, C.P. Swann, and K.M. Unruh. J Cryst Growth 157: 386–391, 1995. 11. T.R. Bramblett, Q. Lu, T. Karasawa, M.-A. Hasan, S.K. Jo, and J.E. Greene. J Appl Phys 76: 1884– 1888, 1994. 12. B.S. Meyerson. Appl Phys Lett 48: 797–799, 1986. 13. B.S. Meyerson. Proc IEEE 80: 1593–1608, 1992. 14. B.S. Meyerson. U.S. Patent 5,906,680, 1999. 15. P. Meunier-Beillard, M. Caymax, K. Van Nieuwenhuysen, G. Doumen, B. Brijs, M. Hopstaken, L. Geenen, and W. Vandervorst. Appl Surf Sci 224: 31–35, 2004. 16. M. Hierlemann and C. Werner. Mater Sci Sem Proc 3: 31–39, 2000. 17. P.J. Robinson and K.A. Helbrook. Unimolecular Reactions. New York: Wiley Interscience, 1972. 18. A.M. Dean. J Phys Chem 89: 4600–4608, 1985. 19. S.M. Gates, C.M. Greenlief, S.M. Kulkarni, and H.H. Sawin. J Vac Sci Technol A 8: 2965–2969, 1990. 20. S. Hong and M.Y. Chou. Phys Rev B 58: R13363–R13366, 1998. 21. P.-H. Wu and D.-S. Lin. Phys Rev B 57: 12421–12727, 1998. 22. W.K. Liu, S.M. Mokler, N. Ohtani, C. Roberts, and B.A. Joyce. Surf Sci 264: 301–311, 1992. 23. A.R. Laracuente and L.J. Whitman. Surf Sci 545: 70–84, 2003. 24. J.J. Boland. Phys Rev B 44: 1383–1386, 1991. 25. K. Sinniah, M G. Sherman, L.B. Lewis, W.H. Weinberg, J.T. Yates, and K.C. Janda. Phys Rev Lett 62: 567–570, 1989. 26. C.M. Greenlief and M. Armstrong. J Vac Sci Technol B 13: 1810–1815, 1995. 27. R. Walsh. Acc Chem Res 14: 246–252, 1981. 28. S.M. Gates. Surf Sci 195: 307–329, 1988. 29. A.M. Beers and J. Bloem. Appl Phys Lett 41: 153–155, 1982. 30. N. Gonohe, S. Shimizu, K. Tamagawa, T. Hayashi, and H. Yamakawa. Jpn J Appl Phys 26: L1189– L1192, 1987. 31. J. Ramm. III Vs Rev 15(7): 42–45, 2002. 32. F.W. Smith and G. Ghidini. J Electrochem Soc 129: 1300–1306, 1982. 33. G. Ghidini and F.W. Smith. J Electrochem Soc 131: 2924–2928, 1984. 34. A.S. Segal, S. Yu. Karpov, A.P. Sid’ko, and Yu. N. Makarov. J Cryst Growth 225: 268–273, 2001. 35. D.C. Houghton. J Appl Phys 70: 2136–2151, 1991. 36. J.H. Comfort and R. Reif. J Electrochem Soc 136: 2386–2398, 1989. 37. C. Li, S. John, E. Quinones, and S. Banerjee. J Vac Sci Technol A 14: 170–183, 1996. 38. W.B. De Boer, D. Terpstra, and J.G.M. Van Berkum. Mater Sci Eng B 67: 46–52, 1999. 39. B.S. Meyerson, F.K. LeGoues, T.N. Nguyen, and D.L. Harame. Appl Phys Lett 50: 113–115, 1987. 40. H. Lafontaine, D.C. Houghton, D. Elliot, N.L. Rowell, J.-M. Baribeau, S. Laframboise, G.I. Sproule, and S.J. Rolfe. J Vac Sci Technol B 14: 1675–1681, 1996. 41. S. Bodnar, C. Morin, and J.L. Regolini. Thin Solid Films 294: 11–14, 1997. 42. Y. Kiyota, R. Udo, T. Hashimoto, A. Kodama, H. Shimamoto, R. Hayami, E. Ohue, and K. Washio. IEEE Trans Electron Dev 49: 739–745, 2002. 43. K. Washio. IEEE Trans Electron Dev 50: 656–668, 2003. 44. S. Nayak, D.E. Savage, H.-N. Chu, M.G. Lagally, and T.F. Kuech. J Cryst Growth 157: 168–171, 1995. 45. H. Habuka and T. Otsuka. U.S. Patent 6,235,645, 2001. 46. S.R. Stiffler, J.H. Comfort, C.L. Stanis, D.L. Harame, E. de Fre´sart, and B.S. Meyerson. J Appl Phys 70: 1416–1420, 1991. 47. W. Kern and D.A. Puotinen. RCA Rev 31: 187–205, 1970. 48. S. Shwartzman. U.S. Patent 4,261,791, 1981.

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-105

49. A. Abbadie, J.M. Hartmann, P. Holliger, M.N. Semeria, P. Besson, and P. Gentile. Appl Surf Sci 225: 256–266, 2004. 50. M.S. Carrol, J.C. Sturm, and M. Yang. J Electrochem Soc 147: 4652–4659, 2000. 51. R. Loo, M. Caymax, I. Peytier, S. Decoutere, N. Collaert, P. Verheyen, W. Vandervorst, and K. De Meyer. J Electrochem Soc 150: G638–G647, 2003. 52. M. Caymax, R. Loo, B. Brijs, W. Vandervorst, D.J. Howard, K. Kimura, and K. Nakajima. Mater Res Soc Symp Proc 533: 339–344, 1998. 53. J.F. Gibbons, C.M. Gronet, and K.E. Williams. Appl Phys Lett 47: 721–723, 1985. 54. S.S. Iyer, M. Arienzo, and E. de Fre´sart. Appl Phys Lett 57: 893–895, 1990. 55. S. Wright and H. Kroemer. Appl Phys Lett 36: 210–213, 1980. 56. J.F. Morar, B.S. Meyerson, U.O. Karlson, F.J. Himpsel, F.R. McFreely, D. Rieger, A. Taleb-Ibrahimi, and J.A. Yarnoff. Appl Phys Lett 50: 463–465, 1987. 57. K. Nozawa, K. Katayama, Y. Kanzawa, G. Sugahara, T. Saitoh, and M. Kubo. Mater Res Soc Symp Proc 569: 83–88, 1999. 58. M. Caymax, S. Decoutere, E. Rohr, W. Vandervorst, M. Heyns, H. Sprey, A. Storm, and J.-W. Maes. Diffus Def Data pt B 65–66: 237–240, 1999. 59. H. Ogawa, T. Arai, M. Yanagisawa, T. Ichiki, and Y. Horiike. Jpn J Appl Phys 41: 5349–5358, 2002. 60. H.W. Kim, K.S. Kim, and J.H. Lee. Met Mat Int 8: 183–190, 2002. 61. T. Ohmi, K. Hashimoto, M. Morita, and T. Shibata. IEDM, 1989, pp. 53–56. 62. J.C. Bean, G.E. Becker, P.M. Petroff, and T.E. Seidel. J Appl Phys 48: 907–913, 1977. 63. Y. Ma, M.L. Green, L.C. Feldman, J. Sapjeta, K.J. Hanson, and T.W. Weidman. J Vac Sci Technol B 13: 1460–1465, 1995. 64. S.-H. Lim, S. Song, T.-S. Park, and E. Yoon. J Vac Sci Technol B 21: 2388–2392, 2003. 65. T.J. Donahue and R. Reif. J Electrochem Soc 131: 1691–1697, 1886. 66. J.L. Regolini, D. Bensahel, Y.I. Nissim, J. Mercier, E. Scheid, A. Perio, and E. Andre. Electron Lett 24: 408–409, 1988.

© 2006 by Taylor & Francis Group, LLC

2.6 Defects and Diffusion in SiGe and Strained Si 2.6.1 2.6.2

Introduction............................................................... 2.6-107 Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge ......................... 2.6-109 The Lattice Vacancy and Vacancy–Impurity Complexes in Si . The Lattice Vacancy and Vacancy–Impurity Complexes in Ge . The Silicon Interstitial and Interstitial-Related Interactions in Si . The Germanium Interstitial and Interstitial-Related Interactions in Ge

2.6.3

Effects of SiGe Alloy Composition and Strain on Defect Characteristics.......................................... 2.6-112 Effect of Alloy Composition on the Formation Energies of Intrinsic Defects in SiGe . Effect of Alloy Composition on Electronic Properties of Defects in SiGe . Effect of Strain on Defect Characteristics

2.6.4

Specific Defects in SiGe ............................................ 2.6-114 Shallow Dopants . Radiation (Implantation)-Induced Defects . Metallic Impurities

2.6.5

A.R. Peaker and V.P. Markevich University of Manchester

Diffusion .................................................................... 2.6-115 The General Picture . Self-Diffusion in Unstrained Si1xGex . Dopant Diffusion in Unstrained SiGe . The Impact of Strain and Interfaces on Diffusivity

2.6.6 2.6.7

Dislocations................................................................ 2.6-122 Summary .................................................................... 2.6-122

2.6.1 Introduction Defects play a crucial role in semiconductor processing and in finished devices by mediating diffusion, defining junction leakage, and controlling carrier recombination. As a result, issues as wide ranging as junction depth, noise, and memory retention time are critically dependent on the defect population. By far the most important source of point defects is the ion implantation process, which produces high concentrations of intrinsic defects (self-interstitials and vacancies). The issues regarding diffusion enhancement in silicon by intrinsic defects have been studied in great detail in relation to small devices and although some work exists for the SiGe case, the problem is vastly more complicated because of the interaction of defects with strain, interfaces, and, in some cases, the introduction of dislocations. In this section of the handbook we consider briefly the principles behind these effects and then review the relevant literature on point defects and defect complexes in silicon, in germanium, and in silicon– germanium. We consider the electronic properties of the defects and in particular their position in the bandgap and as a consequence the likely effects on the electrical behavior of devices. The recent literature on diffusion in SiGe and strained Si is reviewed and the effects of point defects on diffusion are 2.6-107 © 2006 by Taylor & Francis Group, LLC

2.6-108

The Silicon Heterostructure Handbook

considered along with the impact of strain on diffusivities of the common dopants. Finally we look at the significance of dislocations in relation to device performance. Much of our understanding of ion implantation defects in silicon and their annealing kinetics is based on studies of electron-irradiated silicon. A high-energy electron will displace an atom in the semiconductor matrix to produce a vacancy and an interstitial as a Frenkel pair. The interstitial is quite mobile and diffuses either to react with a vacancy or substitutional impurities or to add to the surface of the crystal. The remaining vacancies pair with impurities in the immediate vicinity of the displacement or with themselves to form divacancies. The most common reaction products in Si and SiGe are the vacancy–oxygen pair and the divacancy. However there are very substantial differences between the point defects introduced by electron damage and the defects commonly seen in ion-implanted semiconductors. As the mass and energy of the implanted species increases, a more complex population of defects is created. There is clear evidence that this is due to clusters of interstitials or vacancies depending on the depth below the surface relative to the implant range. Many of the vacancies and interstitials recombine to reconstitute the lattice, others react with each other to form clusters of vacancies or clusters of interstitials. Such clusters result in relatively stable entities, which may dissociate during the annealing process used to activate the implanted dopants. The released point defects can result in substantial changes in the diffusivity of the dopants. By far the best known example is the enhancement of boron diffusivity in silicon by excess of self-interstitials in which the diffusivity is increased by several orders of magnitude. The generation of intrinsic defects is very nonuniform throughout the ion path, with the majority of defects created near the end of range. Redistribution of the defects at the implant temperature results in a vacancy-rich region near the surface and an interstitial-rich region just beyond the concentration peak of the implanted species. On annealing, particularly under oxidizing conditions where the surface cannot act as a sink for the interstitials, extrinsic stacking faults with their bounding Frank partial dislocation loops can be formed at the end of the implant range. These accommodate the excess of selfinterstitials locally as an extra plane of atoms. Some of the defects react with impurities (dopants, carbon, oxygen, and hydrogen) during the annealing process. However the majority of these defects can be removed from the active region of the device provided the device design will withstand a sufficient thermal budget. In the next section we examine the populations of defect complexes that evolve and their position in the bandgap. This is an issue of crucial importance in relation to device-significant properties. Figure 2.6.1 shows the conceptual behavior of such defect levels in terms of their behavior as generation, recombination, or trapping centers. Process (A) is the dominant mechanism affecting the generation lifetime. It is a very important process in memory applications particularly DRAM but can also be a major contributor to CMOS quiescent current. In Si and SiGe, process (D) is the dominant mechanism

Conduction band en

Cn en

(A)

Cn

(B) (D)

(C) ep ep

Cp Cp

Valence band

FIGURE 2.6.1 The classic Shockley–Hall–Read representation of (A) a generation center, (B) an electron trap, (C) a hole trap, and (D) a recombination center.

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-109

in defining the recombination lifetime; it is important in bipolar devices and can have a defining influence on the base transport factor and hence the gain in some transistor structures. The trapping processes (B) and (C) are potential sources of noise. In practice the noise frequency is low and in general trapping processes are regarded as contributors to 1/f noise and in consequence are of most significance in analog circuits, particularly RF mixers. If such centers are present in very high concentrations, the charge they store can shift the operating point of devices, either slowly with time or after overload conditions.

2.6.2 Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge The Lattice Vacancy and Vacancy–Impurity Complexes in Si The isolated lattice vacancy in Si has been identified by electron paramagnetic resonance (EPR) in both its paramagnetic single positive (Vþ) and negative (V) charge states after in situ electron irradiation at cryogenic temperatures (4.2 to 20.4 K) [1, 2]. It was found that the vacancy can take on five different charge states in the silicon band gap: (þþ), (þ), (0), (), and ( ). The information available on the electronic and structural properties of the vacancy is summarized in Table 2.6.1. The EPR spectra of the isolated vacancy disappear after a 15-min annealing at 70 K in n-type Si, 150 K in p-type, and 200 K in high-resistivity material [1, 2]. The disappearance is argued to be related to the long-range diffusion of the vacancy, and the difference in the annealing temperatures is caused by the different values of the activation energy for the vacancy migration in different charge states. The activation energies for migration were determined as 0.18 + 0.02 eV for V , 0.45 + 0.04 eV for V0, and 0.32 + 0.02 eV for Vþþ [1, 2]. The disappearance of the EPR spectra of the isolated vacancy is accompanied by the appearance of other EPR signals, which are identified as due to vacancies paired with other defects. The Si vacancy forms pairs with group V donor atoms (P, As, Sb) as well as with oxygen, germanium, tin, and some other impurity atoms [1–5]. The interaction of two vacancies was found to result in the formation of the divacancy. The information available on the electronic properties, symmetry, and thermal stability of some vacancy-related point defects is presented in Table 2.6.1. Important issues to be considered in relation to diffusion problems are equilibrium concentrations of intrinsic defects at high temperatures. The equilibrium concentration of a point-defect species X can be expressed as [6]: f Cx DGxf DSx DHxf ¼ Qx exp exp ¼ Qx exp Cs kT k kT where DG xf, DHxf, and DS xf are, respectively, Gibbs free energy, the enthalpy, and the entropy changes related to the formation of one defect X. DSxf has a configurational contribution and a vibrational contribution that arises from a change in the lattice vibrational frequency spectrum in the vicinity of X: DSxf ¼ DSxf ,c þ DSxf ,v The term Qx is the number of equivalent, distinguishable configurations that X can take (per lattice site); for a given lattice site, at most, one of the Qx configurations that are associated with it can be occupied at any time. Cs is the number of available lattice sites in the crystal (i.e., number of substitutional sites, tetrahedral interstitial sites, etc.). It should be mentioned that there are no experiments where equilibrium concentrations of vacancies or interstitials in Si have been measured definitely. Estimates of the vacancy formation enthalpy based on experimental studies gave the values in the range of 2 to 3.2 eV [4, 7], while the values obtained from theoretical calculations are higher, 3.5 to 3.7 eV [8, 9].

© 2006 by Taylor & Francis Group, LLC

2.6-110

The Silicon Heterostructure Handbook

TABLE 2.6.1 Charge States in the Gap, Symmetry, Position of Energy Levels, and Temperature Ranges of Annealing Out for the Most Abundant Vacancy-Related Defects in Si (from Refs. [2, 3] unless indicated) (Question Marks Indicate the Data that Are Doubtful)

Defect

Charge States

Vacancy

Vacancy—oxygen Vacancy—phosphorus Vacancy—antimony Vacancy—germanium

Divacancy

Vacancy—boron Vacancy—aluminum

0 þ þþ – 0 – 0 0 0 þ þþ 0 þ 0 þ 0

Configuration (Point-Group Symmetry) At Low Temperatures C2v C2v D2d D2d Td C2v C2v — C2h — C2h — —

D3d C2h C2h C2h C1h — C3v —

Energy Levels E( /) Ec0.17 eV E(/0) ¼ Ec0.57 eVa (?) E(0/þ) ¼ Evþ0.05 eV E(þ/þþ) ¼ Evþ0.13 eV

Annealing Out Temperature Ranges (8C) (15–30 min Isochronal) (225) to (175) (75) to (25)

E(/0) ¼ Ec0.17 eV

(125) to (75) 325–375

E(/0) ¼ Ec0.43 eV

100–175

E(/0) ¼ Ec0.44 eV

175–225

E( /) ¼ Ec0.29 eVb (?) —

(75) to (25)

E( /) ¼ Ec0.24 eV E(/0) ¼ Ec0.43 eV E(0/þ) ¼ Evþ0.20 eV

225–300

—

(25) to 25

— 225–275

a

From PM Fahey, PB Griffin, and JD Plummer. Point defects and dopant diffusion in silicon. Reviews of Modern Physics 61:289–388, 1989. With permission. b From CV Budtz-Jorgensen, P Kringhoj, A Nylandsted Larsen, and NV Abrosimov. Deep-level transient spectroscopy of the Ge-vacancy pair in Ge-doped n-type silicon. Physical Review B 58:1110–1113, 1998. With permission.

The Lattice Vacancy and Vacancy–Impurity Complexes in Ge In contrast to the silicon case, reliable information available on the properties of the lattice vacancy and vacancy–impurity complexes in crystalline Ge is rather limited. According to recent theoretical calculations [10, 11], the structure and electronic properties of the vacancy in Ge are similar to those of the vacancy in Si: the vacancy in Ge is present as five charge states: (þþ), (þ), (0), (), and ( ). However, the magnitudes and energies of Jahn–Teller distortions were found to be smaller for the vacancy in Ge compared to Si. Comparison with the results for silicon showed that the vacancy formation energies in germanium (from 1.7 to about 2.5 eV) are significantly smaller than in silicon, for all charge states, which makes the vacancy much more important for diffusion in Ge than in Si [10]. Very little information on the positions of energy levels of the isolated vacancy and activation energies for the vacancy migration in Ge is available. However, it was suggested recently on the basis of perturbed angular correlation (PAC) spectroscopy measurements that the (/0) energy level of the Ge vacancy should be at about Ev þ (0.2 + 0.04) eV [12]. A PAC signal, which was assigned to a complex of a 111In atom with a vacancy nearby, appeared upon annealing at temperatures around 200 K

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-111

in Ge samples subjected to electron irradiation at 77 K. It was proposed that this process is related to the long-range migration of neutral vacancies, and the activation energy for the V0 diffusion was estimated as 0.6 + 0.1 eV [12]. Regarding the vacancy diffusivity in Ge, there is another study [13], the results of which look inconsistent with the results obtained from PAC measurements. It was found by Whan [13] that in oxygen-rich Ge samples, which were electron-irradiated at 25 K, oxygenrelated LVM lines emerged upon annealing in the temperature range 45 to 80 K. These lines were associated with vacancy–oxygen complexes, and the above observation was considered as an evidence for the vacancy diffusion in Ge at low (50 K) temperatures. It might be possible, however, that the vacancy diffusion occurred in different charge states in PAC [12] and infrared (IR) absorption [13] measurements. As in the case of silicon, there are some strong indications that the vacancy in Ge can interact with oxygen and group V donor atoms (P, As, Sb, Bi) with the formation of complexes stable at room temperature. It was shown recently in a combined deep-level transient spectroscopy (DLTS) and IR absorption spectroscopy study that the vacancy–oxygen complex in Ge can exist in three charge states: ( ), (), and (0), with the corresponding energy levels at about E( /) ¼ Ec 0.21 eV and E(/0) ¼ Ev þ 0.27 eV [14, 15]. Strong arguments were presented recently that the Sb–V vacancy in Ge introduces two acceptor levels in the gap at about E( /) ¼ Ec 0.20 eV and E(/0) ¼ Ev þ 0.30 eV [16, 17]. The Sb–V complex in Ge annealed out in the temperature range 140 to 1808C [16, 17].

The Silicon Interstitial and Interstitial-Related Interactions in Si In contrast to the isolated vacancy, the isolated self-interstitial has not been observed directly either in p-type or n-type Si after low-temperature electron irradiation, and the structure and electronic properties of the Si self-interstitial are not known definitely [3]. In p-type Si after low temperature irradiation, EPR signals due to defects which were identified as interstitials trapped at impurities were observed and the same concentration as isolated vacancies. It is argued that the isolated interstitial atoms must be highly mobile in p-type material, even at 4.2 K. There is also strong evidence for lowtemperature (<175 K) long-range migration of Si self-interstitials in n-type Si. Si self-interstitials were found to interact effectively with group III acceptor atoms (B, Al) and substitutional carbon atoms [3]. Information available on electronic properties and thermal stability of the first generation trapped interstitials (Ali Bi, Ci) is given in Table 2.6.2. It was found that these defects can, in turn, migrate over long distances and form pairs with other defects. Table 2.6.2 shows information on the properties of some of these second generation interstitial defects. The values of formation enthalpy of the Si self-interstitial estimated on the basis of some experimental studies are in the range of 3.2–3.8 eV [4, 21]. These values are close to those obtained from theoretical calculations, 3.2–3.7 eV [8, 9].

The Germanium Interstitial and Interstitial-Related Interactions in Ge Reliable information available on the properties of the Ge self-interstitial and its interaction with impurities in crystalline germanium is rather limited. It was found in a recent theoretical study that the Ge interstitial could be an amphoteric defect with an acceptor and a donor level in the gap [22]. For all the charge states the h1 1 0i-split dumbbell configuration was found to be the energetically favored one. The formation energy for the neutral Ge interstitial (2.3 eV) was found to be significantly lower than the corresponding value for Si (3.2 eV) according to the calculations [22]. It was suggested in a recent study based on PAC measurements that Ge self-interstitial has an energy level at about Ec 0.04 eV and is mobile, either in neutral or in singly positively charged state, at temperatures above 220 K [12]. The activation energy for the diffusion was estimated as 0.6 + 0.1 eV.

© 2006 by Taylor & Francis Group, LLC

2.6-112

The Silicon Heterostructure Handbook

TABLE 2.6.2 Charge States in the Gap, Position of Energy Levels, and Temperature Ranges of Annealing Out for the Most Abundant Interstitial-Related Defects in Si Defect

Ali

Bi

Ci

Bi–Oi Ci–Oi Ci–Cs

Charge States

0 þ þþ 0 þ 0 þ þ þþ 0 þ 0 þ

Energy Levels

— E(þ/þþ) ¼ Evþ0.17 eV

Annealing Out Temperature Ranges (8C) (15–30 min Isochronal) — 175–225a —

E(/0) ¼ Ec0.37 eV E(0/þ) ¼ Ec0.13 eV (25) to 25a E(/0) ¼ Ec0.10 eV E(0/þ) ¼ Evþ0.28 eV

50–100

E(þ/þþ) ¼ Ec0.27 eVb (?) E(0/þ) ¼ Evþ0.35 eV

150–200 350–400

E(/0) ¼ Ec0.16 eV E(0/þ) ¼ Evþ0.09 eVc

225–275

a

Annealing out of Bi and Ali is free-carrier injection dependent, much faster upon injection conditions; see Refs. [3, 18]. b From PM Money, LI Cheng, M Su¨li, JD Gerson, and JW Corbett. Defect energy levels in boron-doped silicon irradiated with 1-MeV electrons. Physical Review B 15: 3836–3843, 1977. With permission. c The Ci–Cs is a bistable defect; see Ref. [20] for the details of its electronic structure. Source: From GD Watkins. Vacancies and interstitials and their interactions with impurities in c-Si. Properties of Crystalline Silicon (EMIS Data Review Series No. 20), R. Hull (ed.), INSPEC, London, 1999, chapter 11.1, pp. 643–652. With permission.) (Question Marks Indicate The Data that Are Doubtful)

2.6.3 Effects of SiGe Alloy Composition and Strain on Defect Characteristics Effect of Alloy Composition on the Formation Energies of Intrinsic Defects in SiGe The effect of SiGe alloy composition on the formation energy of vacancies has been studied by ab initio calculations in Refs. [23–25]. There was a consensus that the formation energy of a vacancy in Si1xGex alloys drops by about 0.2 to 0.25 eV for each Ge atom surrounding the vacancy. The energy of the system with a vacancy was found to drop by 0.04 eV for every second nearest-neighbor Ge atom to the vacancy [25]. There are no reliable data on the effect of SiGe alloy composition on the self-interstitial formation energy.

Effect of Alloy Composition on Electronic Properties of Defects in SiGe Electronic properties of defects in SiGe alloys have been considered recently in Ref. [26]. It was argued that there are three types of behavior a defect may exhibit in the Si1xGex alloys. First, the core of the defect might be occupied with Ge atoms and consequently the properties of the center are quite different from those of the defect in pure Si. Second, the change in the lattice parameter can cause the vibrational modes or energy levels to shift often in a linear way for dilute concentrations of Ge, and third, the presence of Ge atoms affect the conduction and valence bands in a way beyond the change in bond length and this has an influence on the lattice parameter and other properties. It is often difficult to distinguish these three effects in the alloy experimentally, but the recently developed technique of Laplace deep-level transient spectroscopy (LDLTS) [27] has enabled them to be separated

© 2006 by Taylor & Francis Group, LLC

2.6-113

Defects and Diffusion in SiGe and Strained Si

in some cases and so used to study the local environment of defects [26, 28]. As an example, Figure 2.6.2 shows results of a study of the siting of Au in SiGe. The populations could be quantified and so it was possible to state that gold has a strong preference to site in the vicinity of germanium [28]. Each of the three above mentioned effects might cause changes in diffusivity of defects and binding energies of complexes.

Effect of Strain on Defect Characteristics

Laplace DLTS amplitude

The application of uniaxial or biaxial stress to a semiconductor changes the equilibrium population of interstitials and vacancies. These effects are significant enough to change diffusion coefficients [29] as will be discussed later. Stress modifies other important parameters, such as the formation of interstitial dislocation loops after implantation and the behavior of implantation-induced point defects. The effect of strain on point defects is to lift the degeneracy so that the electronic behavior is different in different directions. This can be observed as a splitting of the properties in techniques with sufficient resolution; classically this has been done in optical absorption, electron spin resonance, and photoluminescence. Unfortunately, these techniques cannot be used on thin layers, but the application of LDLTS [27] allows the direct measurements of electronic properties and the observation of defect motion in thin epitaxial layers under uniaxial stress. An example is given in Figure 2.6.3 for the divacancy [30]. In this experiment, compressive stress is applied to the sample during measurements and the splitting can be observed as a function of stress. Combined with heating, the same technique can be used to study the motion of impurities in strained silicon. In this case, the impurity is aligned at a temperature above that used for the measurement and then cooled to the measurement temperature. The motion can be observed as a function of annealing and activation energies for the process extracted in the usual way. This motion, on an atomic scale, is at the heart of diffusion mechanisms and these novel techniques for observing and quantifying it have the potential to give us a much deeper understanding of the mechanisms involved than the traditional top–down approach and these mechanisms are normally the basis of diffusion studies in more conventional systems.

SiGe: Au 5% Ge at T = 248 K 0

Si

Ge 1 2 1

10 100 1000 Emission rate (s−1)

FIGURE 2.6.2 Electron emission from gold in Si0.95Ge0.05 with a flat diagram representation of first and second nearest neighboring atoms. The labelling on the peaks represents emission from gold with 0, 1, or 2 Ge atoms in the first nearest-neighbor position. (Adapted from L Dobaczewski et al. Physical Review Letters 83: 4582–4585, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

FIGURE 2.6.3 The effect of uniaxial stress on the dominant ion implantation defect in silicon. The stress lifts degeneracy and shifts in the electron binding energy are observed as line splitting. (Adapted from L Dobaczewski et al. Physical Review B 65: 113203-1 to 113203-4, 2002. With permission.)

2.6-114

The Silicon Heterostructure Handbook

2.6.4 Specific Defects in SiGe Shallow Dopants Phosphorus donors have been studied in Si-rich Si1xGex alloys (0 x 0.27) by means of IR absorption [31]. A weak shift of the activation energy with germanium content was found: E(A1) ¼ (45.5 26x) meV. This was explained by multivalley effective mass theory with a phenomenological central cell potential, which does not depend on alloy composition within the investigated range. The experiments showed that P atoms are distributed at random in the alloy and that their positions are uncorrelated to those of the Ge atoms. Boron–germanium pairs were detected in Si-rich Si1xGex alloys (0 x 0.075) by means of b-nuclear magnetic resonance (NMR) technique [32]. It was found that the binding energy of the B–Ge pair is low and the probability of the formation of the complex matches with statistical expectations.

Radiation (Implantation)-Induced Defects Vacancy-Related defects The effect of SiGe alloy composition on the electronic properties and thermal stability of vacancy–donor (P, Sb) atom pairs was studied by means of DLTS in strain-relaxed Si1xGex samples (0 x 0.25), which were grown by the molecular beam epitaxy (MBE) technique [33]. It was found that the activation enthalpy of electron ionization from the single acceptor level of the Sb–V pair increases from 0.41 to 0.51 eV with the increase in Ge content [33]. Recent positron annihilation spectroscopy study showed that Ge atoms are effective sinks for mobile phosphorus–vacancy pairs in strained Si-rich SiGe samples [34]. The V–P–Ge complex was found to anneal out at about 2008C. The 508C higher annealing temperature of the V–P–Ge complex corresponds to about 0.1 to 0.2 eV larger binding energy than that of the V–P pair [34]. Electronic properties of vacancy–oxygen complexes in SiGe alloys were investigated recently in a combined DLTS and ab initio modeling study [26]. Bulk unstrained Czochralski-grown SiGe samples irradiated with electrons were studied. At least three configurations of the VO centers were identified in SiGe alloys. The most stable configuration consists of a Si–O–Si unit and a Ge–Si reconstructed bond in a vacancy. This configuration was found to be about 0.2 eV more stable than separated VO and Ges defects and possesses an acceptor level, which is about 25 meV deeper compared to the level of the VO center without a Ge atom in a nearest-neighbor site. The increase of the ionization enthalpy of the VO complexes with the increase in Ge content in Si1xGex crystals (the rate of the increase was determined to be about 0.55x eV) was associated with changes in the average Si–Si bond length [26]. The energy levels of the divacancy have been studied in epitaxially grown, strain-relaxed Si1xGex as a function of x for 0 x 0.5, using DLTS on particle-irradiated pþn and nþp diodes [35]. The two acceptor levels situated in the upper half of the bandgap in Si (see Table 2.6.1) were found to move gradually deeper into the gap with increasing x and the single-acceptor level crosses the midgap for x 0.25, from then on the change of energy changes slope with x . The donor level in the lower half of the bandgap becomes gradually more shallow, pinned to the conduction band. The annealing temperature of the divacancy was found to be independent of composition in the investigated composition range [35]. Interstitial-Related defects DLTS has been used to study electronic properties and annealing behavior of Ci and CiCS defects, created by proton or electron irradiation in strain-relaxed, epitaxial Si1xGex of 0.005 x 0.5 [36, 37]. It was shown that neither the acceptor levels of Ci and CiCS nor the donor levels of the Ci center are pinned to any of the band edges when the composition of the Si1xGex was varied. The electron ionization enthalpies of the acceptor levels were found to increase with a rate dDH/dx 0.3 eV/x . The two levels of the Ci defect

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-115

remained at an energy of 0.8 eV separation from each other, independent of composition. The migration enthalpy of Ci was found to be independent of composition (DHm 0.75 eV) in the investigated composition range, 0 x 0.15. The experimentally observed increased stability of Ci with increasing x was argued to be due to a dramatic decrease of the entropy of migration of the Ci defect. It was argued that the entropy is a crucial parameter when discussing dynamic effects in disordered materials [37]. Electronic properties of the Ci–Oi complex were investigated recently in bulk unstrained Czochralskigrown Si1xGex samples irradiated with electrons. The enthalpy of hole ionization for the single donor level of the complex relative to the valence band edge, DHp, was found to decrease with a rate d(DHp)/dx ¼ 0.96 eV upon increase in Ge content [38]. The level is not pinned to the conduction band edge or to the valence band edge.

Metallic Impurities DLTS and high-resolution LDLTS techniques have been also used to study effects of SiGe alloy composition and strain on the electronic properties of 3d transition metal (Fe, Ti, Cr, Ni) and 5d noble metal (Au, Pt) impurities [39–43]. It was found that, as a rule, in strain-relaxed Si1xGex alloys metal-related energy levels in the lower part of the bandgap move towards the valence band edge with increasing Ge content [39–43]. For the metal-related energy levels in the upper part of the gap both the increase and decrease in activation energies for ionization relative to the conduction band edge were observed upon the increase in Ge content [39–42]. Activation energies of ionization of both electron and hole traps related to metallic impurities were found to increase with the increase of strain in SiGe alloys [41]. The strain dependence was described in terms of the deep state uniaxial and hydrostatic deformation potentials. The difference between the deep state activation energies in Si and Si1xGex did not agree with the independently determined Si–Si1xGex band offsets [41, 42]. This demonstrated that the concept of 3d state as an independent, internal reference level, well established for III–V and II–VI compounds, fails in the case of group IV semiconductors [41, 42].

2.6.5 Diffusion The General Picture Diffusion of the common dopants (boron, phosphorous, arsenic, and antimony) in silicon–germanium alloys is inherently more complex than in the elemental semiconductors. In general, diffusion proceeds via the interaction of the dopant species with point defects. In this case these are predominantly the silicon and germanium interstitials and vacancies. An example of the significance of the importance of intrinsic defects is the diffusion of boron in silicon. There have been numerous studies of the release of interstitials from clusters of silicon atoms formed during ion implantation [44, 45]. The dissociation of these clusters during annealing is the basis of enhanced diffusion with diffusivity increases of several orders of magnitude. This has proved to be an immense problem in producing silicon devices with small feature sizes. In contrast species such as antimony, in which diffusion is mediated by vacancies, exhibit a reduced diffusivity in the presence of excess of interstitials. In the alloy the presence of two species results in parallel mechanisms for diffusion. In the general case a classical Arrhenius dependence of the diffusivity D on the temperature T is observed and so we can express the vacancy and interstitial contributions separately: D¼

D0I

I V Ea Ea V exp þ D0 exp kT kT

The activation energies are each derived from two components namely the energy required to form the intrinsic defect and the migration energy. In principle both of these components might be expected to

© 2006 by Taylor & Francis Group, LLC

2.6-116

The Silicon Heterostructure Handbook

depend on composition of the alloy. For example, the energy required to form a vacancy will depend on the local environment, i.e., how many germanium atoms occupy the four first nearest-neighbor sites. According to the dominant mechanism the diffusion of a particular species is referred to as being interstitially mediated or vacancy mediated. However, another major difference is the presence of strain, which, among other things, alters the equilibrium concentration of intrinsic defects. It is now generally accepted that the formation energy of the self-interstitial increases with increasing compressive strain and decreases with increasing tensile strain. Strain is present in most SiGe systems of technological interest and in general the strained layers are rather thin bounded by heterojunctions or surfaces. The surfaces and interfaces perturb the vacancy and interstitial populations. In the case of the surface the presence of oxide introduces additional interstitials while a nitrided surface will introduce excess vacancies. This is well documented for the case of silicon but has not been studied in the same detail for germanium or germaniumrich alloys. In consequence it is very important to deconvolute the effects of alloy composition from that of strain and the effects of interface proximity. Attempts have been made to do this by modeling [46]. Experimentally the simultaneous presence of strain and alloy effects makes quantifying diffusivity in SiGe extremely difficult with many experimental pitfalls. In consequence there are considerable differences in the literature in absolute values. However, it is possible to measure diffusivity in unstrained SiGe although it is important that the unstrained state is not achieved through relaxation via dislocation formation. This is because the presence of these extended defects at diffusion temperatures modulates the intrinsic defect population and introduces localized strain. In this review, we have focussed on studies of single-crystal material with low dislocation density, ignoring some of the older work on polycrystalline or highly dislocated material. For dilute alloys of Si1xGex (x > 0.9 or x < 0.1) bulk Czochralski-grown material can be grown [47] but for 0.1 x 0.9 virtual substrate layers must be used [48]. Separation of the effects on diffusivity of strain from other parameters must be achieved if SiGe process models are to have general applicability. A further complication is self-diffusion. Interdiffusion is enhanced by strain and in thin layers it may be the dominant mechanism for strain relaxation rather than dislocation formation. Such diffusion tends to reduce the germanium concentration in the germanium-rich region of the heterostructure and vice versa, so introducing uncertainty into both the strain and composition in such experiments. However, self-diffusion also gives us insight into the mechanisms of diffusion in SiGe.

Self-Diffusion in Unstrained Si1xGex It is generally accepted that the diffusion of most species in Ge is mediated by vacancies and this is true of self-diffusion. However in silicon Ge diffusion depends on both vacancies and interstitials. In the alloy the interstitially mediated diffusion of Ge in Si1xGex is significant in the range 0 < x < 0.25 and although there are far fewer data this is probably true of Si diffusion as well. Most recent self-diffusion experiments have been carried out by the introduction of an isotopically enriched region either during growth or by implantation. Considerable care needs to be taken when using implantation as this will perturb the equilibrium concentration of intrinsic defects. The behavior of Ge diffusion in relaxed material is seen clearly in Figure 2.6.4 taken from Laitinen et al. [49]. The diffusivity D at a specific temperature is given from the data by Ea D ¼ D0 exp kT In the diagram the activation energy Ea is presented as an enthalpy H. The diagram includes some data from Strohm et al. [50] and Hettich et al. [51]. Strohm’s and Zangenberg’s [52] data are quantified in Table 2.6.3 which also includes a result (x ¼ 0.8) from Laitinen. The change of behavior at x 0.25 is very pronounced and reflects the transition from vacancy-mediated diffusion in the germanium-

© 2006 by Taylor & Francis Group, LLC

2.6-117

Defects and Diffusion in SiGe and Strained Si

5.5

H (eV)

10−2

D0(x)

4.5

10−3

4.0

10−4

H(x)

3.5 3.0 0.00

0.25

0.50

D 0 (m2S−1)

10−1

5.0

0.75

1.00

10−5

x

FIGURE 2.6.4 Self-diffusion enthalpies H (filled symbols) and pre-exponential factors D0 (open symbols) of diffusion coefficients in SiGe as functions of the Ge content x (circles: 71Ge in SiGe epilayers [50]; diamonds: 71Ge in bulk Si [51]; downtriangles: 71Ge in Si0:20Ge0:80 epilayers and in bulk Ge; uptriangles: 31Si in Si0:20Ge0:80 epilayers). (Reprinted with permission from Laitinen et al. Physical Review Letters 89, 085902 (2002). Copyright 2002 by the American Physical Society.)

TABLE 2.6.3 Activation Energies (Ea) and Pre-Exponential Factors (D0) for Self-Diffusion of Ge in Si1xGex Alloys of Composition x Si1xGex Composition x

VPE SiGea,b Implanted 71Ge Ea (eV)

0 (Si) 0.05 0.10 0.2 0.25 0.3 0.4 0.43 0.50 0.8 0.95 1 (Ge)

4.97 4.9 4.7 4.1

MBE SiGec Grown in 72Ge Spike

D0 (cm2/sec)

Ea (eV)

D0 (cm2/sec)

2500 4000 400

4.65

310

4.66 4.00

870 6.6

3.82 3.72

4.7 4.2

3.23

0.11

33

4.0

29

3.48 3.3 3.09

81 100 13.6

a

From A Strohm, T Voss, W Frank, J Ra¨isa¨nen, and M Dietrich. Self-diffusion of 71Ge in Si–Ge. Physica B 308–310: 542–545, 2001. With permission. b ¨ ysto¨, From P Laitinen, A Strohm, J Huikari, A Nieminen, T Voss, C Grodon, I Riihima¨ki, M Kummer, J A P Dendooven, J. Ra¨isa¨nen, W Frank, and ISOLDE Collaboration. Self-diffusion of 31Si and 71Ge in relaxed Si0:20Ge0:80 layers. Physical Review Letters 89: 085902-1 to 085902-4, 2002. With permission. c From N Zangenberg, J Lundsgaard Hansen, J Fage-Pedersen, and A Nylandsted Larsen. Ge self-diffusion in epitaxial Si1xGex layers. Physical Review Letters 87:125901, 2001. With permission.

rich material to interstitially dominated mediation in pure silicon. A more detailed study by Strohm et al. [53] reports a very similar trend but puts the transition from interstitial dominance to vacancy dominance at x 0.35 and details a comprehensive analysis of the relative contributions. However, in terms of absolute values, there is a clear systematic behavior reflected in all the published data showing increased self-diffusivity of Ge with increasing Ge content. The data on self-diffusion of Si in SiGe are very limited but values very similar to those of Ge have been reported in relaxed Si0.2Ge0.8 and silicon [49, 53]. The enthalpy values are the sum of the energy of formation of the vacancy and the energy required for its migration. Venezuela et al. have calculated the formation energies of vacancies in Si0.5Ge0.5 using

© 2006 by Taylor & Francis Group, LLC

2.6-118

The Silicon Heterostructure Handbook

first-principle methods [24]. They find a strong dependence of the formation energy on the configuration of the first nearest-neighbor atoms. This varies linearly from 2 to 3 eV as the number of nearestneighbor Ge atoms varies from 4 to 0. Ramanarayanan et al. Have undertaken ab initio calculations of the vacancy migration energy [25]. However as yet these calculations are quite a long way from providing a comprehensive explanation of the experimental observations in relaxed material.

Dopant Diffusion in Unstrained SiGe Table 2.6.4 provides data on the diffusion mechanism of a number of species in silicon and germanium by indicating whether diffusion is mediated by interstitials or vacancies. This is important as it enables us to decide whether diffusivity will be enhanced or retarded under implant conditions and to predict the effects of strain [54]. We will review the published data on the common dopant species. Arsenic A systematic study of arsenic diffusion in relaxed SiGe across the entire composition range has been undertaken by Laitinen et al. [55] as detailed in Table 2.6.5. Radioactive isotopes (73As and 72As) were introduced by implantation into 1 mm-thick relaxed Si1xGex epilayers grown by low-energy plasma enhanced chemical vapor deposition (LEPECVD) on graded buffer layers. The density of the threading dislocations was estimated to be about 106 cm2. As stated previously self-diffusion in Si1xGex for x > 0.35 is vacancy dominated. Although as shown in Table 2.6.4 diffusion of As in Si is mediated predominantly by interstitials in germanium-rich alloys it is considered to proceed via vacancies. When the arsenic activation energies are compared with Ge self-diffusion values for SiGe, their dependence on the SiGe composition is very similar and it seems likely that the decrease in activation energy as a function of x results from the decrease in vacancy formation energy. The activation energy values for arsenic diffusion are 0.5 eV lower than for self-diffusion. It is postulated that this may be due to the arsenic migrating via a vacancy–arsenic complex [55].

TABLE 2.6.4 Role of Vacancies and Interstitials in Promoting Diffusion in Silicon and Germanium Migrating Species

Silicon Matrix

Germanium Matrix

Boron Phosphorous Arsenic Antimony Silicon Germanium

Interstitial Interstitial Interstitial Vacancy Mixed Mixed

Vacancy? Vacancy Vacancy Vacancy Vacancy Vacancy

TABLE 2.6.5 Activation Energies (Ea) and Pre-Exponential factors (D0) of the As Diffusion Coefficients as a Function of Si1xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated from Ea and D0 (Extrapolated Data are Shown in Italics) Si1xGex Composition x 0 0.20 0.35 0.50 0.65 0.80 1.00

Temperature Range (8C)

Ea (eV)

D0 (cm2/sec)

D8508C (cm2/sec)

882–1120 882–1120 812–1050 750–1020 675–870 696–925 490–600

3.81 3.83 3.68 3.47 3.16 2.97 2.42

4.3 30 23 18 16 11 5.8

2.2 1019 1.9 1016 7 1016 4.8 1015 4.3 1015 5.2 1013 8 1011

Source : From P Laitinen, I Riihima¨ki, J. Ra¨isa¨nen, and ISOLDE Collaboration. Arsenic diffusion in relaxed Si1xGex. Physical Review B 68: 155209-1 to 155209-6, 2003. With permission.

© 2006 by Taylor & Francis Group, LLC

2.6-119

Defects and Diffusion in SiGe and Strained Si

Eguchi et al. [56] have separated the transient diffusion effects following implantation from the equilibrium behavior in relaxed SiGe. They find, as above, that increased germanium content increases the equilibrium diffusivity but observe a decrease in transient diffusion effects with increasing germanium content. Antimony Antimony is the only dopant which diffuses in both Si and Ge via a mechanism that is mediated predominantly by vacancies. In silicon the diffusion mechanism is via the vacancy Sb pair (the E center) discussed previously in Section 2.6.2. Larsen and Kringhøj [57] have studied the diffusion of antimony in relaxed Si1xGex layers grown by molecular beam epitaxy for 0 < x < 0.5. The diffusivity of antimony was found to increase with the Ge alloy content. The activation energies for diffusion were found to decrease with increasing germanium content. A summary of their results is given in Table 2.6.6. Antimony exhibits a particularly strong dependence of diffusivity on concentration. In germanium Boltaks [58] reports a change of Ea from 1.69 to 2.13 eV with an increase in Sb concentration from 1015 to 1018 cm3 and a corresponding increase in D0 from 2.7103 to 0.35 cm2/sec. In Table 2.6.6 Chui’s [59] value for [Sbmax] ¼ 61019 cm3 is included for pure Ge which enables comparison with Larsen et al., who have used quite high concentrations of [Sbmax] in their experiments (1019 cm3). These data represent much lower diffusivities than have been reported by Dan et al. [60] who have used point-defect injection from surface oxidation or nitridation to introduce excess of interstitials or vacancies, respectively. This has confirmed that Sb diffusion is vacancy-mediated in Si and Si0.9Ge0.1. However, lower Sb concentrations were used [Sbmax] ¼ 31018 cm3 and the SiGe layer used by Dan was compressively strained, which would reduce the formation energy of the vacancy as will be discussed in Section 2.6.5.5. The combination of these two effects probably accounts for the differences in the reported diffusivities. Phosphorus Table 2.6.7 presents the results of Zangenberg et al. [61] and data on pure germanium [59, 62]. Here the activation energy of the diffusivity in Si is rather low compared to the generally accepted values. The authors attribute this to non-Arrhenius behavior as their measurements have been made at relatively low temperatures. However, the diffusion coefficient (as distinct from the individual values of Ea and Do) calculated from the data agrees with the literature below 9008C. The conclusion is similar to that of Eguchi et al. [63], i.e., that the presence of Ge enhances the diffusion coefficient of phosphorus. Boron The case of boron is quite complicated. As already discussed the diffusivity of boron is very sensitive to the presence of excess of interstitials and so issues of ion implantation damage and surface generation of interstitials (e.g., by annealing in an oxidizing atmosphere) create variables which confuse both researchers and process engineers. However, there are other variables. The boron interstitial exists in both neutral and positive charge state. This is believed to have an effect on the diffusivity at low temperatures where the intrinsic carrier concentration is less than the extrinsic hole concentration

TABLE 2.6.6 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Sb Diffusion Coefficients as a Function of Si1xGex Composition x Si1xGex Composition x 0 (Si) 0.1 0.2 0.3 0.5 1 (Ge)

Ea (eV)

D0 (cm2/sec)

D8508C (cm2/sec)

4.06 4.07 4.07 3.89 3.63 2.28

0.2 0.4 1.3 0.8 4.2 0.12

1.21019 2.21019 7.11019 2.81018 2.11016 7.11012

Source : Ref. [57] with the exception of the Ge data, which are from Ref. [59].

© 2006 by Taylor & Francis Group, LLC

2.6-120

The Silicon Heterostructure Handbook

TABLE 2.6.7 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Phosphorus Diffusion Coefficients as a Function of Si1xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated from Ea and D0 (an Extrapolated Figure is Shown in Italics) Si1xGex Composition x 0 0.07 0.12 0.24 0.4 1 (Ref. [63]) 1 (Ref. [60])

Temperature range (8C)

D0 (cm2/sec)

Ea (eV)

D8508C (cm2/sec)

825–900 825–900 800–900 800–900 800–900 560–850 650 þ model

2.0103 1.8101 1.1101 1.7103 1.7102 2.5 4.4102

2.80 3.24 3.11 4.01 3.83 2.48 2.07

5.51016 5.21016 1.11015 1.71015 1.11015 1.81011 2.21011

Source : Ref. [61] with the exception of the Ge data, which are from Refs. [59, 62].

(ni < p). The small size of the boron atom compared to silicon and germanium introduces lattice relaxation effects, which have an impact on transit paths in SiGe and favor the formation of complexes. Cowern et al. [64] have proposed a mechanism by which oxidation-enhanced diffusion occurs via the formation of boron–interstitial complexes. There is a substantial literature on boron diffusion in Si and SiGe but unfortunately there are significant discrepancies in values of activation energies and prefactors. However when this is translated into diffusion coefficients around the temperatures at which the measurements were undertaken the discrepancies are much less pronounced. It is not really clear, as a generality, whether this is due to fitting Arrhenius behavior over a limited temperature range or more fundamental issues associated with the entropy term as exemplified by the Meyer–Neldel rule [65]. Zangenberg et al. [61] have measured diffusion in Si1xGex for 0 < x < 0.4 in relaxed MBE material at temperatures in the range 8008C to 9008C. These results are shown in Table 2.6.8 together with a diffusivity result for pure Ge from Uppal et al. [66]. Perhaps the most noteable result is that the diffusion coefficient shows almost no change across the entire composition range of SiGe. Uppal’s result has led to speculation that the longstanding assumption that boron diffusion in Ge is vacancy mediated may not be correct. However Uppal et al. used experimental conditions that injected large concentrations of interstitials, which would be expected to suppress vacancy mediated diffusion. This discrepancy may result from conditions that were very different from previous experiments, which gave much higher diffusivities [62]. Recent first-principle calculations [67] appear to support Uppal’s interpretation but further experimental work is needed to resolve this important issue particularly in the Ge-rich SiGe alloys.

The Impact of Strain and Interfaces on Diffusivity The application of hydrostatic pressure or stress (uniaxial or biaxial) to a semiconductor changes the equilibrium population of interstitials and vacancies. Free energy calculations for the hydrostatic pressure case indicate that the formation energy of the self-interstitial increases with increasing compressive strain and decreases with increasing tensile strain. The formation energy of the vacancy decreases with increasing compressive strain and is almost independent of tensile strain [68]. Aziz [53] and Zhao et al. [69] have considered the hydrostatic case theoretically and experimentally and the relationship between hydrostatic, biaxial, and uniaxial stress in relation to point-defect generation. In the strained Si and SiGe cases, it is obviously biaxial stress that is technologically important and is significant enough to change self-diffusion coefficients and the diffusivity of common impurities under normal process conditions. Zangenberg et al. [52] have measured the effect of strain on self-diffusion (Ge in Si0.9Ge0.1). Their work showed a decrease in diffusion coefficient and an increase in activation energy on going from compressive to relaxed to tensile strain. A compressive strain of 0.21% (corresponding to an

© 2006 by Taylor & Francis Group, LLC

2.6-121

Defects and Diffusion in SiGe and Strained Si

TABLE 2.6.8 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Boron Diffusion Coefficients as a Function of Si1xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated From Ea and D0 Si1xGex composition x 0 0.01 0.12 0.24 1

Temperature range (8C)

D0 (cm2/sec)

Ea (eV)

D8508C (cm2/sec)

800–900 800–925 800–925 800–925 850

3.4104 3.4102 2.4101 5.7102 —

2.68 3.13 3.30 3.18 —

3.21016 3.11016 3.81016 3.11016 1.31016

a

Source: Ref. [61] with the exception of the Ge data, which are from Ref. [64].

in-plane stress of 0.4 GPa) produced an increase in diffusivity by a factor of 1.8 at 10008C while the same tensile stress reduced the diffusivity by about 20%. Earlier results from Cowern et al. [70] show changes in the same sense but of considerably greater magnitude. However, there is a fundamental difference between the experiments in that Cowern et al. measured the diffusion from a Si1xGex layer with 0.1< x < 0.3 into Si, while Zangenberg et al. used a substitution of 72Ge for the natural Ge in the epilayer. In this latter experiment the diffusion of the germanium within the SiGe produced no change in composition and hence no stress relief. In Cowern’s case the interdiffusion is driven by strain relaxation, which is probably favored kinetically over dislocation growth as the relaxation mechanism. Work by Zangenberg et al. on boron in strained Si0.88Ge0.12 showed a reduction (by a factor of 2) in the diffusion coefficient with compressive strain of 0.21% and a very slight reduction with a similar value of tensile strain. In the case of silicon a factor of 2 increase of boron diffusivity was seen in tensile strained material compared to unstrained silicon [60]. Earlier work by Moriya et al. [71] and by Kuo et al. [72] also showed a retarded B diffusion in compressively stressed SiGe but the separation of the strain effects from the role of germanium was not clear. However, subsequent work discussed above [61] seems to indicate that the chemical effect is small in the case of boron and the dominant effect is strain. Paine et al. [73] have measured the diffusion of boron in compressively strained Si1xGex layers over the entire composition range but again their results convolute the effects of strain and composition. Over the range 0 < x < 0.5 the diffusivity decreases by almost an order of magnitude with increasing germanium content but then in the germanium-rich region the diffusivity was observed to increase with increasing Ge concentration. Unlike boron in which diffusion is mediated by interstitials the diffusion of antimony is mediated by vacancies; as a consequence the expectation is that compressive stress will enhance the diffusivity due to the reduced energy of formation of the vacancy while tensile stress will have little effect. Kringhøj et al. [29] have studied Sb diffusion under both compressive and tensile stress in Si and Si0.91Ge0.09 and indeed diffusivity is enhanced by compressive stress and retarded by tensile stress. In real devices the issue of composition change is almost always convoluted with strain but in addition interfaces are present. We have already referred to the studies of Cowern et al. [70] where the interdiffusion across a heterojunction was driven by strain relaxation. More recently Lever et al. [74] have studied diffusion across interfaces. The test structures used were grown on Si substrates by LPCVD and consisted of a boron-doped silicon layer sandwiched between two dilute undoped Si1xGex layers with x ¼ 0.1 or 0.03. After annealing at 8508C the boron profile was determined by SIMS. In all cases there was a clear accumulation of boron in the SiGe layers, which was attributed to a preferential siting of the boron with Ge as a first nearest neighbor. This confirms earlier work by Hu et al. [75] in which experimental results were obtained on the segregation coefficients of boron, phosphorus, and arsenic in Si–(GexSi1x) heterostructures. It was found that boron tended to segregate into the germanium-rich region, while phosphorus and arsenic tend to segregate away from it. Within experimental error, the diffusivities were not appreciably affected.

© 2006 by Taylor & Francis Group, LLC

2.6-122

The Silicon Heterostructure Handbook

2.6.6 Dislocations The only issue we consider here is the electrical behavior of dislocations although of course they can have a significant effect in device processing as diffusion pipes with resultant shorts across junctions. It is well established that dislocations in Si and in SiGe have levels in the bandgap [76, 77] and so it is apparent there are two key questions to address; firstly the position of the levels in the gap and secondly whether the concentration is sufficient to affect device performance. Dislocations introduce an ensemble of electronic levels into the gap, which can appear as a continuum or mini band of states. The electronic behavior is distinctly different to that of point defects, which, in general, have well-defined discrete energy levels. A very important issue in assessing the significance of dislocations is the role of decoration. The energy state associated with the undecorated dislocation is relatively shallow, typically 120 meV, but as impurities are drawn into the region of the strain field the level moves towards mid-gap [78]. This is very significant as the mid-gap states are extremely effective generation centers while the shallower ‘clean’ state is ineffective in this role. This work has been done mostly on Frank partial dislocations bounding stacking faults but dislocations with larger Burgers vectors behave similarly. In these experiments extremely small levels of ‘decoration’ with transition metals were used. These are well below those detectable in transmission electron microscopy (TEM) and probably typical of levels found in ‘adequate’ fabs in the late 1980s (a few ppb averaged over the layer volume). The behavior with different metals is remarkably similar provided they can diffuse to the defect. However, as the concentration of impurity is increased, metals which precipitate (e.g., copper) produce electrically inert objects which draw the impurity away from dislocations with small Burgers vectors and the state moves away from mid-gap, making it less effective as a generation center. There is also evidence from scanning electron microscopy studies using electron beam induced currents and from luminescence mapping that decorated dislocations are also much more important as recombination centers than clean dislocations [79]. In the limit a dislocation can trap one charge at each atomic plane it threads through but experimental observations indicate that on average the concentration of charge traps is much lower. This gives us a basis for calculating the effects of dislocations on devices assuming a worst-case scenario in which the decoration is such as to move the level to mid-gap. A generation state is only active in the depletion region so if we know the depletion width we can calculate the leakage current produced by one dislocation. For the purpose of this calculation we will assume a device operating temperature of 708C and transistors typical of the 90 nm node in the International Technology Roadmap for Semiconductors (ITRS). At this node the physical gate length is 37 nm, the junction depth 33 nm and Vdd 1 V. The worst-case leakage current associated with a single dislocation is 200 pA. The value is essentially the same for a threading dislocation or a misfit dislocation. This is dramatically different from measurements on devices with wide depletion regions (e.g., power devices where leakage currents as high as 1 mA /dislocation have been reported) [80]. The reason is due to the size of the device and the length of dislocation which can be accommodated in the depletion region. The probability of finding more than one dislocation in a 35-nm device is extremely remote so the question is will our technology accept a leakage current of 200 pA? The design rules for the 90-nm CMOS mode accommodate 20 nA /mm and so it seems that even this worst-case scenario is acceptable for conventional CMOS although the requirements for some memory devices are more stringent. The case of bipolar transistors can be considered very simply. The leakage considerations are very similar to those discussed above. In relation to the effects of dislocations on gain (recombination), the effects are negligible. Beyond the 180-nm node the base width in both hetero- and homojunction transistors is sufficiently small for us to be able to neglect the role of base recombination in the transistor gain.

2.6.7 Summary In this section of the handbook we have tried to give an overview of defects and diffusion in SiGe. It is clear that in the last few years very substantial progress has been made towards resolving one of the

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-123

major problems that plagued early work, namely, separating the issues associated with strain from the chemical effects associated with the presence of two species in the host matrix. There is now a very substantial and reliable literature on defects in silicon and in dilute Si1xGex (i.e., where x < 0.3). However recent work has caused us to doubt the validity of some of the previously accepted work on germanium. Very little experimental data exist on defects or on diffusion in the germanium-rich alloys (x > 0.5) and extrapolation from x < 0.3 is not feasible because of changes in intrinsic defect mechanisms at around x ¼ 0.25. Interpolation between x ¼ 0.3 and x ¼ 1 is dubious partly for the same reason but also because of doubts regarding the pure germanium data. It is evident that much more work is required if we are to have a sufficiently rigorous understanding of defects and defect reactions to develop reliable process models for devices containing pure germanium or germanium-rich layers.

Acknowledgments We are grateful to our colleagues for valuable discussions and their contribution to this work. In particular we thank A.N. Larsen, K. Bonde Nielsen, L. Dobaczeweski, G. Davies, A.F.W. Willoughby, J.M. Bonar, L.I. Murin, J.L. Lindstro¨m, A. Mesli, and N.V. Abrosimov. We would also like to thank W. Frank and A. Strohm for providing data on self-diffusion.

References 1. GD Watkins. EPR studies of the lattice vacancy and low-temperature damage processes in silicon. Lattice Defects in Semiconductors 1974, edited by FA Huntley. Inst. Phys. Conf. Ser. No 23, IOP, Bristol, 1975, pp 1–22. 2. GD Watkins. The lattice vacancy in silicon. Deep Centers in Semiconductors, ST Pantelides (ed.). Gordon and Breach, New York, 1986, chapter 3, pp 147–183. 3. GD Watkins. Vacancies and interstitials and their interactions with impurities in c-Si. Properties of Crystalline Silicon (EMIS Data Review Series No. 20), R. Hull (ed.), INSPEC, London, 1999, chapter 11.1, pp. 643–652. 4. PM Fahey, PB Griffin, and JD Plummer. Point defects and dopant diffusion in silicon. Reviews of Modern Physics 61: 289–388, 1989. 5. CV Budtz-Jorgensen, P Kringhøj, A Nylandsted Larsen, and NV Abrosimov. Deep-level transient spectroscopy of the Ge-vacancy pair in Ge-doped n-type silicon. Physical Review B 58: 1110–1113, 1998. 6. M Lannoo and J Bourgoin. Point Defects in Semiconductors I: Theoretical Aspects. Springer Series in Solid State Sciences No 22, Springer, New York, 1981. 7. S Dannefaer, P Mascher, and D Kerr. Monovacancy formation enthalpy in silicon. Physical Review Letters 56: 2195–2198, 1986. 8. JS Nelson, PA Schultz, and AF Wright. Valence and atomic size-dependent exchange barriers in vacancy-mediated dopant diffusion. Applied Physics Letters 73: 247–249, 1998. 9. J Xie and SP Chen. Diffusion and clustering in heavily arsenic-doped silicon: discrepancies and explanation. Physical Review Letters 83: 1795–1798, 1999. 10. A Fazzio, A Janotti, AJR da Silva, and R Mota. Microscopic picture of the single vacancy in germanium. Physical Review B 61: R2401–R2404, 2000. ¨ gu¨t and R Chelikowsky. Ab initio investigation of point defects in bulk Si and Ge using a cluster 11. S O method. Physical Review B 64: 245206-1 to 245206-11, 2001. 12. H Haesslein, R Sielemann, and C Zistl. Vacancies and self-interstitials in germanium observed by perturbed angular correlation spectroscopy. Physical Review Letters 80: 2626–2629, 1998. 13. RE Whan. Investigations of oxygen-defect interactions between 25 and 700 K in irradiated germanium. Physical Review 140: A690–A698, 1965.

© 2006 by Taylor & Francis Group, LLC

2.6-124

The Silicon Heterostructure Handbook

14. VP Markevich, ID Hawkins, AR Peaker, VV Litvinov, LI Murin, L. Dobaczewski, and JL Lindstro¨m. Electronic properties of vacancy–oxygen complex in Ge crystals. Applied Physics Letters 81: 1821– 1823, 2002. 15. VP Markevich, VV Litvinov, l Dobaczewski, JL Lindstro¨m, LI Murin, and AR Peaker. Radiationinduced defects and their transformations in oxygen-rich germanium crystals. Physica Status Solidi (c) 0: 702–706, 2003. 16. J Fage-Pedersen, A Mesli, and A Nylandsted Larsen. Irradiation-induced defects in Ge studied by transient spectroscopies. Physical Review B 62: 10116–10125, 2000. 17. VP Markevich, AR Peaker, VV Litvinov, VV Emtsev, and LI Murin. Electronic properties of antimony–vacancy complex in Ge crystals. Journal of Applied Physics 95: 4078–4083, 2004. 18. JR Troxell, AP Chatterjee, GD Watkins, and LC Kimerling. Recombination-enhanced migration of interstitial aluminum in silicon. Physical Review B 19: 5336–5348, 1979. 19. PM Money, LI Cheng, M Su¨li, JD Gerson, and JW Corbett. Defect energy levels in boron-doped silicon irradiated with 1-MeV electrons. Physical Review B 15: 3836–3843, 1977. 20. LW Song, XD Zhan, BW Benson, and GD Watkins. Bistable interstitial-carbon–substitutionalcarbon pair in silicon. Physical Review B 42: 5765–5783, 1990. 21. H Bracht, NA Stolwijk, and H Mehrer. Properties of intrinsic point defects in silicon determined by zinc diffusion experiments under nonequilibrium conditions. Physical Review B 52: 16542–16560, 1995. 22. AJR da Silva, A Janotti, A Fazzio, RJ Baierle, and R Mota. Self-interstitial defect in germanium. Physical Review B 62: 9903–9906, 2000. 23. J Lento, M Pesola, J-L Moros, and RM Nieminen. Vacancies in SiGe: Jahn–Teller distortion and spin effects. Applied Physics Letters 77: 232–234, 2000. 24. P Venezuela, GM Dalpian, AJR da Silva, and A Fazzio. Vacancy-mediated diffusion in disordered alloys: Ge self-diffusion in Si1xGex . Physical Review B 65: 193306-1 to 193306-4, 2002. 25. P Ramanarayanan, K. Cho, and BM Clemens. Effect of composition on vacancy mediated diffusion in random binary alloys: first principles study of the Si1xGex system. Journal of Applied Physics 94: 174–185, 2003. ¨ berg, PR Briddon, LI Murin, 26. VP Markevich, AR Peaker, J Coutinho, R Jones, VJB Torres, S O L Dobachewski, and NV Abrosimov. Structure and properties of vacancy–oxygen complexes in Si1xGex alloys. Physical Review B 69: 125218-1 to 125218-11, 2004. 27. L Dobaczewski, P Kaczor, ID Hawkins, and AR Peaker. Laplace transform deep-level transient spectroscopic studies of defects in semiconductors. Journal of Applied Physics 76: 194–198, 1994. 28. L Dobaczewski, K Goscinski, K Bonde Nielsen, A Nylandsted Larsen, J Lundsgaard Hansen, and AR Peaker. Alloy splitting of gold and platinum acceptor levels in SiGes. Physical Review Letters 83: 4582–4585, 1999. 29. P Kringhøj, A Nylandsted Larsen, and Yu Shiryaev. Diffusion of Sb in strained and relaxed Si and SiGe. Physical Review Letters 76: 3372–3375, 1996. 30. L Dobaczewski, K Goscinski, ZR Zytkiewicz, K Bonde Nielsen, L Rubaldo, O Andersen, and AR Peaker. Piezoscopic deep-level transient spectroscopy studies of the silicon divacancy. Physical Review B 65: 113203-1 to 113203-4, 2002. 31. R Kru¨ssmann, H Vollmer, and R Labusch. The activation energy of phosphorus donors in siliconrich silicon–germanium alloys. Physica Status Solidi (b) 118: 275–282, 1983. 32. J Hattendorf, W-D Zeitz, W Schro¨der, and NV Abrosimov. On the formation of boron–germanium pairs in silicon–germanium mixed crystals. Physica B 340–342: 858–862, 2003. 33. P Kringhøj and A Nylandsted Larsen. Irradiation-induced defect states in epitaxial n-type Si1xGex alloy layers. Physical Review B 52: 16333–16336, 1995. 34. S-L Sihto, J Slotte, J Lento, K Saarinen, EV Monakhov, AYu Kuznetsov, and BG Svensson. Vacancy– phosphorus complexes in strained Si1xGex: structure and stability. Physical Review B 68: 115307-1 to 115307-10, 2003.

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-125

35. H av Skardi, A Bro Hansen, A Mesli, and A Nylandsted Larsen, The divacancy in particleirradiated, strain-relaxed SiGe. Nuclear Instruments and Methods in Physics Research B 186: 195– 200, 2002. 36. TP Leevard Pedersen, A Nylandsted Larsen, and A Mesli. Carbon-related defects in protonirradiated, n-type epitaxial Si1xGex . Applied Physics Letters 75: 4085–4087, 1999. 37. A Nylandsted Larsen, A Bro Hansen, D Reitze, J-J Goubet, and J Fage-Pedersen. Interstitial-carbon defects in Si1xGex . Physical Review B 64: 233202-1 to 233202-4, 2001. 38. VP Markevich, AR Peaker, LI Murin, and NV Abrosimov. Oxygen-related radiation-induced defects in SiGe alloys. Journal of Physics: Condensed Matter 15: S2835–S2842, 2003. 39. F Nikolajsen, P Kringhoj, and A Nylandsted Larsen. Substitutional gold in Si1xGex. Applied Physics Letters 69: 1743–1745, 1996. 40. A Mesli, P Kringhoj, and A Nylandsted Larsen. Pinning behaviour of gold-related levels in Si using Si1xGex alloy layers. Physical Review B 56: 13202–13217, 1997. 41. K Nauka and TI Kamins. Deep state defects in strained and relaxed epitaxial Si1xGex on Si introduced by 3d transition metal and 5d noble metal impurities. Physica B 273–274: 603–607, 1999. 42. K Goscinski, L Dobaczewski, K Bonde Nielsen, A Nylandsted Larsen, and AR Peaker. Highresolution deep-level transient spectroscopy studies of gold and platinum acceptor states in diluted SiGe alloys. Physical Review B 63: 235309-1 to 235309-10, 2001. 43. A Mesli, B Vileno, C Eckert, A Slaoui, C Pedersen, A Nylandsted Larsen, and NV Abrosimov. Iron in relaxed Si1xGex alloy: band gap related levels, diffusion, and alloying effects. Physical Review B 66: 045206-1 to 045206-12, 2002. 44. NEB Cowern, GFA van de Walle, PC Zalm, and DJ Oostra. Reactions of point defects and dopant atoms in silicon. Physical Review Letters 69: 116–119, 1992. 45. DJ Eaglesham, PA Stolk, H-J Gossmann, and JM Poate. Implantation and transient B diffusion in Si: the source of the interstitials. Applied Physics Letters 65: 2305, 1994. 46. A Pakfar. Dopant diffusion in SiGe: modeling stress and Ge chemical effects. Materials Science and Engineering B89: 225–228, 2002. 47. NV Abrosimov, SN Rossolenko, V Alex, A Gerhardt, and W Shro¨der. Single crystal growth of Si1xGex by the Czochralski technique. Journal of Crystal Growth 166: 657, 1996. 48. A Nylandsted Larsen. Growth and process-induced defects in SiGe-based heterostructures. Diffusion and Defect Data Part B (Solid State Phenomena) 69–70: 43–45, 1999. ¨ ysto¨, 49. P Laitinen, A Strohm, J Huikari, A Nieminen, T Voss, C Grodon, I Riihima¨ki, M Kummer, J A 31 71 P Dendooven, J. Ra¨isa¨nen, W Frank, and ISOLDE Collaboration. Self-diffusion of Si and Ge in relaxed Si0:20Ge0:80 layers. Physical Review Letters 89: 085902-1 to 085902-4, 2002. 50. A Strohm, T Voss, W Frank, J Ra¨isa¨nen, and M Dietrich. Self-diffusion of 71Ge in Si–Ge, Physica B 308–310: 542–545, 2001. 51. G Hettich, H Mehrer, and K Maier. Tracer diffusion of 71Ge and 31Si in intrinsic and doped silicon. Institute of Physics Conference Series 46: 500–504, 1979. 52. N Zangenberg, J Lundsgaard Hansen, J Fage-Pedersen, and A Nylandsted Larsen. Ge self-diffusion in epitaxial Si1xGex layers. Physical Review Letters 87: 125901, 2001. 53. A Strohm, T Voss, W Frank, P Laitinen and J Ra¨isa¨nen. Self-diffusion of 71Ge and 31Si in Si–Ge. Zeitschrift fu¨r Metallkunde 93: 737–744, 2002. 54. MJ Aziz. Thermodynamics of diffusion under pressure and stress: relation to point defect mechanisms. Applied Physics Letters 70: 2810–2812, 1997. 55. P Laitinen, I Riihima¨ki, J Ra¨isa¨nen, and ISOLDE Collaboration. Arsenic diffusion in relaxed Si1xGex. Physical Review B 68: 155209-1 to 155209-6, 2003. 56. S Eguchi, CN Chleirigh, OO Olubuyide, and JL Hoyt. Germanium-concentration dependence of arsenic diffusion in silicon germanium alloys. Applied Physics Letters 84: 368–370, 2004. 57. A Nylandsted Larsen and P Kringhøj. Diffusion of Sb in relaxed Si1xGex. Applied Physics Letters 68: 2684–2686, 1996.

© 2006 by Taylor & Francis Group, LLC

2.6-126

The Silicon Heterostructure Handbook

58. BI Boltaks. Diffusion in Semiconductors. Infosearch Ltd., London, 1963, p. 190. 59. Chi On Chui, K Gopalakrishnan, PB Griffin, JD Plummer, and KC Saraswat. Activation and diffusion studies of ion-implanted p and n dopants in germanium. Applied Physics Letters 83: 3275–3277, 2003. 60. Aihua Dan, AFW Willoughby, JM Bonar, BM Mcgregor, MG Dowsett, and RJH Morris. Antimony diffusion in silicon gemanium alloys under point defect injection. International Journal of Modern Physics B 16: 4195–4198, 2002. 61. N Zangenberg, J Fage-Pedersen, J Lundsgaard Hansen, and A Nylandsted Larsen. Boron and phosphorus diffusion in strained and relaxed Si and SiGe. Journal of Applied Physics 94: 3883–3890, 2003. 62. WC Dunlap Jr. Diffusion of impurities in germanium. Physical Review 94: 1531–1540, 1954. 63. S Eguchi, JL Hoyt, CW Leitz, and EA Fitzgerald. Comparison of arsenic and phosphorus diffusion behavior in silicon–germanium alloys. Applied Physics Letters 80: 1743–1745, 2002. 64. NEB Cowern, KTF Janssen, GFA van de Walle, and DJ Gravesteijn. Impurity diffusion via an intermediate species: the B–Si system. Physical Review Letters 65: 2434–2437, 1990. 65. NR Zangenberg and A Nylandsted Larsen, The Meyer–Neldel rule for diffusion in Si and SiGe. Physica B 340–342: 780–783, 2003. 66. S Uppal, AFW Willoughby, JM Bonar, AGR Evans, NEB Cowern, R Morris, and MG Dowsett. Diffusion of ion-implanted boron in germanium. Journal of Applied Physics 90: 4293–4295, 2001. 67. P Delugas and V Fiorentini. Energetics of transient enhanced diffusion of boron in Ge and SiGe. Physical Review B 69: 085203-1 to 085203-5, 2004. 68. A Antonelli and J Bernholc. Pressure effects on self-diffusion in silicon. Physical Review B 40: 10643– 10646, 1989. 69. Y Zhao, MJ Aziza, H-J Gossmann, S Mitha, and D Schiferl. Activation volume for boron diffusion in silicon and implications for strained films. Applied Physics Letters 74: 31–33, 1999. 70. NEB Cowern, PC Zalm, P van der Sluis, DJ Gravesteijn, and WB de Boer. Diffusion in strained Si(Ge). Physical Review Letters 72: 2585–2588, 1994. 71. N Moriya, LC Feldman, HS Luftman, CA King, J Bevk, and B Freer. Boron diffusion in strained Si1xGex epitaxial layers. Physical Review Letters 71: 883–886, 1993. 72. P Kuo, JL Hoyt, JF Gibbons, JE Turner, RD Jacowitz, and TI Kamins. Comparison of boron diffusion in Si and strained Si1xGex epitaxial layers. Applied Physics Letters 62: 612–614, 1993. 73. ADN Paine, AFW Willoughby, and JM Bonar. Point defect redistribution in Si1xGex alloys. Journal of Material Science: Materials in Electronics 10: 339–343, 1999. 74. RF Lever, JM Bonar, and AFW Willoughby. Boron diffusion across silicon–silicon germanium boundaries. Journal of Applied Physics 83: 1988–1994, 1998. 75. SM Hu, DC Ahlgren, PA Ronsheim, JO Chu. Experimental study of diffusion and segregation in a Si–(GexSi1x) heterostructure. Physical Review Letters 67: 1450–1453, 1991. 76. P Omling, ER Weber, L Montelius, HM Alexander, and J Michel. Electrical properties of dislocations and point defects in plastically deformed silicon. Physical Review B 32: 6571–6581, 1988. 77. PN Grillot, SA Ringel, EA Fitzgerald, GP Watson, and YH Xie. Electron trapping kinetics at dislocations in relaxed Ge0.3Si0.7/Si heterostructures. Journal of Applied Physics 77: 3248–3256, 1995. 78. A Berg, I Brough, JH Evans, G Lorimer, and AR Peaker. Recombination–generation behaviour of decorated defects in silicon. Semiconductor Science and Technology 7: 263–268, 1992. 79. V Higgs and M Kittler. Investigation of the recombination activity of misfit dislocations in Si /SiGe epilayers by cathodoluminescence imaging and the electron beam induced current technique. Applied Physics Letters 63: 2085–2087, 1993. 80. BO Kolbesen, W Bergholz, H Cerva, F Gelschorf, H Wendt, and G Zoth. Effects of extended lattice defects on silicon semiconductor devices. Structure and Properties of Dislocations in Semiconductors 1989. Proceedings of the Sixth International Symposium, 1989, Inst. Phys. Conf. Ser. 104: 421–430, 1990.

© 2006 by Taylor & Francis Group, LLC

2.7 Stability Constraints in SiGe Epitaxy 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6

Armin Fischer

2.7.7

Innovations for High Performance Microelectronics (IHP)

2.7.8

Introduction............................................................... 2.7-127 Image-Force Method for Strained Layer Relaxation................................................................... 2.7-128 Surface Relaxation Stress .......................................... 2.7-130 Interaction between Internal Stress and External Stress............................................................ 2.7-132 Critical Thickness and Film Stress of SiGe/Si Layers ............................................................ 2.7-133 Plastic Deformation and Work Hardening in SiGe/Si ................................................................... 2.7-135 Force Balance Model for Buried SiGe Strained Layers........................................................... 2.7-136 Summary .................................................................... 2.7-139

2.7.1 Introduction The growth of coherent thin layers on rigid crystalline substrates is possible when biaxial compressive or tensile strain in the layer accommodates the lattice mismatch between the film and substrate material. When the stored strain energy exceeds a certain threshold, the heterostructure becomes metastable and the film strain may give way to misfit dislocations. The basic energetic and kinetic parameters describing mismatch accommodation by elastic strain and misfit dislocation in metastable heterostructures appear to be well described by the framework of Matthews and Blakeslee [1–3] and Dodson and Tsao [4, 5]. However, it is evident that they cannot adequately explain the point of strain relief onset via plastic flow and the work hardening behavior of strained layers at the end of thermal relaxation process. This stems from ignoring the effects of elastic surface relaxation on the film lattice cells and the elastic interaction between straight misfit dislocations within the film–substrate interface. The first includes the problem of developing a relationship between the equilibrium critical thickness at which dislocations form and the bulk lattice mismatch [6]. The latter involves balancing the force required to move misfit dislocations against the internal elastic stress field due to dislocation–dislocation interactions [7]. Finally, suffice it to say that classical equilibrium and kinetic models for strained layer case do not imply rigorously the conditions of equilibrium at the boundary. In this chapter we present a modified Volterra approach in equilibrium theory for strain relaxation in metastable heteroepitaxial semiconductor structures, which includes the surface effects on mismatch accommodation by tetragonal distortion of the cubic lattice cells and the elastic interaction between straight misfit dislocations. Because of the mathematical complexities involved in a proper atomistic description of the competing forces, the subject is not treated here in a Frenkel–Kontorowa model or its approximations. The principle of our theoretical method is straightforward. The free-surface boundary conditions are satisfied by placing an image dislocation outside the crystal so that its stress 2.7-127 © 2006 by Taylor & Francis Group, LLC

2.7-128

The Silicon Heterostructure Handbook

field cancels that of the real misfit dislocation at the surface. We will discuss the effect of the Airy stress function that removes the fictitious shear and normal stresses at the crystal surface and thus makes the crystal stress-free. We show that this image-force method provides an equilibrium theory that correctly predicts experimentally observed values of critical layer thickness. To demonstrate the physical significance of the present approach in equilibrium theory for strained layer relaxation, we have calculated the equilibrium critical thickness and Ge content via coherency strain of SiGe/Si strained layer structures and compared our results to those predicted by using relaxation models based on the absence of surface relaxation effects and elastically noninteracting dislocations. Furthermore, by considering the exact solution for the elastic interaction of real and image dislocations, our equilibrium model can completely describe the strain relief via lattice distortion, plastic flow, and work hardening in lattice-mismatched epilayers. We show that our Volterra dislocation model is also appropriate when the film thickness is smaller than the misfit dislocation spacing. It is pointed out that the elastic coherency stress of the strained material is really affected by a large surface relaxation stress. This is essential for experimental determination of the Ge content of extremely thin films as a function of the tetragonal distortion of the cubic lattice cells. The equilibrium theory is also used to define the degree of strain relaxation and to predict the incomplete strain relief at the end of thermal relaxation process of metastable SiGe/Si heterostructures. We consider here only the thermodynamic equilibrium and homogeneous deformations of strained layer structures, recognizing that kinematic factors can influence the attainment of the equilibrium state of strain. In the final portion of the chapter we treat the case of Si-capped SiGe epilayer on Si substrate in some detail to expand the basic equilibrium theory for strained layer relaxation to such a Si /SiGe/Si geometry with two adjacent interfaces and a free surface at the top of the heteroepitaxial stack.

2.7.2 Image-Force Method for Strained Layer Relaxation In thermodynamic equilibrium, misfit dislocations appear at the interface of a strained layer heterostructure when the strained layer is thick enough that it is energetically favorable for the mismatch to be accommodated by a combination of elastic strain and interfacial misfit dislocations rather than by elastic strain alone [8]. This equilibrium critical thickness hcrit has been calculated and discussed by many authors in the continuum picture as well as through phenomenological description of dislocation dynamics [1, 3, 5, 9–14]. However, there have been many reports (e.g., in Refs. [11, 14–16]) of experimental determinations of hcrit, indicating that coherence apparently persists to thicknesses much greater than that predicted by classical equilibrium theories. The semiempirical kinetic model of Dodson and Tsao [4, 5] is more appropriate to describe the latter stages of relaxation, where the effective stress is decreasing due to a reduction in misfit strain produced by the high dislocation density. For the case of sufficiently low dislocation content in the strained layer near the point of strain relief onset, this model reduces to the equilibrium form of Matthews and Blakeslee [1, 3]. Thus the challenge remains to develop a predictive model appropriate for strained layer relaxation [17]. To introduce an appropriate continuum model, we begin by analyzing the conditions under which the strained layer relaxation should occur in metastable heterostructures, and then we modify the governing models to account for the discrepancies mentioned above. In a finite body, boundary conditions at the surface must be satisfied. For example, no forces can act on a free surface. The image-force method provides a powerful tool to solve such problems in the continuum theory of elasticity [18]. Let us now consider the schematic illustration in Figure 2.7.1. For the strained layer case, the free-surface boundary conditions are satisfied by placing an image dislocation outside the crystal such that its stress field cancels that of the real interfacial misfit dislocation at the surface. The condition is fulfilled if the selfstress of an image misfit dislocation of equal strength and opposite sign at a position 2h along the strained interface normal is superposed on the self-stress of the real primary dislocation. In general, the complete stress distribution for a mixed dislocation is given by the superposition of the stress fields of the real dislocation, the image dislocation, and a stress term derived from the Airy stress function that makes the surface traction-free. In our case of a mixed dislocation in a coaxial cylinder with its line

© 2006 by Taylor & Francis Group, LLC

2.7-129

Stability Constraints in SiGe Epitaxy

Image dislocation

h Free surface R

h

Strained layer Interface Substrate

Real primary dislocation

Real secondary dislocation p

FIGURE 2.7.1 Schematic illustration of the configuration of real and image misfit dislocations in a strained heteroepitaxial structure. The modulus of complex dislocation semispacing jRj is indicated. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

parallel to the surface, the image construction gives the dominant part of the shear stress component. Since the corresponding stress function term exerts no force component along the strained interface normal, the shear stress of the dislocation construction is approximately obtained from the shear stress of the image dislocation alone. Notice that only shear stresses in the slip system produce glide forces on a dislocation. In the continuum picture, the presence of dislocations causes strains around the line and, as a response to these, stresses as known from conventional elasticity theory. These stresses are defined by the contact forces transmitted through internal area elements. We speak of self-stresses to distinguish them from the applied misfit stresses. In linear approximation, the Volterra expression for the shear self-stress ss of a mixed straight dislocation due to its line tension in a region bounded by a coaxial cylinder of radius R is ss ¼

Gb(1 n cos2 u) aR ln 1 , 4p(1 n)R cos f b

(2:7:1)

where G is the anisotropic shear modulus in the h1 1 0i direction of the (0 0 1) plane of the epilayer material, n is its Poisson ratio, b is the magnitude of the Burgers vector, u is the angle between the dislocation Burgers vector and its line direction, f is the angle between the slip plane and the strained interface normal, and a is a factor that accounts for the energy in the dislocation core where linear elasticity does not apply. a is generally taken to be in the range from 1 to 4 for covalently bonded semiconductor materials [18]. Because of the logarithmic dependence and the R >> b Volterra regime, the elastic self-stress is insensitive to the precise value of a. We set a/2.7 ¼ 1. Here ss is considered to act on the plane containing the dislocation line direction and the interface normal. So, referred to the slip plane surface, the shear component of the self-stress of a straight dislocation ts is given by ts ¼ cos f ss. For our case, an interfacial 608-type misfit dislocation on the slip plane causes resolved shear stress, i.e., n Gb 1 R 4 ts ¼ ln , 4p(1 n)R cos f b

© 2006 by Taylor & Francis Group, LLC

(2:7:2)

2.7-130

The Silicon Heterostructure Handbook

where the ratio G /cos f is the isotropic shear modulus in the {1 1 1} slip planes. Thus, in this case the quantity bts is an image force given by the simple image construction. Under these conditions the attraction of the real primary dislocation toward the surface is obtained from the stress of the image dislocation alone. So far we have considered the image-force and shear self-stress problems for a misfit dislocation in a metastable heterostructure. As shown in Figure 2.7.1, imagine now a real secondary dislocation of equal strength and sign lying parallel to the real primary dislocation at a distance of p and moving continuously towards the primary dislocation. For further deformation under the driving force produced by the external misfit stress, it is necessary that the moving misfit dislocation overcomes the resistance caused by superposed shear self-stress field of the image dislocation and the real primary dislocation bounded by a virtual cylinder of radius R ¼ h. Note that at larger distances from the real primary dislocation the image stresses largely cancel the dislocation stresses. Now for the elastic shear stress field extension of the real interfacial misfit dislocations lying parallel to another, a reasonable approximation would be to take roughly one-half the distance p between dislocations for R in Equation (2.7.2) (see Ref. [18]). However, in this case the quantity bts is a real repulsive force that drives the real primary dislocation in its slip plane toward the surface. According to the Green function method for the elastic displacements u(R) / b/R2 and the principle of superposition of displacement fields [18], we now combine the imaginary, i.e., fictitious, and the real free-surface term of the shear self-stress of a misfit dislocation, i.e., h and p/2, respectively, and get a complex dislocation semispacing R as the first-order solution. Its modulus jRj ¼ Rh,p is given by 1 1 4 2 ¼ h2 þ p2 , Rh;p

(2:7:3)

where h is the thickness of the epilayer and the subscripts h and p stand for the fictitious and the real component, respectively. We can say that the modulus of complex dislocation semispacing Rh,p is an approximate solution for the stress-free boundary associated with the presence of two free surfaces. The relationship represented by Equation (2.7.3) is plotted in Figure 2.7.2 for different layer thicknesses h. The pursual of Figure 2.7.2 shows some interesting relationships. For dislocation spacings p greater than 5h, the modulus of complex dislocation semispacing as a measure of the extension of the elastically strained continuum about a misfit dislocation is dominated by its fictitious term, i.e., by the layer thickness h. In this case, Equation (2.7.3) reduces to Rh,p h. If p diminishes continuously, then the effect of the real term on Rh,p increases slowly. When the dislocation spacing reaches the value p 2h, the fictitious and the real free-surface terms make the same contribution to the modulus of complex dislocation semispacing. Below p h /5, as the real misfit dislocations approach one another, the effect of the fictitious component vanishes and Rh,p does not depend on h. Replacing R with Rh,p in Equation (2.7.2), the shear component of the total self-stress created by present dislocation content in a finite body becomes finally n Gb 1 Rh;p 4 ln : ts ¼ 4p(1 n)Rh;p cos f b

(2:7:4)

We notice that, up until now, we have considered a type of plane strain deformation under shear stresses, in which the body undergoes only changes of shape, but no changes of volume. Now let us consider the effect of the Airy stress function, which removes the fictitious tangential and radial normal stresses at the cylinder surface and thus changes the volume of the epilayer.

2.7.3 Surface Relaxation Stress In the case of the normal self-stress components of 608 misfit dislocations the above solution is inadequate and large additional stresses must be superposed. For such dislocations the normal selfstress components given by the simple image construction do not vanish at the free surface. The

© 2006 by Taylor & Francis Group, LLC

2.7-131

Stability Constraints in SiGe Epitaxy

Modulus of complex dislocation semispacing, Rh,p (Å)

1000 900Å

900 800 700

700Å

600 500Å

500 400

350Å 300 200

200Å

100 0 100

1⫻103

1⫻104

1⫻105

Dislocation spacing, p (Å)

FIGURE 2.7.2 Plot of the calculated modulus of complex dislocation semispacing jRj ¼ Rh,p as a function of misfit dislocation spacing p for strained layer thicknesses h ¼ 200, 350, 500, 700, and 900 A˚. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

procedure for solving this case is the same as that outlined above: first to superpose the simple image and then to devise a stress function that cancels the remaining forces acting at the free surface and thus satisfy the boundary conditions. Hirth and Lothe [18] have given the explicit solution of the Airy stress function for a pure edge dislocation in a cylinder parallel to a free surface. In analogy to the edge dislocation case, the first-order solution for a straight 608 misfit dislocation gives the normal self-stress components sf,t and sf,r that remove the fictitious plane strain and make the crystal stress-free: n Gb 1 3h b2 4 sf ;t ¼ , 2p(1 n) cos f h2 h3 n Gb 1 h b2 4 , þ sf ;r ¼ 2p(1 n) cos f h2 h3

(2:7:5a)

(2:7:5b)

where h is the distance from the interface in direction to the crystal surface. These tangential and radial stress terms are in fact the external state of stress that gives rise to the image dislocation construction, which in turn creates the state of tension within the epilayer. Then, according to the generalized Hooke’s law, the normal stress sf,n acting perpendicular to the slip plane is given by the combined effect of the tangential sf,t and radial sf,r stress components on the slip plane. Therefore, from Equations (2.7.5a) and (2.7.5b) we can write the relation

sf ;n

© 2006 by Taylor & Francis Group, LLC

n b 1 1 þ 2n h 4 ¼ : 2G(1 þ n) (1 2n)(1 þ n) 2p(1 n) cos f h2

(2:7:6)

2.7-132

The Silicon Heterostructure Handbook

Here 2G(1þn) is Young’s modulus of the epilayer. sf,n creates a state of tension between the slip planes of the epilayer. We call the normal stress sf,n the surface relaxation stress. A transformation of this normal stress into the interface plane with the tensile axis normal to the dislocation line gives the state of inplane tension within the epilayer. In these coordinates, Equation (2.7.6) yields the in-plane surface relaxation stress sf. We get sf ¼ 2 cos lsf,ncos f/cos2 f where l is the angle between the Burgers vector and the direction in the interface, normal to the dislocation line. For typical values of n from 0.26 to 0.28, the quantity (1 þ 2n)(1 – n/4)/p(1 – 2n)(1 þ n)cos2 f varies from 1.1 to 1.2, close to unity. Thus the result for the in-plane surface relaxation stress becomes approximately sf ¼

2G(1 þ n) h b cos l 2 : 1n h

(2:7:7)

In words, the in-plane surface relaxation stress decreases linearly from its maximum value at the crystal surface h ¼ h to zero at the interface h ¼ 0, whereas the strength of surface relaxation effects on the strained layer structure is related to the reciprocal of the square of the layer thickness h. Obviously, it is a remarkable result with regard to our considerations of the lattice-mismatch accommodation. When these effects are ignored and a coherency strain calculation is carried out, one obtains a spurious result, leading to an erroneous strain that acts on a misfit dislocation — image dislocation pair for its generation. In addition, these effects should play a role in the lattice resistance to plastic flow of the material. For practical purposes, a reasonable approximation would be to take an average value sfav for sf (h), i.e., sav f ¼

1 h

Z

h

0

sf ðhÞdh ¼

2G(1 þ n) b cos l : 1n 2h

(2:7:8)

Notice once again that G is the anisotropic shear modulus in the h1 1 0i direction of the (0 0 1) plane of the epilayer. Furthermore, we have measured the effect of the elastic surface relaxation on the strained layer heterostructure directly. The results are presented in Section 2.7.5.

2.7.4 Interaction between Internal Stress and External Stress For a complete description of the equilibrium state of stress in lattice-mismatched epilayers, we should now consider the resolved shear stress t that acts on the slip system as a consequence of an externally applied misfit stress. In an initially misfit dislocation-free substrate–epilayer system, the in-plane misfit strain is given by (al – as)/as, where a denotes the bulk lattice parameter and the subscripts ‘s’ and ‘l’ refer to the substrate and the layer, respectively. When the elastic strain is partially relieved by a single array of misfit dislocations created at the interface, the residual in-plane strain becomes « ¼ [(al as)/as] (b cos l/p), where the term b cos l/p represents the strain relief via plastic flow [19]. Here p is the average distance between the dislocations. Hence it follows that the lattice-mismatch accommodation would occur without in-plane tension within the epilayer caused by the surface relaxation stress. In other words, as explained above, for the case where p > h/5, the heterostructure is not tractionfree, because normal stress components acting on the crystal surface are not taken into account. To overcome this difficulty we will now substitute the modulus of complex dislocation semispacing Rh,p for p/ 2 in the residual in-plane strain expression above. So the true residual in-plane strain becomes « ¼ [(al as)/as] [b cos l/ (2Rh,p)], where the h term accounts for the purely elastic surface relaxation and the p term for plastic flow. In this case, the resolved shear stress t acting on the slip system on a misfit dislocation is given by t ¼ cos l cos f

© 2006 by Taylor & Francis Group, LLC

2G(1 þ n) a1 as b cos l : (1 n) cos f 2Rh;p as

(2:7:9)

Stability Constraints in SiGe Epitaxy

2.7-133

Thus the surface relaxation stress term is implied in the expression for the resolved shear stress that produced the driving force for plastic flow of the crystal. Note that the ratio G/cos f is the isotropic shear modulus in the {1 1 1} slip planes. As we have previously argued, a finite heterostructure is subjected to point and lattice-mismatch forces. The stresses and strains caused by such internal and external sources of stress can be superposed. We should now consider the resolved shear stress that acts on the slip system as a consequence of the externally applied stress and the elastic shear stress field due to dislocation–dislocation interactions. As shown above, during misfit strain relief via plastic flow, an intrinsic elastic stress field is built up. For further deformation, the moving misfit dislocations have to overcome the resistance caused by this stress field. Consequently, the dislocation shear self-stress field is in the direction opposite the applied misfit stress. The excess resolved shear stress required to produce plastic flow will then be given by the difference between the two stress components. Equations (2.7.4) and (2.7.9) yield texc ¼ t ts, where the second term also accounts for work hardening of the material. Combining the two terms, we obtain an expression for the excess resolved shear stress: t exc ¼ cos l cos f

2G(1 þ n) a1 as b cos l (1 þ b) ; (1 n) cos f 2Rh;p as

(2:7:10)

with b¼

Rh;p 1 (n=4) ln : 4p cos2 l cos f(1 þ n) b

Here the quantity [bcosl/(2Rh,p)]b corresponds to the decrease in active shear stress through elastic interaction between dislocations depending on the current misfit dislocation density of the crystal. As a final topic, a few words on the expression for the excess resolved shear stress are appropriate. This is a convenient expression. The applications are numerous: problems of elastic strain retained by the epilayer, equilibrium critical thickness of a SiGe layer on Si substrate, initial and residual in-plane strain, film stress, work hardening of the material, degree of elastic and plastic strain relaxation, and misfit dislocation density reached at the equilibrium strain state, for example. Some of the applications are discussed in the following sections.

2.7.5 Critical Thickness and Film Stress of SiGe/Si Layers To demonstrate the physical significance of the present approach in equilibrium theory for strained layer relaxation proposed here, we have calculated the equilibrium critical thickness of Si1xGex /Si strained layer structures as a function of the fractional atomic Ge content x. We have compared our results with those predicted by classical relaxation models, which do not include surface relaxation effects and dislocation–dislocation interactions. Taking the in-plane misfit strain [(al as)/as] ¼ 0.0418x , Equations (2.7.3) and (2.7.10) and the equilibrium conditions for the point of strain relief onset via plastic flow, i.e., texc ¼ 0 and p ! 1, lead to the following expression for the critical strained layer thickness hcrit: 2 3 n 1 b cos l 4 h crit 4 5: ln 1þ x¼ 0:0836hcrit 4p cos2 l cos f(1 þ n) b

(2:7:11)

In the absence of surface relaxation forces, the equilibrium critical thickness of a single strained epilayer upon a substrate of different lattice parameter according to Matthews and Blakeslee is given by the formulation reported in Ref. [1]. Inserting appropriate material parameters in Equation (2.7.11) and in the Matthews–Blakeslee formulation, cos l ¼ 0.5, cos f ¼ 0.816, n ¼ 0.36 (in the (1 1 1) plane) [21],

© 2006 by Taylor & Francis Group, LLC

2.7-134

The Silicon Heterostructure Handbook

and b ¼ 3.84 A˚ for growth on the (0 0 1) surface, the equilibrium critical thickness calculated for the two different models is plotted in Figure 2.7.3. It is seen, at first glance, that our values of hcrit represented by Equation (2.7.11) are much larger than the values calculated using equation of Matthews and Blakeslee. Moreover, for a fractional atomic Ge content x greater than 0.5, the Matthews–Blakeslee formulation does not provide any value for hcrit. Additionally, we have compared our theoretical results with the published experimental data [14, 15] of hcrit obtained from Si1xGex /Si structures, grown by molecular beam epitaxy (MBE) at a growth temperature of 7508C. For each composition, there is good agreement between our theoretical results and experimental data reported. For example, for x ¼ 0.25, hcrit was found to be approximately 200 A˚. As seen in Figure 2.7.3, for this case, our analysis yields the value of 200 A˚. The Matthews–Blakeslee model predicts only an equilibrium critical thickness value of 60 A˚. So far, we have been considering the equilibrium critical thickness of a coherently strained structure. Let us now consider film stresses for elastically strained Si1–xGex /Si layers. For the pseudomorphically strained layer case, where p ! 1, according to the previous equation (2.7.9), the in-plane film stress s becomes 2G(1 þ n) b cos l 0:0418x : s¼ (1 n) 2h

(2:7:12)

This equation can then be used to predict the stress response to a strain increment, which is related to the volume change of the layer. The first term on the right-hand side corresponds to a volume expansion due to Ge incorporation and the second one to a volume contraction via surface relaxation. Thus the residual in-plane strain is given by « ¼ 0.0418x (b cos l/2h). Figure 2.7.4 shows a plot of s versus h for x ¼ 0.3, n ¼ 0.28 (in the (1 0 0) plane) [21], and G ¼ 51 GPa. This relationship between coherency stress and surface relaxation stress has also been studied experimentally. The in-plane epitaxial film stress s as a function of layer thickness was measured by a thin-film stress measuring apparatus, which

x = 0.3 2.5 In-plane misfit stress

2.1 Stress (GPa)

Equilibrium critical thickness, hcrit (Å)

103

100

1.7 1.3 In-plane film stress σ

F MB

10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Ge content, x

FIGURE 2.7.3 Comparison of predicted equilibrium critical thickness hcrit for relaxation models based on a nonstress-free body (MB, Matthews–Blakeslee) and a stress-free body (F, this study) as a function of Ge content x. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

0.9 0.5 100

200 300 400 500 SiGe layer thickness, h (Å)

600

FIGURE 2.7.4 Theoretical (solid line) and experimental (?) in-plane epitaxial film stress s as a function of thickness h for as-grown SiGe/Si. The in-plane misfit stress (elastic coherency stress) corresponding to a strain of 0.0418x is also shown. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54: 8761–8768, 1996. With permission.)

2.7-135

Stability Constraints in SiGe Epitaxy

measures the changes in the radius of curvature of a substrate created by deposition of a stressed thin film on its surface. Our experimental data are also shown in Figure 2.7.4. To our knowledge, such measurements of surface relaxation stresses have not been reported previously. It is seen that there is good agreement between our theoretical results and experimental data. This tells us that the elastic coherency stress of the strained material in the plane of the surface is really affected by a large surface relaxation stress.

2.7.6 Plastic Deformation and Work Hardening in SiGe/Si SiGe/Si structures may be grown to substantially greater thickness than our equilibrium critical thickness predictions, before misfit dislocation nucleation and propagation are observed. The heterostructure becomes metastable during growth because texc > 0. This metastable growth regime is concerned with the initial period of creep of diamond structure materials, in which marked plastic deformation under static load does not start abruptly. In our case of strained layer relaxation, such an initial period is characterized by an incubation time encouraged by lower growth temperature and lattice mismatch. The initial creep period is finally terminated by the onset of in-plane strain relief via plastic flow. The ramifications of our model for plastic flow and work hardening in Si1xGex /Si strained layer structures will now be discussed. According to Equation (2.7.9), the in-plane film stress s becomes s¼

2G(1 þ n) b cos l : 0:0418x (1 n) 2Rh;p

(2:7:13)

Putting the values of the material parameters into Equations (2.7.4), (2.7.10), and (2.7.13), assuming a metastable epilayer with x ¼ 0.3 and h ¼ 500 A˚, and recalling Equation (2.7.3), we can evaluate the variation in excess resolved shear stress texc acting on the slip system and in-plane epitaxial film stress s for the complete thermal relaxation process. At the beginning of deformation, where p ! 1, texc ¼ 0.7 GPa and s ¼ 1.9 GPa, as illustrated in Figure 2.7.5. During plastic flow via misfit dislocation generation and propagation, texc and s diminish continuously and then remain unchanged at zero and 1.15 GPa, respectively, whereas the shear self-stress component ts rises to its maximum value. At this equilibrium deformation stage, the externally applied misfit stress and the shear component of elastic stress field due to dislocation interaction compensate one another and strain relief via plastic flow comes to rest. Thus, as a result of work hardening, the lattice-mismatched epilayer will remain in a certain state of strain at the end of thermal relaxation process, i.e., the strained layer is in a stable state. It should be mentioned here that investigations by Gillard et al. [20] suggest that dislocation blocking plays a certain role in limiting strain relaxation. We believe, as shown in the present and the previous sections, that the creep process in all the stages of strain relaxation in these structures is essentially determined by a purely elastic interaction between dislocations, which leads ultimately to work hardening of the material. Further experiments would be required to assess the relative contribution from blocking mechanism. For homogenous deformation, our equilibrium theory for strained layer relaxation is able to predict the degree of in-plane misfit strain relaxation both at the point of onset of plastic flow and at the point of equilibrium strain state where the plastic flow comes to rest. Returning to Equation (2.7.13), which is the general in-plane film stress equation, we define the degree of strain relaxation g as the relative lattice-mismatch accommodation by elastic surface relaxation and interfacial misfit dislocations compared to mismatch accommodation by the elastic in-plane strain alone. It can be written as the ratio of the in-plane strain relief to the in-plane misfit strain (coherency strain). For Si1xGex /Si heterostructures, we get g¼

© 2006 by Taylor & Francis Group, LLC

b cos l : 0:0836xRh;p

(2:7:14)

2.7-136

The Silicon Heterostructure Handbook

2

x = 0.3, h = 500 Å

1.75

s

1.25 1

Strain relief via plastic flow

0.75

texc

Equilibrium strain state

Stress (GPa)

1.5

0.5 ts 0.25 0 2500

2000 1500 1000 500 Dislocation spacing, p (Å)

0

FIGURE 2.7.5 Decrease in the in-plane epitaxial film stress s and excess resolved shear stress texc during strain relief via plastic flow as a function of the dislocation spacing p. The shear self-stress component ts, the direction of strain relief via plastic flow, and the equilibrium strain state at the end of the thermal relaxation process are indicated. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

For the point of strain relief onset via plastic flow, where p ! 1, Equation (2.7.14) reduces to gel ¼ bcos l/0.0836xh, which can be a general expression for the degree of elastic strain relief via surface relaxation. gel is a constant for a given metastable or stable SiGe /Si strained layer system. Again, according to Equation (2.7.14), the degree of total strain relaxation gt(0) for the point of equilibrium strain state at the end of thermal relaxation process is given by gt(0) ¼ b cos l/0.0836xRh,p(0), where the subscript p(0) stands for the misfit dislocation spacing reached at the equilibrium deformation stage. In our case, for Si0.7Ge0.3/Si, h ¼ 500 A˚, we get gel ¼ 0.15 and gt(0) ¼ 0.49 with p(0) ¼ 330 A˚. As the corresponding degree of plastic strain relaxation is gpl(0) ¼ gt(0) gel, we thus have gpl(0) ¼ 0.34. Thus, as stated previously, the lattice-mismatched epilayer remains in a certain state of strain at the end of thermal relaxation process. For the given heterosystem, as a result of work hardening, the residual inplane strain is approximately 51%. Again, an elastic strain of 15% is retained in the epilayer by surface relaxation effects and about 34% of the in-plane strain due to lattice mismatch is relieved via plastic flow. It should be noted that, up to now, neither equilibrium theory was able to predict the correct relaxed strain in heteroepitaxial films.

2.7.7 Force Balance Model for Buried SiGe Strained Layers Up to now, both the classical force balance [1, 3–5, 11, 22, 23)], and energy minimization [15, 24] approaches for the determination of the critical thickness hcrit of a coherently strained layer structure at which dislocations form cannot predict this value for a Si-capped SiGe epilayer on Si substrate. The main difficulties to determine the exact strain relief onset via plastic flow in Si /SiGe/Si multilayer structures frequently arise because the classical theories are insensitive both to the effect of the free surface and the ratio of the stored elastic strain energy in the Si cap layer to that in the buried SiGe layer. Within the classical theoretical framework, it is impossible to decide at which cap layer thickness the plastic relaxation may take place through single misfit dislocation injection at the lower SiGe /Si interface

© 2006 by Taylor & Francis Group, LLC

2.7-137

Stability Constraints in SiGe Epitaxy

or through the generation of misfit dislocation dipoles with segments located at both interfaces. Detailed experimental results of hcrit for different cap layer thicknesses have also not been available. Here we extend the basic image-force equilibrium model for strained layer relaxation explained above to Si/SiGe/Si layers with a free surface at the top of the heteroepitaxial stack. The solution of the force balance problem will be carried out in plane stress [25] assuming equal elastic moduli. Far from any lateral free surface and referred to the slip plane {1 1 1} and slip directions h1 1 0i, the state of stress is uniformly biaxial of magnitude t, which is related to the in-plane strain « through t ¼ cos l cos f

2Gð1 þ nÞ «: ð1 nÞ cos f

ð2:7:15Þ

The misfit strain arising from the lattice parameter difference between silicon and germanium in a SiGe epilayer on Si substrate is 0.0418x. In a Si /SiGe /Si heterostructure, the strain that acts on a misfit dislocation–image dislocation pair for its generation is given by [26] « ¼ 0:0418x

b cos l ; 2(h þ H)

(2:7:16)

where h and H are the thicknesses of the buried SiGe layer and the Si cap layer, respectively. This relation includes the surface relaxation effects on the strained layer stack and makes the crystal stress-free at the surface to satisfy the boundary conditions [17, 18]. Counteracting the shear stress component t are the dislocation self-stress terms [11, 26]. These are associated with the strain energy required to create straight misfit dislocation segments at interfaces and the dislocation–dislocation interaction energy between the two parallel segments. The self-stress of a strain-relaxing 608 misfit dislocation on the slip plane of the lower SiGe/Si interface is

t SiGe

n Gb 1 hþH 4 ln ; ¼ 4p(1 n)h cos f b

(2:7:17:1)

where h þ H is the outer cutoff distance of the interfacial dislocation, a measure of the energy stored in the elastic stress field of the misfit dislocation. Note that the strain energy can be regarded as either the work done on a radial cylinder cut surface in creating the dislocation or, equivalently, by Stoke’s theorem, the stored elastic strain energy in a coaxial cylinder containing the dislocation. Then, the selfstress of a misfit dislocation on the slip plane of the upper Si /SiGe interface is of the form n Gb 1 H 4 ln ; t Si ¼ 4p(1 n)h cos f b

(2:7:17:2)

where, in this case, H is the outer cutoff distance of the strain-relaxing interfacial dislocation, identical to the cap layer thickness. The attraction of the dipole segments of equal strength and opposite sign lying on adjacent interface planes is given by a stress term connected with a negative dislocation–dislocation interaction energy between the two parallel segments [18, 27]:

t Si=SiGe

n Gb 1 hþH 4 ln : ¼ 4p(1 n)h cos f h

(2:7:17:3)

where the negative interaction energy represents the decrease in free energy of the crystal when the dipole segments of opposite sign are brought together from a distance of h þ H to a separation h. Since the free energy change is a state function, it is independent of the path taken.

© 2006 by Taylor & Francis Group, LLC

2.7-138

The Silicon Heterostructure Handbook

Now consider the ratio of the stored misfit strain in the Si cap layer to that in the buried SiGe layer of a coherent Si /SiGe/Si system to find a measure for the stored elastic strain energy in the layers to drive misfit dislocation generation. This ratio is also a measure for the different frequency of the occurrence of misfit dislocations at the heterointerfaces. The total misfit strain «t in a Si-capped SiGe epilayer with an average value of the fractional atomic Ge content xh /(h þ H) (see Equation (2.7.11)) is given by «t ¼ 0:042x

h : hþH

(2:7:18:1)

Taking only the misfit strain «b in the buried SiGe layer, Equation (2.7.18.1) leads for H ¼ 0 to the wellknown expression «b ¼ 0:042x:

(2:7:18:2)

The misfit strain «c in the Si cap layer will then be given by the difference between the two strain components «t and «b . Thus we have finally «c ¼ 0:042x

H : hþH

(2:7:18:3)

This shows that, if the buried SiGe layer incorporates the nucleation energy for one misfit dislocation, the Si cap layer holds energy only for H /(hþH) misfit dislocations. This energy density factor, denoted by d can vary from zero for a capless structure up to 1 for an infinitely thick Si cap layer. In the latter case, only misfit dislocation dipoles occur during strained layer relaxation. Note that, up to now, no equilibrium or energy minimization model takes into account the stored elastic strain energy in the Si cap layer. The excess resolved shear stress texc driving the bending of threading dislocations to form single and / or double misfit dislocation segments will then be given by the difference between the external stress t [Equations (2.7.15) and (2.7.16)] and the internal stress components tSiGe, tSi, tSi–Ge [Equations (2.7.17.1)–(2.7.17.3)]. Including the energy density factor d (from Equations (2.7.18.1)–(2.7.18.3)), we have texc ¼ t tSiGe dtSi dtSi–SiGe. Taking the equilibrium condition for the point of strain relief onset via plastic flow, i.e., texc ¼ 0, this force balance approach leads to the following implicit expression for the critical strained layer thickness hcrit as a function of the Ge content x and the cap layer thickness H: 2 3 n 1 b cos l 4 hcrit hcrit þ H H hcrit þ H 5 4 þ d ln d ln þ ln x¼ 0:0836hcrit hcrit þ H 4p cos2 l cos f(1 þ n) b b hcrit with d ¼

(2:7:19)

H : hcrit þ H

This formulation gives a generalized statement of the balance between external and internal forces acting at planar Si /SiGe /Si structures. It is a measure of the transition from the thermodynamically stable to the metastable state of the strained layer system. Finally, it is worth considering the transition thickness for loss of coherency in uncapped SiGe heterostructures. For H ¼ 0, we easily obtain the solution for the critical thickness of a SiGe /Si layer substrate system given by Equation (2.7.11). Inserting appropriate material parameters given above in Equation (2.7.19) the equilibrium critical thickness hcrit calculated for the Si cap layer thicknesses H ¼ 0, 500 A˚, and 1000 A˚ is plotted versus Ge content of the SiGe layer in Figure 2.7.6. Our experimental data obtained from MBE [26, 28] and chemical vapor deposition (CVD) epitaxy [26, 29] are also shown. The agreement between calculated and measured values is evident.

© 2006 by Taylor & Francis Group, LLC

2.7-139

Stability Constraints in SiGe Epitaxy

750 H = 1000 Å

H = 500 Å H = 0

Equilibrium critical thickness, hcrit (Å)

650

550

Area with misfit dislocations

450

350

250

150 0.05

Area without misfit dislocations

0.1

0.15

0.2

0.25

Ge content (x)

FIGURE 2.7.6 Theoretical values (solid lines) and experimental measurements (symbols) of the equilibrium critical thickness hcrit as a function of fractional atomic Ge content x for different Si cap layer thicknesses H. The open data points correspond to structures that maintained coherency; the filled data points correspond to structures that became partially incoherent. The x-ray measuring accuracies are Dh, DH ¼ 10 A˚, and Dx ¼ 0.005. For comparison, the predicted equilibrium critical thickness for relaxation models based on a nonstress-free body (From JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations. Journal of Crystal Growth 27:118–125, 1974; JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: III. Preparation of almost perfect multilayers. Journal of Crystal Growth 32:265–273, 1976) is shown by the dotted line for uncapped SiGe/Si heterostructures. (From A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. Solid-State Electronics 44:869–873, 2000. With permission.)

2.7.8 Summary In this chapter I have attempted to provide a physical basis for a different approach in equilibrium theory for strain relaxation in metastable heteroepitaxial semiconductor structures. This approach includes the surface relaxation effects on the strained layer structure and the elastic interaction between straight misfit dislocations. The main purpose of this work was to develop a straightforward treatment, valid in linear elasticity, for the relatively complicated case of deformation of a finite body containing internal stresses and subjected to lattice-mismatch forces. The model we have outlined yields an expression in terms of the excess resolved shear stress for strained layer relaxation, so that the elastic strain retained by the epilayer, the equilibrium critical thickness of the strained layer, the initial and residual in-plane strain, the film stress, work hardening effects on the material, the degree of strain relaxation, and the misfit dislocation density, reached at the equilibrium strain state, can be predicted. I believe that the image-force method proposed here provides an equilibrium theory that correctly predicts the coherency and relaxation behavior of SiGe/Si and Si /SiGe/Si heterostructures. Finally, this more refined model yields better agreement between computed and measured values, and provides a consistent picture of the complex mechanism for strain relief and defect propagation in a strained layer on a lattice-mismatched substrate.

© 2006 by Taylor & Francis Group, LLC

2.7-140

The Silicon Heterostructure Handbook

References 1. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations. Journal of Crystal Growth 27:118–125, 1974. 2. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: II. Dislocation pile-ups, threading dislocations, slip lines and cracks. Journal of Crystal Growth 29:273–280, 1975. 3. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: III. Preparation of almost perfect multilayers. Journal of Crystal Growth 32:265–273, 1976. 4. BW Dodson and JY Tsao. Relaxation of strained-layer semiconductor structures via plastic flow. Applied Physics Letters 51:1325–1327, 1987. 5. BW Dodson and JY Tsao. Erratum: relaxation of strained-layer semiconductor structures via plastic flow. Applied Physics Letters 52:852, 1988. 6. E Kasper and HJ Herzog. Elastic strain and misfit dislocation density in Si0.92Ge0.08 films on silicon substrates. Thin Solid Films 44:357–370, 1977. 7. A Fischer and H Richter. On plastic flow and work hardening in strained layer heterostructures. Applied Physics Letters 64:1218–1220, 1994. 8. GC Osbourn. Strained-layer superlattices: a brief review. IEEE Journal Quantum Electronics QE22:1677–1681, 1986. 9. DC Houghton. Misfit dislocation dynamics in Si1–xGex /(100)Si: Uncapped alloy layers, buried strained layers, and multiple quantum wells. Applied Physics Letters 57:1434–1436, 1990. 10. DC Houghton. Nucleation rate and glide velocity of misfit dislocations in Si1–xGex /(100) Si heterostructures. Applied Physics Letters 57:2124–2126, 1990. 11. DC Houghton. Strain relaxation kinetics in Si1–xGex /Si heterostructures. Journal of Applied Physics 70:2136–2151, 1991. 12. R Hull, JC Bean, DJ Werder, and RE Leibenguth. Activation barriers to strain relaxation in latticemismatched epitaxy. Physical Review B 40:1681–1684, 1989. 13. R Hull. Equilibrium theories of misfit dislocation networks in the SiGe /Si system. In: E Kasper (ed.), Properties of Strained and Relaxed Silicon Germanium. London: Inspec, 1995. 14. E Kasper. Strained layer superlattices. In: EE Mendez and K von Klitzing (eds), Physics and Applications of Quantum Wells and Superlattices. New York: Plenum Press, 1987. 15. R People and JC Bean. Calculation of critical layer thickness versus lattice mismatch for GexSi1–x /Si strained layer heterostructures. Applied Physics Letters 47: 322–324, 1985. 16. BA Fox and WA Jesser. The effect of frictional stress on the calculation of critical thickness in epitaxy. Journal Applied Physics 68:2801–2808, 1990. 17. A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. 18. JP Hirth and J Lothe. Theory of Dislocations. New York: McGraw-Hill, 1968. 19. JR Willis, SC Jain, and R Bullough. Work hardening and strain relaxation in strained-layer buffers. Applied Physics Letters 59:920–922, 1991. 20. VT Gillard, WD Nix, and LB Freund. Role of dislocation blocking in limiting strain relaxation in heteroepitaxial films. Journal of Applied Physics 76:7280–7287, 1994. 21. JJ Wortmann and RA Evans. Young’s modulus, shear modulus, and Poisson’s ratio in silicon and germanium. Journal of Applied Physics 36:153–156, 1965. 22. CG Tuppen and CJ Gibbings. A quantitative analysis of strain relaxation by misfit dislocation glide in Si1–xGex /Si heterostructures. Journal of Applied Physics 68:1526–1534, 1990. 23. R Hull, JC Bean, D Bahnck, LJ Peticolas Jr, and KT Short. Interpretation of dislocation propagation velocities in strained GexSi1–x /Si(100) heterostructures by the diffusive kink pair model. Journal of Applied Physics 70:2052–2065, 1991. 24. JH van der Merwe. Structure of epitaxial crystal interfaces. Surface Science 31:198–228, 1972. 25. SP Timoshenko and NJ Goodier. Theory of Elasticity. New York: McGraw-Hill, 1982.

© 2006 by Taylor & Francis Group, LLC

Stability Constraints in SiGe Epitaxy

2.7-141

26. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 27. FRN Nabarro. The mathematical theory of stationary dislocations. Advances in Physics 1:269–394, 1952. 28. H-J Osten, HP Zeindl, and E Bugiel. Considerations about the critical thickness for pseudomorphic Si1–xGex growth on Si(001). Journal of Crystal Growth 143:194–199, 1994. 29. B Tillack, HH Richter, G Ritter, A Wolff, G Morgenstern, and C Eggs. Monitoring of deposition and dry etching of Si /SiGe multiple stacks. Journal Vacuum Science Technology B 14:102–105, 1996.

© 2006 by Taylor & Francis Group, LLC

2.8 Electronic Properties of Strained Si/SiGe and Si1yCy Alloys 2.8.1 2.8.2 2.8.3

Introduction............................................................... 2.8-143 Strain and its Impact on Energy Bands .................. 2.8-143 Measurements of Energy Band Lineups.................. 2.8-147 The Strained Si/Strained Si1yGey/Relaxed Si1xGex System . The Si/SiC System

Judy L. Hoyt Massachusetts Institute of Technology

2.8.4 2.8.5

Introduction to Transport Properties...................... 2.8-152 Summary .................................................................... 2.8-153

2.8.1 Introduction Knowledge of the basic electronic properties of silicon-based heterostructures is essential to understand their applications. This chapter is a review of the electronic properties of strained SiGe, strained Si on relaxed SiGe, and a brief introduction to strained Si1yCy /Si heterostructures. Because the energy band lineups are critical in determining the types of applications of these materials, the emphasis here is on reviewing theoretical and experimental determinations of the energy band lineups (Sections 2.8.2 and 2.8.3). Section 2.8.4 introduces transport properties in such materials, with an eye towards field-effect transistor (FET) applications, though readers are referred to other chapters of this volume for details on transport and FET applications.

2.8.2 Strain and its Impact on Energy Bands Figure 2.8.1(a) schematically illustrates the relaxed, or equilibrium lattice structures for Si, random Si1xGex alloys, and Ge. The equilibrium lattice parameters a0 for Si and Ge are 5.431 and 5.646 A˚, respectively [1]. This corresponds to a lattice mismatch to Si m ¼ 100

a0 (alloy) a0 (Si) a0 (Si)

equal to approximately 4.1% (for pure Ge). When an alloy is formed of Si and Ge the equilibrium lattice parameter can roughly be linearly interpolated between a0 for Si and Ge, though there is a slight negative deviation from Vegard’s law [1]. Figure 2.8.1(b) illustrates the case of pseudomorphic epitaxial growth in which the in-plane lattice parameter of the epitaxial layer compresses or stretches in order to match that of the substrate, and the out-of-plane parameter is elongated or compressed accordingly. Thus, when strained SiGe is grown pseudomorphically on relaxed Si (left-hand side of Figure 2.8.1(b)), the layer experiences in-plane biaxial compression. Conversely, when a thin layer of strained Si is grown on 2.8-143 © 2006 by Taylor & Francis Group, LLC

2.8-144

The Silicon Heterostructure Handbook

(a) Relaxed (equilibrium) lattices

a0

Si

Ge

Si1−xGex

(b) Pseudomorphic growth

Biaxial compression

Biaxial tension

FIGURE 2.8.1 Schematic illustration of the lattice structures for (a) relaxed Si, Si1xGex, and Ge, and (b) pseudomorphic epitaxial layers of strained SiGe on Si in biaxial compression (left-hand side), and of strained Si on relaxed SiGe in biaxial tension (right-hand side). The symbol a0 refers to the equilibrium lattice parameter of the material.

relaxed SiGe (right-hand side of the figure), the Si experiences biaxial tensile stress. As will be discussed below, the energy band lineups are quite different in these two cases, and determine, to a large extent, the device applications relevant for the two materials structures. Perfect pseudomorphic growth is only possible up to a certain strained layer thickness, above which misfit dislocations form and the strain begins to relax, as discussed elsewhere in this handbook. Si and Ge are completely miscible and the full range of alloy compositions can be grown in single crystal form. This is not true of Si and C, though it is possible to grow alloys of Si1yCy with up to 2 at.% C in substitutional lattice sites. The lattice mismatch between Si and Si0.5C0.5 is 20%, much larger than that between Si and Si0.5Ge0.5 (þ2%). Si1yCy layers containing up to a few percent C can be grown pseudomorphically on Si, with the Si1yCy layer experiencing biaxial tensile stress, analogous to the case of strained Si on relaxed SiGe. Growth of Si1yCy is discussed elsewhere in this handbook. Perhaps the most well-known electronic property of SiGe alloys is the reduction in the indirect energy bandgap compared to that of Si as Ge is added to the alloy. Figure 2.8.2 shows the energy bandgap difference, DEg ¼ Eg(SiGe) Eg(Si) between SiGe alloys and Si as a function of the Ge percentage in the alloy. The upper curve corresponds to the data for unstrained or relaxed alloys, measured by Braunstein et al. by optical absorption at 300 K [2]. The conduction band minimum is along the D direction in the Brillion zone for alloy compositions up to roughly 85% Ge [2]. For higher Ge contents, where the magnitude of the bandgap difference increases rapidly with Ge composition, the conduction band minimum appears along the L direction, similar to that for pure Ge. The remainder of the data in Figure 2.8.2 corresponds to DEg for strained SiGe grown on relaxed Si. As shown in the figure, DEg as determined from photocurrent measurements by Lang et al. [3], and extracted from heterojunction bipolar transistors (HBTs) by King et al. [4], is in reasonable agreement with theoretical predictions by People [5]. It is clear that strain makes a large contribution to the bandgap reduction in SiGe. This is true in general in silicon-based heterostructures, where the strain splitting of degeneracies at the band edges tends to close the bandgap relative to the unstrained state, as discussed below. Note that the electron affinity of relaxed SiGe alloys is not well documented in the literature. Morar et al. employed electron-energy-loss

© 2006 by Taylor & Francis Group, LLC

2.8-145

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

Energy bandgap difference Eg(SiGe) − Eg(Si)(eV)

0 Unstrained (Braunstein et al., 300 K)

−0.1 −0.2 −0.3

HBT (King et al., ~ 300K )

−0.4

Strained SiGe on Si Photocurrent (Lang et al., 90 K)

−0.5 −0.6

Calculation (People)

0

20

40

60

80

100

Ge percentage (%)

FIGURE 2.8.2 The energy bandgap difference, DEg ¼ Eg(SiGe) Eg(Si) between SiGe alloys and Si as a function of the Ge percentage in the alloy. The upper curve is for unstrained alloys, measured by Braunstein et al. by optical absorption at 300 K [2]. The remainder of the data corresponds to DEg for strained SiGe grown on relaxed Si, including photocurrent measurements by Lang et al. (?) [3], and heterojunction bipolar transistors (HBTs) by King et al. (~) [4]. The hatched region represents the range of theoretical predictions due to uncertainties in the values of the deformation potentials [5]. (From C.A. King, J.L. Hoyt, and J.F. Gibbons. Bandgap and transport properties of Si1xGex by analysis of nearly ideal Si /Si1xGex /Si heterojunction bipolar transistors. IEEE Trans. Elec. Dev. 36:2093– 2104, 1989. With permission.)

spectroscopy to extract the variation in the conduction band minimum for a range of relaxed SiGe alloy compositions [6], which gives some indication of electron affinity variation. In many applications, it is assumed that the conduction bands of relaxed Si and relaxed SiGe are closely aligned. Figure 2.8.3 illustrates the energy band lineups for some important silicon heterostructures, including (a) compressively strained SiGe on relaxed Si and (b) strained Si grown on relaxed SiGe. The band alignment for strained SiGe on Si (a) is such that almost all of the bandgap difference appears in the valence band [7]. This material is thus ideally suited for the fabrication of npn Si /SiGe/Si heterojunction bipolar transistors, as well as for applications such as p-channel FETs where confinement of holes in the SiGe layer is desired. Strained Si on relaxed SiGe results in a Type II alignment, with electrons preferentially populating the strained Si layers and holes the SiGe layers (Figure 2.8.3(b)). In the figure, DEs represents the strain-induced energy splitting of the conduction band minimum, where the sixfold degenerate conduction band at the D point splits into a set of twofold (D2) and fourfold (D4) degenerate valleys. The constant energy surfaces corresponding to these valleys are shown in Figure 2.8.3(c). DEs is directly proportional to the lattice distortion, and can be calculated from deformation potential theory [8, 9]. It can be shown that DEs corresponds to roughly 67 meV/10% Ge in the substrate, for strained Si on relaxed SiGe, and approximately 66 meV/1% C for strained Si1yCy on cubic Si [10], as illustrated in Figure 2.8.3(d). The strain-induced splitting of the conduction band degeneracy for strained Si on relaxed SiGe leads to a configuration that is particularly favorable to inplane electron transport [11, 12]. In this case, electrons preferentially occupy the lower-energy D2 conduction band, which has a smaller in-plane effective transport mass than for the case of unstrained Si, where the in-plane effective mass is calculated by averaging over all six valleys. In addition to this effect, intervalley scattering is suppressed by the conduction band energy splitting. These effects contribute to the enhanced electron mobility in strained Si that is being leveraged in CMOS circuits, as discussed in Chapter 5 of this handbook.

© 2006 by Taylor & Francis Group, LLC

2.8-146

The Silicon Heterostructure Handbook

(a) ∆ES

D2

(b)

D4

∆ES ~ 67 mev/ 10%Ge EC

D6

Strained Si1−xGex

D4

D6

D2 Strained Si

Cubic Si

Cubic Si1−x Gex HH & LH

(c)

D4

(d) ∆ES = 66 meV /1%C

[0 0 1]

D6 D2

EC

C ubic Si

S trained Si1−y Cy ∆4Valleys

EV

EV

HH & LH ∆2Valleys

EC

[0 1 0] HH & LH

[1 0 0]

EV

FIGURE 2.8.3 Energy band lineups for various silicon heterostructures, including (a) compressively strained SiGe on relaxed Si and (b) strained Si grown on relaxed SiGe. The heavy solid lines indicate the band edges. DEs represents the strain-induced energy splitting of the conduction band minimum. The conduction band constant energy surfaces are shown in (c), and the band lineup for strained Si1yCy on cubic (relaxed) Si is illustrated in (d).

(a) Tensile stress EC

D4

D6

D2 EV

LH & HH

LH

EC EV

HH Relaxed

Hydrostatic stress

Biaxial stress

D2 EC

D6

D4 HH

EV

LH & HH

EC EV

LH

(b) Compressive stress

FIGURE 2.8.4 Schematic illustration of the effects of hydrostatic and biaxial stress on the energy bands in Si for (a) tensile and (b) compressive stress.

Biaxial strain can be decomposed into a hydrostatic contribution (equal dilation in all three directions) plus uniaxial strain in the direction normal to epitaxial growth. The hydrostatic component leads to an energy band shift (and change of the bandgap) while the uniaxial component results in a splitting of the conduction and valence band edge degeneracies. Figure 2.8.4 shows schematically the effects of hydrostatic and biaxial stress on the energy bands in Si for both (a) tensile and (b) compressive stress. For example, biaxial tensile stress (a) corresponds to hydrostatic tension combined with uniaxial compression in the z-direction. For this case, a uniform hydrostatic stretching of the lattice shifts the conduction and valence band edges to lower energies relative to their equilibrium positions, while the uniaxial contribution induces a splitting that does not affect the average band energy. The D2 and D4 bands move in opposite directions and the D2 level moves by twice the amount as the D4 level. One can

© 2006 by Taylor & Francis Group, LLC

2.8-147

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

also see from the figure that in the absence of other (e.g., chemical) effects, biaxial tension favors the introduction of a conduction band offset while biaxial compression tends to produce a valence band offset. This is due to the particular way in which hydrostatic and uniaxial stress affect the bands. Strain effects are only part of the story of the energy band lineup at a heterointerface. Another effect comes from the chemical difference between the two semiconductor materials. Van de Walle and Martin were the first to discuss both the chemical and strain effects on the band alignment, and presented a methodology for calculating the valence band offsets in the Si /Ge system for various strain states [13]. Figure 2.8.5 shows the energy bands as calculated by Van de Walle for both strained SiGe on cubic Si (biaxial compression) and strained SiGe on cubic Ge (biaxial tension). For thorough theoretical reviews of the calculation of energy band lineups and the impact of stress on the band offsets, the reader is referred to Refs. [13–16]. Rieger and Vogl [15] and Schaffler [16] calculated and plotted the theoretical conduction and valence band offsets for a Si1yGey strained layer on a Si1xGex substrate.

2.8.3 Measurements of Energy Band Lineups For compressively strained SiGe on cubic Si with Ge contents below 50% it is reasonably well established that the conduction band offset is less than 20 meV. In fact, rigorous studies using photoluminescence suggest that the Si and strained SiGe conduction bands are very close to each other for a Ge composition of 30% [17]. In the case of strained Si /strained SiGe/relaxed SiGe heterostructures, the uncertainty in the theoretical values of the band lineups can be as high as +100 meV, particularly for higher Ge contents, which is too large for device applications. For example, in heterojunction bipolar transistor applications, the collector current varies exponentially with the band offset DEg /kT, and in FETs the threshold voltage is often proportional to an energy band offset in the heterostructure. Hence, accurate determination of

Strained Si1−xGex grown on cubic Si (0 0 1)

Strained Si1−xGex on cubic Ge (0 0 1)

2.0

2.0 Conduction bands

L

L D4 Conduction bands

Energy (eV)

D2 1.17 1.0 0.84

D4

1.0

Eg (Si1−x Gex)

0.74 D2

Valence bands

0.0

0.0 0 Si

0.5 Ge fraction (x)

1 Ge

0 Si

Valence bands

0.5 Ge fraction (x)

1 Ge

FIGURE 2.8.5 Energy bands as calculated by Van de Walle and Martin [13] for both strained SiGe on cubic Si (biaxial compression) and strained SiGe on cubic Ge (biaxial tension). The three strain-split valence bands represent the heavy hole, light hole, and split-off hole bands. The dashed lines represent the weighted average positions of the conduction and valence bands before the uniaxial strain splitting is taken into account. It should be noted that the data of Braunstein et al. [2] were used to place the weighted average conduction band relative to the valence bands. (From G.G. Van de Walle and R.M. Martin. Theoretical calculations of heterojunction discontinuities in the Si /Ge system. Phys. Rev. B 34: 5621–5634, 1986. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-148

The Silicon Heterostructure Handbook

such quantities is required. The following sections discuss measurements of the energy band lineups in silicon heterostructures.

The Strained Si/Strained Si1yGey/Relaxed Si1xGex System There are a number of methods used for estimating energy band offsets at semiconductor heterojunctions, including methods such as photoluminescence and x-ray photoelectron spectroscopy (XPS). XPS generally has error bars on the order of 0.1 eV, too large for electronic device applications. Electrical techniques such as admittance spectroscopy and capacitance voltage profiling of reverse-biased Schottky diodes are popular methods [18, 19], though care must be taken as both techniques can be influenced by the presence of deep levels within the depletion region or interface states that can impact the magnitude of the extracted energy band offset. A variation on the Schottky diode methods that is particularly useful for thin heterostructures of interest in FETs is the MOS capacitance–voltage (C–V ) method, as applied to MOS capacitors or MOSFETs [20–22]. By simulating and fitting the measured gate-to-channel capacitance characteristics of strained Si MOSFETs, Welser was able to extract values for the conduction and valance band offsets, DEc and DEv , for strained Si /relaxed SiGe heterojunctions [21]. These results are illustrated in Figure 2.8.6. As shown in the figure, there is generally good agreement between the magnitude of the extracted band offsets (symbols) and the theoretical calculations (lines). The bandgap of strained Si can be estimated by

∆EC (eV)

0.30

0.20

(a) Measurements by J. Welser

0.10 Calculated People and Bean (APL 48(8),1986) 0.00 0.30

∆EV (eV)

(b)

0.20

0.10

0.00 0.00

Calculated Van de Walle and Martin (PR B 34(8), 1986) 0.10

0.20 Ge fraction (x)

0.30

0.40

FIGURE 2.8.6 Conduction (a) and valence (b) band offsets for strained Si/relaxed SiGe heterojunctions determined by Welser [21]. Solid symbols are experimentally extracted from modeling of C–V characteristics measured for strained Si MOSFETs. The band alignment is as shown in Figure 2.8.3(b). (From J.J. Welser. The application of strained Si /relaxed-Silicon germanium heterostructures to metal-oxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-149

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

combining these data with the measured data for the bandgap of relaxed SiGe from Braunstein, according to Eg(strained Si) ¼ Eg(relaxed SiGe) DEc þ DEv. Figure 2.8.7 illustrates the resulting estimate of the strained Si bandgap as a function of the Ge fraction of the SiGe substrate. The results are in good agreement with the calculations from People and Bean [7]. Note that the error bars in the figure represent the uncertainty in the fitting as opposed to an absolute error. The impact of uncertainties in the strain-induced density of states and quantum corrections on such analysis is discussed in more detail below in the analysis of dual-channel structures. A particularly exciting heterostructure for MOSFET applications is the dual-channel structure [23, 24] shown schematically in Figure 2.8.8. This structure has a top strained Si layer that forms a high-mobility electron channel and a slightly buried, strained high-Ge-content SiGe channel that serves as a high-hole mobility channel. The high Ge content in the buried layer is made possible in part by the relaxed SiGe layer that reduces the overall mismatch. It has been demonstrated that both high electron and hole mobility enhancements can be achieved simultaneously in dual-channel structures [25]. It is critical to know the energy band offsets in such structures in order to predict hole confinement, mobility, and device properties such as threshold voltage and subthreshold slope. The valence band offset, DEv , between the strained Si and strained SiGe layers is particularly important. For the purpose of extracting this energy band offset, p-type heterostructures shown schematically in Figure 2.8.8 have been fabricated [26]. Figure 2.8.9(a) illustrates the energy band diagram for these MOS capacitors at flatband (solid lines) and negative bias (dashed lines). Under increasing negative bias it is clear that holes first accumulate in the buried SiGe well and then at the oxide-strained Si interface. The resulting CV curves of these MOS capacitors are illustrated in Figure 2.8.9(b). The plot is divided into three regions: inversion on the surface oxide–silicon interface (gate voltages greater than zero) with electrons in the strained Si layer, accumulation of holes in the SiGe well, and accumulation of holes at the oxide–silicon interface. The width of the characteristic plateau region is indicative of the valence band offset, DEv , as shown in the figure. This feature is utilized in order to extract the valence band offset. One-dimensional simulations have been performed to fit the experimental data using the Dessis device simulator [27]. Quantum effects are taken into account in the simulation using the density

1.20 1.15

Calculated People and Bean (1986)

Eg (eV)

1.10 1.05 1.00 0.95 0.90 0.00

Relaxed Strained Si Si1−xGex Eg Bandgap of strained Si on relaxed Si1−x Gex 0.10

0.20 Ge fraction (x)

0.30

0.40

FIGURE 2.8.7 The bandgap energy of strained Si on relaxed SiGe as determined by Welser [21], by combining the data in Figure 2.8.6 with the data for the bandgap of relaxed SiGe from Braunstein et al. [2], according to Eg(strained Si) ¼ Eg(relaxed SiGe) DEc þ DEv. (From J.J. Welser. The application of strained Si /relaxed-silicon germanium heterostructures to metal-oxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-150

The Silicon Heterostructure Handbook

TiN gate Gate oxide ~ 4 nm p Si (strained) ~ 7 nm

∆EC

∆EV

p Si1−y Gey (Strained) ~ 12 nm p Si1−x Gex (Relaxed) ~ 500 nm p graded Si1−x Gex p+ Si substrate EV

EC

FIGURE 2.8.8 Schematic illustration of an MOS capacitor formed on a dual-channel heterostructure, and associated energy band diagram. This structure has a top strained Si layer that serves as a high-mobility electron channel and a slightly buried, strained high-Ge-content SiGe layer that serves as an enhanced hole mobility channel. Flatband High bias

(a)

EC EF ∆EV

1

EV

(b)

Normalized capacitance (C/Cox)

COX

100 kHz 300 K TSi

0.8

0.6

C⬘OX ∆EV

0.4

0.2

Accumulation Si−oxide interface

0 −4

−3

Cmin

SiGe well Inversion −2 −1 0 Gate voltage (V)

1

2

FIGURE 2.8.9 (a) Energy band diagram at flatband (solid lines) and negative gate bias (dashed lines), and (b) CV data for a dual-channel MOS capacitor shown schematically in Figure 2.8.8, with y ¼ 0.6 and x ¼ 0.3. The plateau feature in the CV characteristics, observed when holes accumulate in the SiGe well, is related to the magnitude of the valence band offset DEv. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1yGey on relaxed Si1xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-151

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

∆EV −20 meV

4 ⫻10−10

Tox = 4.6 nm TSi = 6.6 nm

Capacitance (F)

Na = 1016 cm−3 Area = 250 µm2 −10

3 ⫻10

∆EV +20 meV

2 ⫻10−10

1 ⫻10−10 −2.5

Measured data Simulation ∆EV = 435 meV Simulation ∆EV = 435 ± 20 meV −2

−1.5 −1 −0.5 Gate voltage (V)

0

0.5

FIGURE 2.8.10 Measured (symbols) and simulated (lines) C–V characteristics for an MOS structure containing strained Si/strained Si0.4Ge0.6 on a relaxed Si0.7Ge0.3 substrate. The dashed lines show simulations for DE v ¼ 435 + 20 meV. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1yGey on relaxed Si1xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

gradient quantum correction model. Figure 2.8.10 compares measured (symbols) and simulated (lines) C–V characteristics for a structure consisting of strained Si /strained Si0.4Ge0.6 on a relaxed Si0.7Ge0.3 substrate. The dashed lines show simulations for DEv ¼ 435 + 20 meV, illustrating that the quality of the fit is very sensitive to small changes in the valence band offset. It has been found that the C–V simulations are sensitive to the values used for the effective valence band density of states Nv in the strained Si. Note that this density of states decreases with increasing strain and Ge content due to the splitting and deformation of the valence bands. Use of the theoretical values for Nv for strained Si produces a much better fit to the C–V data in the portion of the curve corresponding to the population of the strained Si valence bands [26]. Analysis indicates that for this sample, a 15 meV difference in the extracted value of DEv can result from the use of the unstrained values of the density of states in place of the strained values. It is thus important to use a self-consistent parameter set including both Nv and DE v when modeling dual-channel MOSFETs. Figure 2.8.11 illustrates the extracted DE v for strained Si /strained Si1yGey on relaxed Si1xGex heterostructures as a function of the compositions x and y. The valence band offset increases with both composition and strain in the Si1yGey layer. Linear fits to the data yield an average slope of roughly 100 meV/10% Ge in the strained Si1yGey layer. This follows the theoretical trend, which displays a slope of 75 meV/10% Ge.

The Si/Si1yCy System Figure 2.8.3(d) illustrates the band lineup for strained Si1yCy grown on Si, for C compositions less than 2 at.%. Such Si1yCy layers are strained in biaxial tension. The situation is complementary to that of strained SiGe grown on Si, and the Si1yCy /Si band lineup, with a conduction band offset and little valence band offset is ideal for the fabrication of pnp Si /Si1yCy /Si HBTs [28]. Theoretical predictions of conduction band offsets have been reported to accompany the addition of C to Si [29], and there has been some controversy concerning the presence of large conduction band offsets in the SiGeC/Si system [22, 30–32]. The estimated conduction band offset between strained Si1yCy and Si is approximately 65 meV/at.% C. A combination of MOS C–V analysis to extract DEc, similar to that employed above, and

© 2006 by Taylor & Francis Group, LLC

2.8-152

The Silicon Heterostructure Handbook

600

Valence band offset (meV)

500

400

Bulk Si substrate

300

200

0.40 Substrate Ge (x) 100

0.31 0.19

0 0

0.2 0.4 0.6 0.8 Ge Fraction y in strained Si1−yGey Layer

FIGURE 2.8.11 Extracted DE v for strained Si/strained Si1yGey on relaxed Si1xGex heterostructures as determined by fitting MOS CV analysis. Theoretical values for the effective density of states in strained Si and strained Si1yGey were used in the extractions. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1yGey on relaxed Si1xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

temperature-dependent measurements of the collector current in pnp Si /Si1yCy /Si HBTs to extract DEg, indicates that for strained Si1yCy on Si, most of the band offset is in the conduction band [33]. These results are summarized in Figure 2.8.12. Note that when plotted as a function of the magnitude of the lattice mismatch to silicon (upper x-axis in the figure), the magnitude of the bandgap offset per percent mismatch for strained Si1yCy on Si is close to that for strained SiGe on Si.

2.8.4 Introduction to Transport Properties Although minority carrier diffusion in SiGe has been studied for modeling of npn Si /SiGe HBTs [35–37], the greatest excitement exists today for understanding transport in strained Si and strained SiGe layers for high-speed FET applications, including digital CMOS. For the Si conduction band, it has already been mentioned that the biaxial tensile strain-induced splitting of the degeneracies at the D point is beneficial to in-plane electron transport. There is little deformation of the Si conduction band ellipsoids themselves, but energy shifting and repopulation of the valleys in k-space [15]. The resulting enhancement in electron mobility by a factor of 1.8 has been the subject of investigation for CMOS applications [38] as discussed elsewhere in this volume. Although models have been used to explain the measured strain dependence of peak electron mobility enhancements in strained Si /relaxed SiGe n-MOSFETs [12], ab initio calculations have not been able to account for the enhanced electron mobilities in strained Si n-MOSFETs measured at high vertical electric fields [39], and further work aimed at understanding these effects is required. In addition to the shifts in band edge positions, the shape of the energy bands can change under strain and alloying effects. The valence band is considerably more complex than the conduction band, undergoing warping, splitting, and deformation with strain. Reviews of calculations of the valence band structure in strained SiGe can be found in Refs. [40–43]. To first order as the valence bands split the mass of the uppermost band near k ¼ 0 is reduced, and this is associated with an enhanced in-plane hole mobility in biaxial tensile-strained Si on relaxed SiGe [44]. Recent three-dimensional calculations

© 2006 by Taylor & Francis Group, LLC

2.8-153

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

Magnitude lattice mismatch to Si (%) 0

0.2

0.4

0.6

0.8

0

Band offset (meV)

Fit to HBT data ∆Eg (Si0.9Ge0.1)

−40

Fit to MOS-CV data

−80

∆Ec : MOS CV(Ref. 22) ∆Ec : MOS CV(Ref. 34) ∆Eg : HBT's (No BGN correction) ∆Eg : HBT's (BGN correction)

−120

0

0.5

1 1.5 Substitutional C (at.%)

2

FIGURE 2.8.12 Summary of band offsets for strained Si1yCy on Si heterojunctions. The solid line is a fit to the DEg values extracted from pnp HBTs. (From D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Novel epitaxial p-Si /n-Si1yCy / p-Si heterojunction bipolar transistors. Technical Digest of International Electron Devices Meeting 2000, pp. 749– 752. With permission.) The dashed line is a fit to the DEc values extracted from MOS CV analysis. The estimated conduction band offset between strained Si1yCy and Si is approximately 65 meV/at.% C. The bandgap offset DEg for Si0.9Ge0.1/Si (mismatch ¼ 0.4%) is shown (6) for reference. (From D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Effect of band alignment and density of states on the collector current in p-Si /n-Si1yCy /p-Si HBTs. IEEE Trans. Elec. Dev. 50:425–432, 2003. With permission.)

of the Si band structure under ‘‘uniaxial’’ compressive stress indicate a complex behavior that enhances the hole mobility for transport in the direction of compression [45]. The addition of Ge to SiGe leads to a more Ge-like valence band with a higher curvature and reduced effective mass, as well as to strainenhanced mobilities for pseudomorphic growth. Hole mobilities increase dramatically for strained SiGe with Ge contents above 50%. The highest mobilities in the silicon heterostructure system have been obtained for high-Ge-content strained Si1yGey or strained Ge grown on relaxed Si1xGex layers with y > x [46].

2.8.5 Summary There has been considerable progress in the understanding of the band structure and basic electronic properties of silicon heterostructures over the years. Strain plays a critical role in determining the energy band structure and the lineup of the bands at strained SiGe/Si and strained Si /SiGe heterojunctions. Research continues in this area as interest in the use of strained Si and SiGe in FET applications grows. More experimental and theoretical work is needed to formulate an accurate picture of transport in strained Si and strained SiGe heterostructures, particularly in inversion layers where electric field quantization is also important, and this is currently an exciting area of investigation.

Acknowledgments I am indebted to a number of talented people with whom I have worked in the area of silicon heterostructures, and whose efforts are represented in this chapter. In particular I would like to thank past collaborators including James Gibbons, Clifford King, Jeff Welser, Kern Rim, Shinichi Takagi, and Dinkar Singh, as well as present collaborators, especially Cait Ni Chleirigh, Oluwamuyiwa Olubuyide, Dimitri Antoniadis, and Eugene Fitzgerald.

© 2006 by Taylor & Francis Group, LLC

2.8-154

The Silicon Heterostructure Handbook

References 1. R.W. Olesinski and G.J. Abbaschian. Bull. Alloy Phase Diagrams 5:180, 1984. 2. R. Braunstein, A.R. Moore, and F. Herman. Intrinsic optical absorption in germanium–silicon alloys. Phys. Rev. 109:695–710, 1958. 3. D.V. Lang, R. People, J.C. Bean, and A.M. Sergent. Measurement of the band gap of Si1xGex /Si strained-layer heterostructures. Appl. Phys. Lett. 47:1333–1335, 1985. 4. C.A. King, J.L. Hoyt, and J.F. Gibbons. Bandgap and transport properties of Si1xGex by analysis of nearly ideal Si/Si1xGex /Si heterojunction bipolar transistors. IEEE Trans. Elec. Dev. 36:2093–2104, 1989. 5. R. People. Indirect band gap of coherently strained GexSi1x bulk alloys on (0 0 1) silicon substrates. Phys. Rev. B 32:1405–1408, 1985. 6. J.F. Morar, P.E. Batson, and J. Tersoff. Heterojunction band lineups in Si–Ge alloys using spatially resolved electron-energy-loss spectroscopy. Phys. Rev. B 47:4107–4110, 1993. 7. R. People and J.C. Bean. Band alignments of coherently strained GexSi1x /Si heterostructures on (0 0 1) Gey Si1y substrates. Appl. Phys. Lett. 48:538–540, 1986. 8. C. Herring and E. Vogt. Phys. Rev. 101:944, 1956. 9. I. Balslev. Phys. Rev. 143:636, 1966. 10. J.L. Hoyt. Substitutional carbon incorporation and electronic characterization of Si1yCy /Si and SiGeC/Si heterojunctions, in Silicon–Germanium Carbon Alloys: Growth, Properties and Applications, Taylor and Francis, New York, 2002, pp. 59–89. 11. T. Vogelsang and K.R. Hofmann. Electron transport in strained Si layers on Si1xGex substrates. Appl. Phys. Lett. 63:185–187, 1993. 12. S. Takagi, J.L. Hoyt, J. Welser, and J.F. Gibbons. Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 80:1567–1577, 1996. 13. G.G. Van de Walle and R.M. Martin. Theoretical calculations of heterojunction discontinuities in the Si /Ge system. Phys. Rev. B 34:5621–5634, 1986. 14. R. People. Physics and applications of Gex Si1x /Si strained layer heterostructures. IEEE J. Quantum Electronics 22:1696–1710, 1986. 15. M.M. Rieger and P. Vogl, Electronic-band parameters in strained Si1xGex alloys on Si1yGey substrates. Phys. Rev. B 48:14276–14287, 1993. 16. F. Schaffler, High-mobility Si and Ge structures. Semicond. Sci. Technol. 12:1515–1549, 1997. 17. M.L.W. Thewalt, D.A. Harrison, C.F. Reinhart, J.A. Wolk, and H. Lafontaine. Type II band alignment in Si1xGex /Si(0 0 1) quantum wells: the ubiquitous type I luminescence results from band bending. Phys. Rev. Lett. 79:269–272, 1997. 18. R.E. Cavicchi, D.V. Lang, D. Gershoni, A.M. Sergent, J.M. Vandenberg, S.N.G. Chu, and M.B. Panish. Admittance spectroscopy measurement of band offsets in strained layers of InxGa1x As grown on InP. Appl. Phys. Lett. 54:739–741, 1989. 19. H. Kroemer, W.-Y. Chen, J.S. Harris Jr. and D.D. Edwall. Measurement of isotype heterojunction barriers by C–V profiling. Appl. Phys. Lett. 36:295–297, 1979. 20. S.P. Voinigescu, K. Iniewski, R. Lisak, C.A.T. Salama, J.P. Noel, and D.C. Houghton. New technique for characterization of Si /SiGe layers using heterostructure MOS capacitors. Solid-State Electron. 37:1491, 1994. 21. J.J. Welser. The application of strained Si /relaxed-silicon germanium heterostructures to metaloxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. 22. D.V. Singh, K. Rim, T.O. Mitchell, J.L. Hoyt, and J.F. Gibbons. Measurement of the conduction band offsets in Si /Si1xyGexCy and Si /Si1yCy heterostructures using metal-oxide-semiconductor capacitors. J. Appl. Phys. 85:978–984, 1999. 23. C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Hole mobility enhancements in strained Si /Si1yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1xGex (x < y). Appl. Phys. Lett. 79:4246–4248, 2001.

© 2006 by Taylor & Francis Group, LLC

Electronic Properties of Strained Si/SiGe and Si1yCy Alloys

2.8-155

24. C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Channel engineering of SiGe-based heterostructures for high mobility MOSFETs, in Materials Issues in Novel Si-Based Technology. Symposium (Materials Research Society Symposium Proceedings) Vol. 686:113–118, 2002. 25. J. Jung, M.L. Lee, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis. Implementation of both high-hole and electron mobility in strained Si /strained Si1yGey on relaxed Si1xGex / (x < y). IEEE Electron Dev. Lett. 24:460–462, 2003. 26. C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1yGey on relaxed Si1xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004 –7, pp. 99–109, 2004. Pennington, N.J. 27. Dessis: Comprehensive semiconductor device simulator, Integrated Systems Engineering AG, Switzerland, http://www/ise.com. 28. D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Novel epitaxial p-Si /n-Si1yCy /p-Si heterojunction bipolar transistors. Technical Digest of International Electron Devices Meeting 2000, pp. 749–752. 29. A.A. Demkov and O.F. Sankey. Theoretical investigation of random Si–C alloys. Phys. Rev. B 48: 2207–2214, 1993. 30. B.L. Stein, E.T. Yu, E.T. Croke, A.T. Hunger, B. Laursen, A.E. Bair, J.W. Mayer, and C.C. Ahn. Band offsets in Si /Si1xyGexCy heterojunctions measured by admittance spectroscopy. Appl. Phys. Lett. 70:3413–3415, 1997. 31. B.L. Stein, E.T. Yu, E.T. Croke, A.T. Hunger, B. Laursen, A.E. Bair, J.W. Mayer, and C.C. Ahn. Measurement of band offsets in Si /Si1xGex and Si /Si1xyGexCy heterojunctions. J. Vac. Sci. Technol. B15:1108–1111, 1997. 32. D.V. Singh, K. Rim, T.O. Mitchell, J.L. Hoyt, and J.F. Gibbons. Admittance spectroscopy analysis of the conduction band offsets in Si /Si1xyGexCy and Si /Si1yCy heterostructures. J. Appl. Phys. 85:985–993, 1999. 33. D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Effect of band alignment and density of states on the collector current in p-Si /n-Si1yCy /p-Si HBTs. IEEE Trans. Elec. Dev. 50:425–432, 2003. 34. K. Rim, T.O. Mitchell, D.V. Singh, J.L. Hoyt, J.F. Gibbons, and G. Fountain. Metal-oxide semiconductor-capacitance–voltage characteristics and band offsets for Si /Si1yCy/Si heterostructures. Appl. Phys. Lett. 72: 2286–2288, 1998. 35. J. Poortmans, M. Caymax, A. Van Ammel, M. Libezny, and J. Nijs. Study of the transversal electron mobility in heterojunction bipolar transistors with strained Si1xGex-base. Semiconductor Heterostructures for Photonic and Electronic Applications Symposium, 1993, pp. 409–414. 36. A. Gruhle, A. Schuppen, H. Kibbel, and U. Konig. Minority carrier mobility and density of states in SiGe HBTs determined by a new method. Compound Semiconductors 1994. Proceedings of the Twenty-First International Symposium, 1995, pp. 253–258. 37. T. Ghani. Characterization of Minority Carrier Transport and Heavy Doping Effects in n-Si /p-SiGe/ n-Si Heterojunction Bipolar Transistors, Ph.D. Thesis, Stanford University, 1994. 38. J.L. Hoyt, H.M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E.A. Fitzgerald, and D.A. Antoniadis. Strained Silicon MOSFET Technology. Tech. Digest IEEE International Electron Devices Meeting, Dec. 2002, pp. 23–26, and references therein. 39. M.V. Fischetti, F. Gamiz, and W. Hansch. On the enhanced electron mobility in strained-silicon inversion layers. J. Appl. Phys. 92:7320–7324, 2002. 40. J.M. Hinckley and J. Singh. Hole transport theory in pseudomorphic SiGe alloys grown on Si(001) substrates. Phys. Rev. B 41:2912–2926, 1990. 41. M.V. Fischetti and S.E. Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys. 80:2234–2252, 1996. 42. T. Manku and A. Nathan, Energy-band structure for strained p-type SiGe. Phys. Rev. B 43: 12634– 12637, 1991.

© 2006 by Taylor & Francis Group, LLC

2.8-156

The Silicon Heterostructure Handbook

43. T. Manku and A. Nathan. Valence energy-band structure for strained group-IV semiconductors. J. Appl. Phys. 73:1205–1213, 1993. 44. D.K. Nayak and S.K. Chun. Low-field hole mobility of strained Si on (001) SiGe substrate. Appl. Phys. Lett. 64:2514–2516, 1994. 45. M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, and K. Zawadzki. Understanding Stress Enhanced Performance in Intel 90 nm CMOS Technology, Proceedings of IEEE Symposium on VLSI Technology, 2004, pp. 118–119. 46. M.L. Lee and E.A. Fitzgerald. Optimized strained Si /strained Ge dual-channel heterostructures for high mobility p- and n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting 2003, pp. 433–436.

© 2006 by Taylor & Francis Group, LLC

2.9 Carbon Doping of SiGe

H. Jo¨rg Osten University of Hanover

2.9.1 Introduction............................................................ 2.9-157 2.9.2 Basic Considerations .............................................. 2.9-157 2.9.3 Growth of C-Containing Alloys ............................ 2.9-158 2.9.4 Control of Dopant Diffusion by Adding Carbon ....................................................... 2.9-160 2.9.5 Strain Manipulation in Si1xyGexCy Layers ....... 2.9-162 2.9.6 Microscopic Structure of SiGeC Layers................ 2.9-163 2.9.7 Strain-Stabilized Layers with High C Concentration ......................................................... 2.9-163 2.9.8 Thermal Stability .................................................... 2.9-164 2.9.9 Impact of Carbon on Electrical Layer Properties ................................................................ 2.9-164 2.9.10 Summary ................................................................. 2.9-165

2.9.1 Introduction Silicon is the most important semiconductor material in the microelectronic industry. There have been several attempts to increase the material variety that is compatible with Si technologies. Silicon– germanium alloys and heterojunctions will extend the performance of future Si-based devices. However, the Si1xGex on Si(0 0 1) system exhibits severe limitations. Examples include the existence of a critical thickness for perfect pseudomorphic growth, which depends on the amount of germanium (the introduced strain). In addition, the main band offset between Si and strained SiGe is located in the valence band, that is, this system is much better suited for hole channel than for electron channel devices. Recently, it was shown that Si1yCy and Si1xyGexCy layers can also be grown pseudomorphically on Si(0 0 1). This new material might alleviate some of the limitations of SiGe on Si(0 0 1). Research on highly supersaturated, C-containing alloys on silicon substrates started only a few years ago. Meanwhile, knowledge has been accumulated on growth, strain manipulation, thermal stability, and carbon effects on band structure and charge carrier transport [1–3]. Low carbon concentrations can also be used to control diffusion of dopants without affecting strain and band alignment. This unique property has already found its first device application, the SiGe:C heterojunction bipolar transistor (HBT) [4].

2.9.2 Basic Considerations Epitaxial growth of C-containing Si1yCy or Si1xyGexCy alloys is more complex than SiGe growth. Several additional problems have to be addressed [5, 6]: Unlike to the Si /Ge system, silicon and carbon are not miscible. According to the binary Si C phase diagram, stoichiometric SiC (silicon carbide) is 2.9-157 © 2006 by Taylor & Francis Group, LLC

2.9-158

The Silicon Heterostructure Handbook

the only stable compound. Any alloy with a smaller C concentration is thermodynamically metastable. Such alloy layers can be achieved by kinetically dominated growth methods, like molecular beam epitaxy (MBE) [5, 6], various kinds of chemical vapor deposition (CVD) at relatively low temperatures [7], or solid-phase epitaxy (SPE). The SPE approach is based on recrystallization of amorphous mixtures of Si / Ge /C obtained mainly by ion implantation with well-defined temperature profiles [8, 9]. All of these methods generally work under far from thermodynamic equilibrium conditions, allowing a kinetic stabilization of metastable phases. Although the bulk solubility of carbon in silicon is small (3 1017 atoms/cm3 at the melting point of Si [10]), epitaxial layers with more than 1% C can be fabricated. Once deposited as a random alloy at low temperatures (500–7008C), the Si1yCy appears to be able to withstand anneals up to significantly higher temperatures (up to 9008C) [11, 12]. Contrary to the Si /Ge alloy, carbon in silicon can easily form interstitial defect complexes. Thus, one of the most crucial questions is the relationship between substitutional and interstitial carbon incorporation, which has a large impact on the electrical properties of these layers. Substitutionally incorporated C atoms allow strain manipulation, including the growth of strain-compensated or inversely C system is the extreme mismatch of the strained Si1xyGexCy layers. The striking feature of the Si Si Si and Si C bond lengths. Disordered alloys will exhibit large local strain. Local ordering will occur due to atomic size differences.

2.9.3 Growth of C-Containing Alloys Any alloy with a substitutional C concentration above the bulk solubility limit is thermodynamically metastable. In equilibrium, the solid solubility of a substitutional C impurity (i.e., the value of y for Si1yCy) is given by: y ¼ exp[(E m)/kT ], where E is the energy of a substitutional C atom in Si, m the chemical potential, and k the Boltzmann constant. The concentration of C is limited by the formation of SiC precipitates, which prevents m from rising higher than the value corresponding to a SiC reservoir [13]. However, during growth it is not the equilibrium bulk solubility that is important but rather a ‘‘surface solubility.’’ The increased solubility results from two factors [13]: First, the presence of a surface breaks the bulk symmetry and therefore creates sites for adatoms that are energetically nonequivalent to bulk sites. The stress associated with the atomic size mismatch between C and Si is partially relieved and the energy of the substitutional C decreases smoothly as it approaches the surface. Second, there is a stress field near the surface, associated with the atomic reconstruction there [14]. The coupling of the carbon stress to this spatially varying surface stress substantially lowers the carbon energy on certain sites. For a (21) reconstructed Si(0 0 1) surface there are two nonequivalent sites: One lies beneath the surface dimer (a site), and the other site lies between the dimers (b site). As discussed by Kelires and Tersoff [14], the a sites are under compressive stress. Thus, they are favorable sites for a smaller atom such as C. The adatoms are rapidly buried on subsurface sites, which serve like a sink, and thus immobilized. The high carbon density near the surface is frozen in as the crystal grows, permitting the growth of a highly supersaturated solid-solution, e.g., high carbon concentrations in silicon or silicon–germanium. Tersoff used an empirical many-body potential to model the interaction between atoms in the Si1yCy system [13]. Including also the surface reconstruction, he found an enhancement of 104 over equilibrium bulk solubility. Thus, the surface solubility of carbon can easily be in the percentage range. The lowest-energy position of carbon in Si is found to be the substitutional site. In addition, the observed activation energy for the diffusion of substitutional carbon (3 eV) is quite large [7]. This is the origin for the achieved stability of these metastable alloys. Carbon precipitation is a rare process that has been reported to occur only in the presence of a supersaturation of silicon self-interstitials or oxygen [15]. The mechanism described here has another possible consequence, in addition to enhanced solubility. If the C atoms have sufficient mobility within the first layers, they will lie only on sites beneath the dimers, with negligible occupancy of the other sites. This ordering should not be lost as the layers are buried deeper, if the C is immobile in deeper layers. First indications of local ordering in Si1yCy layers have been observed [16, 17].

© 2006 by Taylor & Francis Group, LLC

2.9-159

Carbon Doping of SiGe

Substrate C concentration

The carbon substitutionality (nS /n0) is strongly influenced by the growth conditions, such as temperature and the Si growth rate. Similar trends were observed for MBE and CVD growth [18–21]. All authors found a significant decrease of the substitutional carbon concentration with increasing growth temperature or decreasing growth rate. Osten et al. [18] proposed the following simple model: If the temperature is high enough for Si epitaxy, one can assume that all arriving C adatoms are rapidly incorporated in positions beneath the Si dimers. When another Si adatom arrives above a surface position filled with a C atom, either (i) it migrates further on the surface, or (ii) it binds to the carbon (‘‘freezing in’’ of the C atom on lattice position), or (iii) it kicks the C atom out of a lattice position, forming a SiC interstitial complex or a C C dimer on the surface. The substitutional versus interstitial carbon concentration is therefore primarily controlled by process (iii), i.e., by all parameters affecting the formation of the interstitial defect complexes [22]. Desorption processes are likely excluded for the used growth temperatures. Recently, Kelires and Kaxiras [23] reported atomistic calculations of the surface structure of Si with substitutional carbon atoms. One of their important results is that the lowest energy configuration involves the C atoms in the very top layer of the Si(0 0 1) surface, forming dimers in the (2 1) reconstruction. The authors suggest that the strong preference of C to remain on the surface is due to the bond between the two threefold coordinated C atoms (similar to the Si surface atoms forming dimers). The ability of C to form double bonds makes this a low-energy structure. This has important consequences. It implies that if C atoms have a chance to form C C dimers upon arrival on the Si(0 0 1) surface, their subsequent incorporation in the growing film will be limited. The formation of such dimers depends on several factors, including the frequency of surface hops (i.e., the growth temperature), the time before further deposition immobilizes the atoms (i.e., the growth rate), and the probability of finding another C atom (i.e., the total carbon concentration). In addition, some carbon evaporation sources deliver larger C fragments. Therefore, we have to assume different incorporation kinetics for different C sources. Osten et al. [22] extended their model for the incorporation of substitutional C during epitaxial growth as a function of various parameters. Based on that model one should expect for a certain Si growth rate and C flux the behavior illustrated schematically in Figure 2.9.1. Generally, we can distinguish three different regions (labeled A to C in Figure 2.9.1). In the first region, we have complete substitutional incorporation, independent of the growth temperature. For the highest temperatures in this region, we might find a slight decrease in the substitutional carbon concentration (ns) with increasing temperature. This behavior is similar to the one reported by Zerlauth et al. [20]. In the middle region (B), we observe a relatively strong decrease of ns with increasing growth temperature, similar to the results reported in Refs. [18, 19]. For even higher growth temperatures (region C), almost no substitutional carbon incorporation should be possible. If the substrate temperature is too high, a metastable regime no longer exists, and some deterioration in crystal quality (like a transition to 3D growth or a mixed alloy carbide phase) occurs. The observed behavior can be described using the growth rate r (limiting the time available for defect formation), the total carbon concentration

A

B

C

Temperature

FIGURE 2.9.1 Schematic representation of substitutional carbon incorporation in Si1yCy layers as a function of growth temperature for given and constant Si and C fluxes. Three distinct regions are marked.

© 2006 by Taylor & Francis Group, LLC

2.9-160

The Silicon Heterostructure Handbook

n0, the growth temperature T, and an energy barrier Ec. Any incorporated C atom has to overcome this barrier to form an interstitial C-containing defect complex. The frequency of defect formation k is given by: k ¼ k0 exp(Ec /kT ). Based on all available data it seems reasonable to postulate that the energy barrier is lowered by the presence of surface strain, that is, Ec decreases with increasing n0. This behavior can be modeled by a first-order exponential decay, leading to a value of Ec for n0 approaching zero which is close to the barrier obtained for the diffusion of substitutional carbon in bulk silicon with very low carbon concentrations [7]. For the low carbon concentrations used to control dopant diffusion, the energy barrier is still large enough to suppress any defect formation within the temperature window for epitaxial growth. Thus, low carbon concentrations will be predominantly incorporated substitutionally. The preexponential frequency factor k0 decreases over several orders of magnitude with increasing n0. This factor mainly describes the ability of adatoms to migrate on the surface. Thus, the presence of carbon on the surface appears to reduce surface diffusion significantly. Extrapolating to n0 ¼ 0, k 0(0) is in the same order of magnitude typically assumed for surface migration of adatoms on an unperturbed Si surface. There is another interesting consequence arising from the decrease of Ec and k0 with increasing C concentration, namely that the fraction of substitutionally incorporated carbon atoms decreases with increasing n0. This leads to a saturation limit, i.e., any further increase in the carbon flux leads mainly to an increase in the number of interstitial defects, with the amount of substitutionally incorporated carbon remaining constant [22]. This behavior supports the often postulated existence of a limit for substitutional carbon incorporation [1]. This limit depends, of course, on the specific growth conditions and the specific carbon source. So far, we discussed the incorporation of C into silicon. Liu and Osten [24] extended the investigations to substitutional C incorporation during MBE growth of Si1xyGexCy alloys. The strain introduced by the incorporation of C and Ge makes these processes even more complicated. They showed that the substitutional C incorporation can be dominated by the Ge or C concentration, depending on the total C concentration range. At low total C concentration, the Ge impact is insignificant; increasing total C concentration leads to less substitutional C incorporation efficiency. At high n0, the impact of C concentration becomes marginal, and the presence of Ge inhibits the substitutional C incorporation. The very low substitutional C incorporation during Ge1yCy growth even at an extremely low growth temperature of 2008C (reported recently in Ref. [25]) is consistent with this prediction.

2.9.4 Control of Dopant Diffusion by Adding Carbon The amount of carbon discussed in this chapter is in the order of dopant concentrations. To distinguish these materials from the Si1yCy or Si1xyGexCy systems discussed so far, we will use the same notation as for dopants, that is Si:C or SiGe:C. The carbon concentration is too low to affect significantly band alignment and strain of the epitaxially grown Si:C or SiGe:C layers. However, the used carbon concentration in the range of 1020 cm3 is still orders of magnitude higher than the solid solubility limit, i.e., we have to consider metastable systems with carbon supersaturation. A major challenge for the fabrication of ultrasmall devices for next silicon technology generations is the control of steep dopant profiles. In this context, it is tempting to apply supersaturated carbon as a diffusion-controlling agent in silicon. The fundamental question for applications of C-rich Si in devices is whether electronic device parameters are affected by possible C-related defects. Recently, Gossmann et al. [26] have announced the realization of MOSFET with reduced reverse short-channel effect due to suppressed transient diffusion in C-rich silicon. Little increase in leakage current was reported for devices with carbon. Successful applications of C-rich layers were reported for SiGe HBT [27, 28]. The IHP group has demonstrated that transistors with excellent static and dynamic parameters can be fabricated with epitaxial SiGe:C layers [29, 30]. The main result of this investigation was that carbon supersaturation can preserve steep boron doping profiles without degrading fundamental transistor parameters. The diffusion coefficient of B in Si is reduced by more than one order of magnitude when the concentration of substitutional C is elevated to about 1020 cm3 [31]. Furthermore, transientenhanced diffusion (TED) of B is strongly suppressed in C-rich Si [32].

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-161

In the following, we will describe the physical mechanism for suppressed boron diffusion in C-rich Si and SiGe (below 0.2% carbon) based on an undersaturation of Si self-interstitials [31, 33, 34]. Diffusion of dopants as well as Si self-diffusion, and diffusion of Ge and C in Si are mediated by point defects, i.e., vacancies and self-interstitials. It is generally accepted that both vacancy and interstitial mechanisms contribute to atomic transport in Si while the direct exchange mechanism of nearest-neighbor atoms plays a negligible role. The effect of C on B diffusion can be explained by coupled diffusion of B and point defects in Si. Diffusion of C out of C-rich regions causes an undersaturation of Si self-interstitials in the C-rich region, which in turn results in suppressed diffusion of boron. Pronounced non-Fickian diffusion behavior was found experimentally for buried carbon with concentrations well above its solid solubility [34]. The basic mechanism for nonequilibrium point defect densities due to C outdiffusion is as follows [1, 31]. Depending on growth conditions, carbon can be mainly substitutionally dissolved in Si. Diffusion of C in Si is via a substitutional–interstitial mechanism. Immobile substitutional carbon atoms (Cs) are transformed into mobile interstitial carbon (Ci) through the kick-out reaction with Si self-interstitials (I ): Cs þ I $ Ci. In addition, interstitial C can be formed in the dissociative Frank–Turnbull reaction, Cs $ Ci þ V, where V is a vacancy. In order to conserve the total number of atoms the flux of interstitial C atoms out of the C-rich region has to be balanced by a flux of Si self-interstitials into this region or a flux of vacancies outwards. The individual fluxes are determined by the products of the diffusion coefficient D and the concentration C, which are all known. For C concentrations CC > 1018 cm3, the transport coefficient of C may exceed the corresponding transport coefficients of Si self-interstitials and vacancies: DCCC > DICIeq and DCCC > DVCVeq, where CIeq and CVeq are the equilibrium concentrations of Si self-interstitials and vacancies, respectively. Consequently, outdiffusion of supersaturated C from C-rich regions becomes limited by the compensating fluxes of Si point defects, which leads to an undersaturation of self-interstitials and a supersaturation of vacancies in the C-rich region. In Figure 2.9.2 measured C profiles in Si are compared with model calculation [34]. A 50-nm thick box-shaped C profile was grown using MBE and annealed in pure nitrogen atmosphere. Diffusionlimited rates were assumed for the two reactions described above and for Frenkel-pair generation. For the kick-out reaction, local equilibrium is established for typical point defect parameters. In contrast, the concentration of vacancies in the C-rich region is sensitive to the rate of the Frank–Turnbull reaction. Ru¨cker et al. [34] fitted only the reaction rate to the measured diffusion profile of C. From this simulation, he found also a significant vacancy supersaturation. The point defect distribution after annealing resulting from the calculation is also shown in Figure 2.9.2. In the C-rich region, there is a significant reduction in the interstitial density accompanied by an increase in the vacancy density. This has consequences for all dopants diffusing via point defects. Boron diffusion in Si is via an interstitial mechanism. The effective diffusion coefficient of B is proportional to the normalized concentration of self-interstitials. Accordingly, interstitial undersaturation results in suppressed diffusion of B. Also the diffusion of phosphorous will be strongly reduced. On the contrary, the diffusion of dopants, which are diffusing by a vacancy mechanism (like As or Sb), will be enhanced due to carbon incorporation [34]. TED during the first annealing step after ion implantation accounts for a substantial fraction of dopant redistribution during device processing. The source of TED is an enhanced density of Si selfinterstitials. In a subsequent publication, Ru¨cker et al. [35] have extended this physical model to TED, i.e., nonequilibrium distribution of Si self-interstitials. The authors could show that the same mechanism holds also for TED. The effect of C on diffusion of donors and acceptors can correctly be described by a physically based model for coupled diffusion of C and Si point defects. In the simulation, they have used the ‘‘þ1’’ model for implantation damage and coupled diffusion of C and Si point defects. Reduced diffusion of B in SiGe and the effect of the electric field due to hole confinement in SiGe were also included. The simulation reveals the strong suppression of TED in the C-containing structure. Again, the density of excess interstitials is reduced in the SiGe:C layer due to C outdiffusion. The quality of epitaxial layers for electronic device application can also be evaluated by studying the carrier generation lifetime in MOS-like structures [36]. For LPCVD grown SiGe:C layer stacks similar to that used for HBT application lifetimes above 1 ms were measured, i.e., values that are sufficient for

© 2006 by Taylor & Francis Group, LLC

2.9-162

1019

Carbon (cm−3)

The Silicon Heterostructure Handbook

Annealed

1018 as-grown Simulated

Norm. point defect conc.

10 Vacancies 1

0.1 Interstitials 0.0

0.2

0.4 0.6 Depth (µm)

0.8

1.0

FIGURE 2.9.2 Diffusion profiles of buried carbon layers annealed in nitrogen atmosphere (9008C/45 min). SIMS profiles of as-grown ( ) and annealed ( ) samples are shown in the upper panel together with results of model calculation. The corresponding normalized point defect densities are shown in the lower panel.

successful application of those layers in high-performance devices with low noise. Recently, Heinemann et al. [37] could show that the electron mobility in the p-type base of npn bipolar transistors is not reduced by the incorporation of low C concentrations. They reported about a comparative analysis of vertical minority carrier transport in experimentally realized HBTs with Si, Si1xGex (x ¼ 7.5%), and Si1yCy (y ¼ 0.2% or 1%) base layers. To overcome drawbacks of the simple transit time analysis, they used 2D device simulations to obtain an improved understanding of the measured high-frequency parameters. Taking into account the real doping profiles and device structures, and using a calibrated parameter set for strained SiGe, the simulation results for the Si, Si1xGex, and Si1yCy (y ¼ 0.2%) base layer transistors reproduce very well the measured transit times (assuming the Si data for the electron mobility) in the heteroepiaxial base layers. In the case of higher carbon concentration (y ¼ 1%), the electron mobility is reduced by a factor of two.

2.9.5 Strain Manipulation in Si1xyGexCy Layers Adding a constituent with a covalent radius much smaller than that of silicon to a layer containing the larger Ge (rSi ¼ 1.17 A˚, rGe ¼ 1.22 A˚, but rC ¼ 0.77 A˚) opens the possibility to manipulate the strain. It was shown that it is possible to form an ‘‘inversely distorted’’ SiGe cell, i.e., a cell that is tetragonally distorted due to tensile stress instead of the usual compressive stress by adding some carbon [16]. Using simple linear extrapolations between the different lattice constants and the appropriate relative concentration (Vegard’s law for a ternary system), we can estimate the effective lattice constant in the Si1xyGexCy system as a(x,y) ¼ (1xy)aSiþxaGeþyaC. The linear approximation (between Si, Ge, and diamond) for the average lattice constants results in a Ge:C ratio of 8.2 for complete strain compensation. Ab initio calculations predict values larger than 10 (see for example Ref. [38]). Diamond seems not to be the best choice for interpolating lattice parameter in Si1xyGexCy . Osten et al. [16] proposed a linear interpolation between the lattice constants of Si, Ge, and b-SiC: aSiGeC ¼ (1x2y)aSiþxaGeþ2yaSiC, which is illustrated in Figure 2.9.3. This approach yields that the

© 2006 by Taylor & Francis Group, LLC

2.9-163

Compressive

Carbon Doping of SiGe

Lattice mismatch

40 % Ge 30 % Ge 20 % Ge

Tensile

10 % Ge 0 % Ge 0

1 2 C concentration (%)

3

FIGURE 2.9.3 Estimated strain reduction in SiGe layers due to the presence of carbon (ternary Vegard’s law).

compressing strain of 9.4 % Ge can be fully compensated by 1% C, i.e., strain compensation occurs for a Ge:C ratio of 9.4. Kelires [39] has calculated the lattice constant of Si1yCy . He predicted some small bowing effects, which were also found experimentally by Berti et al. [40]. We define an ‘‘effective lattice mismatch’’ as mfeff ¼ [a(x,y) aSi]/aSi. This quantity is directly accessible by x-ray diffraction. A positive mfeff stands for a compressively strained material, mfeff <0 indicates tensile strain, and mfeff ¼ 0 represents a fully strain-compensated Si1xyGexCy alloy. Such a layer should have on an average scale the cubic silicon structure.

2.9.6 Microscopic Structure of SiGeC Layers The microscopic structure of a fully strain-compensated Si1xyGexCy layer has been investigated in detail in Ref. [41]. The Si C bonds are stretched by about 7% with respect to the bond length in cubic silicon carbide, whereas the C atoms mainly strain the Si Si bond in their neighborhood, with more distant Si Si bonds less affected. Although the average lattice constant of the strain-compensated Si1xyGexCy layer is the same as that of pure silicon, the alloy contains large internal (microscopic) strain. Calculations support the picture of only partial relaxation of the SiSi and Ge Ge bonds towards a common bond length. The Si C and Si Ge bonds in strain-compensated Si1xyGexCy are strongly stretched. The calculated 7% stretching of the Si C in strain-compensated Si1xyGexCy corresponds to 35% relaxation towards the average bond length of the alloy (predicted by Vegard’s law). The observed dependence of Raman spectra on local strain and composition of Si1xyGexCy layers can be explained by the model calculations [41].

2.9.7 Strain-Stabilized Layers with High C Concentration By combining theoretical and experimental results for local Si C phonon modes in dilute Si1yCy alloys, information concerning the short-range order was obtained [42]. Calculations using an anharmonic Keating model predict satellite peaks near the vibrational frequency of an isolated C impurity, associated with second-, third-, etc., nearest-neighbor C C pairs. By comparing theoretical spectra with those obtained by Raman and infrared absorption spectroscopies, it was concluded that the probability for a third-nearest-neighbor coordination of the C atoms is considerably above that for a purely random alloy. Maximizing the number of third-nearest neighbors leads to a Si1yCy system with y 20%. Recently, Ru¨cker et al. [43] investigated the possible existence of such highly concentrated Si1yCy layers embedded in silicon. They demonstrated that Si1yCy layers with y 20% can be grown pseudomorphically on a Si(0 0 1) substrate despite the large difference of the C and Si lattice constants. Such structures could only exist due to strain stabilization. It has been observed previously that semiconductor structures, which are not found in the bulk phase diagram, can be stabilized by the

© 2006 by Taylor & Francis Group, LLC

2.9-164

The Silicon Heterostructure Handbook

substrate-imposed strain in pseudomorphic epitaxial growth. The energy Eepi of an epitaxially confined structure can be decomposed as Eepi ¼ Eequib þ Estrain, where Eequib is the energy at the unconstrained equilibrium lattice constant and Estrain is the work needed to strain the material to match the Si substrate. An epitaxially stabilized structure X occurs when Eepi(X) lies below that of the most stable bulk phase X0 [here, Eepi(b-SiC)]. Detailed structural investigations of such strain-stabilized Si1yCy layers with y 20 % were presented by Ruvimov et al. [44].

2.9.8 Thermal Stability Si1xGex alloys cannot be grown epitaxially on Si or Ge substrates without introducing large amounts of strain. Strain-relief occurs usually by plastic flow, i.e., by injection and propagation of misfit dislocations (see Chapter 2.7). Si1xGex alloys can be grown to much larger thickness than predicted by mechanical equilibrium theory. These layers become metastable. A later temperature treatment, as typical for further Si technological steps, causes also the strain-relieving formation of extended misfit dislocations. Therefore, the inherent strain limits the compatibility of heteroepitaxial SiGe systems to common Si technologies due to its lower thermal stability. In addition, the formation of extended misfit dislocations always changes the in-plane lattice constant (loss of pseudomorphy), enabling the construction of virtual substrates with a lattice constant differing from silicon. The temperature stability of tensile-strained Si1yCy layers was investigated during and after postgrowth annealing [11, 12, 45–47]. Despite the tensile strain in a 100-nm thick layer and the high carbon supersaturation, the samples were stable up to 8508C [12]. Beyond this temperature range, the substitutional carbon content started to decrease exponentially during isothermal annealing. From the temperature–time behavior of the measured changes in lattice spacing, Fischer et al. [12] extracted activation energy for that process of 3.2 eV. However, the layers remain always pseudomorphically to the Si substrate, i.e., they preserve the Si in-plane lattice constants. Although the number of possible nucleation centers for dislocation generation was quite high, no relaxation by the formation of extended misfit dislocation networks was detected [12, 47]. The observed relaxation effect can be explained by precipitation of carbon or nucleation and diffusion-limited growth of SiC nanocrystals. Contrary to the mechanism of strain relief in Si1xGex , in comparably strained Si1yCy epilayers, the main high-temperature process is precipitation, which does not alter the in-plane lattice constant. Thus, relaxed Si1yCy layers are not suitable as virtual substrates with a smaller in-plane lattice constant as silicon. Similar results were obtained for the thermal stability of compressive strained Si1xy GexCy alloys [48, 49]. Carbon incorporation changes the thermal stability of SiGe layers significantly. As for pseudomorphic Si1yCy layers, plastic relaxation is suppressed by the dislocation pinning effect of C, leading to an increase in thermal stability of strained metastable Si1xy GexCy alloys compared to strain-equivalent Si1xGex layers. Recently, the growth of a relaxed, only 1-mm thick, stepwise graded buffer based on a combination of Si1xGex and Si1xy GexCy with a low threading dislocation density was demonstrated [50]. For the nonoptimized buffer growth the authors found a threading dislocation density below 105 cm2. A stepped Si1x Gex buffer with the identical thickness and strain profile grown with the same temperature ramp yield a threading dislocation density above 107 cm2. This buffer concept relies on the retardation of dislocation glide in Si1xy GexCy relative to strain-equivalent Si1xGex on silicon. Due to the very strong local strain fields around the individual carbon atoms, dislocation glide requires a higher energy in Si1xy GexCy than in undisturbed, strain-equivalent Si1xGex on silicon [51, 52]. This indicates that the addition of carbon might be a promising way for new relaxed buffer concepts with low threading dislocation densities.

2.9.9 Impact of Carbon on Electrical Layer Properties Assuming an average band structure for Si1xy GexCy alloys, Soref [53] has suggested an empirical interpolation between Si, Ge, and diamond for the bandgap. This technique results in an increase in the fundamental gap of Si1y Cy layers with increasing y. Alternatively, Demkov and Sankey [54] have

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-165

modeled Si1yCy alloys with supercells with random occupation of the lattice sites according to the alloy composition. They found that the fundamental gap is reduced when a few percent of carbon are added to the silicon lattice. Photoluminescence measurements on tensile-strained Si1yCy layers yield a reduction in the fundamental gap, with the main offset occurring in the conduction band [55]. From these experimental results, we can state that the virtual crystal approximation is not able to describe the changes in band structure for Si1yCy and Si1xy GexCy alloys correctly. Also the carbon effects cannot be reduced to changes in strain only as proposed earlier by Powell et al. [56]. To describe adequately the observed energy shifts for pseudomorphic C-containing layers, we have to consider at least straininduced effects and effects due to alloying [57, 58]. Extensive calculations including all contributions lead to the following conclusions for ternary alloys [58]: In tensile strained Si1yCy , the fundamental bandgap is reduced, with the main offset occurring in the conduction band. This makes Si1yCy layers particularly suitable for electron confinement. The tensile strain lifts the sixfold degeneracy in the conduction band. Thus, the bandgap is determined by the separation between the light hole and the lowered twofold degenerate valley D(2). The energy splitting in the strained alloys transfers electrons from the upper to the lower valleys, which have a smaller effective mass in the plane. In addition, the energy splitting reduces intervalley scattering between twofold and fourfold degenerate valleys. Analogous to strained silicon, both effects should lead to an increase of in-plane electron mobility for low C contents in Si1yCy . However, most available experimental data do not support these predictions, presumably due to scattering by interstitial C-containing defects. For samples with identical lattice distortion due to misfit strain and hence band alignment, Osten et al. [59] found differences in electron mobility of nearly a factor of two due to the different concentrations of interstitial carbon. Electron transport characteristics have been studied experimentally and theoretically using Monte Carlo (MC) simulations [60–62]. The authors found that the dependence of mobility on C content depends critically on the (unknown) value for the alloy scattering potential. For small alloy scattering potentials the authors found the following behavior for the electron mobility as a function of C concentration: With increasing carbon content the mobility first increases up to a maximum of approximately twice the value for silicon. Further increase in C content leads to a decrease in the mobility, which can be lower than the mobility in silicon, depending on the assumed scattering potential. Assuming a larger scattering potential, MC simulations yield a monotonic decrease in electron mobility with increasing carbon content due to the dominance of alloy scattering over the strain-induced mobility gain. Brunner et al. [63] reported that the mobility enhancement induced by strain is larger than the degradation caused by alloy scattering, leading to electron mobility values above the appropriate Si values, especially at low temperatures. Recently, pMOSFETs using tensile-strained Si1yCy channel layers on Si substrates have been shown to provide mobility enhancement over Si epitaxial channel layers and Si bulk devices [64]. These layers did not exhibit the defects typically associated with a relaxed SiGe buffer structure. Furthermore, pMOSFET devices fabricated on these alloy layers demonstrate enhanced hole mobility over Si epi control and Si bulk. However, increased amounts of C may result in degraded device performance. Therefore, when fabricating such devices, a balance must be struck to minimize C-induced interface charges and alloy scattering rate. The bandgap for the ternary alloys is always smaller than that of silicon, independent of strain state (Figure 2.9.4). The addition of C (Ge) into compressive strained Si1xGex (tensile-strained Si1yCy) leads to a smaller reduction in bandgap narrowing than an equivalent strain reduction in the binary alloy (lower Ge or C content, respectively). The band gap of a fully strain-compensated Si1xy GexCy is a linear function of Ge (or C) concentration. Those layers are strain-free, i.e., there are no thickness limitations due to relaxation. This opens a new way for bandgap engineering of a material on Si(0 0 1) that is macroscopically strain-free.

2.9.10 Summary We have briefly reviewed the basic growth issues and some mechanical and electrical material properties of Si1yCy and Si1xy GexCy layers grown pseudomorphically on Si(0 0 1). This new material promises

© 2006 by Taylor & Francis Group, LLC

2.9-166

The Silicon Heterostructure Handbook

1.2

1.2

Si

y

1.0

1.1

1−

C 1− y

Si

Bandgap (eV)

1.1

xG

1% C

10% Ge

e

x

1.0 2% C

20% Ge

0.9

0.9 3% C

30% Ge

0.8

0.8 −1.0

−0.5 0.0 0.5 Effective lattice mismatch (%)

1.0

FIGURE 2.9.4 Bandgap narrowing for ternary Si1xy GexCy alloys, strained on Si(0 0 1) as a function of lattice mismatch. Both binary alloys (tensile strained Si1yCy and compressive strained Si1xGex) are shown as references.

to alleviate some of the constraints of strained Si1xGex , and open new possibilities for device applications of heteroepitaxial Si-based systems. The incorporation of carbon can be used (i) to improve SiGe layer properties, (ii) to obtain layers with new properties, and (iii) to control dopant diffusion in microelectronic devices.

Acknowlegdments The author would like to thank D. Bolze, E. Bugiel, B. Dietrich, K.E. Ehwald, D. Endisch, G.G. Fischer, P. Gaworzewski, J. Griesche, B. Heinemann, M.C. Kim, W. Kissinger, D. Knoll, D. Kru¨ger, G. Lippert, J.P. Liu, M. Methfessel, K. Pressel, H. Ru¨cker, S. Scalese, R. Sorge, H.J. Thieme, B. Tillack, M. Weidner, and P. Zaumseil for their contributions to the research reviewed in this chapter.

References 1. ST Pantelides and S Zollner (Eds). Silicon–Germanium Carbon Alloys, Growth Properties and Application. New York: Taylor and Francis, 2002. 2. HJ Osten. Carbon-Containing Layers on Silicon. Zu¨rich: Transtech Publications, 1999. 3. E Kasper and K. Lyutovich (Eds). Properties of Silicon Germanium and SiGe:Carbon. London: EMIS Data reviews Series No 24, 2000. 4. KE Ehwald, D Knoll, B Heinemann, KChang, J Kirchgessner, R Mauntel, Ik-Sung Lim, J Steele, B Tillack, A Wolff, K Blum, W Winkler, M Pierschel, F Herzel, U Jagdhold, P Schley, R Barth, and HJ Osten. Modular integration of high-performance SiGe:C-HBTs in a deep submicron, epi-free CMOS process. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1999, pp. 561–564. 5. AR Powell, K Eberl, BA Ek, and SS Iyer. Si1xy GexCy growth and properties of ternary systems. J. Crystal Growth 127: 425–429, 1993. 6. HJ Osten. Supersaturated carbon in silicon and silicon germanium alloys. Mater. Sci. Eng. B 36: 268– 274, 1996. 7. JL Regolini, F Gisbert, G Dolino, and P Boucaud. Growth and characterization of strain compensated Si1xy GexCy epitaxial layers. Mater. Lett. 18: 57–60, 1993. 8. S Im, J Washburn, R Gronsky, NW Cheung, KM Yu, and JW Ager. Optimization of Ge/C ratio for compensation of misfit strain in solid phase epitaxial growth of SiGe layers. Appl. Phys. Lett. 63: 2682–2684, 1993. 9. JW Strane, HJ Stein, SR Lee, BL Doyle, ST Picraux, and JW Mayer. Metastable SiGeC formation by solid phase epitaxy. Appl. Phys. Lett. 63: 2786–2788, 1993.

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-167

10. G Davis, RC Newman. Carbon in monocrystalline silicon, in TS Moss (ed.), Handbook of Semiconductors, Vol. 3, Amsterdam: Elsevier Science, 1994. 11. MS Goorsky, SS Iyer, K Eberl, FK LeGouech, J Angilello, and F Cardonne. Thermal stability of Si1xCx /Si strained layer superlattices. Appl. Phys. Lett. 60: 2758–2761, 1992. 12. GG Fischer, P Zaumseil, E Bugiel, and HJ Osten. High temperature behaviour of strained Si1-yCy /Si heterostructures. J. Appl. Phys. 77: 1934–1937, 1995. 13. J Tersoff. Enhanced solubility of impurities and enhanced diffusion near crystal surfaces. Phys. Rev. Lett. 74: 5080–5083, 1995. 14. PC Kelires and J Tersoff. Equilibrium alloy properties by direct simulation: oscillatory segregation at the Si–Ge(100) 2x1 surface. Phys. Rev. Lett. 63: 1164–1167, 1989. 15. WJ Taylor, TY Tan, and U Goesele. Carbon precipitation in silicon: why is it so difficult? Appl. Phys. Lett. 62: 3336–3338, 1993. 16. HJ Osten, E Bugiel, and P Zaumseil. The growth of an inverse tetragonal distorted SiGe layer on Si(001) by adding small amounts of carbon. Appl. Phys. Lett. 64: 3440–3443, 1994. 17. K Pressel, B Dietrich, H Ru¨cker, M Methfessel, and HJ Osten. Optical investigations of Si1yCy alloys. Mater. Sci. Eng. B 36: 167–170, 1996. 18. HJ Osten, M Kim, K Pressel, and P Zaumseil. Substitutional versus interstitial carbon incorporation during pseudomorphic growth of S1yCy on Si(001). J. Appl. Phys. 80: 6711–6715, 1996. 19. MW Dashiell, LV Kulik, D Hits, J Kolodzey, and G Watson. Carbon incorporation in S1yCy alloys grown by MBE using a single-graphite source. Appl. Phys. Lett. 72: 833–835, 1998. 20. S Zerlauth, H Seyringer, C Penn, and F. Scha¨ffler. Growth conditions for complete substitutional carbon incorporation into layers grown by molecular beam epitaxy. Appl. Phys. Lett. 71: 3826–3828, 1997. 21. TO Mitchell, JL Hoyt, and JF Gibbons. Substitutional carbon incorporation in epitaxial S1yCy layers grown by chemical vapor deposition. Appl. Phys. Lett. 71: 1688–1691, 1997. 22. HJ Osten, J Griesche, and S Scalese. Substitutional carbon incorporation in epitaxial Si1yCy alloys on Si(001) grown by molecular beam epitaxy. Appl. Phys. Lett. 74: 836–838, 1999. 23. PC Kelires and E Kaxiras. Substitutional carbon impurities in thin silicon films: equilibrium structure and properties. J. Vac. Sci. Technol. B 16: 1687–1691, 1998. 24. JP Liu and HJ Osten. Substitutional carbon incorporation during Si1xy Gex Cy growth on Si(100) by molecular beam epitaxy: dependence on germanium and carbon concentration. Appl. Phys. Lett. 76: 3546–3548, 2000. 25. R Duschl, OG Schmidt, W Winter, K Eberl, MW Dashiell, J Kolodzey, NY Jin-Phillipp, and F Phillipp. Growth and thermal stability of pseudomorphic Ge1y Cy /Ge superlattices on Ge(0 0 1). Appl. Phys. Lett. 74: 1150–1152, 1999. 26. HJ Gossmann, C Rafferty, G Hobler, H Vuong, D Jacobson, and M Frei. Suppression of reverse short channel effect by a buried carbon layer. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1998, pp. 725–728. 27. HJ Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe HBT performance and process margins. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1997, pp. 803–806. 28. LD Lanzerotti, JC Sturm, E Stach, R Hull, T Buyuklimanli, and C Magee. Suppression of boron transient enhanced diffusion in SiGe heterojunction bipolar transistors by carbon incorporation. Appl. Phys. Lett. 70: 3125–3127, 1997. 29. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillack, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si /SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1998, pp. 703–806. 30. H. Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, HE Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Device Meeting, Washington, 2003, pp. 121–124.

© 2006 by Taylor & Francis Group, LLC

2.9-168

The Silicon Heterostructure Handbook

31. H Ru¨cker, B Heinemann, W Ro¨pke, R Kurps, D Kru¨ger, G Lippert, and HJ Osten. Suppressed Diffusion of boron and carbon in carbon-rich Silicon. Appl. Phys. Lett. 73: 1682–1684, 1998. 32. PA Stolk, DJ Eaglesham, HJ Gossmann, and JM Poate. Carbon incorporation in silicon for suppressing interstitial-enhanced boron diffusion. Appl. Phys. Lett. 66: 1370–1372, 1995. 33. R Scholz, U Go¨sele, JY Huh, and TY Tan. Carbon-induced undersaturation of silicon self-interstitials. Appl. Phys. Lett. 72: 200–202, 1998. 34. H Ru¨cker, B Heinemann, D Bolze, D Knoll, D Kru¨ger, R Kurps, HJ Osten, P Schley, B Tillack, and P Zaumseil. Dopant diffusion in C-doped Si and SiGe: physical model and experimental verification. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1999, pp. 345–348. 35. H Ru¨cker, B Heinemann, D Bolze, R Kurps, D Kru¨ger, G Lippert, and HJ Osten. The impact of supersaturated carbon on transient enhanced diffusion. Appl. Phys. Lett. 74: 3377–3379, 1999. 36. HJ Osten, G Lippert, P Gaworzewski, and R Sorge. Impact of low carbon concentrations on the electrical properties of highly boron doped SiGe layers. Appl. Phys. Lett. 71: 1522–1524, 1997. 37. B Heinemann, D Knoll, GG Fischer, P Schley, and HJ Osten. Comparative analysis of minority carrier transport in npn bipolar transistors with Si, Si1xGex , and Si1yCy base layers. Thin Solid Films 369: 347–351, 2000. 38. W Windl, OF Sankey, and J Mene´ndez. Theory of strain and electronic structure of Si1yCy and Si1xyGexCy alloys. Phys. Rev. B 57: 2431–2442, 1998. 39. PC Kelires. Monte Carlo studies of ternary semiconductor alloys: application to the Si1xyGex Cy system. Phys. Rev. Lett. 75: 1114–1117, 1995. 40. M Berti, D De Salvator, AV Drigo, F Romanato, J Stangl, S Zerlauth, F Scha¨ffler, and G Bauer. Lattice parameter in Si1yCy epilayers: deviation from Vegard’s rule. Appl. Phys. Lett. 72: 1602–1604, 1998. 41. B Dietrich, HJ Osten, H Ru¨cker, M Methfessel, and P Zaumseil. Lattice distortion in a strain compensated Si1xyGexCy layer on silicon. Phys. Rev. B 49: 17185–17190, 1994. 42. H Ru¨cker, M Methfessel, B Dietrich, K Pressel, and HJ Osten. Phonons as a probe of short-range order in Si1yCy alloys. Phys. Rev. B 53: 1302–1309, 1996. 43. H Ru¨cker, M Methfessel, E Bugiel, and HJ Osten. Strain-stabilized highly-concentrated pseudomorphic Si1yCy layers in Si. Phys. Rev. Lett. 72: 3578–3581, 1994. 44. S Ruvimov, E Bugiel, and HJ Osten. Structural characterization of SinC d-layers embedded in a silicon matrix. J. Appl. Phys. 78: 2323–2327, 1995. 45. AR Powell, FK LeGoues, and SS Iyer. Formation of b-SiC nanocrystals by the relaxation of Si1yCy random alloy layers. Appl. Phys. Lett. 64: 324–326, 1994. 46. AR Powell, K Eberl, FK Legoues, and BA Ek. Stability of strained Si1yCy random alloy layers. J. Vac. Sci Technol. B 11: 1064–1068, 1993. 47. HJ Osten, D Endisch, E Bugiel, B Dietrich, GG Fischer, M Kim, D Kru¨ger, and P Zaumseil. Strain relaxation in tensile strained Si1yCy layers on Si(0 0 1). Semicond. Sci. Tech. 11: 1678–1687, 1996. 48. P Warren, J Mi, F Overney, and M Dutoit. Thermal stability of Si /Si1xy GexCy /Si heterostructures grown by rapid thermal chemical vapor deposition. J. Crystal Growth 157: 414 – 419, 1995. 49. P Zaumseil, GG Fischer, K Brunner, and K Eberl. Comparison of the thermal stability of Si0.603Ge0.397/Si and Si0.597Ge0.391C0.012/Si superlattice structures. J. Appl. Phys. 81: 6134–6140, 1997. 50. HJ Osten and E Bugiel. Relaxed Si1xGex /Si1xy GexCy buffer structures with low threading dislocation density. Appl. Phys. Lett. 70: 2813–2815, 1997. 51. E Bugiel, S Ruvimov, and HJ Osten. TEM characterization of Si1xy GexCy and Si1yCy layers grown with molecular beam epitaxy on (0 0 1)Si substrates. Int. Phys. Conf. Ser. 146: 301– 306, 1995. 52. HJ Osten and J Klatt. In situ monitoring of strain relaxation during antimony-mediated growth of Ge and Ge1yCy layers on Si(001) using refection high energy electron diffraction. Appl. Phys. Lett. 65: 630–632, 1994. 53. RA Soref. Optical band gap of the ternary semiconductor Si1xy GexCy . J. Appl. Phys. 70: 2470– 2472, 1991.

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-169

54. AA Demkov and OF Sankey. Theoretical investigation of random Si–C alloy. Phys. Rev. B 48: 2207– 2214, 1993. 55. K Brunner, K Eberl, and W Winter. Near-band-edge photoluminescence from pseudomorphic Si1yCy quantum well structures. Phys. Rev. Lett. 76: 303–306, 1996. 56. AR Powell, K Eberl, BA Ek, and SS Iyer. Si1xyGexCy growth and properties of ternary systems. J. Crystal Growth 127: 425–429, 1993. 57. S Zollner. Theory of optical interband transitions in strained Si1yCy grown pseudomorphically on Si(001). J. Appl. Phys. 78: 5209–5211, 1995. 58. HJ Osten. Band gap changes and band offsets for ternary Si1xyGexCy alloys on Si(0 0 1). J. Appl. Phys. 84: 2716–2721, 1998. 59. HJ Osten, J Griesche, P Gaworzewski, and KD Bolze. Influence of interstitial carbon defects on electron transport in strained Si1yCy layers on Si(0 0 1). Appl. Phys. Lett. 76: 200–202, 2000. 60. HJ Osten and P Gaworszewski. Charge transport in strained Si1yCy and Si1xyGexCy alloys on silicon. J. Appl. Phys. 82: 4977–4981, 1997. 61. M Ershov and V Ryzhii. Monte Carlo study of electron transport in strained silicon–carbon alloy. J. Appl. Phys. 76: 1924–1926, 1994. 62. P Dollfus, S Galdin, P Hesto, and HJ Osten. Band offsets and electron transport calculation for strained Si1xyGexCy /Si heterostructures. J. Mater. Sci.: Mater. Electron. 12: 245–248, 2001. 63. K Brunner, W Winter, K Eberl, NY Jin-Phillip, and F Phillip. Fabrication and band alignment of pseudomorphic Si1yCy , Si1xyGexCy and coupled Si1yCy /Si1xyGexCy quantum well structures on Si substrates. J. Crystal Growth 175/176: 451–458, 1997. 64. E Quinones, SK Ray, KC Liu, and S Banerjee. Enhanced mobility pMOSFETs using tensile-strained Si1yCy layers. IEEE Electron. Device Lett. 20: 338–340, 1999.

© 2006 by Taylor & Francis Group, LLC

2.10 Contact Metallization on Silicon– Germanium

C. K. Maiti Indian Institute of Technology Kharagpur

2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7

Introduction........................................................... 2.10-171 Contact Metallization: Current Status................. 2.10-172 Contact Metallization: Challenges ....................... 2.10-173 Poly-SiGe Gate Technology .................................. 2.10-175 Silicidation of SiGe................................................ 2.10-175 Silicidation of SiGeC............................................. 2.10-181 Summary ................................................................ 2.10-181

2.10.1 Introduction During the last 40 years, Si-based complementary metal oxide semiconductor (CMOS) technology has emerged as the most predominant technology for the microelectronics industry. The success of the technology has largely been due to technological innovations that enabled continuous scaling of device dimensions, which have resulted in improvements in both device performance and packing density. However, this trend cannot continue indefinitely and we are approaching the fundamental limits of Si technology. To overcome the fundamental limits of Si, still maintaining compatibility with the conventional Si processing, several new materials such as strained-SiGe, strained-Si, and silicon–germanium– carbon (SiGeC) are currently being considered. Acceptance of a new material in CMOS technology requires a detailed understanding of the consequences, if incorporated. Currently, self-aligned silicide technology is being used to form the source and drain regions to reduce the RC delay, increase driving current, and enhance the performance of deep submicron CMOS devices. In CMOS technologies, among many other metals, Ti, Co, Ni, Pt, and Pd have been studied in detail for silicidation. The reader may refer to an excellent recent review by Zhang and Ostling [1]. Properties of some commonly used metals and their silicides for salicide applications in Si CMOS technology are shown in Table 2.10.1 and Table 2.10.2, respectively. According to the International Technology Roadmap for Semiconductors (ITRS) 2003 [2], the device scaling and increased functionality is expected to continue at least until 2016, when the minimum feature size is projected to be 22 nm. Currently one of the key challenges in device scaling is to develop new contact technologies for the MOSFETs as the source/drain (S/D) parasitic series resistance is becoming a significant fraction of the channel resistance. The ITRS roadmap predicts the requirements for source/drain contact regions as: (i) junction depth/sheet resistance (<100 ohm/sq. for 30 nm junctions), (ii) ultralow resistivity contacts (1.5 108 ohm-cm2), (iii) excellent reverse leakage characteristics (less than 1% of the Ioff ), and (iv) integration compatibility with high-k gate dielectrics using the conventional CMOS process flow.

2.10-171 © 2006 by Taylor & Francis Group, LLC

2.10-172

The Silicon Heterostructure Handbook

TABLE 2.10.1

Properties of Some Commonly Used Metals for Silicide Applications in Si CMOS Technology

Melting Point (8C)

Resistivity (mV-cm)

Schottky Barrier (eV) (on n-Si)

Reaction Temperature to Si (8C)

Thermal Stability on SiO2 (8C)

W TiN Ta Mo Ti Al

3387 2950 2996 2610 1675 660

6–15 50–200 15–20 6–15 45–50 3–4

0.65–0.7 0.45–0.5 0.55–0.6 0.6–0.7 0.5–0.55 0.65–0.75

600–700 450–500 450–500 400–700 400–500 250

1000 900 700 900

TABLE 2.10.2

Properties of Commonly Used Silicides for Salicide Applications

Formation temperature (8C) Silicide per nm of metal Silicon consumption per nm of silicide Resistivity (mV-cm) Barrier height on n-Si (eV)

26 Q & Silicide thickness (nm)

TiSi2

CoSi2

NiSi

PtSi

750–900 2.3 0.904 13–20 0.61

550–900 2.6 1.03 14–20 0.65

350–750 1.8 0.82 14–20 0.67

350–750 1.3 0.7 28–35 0.87

Silicide thickness (R) Max. silicon consumption (Q)

24

450

18

22

16

20

14

18 16

12

R

14 12

10

Q

10

8

8

6

6 5

10

15

20 25 30 35 Gate length (nm)

40

45

50

Contact silicide sheet resistance (Ohms/sq)

Metal

FIGURE 2.10.1 The predicted silicon consumption, silicide thickness, and the silicide sheet resistance values by ITRS-2003 are plotted as a function of gate length.

In addition to providing a low contact resistivity, future contact materials should satisfy several criteria, such as the formation of ultrathin silicide contacts, low silicide resistivity, and minimum temperature required to reach the low resistivity phase. Junction depth scaling requires that the thickness of the silicide be also scaled accordingly to reduce the silicon consumption and preserve the integrity of the junction. The trend can be seen in Figure 2.10.1, which shows the ITRS 2003 predictions for junction depth, silicide thickness, and silicide sheet resistance for future CMOS technology nodes.

2.10.2

Contact Metallization: Current Status

Recently, there have been concerns related to the increase of TiSi2 film resistivity on submicron gate lines due to the retarded phase transition from the high-resistivity C49 phase to the low-resistivity C54 phase

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-173

[3, 4]. Ni–silicide has been proposed as a potential candidate for advanced CMOS Si technology because Ni consumes less silicon (important for applications on ultrathin Si layers) [5], and has less risk of spiking in ultrashallow junctions. NiSi is used not only in CMOS but also in bipolar technology as the contact material because of its superior properties. NiSi does not show adverse line-width dependence of sheet resistance, which is often a big problem in TiSi2 and sometimes in CoSi2. Silicon consumption during the silicidation is the smallest among the Ti, Co, and Ni [6]. As such NiSi or nickel monosilicide are chosen as the gate, source, and drain contact material. The sheet resistance of the narrow line was found to even decrease because of the edge effect specific to NiSi [7], which is suitable for ultrashallow S/D junction formation for scaled CMOS. The mechanical stress of the NiSi film on silicon substrate is also the smallest. Contact resistance to p-type silicon, which was a problem for TiSi2, is the smallest due to its lowest barrier height, and that to n-type silicon was found to be also small [8]. Bridging failure between the gate electrode and source/drain hardly occurs for the NiSi silicide due to its reaction mechanism. On the other hand, major concern for NiSi salicide is its low heat resistance. In fact, the maximum allowable process temperature after the salicidation is around 700–7508C. In addition, NiSi can be formed by one-step annealing at low temperature (400–6008C) without any agglomeration and shows a lower resistivity and junction leakage. Aggressive scaling of the channel length and gate oxide thickness in a MOSFET leads to several problems, such as excessive tunneling current through the gate dielectric (100 A /cm2), which limits the scaling of gate oxide thickness around 12–14 A˚, polysilicon (poly-Si) gate depletion which increases the equivalent SiO2 thickness by about 3 A˚, high gate resistance, gate tunneling leakage current, and boron penetration into the channel region. Metal gate technology not only eliminates the gate depletion and boron penetration problems, but also greatly reduces the gate sheet resistance, particularly of interest in ac performance. Replacement of polysilicon gate electrodes in MOSFETs with metal thus promises many advantages. An approach analogous to the established dual poly-Si gate technology (dual metal) is desirable. The major challenge is to find two metals with suitable work functions and a way to integrate them in a CMOS process. Alternative gate dielectrics such as HfO2, ZrO2, Ta2O5, and Si3N4 are being investigated for scaling gate dielectric thickness below 20 A˚ when direct tunneling current through SiO2 may be too high for acceptable standby power consumption. Currently, the silicon nitride/oxynitride dielectric stack is in use due to its compatibility with CMOS processes. Therefore, a process that combines the advantages of dual metal gate and the high-k gate dielectric would be an attractive technology option for scaling the conventional MOSFET structures below 0.1 mm (beyond 65-nm technology node). For future technology nodes, junction formation at low temperatures is also a key necessity since high-k gate dielectrics of interest cannot withstand typical annealing temperatures used to remove implantation damage and activate the dopants.

2.10.3 Contact Metallization: Challenges While the dual metal contact approach appears to be promising at a first glance, integration of two different self-aligned silicide processes is likely to be quite challenging. Furthermore, Fermi level pinning will most likely restrict the benefits of using materials with different work functions. Thus, there is an urgent need to develop new source/drain junction and contact technologies that limit the parasitic series resistance to a fraction of the MOSFET channel resistance (see Figure 2.10.2), and requires fundamentally new approaches. Of particular interest is the smaller bandgap of Si1xGex, resulting in a smaller metal–semiconductor barrier height, which is a key advantage in reducing the contact resistivity of a metal–semiconductor contact. Interest in Si1xGex alloys for performance enhancement of MOSFETs has been escalating in recent years as well [9]. Epitaxially grown Si1xGex layers on Si, under compression, display an enhanced effective hole mobility compared to bulk-Si. This hole mobility enhancement offers a superior channel properties compared to the conventional Si channel in a MOSFET. The SiGe alloys may be incorporated in a MOSFET to enhance the device performance as: (a) compressively strained channel, (b) relaxed

© 2006 by Taylor & Francis Group, LLC

2.10-174

The Silicon Heterostructure Handbook

Poly-Si gate

Source

P+

Drain

P+ SiGe layer under compression n-type Si substrate

(a)

Rcontact

Rchannel Rextension

Rspreading

(b)

FIGURE 2.10.2 (a) Presence of Si1xGex alloy layer in different parts of a heterostructure MOSFET and (b) cross section of a MOS transistor illustrating the parasitic series resistance components.

virtual substrate for tensile strained-Si, (c) tunable work function in the gate, and (d) low-resistivity source/drain extension. Presence of Si1xGex alloys in different structural forms in the various parts of a MOSFET is shown in Figure 2.10.2. SiGe is advantageous because it can be selectively deposited as well as selectively etched compared to Si. In order to realize the improvements in electron mobility and a usable conduction band offset, it is necessary for the film to be in biaxial tension. Instead of growing a thin Si1xGex layer on Si, a thin epitaxial layer of Si grown on a thick relaxed Si1xGex buffer layer can serve this requirement. Due to the lattice mismatch, the thin Si layer is in biaxial tension and exhibits an enhancement in both electron and hole mobilities, making it useful for both n- and p-MOSFETs. It also shows fairly large band offsets (on the order of 100 meV or more) in both valence and conduction bands relative to the relaxed Si1xGex on which it is grown. This allows the tailoring of the band structure to confine both holes and electrons. Strained-Si /SiGe heterolayers on Si wafers are currently being explored as a channel material for high performance heterostructure MOSFETs [10]. Developing robust technology for forming good metal(M)/SiGe source/drain contact regions and ultimately developing a metal silicidation process for application in future strained-Si and SiGe-channel hetero-FETs with high performance is of technological interest. Several new S/D technology using Si1xGex for future CMOS technology nodes have been proposed [11, 12]. However, applying the conventional self-aligned silicide process to the strained-Si and SiGe MOSFETs is not straightforward due to the following reasons: 1. The strained-Si film is too thin to accommodate the conventional silicide. For example, if cobalt or nickel is used to make the silicide, then the Si film must be thicker than about 25 nm to accommodate the silicide. 2. The pseudomorphic strained-Si layer cannot be made thicker than 20 nm as the critical thickness depends upon the composition of the substrate, such as the mole fraction of Ge in the relaxed layer. 3. Since the strained-Si film is not thick enough to supply enough silicon to form the silicide, the silicide will consume some of the underlying SiGe buffer.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-175

The conventional approach in the Si CMOS technology to the abovementioned problems is to make the silicon thicker in the source and drain regions prior to applying the salicide process. But the addition of Si must be selective, and should be limited only to the source and drain regions, which may be obtained by a selective deposition. Selective epitaxy is usually preferred to deposit Si only to the source, drain, and gate regions. Recently, a new self-aligned salicide process that does not require an increase in the thermal budget (high temperature) and is applicable to strained-Si /SiGe materials involving Ni, has been proposed [13].

2.10.4 Poly-SiGe Gate Technology The fabrication of Si1xGex channel MOSFETs [14] always leads to the presence of Si1xGex in the source/ drain regions (see Figure 2.10.2). Perhaps the most important advantage of using Si1xGex instead of Si as a junction material is that Si1xGex provides a promising solution to the contact resistance challenge by raising the possible active doping concentration and lowering the contact barrier height [11, 15–19]. A poly-SiGe gate technology offers several advantages over conventional gate (poly-Si) conductors. First, poly-SiGe gate conductors require a relatively low-temperature rapid thermal anneal (RTA) to activate the dopants such as boron and phosphorous in the gate conductor. A low-temperature RTA facilitates the formation of ultrashallow source/drain junctions and the formation of ultratight pocket regions. Second, poly-SiGe gate conductors effectively suppress boron penetration into a gate conductor heavily doped with phosphorous. Third, poly-SiGe gate conductors can be utilized to adjust the threshold voltage of the transistor. The bandgap of Si1xGex lies between 0.67 eV (bandgap of Ge) and 1.12 eV (bandgap of Si) depending on the amount of Ge and the amount of strain in the lattice. The work function of a transistor is related to the concentration of Ge in the poly-SiGe gate conductor. This aspect is particularly advantageous in integrated circuits having transistors with several threshold voltage levels. Poly-Si1xGex gate technology offers a reduction in gate depletion compared to poly-Si as well. Bang et al. [20] have reported sheet resistance, Hall mobility, and effective carrier concentration as a function of annealing parameters for boron and phosphorus ion implanted films of poly-Si, Si0.75Ge0.25 and Si0.50Ge0.50. The films were ion implanted with boron or phosphorus at dosages between 5 1014 and 4 1015 cm2 and then thermally annealed between 5508C and 6508C from 0.25 to 120 min. The solid solubility of the most common dopants, such as B, P, and As is much higher in Si than in Ge. Boron-doped films showed decreasing minimum sheet resistance with increasing Ge mole fraction while phosphorus-doped films exhibited the reverse trend. However, the solubility of B in Si1xGex is found to drop when increasing the Ge fraction [21]. Supersaturation doping of Si1xGex with B is possible with the in situ doping technique using Si-, Ge-, and B-source gases simultaneously. For strained Si1xGex, alloying with B up to 10 at.%, due to strain compensation effect [22, 23], has been demonstrated by Gannavaram and Ozturk to yield extremely low specific resistivity and contact resistivity values [11] of 0.2-mV-cm and 1.5 108 cm2, respectively.

2.10.5 Silicidation of SiGe In order to form contacts to source /drain junctions formed by the selective Si1xGex technology, a selfaligned contact process needs to be developed. Fortunately, Si1xGex alloys react with common silicide metals to form germanosilicides with properties much like those of silicides. To form these germanosilicide contacts, a good understanding of the metal /Si1xGex ternary solid-phase reactions is necessary. It is important to identify the most promising germanosilicides as self-aligned contacts to source/drain junctions formed by the selective Si1xGex technology. Towards this end, many research groups have made significant contributions towards the understanding of silicide formation of various metals in strained-SiGe and strained-Si layers. Results of studies of interaction between Si1xGex and other transition metals than Ti, Co, and Ni, such as Pd [24, 25], Pt [26–29], Fe [30], Mo [31], W [32], and Zr [33–39] are available in the literature, but they will not be discussed in order to keep our focus on

© 2006 by Taylor & Francis Group, LLC

2.10-176

The Silicon Heterostructure Handbook

contact metallization using the SALICIDE technique in CMOS technology. Experimental SiGe germanosilicide results on Ti [40–45], Co [43, 46–50], and Ni [51–56] have been reported. It is important to note that the majority of the published work on metal /Si1xGex solid-phase reactions involve undoped Si1xGex layers. For applications in strained-Si and SiGe, NiSi is chosen because Ni reacts with both strained-Si and SiGe and forms low sheet resistance silicide and germanosilicide in the source /drain area [54]. To study the solid-state interactions between Ti, Co, or Ni and Si1xGex, the relevant phase diagrams are important. The available thermochemical data indicate that the germanides are less stable than their corresponding silicides with the same atomic composition but by replacing Ge with Si, as the heats of formation (enthalpy) or Gibbs free energies are lower (less negative) for the germanides. An approximate ternary phase diagram depicting the composition domains directly concerning the formation of NiSi1xGex as well as its interaction with Si1xGex is shown in Figure 2.10.3. The formation of germanides or germanosilicides tends to occur at a lower temperature than the formation of the silicides. The required experimental thermochemical data for the different phases involved in the pseudophase diagram were obtained from Ref. [55]. The pseudophase diagram shows that Ni, Si, Ge, NiSi, and NiGe surround the triangle. The existence and orientation of the tie lines provide the necessary information about the formation of Ni(Si,Ge) during low-temperature silicidation. A comparative study on Ni and Co reacting with single-crystal Si0.3Ge0.7 also shows a clear advantage with Ni because a continuous NiSi1xGex layer was found, yielding the desired low-resistivity contact [57]. Figure 2.10.4 indicates that the processing window for CoSi2 and TiSi2 as 800–8508C. At low annealing temperatures, cobalt yielded a very high sheet resistance, presumably due to the formation of Co(Si1yGey) and retarded the formation of low resistive CoSi2 phase. Because Ge atom hinders the transformation of Co(Si1yGey) structure to its lowest resistive Co-silicide phase CoSi2 which forms at a high temperature, 9008C, and the germanosilicide layer shows severe agglomeration. But Ni is also found to be suitable in metal–semiconductor contact formation as its lowest resistive phase is attainable below 7008C as shown in Figure 2.10.4. Figure 2.10.5(a) and (b) shows the SEM micrographs of the Ni-silicided films annealed at 5008C and 6008C for 60 s, respectively. The SEM micrographs show that the surface of the silicided film is still relatively smooth and the grain boundaries are not very prominent. Size of the grains gradually increases with increasing annealing temperature. It has been observed that agglomeration starts to take place above 7008C annealing and it results in a very abrupt increase in the sheet resistance [54, 56].

Sheet resistance (Ω/ )

103

Ni 600⬚C

NiSi

NiGe

Si

Co-germanosilicide Ti-germanosilicide

NiSi

Ni-germanosilicide

102

101

Ge

FIGURE 2.10.3 Pseudophase diagrams of the Ni–Si–Ge ternary system at 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48: 1391–1399, 2004.)

© 2006 by Taylor & Francis Group, LLC

CoSi2 TiSi2

400

500 600 700 800 Annealing temperature (⬚C)

900

FIGURE 2.10.4 Variation of sheet resistance as a function of annealing temperature. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

2.10-177

Contact Metallization on Silicon–Germanium

(a) 5008C

Acc V 9mol Magn 001 WD 5.00kV 3.0 30000x TLD 4.8 sg5

500 nm

(b) 6008C

Acc V 9mol Magn 001 WD 5.00kV 3.0 50000x TLD 4.8 sg5

500 nm

FIGURE 2.10.5 SEM micrographs of Ni-germanosilicided/Si1xGex film annealed at (a) 5008C and (b) 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

The XTEM micrographs of Ni-silicided Si1xGex films annealed at 5008C and 6008C, for 60 s are shown in Figure 2.10.6(a) and (b), respectively. The grain formation generally starts by grain boundary grooving and the atoms diffuse away from the highly curved grain boundaries. It is evident that Ge with higher diffusion coefficient in germanosilicide may out-diffuse into the grain boundaries and form a Ge-rich Si1xGex grain with an increase in the annealing temperature. At 5008C, a layer of relatively uniform NiSi0.75Ge0.25, with a thickness of about 80+10 nm, was found. However, a very small amount of Ge-rich Si1xGex grains was detected, in between the Ni(Si0.75Ge0.25) grains. Similar results were also obtained for a

© 2006 by Taylor & Francis Group, LLC

2.10-178

The Silicon Heterostructure Handbook

(a) 5008C

50 nm

SiGe

Ni(SiGe)

(b) 6008C

50 nm

SiGe

Ni(SiGe)

FIGURE 2.10.6 XTEM micrographs of the Ni-germanosilicided/Si1xGex films annealed at (a) 5008C and (b) 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

lower anneal temperature (3008C) except that the NiSi0.75Ge0.25 was relatively uniform without the presence of any Ge-rich Si1xGex grains. At 6008C anneal temperature, Ge out-diffuses from the Ni(Si0.75Ge0.25) grain and penetrates into the grain boundaries and reacts with both Si and Ge. The distribution and thickness of such germanosilicide grains increase with the increase in annealing temperature. Due to thermal agglomeration, germanosilicide grains lose their columnar structure at the surface and at the interface of silicide–substrate. However, it is clear from the TEM images that the silicide / Si1xGex interface remains smooth within the annealing temperature range of 300–6008C [52, 58, 59]. Aldrich et al. [41, 42] have studied the Ti/Si1xGex system, and found that C49 and C54 Ti/Si1yGey phases are formed with the Ge concentration of the Si1xGex substrate (when x < 0.40). At higher annealing temperatures, the Ge concentration in the germanosilicide decreases and a Ge-rich Si1zGez

© 2006 by Taylor & Francis Group, LLC

2.10-179

Contact Metallization on Silicon–Germanium TABLE 2.10.3

Lattice Structure and Lattice Constants for Ni and Pt Silicide and Germanide

NiSi NiGe PtSi PtGe PdSi

Lattice Structure

a (A˚)

b (A˚)

c (A˚)

Orthorhombic Orthorhombic Orthorhombic Orthorhombic Orthorhombic

5.233 5.381 5.595 5.719 5.599

3.258 3.428 3.603 3.697 3.381

5.659 5.811 5.932 6.084 6.133

alloy precipitates along the grain boundaries, while germanium segregates out of the germanosilicide lattice, and is replaced by Si from the alloy. Lattice structure and lattice constants for Ni and Pt silicide and germanide are shown in Table 2.10.3. Formation of Ni2Si causes an intrinsic compressive stress [60] in agreement with the expectation of a volumetric expansion at the Ni2Si–Si interface. Forces caused by the formation of NiSi are difficult to understand due to the presence of two reaction interfaces. The force changes during the silicide formation and was modeled by Zhang and d’Heurle [61]. However, when the Ni films are subjected to prolonged isothermal annealing, stresses that developed during silicide formation gradually relax. Metal silicides and silicides /germanides have the drawback of less thermal stability and the consumption of silicon/germanium; while the latter is less of a problem for raised source/drains, scaling of vertical dimensions is never the less hampered. Studies on the effect of Ge concentration in relaxed Si1xGex on Ni silicidation process for different annealing temperatures have revealed that ternary compounds always form, and at the same time, Ge segregation has been observed when annealing temperature is above 4008C. Ge segregation with strain relaxation of the underlying Si1xGex, which commonly appears in the metal /Si1xGex reactions using conventional annealing techniques, was effectively suppressed using pulsed laser annealing for Co [50] and Ni [51–53]. Due to rapid melt and solidification processes in laser annealing, the microstructure of the germanosilicide formed by pulsed laser annealing has been shown to be superior. The segregated germanium atoms can react with Si atoms and result in a Ge-rich Si1xGex alloy adjacent to the germanosilicide. Therefore, the solid-phase reactions between metals and Si1xGex can, in general, be characterized as [42]: 1. germanosilicide formation at lower temperatures; and 2. germanosilicide formation accompanied with germanium loss at higher temperatures. The two cases can be described with the following equations: M þ Si1x Gex ! My (Si1x Gex )1y My (Si1x Gex )1y þ Si1x Gex ! My (Si1w Gew )1y þ (Si1z Gez ) (w < x < z) A schematic representation of this reaction sequence is shown in Figure 2.10.7. As shown, Ge loss from the germanosilicide occurs via Ge segregation at the grain boundaries, resulting in the formation of Ge-rich Si1zGez precipitates. The precipitates promote agglomeration and lead to higher sheet resistance due to high resistivity conduction barriers through the germanosilicide [42, 62]. The structure, melting point, typical formation temperature, specific resistivity, and Schottky barrier heights to n-type Si for monosilicides of Ni, Pt, and Pd and monogermanides of Ni and Pt thin films are shown in Table 2.10.4. As Ge segregation will degrade the contact performance, the control of the Ge segregation is crucial. Some reports have shown that the onset temperature for obtaining uniform low-resistivity Ni–SiGe is a strong function of the Ge concentration. In addition, it has further been shown that the RTA technology

© 2006 by Taylor & Francis Group, LLC

2.10-180

The Silicon Heterostructure Handbook

M

M

M

M (a)

Si1−xGex

Si1−xGex

My(Si1−xGex)1−y

Si1−xGex

My(Si1−xGex)1−y (b) Si1−xGex

Ge

Ge

Ge

Ge (c)

Si1−xGex My(Si1−wGew)1−y

Si1−zGez

My(Si1−wGew)1−y (d)

Si1−xGex

FIGURE 2.10.7 Model for the formation of Si1zGez grains between germanosilicide grains: (a) thermal reaction starts initially by the interdiffusion of metal (M), Si, and Ge, (b) formation of M-germanosilicide, (c) segregation of Ge from the germanosilicide grains, and (d) germanosilicide grains become discontinuous due to a rapid growth of Ge-rich grains.

TABLE 2.10.4 Structure, Melting Point, Typical Formation Temperature, Specific Resistivity, and Schottky Barrier Heights to n-type Si for Monosilicides of Ni, Pt, and Pd and Monogermanides of Ni and Pt Thin Films Phase

Melting Point (8C)

Reaction Temperature (8C)

Resistivity (V-cm)

SBH (eV)

NiSi NiGe PtSi PtGe PdSi

980 860 1230 1075 972

250–400 <400 200–540 — 850

14 — 80 — 30

0.65 0.88 — —

has a very narrow process window for different Ge concentrations and may not be a viable manufacturable technology for fabricating uniform Ni–SiGe. In general, due to Ge segregation during germanosilicide formation, agglomeration and strain relaxation of the unreacted Si1xGex film take place. At present, among all the germanosilicides studied, NiSi1xGex has offered the lowest resistivity and is capable of satisfying most of the needs of future CMOS technology. Since NiSi1xGex is a monogermanosilicide, it consumes less of the underlying Si1xGex compared to other digermanosilicides such as those of titanium or zirconium. However, the only concern for Ni germanosilicide appears to be its limited thermal stability. It has been observed that at temperatures equal to or higher than 5008C, Ge out-diffusion from the NiSi1xGex results in formation of Ge-rich Si1zGez precipitates, which could eventually transform into Si1zGez grains, which results in a rough top surface as well as a rough interface, high sheet resistance, and also high junction leakage. A new approach has been proposed to improve the thermal stability of NiSi1xGex. It has been reported that by inserting a thin layer of Pt between Ni and Si1xGex the thermal stability of the germanosilicide can be significantly improved through delaying the transition from NiSi to NiSi2, which is responsible for the increased resistivity and the junction consumption [63–68]. It has also been

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-181

observed that on heavily boron-doped Si1xGex, the sheet resistance of the NiSi1xGex formed with a thin Pt interlayer is more stable than that of NiSi1xGex formed from pure Ni. However, the lowest sheet resistance value achieved using Ni with a thin Pt interlayer is slightly higher than the sheet resistance of the NiSi1xGex achieved using pure Ni. For phosphorus-doped nþ-Si1xGex, Pt incorporation might change the barrier height of the contact and preliminary results on nþ-Si1xGex obtained indicate that the Pt interlayer actually improves the contact resistance for Ni germanosilicide on nþ-Si1xGex while the contact resistance with pure Pt germanosilicide is higher. Incorporation of a small amount of Pt in Ni-Si1xGex via a thin Pt interlayer between Ni and Si1xGex, in general, results in an improved thermal stability of Ni(Pt) germanosilicide.

2.10.6 Silicidation of SiGeC The large mismatch between SiGe alloys and Si leads to severe restrictions in terms of critical thickness and thermal stability. The equilibrium critical thickness of a pseudomorphic SiGe layer depends on the total strain energy in the layer and restricts the applications where high Ge concentrations are needed. Addition of substitutional carbon to a SiGe alloy gives an extra degree of freedom to control the bandgap. Moreover, the strain introduced by the Ge atoms can be compensated by C atoms, which are smaller than Ge and Si atoms, resulting in a critical thickness that can be significantly increased. Aubry-Fortuna et al. [35] have investigated the reactions between Zr and SiGeC alloys using RTA. The interactions of the metal films with the Si1xyGexCy alloys have been investigated by using various analytical tools. The authors concluded that Zr may be a good candidate for contacts on IV–IV alloys in terms of thermal stability. The reaction of Co with epitaxial SiGeC /Si layers has been investigated and compared to the reaction of Co with SiGe /Si layers by Donaton et al. [69]. The sequence of phase formation is the same as the reaction of Co with monocrystalline Si, however, cobalt disilicide is formed at much higher temperatures. The presence of C delays the disilicide formation, as a result of C accumulation at the silicide– substrate interface during the reaction, which blocks the Co diffusion paths. XRD spectra of 17 nm Co on Si0.811Ge0.18C0.009 after annealing for 30 s at different temperatures showed that after 5008C the predominant phase is Co2Si in both cases, although the presence of the monosilicide (CoSi) has been observed. Further annealing at 6008C and 7008C results in a full transformation to CoSi. At 8008C both the mono- and the disilicide phases have been identified, with the CoSi2 peaks being much more intense in the case of the reaction on SiGe than on SiGeC, indicating the presence of a higher fraction of this phase in the former film. It has been observed that the presence of C retards the formation of the disilicide phase. During the reaction, C piles up at the silicide–substrate interface, which is believed to block the Co diffusion paths. The precise role of the C atoms in this retardation is not yet fully understood and is a subject that deserves further investigation. Also, in case of Si1xyGexCy , the presence of substitutional C was found to be effective in reducing strain relaxation during solid-phase reactions to form Ti germanosilicide [44].

2.10.7 Summary One of the key challenges for future CMOS technology is to form source/drain junctions and contacts with very small parasitic series resistance. Germanosilicides of different metals were reviewed with the objective of finding the best germanosilicide candidates for low-resistivity contacts to heavily doped Si1xGex alloys. Formation of germanosilicide of Ti, Co, and Ni contacts to Si1xGex alloys has been discussed in detail. Similar to other germanosilicides, Ni /Si1xGex suffers from Ge out-diffusion. It was found that Ge lost from the Ni /Si1xGex grains formed Ge-rich Si1zGez precipitates accumulating at the germanosilicide grain boundaries. Consequently, the formation temperature of Ni/Si1xGex needs to be kept below 4508C.

© 2006 by Taylor & Francis Group, LLC

2.10-182

The Silicon Heterostructure Handbook

New junction formation technology based on selective deposition of Si1xGex alloys in source/drain regions is needed. Smaller bandgap of Si1xGex and poly-SiGe resulting in a smaller metal–semiconductor barrier height, which reduces the contact resistivity of a metal–semiconductor contact has been described. Ni and Pt germanosilicides are found to be attractive because they form both monogermanosilicides and consume much less Si1xGex than Zr(Si1 xGex)2. A new approach to form ultrathin Ni / Si1xGex layers with enhanced thermal stability by incorporating a thin Pt interlayer between Ni and Si1xGex has also been discussed. There is a growing interest to form strained-Si layers without a thick relaxed Si1xGex buffer. As the MOSFET dimensions are scaled down to tens of nanometers, the composition of the source/drain junctions will most likely have a strong impact on the strain in the channel region. In particular, the impact of Si1xGex junctions on the two sides of a MOSFET channel needs further investigation. However, the Si1xGex junction technology may provide a simple yet powerful means to form strained-Si channels without involving complex and costly fabrication procedures.

References 1. SL Zhang and M Ostling. Metal silicides in CMOS technology: past, present, and future trends. Crit Rev Solid State Materials Sci 28:1–129, 2003. 2. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, San Jose, California, 2003. 3. J Lasy, J Nakos, O Chin, and P Geiss. Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2. IEEE Trans Electron Dev 38:262–269, 1991. 4. H Jeon, CA Sukow, Honecutt, GA Rozgonyi, and RJ Nemanich. Morphology and phase stability of TiSi2 on Si. J Appl Phys 71:4269–4276, 1992. 5. MC Poon, CH Ho, F Deng, SS Lau, and H Wong. Thermal stability of cobalt and nickel silicides. Microelectron Reliab 38:1495–1498, 1998. 6. T Morimoto, HS Momose, T Iinuma, I Kunishima, K Suguro, H Okano, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. A NiSi salicide technology for advanced logic devices. IEEE IEDM Tech Dig 653–656, 1991. 7. T Ohguro, S Nakamura, M Koike, T Morimoto, A Nishiyama, Y Ushiku, T Yoshitomi, M Ono, M Saito, and H Iwai. Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films. IEEE Trans Electron Dev 41:2305–2317, 1994. 8. T Morimoto, T Ohguro, H S Momose, T Iinuma, I Kunishima, K Suguro, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI. IEEE Trans Electron Dev 42:915–922, 1995. 9. CK Maiti and GA Armstrong. Applications of Silicon–Germanium Heterostructure Devices. Bristol: Institute of Physics, 2001. 10. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. UK: IEE, 2001. 11. S Gannavaram, N Pesovic, and MC Ozturk. Low temperature (< 8008C) recessed junction selective silicon-germanium source /drain technology for sub-70 nm CMOS. IEEE IEDM Tech Dig 437–440, 2000. 12. MC Ozturk, J Liu, H Mo, and N Pesovic. Advanced Si1xGex source /drain and contact technologies for sub-70 nm CMOS. IEEE IEDM Tech Dig 375–378, 2002. 13. Q Xiang, JS Goo, J Pan, B Yu, S Ahmed, J Zhang, and MR Lin, Strained silicon NMOS with nickel– silicide metal gate. IEEE VLSI Tech Symp Dig 101–102, 2003. 14. SV Vandebroek, E Crabbe, B Meyerson, D Harame, P Restle, J Stork, and J Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Trans Electron Dev 41:94–101, 1994. 15. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. IEEE IEDM Tech Dig 253–256, 1990.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-183

16. TJ King, JR Pfiester, and KC Saraswat. A variable work function polycrystalline Si1xGex gate material for submicrometer CMOS technologies. IEEE Electron Dev Lett 12:533–535, 1991. 17. YV Ponomarev, C Salm, J Schmitz, PH Woerlee, PA Stolk, and DJ Gravesteijn. Gate workfunction engineering using poly-(Si, Ge) for high-performance 0.18 m CMOS technology. IEEE IEDM Tech Dig, 1997, 829–832. 18. PE Hellberg, SL Zhang, HH Radamson, and W Kaplan. Threshold voltage control for pMOSFETs using an undoped epitaxial Si channel and a pþ-SixGe1x gate. Solid-State Electron 44:2085–2088, 2000. 19. WC Lee, B Watson, TJ King, and C Hu. Enhancement of PMOS device performance with poly-SiGe gate. IEEE Electron Dev Lett 20:232–234, 1999. 20. DS Bang, M Cao, A Wang, KC Saraswat, and TJ King. Resistivity of boron and phosphorous doped polycrystalline Si1xGex films. Appl Phys Lett 66:195–197, 1995. 21. PE Hellberg, A Gagnor, SL Zhang, and CS Petersson. Boron doped polycrystalline SixGe1x films: Dopant activation and solid solubility. J Electrochem Soc 144:3968, 1997. 22. B Tillack, P Zaumseil, G Morgenstern, D Kruger, B Dietrich, and G Ritter. Strain compensation in ternary Si1x yGexBy films. J Cryst Growth 157:181-184, 1995. 23. S Gannavaram and MC Ozturk. Ultra-shallow pþ–n junctions for 35–70 nm CMOS using selectively deposited very heavily boron doped silicon-germanium films. ECS Meeting Proc Abs 2000, p. 73. 24. QZ Hong, JG Zhu, and JW Mayer. Solid phase epitaxy of a Ge–Si alloy on [111] Si through a Pd2Si layer. Appl Phys Lett 55:747–749, 1989. 25. A Buxbaum, M Eizenberg, A Raizman, and F Schaffler. Interaction of Pd with strained layers Si1xGex epitaxially grown on Si(100). Jpn J Appl Phys 30:3590–3593, 1991. 26. QZ Hong and JW Mayer. Thermal reactions between Pt thin films and Si1xGex alloys. J Appl Phys 66:611–615, 1989. 27. H Kanaya, Y Cho, F Hasegawa, and E Yamaka. Preferential PtSi formation in thermal reaction between Pt and Si0.80Ge0.20 MBE layers. Jpn J Appl Phys 29:L850–L852, 1990. 28. P Zhong and Y Zheng. Study of Ge movement during thermal reactions between Pt and GeSi /Si heterostructures. Appl Phys Lett 62:3259–3261, 1993. 29. HK Liou, X Wu, U Gennser, VP Kesan, SS Iyer, KN Tu, and ES Yang. Interfacial reactions and Schottky barriers of Pt and Pd on epitaxial Si1xGex alloys. Appl Phys Lett 60:577–579, 1992. 30. H Chen, P Han, XD Huang, LQ Hu, Y Shi, and YD Zheng. Semiconducting Ge–Si–Fe alloy grown on Si(100)substrate by reactive deposition epitaxy. Appl Phys Lett 69:1912–1914, 1996. 31. JS Luo, WT Lin, CY Chang, PS Shih, and TC Chang. Pulsed KrF laser annealing of Mo/Si0.76Ge0.24. Nuclear Inst Meth Phys Res B 169:129–134, 2000. 32. V Aubry, F Meyer, R Laval, C Clerc, P Warren, and D Dutartre. Thermal stability of W on RTCVD Si1xGex films. Appl Surf Sci 73:285–289, 1993. 33. Y Yasuda, O Nakatsuka, and S Zaima. Interfacial reactions of Ti/ and Zr/Si1xGex /Si contacts with rapid thermal annealing. Thin Solid Films 373:73–78, 2000. 34. Z Wang, DB Aldrich, RJ Nemanich, and DE Sayers. Electrical and structural properties of zirconium germanosilicide formed by a bilayer solid state reaction of Zr with strained Si1xGex alloys. J Appl Phys 82:2342–2348, 1997. 35. V Aubry-Fortuna, M Barthula, JL Perrossier, F Meyer, V Demuth, HP Strunk, and O ChiaxPluchery. Contacts on Si1xyGexCy alloys: electrical properties and thermal stability. J Vac Sci Technol B 16:1659–1662, 1998. 36. V Aubry-Fortuna, A Eyal, O Chaix-Pluchery, M Barthula, F Meyer, and M Eizenberg. Thermal stability and electrical properties of Zr/Si1xyGexCy contacts after rapid thermal annealing. Appl Phys Lett 73:1248–1250, 1993. 37. V Aubry-Fortuna, G Tremblay, F Meyer, Y Miron, Y Roichman, M Eizenberg, F Fortuna, U Hormann, and H Strunk. Phase formation and strain relaxation during thermal reaction of Zr and Ti with strained Si1xyGexCy epilayers. J Appl Phys 88:1418–1423, 2000.

© 2006 by Taylor & Francis Group, LLC

2.10-184

The Silicon Heterostructure Handbook

38. V Aubry-Fortuna, O Chaix-Pluchery, F Fortuna, C Hermandez, Y Campidelli, and D Bensahel. Structural properties and stabilities of Zr and Ti germanosilicides formed by rapid thermal annealing. J Appl Phys 91:5468–5473, 2002. 39. V Aubry-Fortuna, M Barthula, F Meyer, A Eyal, C Cytermann, M Eizenberg, and O Chaix-Pluchery. Characterizations of Zr/Si1xyGexCy after rapid thermal annealing. Proc Mater Res Soc 1998, pp. 49– 53, 1998. 40. JB Lai and LJ Chen. Effects of composition on the formation temperatures and electrical resistivities of C54 titanium germanosilicide in Ti–Si1xGex systems. J Appl Phys 86:1340–1345, 1999. 41. DB Aldrich, YL Chen, DE Sayers, RJ Nemanich, SP Ashburn, and MC Ozturk. Effect of composition on phase formation and morphology in Ti–Si1xGex solid phase reactions. J Mater Res 10:2849– 2863, 1995. 42. DB Aldrich, YL Chen, DE Sayers, RJ Nemanich, SP Ashbun, and MC Ozturk. Stability of C54 titanium germanosilicide on a silicon–germanium alloy substrate. J Appl Phys 77:5107–5114, 1995. 43. Z Wang, DB Aldrich, YL Chen, DE Sayers, and RJ Nemanich. Silicide formation and stability of Ti/ SiGe and Co/SiGe. Thin Solid Films 270:555–560, 1995. 44. R Eyal, R Brener, R Beserman, M Eizenberg, Z Atzmon, DJ Smith, and JW Mayer. The effect of carbon on strain relaxation and phase formation in the Ti/Si1xyGexCy /Si contact system. Appl Phys Lett 69:64–66, 1996. 45. JC Huang, JS Luo, WT Lin, CY Chang, and PS Shih. Effects of an interposed Mo layer on the interfacial reactions of Ti/Si0.76Ge0.24 by rapid thermal annealing and pulsed laser annealing. Semicond Sci Technol 15:941–945, 2000. 46. SP Ashburn, MC Ozturk, G Harris, and DM Maher. Phase transitions during solid-phase formation of cobalt germanide by rapid thermal annealing. J Appl Phys 74:4455–4460, 1993. 47. JS Luo, WT Lin, CY Chang, WC Tsai, and SJ Wang. Interfacial reactions of the Co/Si1xGex system. Mater Chem Phys 48:140–144, 1997. 48. O Nur, M Willander, HH Radamson, MR Sardela, Jr., GV Hansson, CS Patersson, and K Maex. Strain characterization of CoSi2 /n-Si0.9Ge0.1 /p-Si heterostructures. Appl Phys Lett 64:440–442, 1994. 49. O Nur, M Willander, L Hultman, HH Radamson, GV Hansson, MR Sardela, and JE Greene. CoSi2 / Si1xGex /Si(0 0 1) heterostructures formed through different reaction routes: silicidation-induced strain relaxation, defect formation and interlayer diffusion. J Appl Phys 78:7063–7069, 1995. 50. JS Luo, YL Hang, WT Lin, CY Chang, and PS Shih. Interfacial reactions of Co/Si0.76Ge0.24 and Co(Si0.76Ge0.24)/Si0.76Ge0.24 by pulsed KrF laser annealing. J Mater Res 14:3433–3438, 1999. 51. JS Luo, WT Lin, CY Chang, PS Shih, and FM Pan. Annealing effects on the interfacial reactions of Ni on Si0.76Ge0.24 and Si1xyGexCy . J Vac Sci Technol A 18:143–148, 2000. 52. JS Luo, WT Lin, CY Chang, and WC Tsai. Pulsed KrF laser annealing of Ni/Si0.76Ge0.24 films. J Appl Phys 82:3621–3623, 1997. 53. JS Luo, WT Lin, CY Change, and WC Tsai. Interfacial reactions of Ni on Si0.76Ge0.24 and Si by pulsed laser annealing. Mater Chem Phys 54:160–163, 1998. 54. HB Zhao, KL Pey, WK Choi, S Chattopadhyay, EA Fitzgerald, DA Antoniadis, and PS Lee. Interfacial reactions of Ni on Si1xGex (x ¼ 0.2,0.3) at low temperature by rapid thermal annealing. J Appl Phys 92:214–217, 2002. 55. T Jarmar, J Seger, F Ericson, D Mangelinck, U Smith, and SL Zhang. Morphological and phase stability of nickel-germanosilicide on Si1xGex under thermal stress. J Appl Phys 92:7193–7199, 2002. 56. KL Pey, WK Choi, S Chattopadhyay, HB Zhao, EA Fitzgerald, DA Antoniadis, and PS Lee. Thermal reaction of nickel and Si0.75Ge0.25 alloy. J Vac Sci Technol A 20:1903–1910, 2002. 57. CY Lin, WJ Chen, CH Lai, A Chin, and J Liu. Formation of Ni germeno-silicide on single crystalline Si0.3Ge0.7/Si. IEEE Electron Dev Lett 23:464–466, 2002. 58. S Zaima, O Nakatsuka, A Sakai, J Murota, and Y Yasuda. Interfacial reaction and electrical properties in Ni /Si and Ni/SiGe(C) contacts. Appl Surf Sci 224:215–221, 2004.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-185

59. V Aubry, OC Pluchery, F Fortuna, C Hernandez, Y Campidelli, and D Bensahel. Structural properties and stability of Zr and Ti germanosilicides formed by rapid thermal annealing. J Appl Phys 91:5468–5473, 2002. 60. CJ Tsai and KH Yu. Stress evolution during isochronal annealing of Ni /Si system. Thin Solid Films 350:91–95, 1999. 61. SL Zhang and FM d’Heurle. Stresses from solid state reactions — a simple model silicides. Thin Solid Films 213:34–39, 1992. 62. KL Pey, S Chattopadhyay, WK Choi, Y Miron, EA Fitzgerald, DA Antoniadis, and T Osipowicz. Stability and composition of Ni-germanosilicided Si1xGex films. J Vac Sci Technol B 22:852–858, 2004. 63. D Manglelinck, JY Dia, JS Pan, and SK Lahiri. Enhancement of thermal stability of NiSi films on (100)Si and (111)Si by Pt addition. Appl Phys Lett 75:1736–1738, 1999. 64. LW Cheng, SL Cheng, LJ Chen, HC Chien, HL Lee, and FM Pan. Formation of Ni silicides on (001) Si with a thin interposing Pt layer. J Vac Sci Technol A 18:1176–1179, 2000. 65. JF Liu, HB Chen, JY Feng, and J Zhu. Improvement of the thermal stability of NiSi films by using a thin Pt interlayer. Appl Phys Lett 77:2177–2179, 2000. 66. DZ Chi, D Mangelinck, SK Lahiri, PS Lee, and KL Pey. Comparative study of current–voltage characteristics of Ni and Ni(Pt)-alloy silicided pþ/n diodes. Appl Phys Lett 78:3256–3258, 2001. 67. JF Liu, JY Feng, and J Zhu. Comparison of the thermal stability of NiSi films in Ni /Pt /(111)Si and Ni/Pt /(100)Si systems. J Appl Phys 90:745–749, 2001. 68. PS Lee, KL Pey, D Mangelinck, J Ding, DZ Chi, and L Chan. New silicidation technology with Ni(Pt) alloy for MOSFETs. IEEE Electron Dev Lett 22:568–570, 2001. 69. RA Donaton, K Maex, A Vantomme, G Langouche, Y Morciaux, AS Amour, and JC Sturm. Co silicide formation on SiGeC /Si and SiGe /Si layers. Appl Phys Lett 70:1266–1268, 1997. 70. AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.

© 2006 by Taylor & Francis Group, LLC

2.11 Selective Etching Techniques for SiGe/Si 2.11.1 2.11.2

Introduction........................................................... 2.11-187 Process Development for Industrial Applications ........................................................... 2.11-188 Equipment . Influence of the Different Parameters . Process Development . Selective Passivation of Si . Selective Passivation of SiGe . Other Solutions under Consideration

2.11.3

Introduction . Implementation of the SON Process for MOSFET . SON MOSFETs with Metal Gates . SON without Channel Rupture: ‘‘Localized SOI’’ . Implementation of the SON Process to Gate All Around (GAA) MOSFETs . Implementation to Multigate Devices . SON and Microelectromechanical Systems (MEMS)

S. Monfray and T. Skotnicki ST Microelectronics

S. Borel CEA LETI

Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology .............. 2.11-196

2.11.4

Summary ................................................................ 2.11-207

2.11.1 Introduction SiGe alloys are used extensively for their electrical properties (bandgap engineering by adjusting the Ge content, carriers mobility improvement). With the progress in deposition by epitaxial growth, a new application is emerging, based on the crystalline properties of the material. Indeed, from pure Si (x ¼ 0) to pure Ge (x ¼ 1), any Si1xGex alloy can be deposited on Si with the same crystal structure and the same lattice constant (in the growth plane) as the substrate, provided that it does not exceed the critical thickness for plastic relaxation (Ec). As a consequence, SiGe can be buried between mono-Si layers without modifying their conduction properties. This method is used in several advanced microelectronics architectures that require a thin single-crystal Si-film isolated from the substrate by a cavity: the SiGe layer is used as a sacrificial layer for lateral etching. In this approach, the selectivity is crucial because both similar materials are exposed to the complete etching process whereas only one has to be removed. The objective of this chapter is to describe here the mainstream of the selective SiGe etching and its applications. In particular, we present the Silicon-on-Nothing (SON) process and its possible technological variants within the process of simplification, and improvement of versatility and robustness. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors. 2.11-187 © 2006 by Taylor & Francis Group, LLC

2.11-188

2.11.2

The Silicon Heterostructure Handbook

Process Development for Industrial Applications

Getting some selectivity between SiGe alloys and pure Si is challenging because of the similarity between the two materials. Indeed, they have the same crystal structure (diamond), their lattice constants are not so different (<1% for Ge contents <25%) and their components (Si and Ge) are very close in terms of reactivity to halogen-based chemistries (same external electronic configuration, same kind of volatile etching products). Anyway, it is possible to discriminate between them in highly selective etching processes. In fact, there is no clear explanation about the mechanisms responsible for this selectivity. Neither the strain of SiGe deposited on Si, nor the relative strengths of Si Si and Si Ge bonds or electronic effects can explain the high etch rates (ERs) that can be obtained on SiGe as compared to that of pure Si. This section gives a way of obtaining a tunnel by lateral etching of SiGe in a Si/SiGe/Si stack. It details a tool that can be used for this purpose, its functioning, but also a process with its performances and limitations (Figure 2.11.1).

Equipment Shibaura CDE-80 is an industrial tool (Figure 2.11.2) dedicated to chemical dry etching by activated gases, i.e., by neutrals coming from a remote plasma.

SiGe

SiGe

FIGURE 2.11.1 Selective lateral etching of SiGe in a Si/SiGe/Si stack (cross section).

FIGURE 2.11.2 Schematic drawing of CDE-80 etching tool.

© 2006 by Taylor & Francis Group, LLC

2.11-189

Selective Etching Techniques for SiGe/Si

A gas mixture is injected in the etching chamber through a quartz tube (discharge tube) connected to a Teflon tube (transfer tube). The pressure of the system is regulated by an auto pressure controller connected to a dry pump. Then, a plasma is ignited in the discharge tube by using a 2.45 GHz microwave generator. The gas molecules are dissociated and ionized by energetic electrons, leading to several kinds of species. Some of these reactions are given below, as well as examples concerning CF4: .

.

Production of radicals and atoms: AB þ e ! (AB)*

(2:11:1)

CF4 þ e ! (CF4 )*

(AB)* ! A þ B

(2:11:2)

(CF4 )* ! CF3 þ F

Production of electrons and ions by dissociative ionization: AB þ e ! Aþ þ B þ 2e

(2:11:3)

CF4 þ e ! CF3 þ þ F þ 2e

A þ e ! Aþ þ 2e

(2:11:4)

CF3 þ e ! CF3 þ þ 2e

As the plasma is cold and not highly ionized (a < 104), ions and electrons are much less numerous than molecules, radicals, and atoms. Moreover, their lifetime is much shorter, so only a few of them reach the Teflon tube: .

Loss of electrons and ions: ABþ þ e ! A þ B

(2:11:5)

CF2 þ þ e ! CF þ F

Neutral species reach the transfer tube and diffuse through it to the etching chamber. They also partially recombine: .

Loss of radicals and atoms: A þ B þ M ! AB þ M

(2:11:6)

CF þ F þ CF4 ! CF2 þ CF4

As a consequence, the etching of the wafer consists of reactions between the material to etch and neutral species remaining from the discharge. It is purely chemical (no ion bombardment), that is why it is isotropic (no favored direction) and potentially selective (no sputtering). The etching is mainly driven by the composition of the gas mixture, but other parameters can be tuned in order to control it.

Influence of the Different Parameters Gas Mixture As mentioned above, this parameter is of primary importance because of the chemical nature of the process. The gases that are used must contain elements which have a spontaneous affinity for the material to etch, and they must form volatile products with it. Silicon and germanium are commonly etched with halogen-based chemistries because of the easy formation of volatile SiX4 and GeX4 (X ¼ F, Cl, Br) in reactive ion etching. In the case of chemical dry etching, there is no ion bombardment to assist the reaction, and all halogens are not of equal efficiency. Fluorine has a spontaneous action on Si or Ge, so fluorinated compounds are the basic gases for Si or SiGe isotropic etching. Other gases may be added in order to modify the level of dissociation/recombination or the passivation layers at the surface of the wafer. For example, a small amount of oxygen contributes to

© 2006 by Taylor & Francis Group, LLC

2.11-190

The Silicon Heterostructure Handbook

the dissociation of CFx by forming CO2 and atomic fluorine, but an excess of O2 leads to a passivating oxide layer that prevents the etching (Figure 2.11.3). Microwave Power The microwave power sets the level of dissociation in the plasma, i.e., the ratio between active species and inert molecules. At low power, the discharge is unstable and the dissociation is poor. The small number of active species make the etch rate quite low. By increasing the power, the production of electrons is increased so the initiation of the discharge and its stability are easier, leading to a greater dissociation (equations (2.11.1) to (2.11.4)). The amount of active species is higher and the etch rate is increased (Figure 2.11.4). Pressure Pressure determines the rate of recombinations between the different species. An increase of the pressure corresponds to a decrease of the mean free path of the species (Figure 2.11.5). They undergo more collisions and may become inert (Equations (2.11.5) and (2.11.6)). The result is a decrease of the etch rate. Temperature During the process, the quartz tube warms up because of energy dissipated by the discharge. For highpower processes, the tube temperature can exceed 1508C after a few minutes. The consequence is an

Maximum dissociation of CFx

Etch rate (mm/min)

5000

SiGe

4000 3000 2000 1000 Si

Passivating Oxide

0 0

50

100

200

300

400

500

Oxygen amount (sscm)

FIGURE 2.11.3

Effect of O2 addition into pure CF4.

SiGe etch rate (Å/min)

25000 20000 15000 10000 5000 0 200

FIGURE 2.11.4

400 600 Microwave power (W)

Effect of the microwave power on SiGe lateral etch rate.

© 2006 by Taylor & Francis Group, LLC

800

2.11-191

Selective Etching Techniques for SiGe/Si

25000 SiGe etch rate (Å/min)

20000 15000 10000 5000 0 300

600

900 Pressure (mT)

1200

1500

150

24500

100

22500 20500

50 18500

ER (Å/min)

T (˚C)

FIGURE 2.11.5 Effect of the pressure on SiGe lateral etch rate.

16500

0 0

100

200

300

400

Seasoning time (s)

FIGURE 2.11.6 Effect of a seasoning on the quartz tube temperature and on SiGe lateral etch rate.

increase of the etch rate due to more dissociation of the gas mixture. But at low power, or for short etching processes, this phenomenon is negligible (Figure 2.11.6). The temperature of the electrostatic chuck (ESC) that holds the wafer may also play an important role in the control of the reactions that take place on it. Indeed, some products are not volatile at low temperature but they can be produced, gasified, and pumped away at higher temperature (e.g., SiF4 is volatile from 868C at 1 atm). In this process, the chuck temperature is water cooled by a chiller between 58C and 258C but its modifications are not easy, so it is kept constant at 108C.

Process Development Method The process used for the realization of a tunnel in a Si/SiGe/Si stack has to etch SiGe with a high selectivity to pure Si. In other words, the ratio between the tunnel depth and the Si loss must be maximized. This ratio is considered as the most representative index for the selectivity (Figure 2.11.7): Selectivity ¼

Tunnel depth Si loss

This complex structure is essential in order to evaluate the selectivity of a lateral etching process because any simplified method would lead to fallacious results (Figure 2.11.8). Actually, both materials must be present simultaneously on the wafer and the distance between them must be as small as possible. For example, the ratio between SiGe and Si etch rate measured on two independent wafers is lower than the tunnel depth/Si loss (Td/Sl) ratio. This suggests that the presence of SiGe has an influence on Si etch rate.

© 2006 by Taylor & Francis Group, LLC

2.11-192

The Silicon Heterostructure Handbook

Ideal process

Real process

Si Nominal height

SiGe

Si loss Tunnel depth

Si

FIGURE 2.11.7 Selectivity characteristics of a tunnel etching process.

(a)

(b)

(c)

(d)

FIGURE 2.11.8 Relevance of the method used to evaluate the selectivity of a lateral etching process. (a) Two independent wafers covered with SiGe or Si; (b) SiGe and Si samples on an inert holder wafer; (c) the same SiGe and Si samples side by side; and (d) patterned wafer with Si/SiGe/Si stack.

Each tested recipe is performed in the same experimental conditions: . . . .

FH wet treatment in order to remove the native oxide on both materials Etching of a patterned wafer with Si/SiGe/Si stack (20% Ge) Stripping in a O2 plasma in order to remove the resist that protects the upper side of Si SEM cross-section observation in order to determine Td and Sl.

It is then possible to compare the values of Td/Sl or the relative positions of each recipe on the graph in Figure 2.11.9. Best Point Many gas mixtures have been tested, using CF4, CH2F2 or Cl2 as the etching gas, adding N2 or O2 in different ratios. Finally, the chemistry that gives the best results is made of pure CF4 (300 sccm). The pressure is set to the maximum value in order to minimize the etch rate (see section on ‘‘Pressure’’) and better control the process. With 300 sccm of gas, the maximum pressure that can be reached is 1500 mT. A consequence of this high pressure is a selectivity improvement, compared with lower pressure recipes. The same behavior is observed with power: at low power, the etch rate decreases (see section on ‘‘Microwave Power’’) and the selectivity between SiGe and Si is improved. A power of 200 W is applied because lower values lead to plasma instability (Table 2.11.1). Performances The graph of Figure 2.11.10, plotted after 60 sec of the process described above, shows a Td/Sl ratio around 40, which means that when a 100 nm-deep tunnel is etched in the SiGe layer, only 2.5 nm of Si are consumed beneath and underneath the entrance of the tunnel.

© 2006 by Taylor & Francis Group, LLC

2.11-193

Selective Etching Techniques for SiGe/Si

Si consumption

SI1 SI2

SI3

Td

Distance to the end of the tunnel

FIGURE 2.11.9 Comparison between different recipes, based on SEM cross-section images. Recipe 2 (dashed line) is more selective than recipe 1 (dashed–dotted line) but less than recipe 3 (dotted line).

TABLE 2.11.1

Process Parameters of the Best Point for Tunnel Etching

CF4 Flow

Pressure

MW Power

ESC Temperature

300 sccm

1500 mT

200 W

108C

Si consumption (nm)

10 8 6 4 2 0 0

50

100 150 200 250 300 Distance to the end of the tunnel (nm)

350

FIGURE 2.11.10 Characterization of the best process for tunnel etching. (a) SEM cross-section micrograph of the tunnel. (b) Si consumption all along the tunnel.

© 2006 by Taylor & Francis Group, LLC

2.11-194

The Silicon Heterostructure Handbook

The following points are to be noted. The Si loss is higher if the material is doped with arsenic. On the contrary, if it is doped with boron, the Si is almost not impacted. As and B do not need to be activated to play their role, which suggests that this phenomenon is not electron-linked. The process is sensitive to the germanium concentration in the alloy. The more Ge it contains, the faster it gets etched by fluorine atoms. A SiGe/Si multistack with Ge contents from 15% up to 30%, exposed to this process, shows the evolution of the etch rate as a function of [Ge] (Figure 2.11.11). The real structure is represented below, after 10 sec of etching. The measurement of the different etch rates may show a nonlinear relationship between [Ge] and SiGe etch rate. But insofar as all tunnels have a different depth, some additional parameters may have to be taken into account, such as the accessibility of the etching species at the end of the tunnel. Limitations As mentioned in ‘‘Method,’’ the presence of SiGe has an influence on Si etch rate since the selectivity obtained with two blanket wafers is very different from that obtained on a patterned wafer with stacked layers. This is a limitation of the process because in almost all industrial applications, it is used for a complete removal of the SiGe sacrificial layer, which means that at the end of the process, there is only silicon on the wafer. At this moment, Si starts to be etched by fluorine species and the benefit of the selectivity may be rapidly lost. The qualitative representations of Si and SiGe etch rate are given in Figure 2.11.13. They show that as long as some SiGe remains, the Si is preserved, but as soon as SiGe has been totally removed from the pattern, the Si etch rate increases.

FIGURE 2.11.11 Structure used to show the impact of the Ge content on the SiGe ER.

FIGURE 2.11.12 30%.

SEM cross-section micrograph of tunnels after etching of a SiGe/Si multistack with 15% [Ge]

© 2006 by Taylor & Francis Group, LLC

2.11-195

Selective Etching Techniques for SiGe/Si

ER

SiGe

Si No more SiGe

Etching time

FIGURE 2.11.13

Qualitative evolution of Si and SiGe etch rate during the process.

FIGURE 2.11.14

Si loss on small patterns during the etching of large patterns.

A consequence is that the process time must be adjusted in order to minimize the over-etch (necessary in case of bad uniformity of a tool). Another consequence is that large patterns and small patterns cannot be achieved at the same time because large patterns require a longer process time, during which small patterns are over-etched (Figure 2.11.14).

Selective Passivation of Si A possible way of skirting this issue could be the development of a process that passivates Si selectively to SiGe. It would offer a twofold advantage: 1. The entrance of the deep tunnels would be as high as their end (no bevel shape, good integrity of the transistor channel) 2. Small patterns could cohabit with large patterns (no boom in Si etch rate at SiGe disappearance). As silicon oxide is chlorine-resistant whereas germanium oxide is not, a process using O2 and Cl2 may etch oxidized SiGe and stop on oxidized Si.

Selective Passivation of SiGe A process using a mixture of CF4/CH2F2/N2/O2 at high pressure (1500 mT) shows a Si etch rate about 8000 A˚/min and a SiGe etch rate that cannot be measured (Figure 2.11.15). This almost infinite selectivity is due to a passivating layer on SiGe. This process enables the production of tunnels between two SiGe thin layers with no limitation of depth.

© 2006 by Taylor & Francis Group, LLC

2.11-196

The Silicon Heterostructure Handbook

FIGURE 2.11.15 Use of a Si process (infinite selectivity to SiGe) on a Si/SiGe/Si stack.

Other Solutions under Consideration Other kinds of tools, as well as wet approaches, are also tested in order to get a high selectivity between SiGe and Si, but the trends are similar to those obtained on CDE-80 equipment.

2.11.3 Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology Introduction Extremely thin (nanometric) films of monocrystalline silicon on insulator are widely recognized for their potential for end-of-roadmap CMOS transistors [1–7]. Various fabrication technologies (SIMOX, BESOI, Smart Cut, ELTRAN, ELO, etc.) have been developed permitting continuous downscaling of the Si film and the BOX, but the commercial availability of such thin films as 5–15 nm still faces problems of feasibility and dispersions. In contrast with any other SOI technology, in the SON process, the silicon film and buried insulator, both of nanometric scale, are defined by epitaxy on a bulk substrate. Therefore, the SON process opens access to extremely thin films (the silicon channel as well as the BOX) at the same time offering the thickness control as fine as the resolution of the epi process (less than 1 nm). In addition, no more than one (bulk-type) wafer is needed to fabricate the SON layers, in contrast to two wafers in wafer-bonding-type techniques. Successful and highly selective SiGe tunnel etching can be obtained by wet etching using a variety of solvents. Table 2.11.2 summarizes our own experiences with SON-tunnel wet etching. In spite of the

TABLE 2.11.2

Efficiency of SiGe Wet-Etch Solvents Measured in SON Tunnel Lengths

Solution Composition

40 ml HNO3 20 ml H2O2 5 ml HF (5%)

Etch time SON SiGe 50% SON SiGe 30%

© 2006 by Taylor & Francis Group, LLC

1 min 21 nm —

3 min 53 nm <1 nm

10 min — 10 nm

70 ml HNO3

80 ml HNO3

40 ml acetic acide 20 ml HF (5%)

40 ml H2O 10 ml HF (5%)

3 min — 30 nm

3 min — 10 nm

10 min — 70 nm

2.11-197

Selective Etching Techniques for SiGe/Si

good selectivity and etching efficiency obtained with wet-etching, in our experiments a plasma-assisted isotropic dry etching process was used in order to ensure better process reproducibility. As presented in the previous section, a well controlled and reproducible tunnel etching can also be obtained by dry etching. We have used for that a downstream plasma reactor (STRATA from GAZONICS) using NF3, He, and N2. The two important features of this reactor are that: (i) the reactive species are created by plasma and transported to the wafer where the reaction is purely chemical, (ii) the substrates are not biased that practically removes the danger of plasma damage to the wafer. The empty tunnel resulting from this selective etching is the key point for the realization of a thin single-crystal Si film isolated from the substrate by a cavity. Alternatively, we have also used the SHIBAURA reactor using a process very similar to that of STRATA except that CF4 replaces NF3. The first application of the selective SiGe etching was dedicated to the realization of notched gates [8] in order to reduce the source and drain extensions overlap and also to improve the fringing capacitances. In this way, extremely aggressive gates were fabricated within the current state of the art of lithography process, Figure 2.11.16.

Implementation of the SON Process for MOSFET The SON process is very suitable for fabricating thin-film SOI-like devices [9–15]. For this purpose, two selective epitaxial growth (SEG) steps need to be inserted into the conventional CMOS flow just after accomplishing the shallow trench isolation (STI) process. The first SEG step provides a SiGe layer, and the second a Si layer, both layers are grown selectively on active areas (Figure 2.11.17(a)). Next the process comes back to the conventional CMOS flow and runs the usual way up to the step of lowly doped drain (LDD) implants. After the first nitride spacer, a second (TEOS) sacrificial spacer is formed. Then, using the gate and spacers as masks, shallow trenches in active areas are etched to open access to the SiGe layer (Figure 2.11.17(b)) that is selectively etched out (Figure 2.11.17(c)). After this step, the gate stack (polysilicon, gate-oxide and the silicon channel) together with the adjacent spacers is hanging above an empty space — the tunnel remaining after the SiGe etch out. As schematically shown in Figure 2.11.17(d), the stability of the gate stack at this step is due to its bridging across the active area supported by the STI. The tunnel is next cleaned and its inner walls are passivated in an RTO step that is aimed at improving the interface quality. Optionally, this step can be preceded by a sacrificial oxidation aimed at smoothing and removing the inner-tunnel interface.

16 nm 79 nm

Poly-Si 17 nm

Poly-SiGe

16 nm 5 nm

FIGURE 2.11.16 etched gate.

PMOS

TEM cross section of a 16 nm gate length planar CMOS realized with a poly-SiGe selectively

© 2006 by Taylor & Francis Group, LLC

2.11-198

The Silicon Heterostructure Handbook

Si

Gate

Spacer

SiGe

Si SiGe

Si

(a) (b)

Spacer

Selective isotropic removal of SiGe

Gate

STI

Si

(d)

(c) TEOS spacer cleaning

Gate

Selective epitaxial growth

Gate S

Si

Tunnel filled with Dielectric

(e)

D

Si

RTO/HTO

Si3N4

(f)

FIGURE 2.11.17 Key steps of the basic SON process in application to CMOS flow. (a) Selective SiGe/Si epitaxy; (b) standard gate-stack integration and SD etching; (c) SD-etching for the buried SiGe layer access and selective isotropic SiGe removal; (d) after SiGe removal, all the gate stack becomes sustained over the active area; (e) tunnel filling with dielectric and Si-cleaning before selective epi-growth; (f) source and drain area becomes contacted with the conduction channel.

Next, the entire structure is recovered with the first thin layer of deposited dielectric (HTO), sufficiently thin to leave a throughway via the tunnel. The second deposited dielectric (nitride) fulfills completely the tunnel but also recovers all other parts of the structure. Thanks to the dual-dielectric structure, one can, however, etch-back the nitride (everywhere except inside the tunnel) in an anisotropic plasma etch using the HTO layer as an etch-stopper. The remaining HTO oxide is very thin and thus easy to get rid of when cleaning the S/D trenches preparing them for the SEG step. This cleaning step is selective to oxide thus preserving the nitride in the spacers and inside the tunnel. In contrast, the second TEOS spacer is etched out thus exposing the upper part of the extensions to the SEG. The more aggressive is the cleaning, the larger part of the extension is exposed to SEG (Figure 2.11.17(e)). With this double-spacer and dual-dielectric process, wide range of cleaning conditions may be used without jeopardizing either the SEG quality, or the reunification between S/D and the channel. It should be realized that the additional surface of the channel exposed to SEG thanks to the removal of the second TEOS spacer is much larger than the vertical sidewall of the channel. Thanks to this developed exposure surface, the SEG starts not only at the bottom of the S/D trenches but also directly on the exposed parts of the extensions, thus guarantying a reliable reunification (Figure 2.11.17(f)).

© 2006 by Taylor & Francis Group, LLC

2.11-199

Selective Etching Techniques for SiGe/Si

In this way, we can see Figure 2.11.18 in which SON transistors show perfect morphology. On the color map of the entire structure are presented 80 nm transistors with silicon-conduction channel as thin as 20 nm with only 20 nm of buried dielectric. For very thin-film SOI devices the concern is about the bottom interface quality and the crystallinity of the film. The high-resolution TEM cross-section (Figure 2.11.19) made on a finished extremely thin 5 nm-thick SON transistor demonstrates that the bottom interface is almost as smooth as the upper one. This is certainly thanks to the very high SiGe etching selectivity but also due to the fact that the etching is a chemical reaction rather than aggressive ion etching process. This figure also illustrates the perfect monocrystalline structure of the channel (see the lattice regularity). Another major advantage of SON devices is its compatibility with the silicidation process. In general, very thin-film SOI devices need SEG steps to allow S/D silicidation, leading to many issues: charging effects, temperature control on SOI substrates, start on amorphized areas after LDD implant, etc. In the case of SON process, thanks to the continuity between S/D area and the bulk, silicidation can occur without problems. Figure 2.11.20 and Figure 2.11.21 show examples of electrical results obtained on 80 nm NMOS transistors with 30 A˚ of physical oxide thickness and on 38 nm PMOS transistors with 20 A˚ of physical oxide thickness. Concerning the output characteristics, an improvement of as much as 30% at high voltage (Vg Vth ¼ 1.8 V) (Figure 2.11.20) and as much as 130% at low voltage (VgVth ¼ 0.6 V),

SON MOSFET

80 nm Poly Si SiO2 Si3N4

Si epi Si channel

Tunnel filled with dielectric

FIGURE 2.11.18 FIB/TEM color-map illustrating perfect SON morphology; note the uniform thickness of the buried dielectric and of the Si channel and the comfortable reunification between the channel extremities and the S/D domains.

FIGURE 2.11.19 Magnification (TEM picture) of the buried-dielectric/channel/Gate_ox/poly-gate stack for a very thin Si-film (TSi ¼ 5 nm). Note good quality of bottom and upper tunnel interfaces and perfect crystallinity of the channel.

© 2006 by Taylor & Francis Group, LLC

2.11-200

The Silicon Heterostructure Handbook

Reference SON

Bulk ref. @−12 V

450

+30%

200 + 130%

100 0 0.5

1

1.5

Vdrain (V)

FIGURE 2.11.20 Lin Id(Vd) of a 80-nm NMOS SON transistor. The drive current is improved by 30% compared to bulk reference. At low Vdd, the improvement reaches 130%.

2

350

1⫻10−4 1⫻10−5

400

300

0 Tsi = 20 nm, TOX = 30Å

1⫻10−3

500

DIBL = 60 mV

300

1⫻10−6 1⫻10−7

250

1⫻10−8

200 150

1⫻10−9

50

1⫻10−10

0 −1.4

−1

−0.6 −0.2 Vg(V)

Idrain (A/µm)

Vg-Vth 700 1.8 V 600 1.5 V 1.2 V 500 0.9 400 0.6 V

Idrain (µA/µm)

Idrain (µA/µm)

800

1⫻10−11 0.2 Tsi = 9 nm, TOX = 20 Å

FIGURE 2.11.21 Lin Id(Vg) and log-Id(Vg) of our 38 nm PMOS SON device. The architecture shows highresistive SCE properties with only 60 mV of DIBL (pockets implanted). Ioff current is only equal to 100 nA/mm.

has been measured, reflecting large improvement in transconductance (confirmed by direct measurements). 38 nm SON PMOS devices are presented with a 9-nm-thick Si-conduction channel. This architecture leads to a really SCE-resistive device, showing less than 60 mV of DIBL for such an aggressive gate length, (Figure 2.11.21). In absolute numbers, the drain current of those silicided SON pMOSFETs was measured as high as 340 mA/mm at Vg ¼ 1.4 V (with a physical oxide thickness of 20 A˚) with only 100 nA/mm Ioff, which is consistent according to the ITRS roadmap. Those performances are really competitive compared to the state of the art for such aggressive gate length, and can be improved by reducing the gate oxide thickness. In fact, for such aggressive gate length, bulk references were showing so high SCE effects that Id(Vg) characteristics demonstrate quasi-short cuts between the extensions. This point shows that the SON architecture is definitely a major advantage for the aggressive ULSI area.

SON MOSFETs with Metal Gates A major issue of very thin FD devices is that Vth decreases with the Si-film thickness (TSi), leading to intolerably high off current. The threshold voltage level of FD devices with thin films becomes consequently a serious issue that needs to be addressed. This is why metal gates may be mandatory for the end-of-the roadmap devices. The use of mid-gap gates allows Vth adjustment with lowly or undoped channels, and may be also useful for polydepletion and gate-resistance reduction. For SON application, the process of totally gates silicidation [16] can be easily applied: The process of the total gate silicidation is the following: (a) the structure is covered with metal capping and (b) RTP is performed for silicide formation down to the gate oxide (Figure 2.11.22 and Figure 2.11.23). SON architecture allows comfortable silicidation thanks to the metallurgical contact between S/D and the bulk. Figure 2.11.22 shows the implementation of the totally silicided gate process to SON devices, with reduced gate height in order to limit silicidation depth in the junctions. SON transistors were fabricated with this process and Figure 2.11.23 shows that the 800 A˚ height gates were totally transformed into CoSi2. Electrical performances are presented as illustration on 55 nm PMOS transistor with 5 nm of conduction-channel thickness on Figure 2.11.24, showing highly SCE-immune devices — only 60 mV

© 2006 by Taylor & Francis Group, LLC

2.11-201

Selective Etching Techniques for SiGe/Si

Gate CoSi2 S CoSi2

D CoSi2

SID implantation Si

FIGURE 2.11.22 Implementation of the total gate silicidation process to SON devices. SON architecture allows total gate silicidation process without creating voids in the Si-film. This is thank to the metallurgical contact between S/D and bulk.

CoSi2 Tox 2nm

Si 5nm

(a)

5 nm Si-channel

BOX 40 nm

(b)

FIGURE 2.11.23 (a) Example of SON transistor with metal gate integration. (b) Plasmon and (c) HRTEM pictures showing the thickness of the Si-channel. Measured TSi ¼ 5 nm, with perfect top and bottom interfaces.

1⫻10−3

0.0003

1⫻10−4 1⫻10−5 1⫻10−6

0.0002 0.00015

1⫻10−7 DIBL = 60m V

1⫻10−8 1⫻10−9

0.0001

0 −1.2 Vd = −0.1 −1.2 V

1⫻10−10

Ioff = 0.1nA

0.00005

−1.8

−0.4 Vg(V)

Idrain (A/µm)

Idrain (A/µm)

0.00025

1⫻10−11 1⫻10−12 0

FIGURE 2.11.24 LinId(Vg) and Iog-Id(Vg) of a 55-nm SON transistor with CoSi2 gate. Data show high SCEresistive devices (DIBL ¼ 60 mV). Due to the Vth shift induced by the mid-gap gate, Ioff is around 0.1 nA/mm. The drive current is over 250 mA/mm at Vd ¼ 1.2 V with Tox ¼ 20 A˚ and over 350 mA/mm at Vd ¼ 1.4 V.

© 2006 by Taylor & Francis Group, LLC

2.11-202

The Silicon Heterostructure Handbook

of DIBL and a subthreshold slope of 73 mV/dec — in spite of deep S/D junctions. Such results are possible only on SON thanks to its intrinsic strength for SCE/DIBL suppression. Due to the Vth adjustment with mid-gap gate (Vth ¼ 0.47 V at 0.1 V), Ioff was reduced to 0.1 nA/mm for 350 mA/ mm of drive current at 1.4 V.

SON without Channel Rupture: ‘‘Localized SOI’’ This process removes the necessity of breaking the continuity between S/D and channel and thereby also that of reunification of these two regions by SEG of silicon. The indispensable access to the SiGe is obtained at the STI edge by means of a slight de-oxidation, or by a slight Si-etching. Thanks to the very high selectivity and sensitivity of the SiGe etching process, this access is sufficient for underetching the entire active area (Figure 2.11.25). The remaining Si-cap layer is then supported by the gate stack that bridges the active area in the perpendicular direction, as in the basic SON process (Figure 2.11.17). In this process, the tunnel is fulfilled in the same time as the spacer stack is deposited (oxide and Si3N4 deposition). During the standard spacers etching step, the nitride layer is kept in the previous tunnel. This very simple process allows us localized SOI-like structures, as we can see in Figure 2.11.26 and Figure 2.11.27, leading to a new way of co-integration of such devices with bulk transistors on the same chip. On the illustration, SOI-like transistors have a silicon-conduction channel thickness of 10 nm isolated from the bulk by a 30 nm buried dielectric layer. It is worth noting that this process is totally compatible with the standard bulk CMOS process and offers new perspective for localized architecture on the chip.

Tunnel etching

Gate

STI

STI

Si-channel

Si

Buried dielectric

Gate

STI

Si-channel

STI Si

FIGURE 2.11.25 Concept of SON process without channel rupture: the buried SiGe layer is etched from STI edges and then the tunnel is fulfilled in the nitride spacers stack realization.

© 2006 by Taylor & Francis Group, LLC

2.11-203

Selective Etching Techniques for SiGe/Si

FPS− Sustained Si-areas

Empty-tunnel

FIGURE 2.11.26 Morphological demonstration of the feasibility of the SON tunnel etching via the STI edges. Active areas are sustained thanks to the gates.

<< Localized-SOI >>

gate

Tunnel filled with dielectric

FIGURE 2.11.27

gate

Si

We have formed localized SOI-like areas. TSi ¼ 10 nm and Tbox is around 30 nm.

Implementation of the SON Process to Gate All Around (GAA) MOSFETs The SON process may also be easily adapted to fabrication of double gate or gate-all-around (GAA) devices. These kind of devices are reputed for their particularly strong immunity to short-channel effects as well as for their augmented transport efficiency. The main problems remaining to be solved are related to: (i) the thickness control of the Si channel, (ii) its surface roughness, and in some realization (wafer bonding) to (iii) a misalignment between the gates. The GAA SON based process, shown in Figure 2.11.28, starts with a SEG of SiGe on STI isolated wafers. The SiGe/Si stack is next patterned by RIE into a strip expanding above the active area (future transistor channel) and overlapping on STI (future S/D). Then, the underlying SiGe is selectively etched out (Figure 2.11.29) as in the conventional SON process, and the entire bridge-like structure is recovered with dielectric (in our case thermal oxidation for ensuring gate-oxide quality). Next, the structure is recovered with poly-silicon that is patterned into a gate in a masked RIE step (Figure 2.11.30). The residuals of polysilicon remaining in the corners under the bridge are neutral for a static operation of the device but contribute to overlap capacitance, thus necessitating as tight design rules as possible to reduce the gate-topoly spacing. The structure is completed by ion-implantation of S/D junctions and extensions (optionally that of S/D after formation of spacers), silicidation and other conventional back-end steps. Note that this process presents at least three important advantages: (i) the SiGe is not subject to any thermal steps (it is etched away just after deposition and channel patterning) thus limiting the danger of relaxation, (ii) the continuity between the channel and the S/D is never broken thus removing all the troubles we had with the reunification of these regions by SEG of Si, and (iii) the S/D junctions lay on

© 2006 by Taylor & Francis Group, LLC

2.11-204

The Silicon Heterostructure Handbook

Si-conduction channel

Si-mono Si poly

Si poly SiGe Si-substrate

FIGURE 2.11.28 Epi stack: selective SiGe and nonselective Si. The channel of the GAA device is defined by photolithography and is followed by a strip patterning.

Si-conduction channel

Si-mono Si poly

Si poly

Si-substrate

FIGURE 2.11.29

Selective removal of the SiGe layer.

GATE SOURCE

DRAIN

n+

n+

Si-substrate

FIGURE 2.11.30

STI

Gate oxidation, poly-Si deposition, and gate patterning.

field oxide (STI), thus promising reduced junction capacitance and leakage. The point still to improve is that the gates are not of the same size even if they are still self-aligned, thus leading to somewhat increased overlap capacitance relevant to the bottom gate. Nonetheless, SON technological steps can be modified in order to combine the bottom gate etching and S/D epitaxy to realize self-aligned top and bottom gate, see Figure 2.11.31. Figure 2.11.32 demonstrates the feasibility of the GAA SON key steps as observed on our experimental samples. Worth noticing is that the nature of the silicon within the bridge-like structure changes from a monocrystal above the active area to polycrystal above the STI. This is not expected to be a problem as

© 2006 by Taylor & Francis Group, LLC

2.11-205

Selective Etching Techniques for SiGe/Si

S

Top gate

D

Silicide STI

FIGURE 2.11.31

Silicide Bottom gate

STI

GAA transistor with top and bottom self-aligned gates.

Silicon bridge

STI

FIGURE 2.11.32

Sustained silicon-conduction channel.

long as the effective channel region is taken in the central, monocrystalline part of the bridge. Note that the bridge-like silicon strip never communicates with the initial Si-substrate. Thanks to that, it can be doped with very high doses and comfortably annealed for efficient dopant activation, without the danger of junction diffusion as in the case of bulk devices. The last photographs (TEM) (Figure 2.11.33 and Figure 2.11.34) show a perpendicular cross-section in the central part of the bridge after reoxidation, polydeposition and gate patterning. The oxide film is pretty conformal all-around the Si strip, and the poly fills the tunnel homogeneously, without voids. Finally, the devices obtained by this process have shown exceptional performances (Figure 2.11.35), with drive current reaching 2000 mA/mm for 283 nA/mm Ioff.

Mono-Si conduction channel

Top Gate Amorphous Si Bottom Gate Gate oxide

FIGURE 2.11.33

In situ doped amorphous Si surrounding the Si-channel.

© 2006 by Taylor & Francis Group, LLC

2.11-206

The Silicon Heterostructure Handbook

Si-conduction film

Top gate

Bottom gate

FIGURE 2.11.34

Gate all around transistor after gate patterning. The measured Si-film thickness is 16 nm.

Lg = 70 nm, TOX = 2 nm, Tsi = 30 nm

Id (A/µm)

1⫻10−3 1⫻10−5

lon = 1954 µA/µm loff = 283.023 nA/µm @Vdd = 1.2 V

1⫻10−7

S = 77 mV DIBL = 70 mV

1⫻10−9 −0.5

0

0.5 Vg (V)

1

FIGURE 2.11.35 Example of Id(Vg) for a 70 nm gate length SON GAA transistor. The measured drive current is the highest ever measured on such devices.

Implementation to Multigate Devices The principle of the SON technology, which consists in a selective etching of SiGe layer, can be extended to the etching of multilayer. In this way, we can imagine structures where several empty tunnels can be performed and filled with gate oxide and poly-Si or metal gates (Figure 2.11.36 and Figure 2.11.37). This opens access to new devices with multiconduction channels, which can considerably boost the drive current for high-performance applications.

SON and Microelectromechanical Systems (MEMS) The fabrication of mono-silicon bridges can be easily adapted to electromechanical micro switch, if the flexure beam can be obtained by selective SiGe etching. This opens new possibilities for such applications, and in particular for the integration of front-end MEMS. Considering the state-of-the-art, the maximal vibration frequencies that can be obtained with flexure beam are in the range of 10 to 100 MHz. With the introduction of monocrystalline beams and very small gap between the detection electrode and the flexure beam, frequencies in the range of several GHz can be reached. The possibilities that are proposed with the SON technology in this domain are also of great interest (see Figure 2.11.38 and Figure 2.11.39).

© 2006 by Taylor & Francis Group, LLC

2.11-207

Selective Etching Techniques for SiGe/Si

FIGURE 2.11.36 Application of SON-GAA technology to multigate devices. The access to the buried SiGe multilayer is performed from the STI area.

Flexure beam

Anchor

Vdc

Vac

FIGURE 2.11.37 The empty tunnels are filled by polySi (or metal) to realize the multigate structure.

Actuation

FIGURE 2.11.38 Electromechanical micro-switch principle: the flexure beam is realized with the SON process, allowing a thin monocrystalline beam.

Mono-Si flexure beam

FIGURE 2.11.39 Example of morphological realization of a thin monocrystalline flexure beam with the SON technology.

2.11.4 Summary The selective Si/SiGe etching has been presented here and extensively detailed in chemical dry etching. This method can be used in several advanced microelectronics architectures that require a thin singlecrystal Si film isolated from the substrate by a cavity: the SiGe layer is used as a sacrificial layer for lateral etching. This approach is demonstrated as a new innovative technique, which is particularly suitable for the realization of localized SOI on bulk using the SON technology. Furthermore, the capability to perform sustained mono-Si areas over an empty cavity opens a wide range of applications for this

© 2006 by Taylor & Francis Group, LLC

2.11-208

The Silicon Heterostructure Handbook

technique, in particular for the realization of double gate devices, MEMs in nanoscale dimensions, new type of nanodetectors and sensors. In conclusion, the selective etching techniques for SiGe can be considered as a fundamental way for new and innovative approaches, demonstrating in this way a large potential for future applications.

Acknowledgments The author would like to thank P. Coronel; D. Chanemougame; D. Dutarte; A. Talbot; S. Harrison; F. Leverd for their contributions.

References 1. Wong, H.-S.P.; Frank, D.J.; Solomon, P.M. Device design considerations for double-gate, groundplane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation, IEDM Tech. Dig., pp. 407–410, 1998. 2. Schulz, T.; Rosner, W.; Risch, L.; Langmann, U. 50nm vertical sidewall transistors with high channel doping concentrations, IEDM Tech. Dig., pp. 61–64, 2000. 3. Ieong, M.; Jones, E.C.; Kanarsky, T.; Ren, Z.; Dokumaci, O.; Roy, R.A.; Shi, L.; Furukawa, T.; Taur, Y.; Miller, R.J.; Wong, H.-S.P. Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric Double-Gate/Ground plane CMOSFETs, IEDM Tech. Dig., pp. 441–444, 2001. 4. Chau, R.; Kavalieros, J.; Doyle, B.; Murthy, A.; Paulsen, N.; Lionberger, D.; Barlage, D.; Arghavani, R.; Roberds, B.; Doczy, M. A 50nm Depleted-Substrate CMOS transistor (DST), IEDM Tech. Dig., pp. 621–624, 2001. 5. Esseni, D.; Mastrapasqua, M.; Fiegna, C.; Celler, G.K.; Selmi, L.; Sangiorgi, E. An experimental study of low field electron mobility in double-gate, ultra-thin SOI MOSFETs, IEDM Tech. Dig., pp. 445–448, 2001. 6. Majima, H.; Saito, Y.; Hiramoto, T. Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs, IEDM Tech. Dig., pp. 733–736, 2001. 7. Balestra, F.; Benachir, M.; Brini, J.; Ghibaudo, G. Analytical models for subthreshold swing and threshold voltage for thin and ultra thin film SOI MOSFETs, IEEE Trans. Electron Devices, Vol. 37, no. 11, pp. 2303–2311, Nov. 1990. 8. Boeuf, F.; Skotnicki, T.; Monfray, S.; Julien, C.; Dutartre, D.; Martins, J.; Mazoyer, P.; Palla, R.; Tavel, B.; Ribot, P.; Sondergard, E.; Sanquer, A. 16 nm planar NMOSFET manufacturable within state-ofthe-art CMOS process thanks to specific design and optimization, IEDM Tech. Dig. Proc., pp. 637– 640, 2001. 9. Jurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Regolini, J.-L.; Morin, C.; Schiltz, A.; Martins, J.; Pantel, R.; Galvier, J. SON (Silicon On Nothing)—a new device architecture for the ULSI Era, Symp. VLSI Tech. Dig., pp. 29–30, 1999. 10. Monfray, S.; Skotnicki, T.; Morand, Y.; Descombes, S.; Talbot, A.; Dutartre, D.; Leverd, F.; Le Friec, Y.; Palla, R.; Pantel, R.; Haond, M.; Nier, M.-E.; Vizioz, C.; Louis, D. Highly-performant 38nm SON (Silicon-On-Nothing) P-MOSFETs with 9nm-thick channels, IEEE SOI Conference Proc., pp. 22–25, 2002. 11. Monfray, S.; Skotnicki, T.; Tavel, B.; Morand, Y.; Descombes, S.; Talbot, A.; Dutartre, D.; Jenny, C.; Mazoyer, P.; Palla, R.; Leverd, F.; Le Friec, Y.; Pantel, R.; Haond, M.; Charbuillet, C.; Vizioz, C.; Louis, D.; Buffet, N. SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) Polysilicon on 5nm-thick Si-films: the simplest way to integration of Metal Gates on thin FD channels, IEDM Tech. Dig. Proc., pp. 263–266, 2002. 12. Skotnicki, T.; Jurczak, M.; Gwoziecki, R.; Lenoble, D.; Ribot, P.; Paoli, M.; Martins, J.; Tormen, B.; Grouillet, A.; Pantel, R.; Galvier, J. Heavily doped and extremely shallow junctions on insulator—by SONCTION (SilicON Cut-off juncTION) process IEDM Tech. Dig., pp. 513–516, 1999.

© 2006 by Taylor & Francis Group, LLC

Selective Etching Techniques for SiGe/Si

2.11-209

13. Monfray, S.; Skotnicki, T.; Morand, Y.; Descombes, S.; Paoli, M.; Ribot, P.; Talbot, A.; Dutartre, D.; Leverd, F.; Lefriec, Y.; Pantel, R.; Haond, M.; Renaud, D.; Nier, M.-E.; Vizioz, C.; Louis, D. First 80nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance, IEDM Tech. Digest Proc., pp. 645–648, 2001. 14. Jurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Martins, J.; Regolini, J.L.; Dutartre, D.; Ribot, P.; Lenoble, D.; Pantel, R.; Monfray, S. SON (Silicon On Nothing)—an Innovative Process for Advanced CMOS, IEEE Trans. Electron Dev. Vol. 47, Nov. 2000, p. 2179, 2000. 15. T. Skotnicki Silicon On Nothing (SON)—a robust technological platform for ULSI area, ECS Proc., 2001–2003, p. 391. 16. Tavel, B.; Skotnicki, T.; Pares, G.; Carriere, N.; Rivoire, M.; Leverd, F.; Julien, C.; Torres, J.; Pantel, R. Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (2Ohms/square) without metal CMP nor etching, IEDM Tech. Dig., pp. 825–828, 2001.

© 2006 by Taylor & Francis Group, LLC

3 Fabrication of SiGe HBT BiCMOS Technology 3.1

Overview: Fabrication of SiGe HBT BiCMOS Technology J.D. Cressler............ 3.1-213

3.2

Device Structures and BiCMOS Integration Issues D.L. Harame ...................... 3.2-215 Introduction . Types of HBT Structures . BiCMOS Integration Flows . Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes) . Advanced HBT Structures and Scaling Limits . Summary

3.3

SiGe HBTs on CMOS-Compatible SOI J. Cai and T.H. Ning .............................. 3.3-233 The SOI Advantage . Vertical Bipolar Transistors on Thin SOI . Voltage Pinning in a Fully Depleted Collector . Making SiGe HBTs on Thin SOI Substrate . Characteristics of SOI SiGe HBTs . Process Optimization, Device Scaling, and Complimentary Bipolar . Summary

3.4

Passive Components J.N. Burghartz ........................................................................ 3.4-249 Introduction . Resistors and Capacitors . Inductors and Transformers . Transmission Lines . Diodes and Switches . Special Passive Components . Summary

3.5

Industry Examples at State-of-the-Art: IBM A.J. Joseph and J.S. Dunn ............. 3.5-265 Introduction . BiCMOS Process Integration . The SiGe HBT — Key Technology Elements . Electrical Performance . Manufacturability . Summary

3.6

Industry Examples at State-of-the-Art: Jazz P.H.G. Kempf.................................. 3.6-283 Introduction . SiGe Bipolar Transistor . SiGe BiCMOS Process Integration . Process Customization . Summary

3.7

Industry Examples at State-of-the-Art: Hitachi K. Washio.................................. 3.7-295 Introduction . SiGe HBT Technologies . SiGe BiCMOS Technologies . Interconnection and Passive Elements . Summary

3.1-211 © 2006 by Taylor & Francis Group, LLC

3.1-212

The Silicon Heterostructure Handbook

3.8

Industry Examples at State-of-the-Art: Infineon T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck ...................................................... 3.8-307 Introduction . Process Concept . Transistor Fabrication Process . Transistor Results . Additional Devices . Circuit Performance

3.9

Industry Examples at State-of-the-Art: IHP D. Knoll ........................................ 3.9-321 Introduction . History of IHP’s SiGe and SiGe:C HBT Technologies . High-Performance SiGe:C BiCMOS Processes . High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology . Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) . Circuit Applications of IHP’s SiGe:C Technologies . Summary

3.10

Industry Examples at State-of-the-Art: ST A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy ............................................ 3.10-343 Introduction . Device Structures . Doping and Impurity Profiles . BiCMOS Integration Issues . High-Frequency Characteristics . Outlook for the Future

3.11

Industry Examples at State-of-the-Art: TI B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda........................................... 3.11-357 Introduction . Process Integration . Components and their Characteristics . Circuit Application . Summary

3.12

Industry Examples at State-of-the-Art: Philips R. Colclaser and P. Deixler....................................................................................... 3.12-371 Introduction . Historical Background . SiGe in Manufacturing — QUBiC4G . Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X . Summary

© 2006 by Taylor & Francis Group, LLC

3.1 Overview: Fabrication of SiGe HBT BiCMOS Technology

John D. Cressler Georgia Institute of Technology

SiGe HBT BiCMOS technology is the obvious groundbreaker of the Si heterostructures application space and numerous commercial products exist around the world. At present count there are 25 þ SiGe HBT industrial fabrication facilities on line in 2005, and growing steadily. In fact, virtually every major player in the communications electronics market either (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers. Clearly this field is maturing rapidly. Key to this success lies in the successful integration of the SiGe HBT and Si CMOS, with no loss of performance from either device. Chapter 3.2, ‘‘Device Structures and BiCMOS Integration Issues,’’ by D. Harame of IBM Microelectronics, discusses the various nuances of integration of HBTs with CMOS in SiGe fabrication. A recent demonstration of integrating a vertical SiGe HBT on thin film, CMOScompatible SOI substrates has generated considerable interest and is addressed in Chapter 3.3, ‘‘Fabricating SiGe HBTs on CMOS-Compatible SOI,’’ by J. Cai of IBM Research. For mixed-signal circuit applications of SiGe technology, the performance of integrated passive components is often just as important for circuit designers as the transistors, and significant strides have been made in the improvement of passives (and the requisite compact models for them) in recent years, and is reviewed in Chapter 3.4, ‘‘Passive Components,’’ by J.N. Burghartz of Delft University. A novel aspect of this handbook is that it contains numerous ‘‘snapshot’’ views of the industrial ‘‘state-of-the-art’’ for SiGe HBT BiCMOS technology, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global industry. These technology snapshots feature all the leaders of SiGe HBT BiCMOS field, including: Chapter 3.5, ‘‘Industry Examples at State-of-the-Art: IBM,’’ by A. Joseph of IBM; Chapter 3.6, ‘‘Industry Examples at State-of-the-Art: Jazz,’’ by P. Kempf of Jazz Semiconductor; Chapter 3.7, ‘‘Industry Examples at State-of-the-Art: Hitachi,’’ by K. Washio of Hitachi; Chapter 3.8, ‘‘Industry Examples at State-of-the-Art: Infineon,’’ by T. Meister of Infineon; Chapter 3.9, ‘‘Industry Examples at State-of-the-Art: IHP,’’ by D. Knoll of IHP; Chapter 3.10, ‘‘Industry Examples at State-of-the-Art: ST Microelectronics,’’ by A. Chantre of ST Microelectronics; Chapter 3.11, ‘‘Industry Examples at State-of-the-Art: Texas Instruments,’’ by B. El-Kareh of Texas Instruments; and Chapter 3.12, ‘‘Industry Examples at State-of-the-Art: Philips,’’ by R. Colclaser of Philips. In addition to this copious material, and the numerous references contained in each chapter, a number of review articles and books detailing SiGe HBT BiCMOS technology exist, including Refs. [1–11]. 3.1-213 © 2006 by Taylor & Francis Group, LLC

3.1-214

The Silicon Heterostructure Handbook

References 1. JD Cressler, DL Harame, JH Comfort, JMC Stork, BS Meyerson, and TE Tice. Silicon–germanium heterojunction bipolar technology: the next leap in silicon? Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 1994, pp. 24–27. 2. JD Cressler. Re-engineering silicon: Si–Ge heterojunction bipolar technology. IEEE Spectrum 49–55, 1995. 3. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Transactions on Electron Devices 40:455–468, 1995. 4. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Transactions on Electron Devices 40:469–482, 1995. 5. DL Harame. High-performance BiCMOS process integration: trends, issues, and future directions. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1997, pp. 36–43. 6. HJ Osten, D Knoll, B Heinemann, H Rucker, and B Tillack. Carbon-doped SiGe heterojunction bipolar transistors for high-frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 109–116. 7. BS Meyerson. Silicon:germanium-based mixed-signal technology for optimization of wired and wireless telecommunications. IBM Journal of Research and Development 44:391–407, 2000. 8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. R Singh, DL Harame, and MM Oprysko. Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

© 2006 by Taylor & Francis Group, LLC

3.2 Device Structures and BiCMOS Integration 3.2.1 3.2.2

Introduction............................................................... 3.2-215 Types of HBT Structures .......................................... 3.2-215 Bipolar Structure Process Feature Tradeoffs . Bipolar Structure Examples

3.2.3 3.2.4 3.2.5

BiCMOS Integration Flows ...................................... 3.2-223 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes)...................... 3.2-225 Advanced HBT Structures and Scaling Limits ....... 3.2-225

3.2.6

Summary .................................................................... 3.2-229

David L. Harame IBM Microelectronics

THz Performance Possibilities

3.2.1 Introduction SiGe heterojunction bipolar transistors now have performance that rivals the III–Vs and in many cases is superior to them. This technology has grown to be a pervasive technology found in many products, not solely because of the performance, but primarily because it is realized as a BiCMOS technology such that very highly integrated product designs are possible by leveraging a base CMOS technology, which already has existing libraries and intellectual property (IP). Additionally, passives and extensive RF– analog enablement are also added to make custom designs possible that can be merged with the highly integrated digital CMOS section. This combination of the performance of the HBT with all the large digital integration capability is based on having the HBT structure and process fully integrated into the base CMOS process such that it guarantees the compatibility of the HBT and CMOS. This will be the central theme of this section on device structures and BiCMOS integration. The structures will always be seen as within the context of a BiCMOS process. This chapter will begin with a review of the structures that are used in SiGe heterojunction bipolar transistors broadly breaking them up into different types. This will include an extensive section on transistor features, which will emphasize that what the final device looks like is a combination of the bipolar structure and the intended applications. It will then review BiCMOS integration flows followed by a section on the issues in integrating SiGe HBTs into advanced CMOS processes. The chapter will conclude by looking at the performance limits and what very advanced HBT structures might look like.

3.2.2 Types of HBT Structures Bipolar transistor structures can be roughly divided into non-self-aligned and self-aligned structures. A self-aligned transistor structure implies that the extrinsic base region is self-aligned to the emitter opening during the bipolar structure’s fabrication process. Note that this is a fairly limited definition, albeit an important one, considering all of the parts of the final transistor structure. Self-alignment is accomplished by the formation of an outer or inner sidewall, which enables us to make a second broad 3.2-215 © 2006 by Taylor & Francis Group, LLC

3.2-216

The Silicon Heterostructure Handbook

division of structures. Non-self-aligned structures imply that a lithographic alignment tolerance is used for the alignment as opposed to a processing feature during the formation of the structure. Another broad classification seeks to break structures into a combined performance and cost division. This division classes structures into high performance (HP) versus cost performance (CP). The concept is that for the HP set of applications, performance is everything and time to market is critical, making the cost considerations secondary. In contrast, the CP set of applications are commodity cost-sensitive applications where cost is everything and the required peak performance levels are significantly reduced. The CP applications will typically use older lithography generations. Of course, the HP and CP division is much more ambiguously defined when it comes to particular processes, since the features in a process flow are determined by the intended application that may be a mix of requirements. Nevertheless, it is interesting to understand the features and their tradeoffs while arbitrarily assigning them a HP or a CP classification. After the features are discussed, in light of either a HP or CP element, several example NSA and SA processes will be discussed in detail.

Bipolar Structure Process Feature Tradeoffs Some examples of the more typical features and tradeoffs are listed in Table 3.2.1 and several of these examples will be discussed in some detail here, with others addressed throughout this chapter. Issues and limitations of the different features will be discussed in this section. Selection of the starting wafer is a tradeoff. Substrate resistivity has a large impact on microstrip lines and inductors as described in detail by Long and Copeland [1]. Silicon transitions through skin effect, to slow wave, to quasi-TEM propagation modes as the resistivity is changed from low (0.01 ohm-cm) to high ( 50 ohm-cm) resistivity material as shown in Figure 3.2.1. Inductors fabricated on higher resistivity material have higher inductor Q values because of less power dissipation in the substrate [1]. However, high-resistivity wafers may be more susceptible to processing issues (warping during high-thermal steps) and the CMOS may

TABLE 3.2.1 Structural Processing Features of SiGe Heterojunction Bipolar Transistors Process Feature

High Performance

Cost Performance

Wafer Subcollector

High resistivity Nþ subcollector implant followed by n-epitaxy growth. Lowest sheet resistance Deep trench. Best isolation

Same as base CMOS Implanted subcollector without n-epitaxy. Lower cost but higher sheet resistance Junction isolation. Larger transistor layout, less isolation Same as CMOS No additional layers added to the process. Must address all etch steps to not damage the NPN region Nonselective. Structure dependent. Simpler

Transistor isolation Shallow trench NPN protection layer

Epitaxy

Extrinsic base

Same as CMOS Additional layer designed to protect the NPN region during CMOS processing and prior to epi-base. Increases process margin Selective. Structure dependent. Requires close attention to process to maintain high selectivity. Susceptible to nonuniform growth in different areas and density regions Raised extrinsic base. Less like a CMOS transistor. Requires more special steps. Higher performance

Polyemitter

In situ doped. More complex. Fewer small emitter structure issues

Contacts

Separate emitter contact. Structure dependent to make it less susceptible to height differences.

Features are categorized as a high-performance or cost-performance feature.

© 2006 by Taylor & Francis Group, LLC

Implanted extrinsic base. Can be SA or NSA processes. Simplest approach but results in a deeper extrinsic base Implanted emitter. Simpler. May be susceptible to small emitter nonuniform dopant distribution issues CMOS contact. Simpler. With topography differences with CMOS less process margin

3.2-217

Device Structures and BiCMOS Integration

Metal SiO2

1011 SKIN EFFECT

Si

QUASI-TEM

1010

Frequency, in Hz

Electric field distribution

Ground plane Quasi-TEM mode

Digital CMOS

tsi = 350 µm tox = 5 µm

Si bipolar and RF CMOS

tsi = 350 µm tOX = 2 µm

109

tsi = 200 µm tOX = 5 µm 108

Slow-wave

Slow-wave mode 107 10−2

Skin-effect mode

10−1

100

101

102

Silicon resistivity, in Ω-cm

103

Frequency-resistivity mode chart for parallel plate waveguide

FIGURE 3.2.1 Propagation modes in silicon as a function of silicon resistivity and frequency. (J.R. Long, personal communication.)

have significant deltas from the base CMOS latch-up and ESD specifications. A more conservative flow is to select the starting wafer resistivity to be compatible with the base CMOS process or just slightly higher with a typical number around 10 ohm-cm. The formation of the subcollector involves another tradeoff. For the lowest subcollector resistance, a low resistivity buried subcollector is desirable. In this process a high-dose arsenic implant is followed by a long thermal cycle in an oxidizing ambient to drive the arsenic diffusion deep into the wafer and anneal out defects, which is then followed by a thin n-epitaxy layer grown at high temperatures. A buried subcollector process can achieve sheet resistances below 10 ohm/sq. The alternative process is to simply implant the subcollector more like a well implant in CMOS. This has the advantage that it is simpler and allows the starting wafer to be fully compatible with the CMOS process as opposed to adding the n-epitaxy layer to the CMOS regions. The disadvantage is that to avoid defects, the dose and depth of the subcollector implant is significantly less than that of a buried subcollector so that the sheet resistance may be as much as ten times higher than that for a buried subcollector. Reducing sheet resistance and defect density remains a concern for CP sub-collector processes. Transistor isolation is another process feature that is a tradeoff. The best isolation is created by a deep trench (6.0 mm), which is filled with a thick oxide liner and undoped polysilicon. The transistor-totransistor breakdown voltage may easily exceed 50 V. A simpler process is to use junction isolation taking advantage of other implants in the process. The interesting aspect is that it uses no additional steps but the drawback is much reduced isolation voltages and significantly larger transistor-to-transistor spacing is required. In designs with reduced bipolar transistor count density may not be an important issue and the junction isolation may easily provide adequate isolation. The combination of a deep trench and a buried sub-collector leads to reduced collector capacitance (CSC) and collector resistance (RC) parasitics and therefore the highest fT and fMAX values. The next feature is the NPN protection layer which is a layer used in the Base-after-Gate (BaG) integration flow [2] to protect the NPN regions from CMOS processing damage (Figure 3.2.2). This flow will be discussed in a later section of this article but for the moment all that is needed to know is that after the gate polysilicon is etched away from the active NPN area, the SiGe base is grown over that region of silicon. In modern CMOS processes, the gate oxide continues to shrink and is now on the order of 2.0 nm in 90 nm CMOS. The polysilicon gate etch must stop on that thin layer, but with thin gate oxides the silicon is often damaged. In a CMOS process this region will become heavily doped and

© 2006 by Taylor & Francis Group, LLC

3.2-218

The Silicon Heterostructure Handbook

Bipolar before CMOS (base before gate)

Bipolar after CMOS (base after gate)

Isolation

Isolation

Bipolar

CMOS

CMOS

Bipolar

Contacts and interconnects

Contacts and interconnects

Bipolar during CMOS (base during gate) Isolation

Bipolar and CMOS

Contacts and interconnects

FIGURE 3.2.2 Three simple BiCMOS process flows.

silicides formed so that the condition of the silicon surface is not such an issue. However, in a HBT process in which the intrinsic base is grown over that region, any damage in the underlying silicon will result in defects during epi growth and subsequent poor SiGe HBT yield. This damage can be prevented by adding a dielectric layer to protect the region during the gate etch. The use of this layer is based on a decision to select a larger process margin for a noncritical additional processing step, but it will add additional steps to the process. The next process feature is the SiGe epitaxy process used to grow the base layer. The three most commonly used techniques available to grow the SiGe base layer are MBE, UHV/CVD [3, 4], and APCVD or RPCVD [5, 6]. MBE [7] was used initially but is no longer used in production so we will not focus on it here. The fundamental problem in SiGe epitaxy is the removal of the native oxide layer and each of these three techniques addresses this in different ways. In UHV/CVD epitaxy prior to epitaxial deposition, the wafer is exposed to a HF treatment which removes all of the native oxide and forms a hydrogen-passivated layer that is maintained throughout the epitaxial growth. In APVCVD or RPCVD, the wafer is baked at a high temperature in the presence of a hydrogen flow, which desorbs the oxide layer. Selective deposition is possible with both AP or RPCVD [6] and UHVCVD but UHVCVD is usually used as a nonselective process. A concern with AP or RPCVD selective growth is the sensitivity to local pattern (area) densities, which can affect the growth rate by as much as 50% depending on the conditions [8]. All CVD techniques are capable of in situ doping using phosphorus for n-dopants and boron for p-dopants (boron) and incorporating Ge and carbon [9]. A detailed comparison between UHV/CVD and AP or RPCVD may be found in Ref. [10]. Another interesting feature is that of raised extrinsic base versus a simpler nonraised extrinsic base. A raised extrinsic base is a processing feature that requires a separate deposition of heavily doped material either before or after the intrinsic base layer is formed. The idea was advanced early in the development of epitaxial base development [11–13], and one might also argue that it is a part of the selective epitaxial base structure, which we will go over in detail. The advantages are lower base–collector capacitance and base resistance but at a cost of more complexity than a simple planar ion-implanted extrinsic base structure. This completes the review of features and tradeoffs commonly used in bipolar structures. In the next section we will explore three bipolar structures illustrating the use of these features.

Bipolar Structure Examples This section will focus on three structural examples, which will describe the three basic classes of structures: (1) non-self-aligned epitaxial base transistor, (2) self-aligned epitaxial base transistor with an inner sidewall, and (3) self-aligned using an outside sidewall. We will then look at the impact of advanced CMOS structures and the impact on BiCMOS integration and conclude with a section on advanced bipolar structures within the context of the new CMOS processes.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-219

Non-Self-Aligned Bipolar Transistor Structure This structure is the simplest epitaxial base bipolar structure and usually simpler processes are most widely used. It is often referred to as a quasi-self-aligned transistor structure and is essentially the same structure that has been used widely in implanted base BiCMOS integration processes [14]. An SEM of the structure to be built through a series of cross sections is shown in Figure 3.2.3. The process begins with the formation of the buried layer into a CMOS compatible P substrate by patterning an arsenic implant (Figure 3.2.4(a)). The buried layer implant is followed by a high-temperature anneal in an oxidizing implant to drive the implant deep into the silicon and consume the damaged silicon layer. This is followed by the growth of a very lightly doped n-epitaxial layer, which is traditionally grown at high temperature (Figure 3.2.4(b)). The base CMOS process now begins with the formation of shallow trench by depositing a nitride layer, patterning and etching the nitride and silicon (Figure 3.2.4(c)), followed by a deposition of oxide and planarization (Figure 3.2.4(d)) and subsequent nitride strip. The shallow trench is followed by the ‘‘reach-thru’’ implant, which is a high-dose implant to form a low-resistance-doped region contacting the buried layer from the surface (Figure 3.2.4(e)). Typically this is a high-dose phosphorus implant, which is able to diffuse down to the buried arsenic layer under a moderate heat cycle. This example process has a BaG integration and benefits from the formation of a protect layer. The protect dielectric layer is deposited, patterned, and etched everywhere but over the regions where high-quality single intrinsic base growth is required (Figure 3.2.4(f)). After the CMOS structural process is completed a patterning and etch step remove the bipolar protect layer from the active base region and this same step may serve as an implant block mask for a collector implant to save a masking level (Figure 3.2.4(g)). In the next step the nonselective intrinsic in situ doped SiGe(C) layer is grown (Figure 3.2.4(h)). Single crystal material is grown in the region of exposed silicon and polysilicon over any regions where dielectrics are exposed. The polysilicon growth outside the active region serves as a landing pad for the metal contacts as can be seen in the SEM micrograph in Figure 3.2.3. A high-quality emitter base dielectric is formed by oxidation, which is followed by the deposition of thicker dielectrics. The emitter opening is formed by a patterning and etch step (Figure 3.2.4(i)). The alignment is to the shallow trench level. Next, the emitter polysilicon is deposited, doped, capped with a dielectric layer, patterned and etched (Figure 3.2.4(j)). The alignment of the level is also to the shallow trench level, which makes the alignment second order with respect to the emitter opening. The three sigma total overlay we must allow for is given by OLTotal ¼ WC þ

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ TOL2NP þ TOL2EM þ TOL2NP-ST þ TOL2EM-ST

(3:2:1)

where WC is the worst case overlay of NP-EM allowed by the process, OL are overlays and TOL are tolerances of the process. The extrinsic base is then implanted using the emitter polylayer as a mask for

FIGURE 3.2.3

SEM micrograph of a non-self-aligned SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

3.2-220

(a) Implant subcollector

The Silicon Heterostructure Handbook

(h) After LTE EPI and base dielectric deposition Oxide

(b) Grow n- collector epitaxial layer (i) Define emitter

(c) Define and etch shallow trench

(j) Etch NPN emitter poly and emitter films

(d) After trench planarization and pad nitride strip

(e) Implant NPN reachthrough

(k) Implant extrinsic base

(f) Pattern and etch NPN protect film

(l) Etch NPN base poly

(g) Etch base opening; implant deep pedestal

(m) After TiSix Formation

FIGURE 3.2.4 Fabrication sequence of a simple NSA epitaxial base transistor broken in 13 steps.

© 2006 by Taylor & Francis Group, LLC

3.2-221

Device Structures and BiCMOS Integration

the extrinsic base implant (Figure 3.2.4(k)). The extrinsic base layer is then patterned and etched (Figure 3.2.4(l)). A dielectric deposition and etch forms a sidewall on both the emitter polysilicon and the base polysilicon layer. CMOS implants, an RTA anneal, and Ti silicide formation complete the front end of the line process. Self-Aligned Bipolar Transistor Structure with an Inner Sidewall One of the most common implanted structures used in bipolar technology is the double polysilicon self-aligned (DPSA) implanted transistor structure [15] shown in Figure 3.2.5. This transistor structure has been successfully integrated into many production BiCMOS integration flows. The major drawback of the DPSA structure was the difficulty in maintaining a narrow base with an implanted base process. A suggested process improvement was to incorporate an epitaxial base in place of the implanted base process. The most straightforward way to do this was to substitute an epitaxial growth for the intrinsic base implant just prior to formation of the inner sidewall. A two-step sequence using the same basic structure as the double polysilicon structure is shown in Figure 3.2.6(a) and (b) [16]. This approach was successful in achieving a narrower heavily doped base than an implanted base process, but required higher thermal cycles for the preclean and growth with diffused base limiting the scalabilty of the method. With time, this general approach was significantly improved by adding a pad oxide under the extrinsic base and incorporating a selective SiGe base. The process steps are

Inner sidewalls

P+ polysilicon P+ I/I Intrinsic base

FIGURE 3.2.5

Double polysilicon self-aligned transistor structure.

Selectively grown epitaxial base Dielectric P+ polysilicon P+ ST (a) DPSA after epi base Inner sidewalls

Selectively grown epitaxial base

Dielectric P+ Polysilicon P+ ST Deposited + diffused intrinsic base (b) DPSA after sidewall

FIGURE 3.2.6

Double polysilicon with epitaxial base.

© 2006 by Taylor & Francis Group, LLC

3.2-222

The Silicon Heterostructure Handbook

Dielectric

Pad dielectric

P+ polysilicon Dielectric

ST (a) DPSA with Pad oxide Inner sidewalls

Pad dielectric after HF dip

Dielectric P+ polysilicon Dielectric

ST (b) After SW and HF dip Selective SiGe epitaxial base Dielectric

Voids

P+ polysilicon

ST (c) After selective SiGe epitaxial growth

FIGURE 3.2.7 DPSA with pad oxide and selective SiGe epitaxial base deposition.

shown in Figure 3.2.7(a)–(c). Note that the pad oxide lies under the extrinsic base doped polysilicon, preventing the diffusion of the extrinsic base during the epitaxial base prebake and it restricts the area so that the base–collector capacitance is significantly reduced. A disadvantage of this structure is that the HF dip contributes some variability to the underlap under the Pþ polysilicon — therefore variability in the base resistance, and the structure has significant topography so its narrow emitter effects are a concern. The selective SiGe epitaxial growth is subject to area and local pattern densityloading effects, which can significantly change local growth rate (as much as 50% depending on the conditions) and the wafer emissivity (important for lamp-heated selective SiGe reactors) is dependent on the mask pattern. In spite of these difficulties, the structure does optimize fMAX effectively by greatly decreasing CBC. Self-Aligned Bipolar Transistor Structure with an Outer Sidewall An alternative family of structures to those with an inner sidewall, are those which form the extrinsic base by the use of an outer sidewall on a sacrificial structure (referred to as a pedestal). An advantage of these structures is that the growth and deposition are nonselective and the structures have low topography, the two properties which help with manufacturing control. A process for such a bipolar structure is shown in Figure 3.2.8(a)–(g) [17, 18]. A key aspect of the process is the formation of a pedestal of sacrificial material on which sidewalls are formed to self align the extrinsic base to the emitter opening. The process begins after the nonselective in situ doped SiGe(C) base is grown. A series of films are deposited (Figure 3.2.8(a)) and the top two layers are patterned and etched to form a ‘‘sacrificial pedestal’’ (Figure 3.2.8(b)). A dielectric sidewall is formed on the ‘‘sacrificial pedestal’’ (Figure 3.2.8(c)) and the extrinsic base is implanted (Figure 3.2.8(d)) through the remaining films except where the ‘‘pedestal’’ and sidewall block the implant. The dielectrics are removed leaving

© 2006 by Taylor & Francis Group, LLC

3.2-223

Device Structures and BiCMOS Integration

only the patterned pad nitride and the polysilicon layer exposed on the surface of the wafer. Next, the polysilicon is oxidized everywhere except under the pad nitride. The oxidation of polysilicon is pinned near the LOCOS (Figure 3.2.8(e)) nitride edge due to large compressive stress during field oxidation. The mechanism is the same as that in the well-understood poly-buffered-LOCOS (PBL) approach to forming a field oxide [19]. Next, the PBL nitride pad and underlying polysilicon are stripped and the remaining dielectric etched (Figure 3.2.8(f)) followed by the deposition, doping, patterning, and etching of the emitter polysilicon (Figure 3.2.8(g)). This completes the bipolar process-specific portion of the fabrication sequence, silicidation of the extrinsic base polysilicon and collector contact and contacts using the CMOS portions of the process. An SEM of a 0.18 mm SiGe HBT fabricated with this process is shown in Figure 3.2.9 [20].

3.2.3 BiCMOS Integration Flows The previous section gave a detailed process description of three different bipolar structures. Each of these structures can be fabricated together with CMOS in a BiCMOS process. The objective of BiCMOS process integration is to create a final process with CMOS characteristics unchanged from the original CMOS only process and bipolar performance matching the bipolar only process. BiCMOS process integration flows separate out into three cases, which are shown in Figure 3.2.2. The first process flow is that of base-beforegate (BbG). In this case, the bipolar is structurally formed completely before the CMOS and then covered up or protected during the CMOS processing. The disadvantage of this flow is that the thermal cycles of CMOS are much higher than the bipolar and therefore would tend to diffuse and widen the intrinsic base profile. The second technique is Base after Gate (BaG) [2]. In this approach the CMOS is completely

Dielectric

Polysilicon

Nitride

Dielectric

Nonselective SiGe epitaxial base

ST

(a) Nonselective SiGe epitaxial base and layer depositions Polysilicon

Dielectric Nitride

Patterned and etched sacrificial-emitter-pedestal

Nonselective SiGe base

ST (b) Pattern and etch a sacrificial-emitter-pedestal using the top two layers Outer sidewalls

Nonselective SiGe base

ST (c) Deposit dielectric and etch back to form an outer sidewall on the sacrificial-emitter-pedestal

FIGURE 3.2.8 Self-aligned SiGe epitaxial base bipolar structure using an outer sidewall to self-align the extrinsic base. (Continued)

© 2006 by Taylor & Francis Group, LLC

3.2-224

The Silicon Heterostructure Handbook

Extrinsic base implant

Nonselective SiGe base

P+

P+ ST

(d) Extrinsic implant using boron which is self aligned to the emitter opening by the outer sidewall Oxide Nonselective SiGe base

P+

P+ ST

(e) Oxidation of the sacrificial polysilicon layer exposed in the field area but not underneath the nitride using the LOCOS effect, i.e., the polysilicon underneath the pad nitride is not oxidized Emitter Opening Nonselective SiGe base

P+

P+ ST

(f) Uncover emitter opening by selective removal of the nitride, polysilicon, and finally bottom dielectric layer. Note P+ implant is self-aligned to the emitter opening Emitter Polysilicon N+ Nonselective SiGe base

P+

P+ ST

(g) Emitter-polysilicon deposition, doping, and patterning. Note that with lower topography there is reduced narrow emitter effects.

FIGURE 3.2.8 (Continued )

Collector

Base

Emitter SiGe Base

N+ subcollector

FIGURE 3.2.9 SEM micrograph of a 0.18 mm SiGe BiCMOS HBT.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-225

formed and then covered up for protection during the bipolar processing and therefore the higher thermal cycles of the CMOS are completed prior to the deposition of the intrinsic base and the formation of the bipolar structure. This is the dominant integration technique in modern BiCMOS technologies. The last integration flow is base during gate. In this approach the bipolar and CMOS layers and thermal cycles are shared [17, 18]. This approach was practiced in the 0.5 mm lithographic generation [21] but as CMOS became more complex there was a need to decouple the thermal cycles.

3.2.4 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes) There are many challenges in integrating a SiGe HBT into an advanced CMOS process and this section will discuss some of these after first reviewing some key aspects about advanced CMOS processes. To improve the performance of CMOS generation to generation a selective scaling methodology is used. In selective scaling, the gate length is aggressively scaled with reduced scaling of the oxide thickness and power supply voltage [22]. However, in 65 nm and beyond even selective scaling is challenged as standby power and dynamic power become equivalent and FET performance is not dramatically increasing. The new approach requires a combination of material and structural innovation as well as a scaling algorithm. These innovations have led to the introduction of strain to increase electron and hole mobilities [23–25] and novel structures like FINFETS [26]. Both strain and structural innovations (e.g. FINFETS) have been implemented on SOI and in bulk silicon. The incorporation of one or more of these approaches in a BiCMOS process will complicate integration of the SiGe HBT and modify the SiGe HBT device performance. Two commonly used approaches to introduce strain to improve FET mobility are SiGe buffer layers and post-FET structure film depositions. Buffer layers will have a drastic effect on process integration with CMOS [27], especially if the bipolar is fabricated in these strained Si and relaxed Si1x Gex layers. Given the high defect densities that currently exist in these films, there will be a major impact on transistor yield. There are limited available publications on this interesting question so it is bound to be a major research topic in the future. Less drastic process alternatives to introduce strain is through the use of a tensile nitride deposition after the completion of the front-end processing and just prior to interconnect formation [25]. Liu has published the effects of compressive and tensile strain (0.28%) on SiGe HBT and Si BJT controls. Compressive strain showed an increase in IC and current gain (þ4%) while tensile strain showed a decrease (4% to 6%) in IC and current gain [28] although this has not been studied in depth. The effects were indeed found to be minor for DC characteristics. Additionally, FinFETs and double-gate structures introduce a novel way to fabricate CMOS devices, which may well be used in future CMOS technologies. In a BaG BiCMOS integration flow FINFET processes will probably not have an impact on the Bipolar formation as far as thermal cycles are concerned, but may introduce integration difficulties due to the extreme topography of these structures. SOI technology has also emerged as an important technology for high-speed processing and it is interesting to see the possibilities of integrating HBTs with SOI. Most approaches to integrate bipolar with the SOI have centered on creating lateral [29, 30] or novel vertical bipolar structures to take advantage of the SOI technology features or more conservative approaches, which utilized thicker silicon on SOI than is available in conventional logic SOI technologies [31]. Cai successfully integrated a SiGe HBT on SOI [32] and achieved an fT and fMAX of 70 GHz at a 20 V substrate bias. At 0 substrate bias the fT and fMAX was 30 and 45 GHz, respectively. Integration of HBTs with SOI is promising but much work remains to be done.

3.2.5 Advanced HBT Structures and Scaling Limits Scaling in bipolar technologies involves a combination of vertical and lateral scaling. In vertical scaling the total transit time is reduced by reducing each of the component transit times. The expression for the

© 2006 by Taylor & Francis Group, LLC

3.2-226

The Silicon Heterostructure Handbook

total transit time is given in Equation (3.2.2) to Equation (3.2.4). In the case of graded SiGe base HBTs, the base is scaled by shrinking the base width WB and increasing the slope of the Ge across the base, which often includes increasing the peak Ge% [33]. If all doped regions are thinned the transit times may decrease but the RC time constants will increase due to increased resistances. Therefore, innovation is required with vertical scaling to simultaneously reduce the thicknesses in the structure, area of the capacitances, and resistances

tEC

1 ¼ tEC ¼ tC þ tB þ t CSCL 2pfT 2 kT kT WB WB WCSCL þ ¼ CEB þ þ RC þ RE CCB þ g þ qIC qIC Dn VEXIT 2nSAT kT kt DE g¼ 1 [1 e g;GeðgradeÞ=kT ] DEg;GeðgradeÞ DEg;GeðgradeÞ

(3:2:2) (3:2:3) (3:2:4)

In the case of the in situ doped SiGe base the introduction of carbon and the retarding effects on boron diffusion from high-concentration Ge have enabled the sheet resistance of the intrinsic base layer to decrease generation to generation. Fortunately, the epitaxial technology is very advanced today and it is routine to deposit and control very thin SiGe(C) layers. To achieve a higher fT value it is apparent from Equation (3.2.3) that the charging current (IC) must be increased, which means that the Kirk effect must be pushed out to higher current densities. This is accomplished by increasing the collector dopant concentration, usually by an increase in the siliconimplanted collector or SIC, which increases IC and decreases both RC and WCSCL. However, increasing the SIC implant causes more lateral and vertical diffusion, which increases the base–collector capacitance (CCB). The base–collector capacitance is an important term in advanced structures and it indicates an interaction of lateral and vertical scaling that must be carefully controlled to improve the fMAX as well as fT. A schematic cross section of an idealized bipolar shown in Figure 3.2.10 illustrates some of the key parasitics that may be reduced by lateral scaling. To first order, lateral scaling is shrinking all the dimensions and overlaps, which will significantly improve the capacitances and resistances by minimizing

RBSP

RBSU

R BSX RBSSL

Emitter polysilicon C BENP CBEP

CCBOL

CBEA CCBI

Pedestal (SIC)

Base polysilicon Shallow trench

CCBX CCBPB

Subcollector

FIGURE 3.2.10

Cross section through an idealized bipolar transistor showing the key later parasitics.

© 2006 by Taylor & Francis Group, LLC

3.2-227

Device Structures and BiCMOS Integration

the area and distances that current must flow through resistive layers. There are cases in which the shrinking dimensions may cause increased parasitics. For instance, decreasing the trench width increases the perimeter collector to substrate capacitance. Therefore, this dimension is not scaled generation to generation. In another case, decreasing the distance between the SIC implant and the extrinsic base implant will increase the overlap and increase the overlap capacitance CCBOL (see Figure 3.2.10). This component can be a large part of the delay so it must be decreased. The only way to do this is by structural innovation that has resulted in raised extrinsic base structures in which the implant into the silicon is removed to greatly decease the diffusion into the SIC layer (Figure 3.2.11) [33].

THz Performance Possibilities Having reviewed vertical and lateral scaling let us consider what type of future structures would be required to achieve an fT of 1 THz (total transit time < 160 fsec or <40 fsec for tE, tB, tC, tCSCL, respectively). An important assumption is that parasitics, which can be addressed by geometrical scaling, will not be dominant delay components because they can be reduced with clever structural innovations and lithography shrinks. Solutions to THz performance will be found by using the scaling methodology discussed above and methodically addressing each delay component. The emitter delay (tE) component given by Equation (3.2.5) can be addressed by aggressively scaling the emitter area, i.e., emitter width, and therefore CBE. This component will not be a dominant delay component since the emitter width can be relatively easily scaled [34, 35]. Concerns exist about the high current densities but by scaling the shrinkage of the emitter width to 1/(peak fT current density) many of these concerns are mitigated [36]. The base delay (tB) component can be addressed by continuing to shrink the vertical profile using a

Overlap N+ Poly

W Stud contact

Silicide SiGe

N+

DT

STI

SIC

STI

DT

N+ Subcollector P substrate

WE Shallow junction

Raised extrinsic base

STI N+

SIC

N+ Subcollector DT P substrate

FIGURE 3.2.11 Selective scaling in bipolar transistors.

© 2006 by Taylor & Francis Group, LLC

DT

3.2-228

The Silicon Heterostructure Handbook

combination of reduced thermal cycle and increased Ge and C content. Base transit time is limited by transit across the neutral base and the ability of carriers to exit the base at the base–collector space charge region [37]. A graph of these two components versus base width shown in Figure 3.2.12 indicates that at a neutral base width of 80 nm the transit time is less than 40 fsec. Because of the atomic layer control that SiGe epitaxy has [38], achieving neutral base widths of 8 nm is possible. The collector delay (tC) component, given by Equation (3.2.7), is the most complex and will be very challenging. Assuming we can use geometry, and clever structural device design, the CBC term can be reduced by scaling the active collector–base capacitance area and using structures like the raised extrinsic base to reduce the collector– base capacitance per unit area. The most critical area is the overlap between the extrinsic base diffusion and the SIC collector implant. Typically for vertical scaling, the collector doping is increased which increases the current (IC) and pushes out the Kirk effect. This also reduces RC. Structural innovation will also have to occur to continue reducing the emitter and collector resistance. These are difficult challenges but may be possible. And finally the last term to consider is the transit time through the collector–base space charge region given by Equation (3.2.8). This delay component is becoming a significant impediment to vertical scaling. The high-field mobility is a material property and not easily influenced by the process. Therefore, unless there are dramatic changes with a migration to new materials constants this may prove to be the limit to performance kT CBE q IC 2 kT Wb Wb þ tB ¼ DEGe Dn nexit kT t C ¼ RE þ RC þ CBC qIC tE ¼

t CSCL ¼

tB = ∆Eg,Ge kT

2 T 2b kT − T b kT D n ∆EGe D n ∆EGe

Dn ≈ 10

>5

cm2

s−1

nexit ≈

2

(3:2:6) (3:2:7)

WCSCL 2nSAT

1−e−∆EGe /kT

1.0⫻107

(3:2:5)

cm

+

(3:2:8)

Tb nexit

kT ∆E Ge

1−e−∆EGe /kT t B ≈ kT ∆E Ge

s−1

T b2 Dn

+

300 Total

Delay Time (fsec)

250

Correction 200

Diffusion

150 100 50 0 0

50

100

150

200

250

Neutral Base Width (Angstroms)

FIGURE 3.2.12

Base transit delay time components as a function of neutral base width.

© 2006 by Taylor & Francis Group, LLC

300

Tb nexit

Device Structures and BiCMOS Integration

3.2-229

3.2.6 Summary There are many interesting bipolar structures that can be classed into three groups, non-self-aligned, self-aligned using an inner sidewall technique, and self-aligned using an outer sidewall. The BaG process integration flow is the most commonly used approach since it decouples the CMOS and bipolar thermal cycles. A challenge for the future will be the integration into advanced CMOS processes, which use mobility enhancement by strain techniques. SiGe HBTs will continue to improve in performance moving closer to 1 THz peak fT values. To achieve these values substantial material modifications of the SiGe HBTs and significant structural innovation will be required.

Acknowledgment The author would like to thank all the individuals at IBM who have contributed to SiGe HBT technology to make this work possible, as well as A. Joseph, J.-S. Rieh, J. Johnson, G. Freeman, and J. Dunn, for many helpful discussions about this work.

References 1. JR Long and MA Copeland. The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. IEEE J Solid-State Circ 32(3):357–369, 1997. 2. SA St. Onge, DL Harame, JS Dunn, S Subbanna, DC Ahlgren, G Freeman, B Jagannathan, J Jeng, K Schonenberg, K Stein, R Groves, D Coolbaugh, N Feilchenfeld, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, and S Johns. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm LEFF CMOS. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. 3. BS Meyerson, F Himpsel, and KJ Uram. Bistable conditions for low temperature silicon epitaxy. Appl Phys Lett 57:1034–1036, 1990. 4. BS Meyerson. Low temperature silicon epitaxy by ultra-high vacuum/chemical vapor deposition. Appl Phys Lett 48:797–799, 1986. 5. D Dutarte. RTCVD growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 6. WB De Boer, D Terpstra, and JGM Van Berkum. Selective versus non-selective growth of Si and SiGe. Mater Sci Eng 67:46–52, 1999. 7. E Kasper. MBE growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 8. P Magnee. SiGe:C HBT device technology: what is the big deal? Short Course Notes of the IEEE Bipolar BiCMOS Circuits and Technology Meeting, Toulouse, 2003. 9. J Osten. Carbon doping of SiGe. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 10. T Adam. UHV/CVD. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 11. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base pnp transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 12. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JY-C Sun, GJ Scilla, J Warnock, BJ Ginsberg, KA Jenkins, K-Y Toh, DL Harame, and S Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300.

© 2006 by Taylor & Francis Group, LLC

3.2-230

The Silicon Heterostructure Handbook

13. E Ganin, TC Chen, JMC Stork, BS Meyerson, JD Cressler, G Scilla, J Warnock, DL Harame, GL Patton, and TH Ning. Epitaxial-base double-poly self-aligned bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 603–606. 14. ED Johnson, TB Hook, JE Bertsch, Y Taur, CL Chen, HJ Shin, S Ramaswamy, A Edenfeld, and C Alcorn. A high-performance 0.5-mm BiCMOS technology with 3.3-V CMOS devices. Digest of Technical Papers VLSI Technology Symposium, Kyoto, 1990, pp. 89–90. 15. JD Warnock. Silicon bipolar device structures for digital applications: technology trends and future directions. IEEE Trans Electron Dev 42(3):382–383, 1995. 16. JN Burghartz, BJ Ginsberg, SR Mader, T-C Chen, and DL Harame. Selective epitaxial base transistor (SEBT). IEEE Electron Dev Lett 9(5):259–262, 1988. 17. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Trans Electron Dev 40:455– 468, 1995. 18. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Trans Electron Dev 40:455–468, 1995. 19. SA Jang, C-S Han, Y-B Kim, and I-S Yeo. The role of polysilicon in the suppression of Bird’s beak in poly-buffered LOCOS. IEEE Trans Electron Dev 46(2):433–436, 1999. 20. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 21. DL Harame, EF Crabbe, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, JC Malinowski, AJ Dally, S Ratanaphanyarat, MJ Saccamango, W Rausch, J Cotte, C Chu, and JMC Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 22. DJ Frank, RH Dennard, E Nowak, PM Solomon, Y Taur, and H-SP Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288, 2001. 23. K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, P Ronsheim, M Ieong, A Grill, and H-SP Wong. Strained Si NMOSFETs for high performance CMOS technology. Technical Digest of the VLSI Technology Symposium, 2001, pp. 59–60. 24. S Takagi, T Mizuno, T Tezuka, N Sugiyama, T Numata, K Usuda, Y Moriyama, S Nahaharai, J Koga, A Tanabe, N Hirashita, T Irisawa, and T Maeda. Strained — Si/SiGe — On Insultator CMOS Technology as a platform of device performance boosters, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 61–76. 25. T Ghani, M Armstrong, C Auth, M D Giles, K Mistry, A Murthy, L Shifren, S Thompson, and M Bohr. Uniaxial-strained Silicon CMOS Devices for High Performance Logic Nanotechnology, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 681–700. 26. EJ Nowak, I Aller, T Ludwig, K Keunwoo, RV Joshi, C-T Chuang, K Bernstein, and R Puri. Turning silicon on its edge. IEEE Circuits Dev Mag 20(1):20–31, 2004. 27. JL Hoyt, HM Nayfeh, S Eguchi, I Aberg, G Xia, T Drake, EA Fitzgerald, and DA Antoniadis. Strained Silicon MOSFET Technology. Technical Digest of the Electron Devices Meeting, Washington, 2002, pp. 23–26. 28. CW Liu, S Maikap, MH Liao, and F Yuan. BiCMOS devices under mechanical strain, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 437–438.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-231

29. H Nii, T Yamada, K Inoh, T Shino, S Kawanaka, M Yoshimi, and Y Katsumata. A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications. IEEE Trans Electron Dev 47(7):1536–1541, 2000. 30. GG Shahidi, DD Tang, B Davari, Y Taur, P McFarland, K Jenkins, D Danner, M Rodriguez, A Megdanis, E Petrillo, M Polcari, and TH Ning. A novel high-performance lateral bipolar on SOI. Technical Digest of the 1991 Electron Devices Meeting, San Fancisco, 1991, pp. 663–666. 31. T Arnborg and A Litwin. Analysis of new high-voltage bipolar silicon-on-insulator transistor with fully depleted collector. IEEE Trans Electron Dev 42(1):172–177, 1995. 32. J Cai, M Kumar, M Steigerwalt, H Ho, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the 2003 BCTM, Toulouse, 2003, pp. 215–218. 33. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, AD Stricker, DC Ahlgren, and S Subbanna. Transistor design and application considerations for >200-GHz SiGe HBTs. IEEE Trans Electron Dev 50(3):645–655, 2003. 34. G Freeman, J-S Rieh, B Jagannathan, Y Zhijian, F Guarin, and A Joseph. Device scaling and application trends for over 200 GHz SiGe HBTs. Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers 2003 Topical Meeting on Silicon Heterostructures, 2003, pp. 6–9. 35. B Jagannathan, M Meghelli, K Chan, J-S Rieh, K Schonenberg, D Ahlgren, S Subbanna, and G Freeman. 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Dev Lett 24(5):324–326, 2003. 36. J-S Rieh, KM Watson, F Guarin, Y Zhijian, P-C Wang, AJ Joseph, G Freeman, and S Subbanna. Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density. IEEE Trans Dev Mater Reliab 3(2):31–38, 2003. 37. MJW Rodwell, T Mathew, D Scott, D Mensa, Q Lee, J Guthrie, Y Betser, SC Martin, RP Smith, S Jaganathan, S Krishnan, SI Long, R Pullela, B Agarwal, U Bhattacharya, L Samoska, and M Dahlstrom. Submicron sealing of HBTs, IEEE Trans Electron Dev 48 (11): 2606–2604, 2001. 38. B Tillack, Y Yamamoto, and J Murota. Atomic Level Control of SiGe Epitaxy and Doping, Proceedings of the 206th Electrochemical Society, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 803–814.

© 2006 by Taylor & Francis Group, LLC

3.3 SiGe HBTs on CMOSCompatible SOI 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6

Jin Cai and Tak H. Ning IBM, T. J. Watson Research Center

3.3.7

The SOI Advantage ................................................... 3.3-233 Vertical Bipolar Transistors on Thin SOI................ 3.3-234 Voltage Pinning in a Fully Depleted Collector ....... 3.3-235 Making SiGe HBTs on Thin SOI Substrate ............ 3.3-238 Characteristics of SOI SiGe HBTs............................ 3.3-240 Process Optimization, Device Scaling, and Complimentary Bipolar .................................... 3.3-244 Summary .................................................................... 3.3-245

3.3.1 The SOI Advantage Silicon-on-insulator (SOI) technology has matured over the past 15 years to become production-worthy for advanced CMOS manufacturing [1], for applications ranging from high-end servers like IBM’s PowerPC and AMD’s Opteron to ultralow-power systems like Seiko and Oki’s chips for watches. Conventional silicon VLSI processing is based on bulk silicon substrates. When CMOS transistors are built into a thin silicon film of the order of 0.1 mm on top of an insulating silicon dioxide layer, the source and drain junction capacitance is greatly reduced. As a result, SOI CMOS circuits switch faster and use less power than conventional bulk CMOS. The power-delay advantage obtained from substrate material innovation has become particularly important as conventional CMOS scaling is reaching its limit. BiCMOS is the preferred technology platform for many wireless and communication applications, which need both RF/analog functions from bipolar transistors and low-power digital functions from CMOS transistors. From a mixed-signal system perspective, SOI is attractive due to the insulating nature of the substrate, which can provide RF noise isolation between digital and RF/analog components, particularly when a thick insulator or high-resistivity substrate is used [2], or when substrate engineering is applied [3]. The reduction of substrate loss also enables fully integrated high quality-factor passive elements for communication systems [2]. The challenge for SOI BiCMOS integration arises from a fundamental device architectural difference between bipolar and CMOS. Unlike CMOS transistors where current flows in a superficial silicon layer from source to drain, in high-speed vertical bipolar transistors including all SiGe HBTs, electrons flow vertically from the emitter on the top to the collector on the bottom. In order to have low resistance access to the collector from a contact electrode on the top, a subcollector layer on the order of 1 to 2 mm thick with heavy doping is needed underneath the collector, which makes it too thick to build on thin silicon film SOI. Past approaches to SOI BiCMOS integration either used a thick silicon layer on a bonded SOI substrate to accommodate the vertical bipolar transistors, or used lateral bipolar transistors on thin silicon film SOI. In the thick SOI case, the CMOS transistors have the same source and drain junction capacitances as those on a conventional bulk substrate and thus have no power-delay advantage. Digital BiCMOS technology on 1 to 1.5 mm silicon film SOI was developed for soft-error immune 3.3-233 © 2006 by Taylor & Francis Group, LLC

3.3-234

The Silicon Heterostructure Handbook

processors [4, 5]. More recently, a SiGe HBT–CMOS technology on 1 mm silicon film SOI was developed for RF and mixed-signal applications, featuring integrated high-Q inductors [2]. For such thick-silicon SOI BiCMOS, deep trenches are employed to isolate the bipolar transistors from the bulk-like CMOS devices. The lateral SOI bipolar has limited speed due to base width control and is not compatible with SiGe epitaxy. It is noteworthy that process innovations to minimize the base width and base resistance have kept improving the speed of lateral SOI bipolar transistors over the years [6–8]. With fT up to 20 GHz, it still cannot compete with vertical bipolar transistors (not to mention SiGe HBTs) in terms of performance, but it may provide a low-cost solution for mobile wireless communications due to a simpler and more CMOS-compatible manufacturing process [7]. Recently, a novel vertical bipolar transistor suitable for integration on CMOS-compatible SOI was proposed and npn transistors with SiGe base were demonstrated on 0.12 mm SOI [9–12]. The remainder of this chapter is dedicated to the concept, manufacturing process, electrical characteristics, and future prospects of this new transistor.

3.3.2 Vertical Bipolar Transistors on Thin SOI High-performance vertical bipolar transistors consist of an nþ emitter region, a p-type base region, and an n-type collector region stacked atop one another. The base and emitter regions can be built on top of the SOI substrate by epitaxial growth of a silicon–germanium base layer followed by LPCVD deposition of a polysilicon emitter film, like in most SiGe HBTs. Thus the silicon film of the SOI substrate needs to accommodate only the collector part. In conventional vertical bipolar, typically a thick nþ-type subcollector region and an nþ reachthrough region are used to give a low resistance contact to the collector at the silicon surface. The subcollector is placed deep enough to leave a quasineutral region of n-collector between the subcollector and collector space–charge region (or depletion region), such that the collector–base capacitance is not increased. This conventional collector structure would require an SOI substrate with a silicon film thickness (TSi) of at least 1 mm, as illustrated in Figure 3.3.1(a). The silicon film thickness requirement is greatly relaxed if we omit the thick nþ subcollector layer, as shown in Figure 3.3.1(b). The lower bound of TSi is determined by the depth of the depleted collector region (WC). For a collector doping concentration (NC) of 1017 cm3 and a reverse collector–base junction bias of 2 V, WC ¼ 0.19 mm, which approaches the range of TSi for SOI CMOS devices. However, the collector current is carried laterally toward the nþ reachthrough in the thin quasineutral layer above the buried oxide, which is very resistive. The collector series resistance from the quasineutral layer is inversely proportional to NC (TSI WC) and can be more than 103 times higher than that of a heavily doped 1-mm thick subcollector layer. A more radical reduction of TSi to below collector depletion thickness WC leads to a new vertical bipolar transistor, as shown in Figure 3.3.1(c). The collector underneath the base and above the buried oxide is fully depleted. The fully depleted collector not only eliminates the resistive quasineutral layer but also results in a reduced collector–base junction capacitance (CCB) due to its serial connection with a small capacitance from the thick buried oxide layer. To minimize collector series resistance, the nþ reachthrough should be placed as close as possible to the depleted collector region. However, it is desirable to leave a narrow quasineutral region in-between such that the proximity of nþ reachthrough does not limit CCB or the breakdown voltage of the device. The new device structure in Figure 3.3.1(c) is similar to bending the vertical collector structure in Figure 3.3.1(a) by 908 such that most of the vertical collector stack including the lower part of collector depletion region, the quasineutral collector region, and the nþ subcollector region rest on the side of the upper part of collector depletion region. Under forward active mode, electrons injected from the emitter, instead of flowing vertically down toward the subcollector layer as in a typical vertical bipolar transistor, are guided by the two-dimensional electric field in the collector depletion region and make a turn toward the nþ reachthrough on the side.

© 2006 by Taylor & Francis Group, LLC

3.3-235

SiGe HBTs on CMOS-Compatible SOI

C

B

Reachthrough

n+

B

E

n+

n+

p

p

n TSI > 1 µm

C

E

n

Depleted n collector

TSI

Quasi-neutral n collector

n Buriedoxide oxide buried

Subcollector

n+

n

n+

Substrate of SOI

Buried buriedoxide oxide

(b)

Substrate of SOI

(a)

C

B

E

n+ Reachthrough

TSI < 0.2 µm

n+

p n

n

Depleted n collector Quasi-neutral n collector

Buriedoxide oxide buried Substrate of SOI

(c)

FIGURE 3.3.1 Schematics of npn bipolar transistors on SOI substrate, showing the evolution of collector design that leads to the new transistor. The three cross sections have the same base and emitter layers but different collector layers: (a) the traditional design with nþ subcollector underneath the n-collector, (b) without nþ subcollector, and (c) fully depleted n-collector.

The new device concept overcomes the TSi limit for integrating SiGe HBT with SOI CMOS. For a given TSi that is usually dictated by CMOS scaling requirement, there is an upper limit to the collector doping concentration that satisfies WC ¼ TSi. To maximize the high-frequency performance of the HBT, an NC near this limit can be used to delay the onset of base push-out, or Kirk effect.

3.3.3 Voltage Pinning in a Fully Depleted Collector In this section, a simple one-dimensional theory is used to analyze the onset condition of full collector depletion, as a function of the physical structure (TSi, NC) and bias conditions (VB, VC, and VS for base, collector, and SOI substrate, respectively). The unique characteristic of collector voltage pinning and its consequence on bipolar device operation will be highlighted. For simplicity, consider part of the SiGe HBT structure, with base, collector, nþ reachthrough, and SOI substrate, as illustrated in Figure 3.3.2(a). Due to the symmetry, along the central cut line, the electric field is vertical and the potential distribution can be solved exactly using one-dimensional Poisson’s equation. The problem is simply a p–n diode in series with a MOS capacitor. Figure 3.3.2(b) illustrates the band diagram along the cut line for the case where both the p–n diode and MOS capacitor

© 2006 by Taylor & Francis Group, LLC

3.3-236

The Silicon Heterostructure Handbook

VB

VC

VC p y1

n+

n+

n

y2

TBox

Buried oxide Substrate of SOI

p+

VS

(a)

Base Collector SiO2 Substrate

Base Collector SiO2 Substrate

E

TSI

EC

TSI

TSI VS

VB EV

EMAX

VC Y y1

y2

y1

(b)

y2

(c)

FIGURE 3.3.2 Analysis of collector potential distributions based on depletion approximation. (a) Schematic cross section of part of an SOI bipolar transistor with symmetrically placed nþ reachthough regions; (b) energy band diagram along the central cut line; and (c) electric field distribution along the same cut line.

are reverse-biased (VB < VC, VS < VC), with two distinct depletion regions of width y1 and y2, respectively (y1 þ y2 < TSi). Figure 3.3.2(c) illustrates the electric field distribution along the same cut line. The voltage in the collector quasineutral region follows VC of the nþ reachthough regions. 0 Increase of collector voltage widens both depletion regions and at certain critical voltage VC , the 0 two depletion regions merge. Increase of collector voltage beyond VC no longer influences the vertical 0 field. The potential well along the center line has a fixed depth determined by VC. This is referred 0 to as collector voltage pinning. Away from the centerline, the additional voltage VC –VC increases the lateral field. The critical collector voltage can be solved analytically using depletion approximations for both the p/n diode and the MOS capacitor. For the base–collector diode, assuming one-sided abrupt junction, depletion width y1 is described by VC VB þ VBI ¼

q NC y12 ; 2«S

(3:3:1)

where VBI is the diode built-in potential. For the MOS capacitor, the depletion width y2 near the buried oxide is described by VS VC fMS ¼ VOX þ VSI ¼

qNC y2 q NC y22 ; 2«S COX

(3:3:2)

where fMS is the work function difference between the pþ substrate of SOI and the n-collector, VOX and VSI are potentials dropped across the buried oxide and the collector depletion region (y2), respectively. 0 The critical collector voltage VC that fully depletes the collector, i.e., y1 þ y2 ¼ TSi, can be solved based on Equations (3.3.1) and (3.3.2):

© 2006 by Taylor & Francis Group, LLC

3.3-237

SiGe HBTs on CMOS-Compatible SOI

VC0 ¼ VB VBI þ

q q 0 NC (y10 )2 VCM ¼ VB VBI þ NC TSi2 ; 2«S 2«S

(3:3:3)

0

where y1 is the value of y1 at the onset of full depletion: y10

1=COX þ 1=(2CS ) (VB VS þ fMS VBI )=qNC TSi ; ¼ TSi 1=COX þ 1=CS

(3:3:4)

Saturated collector (VC'<0)

I. Fully depleted collector

VC (V)

1.0

=VS −φm

1.5

VC

T_SI = 120 nm T_BOX = 140 nm NC = 1.5E17/cm3 VB = 0 V

2.0

s

CS ¼ «S/TSi and COX ¼ «OX/TBOX. For thick buried oxide (COX << CS) and low substrate biases (VS VB), the depletion region due to the MOS capacitor is narrow and y10 TSi. In general, when the MOS capacitor is under flatband condition and the collector is fully depleted from the p/n diode (y10 ¼ TSi), 0 . More negative substrate bias induces the critical collector voltage reaches the maximum value of VCM a depletion region near the buried oxide, which has the effect of lowering the critical collector voltage via a smaller y10 . In the other direction, under more positive substrate bias, the MOS capacitor is under surface accumulation condition, i.e., electrons accumulate near the buried oxide interface. The accumulation layer is linked to the nþ reachthrough regions and acquires the collector potential VC. This breaks the collector voltage pinning. The vertical potential drop again follows the collector voltage. The accumulation layer acts like an ultrathin subcollector, which is shown to significantly enhance the speed of the SOI SiGe HBTs in Section 3.3.5. We call this novel structure with depleted collector directly on accumulated back surface the accumulation-subcollector transistor. For any SOI bipolar structure, there are four distinct types of collectors depending on the bias condition: (i) fully depleted collector; (ii) partially depleted collector with depleted back surface; (iii) partially depleted collector with accumulated back surface, and (iv) depleted collector on accumulated back surface (accumulation subcollector). The bias condition that defines the collector type is shown in Figure 3.3.3 for an SOI bipolar device with TSi ¼ 120 nm, TBOX ¼ 140 nm, NC ¼ 1.5 1017 cm3, which is used in the experiment described in Section 3.3.4. VB ¼ 0 is the reference voltage. The boundary between regions I and II is described by Equation (3.3.3). The single point that borders all four

IV. Depletedcollector on accu. layer VC = VCM

0.5 VC

C'

=V

0.0 −0.5 −1.0

II. Partially depleted collector (depleted back surface) −4

−2

0 VS (V)

III. Partially depleted collector (accu. back surface)

2

4

FIGURE 3.3.3 The collector characteristic of an SOI bipolar transistor is categorized into four types depending on the collector and SOI substrate bias conditions: (1) fully depleted collector, (2) partially depleted collector with depleted back surface, (3) partially depleted collector with accumulated back surface, and (4) depleted collector on accumulated back interface, or accumulation subcollector.

© 2006 by Taylor & Francis Group, LLC

3.3-238

The Silicon Heterostructure Handbook

regions corresponds to the condition that y10 ¼ TSi in Equation (3.3.4). It is noteworthy that in the fully depleted collector region, reduced vertical potential drop due to the negative substrate bias can lead to effective forward biasing of the B–C junction (VC0 < VB) for an apparent reverse bias condition (VC > VB), as shown by the shaded area. This region gives rise to collector saturation and should be avoided in circuit applications. There is a well-known tradeoff between the speed (fT) and the breakdown voltage (BVCEO) in a traditional bipolar transistor, from the vertical scaling of the collector depletion layer [13]. The voltage swing of a high-speed device is constrained by the breakdown voltage. We can design an SOI bipolar device such that the collector voltage is pinned at a value below the BVCEO of a bulk device with the same collector doping. The SOI device is expected to have improved BVCEO as well as Early voltage VA. Avalanche multiplication and breakdown is sensitive to the maximum electric field (EMAX) near the B–C junction interface. In a bulk device, EMAX increases with collector voltage as a function of pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 0 VC VB þ VBI , whereas in the fully depleted collector device, it is pinned at (qNC/e S)y1 , independent of collector voltage. Thus avalanche effect progresses more slowly with increasing collector voltage in a fully depleted collector device than a bulk device. Avalanche breakdown is delayed to higher collector voltage in the SOI device where the lateral field becomes large enough to raise EMAX. The depletion width on the base side is determined by EMAX, which does not change with collector voltage in the fully depleted collector device. Therefore, the modulation of quasineutral base width by the collector voltage is much weaker than that of a bulk device, which results in higher VA. In an accumulation-subcollector device (region IV in Figure 3.3.3), the B–C junction reverse bias is dropped over TSi whereas in a bulk device the same reverse bias is dropped over a larger distance, or WC > TSi if collector-doping concentrations are the same. This means higher EMAX and somewhat degraded BVCEO and VA in an accumulation-subcollector device. The difference in the maximum field is SOI Bulk EMAX EMAX ¼

qNC WC TSi : «S TSi

(3:3:5)

3.3.4 Making SiGe HBTs on Thin SOI Substrate Figure 3.3.4 shows the process flow diagrams for building npn SiGe HBTs on SOI substrate. The silicon film thickness for SOI CMOS has been scaled down from about 0.2 mm to below 0.1 mm, along with channel length scaling. The new SiGe HBT is expected to be scalable to thinner SOI substrate as will be discussed in Section 3.3.6. In the experiment, we used the same SOI substrate that is used for a 130 nm SOI CMOS technology [14], which has a silicon thickness of 0.12 mm and a buried oxide thickness of 0.14 mm. After shallow-trench isolation, a phosphorus implant is introduced to define the collectordoping concentration in the silicon area. It can be a blanket implant in a bipolar-only process, or a masked implant in a BiCMOS flow. Both a uniform doping profile and a low–high retrograde doping profile were exercised. Then a mask is used for a high-dose phosphorus implant that defines an nþ reachthrough region surrounding the n-type collector in the middle. The mask dimension determines the length of the n-collector, LC, which was varied in the experiment to evaluate its effect on collector resistance and breakdown behaviors. Next, a dielectric stack, followed by a heavily doped pþ polysilicon layer, is deposited over the wafer. The pþ polysilicon will provide low-resistance contact to the base and the dielectric stack is served as an insulator between the pþ polysilicon and the collector. The thickness of the insulator should be optimized as it contributes to parasitic collector–base capacitance. The parasitic CCB could dominate in a fully depleted collector device as the collector–base junction capacitance is minimized. The use of a thicker insulator reduces CCB but creates more topography later in the process that can increase the base resistance. Then a window is etched into the polysilicon and insulator to expose the silicon surface for epitaxial growth of the SiGe base layer. The window size, LB, should be minimized while providing enough room for a defect-free SiGe base region. The SiGe base layer was grown by a nonselective

© 2006 by Taylor & Francis Group, LLC

3.3-239

SiGe HBTs on CMOS-Compatible SOI

n Buried oxide

STI, collector implant

Substrate of SOI

n+

n+

n Buried oxide Substrate of SOI

p+ n+

n+ reachthrough implant p+ n+

n

Dielectric stack, p+ poly

Buried oxide Substrate of SOI

p+ n+

p+

p n

n+

SiGe-base

Buried oxide Substrate of SOI

n+

n+ p+ n+

Dielectric stack, emitter window

p+

p n

n+

Buried oxide

n+ poly emitter

Substrate of SOI

p+ n+

n+ p n

p+ n+

Pattern n+ emitter poly

Buried oxide Substrate of SOI

B p+ n+

E n+ p n

p+

Buried oxide Substrate of SOI

C

Pattern p+ base poly

n+ CoSi, and contact open

FIGURE 3.3.4 An example of process flow to make SiGe HBTs on CMOS-compatible SOI.

© 2006 by Taylor & Francis Group, LLC

3.3-240

The Silicon Heterostructure Handbook

FIGURE 3.3.5 Cross-sectional SEM micrograph of a SiGe HBT on 0.12 mm silicon film SOI.

low-temperature epitaxy (LTE) process using UHV/CVD tools. During the LTE process, polysilicon is grown on the sidewalls of the dielectric window, which provides the link between the SiGe base layer and the overhanging pþ polysilicon layer. Next, a second dielectric stack is deposited which will serve as an insulator between the base and the emitter. An emitter window mask is used to etch an opening in the dielectric stack, and a layer of in situ arsenic-doped polysilicon layer is deposited that becomes the nþ emitter. Due to the two-dimensional electric field in the depleted collector region, the electrons coming down through the middle of the emitter window will have a longer lateral drift path in the depleted collector than those from the edge of the emitter window. The speed of the SOI device is expected to degrade at large emitter width. Simulation results suggest that a good rule of thumb is to keep WE < 2TSi. Two more mask levels are then used to pattern an nþ polysilicon emitter region and a pþ polysilicon base region, respectively. Cobalt silicide is formed over the pþ base and nþ collector reachthrough regions to reduce access resistance to the intrinsic base and collector of the device. Finally, contacts to the nþ emitter, pþ base, and nþ collector reachthrough are etched open. It should be noted that the deep subcollector implantation and drive-in, the n-type epitaxial silicon growth, and the deep-trench isolation process steps associated with fabrication of a conventional vertical bipolar transistor are not needed in fabricating the thin-SOI bipolar. Figure 3.3.5 shows an SEM micrograph of an SOI SiGe HBT, after contacts to the emitter, base, and collector are opened. The mask dimensions of emitter width, LTE window, and collector length are 0.16, 0.5, and 1.2 mm, respectively. The collector-doping profile is uniform, with NC ¼ 1.5 1017 cm3. Devices with smaller LB and LC designs and different collector-doping profiles were also fabricated.

3.3.5 Characteristics of SOI SiGe HBTs In this section, the electrical characteristics of the manufactured thin-SOI SiGe HBTs will be reviewed, with a focus on the breakdown behavior in the depleted collector SOI device as well as the substrate bias effect on both the DC and AC performance. Figure 3.3.6 shows the Gummel plot and the output ICVCE characteristics, with substrate bias, VSE (referenced to the emitter voltage), as a parameter that is varied from 5 to 20 V. The Gummel plot shows a peak current gain of over 400. Since the base and emitter process are borrowed from a bulk SiGe technology [15], the current gain is similar to that of the bulk devices. The substrate bias has an effect at emitter–base forward biases higher than 0.9 V. The opposite movement in IB and IC is a signature of collector saturation effect where the forward biasing of collector–base junction reduces IC while contributing to more IB. A positive substrate bias suppresses this saturation effect by increasing the vertical potential drop in the collector that prevents electrons from back injection into the base. The

© 2006 by Taylor & Francis Group, LLC

3.3-241

SiGe HBTs on CMOS-Compatible SOI

0.01 VCB = 0 V 1⫻10−4 IC IC, IB (A)

1⫻10−6 IB 1⫻10−8

VSE= −5 V 0V 5V 20 V

1⫻10−10

1⫻10−12 0.6

0.7

0.8

0.9

(a) 1.0

1.1

VBE (V) 0.25 IB = 0.1 µA/step

IC (mA)

0.20

0.15

0.10

0.05

(b) 0.00 0

1

2

3 VCE (V)

4

5

6

FIGURE 3.3.6 DC characteristics of a 0.16 mm 0.8 mm SOI SiGe HBT under four substrate bias (VSE ¼ VS VE) conditions: 5 V (dash–dot), 0 (solid), 5 V (dash), and 20 V (dot). (a) Gummel plot and (b) output characteristics.

ICVCE in Figure 3.3.6(b) shows almost identical turn-on behaviors under zero and positive substrate biases, whereas under the negative substrate bias, it requires higher collector voltage to turn on the device, another manifestation of saturation effect. This is consistent with Figure 3.3.3, which predicts an 0 effectively forward biased B–C junction (VC VB < 0) when VS VB < 2 V. As expected from the voltage-pinning effect, BVCEO is the highest at 5.5 V under zero substrate bias. The reduction of BVCEO at VSE ¼ 20 V is due to the accumulation subcollector that breaks the voltage pinning and creates a vertical potential drop of VCB across TSi. In contrast, at VSE ¼ 5 V, avalanche current turns on at the same VCE as the high-positive bias case, but the rate of increase with collector voltage is slower. This can be explained by Figure 3.3.3. Under low-positive VSE, as VCE increases, the collector makes a transition from the one with an accumulation subcollector (region IV) to a fully depleted collector (region I). The transition decouples the collector voltage to the maximum electric field at the B–C junction interface and results in a much slower increase of avalanche current with VCE.

© 2006 by Taylor & Francis Group, LLC

3.3-242

The Silicon Heterostructure Handbook

For the same collector design, BVCEO depends on the current gain (IC/IB) due to the bipolar effect. A more direct examination of avalanche multiplication is through the measurement of the ‘‘M 1’’ factor [16]. In this measurement, a constant forward emitter current (IE) is forced through the device while ramping up the collector voltage. The electron–hole pairs generated by impact ionization in the collector depletion region contribute to an increase in the collector current and a corresponding reduction in the base current (DIC ¼ DIB). The factor ‘‘M 1’’ is extracted as jDIBj/IE. Figure 3.3.7(a) compares the avalanche multiplication in an SOI SiGe HBT to two bulk SiGe HBTs with 90 GHz fT (open symbols) and 50 GHz fT (solid symbols), respectively. In bulk devices, avalanche multiplication has the similar exponential dependence on VCB. The 90 GHz device has an ‘‘M 1,’’ which is about 6 times higher than the 50 GHz device due to heavier collector doping concentration as a part of vertical scaling. The SOI device shows a much weaker dependence of ‘‘M 1’’ on VCB under zero substrate bias, or under positive substrate bias in the high VCB range. This corresponds to the bias conditions for a fully depleted collector. In the open-base configuration, the increase of collector current due to avalanche effect is multiplied by the current gain b of the bipolar transistor. When b(M 1) ¼ 1, the collector current is doubled from its

1

IE = 10 µA Bulk SiGe HBT

Multiplication factor −1

0.1

20V

0.01

5V

1⫻10−3 0V

1⫻10−4

−5V

1⫻10−5 0

1

(a)

2

SOI SiGe HBT 3

4

5

Collector−base reverse bias (V)

M−1 at VCB = 1.5 V (10−3)

5 4

SOI SiGe HBT (increase substrate bias)

3

NC2

2 bulk SiGe HBT (vertical scaling)

1 NC1 0 20

(b)

40

60

80

100

Cut-off frequency (GHz)

FIGURE 3.3.7 Comparison of measured avalanche multiplication factor (M 1) in the collector–base junction between SOI SiGe HBTs and bulk SiGe HBTs. (a) ‘‘M 1’’ as a function of reverse C–B junction bias. (b) Correlation between ‘‘M 1’’ and cutoff frequency, dashed line indicates trend from bulk SiGe HBT technologies.

© 2006 by Taylor & Francis Group, LLC

3.3-243

SiGe HBTs on CMOS-Compatible SOI

low VCB value, which can be used as a measure for device breakdown. The flat portion of the ‘‘M 1’’ data suggests that it is possible to significantly increase the BVCEO of a fully depleted collector device by reducing the current gain from 400 in the experimental hardware to about 100. Under positive substrate bias and in the low VCB range, which corresponds to the accumulation subcollector condition, ‘‘M 1’’ is nearly the same as the 50 GHz bulk device. Under negative substrate bias, the exponential rise of ‘‘M 1’’ suggests that the lateral field dominates avalanche multiplication in the saturated collector region where there is minimum vertical potential drop in the collector. Figure 3.3.7(b) shows that the SOI devices and the bulk devices have a different ‘‘M 1’’ versus fT tradeoff. The peak fT of the SOI devices can be improved by applying positive substrate biases without much increase of avalanche multiplication, while scaling NC in a bulk device results in a steeper penalty in ‘‘M 1,’’ or breakdown voltage. The fT and fMAX characteristics of an SOI SiGe HBT are shown in Figure 3.3.8, along with those of a lateral SOI bipolar device from Ref. [7]. The SiGe HBT shows a 150% to 350% improvement in peak fT, depending on the substrate bias condition. The maximum oscillation frequency, fMAX, on the other pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ hand, is less sensitive to the substrate bias. This is expected from the fMAX / fT =CCB dependence. As VSE increases, CCB increases as the collector makes a transition from a fully depleted one to the one with an accumulation subcollector. A 30% increase of fT is observed for a VSE change from 0 to 5 V, while there is minimal change in fMAX. This suggests that CCB increases by 30% due to the presence of an accumulation back surface. To understand the strong dependence of fT on VSE, it is instructive to look at the two-dimensional potential distribution in the collector depletion region. Figure 3.3.9 shows the simulated equipotential contours in the forward active mode with VCB ¼ 1 V and VBE ¼ 0.84 V. The potential VI is referenced to the vacuum level in the emitter. The boundaries of the collector depletion region are defined approximately by VI ¼ 4 V at the base side and VI ¼ 2.5 V at the nþ reachthrough side. At zero substrate bias (VSE ¼ 0 V) in part (a), the collector is fully depleted under the base and there is little potential drop along the vertical direction. The arrow indicates the electron drift path along the electric field direction. It is mostly lateral with a length of 0.5 mm. At 20 V substrate bias (VSE ¼ 20 V), the potential at the back interface is fixed at VI ¼ 2 V, the same potential as the nþ

80 fT

SOI substrate bias

fMAX

20 V

fT, fMAX (GHz)

60

5V Vertical SOI SiGe HBT 40 0V

20

Lateral SOI Bipolar [7] 0 1⫻10−6

1⫻10−5

1⫻10−4

1⫻10−3

Collector current/emitter length (A/µm)

FIGURE 3.3.8 fT and fMAX characteristics of a 0.16 mm 0.8 mm SOI SiGe HBT, with SOI substrate bias as a parameter. The characteristics of a lateral SOI bipolar transistor from Ref. [7] are plotted for comparison.

© 2006 by Taylor & Francis Group, LLC

3.3-244

The Silicon Heterostructure Handbook

VCB = 1 V, VBE = 0.84 V 1.0

1.0

0.8

0.8

−3.5

3 −2.5

3 −2.5

C

0.4

−2.5

−2.5 −5

−3.5

−4.5 −5

−3.5 −3

−4 −3.5

y (µm)

B

0.6

3 −2.5

C

0.4

−2.5

−3

−3.4 −2.5

−2 5 10 14.8

−4.5 −5

−4

E −4 −5.5

−4 −3.5 −3

5 10 14.8

0.2

0.2

S

S

0.0

VSE = 0 V

x (µm)

(a)

VSE = 20 V

x (µm)

1.0

0.9

0.8

0.7

0.6

0.4

0.3

0.2

0.1

0.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.0

0.5

y (µm)

E

B

0.6

(b)

FIGURE 3.3.9 Simulated potential contours in (a) a fully depleted collector device and (b) the same device transformed to an accumulation subcollector device by a 20 V substrate bias. The arrows represent the direction of electron flow in the collector depletion region. Due to symmetry, only half of the device structure is shown.

reachthrough region. The large substrate bias attracts a majority carrier accumulation layer with an electron concentration of (VS VC VBI)/qCOX ¼ 2.7 1012 cm2. The accumulation layer serves as an ultrathin subcollector, which provides a low resistance path to the nþ reachthrough. It also helps to reduce the collector series resistance in the reachthrough region. The electron drift path becomes vertical and much shorter, on the order of the SOI film thickness, or 0.1 mm. The shortened drift path results in a transit time tBC ¼ WdBC/2vSAT reduction of about 2 psec, which accounts for 80% of the fT improvements. The remaining improvement comes from the reduction of collector series resistance from the accumulation subcollector. Similar fT improvement may be obtained at a much lower substrate bias if the buried oxide is scaled down. For future SOI-CMOS technology, the ability to use a back gate voltage to control the CMOS threshold voltage is desirable for compensating chip-to-chip process variations. This can drive the scaling of buried oxide thickness to below 20 nm. On an SOI substrate with relatively thin buried oxide, it would suffice to connect the SOI substrate of the bipolar portion to the supply voltage VCC (3 V) of the analog–RF circuits to get the benefit of an accumulation subcollector. Use of nþ substrate instead of pþ substrate would further lower the required substrate bias by about 1 V. In lieu of an accumulation subcollector, a retrograde collector-doping profile with low concentration near the base and high concentration near the buried oxide can simulate some of the accumulation-subcollector effect, albeit the doping gradient is limited by the diffusion process and is much less ideal. Experimental hardware with a retrograde collector-doping profile measured a 60 GHz fT at zero substrate bias [11]. The ECL ring oscillator operation has been demonstrated using SiGe SOI bipolar transistors, with a minimum delay time of 18 pico-second per stage for a logic swing of 300 mV [11].

3.3.6 Process Optimization, Device Scaling, and Complimentary Bipolar This section will highlight the opportunities for some future work on the SOI SiGe HBTs. First, there are several process development opportunities for enhancing the device speed while maintaining the benefit

© 2006 by Taylor & Francis Group, LLC

3.3-245

SiGe HBTs on CMOS-Compatible SOI TABLE 3.3.1

Lithographical and SOI Thickness Scaling of Vertical SOI Bipolar Transistors Scaling Factor

Parameters

Fully Depleted Collector

WE, LB, LC TSi NC IC/LE WdBC, lateral WdBC, vertical RCLE CCB/LE RCCCB

a b 1/b2 a/b2 a b — — —

Accumulation Subcollector

Partially Depleted Collector

a b 1/b2 a/b2 — b a a/b a2/b

a b 1/b2 a/b2 — b ab a/b a2

of high breakdown voltage, which includes: (1) self-alignment of the LTE window to the nþ reachthrough region; (2) minimizing the ‘‘facet’’ region near the edge of the epitaxial layer such that the LTE window size (LB) can be reduced for the same emitter width; and (3) self-alignment of the emitter opening to the base layer. All these steps would facilitate closer placement of the nþ reachthrough to the center of the device to reduce the lateral drift path in a fully depleted collector. A buffered region of intermediate doping concentration between the nþ reachthrough and the n-collector would also help to reduce the lateral drift path while maintaining the same collector voltage pinning under the base. For SOI-CMOS, the trend in lateral (lithography dimensions) and vertical (TSi) scaling is expected to continue. We will show that the RF performance of the SOI bipolar device will benefit from this scaling trend as well. Table 3.3.1 shows the effect of scaling on the collector depletion layer drift length WdBC and collector delay time RCCCB for three types of collectors: fully depleted, depleted with accumulation subcollector, and partially depleted. Independent lateral and vertical scaling factors, a(<1) and b(<1), respectively, are assumed. A good guideline is to increase the collector doping concentration (NC) by 1/b2, such that the collector depletion width is reduced by the same factor b as TSi. A fully depleted collector remains fully depleted after scaling, with a shorter lateral drift path determined by the lateral scaling factor a. For the accumulation subcollector and partially depleted collector devices, in addition to a reduction in the vertical drift path by b, the collector resistance reduction results in an RC delay time reduction of up to a factor of a2. Thus, even the partially depleted device can be an attractive option after significant reduction in RC delay time. Simulation results suggest at 100 nm emitter width, 200 GHz fT can be achieved on 55 nm SOI substrates using a collector-doping concentration of 2.4 1018 cm3. The guideline for NC scaling will be eventually limited by the base–collector band-to-band tunneling current and the collector breakdown voltage. Though the speed of SOI SiGe HBT will not be as high as the most advanced bulk SiGe HBT, it will be adequate for most of the RF and wireless applications. Compared to bulk SiGe HBTs, the SOI device features a simpler manufacturing process as deep trench isolation and epitaxial collector are not necessary and the deep subcollector is omitted. The full dielectric isolation of each transistor by the shallow-trench and the buried oxide provides a lower cost opportunity to make both vertical npn and vertical pnp bipolar transistors on the same chip, as illustrated in Figure 3.3.10. In bulk technologies, usually only vertical SiGe npn and lateral Si pnp transistors are available, the latter simply as two back-to-back connected p–n diodes that have very low performance. The availability of a high-performance vertical SiGe pnp transistor should provide innovation opportunities in analog circuit design for significant performance improvement and power saving.

3.3.7 Summary We presented a new class of vertical SiGe HBTs that is compatible with SOI-CMOS. The unique feature of collector voltage pinning in thin silicon film was discussed in depth, which gives rise to high breakdown voltage, high early voltage, and low collector capacitance. The SOI device is promising for

© 2006 by Taylor & Francis Group, LLC

3.3-246

The Silicon Heterostructure Handbook

pnp

npn

E

E B p+ n+ p+ C

B C n+ p+ n+ p+

p

p+

n+

n

n+

nMOS

pMOS

G

G

S n+ D D p+ S n+ p n+ p+ n p+

Buried oxide Substrate of SOI FIGURE 3.3.10

Illustration of an SOI complementary bipolar and CMOS technology.

a better fT-BVCEO tradeoff than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of DC and RF characteristics on SOI substrate bias. The relatively low speed of a fully depleted collector device can be significantly enhanced by a positive substrate bias for an accumulation-subcollector operation. The new device is expected to scale well with SOI-CMOS and can enable complementary SOI-BiCMOS with the possibility of a high-performance pnp transistor.

Acknowledgments The authors would like to thank M. Kumar, M. Steigerwalt, H. Ho, A. Ajmera, K. Stein, H. Chen, and M. Khater for process support, Q. Ouyang, P. Oldiges, J. Rieh, and K. Jenkins for simulation and characterization help, and G. Shahidi, W. Haensch, G. Freeman, and D. Ahlgren for management support.

References 1. G.G. Shahidi. SOI technology for the GHz era. IBM J. Res. Develop. 46(2–3), 121–131 (2002). 2. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, K. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180 GHz fMAX 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEDM Tech. Digest, 741–744 (2000). 3. J.N. Burghartz, M. Bartek, B. Rajaei, P.M. Sarro, A. Polyakov, N.P. Pham, E. Boullard, and K.T. Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proc. BCTM, pp. 17–23 (2002). 4. T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Usami, and T. Ikeda. A 27-GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mm2 CMOS cells for ECL-CMOS SRAM applications. IEDM Tech. Digest, 39–42 (1992). 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Konda, S. Konda, Y. Homma, N. Owada, and T. Ikeda. A 0.2 mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. IEDM Tech. Digest, 209–212 (1998). 6. G.G. Shahidi, D.D. Tang, B. Davari, Y. Taur, P. McFarland, K. Jenkins, D. Danner, M. Rodringuez, A. Megdanis, E. Petrillo, M. Polcari, and T.H. Ning. A novel high-performance lateral bipolar on SOI. IEDM Tech. Digest, 663–666 (1991). 7. T. Shino, S. Yoshitmi, H., Nii, S. Kawanaka, K. Inoh, T. Yamada, T. Fuse, Y. Katsumata, M. Yoshimi, S. Watanabe, and J. Matsunaga. Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications. IEEE Trans. Electron Dev. 49(3), 414–421 (2002). 8. H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshomi, and Y. Katsumata. A novel lateral bipolar transistor with 67-GHz fMAX on thin-film SOI for RF analog applications. IEEE Trans. Electron Dev. 47, 1536–1541 (2000).

© 2006 by Taylor & Francis Group, LLC

SiGe HBTs on CMOS-Compatible SOI

3.3-247

9. J. Cai, A. Ajmera, Q. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, and T. Ning. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI. Symp. VLSI Tech. Digest, pp. 172–174 (2002). 10. Q. Ouyang, J. Cai, P. Oldiges, and J. Johnson. A simulation study of thin SOI bipolar transistors with fully or partially depleted collector. BCTM Tech. Digest, 28–31 (2002). 11. J. Cai, M. Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K. Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Oldiges, and T. Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proc. BCTM, pp. 215–218 (2003). 12. L. Geppert. A better bipolar transistor for wireless ICs. IEEE Spectrum, December 2003, p. 20. 13. Y. Taur and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (1998) [chapter 8]. 14. P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L. Lin, R. Mann, E. Meciejewski, S. Narasimha, P. O’Neil, S. Rauch, D. Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt, and T.C. Chen. A high-performance 0.13 mm SOI CMOS technology with Cu interconnects and low-k BEOL dielectrics. Symp. VLSI Tech. Digest, pp.184–186 (2000). 15. G. Freeman, D. Ahlgren, D.R. Greenberg, R. Groves, F. Huang, G. Hugo, B. Jagnnathan, S.J. Jeng, J. Johnson, K. Schonenberg, K. Stein, R. Volant, and S. Sabbanna. A 0.18 mm 90 GHz fT SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications. IEDM Tech. Digest, 569–572 (1999). 16. G. Freeman, J. Rieh, B. Jagannathan, Z. Yang, and F. Guarin. Device scaling and application trends for over 200GHz SiGe HBTs. Proc. International SiGe Technology and Device Meeting, pp. 51–52 (2003).

© 2006 by Taylor & Francis Group, LLC

3.4 Passive Components 3.4.1 3.4.2 3.4.3

Introduction............................................................... 3.4-249 Resistors and Capacitors........................................... 3.4-251 Inductors and Transformers..................................... 3.4-252 Inductors on Silicon Substrates . Integrated Transformers

3.4.4 3.4.5 3.4.6

Transmission Lines .................................................... 3.4-258 Diodes and Switches ................................................. 3.4-258 Special Passive Components..................................... 3.4-259

3.4.7

Summary .................................................................... 3.4-260

Joachim N. Burghartz Delft University of Technology

Emerging Passives . Suppression of Parasitic Effects

3.4.1 Introduction Passive components (e.g., resistors, capacitors, inductors, and transformers) and passive devices (e.g., varactors, Schottky diodes, and pin diodes) are integral parts of the functioning and performance of radio-frequency (RF) building blocks [1]. They are used for impedance matching and transformation, in filters, in resonators, in delay lines and baluns, and for many other purposes. In RF front-end circuits they often outnumber the active device count. Unlike in the past, bipolar/BiCMOS and CMOS technologies for communications are limited today to a large extent by the quality and cost of those passive components and devices. Modern wireless communication products increasingly contain integrated passives, i.e., passive components that are engineered by exploiting the structures and materials of the device integration process itself. This is in contrast to the hybrid RF systems that have been used in RF communications for a long time. The reason behind the trend toward integration is not only cost reduction but also the small inductance (0.5 to 10 nH) and capacitance (100 to 1 pF) values needed in the current RF circuits operating at >>1 GHz. The parasitic inductances, capacitances, and resistances of the interconnects are then becoming comparable in value to those of the passive component itself, thus generally lowering the quality of that component. Also, such interconnects with all associated parasitics have to be carefully considered in the circuit design making that task extremely difficult. Placement of passive components off chip into the package or onto the printed circuit board (PCB) as a coplanar waveguide (CPW), a microstrip, or a discrete element is no longer an option as RFs are >1 GHz. Chip integration of passives, however, raises other concerns [2]. At frequencies in the range of about 900 MHz to 2.4 GHz, the inductance and capacitance values needed are considerably large (e.g., for a 50-V impedance; see Figure 3.4.1), thus occupying excessive chip real estate. Since that chip area is cycled through the entire transistor fabrication process on-chip inductors and capacitors are expensive. The total area taken by the inductors can in some circuits occupy nearly 50% of the total chip area. An option, which is sometimes used at frequencies near 1 GHz, is the simulation of a large capacitance or a large inductance by active circuitry. That technique, however, has the disadvantage that it generally leads to higher power and noise. The task of integrating inductors and capacitors is simpler at elevated RF, at which comparably smaller values of inductance and capacitance are required. Figure 3.4.1 illustrates that near 15 GHz, however, inductance values as low as 0.5 nH are needed to represent a 50-V impedance on 3.4-249 © 2006 by Taylor & Francis Group, LLC

3.4-250

The Silicon Heterostructure Handbook

Too large size!

Too small inductance value! Too long transmission line!

2

10

1.5 l = λ/4

1

1

l (mm)

L (nH); C (pF)

wL = 50 W

0.5 1/wC = 50 W 0.1

0

10

20

30

40

50

0

f (GHz)

FIGURE 3.4.1 Inductance and capacitance values needed to represent a 50 V impedance. Microstrip length required for a l/4 transmission line. (From JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Integrated RF passive components — discrete vs. distributed. Proceedings of the Device Research Conference, 2001, pp. 113– 114. With permission.)

chip. Beyond about that value on-chip inductors face the same virtue as their in-package counterparts did at about 1 GHz, i.e., their inductance becomes comparable to that of the interconnects feeding signals into them. At frequencies >15 GHz one, therefore, would like to use inductors and capacitors in a distributed form, i.e., by using CPWs or microstrips, as one used to do on PCB at low RF. In contrast to the lumped passive elements, which had to be smaller than l/10, such transmission line structures need to have a physical size of at least l/4 [3]. That means that the concerns with the size of the on-chip passive components suddenly become stressed again with that migration from lumped to distributed component design. Only at frequencies >30 GHz RF circuit design based on integrated microstrips or CPWs starts to become economically feasible (Figure 3.4.1). In spite of the simplicity of the illustrations in Figure 3.4.1, it becomes obvious that the frequency range from 15 to 30 GHz requires the RF engineer’s ingenuity to be able to come up with solutions to the integration of passive components [4]. In addition to the issue of chip area, any extra process steps required for the integration of the passive components and devices have to be taken into consideration. In a SiGe fabrication process, preference will likely be given to such passive component and device structures that can be integrated by exclusively using process elements from the bipolar transistor integration process (Table 3.4.1). Since most silicon RF integration schemes today are BiCMOS processes, with the SiGe HBT merged into a logic CMOS

TABLE 3.4.1 Types of Passive Components and Devices Listed with the Device Integration Processes, in which They Most Efficiently Can Be Realized Type of Passive Component

Bipolar

CMOS

Add-On

Resistor Capacitor Varactor Diode RF Switch Inductor Transformer Transmission line Resonator or filter

Polysilicon Interdigitated PN Junction

Implanted MOS MOS

Thin Film MIM MEMS Schottky

© 2006 by Taylor & Francis Group, LLC

PN MOS-FET PIN; MEMS Spiral Shielded Spiral Spiral: stacked; bifilar; nested Microstrip; coplanar waveguide LC; SAW

MEMS; FM Core FM Core Micromachined MEMS; BAW

Passive Components

3.4-251

process, the range of such ‘‘free’’ passive components can greatly be expanded, as Table 3.4.1 shows. Nevertheless, there are special passives that require additional process steps or materials. They are adopted if more economic solutions are not satisfactory to the RF circuit designer or if they are instrumental in overcoming a design bottleneck.

3.4.2 Resistors and Capacitors Resistors and capacitors have been a part of silicon fabrication processes for a long time. Resistors are used in bipolar circuits for dc biasing purposes and metal–oxide–silicon (MOS) capacitors are freely available in CMOS and BiCMOS processes. Resistors can be integrated in three basic forms, i.e., as an implanted or diffused component, as a polysilicon resistor, and as a thin-film metal element (Table 3.4.1). In bipolar processes sheet resistances ranging from 10 to 10,000 V/sq. can be realized by exploiting either the diffused regions (buried layer, intrinsic base) or the polysilicon films (extrinsic base, emitter). In BiCMOS processes, the well and channel stopper diffusions can also be used in order to cover the sheet resistance range from 100 to 1000 V/sq. Implanted and diffused resistors, however, are not well suited for RF circuit design because the junction isolation leads to a considerably large-shunt capacitance that is bias dependent. Polysilicon resistors work better in that respect since they are separated from the silicon substrate by the field oxide, leading to a much smaller shunt capacitance. The sheet resistance of doped polysilicon, however, varies with the polygrain structure and the dopant distribution between grains and grain boundaries. This results in a typically much larger statistical variation of the sheet resistance compared to implanted or diffused resistors [5]. The best results can be achieved with metal thin-film resistors that are imbedded into the multilevel interconnect stack [6] by, however, investing an extra masks layer and additional process steps (Table 3.4.1). The good electrical isolation of poly and metal thin-film resistors from the silicon substrate, however, causes that such resistors are also thermally isolated due to the poor thermal conductivity of the SiO2. A small temperature coefficient is therefore another aspect in selecting the optimum resistor structure for RF applications. Capacitors can be integrated as an interdigitated metal structure, an MOS structure, or a metal– insulator–metal (MIM) structure. The interdigitated capacitor is adopted from III-V monolithic microwave integrated circuit (MMIC) technology, where it is useful since often only one interconnect layer is available. Since this is not an issue in silicon technology and because the capacitance or area is very small in comparison to that of the MOS and the MIM capacitors, the interdigitated capacitor is not used in SiGe MMICs. MOS capacitors have the same disadvantage as the mentioned implanted or diffused resistors, i.e., a considerable portion of the RF signal flows through the silicon substrate. Also, one terminal is built in silicon causing a relatively high series resistance, thus lowering the quality of the RF capacitor. Nevertheless, MOS capacitors have the comparably highest capacitance/area so that they are used in special applications, such as for dc blocking. The most favorable RF capacitor is the MIM structure since both terminals are built in metal and the structure has good oxide isolation from the substrate. A lumped-element model of an MIM capacitor is shown in Figure 3.4.2. The figure-of-merit of an RF capacitor is the quality factor (Q), which is defined as the ratio of the stored and the dissipated energies, i.e., QC ¼ im(Z)/re(Z), with Z the impedance of the component. It is obvious that the Q-factor will become lower as the frequency is increased, because the impedances of the lumped capacitors drop with frequency so that an increasing fraction of the total energy applies to dissipation at the resistors (see Figure 3.4.2). A second concern is self-resonance. The resonance frequency (fSR) is set by the parasitic series inductance LS and (primarily) CP and should be sufficiently larger than the desired operating frequency. Apart from the types and thicknesses of metal and dielectric layers available with a particular fabrication process layout optimization is effective in optimizing for Q and fSR [7]. Figure 3.4.3 illustrates that a finger layout with a high aspect ratio leads to both an increased Q and a higher fSR. A multifinger layout rather than one single finger can be used to best fit the MIM capacitor into the RF circuit layout. Another issue, besides layout optimization, is the accurate compact modeling of the capacitor. Figure 3.4.4 shows an example of the optimum 1.3-pF MIM capacitor layout from Figure 3.4.3, which is well applicable up to 10 GHz. The compact model with parameters shown in the insert of

© 2006 by Taylor & Francis Group, LLC

3.4-252

The Silicon Heterostructure Handbook

CP

P1

LS COx

CB

P2

RS RP

RB

COx RB

CB

Sub*

FIGURE 3.4.2 Compact model of an integrated capacitor. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) 100

MIM Capacitors: Areas from 10⫻194 mm2 to 80⫻24.5 mm2

4 3

80

Finger ratio increase

Q

60 40

2 1

Quality factor

Capacitance (pF)

5

20

C 0

0 0

2

4

6

8

10

Frequency (GHz)

FIGURE 3.4.3 Measured capacitances and quality factors of multifinger MIM capacitors with varied finger aspect ratios. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

Figure 3.4.4 is derived from the general MIM capacitor model in Figure 3.4.2 with simplifications by neglecting RP and CB.

3.4.3 Inductors and Transformers Inductors on Silicon Substrates Design and Compact Modeling Inductors, in contrast to capacitors and resistors, are fairly new passive components in silicon technology. In 1990, Nguyen and Meyer [8] were the first to place a spiral coil (Figure 3.4.5) over a conductive, and thus lossy, silicon substrate. The Q of a spiral inductor (QL ¼ þim(Z)/re(Z)) hardly reached Q ¼ 5 in the early attempts in spite of extensive knowledge in spiral inductor design from III-V MMICs and PCB implementations. As rough guidelines, the ratio of outer (R) to inner (Ri) coil radius should be R/Ri ¼ 5 for a maximum Q value and the maximum radius should not exceed l/60 to avoid distributed effects [3]. The fact that in silicon technology the inductor coil is placed over a conductive substrate is the main cause of the difficulties to reach appropriate Qs. The primary parameter set to define a spiral inductor on silicon (without the underpath) thus includes the conductor width (W) and space (S), the number of turns (N), the coil radius (R), the metal thickness (TM) and resistivity (rM), the thickness (TOx) and permittivity («Ox) of the dielectric layer between coil and silicon, and the resistivity (rSi), permittivity («Si), and thickness (TSi) of the silicon substrate (Figure 3.4.5). In addition, the specifica-

© 2006 by Taylor & Francis Group, LLC

3.4-253

Passive Components

100

10 0.04 nH

MIM-Cap

0.7 Ω

1.37 pF

Capacitance (pF)

6

0.026 pF 15 Ω

60

Sub

40

Q 4

C

2

Quality factor

80

8

20

0

0 2

0

4

6

8

10

Frequency (GHz)

FIGURE 3.4.4 Measured and modeled frequency dependence of capacitance and quality factor of an optimized multifinger MIM capacitor (model with parameters in inset). (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) N rM

eOx TM R TOx

TSi

W

S

rSi, e Si

FIGURE 3.4.5 Cross section of a spiral inductor on silicon, defined by the width (W) and space (S) of the metal conductor, the number of turns (N), the outer radius of the coil (R), the metal resistivity (rM), the metal thickness (TM), the distance of the spiral coil from the silicon substrate (TOx), the oxide permittivity («Ox), the thickness of the silicon substrate (TSi), and the permittivity («Si) and resistivity (rSi) of the silicon. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

tions of the underpath that connects the inner coil terminal to the outside have to be considered, though play a minor role in most designs. The limitation in Q is a result of ohmic losses and parasitic capacitances in the coil and in the substrate, as illustrated in the compact model in Figure 3.4.6. There, the electrical characteristics of the spiral coil are represented by LS*, RS, and CP. The dielectric isolation between coil and substrate is modeled by COx, and the substrate is described by RB and CB. The elements LE, RE, and M are used to illustrate the effect of eddy currents in the substrate, which become noticeable only for a high silicon conductivity. The resistor RSub describes the effect of a planar substrate contact on the inductor characteristics. First, we discuss the situation for RSub ! 1 (no

© 2006 by Taylor & Francis Group, LLC

3.4-254

The Silicon Heterostructure Handbook

CP POut COx RSub CB

PIn

R LS*=LS−M S M

COx

LE−M RE RShield

RB

RB

CB

Sub Sub*

FIGURE 3.4.6 Compact model of an integrated inductor. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.) 25

60 Qmax

sse

rate

15

los

ses

10

f(Qmax)

5

L

10 0 0

Quality factor

bst

il lo

30 20

20 Su

s

40

Co

Inductance (nH)

50

1

2 3 Frequency (GHz)

4

5

0

FIGURE 3.4.7 Inductance and quality factor of an integrated inductor versus frequency. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

substrate contact) and RE ! 1 (no substrate eddy currents, i.e., M ¼ 0; LS* ¼ LS). If a low-frequency bias is applied between the inductor terminals (POut, PIn in Figure 3.4.6) the RF signal primarily passes through the inductance LS and the resistance RS, because the impedance vLS is small and the impedances 1/vCP and 1/vCOx are large. The quality factor increases then as Q ¼ vLS/RS, which is shown in Figure 3.4.7. With increasing frequency a larger fraction of the RF signal passes through the substrate since vLS becomes larger, 1/vCOx becomes smaller, and because COx >> CP (TOx << R). As a result, a maximum Q-factor (Qmax) appears at a particular frequency f (Qmax), as shown in Figure 3.4.7. It is obvious that the inductor design should aim for optimizing Qmax at the operating frequency, i.e., f0 ¼ f (Qmax), through tailoring coil and substrate losses. Furthermore, self-resonance should occur sufficiently above f (Qmax). This can be achieved by preventing from resonance via COx so that the much smaller CP leads to a high fSR, as achieved for the sample 10-nH inductor in Figure 3.4.7. The metal losses in the spiral coil can be lowered by shunting several layers of the multilevel interconnects together to arrive at an effectively thicker conductor, as first shown by Soyuer et al. [9, 10]. Local thickening of the top metal layer is another economic means to reduce the coil losses [11]. Other design concepts address the skin effect that leads to an increased coil resistance at increased frequency. While the skin effect from the magnetic field caused by the current through a conductor itself cannot significantly be reduced, the skin effect from a magnetic field caused by current flow through a neighboring conductor can well be minimized. The latter effect is experienced as crowding of the current to the conductor edges. That means that at high RF a large conductor width (W) may not be

© 2006 by Taylor & Francis Group, LLC

3.4-255

Passive Components

as effective as a sufficient conductor spacing (S). Furthermore, eddy currents can be caused in particular in the inner metal turns so that hollow coils [12] or smaller conductor width at the inner turns [13] can result in reduced losses. The coil design also affects the interturn capacitance (CP1) and the capacitance between spiral coil and underpath (CP2), which both contribute to CP ¼ CP1 þ CP2 that affects the fSR of the inductor. The coil design discussed so far has been restricted to a spiral coil consisting of a continuous metal conductor at the same interconnect layer. By alternating between interconnect layers less current crowding [14] and a higher resonance frequency [15] can be achieved particularly for large inductances. Also, multilayer inductor structures, providing higher inductance/area figures then become feasible [16, 17]. Substrate Effects and Shields The substrate resistivity can have distinct effects on the inductor characteristics, as illustrated in Figure 3.4.8 for a simulated 2-nH inductor, varying only the silicon resistivity. For resistivities above 10 V cm both Qmax and f (Qmax) increase steadily toward higher resistivity. This so-called ‘‘inductor mode’’ of operation relates to what we had discussed above and the sample inductor in Figure 3.4.7. In the range of 0.1 to 10 V cm the component operates in the ‘‘resonator mode’’ because then self-resonance occurs via the substrate, i.e., COx. With COx >> CP, fSR shows a pronounced decay, which causes that fSR >> f (Qmax) is no longer valid and the component operates as a resonator rather than an inductor. That

Resonator mode regime

Eddy current regime

Inductor mode regime

x 5

L (Q max) (nH)

(a)

20

Qmax

10

f(Qmax)

0

0

6

25

5

20

4

fSR

15 L(Q max)

3

10

2

5

1 0 0.001 (b)

fSR (GHz)

Qmax

10

f (Qmax) (GHz)

30

15

0 0.1

10

1000

Silicon resistivity (Ω-cm)

FIGURE 3.4.8 Maximum quality factor (Qmax), frequency at Qmax (f (Qmax)), inductance (L(Qmax)), and resonant frequency (fSR) of an integrated inductor as a function of substrate resistivity with indication of the three characteristic modes of operation. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.4-256

The Silicon Heterostructure Handbook

means, however, that the design direction becomes distinctly different. Now, not an increase but a reduction in substrate resistivity leads to a higher Qmax. The Q of the resonator namely depends on both the qualities of the lossy inductor coil (QL ¼ vLS/RS) and the lossy oxide capacitor (QC ¼ 1/vRBCOx). The QC is increased by lowering the substrate resistivity and thus RB. It can be seen from Figure 3.4.8 that, surprisingly, somewhat higher Qmax values can be achieved in comparison to a 10 V cm substrate resistivity, particularly if eddy currents in the substrate can be suppressed. (Note that these three modes of operation of a spiral coil structure are closely related, but not identical, to the TEM, slow wave, and eddy current modes of a microstrip as described by Hasegawa et al. [18].) While eddy currents cannot, or at least not easily, be suppressed in the low-resistivity silicon, operation in resonator mode with suppressed eddy currents can be enforced by inserting a patterned ground shield in between the spiral coil and the silicon substrate [19]. Figure 3.4.9 shows the Qmax and the fSR of the 2-nH inductor (from Figure 3.4.8) with a patterned ground and the shield resistivity as the only parameter, showing that Qmax can be raised by 50% while sacrificing fSR. The effect of a patterned ground shield can be modeled by the resistor RShield in the compact model of Figure 3.4.6. Inductor Optimization The optimization of inductors on silicon is extensively discussed in a review paper by Burghartz and Rejaei [20]. In Figure 3.4.10, the Qmax values achievable for a wide range of inductances are shown for a conventional Al metallization and substrate resistivity for thick Cu interconnects in combination with high-resistivity silicon (HRS). There is a general trend that large inductance values combine typically with considerably lower Qs than small inductances. This is a result of the larger area needed to accomplish large inductances and the consequently lower impedance of the substrate leakage path (COx, CB, RB in Figure 3.4.6). Another consequence is that with larger inductance values Qmax appears at a lower frequency f (Qmax). This does not appear to be an issue in RF circuit design since at higher frequencies the required inductance values are smaller and the Qs needed are larger. The last feature from Figure 3.4.6 to be discussed is the effect of a substrate contact. Clearly, a uniform ground potential underneath the inductor coil would provide the best possible electrical symmetry of the component, except for the small geometrical asymmetry of the coil itself [21]. In silicon technology, however, only planar substrate contacts can be used to bias the silicon substrate. It has been shown that, if such a planar substrate contact is positioned close to the coil, the inductor would become electrically

40

16 Eddy currents QMax No eddy currents

30 fSR

8

20

4

10

fSR (GHz)

12 Qmax

rSi = 10 Ω-cm

rShield 0 0.0001

0.01

1

100

0 10,000

Shield resistivity (Ω-cm)

FIGURE 3.4.9 Maximum quality factor (Qmax) and resonant frequency (fSR) of an integrated inductor with patterned ground shield as a function of the resistivity of the shield metal. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.4-257

Passive Components

Maximum quality factor

100 SAM

4 µm Cu+ 3 kΩ-cm Si

10

1µm Al+ 5 Ω-cm Si 1 1

10 Inductance (nH)

100

FIGURE 3.4.10 Maximum quality factor (Qmax) versus inductance of spiral inductors built in a conventional aluminum interconnect process or with copper metallization on a high-resistivity silicon substrate. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

asymmetric. The substrate contact thus has to be considered in the circuit layout [22]. Only an RF ground plane underneath the coil can eliminate this asymmetry, provided that the ground plane is spaced away sufficiently to prevent from eddy current effects [23, 24]. That sensitivity of the inductor characteristics to eddy currents in nearby metal features also prevents one from placing other circuit components inside the large spiral coil or from building the coil over other circuitry [25], except if micromachining techniques are adopted (Section 3.4.6). Accurate modeling of the spiral inductor structure is another important task. While the compact model in Figure 3.4.6 is already sufficiently accurate, it has the restriction of being nonpredictive. An extensive review of predictive inductor models [26–29] is included in Ref. [30].

Integrated Transformers Transformers have been used in RF circuits since the early days of telegraphy. Conceptually, a transformer consists of two spiral coils that are brought in close proximity to achieve mutual magnetic coupling. Figure 3.4.11 shows the three generic types of transformers that are conceivable, i.e., the stacked (Finlay) type, the bifilar (Shibata resp. Frlan) type, and the nested coil type [31, 32]. The mutual coupling, which is a first indication of quality of a transformer, is higher for the stacked coils than that of the bifilar structure, which again is higher than that of the nested coils [32]. The strong mutual coupling, however, also results in a large parasitic capacitance between the coils, which affects the bandwidth of the transformer by making the mutual coupling of the coils partly capacitive. The maximum available gain (Gmax), as used for RF transistors [3], is a useful figure-of-merit of a transformer [32], since it is independent of the port impedances. A good transformer should obviously have both high Gmax and large bandwidth. In that respect, the stacked coils provide the best results in comparison, followed by the bifilar and the nested types [33]. Stacked coils also consume minimum chip area but require three interconnect layers instead of two needed to fabricate the other types. Obviously, if capacitive coupling between the coils has a detrimental effect on the transformer Gmax and bandwidth, substrate effects will play a considerable role and will degrade the transformer in both aspects [32]. Substrate effects are minimum for the stacked coil configuration. Interestingly, a patterned metal ground shield can provide a slightly increased Gmax and bandwidth [32]. The bifilar coil type is most suitable for the design of multifilament, balun, and symmetric transformers, as extensively discussed in a review paper by Long [31] and in a book by Niknejad and Meyer [34].

© 2006 by Taylor & Francis Group, LLC

3.4-258

The Silicon Heterostructure Handbook

Bifilar coils (Shibata)

Stacked coils (Finlay)

Nested coils Bifilar coils (Frlan)

FIGURE 3.4.11 Plan view sketches of generic transformer structures. (From JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. With permission.)

3.4.4 Transmission Lines At frequencies beyond about 30 GHz inductances and capacitances have to be integrated as distributed elements (Figure 3.4.1). This requires the fabrication of transmission lines on a lossy silicon substrate either as a CPW or as a microstrip. Both types of lines have been used on PCB or in III–V MMICs. In silicon technology, however, CPWs suffer from considerable losses in the conductive silicon substrate and microstrips are difficult to integrate due to lack of a through-substrate via process in conventional silicon technology. During the past decade these issues have been circumvented and addressed, respectively, by building microstrips in the multilevel interconnects away from the substrate [35] and by fabricating CPWs over HRS [36]. The small vertical spacing of signal and ground planes of microstrips built in the multilevel interconnects leads to a comparably narrow required width of the signal line, thus raising ohmic losses and the overall attenuation of the line. A wider signal line for reduced losses is feasible if the ground plane is integrated into the silicon substrate. This, however, requires micromachining techniques [37] (see also Section 3.4.6). In that case, as for the CPWs, HRS substrates have to be used to suppress the losses in the silicon. Then, particularly for the CPW, the passivation of the silicon near the Si–SiO2 interface is crucial to be able to minimize those losses [38]. The attenuation figures achieved for transmission lines on silicon substrates are in the range of 2 to 5 dB/cm at 10 GHz, depending on the metal type and thickness and on the silicon resistivity. With the passivation the attenuation can be about tenfold improved.

3.4.5 Diodes and Switches There are several types of diodes that can be applied in RF and microwave applications. Varactors are used, for example, in voltage-controlled oscillators (VCO) and can be built as pn-junction [7] and MOScapacitor type components [39]. The pn-junction varactor can directly be derived from the collector– base junction structure of the bipolar transistor. The component can be modeled by using the scheme in Figure 3.4.2. The challenge in integrating a varactor on a silicon substrate is to achieve a maximum capacitance/area with minimum parasitic resistances and inductances of the terminals and the internal metallization, leading to a multifinger structure as the optimum layout of the component [7]. For

© 2006 by Taylor & Francis Group, LLC

3.4-259

Passive Components

60

5 A= 2 ⫻ 15 ⫻ 27.75 µm2

4 Capacitance (pF)

Varactor (pn junction): 50 40

3 30

Bias increase

2

C 20

1

Quality factor

Q

10

0 0

2

4 6 Frequency (GHz)

8

0 10

FIGURE 3.4.12 Measured capacitances and quality factors of multifinger pn-junction MIM capacitors with varied reverse bias. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

varactors used in the 900 MHz to 2.4 GHz range the multifinger design provides Qs in the range of 20 to 50 (Figure 3.4.12), which is quite sufficient considering the limited Qs of the inductors in the LC tank of the VCO. Diodes, more specifically p–i–n diodes, are used in RF switches, particularly the transmit– receive (T–R) switch at the antenna of the RF transceiver [40]. A p–i–n diode works as a bias-controlled resistor with excellent linearity and distortion and has also been applied in microwave circuits to amplitude modulation, attenuation, and signal leveling. In addition to their use in RF switches, they also make excellent phase shifters and limiters [3]. The integration of p–i–n diodes in silicon processes, however, is difficult since they are typically built as vertical devices by exploiting the entire wafer thickness. Therefore, as the MESFET switch in III–V technology, it is possible to consider MOSFET switches in silicon technology, but they have an inferior insertion loss and isolation and they consume more chip area compared to their III–V contenders [41]. The third type of switch device that is considered for silicon technology is the MEMS switch [42], which appears to be only a technological option in applications where the p–i–n and MOS switches cannot meet the required specifications. A third type of diode that is well integratable in silicon technology is the Schottky rectifier, which can reach cutoff frequencies well in excess of 100 GHz [3, 43].

3.4.6 Special Passive Components Emerging Passives With the trend toward fully monolithic RF transceivers novel materials and structures are now introduced to silicon technology. Introducing them as an addition to the core device integration process is a favorable concept for economic reasons [44]. Micromachining and MEMS can be used to greatly increase the quality of passive components [37, 45, 46] or to integrate large components above [46] or below the active devices into the bulk silicon substrate [37]. Micromachining can also be used to establish an RF ground plane in silicon process technology [37] (see ‘‘Substrate Effects and Shields’’). The enhancement in component quality is quite pronounced in mechanical resonators [47], mechanically variable capacitors [48], and RF MEMS switches (Section 3.4.5). Ferromagnetic thin films can be instrumental in reducing the size of inductors and transformers and to realize novel-integrated RF passive components [49, 50]. The integration of bulk-acoustic wave filters

© 2006 by Taylor & Francis Group, LLC

3.4-260

The Silicon Heterostructure Handbook

[51] and tunable passives becomes possible by using ferroelectric thin films on silicon [52]. In this way, other microwave components known from the hybrid technologies may be brought to silicon technology by exploiting integratable ferromagnetic and ferroelectric thin films [49]. On-chip antenna is another passive component that may gain significance in the emerging fields of integrated microwave sensors [53], unobtrusive radio devices [54], and for intrachip [55] and chip–chip signal transmission [56].

Suppression of Parasitic Effects In addition to the desired passive components there are parasitic effects that affect the characteristics of an integrated RF circuit. RF currents through the electrically conducting silicon substrate [37], electromagnetic coupling between integrated inductors and to the package [23, 25], and thermal coupling through the silicon [57] are such parasitic effects that are undesirable since they are difficult to model and are detrimental to the circuit performance. Such parasitic effects, therefore, have to be carefully considered in the circuit layout [58]. Isolation techniques available with conventional silicon process technology, however, are not sufficiently effective at RF and microwaves [59]. Novel structures to block or to ground such crosstalk signals between RF circuit elements are therefore required. Availability of an RF ground plane with a via connection to the wafer frontside is, therefore, a valuable addition to any RF silicon integration process (see also Section 3.4.4) [37]. In addition to the unwanted crosstalk signals to an RF ground, crosstalk can also be lowered to some extent by increasing the silicon substrate resistivity and the spacing between source and drain of the parasitic RF signals. Overly, high substrate resistivity, however, does not provide any benefit as far as the crosstalk goes, since then the substrate characteristics are fully capacitive and in TEM mode [18, 60]. Then, local replacement of the silicon by a low-permittivity material will have the effect of a virtual increase of the length of the crosstalk path. This can, for example, be achieved by etching trenches through the entire substrate [37].

3.4.7 Summary In this chapter, we have given a broad overview of the passive components and devices required for RF silicon integration processes. The discussion has been restricted to passives that are integrated on the chip, but with highlighting the criteria that favor the integration of passive components over off-chip or in-package solutions. The effect of parasitics on the quality and the characteristics of passive components, as well as on the coupling between passives, have been addressed as well. Among the passive components and devices, the spiral inductor on silicon has particularly been highlighted in the discussions, because this component is still fairly new to silicon technology, it limits the performance and power consumption of RF circuits, and it consumes a considerable fraction of the costly chip area. The discussion of other passive components and devices, as well as of parasitic effects, has been kept brief but combined with an extensive reference list. All in all, it can be stated that passive components and devices are an integral, if not dominant, part of monolithic RF silicon technology.

Acknowledgments The author would like to thank his colleagues at the Laboratory of High-Frequency Technology and Components (HiTeC) at DIMES, TU Delft, and his former colleagues at IBM Research and IBM Microelectronics for the many stimulating discussions on aspects of RF silicon technology. This applies particularly to Dr. Behzad Rejaei (HiTeC), Dr. Mehmet Soyuer (IBM), and Dr. Keith Jenkins (IBM).

References 1. LE Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip.’’ IEEE Transactions on Electron Devices 50:683–699, 2003.

© 2006 by Taylor & Francis Group, LLC

Passive Components

3.4-261

2. JN Burghartz. Silicon RF technology — The two generic approaches. Proceedings of the European Solid-State Device Research Conference (ESSDERC), 1997, pp. 143–153. 3. I Bahl and P Barthia. Microwave Solid State Circuit Design. New York, NY: John Wiley & Sons, 1988. 4. JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Integrated RF passive components — discrete vs. distributed. Proceedings of the Device Research Conference, 2001, pp. 113–114. 5. A Schuppen, H Dietrich, S Gerlach, H Hohnemann, J Arndt, U Seller, R Gotzfried, U Erben, and H Schumacher. SiGe-technology and components for mobile communication systems. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1996, pp.130–133. 6. R Henderson, P Zurcher, A Duvallet, C Happ, M Petras, M Raymond, T Remmel, D Roberts, B Steimle, S Straub, T Sparks, M Tarabbia, and M Miller. Tantalum nitride thin film resistors for integration into copper metallization based RF-CMOS and BiCMOS technology platforms. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2001, pp. 71–74. 7. JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. 8. NM Nguyen and RG Meyer. IC-compatible inductors and LC passive filters. IEEE Journal of SolidState Circuits 25:1028–1031, 1990. 9. M Soyuer, JN Burghartz, KA Jenkins, S Ponnapalli, JF Ewen, and WE Pence. Multilevel monolithic inductors in silicon technology. Electronics Letters 31:359–360, 1995. 10. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 11. JN Burghartz and B Rejaei. Saddle add-on metallization for RF-IC technology. IEEE Transactions on Electron Devices 51:460–466, 2004. 12. J Crols, P Kinget, J Craninckx, and M Steyaert. An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz. Digest of Technical Papers of the Symposium on VLSI Circuits, 1996, pp. 28–29. 13. JM Lopez-Villegas, J Samitier, C Cane, and P Losantos. Improvement of the quality factor of RF integrated inductors by layout optimization. Technical Digest of the Radio Frequency Integrated Circuits (RFIC) Symposium, 1998, pp. 169–172. 14. LF Tiemeijer, D Leenaerts, N Pavlovic, and RJ Havens. Record Q spiral inductors in standard CMOS. Technical Digest of the International Electron Devices Meeting (IEDM), 2001, pp. 949–951. 15. HB Erzgra¨ber, M Pierschel, GG Fischer, T Grabolla, and A Wolff. High performance integrated spiral inductors based on a minimum AC difference voltage principle. Digest of Technical Papers of the Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 71–74. 16. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors Using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 17. RB Merrill, TW Lee, Y Hong, R Rasmussen, and LA Moberly. Optimization of high Q integrated inductors for multi-level metal CMOS. Technical Digest of the IEEE International Electron Devices Meeting, 1995, pp. 983–986. 18. H Hasegawa, F Mieko, and Y Hisayoshi. Properties of microstrip line on Si–SiO2 system. IEEE Transactions on Microwave Theory and Techniques 19:869–881, 1971. 19. CP Yue and SS Wong. On-chip spiral inductors with patterned ground shields for Si-based RF ICs. IEEE Journal of Solid-State Circuits 33:743–752, 1998. 20. JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. 21. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. 22. JN Burghartz, AE Ruehli, KA Jenkins, M Soyuer, and D Nguyen-Ngoc. Novel substrate contact structure for high-Q silicon-integrated spiral inductors. Technical Digest of the IEEE International Electron Devices Meeting, 1997, pp. 55–58.

© 2006 by Taylor & Francis Group, LLC

3.4-262

The Silicon Heterostructure Handbook

23. JN Burghartz. Progress in RF inductors on silicon-understanding substrate losses. Technical Digest of the International Electron Devices Meeting, 1998, pp. 523–526. 24. KT Ng, NP Pham, PM Sarro, B Rejaei, and JN Burghartz. Characterization of a bulk-micromachined post-process module for silicon RF technology. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 99–102. 25. JN Burghartz, DC Edelstein, M Soyuer, HA Ainspan, and KA Jenkins. RF circuit design aspects of spiral inductors on silicon. IEEE Journal of Solid-State Circuits 33:2028–2034, 1998. 26. JR Long and MA Copeland. Modeling of monolithic inductors and transformers for silicon RFIC design. In Microwave Symposium Digest (Technologies for Wireless Applications), 1995, pp. 129–134. 27. CP Yue, C Ryu, J Lau, TH Lee, and SS Wong. A physical model for planar spiral inductors on silicon. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1996, pp. 155–158. 28. AM Niknejad and RG Meyer. Analysis, design, and optimization of spiral inductors and transformers for Si RF Ics. IEEE Journal of Solid-State Circuits 33:1470–1481, 1998. 29. B Rejaei, JL Tauritz, and P Snoeij. A predictive model for Si-based circular spiral inductors. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 1998, pp. 148–154. 30. JN Burghartz. Spiral inductors on silicon — Status and trends. International Journal of RF and Microwave Computer-Aided Engineering 8:422–432, 1998. 31. JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. 32. KT Ng, B Rejaei, and JN Burghartz. Substrate effects in monolithic RF transformers. IEEE Transactions on Microwave Theory and Techniques 50:377–383, 2002. 33. KT Ng, B Rejaei, TR deKruiff, M Soyuer, and JN Burghartz. Analysis of generic spiral–coil RF transformers on silicon. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp.103–107. 34. AM Niknejad and RF Meyer. Design, Simulation, and Applications of Inductors and Transformers for Si RF ICs. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2000. 35. DC Laney, LE Larson, P Chan, J Malinowski, D Harame, S Subbanna, R Volant, and M Case. Microwave transformers, inductors and transmission lines implemented in an Si/SiGe HBT process. IEEE Transactions on Microwave Theory and Techniques 49:1507–1510, 2001. 36. HH Meinel. Millimeter-wave technology advances since 1985 and future trends. IEEE Transactions on Microwave Theory and Techniques 39:759–767, 1991. 37. NP Pham, PM Sarro, KT Ng, and JN Burghartz. IC-compatible two-level bulk micromachining process module for RF silicon technology. IEEE Transactions on Electron Devices 48:1756–1764, 2001. 38. B Rong, JN Burghartz, LK Nanver, B Rejaei, and M vanderZwan. Surface-passivated high-resistivity silicon substrates for RFICs. IEEE Electron Device Letters 25:176–178, 2004. 39. WMY Wong, PS Hui, C Zhiheng, S Keqiang, J Lau, and PCH Chan. A wide tuning range gated varactor. IEEE Journal of Solid-State Circuits 35:773–779, 2000. 40. RH Caverly. RF technique for determining ambipolar carrier lifetime in PIN RF switching diodes. Electronics Letters 34:2277–2278, 1998. 41. RH Caverly. Linear and nonlinear characteristics of the silicon CMOS monolithic 50-V microwave and RF control element. IEEE Journal of Solid-State Circuits 34:124–126, 1999. 42. GM Rebeiz. RF MEMS: theory, design, and technology. New York, NY: John Wiley & Sons, 2003. 43. KM Strohm, J Buechler, and E Kasper. SIMMWIC rectennas on high-resistivity silicon and CMOS compatibility. IEEE Transactions on Microwave Theory and Techniques 46:669–676, 1998. 44. JN Burghartz, M Bartek, B Rejaei, PM Sarro, A Polyakov, NP Pham, E Boullaard, and KT Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2002, pp. 17–23.

© 2006 by Taylor & Francis Group, LLC

Passive Components

3.4-263

45. KJ Herrick, JG Yook, and LPB Katehi. Microtechnology in the development of three-dimensional circuits. IEEE Transactions on Microwave Theory and Techniques 46:1832–1844, 1998. 46. JB Yoon, YS Choi, BI Kim Y Eo, and E Yoon. CMOS-compatible surface-micromachined suspendedspiral inductors for multi-GHz silicon RF Ics. Electron Device Letters, IEEE 23:591–593, 2002. 47. JR Clark, WT Hsu, and CT Nguyen. High-Q VHF micromechanical contour-mode disk resonators. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2000, pp. 493–496. 48. M Bakri-Kassem and RR Mansour. Two movable-plate nitride-loaded MEMS variable capacitor. IEEE Transactions on Microwave Theory and Techniques 52:831–837, 2004. 49. B Rejaei, M Vroubel, Y Zhuang, and JN Burghartz. Assessment of ferromagnetic integrated inductors for Si-technology. Digest of Papers of the topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 100–103. 50. MG Allen. MEMS technology for the fabrication of RF magnetic components. IEEE International Magnetics Conference, 2003, pp. FC-05. 51. M Ylilammi, J Ella, M Partanen, and J Kaitila. Thin film bulk acoustic wave filter. IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control 49:535–539, 2002. 52. KA Jose, H Yoon, KJ Vinoy, P Sharma, VK Varadan, and V Varadan. Low voltage tunable capacitors for RF MEM filters and antenna applications. Digest of the International Symposium on Antennas and Propagation, Vol. 3, 2001, pp. 670–673. 53. P Russer. Si and SiGe millimeter-wave integrated circuits. IEEE Transactions on Microwave Theory and Techniques 46:590–603, 1998. 54. E Aarts. Ambient intelligence: A multimedia perspective. IEEE Multimedia 11:12–19, 2004. 55. BA Floyd, H Chih-Ming Hung, KK O. Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE Journal of Solid-State Circuits 37:543–552, 2002. 56. JJ Lin, L Gao, A Sugavanam, X Guo, R Li, JE Brewer, and KK O. Integrated antennas on silicon substrates for communication over free space. IEEE Electron Device Letters 25:196–198, 2004. 57. BM Tenbroek, MSL Lee, W Redman-White, RJT Bunyan, and MJ Uren. Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE Journal of Solid-State Circuits 33:1037– 1046, 1998. 58. T Blalack, Y Leclercq, and CP Yue. On-chip RF isolation techniques. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, 2002, pp. 205–211. 59. KA Joardar. A simple approach to modeling cross-talk in integrated circuits. IEEE Journal of SolidState Circuits 29:1212–1219, 1994. 60. M Pfost, HM Rein, and T Holzwarth. Modeling substrate effects in the design of high-speed Si-bipolar Ics. IEEE Journal of Solid-State Circuits 31:1493–1501, 1996.

© 2006 by Taylor & Francis Group, LLC

3.5 Industry Examples at the State-of-the-Art: IBM

Alvin J. Joseph and James S. Dunn IBM Microelectronics

3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6

Introduction............................................................... 3.5-265 BiCMOS Process Integration ................................... 3.5-265 The SiGe HBT — Key Technology Elements.......... 3.5-269 Electrical Performance .............................................. 3.5-270 Manufacturability ...................................................... 3.5-276 Summary .................................................................... 3.5-280

3.5.1 Introduction The general market acceptance of SiGe BiCMOS technologies can be attributed to the ability to address the product performance at a very competitive cost by integrating high-performance SiGe HBTs, with state-of-the-art CMOS, and high-quality passives. SiGe HBTs have shown to be highly reliable even under extreme stress conditions [1, 2] and give superior yields compared to other compound semiconductor technologies (e.g., GaAs). It is not surprising, therefore, to see SiGe BiCMOS technologies in mass production that range in various applications, such as wireless, storage, and instrumentation [3, 4]. SiGe BiCMOS technologies offer the flexibility to be optimized based on the specific market applications. For example, performance focus applications such as wired, automotive, and instrumentation require ultrahigh-performance SiGe HBTs. Integrating a simplified low-cost SiGe HBT is the focus, however, for consumer applications such as wireless and storage. Therefore, a ‘‘one size fits all’’ approach for technology optimization will not be optimal to address various market segments due to significant tradeoffs one has to make on either performance or cost. The IBM SiGe BiCMOS technology roadmap addresses these wide-ranging applications by offering two flavors of SiGe HBTs. State-of-the-art examples of IBM SiGe BiCMOS technologies at 0.13 mm CMOS node will be discussed in detail in this section. SiGe BiCMOS 8HP is a technology which features a 200/275 GHz (fT/fmax) SiGe HBT with passives and back-end-of-the-line (BEOL) metallurgy tailored for applications in the 77 GHz range. Technology optimization in this case centers around the performance of the SiGe HBT. SiGe BiCMOS 8WL technology features a 100/200 GHz (fT/fmax) SiGe HBT with 0.5 dB minimum noise figure (NFMIN) at 10 GHz with wide range of active and passive devices that support cost-sensitive consumer applications. In this case, the technology optimization focus shifts to reducing process complexity (or cost) while maintaining adequate SiGe HBT performance.

3.5.2 BiCMOS Process Integration The state-of-the-art BiCMOS process integration approach falls into the category of a base-after-gate (BAG) method, where the base of the SiGe HBT is built after the bulk of the CMOS processing is completed 3.5-265 © 2006 by Taylor & Francis Group, LLC

3.5-266

The Silicon Heterostructure Handbook

BiCMOS 8HP 0.13 µm CMOS Backbone

Shallow trench

BiCMOS 8WL

Bipolar

Subcoll., Nepi, Deep Trench

0.13 µm CMOS Backbone

Shallow trench

Coll. reachthru Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

S/D implant, anneal, Resistor salicide block

Base window, collector pedestal, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

Bipolar

Subcollector I/I Base window, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

S/D Implant, anneal, Resistor salicide block Custom trench

Salicide and contacts Salicide and contacts

Metal interconnect Custom analog metals

Metal interconnect

Custom analog metals

FIGURE 3.5.1 Process flow comparing both BiCMOS 8HP and BiCMOS 8WL in a 0.13 mm CMOS backbone.

[5]. This approach is chosen to minimize the thermal budget for the SiGe HBT. Figure 3.5.1 shows the integration flows utilized in the 0.13 mm IBM SiGe BiCMOS processes. Both 8HP and 8WL process flow use the 0.13 mm CMOS backbone with the addition of bipolar and custom BEOL analog metals. Process flows deviate between 8HP and 8WL due to the tradeoff associated with the bipolar performance. The process flow starts with the formation of the NPN subcollector and the appropriate SiGe HBT isolation scheme. For the 200 GHz fT SiGe HBT in 8HP, critical process elements include a very lowresistance buried subcollector, n-type epitaxy formation, collector reach-through, and deep-trench isolation. In contrast, the 100 GHz fT SiGe HBT in 8WL does not require such process components and can be easily replaced by an implanted subcollector. After such processing sequence, the wafer in each case essentially looks like a standard CMOS processed wafer and can be put through the exact same processing sequence without any significant perturbation to the base CMOS process flow. Both BiCMOS flows then proceed with the standard CMOS processing steps: well implants, single and dual gate oxidations, gate poly deposition or pattern or etch, sidewall oxidation, LDD and extension implants, and finishing with the spacer formation. Essentially, bulk of the CMOS processing is completed with only the source–drain implant and activation remaining. There are multiple reasons for postponing the source–drain implants till after the bipolar formation — (a) the phosphorus (n-FET) and boron (pFET) dopants utilized for advanced CMOS tend to diffuse through the gate with additional lowtemperature cycles from the bipolar processing, (b) these implants can be used for the contact regions of parasitic active or passive devices built using bipolar elements, and (c) preserve modularity with the single activation RTA that can activate the CMOS and bipolar emitter. It should be noted that while the ‘‘BAG’’ approach reduces the thermal cycle for SiGe HBTs, it shifts the process challenge to clearing bipolar films from CMOS regions as well as requiring some re-engineering of CMOS well/extension/LDD implants for parametric centering. Prior to moving into the SiGe HBT build, the CMOS regions are protected by an etch stop layer that can later be easily removed. The bipolar module is extensively the same between 8HP and 8WL, with minor differences in the collector tailor implants and SiGe base profile. Structurally, both devices look quite similar and utilize advanced concepts of raised extrinsic base [6, 7] as well as fully realigned in situ doped emitter processing [8, 9] (see Figure 3.5.2). The bipolar module begins by defining a bipolar window opening by etching through a seed polysilicon and dielectric stack. Afterwards, the nonselective epitaxial growth of the

© 2006 by Taylor & Francis Group, LLC

3.5-267

Industry Examples at the State-of-the-Art: IBM

In situ doped emitter

Dielectric Isolation Silicide

Raised extrinsic base Boron-Doped SiGe base Collector Reachthrough plug Trench isolation

SIC collector Subcollector

FIGURE 3.5.2 Cross-sectional diagram of a raised extrinsic base SiGe HBT device.

UHV/CVD SiGe base region is completed. The raised extrinsic base with heavily doped p-type is then introduced. This provides a low-resistance linkup to the intrinsic base as well as much-reduced collector–base capacitance (CCB) for the SiGe HBT. The emitter–base junction is completed by the formation of an emitter opening with inside spacers, and then depositing an in situ doped polysilicon realigned emitter. The emitter polysilicon is then patterned and etched followed by the pattern or etch of the base polysilicon. The process challenge resides in the careful choice of an etch stop CMOS protect layer and the isotropic polysilicon etch that can clear all residual bipolar films from the CMOS gate topography. The CMOS protect layer is then removed for the source–drain implant and activation RTA. In the case of 8WL, prior to salicidation, a custom trench is etched around the NPN to reduce the collector–substrate capacitance. The trench is later filled with the contact dielectric and planarized. This allows minimum perturbation to the BiCMOS flow, while providing significant performance advantage for HBTs with negligible cost addition. The process sequence then moves into cobalt salicidation, contact formation, and BEOL metallization. Figure 3.5.3 shows a top view SEM of a static RAM cell built in 8HP, showing a clean CMOS integration that is possible with the 0.13 mm BiCMOS integration scheme. High-quality passive elements such as precision resistor, MIMcap, inductors, along with varactor, Schottky, and PIN diodes are integrated in a modular fashion to make technology attractive for various applications. Table 3.5.1 shows a comparative look at the various passive elements offered in 8HP and 8WL. Multiple resistors are available that range in sheet resistance, TCR, parasitic capacitance to substrate, and tolerance. For example, low TCR (<100 ppm/8C) and tight tolerance of less than 10% (3s) are achieved by the low-value polyresistor. Optimization of devices such as MIM capacitors and varactors varies from 8HP to 8WL due to the targeted applications. For example, the 8HP varactor is optimized for a Q value of 10 at 77 GHz, while the 8WL varactor is optimized for high-tuning range as well as linearity with Q >100 at 5 GHz. High-density MIM capacitors are required in wireless application to reduce the area consumed by precision capacitors that typically range from 1 to 10 pF. A high-k dielectric MIM capacitor has been developed in 8WL that is capable of 5 f F/mm2 density with high reliability of 10 ppm failure rate at 5 V for a

© 2006 by Taylor & Francis Group, LLC

3.5-268

The Silicon Heterostructure Handbook

Metal-1 Contact

Polygate

FIGURE 3.5.3 Top view scanning electron micrograph of a static RAM built using 0.13 mm groundrules and fully compatible with foundry CMOS integrated in BiCMOS 8HP.

TABLE 3.5.1

Passive Devices Offered in Both 8HP and 8WL Technologies

Resistors Diffused (n-type — ohms/sq.) Poly (p-type — ohms/sq.) Metal (TaN — ohms/sq.) Capacitors Hyper-abrupt varactor (VA ¼ 0 to 3 V) MOS varactor (VG ¼ 1 to 1 V) MIMcap (fF/mm2) Decoupling (fF/mm2) Inductor AM with M1 groundplane Dual Cu with M1 groundplane Diodes Schottky barrier (Vf at 100 uA in mV) ESD protection

BiCMOS 8HP

BiCMOS 8WL

8.8, 73 340, 1700 60

73 220, 340, 1700 60

3.6:1 tuning 6:1 tuning 1 11

4:1 tuning 6:1 tuning 5 11

Q ¼ 19; L ¼ 1 nH Q ¼ 22.5; L ¼ 1 nH — Yes

350 Yes

total device area of 106 mm2 at 100 K power-on-hours (see Figure 3.5.4). This MIM capacitor is compatible with both Al and Cu BEOL integration as a modular element and does not require any changes to the standard BEOL processes to achieve high reliability. Due to the high frequency requirements in 8HP, the MIM capacitor is mostly limited by the minimum geometry possible as opposed to density. For example, to get 50 V impedance for applications in 60 to 80 GHz range, the MIM capacitor geometry of approximately 50 mm2 is reasonable to control if a 1.0 f F/mm2 capacitance density is utilized. The requirements for metallization also diverge due to the targeted application space for 8HP and 8WL. Clearly, the lower levels of metal wiring are required for tight-pitch CMOS integration that enables chip size reduction for system-on-chip integration trends observed in wireless applications. Analog metal above the standard CMOS wiring is needed to address several parameters such as inductor Q, transmission line, and wireability. In the case of 8HP, a standard 4-mm thick Al metal wire separated by at least 10 mm from metal-1 supports the 77 GHz transmission lines. This single metal scheme, however, is not optimal for varied wireless applications due to the cost and complexity considerations. In 8WL, therefore, multiple analog metal options are offered to address performance and cost tradeoffs. Figure 3.5.5 compares various options offered in 8WL relative to 8HP and base CMOS technology. Thick single and dual damascene Cu levels with tight pitch are utilized in 8WL to lower the wire and via resistance as well as to reduce the inductor footprint.

© 2006 by Taylor & Francis Group, LLC

3.5-269

Industry Examples at the State-of-the-Art: IBM

100 K µm2 single MIM capacitor

109

100KPOH

108

Time (s) to failure

107 106 105 104 103 102

Fit 1 PPM 10 PPM 100 PPM

101 100

6

8 10 12 Stress voltage (V)

14

16 18 20

FIGURE 3.5.4 A state-of-the-art MIM capacitor built using high-k dielectric with density of 5.0 fF/mm2 and a lifetime of 100K POH at 9.0 V. This device is integrated into the 8WL Cu BEOL metallurgy.

0.13 µm CMOS

8HP

8WL Option 1

8WL Option 2

8WL Option 3

AM

Al

RF/Analog module

EZ Cu

LY

E1

E1 LM

2X 2X 1X 1X 1X 1X

Standard CMOS ASIC Layers

FIGURE 3.5.5 Cross-sectional sketch of the BEOL metals in 0.13 mm BiCMOS technologies relative to the base CMOS configuration. Analog metal modules are kept thick to improve the inductor performance.

3.5.3 The SiGe HBT — Key Technology Elements In this section, we discuss the key process modules that undergo optimization depending on the technology of choice, i.e., 8HP or 8WL. Primarily, we focus on the subcollector, base–emitter regions, and bipolar isolation. In order to attain the lowest collector resistance, high-performance transistors typically employ buried subcollector with an epi growth. In addition, collector epilayer thickness allows one to tune fT as well as

© 2006 by Taylor & Francis Group, LLC

3.5-270

The Silicon Heterostructure Handbook

allow for multiple breakdown voltage devices. This technique is employed in 8HP to achieve 200 GHz fT. For transistors where subcollector resistance is not the performance limiter, one can easily replace with an implanted subcollector, leading to a much simplified processing [10]. The desired subcollector offset, such as that attained by epitaxial layer growth, is set by the implantation depth and reduction to channeling tails. Special process considerations, such as resist profile and postimplant annealing, need to be employed for ensuring manufacturability. By using various layout techniques one can reduce the total collector resistance and improve fT, without compromising on the processing complexity. The best achievable sheet resistances from both these methods differ by at least an order of magnitude, at the expense of complexity or wafer cost. This difference results in an acceptable but modest peak-fT reduction (<15 GHz) that can somewhat be recovered by using specialized collector layouts [11]. Typically, there are multiple variants of SiGe HBTs in any one technology that are attained by optimizing the collector profile. The maximum breakdown voltage SiGe HBT achievable in any technology will be set by the choice of the subcollector. In order to attain high-performance (HP) SiGe HBT one needs to reduce the vertical distance from the subcollector to base profile by adjusting the epi thickness, which limits the achievable breakdown voltage for the high-breakdown (HB) SiGe HBT. In order to increase the breakdown voltage of HB SiGe HBT, particularly used in power amplifiers and storage preamps, one needs to add additional masks to create an independent subcollector. An intermediate or medium performance (MP) SiGe HBT can be achieved by adding an implant mask to form selectively implanted collector (SIC) profile. In the case of SiGe 8WL, this implant is shared with CMOS well implant to obtain a 65 GHz HBT with no added mask cost. The SiGe base profile is engineered with a Ge ramp profile, with Ge peak concentration around 25% to minimize the base transit time. One can engineer the Ge ramp profile to tradeoff between fT (tE / 1/b / 1/Ge-ramp; tB / 1/Ge-ramp), current gain (b), and breakdown voltage (BVCEO / 1/b). For 8HP, the Ge ramp is made steeper than 8WL resulting in b-difference of two times and BVCEO difference of 0.7 V in a HP SiGe HBT. A carbon-doped narrow base boron profile is used in both technologies to minimize the basewidth. The undoped emitter and collector silicon cap thickness are adjusted for both technologies to attain the appropriate emitter–base and collector–base delay times. The extrinsic base link is formed by an in situ doped raised extrinsic base approach that allows one to reduce rbb simultaneously with CCB, and is utilized in both 8HP and 8WL. Polysilicon emitter is yet another module that has seen processing advances in the recent past. As one scales the transistor performance, the increase in emitter resistance (RE) and current gain (b) due to the presence of the emitter poly–Si interfacial oxide becomes unacceptable. Therefore, the advanced state-ofthe-art technologies use in situ doped polysilicon emitters to form a recrystallized mono emitter interface [12]. This method significantly reduces RE, brings b to a useful range, as well as improves fT. Both 8HP and 8WL technologies take advantage of this process element for improved SiGe HBT performance. Bipolar isolation in 8HP is achieved by using both shallow and deep trenches. The shallow-trench process in 8HP and 8WL is similar to the base CMOS process. The deep trench in 8HP is polyfilled and planarized with process commonality maintained to previous generation production SiGe BiCMOS technologies (e.g., 0.18 mm). This deep-trench isolation feature is not only utilized for bipolar collector– substrate capacitance (CCS) reduction, but, also under the passive elements to reduce substrate coupling. The integration of such a deep trench adds more complexity and wafer cost that is not warranted in 8WL. For desired CCS reduction, if one substitutes the deep trench with traditional simple junction isolation the HBT footprint becomes significant. In 8WL, therefore, a custom deep-trench isolation has been employed for HBTs to optimize performance and cost.

3.5.4 Electrical Performance The centerpiece of the BiCMOS technology is the SiGe HBT that enables the frequency performance. SiGe HBTs have shown sevenfold improvement in fT performance since its first introduction in the 0.5 mm production technology (see Figure 3.5.6). Both lateral- and vertical-scaling techniques are

© 2006 by Taylor & Francis Group, LLC

3.5-271

Industry Examples at the State-of-the-Art: IBM

400 Next generation Cutoff frequency (GHz)

350 300 250 0.13 µm

200

0.18 µm

150 100

0.5 & 0.25 µm

50 0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 3.5.6 SiGe HBT performance scaling over multiple technologies.

employed to reduce transit times and parasitics to boost fT/fmax performance. One aspect of the vertical scaling is to reduce base push out by increasing collector-doping concentration. This increases the collector current density required at peak-fT. However, by shrinking the emitter dimension proportionately one can obtain significant improvement in fT at the same collector current or reduce the power level required for the same fT. For example, at 1 mA of collector current, one can achieve an fT of 275 GHz using a 0.11 mm device compared to 43 GHz for a 0.42 mm SiGe HBT. Figure 3.5.7 shows the Gummel characteristics of both HP and HB SiGe HBTs built in 8HP technology. Devices show ideal behavior over several decades of currents, which is clearly reflected in the current gain (see Figure 3.5.8). As expected, the high-injection Ge-induced barrier effects are clearly visible in MP and HB devices due to the lower collector doping and early onset of the Kirk effect compared to high-performance SiGe HBT. It should be noted that the retrograde Ge profiles are designed to minimize the parasitic barriers and allow maximum fT prior to the Kirk effect. The output characteristics for HP, MP, and HB devices in both 8HP and 8WL technologies are shown in Figure 3.5.9 and Figure 3.5.10. High early voltage is attained for all devices over a 1 V voltage swing (VCE). The fT performance of various flavors of SiGe HBTs with minimum emitter width built in 8HP technology is shown in Figure 3.5.11. The fT and fmax are extracted from jh21j and jUj measured at 20 GHz and extrapolated with an ideal slope of 20 dB/decade, respectively. The HP transistor achieves 200 GHz at 5.0 mA of collector current for a 0.12 3 mm2 emitter transistor. With additional collector adjustment masks for the MP and HB transistors one can achieve 115 and 50 GHz, simultaneously on a wafer. The HP device also shows a reasonable fT performance over a wide temperature range (0 to 1258C) as seen in Figure 3.5.12. The peak-fT performance increases from 170 GHz at 1258C to 226 GHz at 08C, with very minor change to the peak-fT current density. One can also observe that the operating collector current reduces by two times at a fixed fT of 120 GHz over 1258C temperature range, primarily due to the temperature dependence of the emitter–base charging time as well as the current gain. In contrast to HBT optimization for peak-fT/fmax performance as in 8HP, the focus shifts to the optimization of power, noise-figure, linearity, breakdown voltage, etc., for the 8WL SiGe HBTs. The key transit time and parasitic reduction elements from the 8HP HBT are shared wherever possible and tradeoffs made on process modules that can lead to significant cost benefits for marginal performance improvement. One example of this study with the collector sinker has shown that the extra collector resistance introduced by replacing the collector reachthrough module in 8HP with available standard CMOS n-type implants reduces the peak-fT by only 3 GHz. This result combined with the subcollector

© 2006 by Taylor & Francis Group, LLC

3.5-272

The Silicon Heterostructure Handbook

1 ⫻ 10−1

Collector and base currents (A)

1 ⫻ 10−2 1⫻

10−3

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

1 ⫻ 10−4 1 ⫻ 10−5 1 ⫻ 10−6 1 ⫻ 10−7 1 ⫻ 10−8 1 ⫻ 10−9 1 ⫻ 10−10

HP HB

1 ⫻ 10−11 1 ⫻ 10−12 0.4

0.5

0.6

0.7

0.8

0.9

1

Base−emitter voltage (V)

FIGURE 3.5.7 Gummel characteristics of BiCMOS 8HP high-performance and high-breakdown SiGe HBTs. 650 600

HP MP HB

550 500 Current gain

450 400 350 300 250 200 150 100 50

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

0 1⫻10−9 1⫻10−8 1⫻10−7 1⫻10−6 1⫻10−5 1⫻10−4 1⫻10−3 1⫻10−2 1⫻10−1 Collector current (A)

FIGURE 3.5.8 Current gain for the three flavors of SiGe HBTs built in BiCMOS 8HP.

optimization data indicates the potential to fabricate very high-performance, state-of-the-art NPN devices, in a low-complexity process. Figure 3.5.13 shows the fT versus IC curves for three different SiGe HBTs fabricated on an 8WL wafer with optimized implanted subcollector process to meet a wide range of breakdown voltage requirements: a HP device with 96 GHz/2.35 V BVCEO, a MP device with 67 GHz/3.1 V BVCEO, and a HB device with 46 GHz/4.7 V BVCEO. These devices have a BVCBO of 10.4, 14, and 18.6 V, respectively. In general, the devices are not operated in the breakdown bias conditions such as BVCBO or BVCEO. However, these conditions represent the extremity of the NPN operation. The general relationship of breakdown voltage and fT for various SiGe HBTs that span several generations of technologies is plotted in Figure 3.5.14.

© 2006 by Taylor & Francis Group, LLC

3.5-273

Industry Examples at the State-of-the-Art: IBM

6⫻10−4 5⫻10−4 Collector current (A)

HP MP HB

BiCMOS 8HP 2 AE = 0.12 ⫻ 3 µm

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100 0

0.5

1

1.5 2 2.5 Collector-emitter voltage (V)

3

3.5

4

FIGURE 3.5.9 Output characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

6⫻10−4 BiCMOS 8WL AE = 0.12 ⫻ 4 µm2

Collector current (A)

5⫻10−4

HP MP HB

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100

0

0.5

1

1.5 2 2.5 3 3.5 Collector-emitter voltage (V)

4

4.5

5

FIGURE 3.5.10 Output characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

This relationship suggests that the operating margin exceeding 5.5 V can be achieved with a 100 GHz SiGe HBT, with the margin dropping only to 3.5 V for a 350 GHz SiGe HBT. The fMAX behavior for HP and HB devices is shown in Figure 3.5.15. The rbb and CCB reduction possible with the raised extrinsic base approach leads to superior fMAX performance for all HBTs, with obvious improvement seen for 8HP devices compared to 8WL over all bias ranges. We expect that the improved fMAX performance will lead to improved NFMIN performance, primarily due to the reduction in rbb. The NFMIN for 8WL shows a comparable performance to 8HP over a wide range of frequencies with 0.23 dB at 2.4 GHz and only upto 1.5 dB at 20 GHz (Figure 3.5.16 and Figure 3.5.17). These performance numbers for 8WL compare favorably with previous generation wireless technologies at 0.5 mm and 0.18 mm nodes (Figure 3.5.18).

© 2006 by Taylor & Francis Group, LLC

3.5-274

Cutoff frequency (GHz)

The Silicon Heterostructure Handbook

220 200 180 160 140 120 100 80 60 40 20 0 0.1

BiCMOS 8HP VCB = 0.5 V

High performance 2 AE = 0.12 ⫻ 3.0 µm

Medium performance 2 A E = 0.12 ⫻ 2.5 µm

High breakdown 2 AE = 0.12 ⫻ 2.5 µm

1 10 Collector current density (mA/mm2)

100

FIGURE 3.5.11 fT characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

240 Cutoff frequency (GHz)

220 200

T = 0⬚C, 25⬚C, 55⬚C, 85⬚C, 125⬚C

180 160 140 120 100 BiCMOS 8HP A E = 0.12 ⫻ 3 µm2 V CB = 0.5 V

80 60 40 1⫻10−4

1⫻10−3 Collector current (A)

1⫻10−2

FIGURE 3.5.12 Temperature dependence of fT for the HP SiGe HBT in BiCMOS 8HP technology.

Cutoff frequency (GHz)

120 100

BiCMOS 8WL AE = 0.12 ⫻ 4 µm2 VCB = 1.0 V

High performance

80 Medium performance

60 40 High breakdown

20 0 0.01

0.1 1 Collector current (mA)

10

FIGURE 3.5.13 fT characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

© 2006 by Taylor & Francis Group, LLC

3.5-275

Industry Examples at the State-of-the-Art: IBM

Peak cutoff frequency (GHz)

400 350 300 250 200 150

BVCBO limited

100

BVCBO limited

50 0 0

10 15 Breakdown voltage (V)

20

25

The general fT and breakdown voltage relationship for various SiGe HBTs. Unilateral maximum power gain frequency (GHz)

FIGURE 3.5.14

5

350 HP HB VCB = 1.0 V

300 250

BiCMOS 8HP

200 150 100 50

BiCMOS 8WL

0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 3.5.15

fMAX characteristics of HP and HB devices built in 8HP and 8WL technologies. 2.5 8HP 8WL

NFmin (dB)

2 20 GHz 1.5 1 10 GHz 0.5 2 GHz 0 0

FIGURE 3.5.16

2

4 6 8 Collector current (mA)

10

12

NFMIN as a function of collector current for HP devices in 8HP and 8WL technologies.

© 2006 by Taylor & Francis Group, LLC

3.5-276

The Silicon Heterostructure Handbook

2.5 8HP 8WL

NFmin (dB)

2 1.5 1 0.5 0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 3.5.17 NFMIN for HP devices built in 8HP and 8WL over a wide range of frequencies.

Minimum noise figure (dB)

3 10 GHz 2.5

5HP: AE = 0.5 ⫻ 20 ⫻ 2 µm2

2 7WL: AE = 0.24 ⫻ 20 ⫻ 2 µm2

1.5 1 0.5

8WL: AE = 0.12 ⫻ 32 µm2

0 0.1

1 Collector current (mA)

10

FIGURE 3.5.18 NFMIN characteristics of 8WL HP device compared to the previous generation wireless technologies at 0.18 and 0.50 mm nodes.

Industry-standard foundry-compatible CMOS devices at 1.2 and 2.5 V are offered in both 8HP and 8WL. In addition to these basic FETs, 8WL includes devices tailored for analog- and mixed-signal applications, such as 3.3 V/5.2 nm gate oxide analog transistors with a gate length of 0.4 mm, zero-VT transistors etc. Triple well nFETs with 2.1 and 5.2 nm gate oxide are also supported in the BiCMOS technologies. RF layouts are developed for the FETs to provide accurate substrate resistance values and wiring parasitics. The 1.2 V/1.5 V 2.1 nm gate oxide logic FETs have gate length of 0.92 mm while the 2.5 V/5.2 nm thick oxide I/O driver FETs have a gate length 0.21 mm. Figure 3.5.19 and Figure 3.5.20 show the VTsat versus Idsat scatter plots demonstrating equivalence of the CMOS parameters in the BiCMOS and 0.13 mm base CMOS technologies.

3.5.5 Manufacturability For a stable manufacturable technology, it is important that the technology demonstrates adequate parametric control as well as yield over large quantities of lots processed over time. In this section, we present some key manufacturability data that provide insight into the state-of-the-art 8HP technology.

© 2006 by Taylor & Francis Group, LLC

3.5-277

Industry Examples at the State-of-the-Art: IBM

600

I d Saturation (mA)

580 560 540 520 500 480 8SF 8HP 8WL 460 440 270

290

310

330 350 370 V t Saturation (mV)

390

410

FIGURE 3.5.19 Thin oxide nFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VTIdsat relationship.

−130 −140

I d Saturation (mA)

−150 −160 −170 −180 −190 −200

8SF

8HP

8WL

−210 −220 −450

−400

−350 V t Saturation (mV)

−300

−250

FIGURE 3.5.20 Thin oxide pFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VTIdsat relationship.

Figure 3.5.21 shows the parametric distribution of base–emitter voltage (VBE) measured at 10 mA of emitter current for 0.12 2.5 mm2 HP transistor for a large sample size of lots processed during technology qualification. This normal distribution shows a 0.7% one-sigma variability, signifying good process control for the emitter–base junction depth as well as the base profile including LTE Ge ramp. For the collector–base control, we show in Figure 3.5.22, the histogram of BVCBO measured at 10 mA for a 0.12 2.5 mm2 HP device on a significantly larger sample size of lots. Data indicate that a tight control of the collector–base junction is possible (one-sigma of 1.3%). We expect that the tight control of the CB profile will also improve the avalanche, fT, CCB, and fMAX performance. The AC performance is sampled (five chips per wafer) routinely to understand the stability of peak-fT/ fmax by measuring s-parameters using a 110 GHz HP analyzer. Figure 3.5.23 shows the fT and fMAX over a

© 2006 by Taylor & Francis Group, LLC

3.5-278

The Silicon Heterostructure Handbook

30

N Mean Sigma Minimum 1st Ptile 5th Ptile 10th Ptile 25th Ptile Median 75th Ptile 90th Ptile 95th Ptile 99th Ptile Maximum LSL Target USL % Low % Yield % High Cp Cpk

25

Percent

20

15

10

5

Normal X2

0 700.5

709.5

718.5

727.5

736.5

745.5

677 727.1496 5.297336 705.6565 711.6716 717.5469 720.4985 724.3328 727.4758 730.3022 733.6274 735.5154 739.8247 742.6243 701 726 751 0 100 0 1.573118 1.50078 65.81932

754.5

Test M1 8211 309 TX6 FVEBS 10UA

FIGURE 3.5.21 Histogram of VBE measured on 0.12 2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple lots.

22.5 20.0 17.5 15.0

Percent

4185

N

12.5 10.0 7.5

Mean

5.87393

Sigma

0.078501

Minimum

5.627674

1st Ptile

5.695866

5th Ptile

5.750379

10th Ptile

5.784013

25th Ptile

5.828348

Median

5.869673

75th Ptile

5.912518

90th Ptile

5.963103

95th Ptile

6.01013

99th Ptile

6.122393

Maximum

6.289583

LSL

5.5

Target

5.9

USL

6.3

% Low

5.0

% Yield % High

1.587784

Cpk Normal X2

0 5.475

5.595

5.715

5.835

5.955

6.075

6.195

0 1.698482

Cp

2.5

0 100

2251.166

6.315

Test M1 8211 313 TX6 BVCBO 10UA

FIGURE 3.5.22 Histogram of BVCBO measured on 0.12 2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple wafer-lots.

© 2006 by Taylor & Francis Group, LLC

3.5-279

Industry Examples at the State-of-the-Art: IBM

320 fMAX

305

Cutoff frequency (GHz)

290 275 260 245

BiCMOS 8HP

230

AE = 0.12 ⫻ 3 µm2 VCB = 0.5 V

fT

215 200 185 170 0

Peak-f T and peak-fmax (GHz), min-Rbb (ohms)

FIGURE 3.5.23 wafer-lots.

10

20

30

40 Wafer

50

60

70

80

Frequency performance trend chart for HP transistor in 8HP technology, sampled over multiple

130

fT

120 110 100

fMAX

90 80 70

AE = 0.2 ⫻ 6.4 µm2

60

Vcb = 1.0 V

50

rbb

40 30 20 10 0 0

3

6

9

12

15

18

21 Lots

24

27

30

33

36

39

FIGURE 3.5.24 Frequency performance trend chart for HP transistor in 0.18 mm/120 GHz technology, sampled over multiple lots during past 2 years.

significant quantity of wafers built over time. Clearly, the fT is well controlled and centered around 200 GHz. The average fMAX shows around 280 GHz with a range from 260 to 310 GHz. It should be noted that some of the fMAX variability is due to the extraction error introduced by the sensitivity of the slope in jUj roll-off. A much larger sample size of AC data has been collected over a period of 2 years from the production 120 GHz 0.18 mm SiGe BiCMOS technology as shown in Figure 3.5.24. Data from close to 40 lots sampled over this significant period of production timeframe indicate stability in the AC performance with all lots meeting specifications. Such a performance control in both these highperformance BiCMOS technologies is a testament to the SiGe epi base process control and the LTE tooling capability.

© 2006 by Taylor & Francis Group, LLC

3.5-280

The Silicon Heterostructure Handbook

The yield is routinely measured on every lot for various active devices, contacts, and the BEOL metallurgy. The NPN yield is measured on an array of 2000 transistors connected in parallel, with the combined leakage measurement for EB, CB, and CE junctions performed. The chain is considered to be a fail if any one junction shows a higher than expected leakage. The chain yield for both HP and HB devices in 8HP is shown in Figure 3.5.25. As expected, the HP transistor has lower yield compared to the HB device due to additional processing. The development of SiGe HBT exposed unique NPN CB yield sensitivity due to the interaction of various processing factors, namely, CMOS RIE etch on bipolar regions, SIC implant, and the LTE processing. This process interaction leads to somewhat depressed yield for NPNs, with HP transistors showing more sensitivity to this mechanism. Data suggest that the yield for NPNs can be improved to well above the 90% by eliminating such sensitivities as typically practiced under volume manufacturing by improved defect learning. Figure 3.5.26 represents the CMOS, contact, and BEOL yield for the last 15 lots fabricated in 8HP technology. The CMOS yield is measured as a cumulative effect of shorts measured from gate-to-source– drain and gate-to-gate and gate-to-well. Contact yield is measured by looking at open on a series of 40K contacts. BEOL cumulative yield is measured as metal shorts and via opens for all the levels. Overall, the combined parametric control as well as yields for various elements of the technology indicates the manufacturability of the state-of-the-art SiGe BiCMOS technology.

3.5.6 Summary The state-of-the-art production SiGe BiCMOS technologies at the 0.13 mm lithography node have been presented. The flexibility of SiGe HBT integration is utilized for tailoring BiCMOS technologies for applications that range from performance-hungry automotive radar to low-cost wireless and storage markets. BiCMOS 8HP and 8WL technologies feature multiple SiGe HBTs that tradeoff fT and breakdown voltage, by optimizing the collector profile through implant masks. CMOS and passive elements are also easily integrated with a fully foundry-compatible Cu BEOL wiring. In addition, we have shown manufacturability data for the 200 GHz SiGe BiCMOS technology, indicating that viability of such technologies in the semiconductor marketplace.

100.0 90.0

NPN 2K chain yield (%)

80.0 70.0 60.0 BiCMOS 8HP 50.0

2K Array

40.0 30.0 20.0 HP HB

10.0 0.0 0

5

10

15

20

25

30

35

Wafers

FIGURE 3.5.25 NPN chain yield for HP and HB transistors in 8HP technology, sampled over multiple wafer-lots.

© 2006 by Taylor & Francis Group, LLC

3.5-281

Industry Examples at the State-of-the-Art: IBM

100 90 80

Yield (%)

70 60 50 40 30 20 10 0 1

2

3

4

5

6 CMOS

7

8 Lots

9

Contact

10

11

12

13

14

15

BEOL

FIGURE 3.5.26 Chain yield data for CMOS, contacts, and BEOL elements in 8HP technology.

Acknowledgments We thank the technology development team in Essex Junction, Vermont and East Fishkill, New York, for their dedication in providing RF, Analog, and Mixed-signal technology solutions. In particular, we greatly appreciate the contributions of Louis Lanzerotti, Xuefeng Liu, Qizhi Liu, David Sheridan, Doug Coolbaugh, Robert Rassel, Jim Slinkman, Bradley Orner, Steve St. Onge, Natalie Feilchenfeld, and Jeffrey Johnson toward the success of this work. Finally, we thank the IBM senior management for their support — Bernie Meyerson, David Harame, Dean Herman Jr., Wally Stein (now retired), and John DiToro — in helping to bring the SiGe BiCMOS solution to the marketplace.

References 1. S. Zhang, J.D. Cressler, S. Subbanna, R. Groves, G. Niu, T. Isaacs-Smith, J.R. Williams, H. Bakhru, P.W. Marshall, H.S. Kim, R.A. Reed. An Investigation of Proton Energy Effects in SiGe HBT Technology. IEEE Transactions on Nuclear Science 49(6):3208–3212, 2002. 2. D.C. Ahlgren, M. Gilbert, D. Greenberg, J. Jeng, J. Malinowski, D. Nguyen-Ngoc, K. Schonenberg, K. Stein, R. Groves, K. Walter, G. Hueckel, D. Colavito, G. Freeman, D. Sunderland, D.L. Harame, B. Meyerson. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace. Technical Digest of International Electron Device Meeting 1996, December 1996, pp. 859–862. 3. SiGe Review. http://www.epenet.com/Newsletters%20-%20Features/sigerev.htm. 4. 802.11 PRISM products. http://www.conexant.com/products/entry.jsp?id ¼ 28. 5. D.L. Harame, D.C. Ahlgren, D.D. Coolbaugh, J.S. Dunn, G.G. Freeman, J.D. Gillis, R.A. Groves, G.N. Hendersen, R.A. Johnson, A.J. Joseph, S. Subbanna, A.M. Victor, K.M. Watson, C.S. Webster, P.J. Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2584, 2001. 6. B. Jagannathan, M. Meghelli, K. Chan, Jae-Sung Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna, G. Freeman, 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Device Letters 24:645–655, 2003. 7. B.A. Orner, Q.Z. Liu, B. Rainey, A. Stricker, P. Geiss, P. Gray, M. Zierak, M. Gordon, D. Collins, V. Ramachandran, W. Hodge, C. Willets, A. Joseph, J. Dunn, J.-S. Rieh, S.-J. Jeng, E. Eld, G. Freeman,

© 2006 by Taylor & Francis Group, LLC

3.5-282

8.

9.

10.

11.

12.

The Silicon Heterostructure Handbook

D. Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fMAX) SiGe HBT. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2003, pp. 203–206. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinares, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharro, J.L. Regolini, G. Vincent, A. Chantre. A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices 46:1525–1531, 1999. A. Joseph, P. Geiss, X. Liu, J. Johnson, K. Schonenberg, A. Chakravarti, D. Ahlgren, J. Dunn. Emitter resistance improvement in SiGe HBTs. Proceedings of the First International SiGe Technology and Device Meeting, January 2003, pp. 223–224. N. Feilchenfeld, L. Lanzerotti, D. Sheridan, R. Wuthrich, P. Geiss, D. Coolbaugh, P. Gray, J. He, P. Demag, J. Greco, T. Larsen, V. Patel, M. Zierak, W. Hodge, J. Rascoe, J. Trappasso, B. Orner, A. Norris, D. Hershberger, B. Voegeli, S. Voldman, R. Rassel, V. Ramachandiran, M. Gautsch, E. Eshun, R. Hussain, D. Jordan, S. St Onge, J. Dunn. High performance low complexity 0.18 mm SiGe BiCMOS technology for wireless circuit applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2002, pp. 197–200. L. Lanzerotti, N. Feilchenfeld, D. Coolbaugh, J. Slinkman, P. Gray, D. Sheridan, J. Higgins, W. Hodge, M. Gordon, T. Larsen, M. Gautsch, P. Lindgren, R. Murty, J. Rascoe, K. Watson, T. Stamper, E. Eshun, J. He, K. Downes, R. Rassel, J. Greco, B. Labelle, S. Sweeney, K. Stein, R. Bolam, K. Vaed, B. Omer, A. Joseph, S. St Onge, J. Dunn. A cost performance 0.13 mm SiGe BiCMOS technology for wireless and mixed signal applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2004, pp. 13–14, 237–240. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, R. Beerkens, N. Zerounian, F. Aniel, A. Chantre. 230 GHz self aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, October 2004, pp. 13–14, 225–228.

© 2006 by Taylor & Francis Group, LLC

3.6 Industry Examples at the State-of-the-Art: Jazz 3.6.1 3.6.2

Introduction............................................................... 3.6-283 SiGe Bipolar Transistor............................................. 3.6-284 Fully Self-Aligned Device Structure . SiGe npn Performance . Vertical Scaling . Lateral Scaling

3.6.3

SiGe BiCMOS Process Integration .......................... 3.6-289 Integration Sequence . CMOS Thermal Budget . SiGe npn Manufacturability

3.6.4

Wireless Technology . High Data Rate and High-Frequency Technology

Paul H.G. Kempf Jazz Semiconductor

Process Customization.............................................. 3.6-291

3.6.5

Summary .................................................................... 3.6-293

3.6.1 Introduction The roots of most commercial silicon germanium (SiGe) BiCMOS processes lie in a tradition of bipolar technology developed relatively slowly over multiple generations. Historical progress of traditional bipolar technology was quickly outpaced by CMOS processes in the 1990s with ever-shrinking linewidths in state-of-the-art CMOS fabs. A step-up to 200 mm wafers for BiCMOS technology created a gap between older generation bipolar technologies, which were optimized at a time when the addition of CMOS compromised bipolar performance, and the new generation of BiCMOS technologies that took full advantage of the tool capabilities in an advanced CMOS fab [1, 2]. Improved capabilities included better control of thermal steps due to vertical furnaces, new temperature monitoring schemes for rapid thermal annealing, higher selectivity etches for silicon, oxide and nitride, in-line SEM metrology for monitoring of critical structures, and tighter photomask alignment tolerances. Along with this fundamentally improved equipment capability came the development of sophisticated factory automation that made it possible to run multiple process technologies with an increasing number of photomask layers at consistently high fab yield. In this new environment, the bipolar transistor was able to realize the full benefit of the addition of silicon germanium to the base structure because lateral scaling reduced performance-limiting parasitic capacitance and resistance, while thermal budget control enabled manufacturable ultra-shallow junctions that were needed for vertical scaling in high-speed bipolar transistors. Acceleration of the performance curve for SiGe bipolar transistors has once again placed the bipolar device as the highest speed transistor available on silicon [3]. This background explains the foundation of Jazz Semiconductor’s SiGe BiCMOS technology, which was released to production as a high-performance upgrade to a 0.35-mm silicon BiCMOS process in the year 2000 (named SiGe60), and later advanced to an ultra-high-performance bipolar module, with fT 3.6-283 © 2006 by Taylor & Francis Group, LLC

3.6-284

The Silicon Heterostructure Handbook

and fmax greater than 155 GHz, integrated with standard 0.18-mm CMOS (named SiGe120). As an example of state-of-the-art production technology, this chapter will focus on the unique optimization of the bipolar structure in a 0.18-mm process, provide a summary of its performance characteristics for different device optimizations up to an fT of 200 GHz, discuss BiCMOS integration challenges for 0.18 and 0.13-mm, and detail some of the customization requirements that are an important aspect of overall technology capability.

3.6.2 SiGe Bipolar Transistor The first choice that must be made when considering transistor architecture is the overall performance level that needs to be met, which is largely fixed by the set of addressable applications for the technology. A dilemma arises when the end-market for a technology is evolving as quickly as the technology. For example, the wireless world was recently focused on up to 2 GHz carrier frequencies, but has since opened up 5 to 60 GHz as a range of interest for high-speed data and other applications. Development of a transistor capable of addressing a wide range of high-speed applications leads to a device design that does not trade off key parameters for one another.

Fully Self-Aligned Device Structure Rather than extending the quasi-self-aligned bipolar structure from the first generation of Jazz SiGe BiCMOS technology to smaller geometries, compromising base link resistance, emitter width, overlap capacitances, and other parameters, a choice was made to create a new self-aligned bipolar device with balanced performance characteristics and physical attributes that would be compatible with supporting a large variety of products integrated with 0.18-mm CMOS technology and below (Figure 3.6.1a). Key attributes include low resistance buried layer and substrate epitaxy for collector formation, deep trench

Self-aligned extrinsic base

Final emitter Collector Base Self-aligned base implant

Direct-patterned Sacrificial emitter Blanket SiGe

Buried layer

Deep trench isolation

Intrinsic Link SiGe base base (a)

(b)

Normalized Rb

3 2.5 2 1.5

SA

1

QSA

0.5 0 0 0.1 0.2 0.3 Effective base link width (microns) (c)

FIGURE 3.6.1 (a) Schematic cross section of the self-aligned SiGe npn transistor. (b) Sacrificial emitter masks the extrinsic base implant. (c) Simulated base resistance at peak fT for self-aligned (SA) versus quasi-self-aligned (QSA) emitter. Error bars show 3-sigma variation.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-285

isolation, near-planar SiGe epi to polysilicon transition, selective collector implants, scalable emitter width with self-aligned base link implants, low-resistance in-situ doped emitter, and conventional cobalt silicidation [4, 5]. The process flow begins with the formation of the buried layer by a high-dose implant and growth of an epitaxial layer. This approach is chosen over use of a high-energy implant to minimize collector resistance and maintain high fT at the low Vce typically employed in small-signal, high-speed applications. It also allows for a wide range of breakdown voltages (BVceo) on the same wafer, which is achieved with different doping levels of the selectively implanted collector (SIC). An optional deep trench is also used to reduce collector–substrate capacitance (Ccs), an important factor in reducing switching delay. The trench is filled with an oxide liner and a polysilicon plug. An oxide-filled shallow trench is also formed, providing a planar surface on which to build the emitter–base structure of the npn bipolar transistor. A blanket SiGe deposition was chosen to support scalable transistor geometries for a wide range of active device area to total wafer area ratios, which is an important capability for a foundry technology that must achieve predictable device performance for a wide variety of circuit layouts. The temperature uniformity that can be achieved across the wafer is superior in the case of a blanket process where similar film stacks are present everywhere during SiGe epi growth. For the base of the drift-field SiGe bipolar transistor, germanium is ramped from 0% near the base–emitter junction to approximately 30% near the collector–base junction, and a very narrow spike of boron is included in the growth sequence. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implants (Figure 3.6.1b), which enable independent optimization of extrinsic base resistance while maintaining a planar base structure that minimizes link resistance effects between the intrinsic epitaxial base and the extrinsic polycrystalline base contact. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimensions of the sacrificial emitter exactly define the final emitter dimensions. This is in contrast to inside spacer techniques that show greater emitter width variation due to the reduced photo and etch resolution of a slot versus a bar, and on the spacer width variation determined by film thickness and etch uniformity (Figure 3.6.1c). Also, this technique results in a self-aligned emitter–base without selective epitaxy, versus the approach used in Ref. [6]. Outside spacers on the emitter poly are necessary for selfalignment of the final extrinsic base used for low base contact resistance and for the prevention of a silicide short between emitter and base polysilicon layers. The subsequent cobalt silicide formation, contact etch, and oxide chemical mechanical polish (CMP) are the same as a standard CMOS process. Achieving extremely low emitter resistance is critical in order to achieve high-speed performance and can be especially limiting for emitter areas that can be as small as 0.2 0.7 mm2 in 0.18-mm technology. Components of the emitter resistance include the emitter to silicon interface, the polysilicon resistivity (dependent on grain structure and dopant activation), the cobalt silicide to polysilicon interface, and the standard contact and metal components. The completed device has a small footprint and a planar intrinsic to extrinsic base transition that enables the high performance of the SiGe npn transistor.

SiGe npn Performance Effective optimization of the SiGe npn transistor results in a device with a wide range of applicability. The scalable architecture is used to build production devices with fT of 38, 78 and 155 GHz with nominal BVceo of 6, 3.5 and 2.2 V, respectively. Changes to the collector doping profile and reduced base width extend the same approach to a technology with fT and fmax greater than 200 GHz [7] while maintaining a BVceo of 2.0 V. As shown in Figure 3.6.2, the gains in the performance of the higher breakdown voltage bipolar devices in each technology have been tracking the high-speed transistor, demonstrating that improvements in the intrinsic device structure have played a significant role in overall SiGe npn performance. While achieving peak fT at modest current density is important for small-signal highspeed circuits, minimum noise figure and low power performance are critical for many RF applications. Benefits derived from low parasitic resistance and capacitance of the Jazz 0.18-mm SiGe bipolar transistor are evident in Figure 3.6.3 relative to the Jazz 0.35-mm SiGe BiCMOS technology that uses

© 2006 by Taylor & Francis Group, LLC

3.6-286

The Silicon Heterostructure Handbook

1000 BC35 SiGe60

f T (GHz)

SiGe90/120 SiGe200

100

10 1

2

3

4 BVceo (V)

5

6

7

FIGURE 3.6.2 fT versus typical BVceo for four generations of Jazz BiCMOS.

200 175

Vce=1 V

SiGe200

fT (GHz)

150

SiGe120

125 100 SiGe90

75

SiGe60

50 25

BC35

0 0.01

0.1

1

10

I C (mA) for minimum We and Le = 1 µm

FIGURE 3.6.3 Higher fT performance at low and high current ranges for 0.18-mm SiGe BiCMOS processes (SiGe90/120/200) versus 0.35-mm (SiGe60, BC35).

a quasi-self-aligned emitter. A large reduction in current required to meet RF circuit specifications, realized over a wide range of frequencies, has been published in various circuit-related studies [8–11]. Performance gains can be attributed to both the vertical and lateral scaling properties of the SiGe bipolar transistor.

Vertical Scaling Vertical scaling has been the traditional advantage of bipolar transistors over n-type MOS transistors due to the better control of vertical profiles versus lateral dimensions. This inherent fT advantage still holds true for advanced npn SiGe bipolar devices versus nanometer gate length CMOS. Optimization of fT is dependent upon a number of factors, as represented by the following analytical model that has proven effective at predicting peak fT of the Jazz bipolar devices:

© 2006 by Taylor & Francis Group, LLC

3.6-287

Industry Examples at the State-of-the-Art: Jazz

1=(2pf T ) ¼ (R e þ kT =(qIc ))(Cbe þ Cbc ) þ Wb2 =(2D b ) þ Wc =(2Vs ) þ Rc Cbc

(3:6:1)

where R e is the emitter series resistance, Ic the collector current, Cbe and Cbc the respective junction capacitances, Wb the base width, Db the electron diffusivity in the base, Wc the collector depletion region, Vs the saturated electron velocity, and Rc the collector resistance. Elements from Equation (3.6.1) can be calculated as a function of process parameters to help analyze trends in the bipolar performance. One method of increasing fT is to increase the collector doping concentration, which moves the Kirk effect to higher collector current density and results in higher peak fT. As shown in Figure 3.6.4, both experimental results as well as predictions from Equation (3.6.1) indicate that this technique is effective at lowering collector doping concentrations, but the benefits saturate at higher doping concentrations due to limitations of Re and Cbc at higher collector current. To achieve higher fT, therefore, Re or Wb must be reduced. Further reduction of base width, Wb, for these high-performance transistors has negative implications on the manufacturability and defect levels for the bipolar device, so reduction of emitter resistance is a more attractive optimization for high fT. Figure 3.6.4 shows that Re does not significantly affect fT at lower collector doping concentrations or lower Ic, and that Re does significantly affect fT at higher collector doping concentrations or higher Ic. Based on this analysis, a strong reduction in emitter resistance, coupled with a small re-optimization in the collector dose, has been used to increase the fT of the SiGe transistor without significantly reducing the base width. A peak fT of 205 GHz is reached for a production device with BVceo of 2.0 V, resulting in an fTBVceo product of 410 GHz-V.

Lateral Scaling For a given vertical scaling of the SiGe bipolar transistor, the fmax, or similarly the unilateral gain, can be improved with lateral scaling that reduces base-to-collector capacitance and the intrinsic base resistance. Reduction of base resistance also results in lower minimum noise figure, which is beneficial for lownoise amplification of RF signals. Lateral scaling of the active transistor area introduces a challenge in process integration of a nonselective SiGe epitaxial module in order to avoid facet growth at the isolation edge. Optimization for high fmax can be accomplished with a focus on reduction of the total base– collector capacitance (Cbc) and also depends on the emitter integration already discussed for fT optimization, as well as minimizing the extrinsic base resistance or base link, which dominates the total of the extrinsic and intrinsic components of base resistance.

225

0.5 ⫻ Re

200

Re

Peak fT (GHz)

175 2.0 ⫻ Re

150 125 100 75 50 25 0 0

1 2 3 Normalized collector doping

4

FIGURE 3.6.4 Calculated (lines) and measured peak fT as a function of collector doping and emitter resistance.

© 2006 by Taylor & Francis Group, LLC

3.6-288

The Silicon Heterostructure Handbook

For any given emitter integration, a compromise exists between fT and fmax as the collector design becomes more aggressive. The relationship for fmax with dependence on fT can be expressed as the following:

fmax

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ fT ¼ 8pRb Cbc

(3:6:2)

The increased collector doping shifts the Kirk effect to higher current and enables higher fT, but also increases Cbc and degrades fmax. The total Cbc is made up of two basic components: the intrinsic is determined by the collector design to achieve target fT; the parasitic extrinsic components, such as the junction from the pþ extrinsic base to the SIC and also to the nþ buried layer, can be reduced by scaling active area to lower Cbc and improve fmax. Scaling of the base–collector area can be represented by the design rule for active overplot of the emitter, as shown in Figure 3.6.5a for two different collector 22

SIC1 SIC2

21 20

SIC1

C bc (fF)

19 18 17

SIC2 = 0.8 ⫻ SIC1 Average doping level

16 15 14 13 0.15

(a)

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

Emitter active overplot (µm)

35

DR A DR B

Unilateral gain (db)

30

25

20

15

10

5

0 1⫻109

(b)

1⫻1010

1⫻1011

Frequency (Hz)

FIGURE 3.6.5 (a) Base–collector capacitance Cbc as a function of the active overplot of the emitter opening for two collector-doping levels. (b) Improvement in unilateral gain with reduced emitter active overplot.

© 2006 by Taylor & Francis Group, LLC

3.6-289

Industry Examples at the State-of-the-Art: Jazz

designs, one more highly doped at the base–collector junction, and the other more moderately doped. With smaller active sizing (i.e., smaller active overplot of emitter), there is a linear reduction of Cbc that is due to a lower coupling of the peripheral extrinsic component to the nþ buried layer. Since the magnitude of the reduction is dependent on the initial doping level, lateral scaling results in more significant Cbc reduction when a more aggressive, highly doped collector profile is used. Since the physical effect of this design rule is to reduce the length of the electrical connection to the intrinsic transistor, the total resistance would be expected to decrease for a given base resistance. This is not the case for the Jazz 0.18-mm SiGe bipolar transistor due to slow SiGe epi growth planes, dominated by a h3 1 1i type, that are less favorable for carrier transport and effectively reduce the active sizing from the original lithographic definition. Small changes to the optimization of the SiGe epi recipe and the integration process module limit facet growth and result in simultaneous Cbc and Rb reduction for the Jazz 200 GHz SiGe process (named SiGe200). The resultant fmax gains are significant, and reach beyond 200 GHz (Figure 3.6.5b). Intrinsic base resistance is lowered with reduced emitter width, and parasitic collector–base capacitance is lowered through reduction of the active base area. The resulting transistor has fT greater than 200 GHz (magnitude of H21) and fmax greater than 200 GHz (unilateral gain) for an emitter width of 0.15-mm.

3.6.3 SiGe BiCMOS Process Integration CMOS and bipolar performance targets within a BiCMOS technology should be considered simultaneously for a range of applications. Maintaining a significant gap between the fT of the n-type MOS transistor and the high-speed npn bipolar, as defined by fT versus line width in Figure 3.6.6, has broadened the application space for each process generation. Since the bipolar transistor is what defines the unique capability of SiGe BiCMOS, a number of process variants include the same self-aligned npn architecture with 0.25, 0.18, or 0.13-mm MOS transistors.

200 SiGe BiCMOS NPN

fT (GHz)

100 80 60

Si BiCMOS NPN

40 CMOS NFET

20

10 0.5

0.35

0.25

0.18 0.15

0.13

Technology (µm)

FIGURE 3.6.6 Performance curve as a function of process generation for production CMOS, BiCMOS, and SiGe BiCMOS technologies.

© 2006 by Taylor & Francis Group, LLC

3.6-290

The Silicon Heterostructure Handbook

Integration Sequence After buried layers are formed in bipolar collector regions, an epitaxially grown n-type silicon layer becomes the starting substrate for the n- and p-type MOS transistors. Standard well implant doses have been slightly adjusted versus the bulk CMOS process for the presence of the lightly doped n-type layer. An oxide-filled shallow trench is created and dual-gate oxides are grown in support of both 1.8 and 3.3 V MOS transistors. After gate formation and patterned opening of the bipolar base regions, the bipolar is integrated by first depositing a blanket SiGe layer using a single-wafer rapid thermal chemical vapor deposition (RT-CVD) reactor. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implant. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimension of the sacrificial emitter exactly defines the final emitter dimension. A collector implant differentiates the fT and BVceo of the three available npn transistors. Several dry etch steps are used to pattern the emitter poly and remove bipolar-related layers from the CMOS regions of the wafer. Next, the CMOS devices are completed with formation of side-wall spacers, implantation of source and drain, final implant activation and cobalt silicidation, all of which are shared with the SiGe bipolar device. Back-end options include three to six layers of metal with a 1 to 4 fF/mm2 MIM capacitor, a 25 ohm/sq metal resistor and up to a 5.2-mm-thick top metal layer and a 3-mm thick top dielectric layer to realize high-quality inductors. These results have been achieved with integrated 1.8/3.3 V dual-gate CMOS. Full digital library compatibility is maintained for 0.18-mm CMOS performance with the integration of the bipolar device. Idsat of the 1.8 V transistors is 600 and 255 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively. Options for a natural Vt MOS transistor and triple-well isolation are included in this modular technology. Compatibility with 0.13-mm dual-gate 1.2/3.3 V CMOS has also been demonstrated, as shown in the typical output curves in Figure 3.6.7. Idsat of the 1.2 V transistors is 500 and 215 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively.

CMOS Thermal Budget As CMOS is scaled, thermal budget constraints of advanced bipolar devices and CMOS devices diverge, leading to more difficult integration. The CMOS gate, re-oxidation, LDD, and pocket implants are included prior to SiGe epi deposition then the source–drain implants and final anneal are implemented after the SiGe bipolar transistor is completely formed. This limits the exposure of the SiGe transistor to CMOS-related thermal budget from the gate and re-oxidation cycles, which is key for technologies

1⫻10−3

Vd = 1.2 V

1⫻10−4 1⫻10−5

Vd = 0.1 V

Ids (A)

1⫻10−6 1⫻10−7 1⫻10−8

NFET

PFET

1⫻10−9

Lmin = 0.13 µm

1⫻10−10 1⫻10−11 1⫻10−12 1⫻10−13 −1.5

−0.5

0.5

1.5

V gs (V)

FIGURE 3.6.7 Subthreshold characteristics of generic 0.13-mm gate length CMOS integrated with a SiGe npn transistor (fT and fmax >200 GHz).

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-291

having a boron-doped silicon or silicon germanium base where the final base width was largely determined by subsequent thermal budget. The situation is different for a carbon-doped SiGe base profile since the use of carbon co-doping to arrest boron diffusion provides a level of independence from any subsequent thermal budget without compromising bipolar performance. However, while the design of the bipolar is less constrained, the CMOS is now limited by the thermal budget bake used to condition the surface prior to SiGe deposition. The optimization of thermal budget must strike a balance between CMOS performance and bipolar yield. Incomplete surface conditioning results in epi defectivity. This process is thermally activated with an activation energy of approximately 1.1 eV. As the footprint of the bipolar is reduced, some reduction in thermal budget will be possible. For example, shrinking the device area by half but keeping defectivity constant could allow nearly a 1008C reduction in bake temperature. Improvements of ex-situ wet processes and in-situ techniques for pre-cleaning and a reduction in active area due to lateral scaling can make it easier to integrate advanced SiGe devices with scaled CMOS.

SiGe npn Manufacturability A key to manufacturability of SiGe technology is the reuse of high-volume CMOS infrastructure. The maturity of process equipment, the high level of factory automation for recipe download and wafer handling, the yield management discipline, and the mechanisms for continuous improvement make it possible to deliver high-quality wafers in complex process technologies. For similar process complexity, as measured by the number of critical photomask layers or the number of process steps, the manufacturing cost and fab yield is comparable regardless of the technology specifics. It is the commitment to establishing process modules that are within the capability of the equipment set that makes it possible to deliver SiGe technology that is as repeatable and cost-effective as mainstream CMOS. RT-CVD has become the most commonly used process for silicon germanium epitaxy due to the commonality of equipment platforms with other production silicon technologies, and the advantages of single-wafer tools for small lot processes in the high mix manufacturing environment typical of many fabs. Single-wafer RT-CVD tools are used for process recipes such as epitaxial silicon growth on silicon substrates, deposition of heavily doped polycrystalline films, and selective silicon-raised source–drain structures. High-quality SiGe epitaxy required the addition of appropriate gas lines, procedures for minimizing oxygen and carbon contamination, and a redesigned wafer susceptor to achieve production worthy results. Focused efforts on both ex-situ and in-situ pre-clean capabilities were necessary to migrate from initial device level results to attainment of low defect density and high yield for typical levels of BiCMOS integration. Though usually limited to approximately 10,000 bipolar transistors and 250,000 CMOS gates for the integration of many analog/RF functions, the 0.18-mm technology must support upwards of 30,000 bipolar transistors and 1.5 million CMOS gates for practical designs. The ability to perform in-line measurement of SiGe epi thickness, germanium content, and boron doping level is required to establish typical production control charts. Spectroscopic ellipsometry can be used on production wafers to monitor SiGe epi thickness, as shown in Figure 3.6.8a. Demonstrated control of 1.64% 1-sigma variation provides feedback on the epi process. Measurement of poly thickness and in-line sheet resistance closes the loop for day-to-day SiGe manufacturing. Process variation related to the emitter formation, such as emitter pre-clean, in-situ poly doping, and final rapid thermal anneal, adds to the SiGe bipolar variability. Control of all of these parameters translates into resistances and vertical doping profiles that determine the range of bipolar fT, which is shown in Figure 3.6.8b to be 2.5% 1-sigma for over 40 production lots of a technology with mean fT greater than 155 GHz.

3.6.4 Process Customization In a technology landscape where standardization is accepted as the most straightforward route to economies of scale, the modularity of Jazz technology stands as an example of mass customization.

© 2006 by Taylor & Francis Group, LLC

3.6-292

The Silicon Heterostructure Handbook

SiGe Epi thickness (Angstroms)

460

USL

450 440 430 Epi in-line measurement

420 410

LSL

400 0

10

20

(a)

30

40

Sampled lots

240

fT fmax (GHz)

220 220 180 160 140

fT fmax

120 100 0 (b)

10

20

30

40

Sampled lots

FIGURE 3.6.8 (a) In-line measurement of SiGe epi thickness for a 40 lot sample of 0.18-mm production wafers. (b) Control of process parameters related to bipolar performance is indicated by small fT and fmax variation for a sample of production lots.

This approach requires rethinking all elements of technology delivery: process development, design kits, design libraries, and manufacturing control systems.

Wireless Technology Wireless applications require high-performance bipolar transistors with high-quality passives, and CMOS density suitable for moderate levels of mixed-signal and logic integration. As the integration of multistandard and multifunction devices in analog/RF subsystems is addressed, higher voltage CMOS and bipolar device options are added to enable integration of power management and power amplification functions. This is achieved in a wireless focused version of the Jazz 0.18-mm SiGe BiCMOS (SiGe90) process by adding modules that meet RF subsystem requirements, such as high-Q capacitors, inductors, and varactors that enable improved RF performance and reduced die size. For handset transceivers, 1.8 V CMOS is not generally required as large digital blocks are often placed on a separate base-band chip. Thus, a single-gate 3.3 V MOS transistor option is available in SiGe90 to reduce mask count and cost. Deep-trench isolation can be removed as most RF blocks (outside of possibly the prescaler) make use of larger devices that do not benefit as much from use of deep trench and are not as sensitive to collector–substrate capacitance. Also, a transistor with 155 GHz peak fT is not relevant for 2–5 GHz applications that typically operate at lower current densities. Because of low parasitics, the higher BVceo devices still maintain a high fmax and provide very good noise and low-current performance. Three different top via and thick metal module options are available for usage depending on the cost, integration level, and inductor performance requirements. A module with 3-mm deep top via and

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-293

5.2-mm thick aluminum offers a significant enhancement in inductor performance or reduction in inductor area for the same level of performance. A 1 kOhm/sq p-type poly resistor provides footprint and matching suitable for 2 to 6 GHz RF circuit design. Upgrade of the MIM capacitor to 2.0 fF/-mm2, or 4.0 fF/mm2 in its stacked topology, reduces capacitor area by using a scaled version of a nitride dielectric.

High Data Rate and High-Frequency Technology To enable implementation of circuits with data rates above 10 Gb/sec or frequencies up to 60 GHz, a fully featured version of the Jazz 0.18-mm SiGe BiCMOS process, SiGe120, is offered. The device set includes dual-gate 1.8/3.3 V CMOS and three SiGe npn transistors with fT of 155/78/38 GHz, four layers of standard metalization for dense digital logic and embedded SRAM, low-capacitance thin film metal resistors for high-frequency operation, a linear MIM capacitor with high Q, and two thick layers of aluminum (1.5 and 3.0-mm) for implementation of transmission lines and inductors. The addition of a higher performance SiGe npn transistor module with peak fT over 200 GHz (SiGe200), and higher fT and fmax over a large range of collector current, enables lower power circuits for networking applications, emerging wireless data standards from 20 to 60 GHz, and even collision-avoidance radar above 60 GHz for automobiles.

3.6.5 Summary Adding new features that build on established technology has resulted in a family of processes that offer a combination of active devices, passive components, and interconnect schemes specifically optimized for different types of products. In the mobile phone, extending the voltage capability of the transistor to 5 to 8 V to meet the requirements of RF power control, power management, and low drop out regulation enables higher levels of analog and RF product integration. High-density passives to scale down capacitor and inductor area can be more important to the reduction of die size than the scaling of digital blocks. Use of only the necessary process modules reduces overall manufacturing complexity, and ultimately cost of a design for a specific market segment. This specialty roadmap for analog and RF functional scaling will repeat with the maturation of subsequent generations of CMOS technology. There will be less emphasis on linewidth reduction and more effort related to the reuse of advanced CMOS process equipment for new materials and structures that advance the functional scaling of highly integrated mixed-signal, analog, and RF products.

Acknowledgments The author would like to thank the entire Jazz Semiconductor team for their technology development efforts, as well Marco Racanelli and Greg U’Ren for their direct contributions to this manuscript.

References 1. M Racanelli, Z Zhang, J Zheng, A Kar-Roy, P Joshi, A Kalburge, L Nathawad, M Todd, C Ukah, C Hu, C Compton, K Schuegraf, P Ye, R Dowlatshahi, G Jolly, and P Kempf. BC35: a 0.35 mm, 30 GHz, Production RF BiCMOS Technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 125–128. 2. A Chantre, M Marty, JL Regolini, M Mouis, J de Pontcharra, D Dutartre, C Morin, D Gloria, S Jouan, R Pantel, M Laurens, and A Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–100. 3. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freemen, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest International Electron Devices Meeting, San Francisco, 2002, pp. 771–774.

© 2006 by Taylor & Francis Group, LLC

3.6-294

The Silicon Heterostructure Handbook

4. M Racanelli and P Kempf. SiGe BiCMOS technology for communication systems. Extended Abstracts of the International Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 286–287. 5. M Racanelli, K Schuegraf, A Kalburge, A Kar-Roy, B Shen, C Hu, D Chapek, D Howard, D Quon, F Wang, G U’Ren, L Lao, H Tu, J Zheng, J Zhang, K Bell, K Yin, P Joshi, S Akhtar, S Vo, T Lee, W Shi, and P Kempf. Ultra high speed SiGe npn for advanced BiCMOS technology, International Electron Devices Meeting Washington, 2001, pp. 01-337–15.3.4. 6. K Oda, E Ohue, I Suzumura, R Hayami, A Kodama, I Shimamoto, and K Washio. Self-aligned selective-epitaxial-growth Si1xy GexCy HBT technology featuring 170-GHz fmax. International Electron Devices Meeting, Washington, 2001, pp. 2–5. 7. M Racanelli and P Kempf. SiGe BiCMOS technology for communication products, Custom Integrated Circuits Conference, San Jose, 2003, pp. 331–334. 8. M Kamat, P Ye, Y He, B Agarwal, P Good, S Lloyd, and A Loke. High performance low current CDMA receiver front end using 0.18-mm SiGe BiCMOS. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 23–26. 9. P Ma, M Racanelli, J Zheng, and M Knight. A 1.4 mA and 3 mW, SiGe90, BiFET low noise amplifier for wireless portable applications. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 237–240. 10. P Ye, B Agarwal, M Reddy, L Li, J Cheng, PC Mudge, E McCarthy, and SL Lloyd. High performance circuits in 0.18-mm SiGe BiCMOS process for wireless applications. IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 329–332. 11. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. 25th GaAs IC Symposium, San Diego, 2003, pp. 183–186.

© 2006 by Taylor & Francis Group, LLC

3.7 Industry Examples at the State-of-the-Art: Hitachi

Katsuyoshi Washio Hitachi Ltd.

3.7.1 3.7.2 3.7.3 3.7.4 3.7.5

Introduction............................................................... 3.7-295 SiGe HBT Technologies ............................................ 3.7-296 SiGe BiCMOS Technologies ..................................... 3.7-300 Interconnection and Passive Elements .................... 3.7-303 Summary .................................................................... 3.7-305

3.7.1 Introduction High-speed monolithic integrated circuits (ICs) and large-scale ICs (LSIs) are the key components for multigigabit data communication systems and wide-bandwidth radio communication systems. Such systems include backbone networks, intercity communication networks, local area networks, and Ethernet for data communications, and microwave and millimeter-wave mobile networks, fixed wireless access, and intelligent transport systems for radio communications. To meet the growing demand for such systems, both high-speed digital operation with sophisticated functions and high-frequency analog operation should be implemented. From this point of view, high-speed SiGe HBT and SiGe HBT with CMOS (BiCMOS) technologies are the most promising candidates to meet these requirements. This is because SiGe HBTs with a sub-5-psec ECL-gate delay and cutoff frequency about 200 GHz have been successfully demonstrated and can be fabricated by the well-established Si process, which is fully compatible with the CMOS process. For the widespread application of these devices in high-speed digital and RF analog ICs/LSIs, SiGe HBTs must be fabricated at a high yield. Moreover, high-quality passive elements, including high-precision resistors, a high-Q varactor, an MIM capacitor, and high-Q inductors, should also be available for integration on a chip. Consequently, technologies for fabricating a self-aligned SiGe HBT by selective epitaxial growth (SEG) and SiGe BiCMOS have been developed. This self-aligned SEG concept can be expected to achieve highspeed and low-power performance as a result of small parasitic resistances and capacitances. A selfaligned SEG SiGe HBT that has shallow-trench and dual-deep-trench isolations (DTIs) and Ti–salicide electrodes was fabricated on a 200-mm wafer line. The fabrication process is almost completely compatible with the 0.2-mm BiCMOS technology that is applied in fabricating fast-cache memory chips. To improve cutoff frequency, maximum oscillation frequency, and ECL-gate delay, optimization of the width of the SiGe SEG layer and the thickness of the Si-cap layer, incorporation of C to suppress B out-diffusion, and application of thin and heavily-boron-doped base have been investigated. In the case of SiGe BiCMOS technology, CMOS devices with gate lengths of 0.25 mm to 80 nm were integrated. For both the SiGe HBT and BiCMOS technologies, a four-level or five-level metal layer structure for interconnection was formed by chemical–mechanical polishing (CMP). Concerning the integration 3.7-295 © 2006 by Taylor & Francis Group, LLC

3.7-296

The Silicon Heterostructure Handbook

of high-quality passive elements, a high-precision poly-Si resistor with a ‘‘quasi-layer-on-layer’’ structure, a high-Q varactor constructed of a SiGe-base and a Si-collector junction, an MIM capacitor formed between the first and second metal layers by plasma SiO2 as an insulator, and a high-Q inductor fabricated by using the fourth metal layer are available for integration on the same chips as active devices.

3.7.2 SiGe HBT Technologies A scanning electron microscopy (SEM) cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT is shown in Figure 3.7.1, including an enlarged view of the active region, the key part of the SiGe HBT [1]. The 0.6-mm-wide Si-cap/SiGe-base multilayer was selectively grown in self-alignment with the 0.2-mmwide emitter by ultrahigh vacuum/chemical vapor deposition (UHV/CVD) [2]. A poly-Si-assisted selfaligned SEG (PASS) structure was applied to provide a good link between the intrinsic SiGe and extrinsic

Base

Emitter

Collector 1st metal

Ti salicide

W 1 µm

Shallow trench Dual deep trench

IDP 0.2 µm Base poly Si

Si/SiGe SEG Poly-SiGe

Buffer poly-Si

FIGURE 3.7.1 An SEM cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT with an enlarged active region, the key part of the SiGe HBT. A 0.6-mm-wide Si-cap/SiGe-base multilayer self-aligned to a 0.2-mm-wide emitter was selectively grown by UHV/CVD. A poly-Si-assisted self-aligned SEG (PASS) structure, shallow-trench and dualdeep-trench isolations, and Ti–salicide electrodes were applied. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Hitachi

3.7-297

poly-Si bases [3, 4]. In the PASS structure, a poly-SiGe base contact was grown, at the same time as the intrinsic SiGe base, around the buffer poly-Si and beneath the extrinsic base poly-Si. This self-aligned active-region structure enabled both low collector capacitance and low base resistance. Furthermore, 0.4-mm-deep shallow-trench isolation (STI) and 0.6-mm-wide 3-mm-DTIs were used to reduce the parasitic capacitances of the collector and substrate, respectively. Ti–salicide layers, with a sheet resistance of 3 V/sq. and contact resistance of about 25 V mm2, were formed on all the electrodes to reduce their parasitic resistances. The process steps in the fabrication of the self-aligned SEG SiGe HBT are explained as follows (Figure 3.7.2). An nþ buried layer (BL) was formed by ion implantation of antimony followed by annealing. A 0.3-mm-thick Si epitaxial layer was then formed. Next, the shallow- and dual-deep-trench grooves for the isolation were formed and filled up with SiO2 by planarization with CMP. Next, the intrinsic region was covered by the three successively deposited films of Si3N4, poly-Si, and SiO2. This multilayer was used to form the PASS structure. An amorphous Si film for the base poly-Si and a thick SiO2 film were then deposited, and a window to the intrinsic region was opened in these films by etching. The first selectively implanted collector (SIC1) region was then formed by phosphorus-ion implantation through the multilayer and into the Si epitaxial layer. After that, the SiO2 film remained on the sidewall of the window after reactive-ion etching (RIE). The Si3N4 film was then deposited, and it remained on the sidewall of the window. At that time, the top film of the multilayer, the Si3N4, was etched. After that, the remaining films of multilayer, poly-Si and SiO2, were selectively etched. The Si3N4 film was then removed from the sidewall, and the window in the Si3N4 film of the multilayer was enlarged by wet side-etching. Next, the Si-cap/SiGe-base multilayer was selectively grown by UHV/CVD using Si2H6, GeH4, and B2H6 source gases at 5508C for the SiGe layer and Si2H6 at 5808C for the Si layer. The SEG layer consisted of a 15-nm-thick Si cap, 20-nm-thick

FIGURE 3.7.2 Process steps for fabricating the self-aligned SEG SiGe HBT. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-298

The Silicon Heterostructure Handbook

Si1xGex , 40-nm-thick Si0.85Ge0.15, and 10-nm-thick Ge-retrograded (from 15% to 0) Si1xGex . A 15nm-thick 2 1019 cm3 boron-doped Si1xGex layer was formed as the intrinsic base. The poly-SiGe base contact was formed simultaneously with the intrinsic SEG, and this formation was assisted by the middle film of the multilayer, the poly-Si (which was used as a buffer). Next, phosphorus ions were implanted in the lower part of the SEG layer to form the second SIC region (SIC2). Double selective implantations of phosphorous were applied to increase the collector-doping level to about 1 1018 cm3. Thin SiO2 and in situ phosphorus-doped poly-Si (IDP) layers were deposited, and the IDP film remained on the sidewall of the window. After an emitter area had been opened by wet etching of the thin SiO2, a second IDP layer was deposited. A shallow emitter with a junction depth of about 20 nm was formed by diffusion from the IDP layers into the Si-cap layer at 9008C for 30 sec. Next, Ti–salicide layers on all electrodes of the emitter, base, and collector were formed simultaneously in a self-aligned manner. The SiGe HBT was fabricated on a 200-mm wafer line and the process to fabricate the SiGe HBTs is, with the exception of the SEG, almost the same as the 0.2-mm BiCMOS process [5]. The process is thus completely compatible with BiCMOS technology. The designed profile of the SiGe layer after SEG, featuring dual plateaus with an intermediately Gegraded slope (DPIG), is shown in Figure 3.7.3. The Ge profile of the SiGe layer was designed as follows: two plateaus with Ge contents of 10% (on the surface side) and 15% (on the substrate side), a 5-nm-thick Ge-graded layer between the plateaus, and two Ge-graded layers at the interfaces with the Si-epitaxial and Si-cap layers. This DPIG Ge profile was designed to enable precise controllability of the collector current against deviation in the position of the emitter–base junction. At the end of the process, the base was about 30-nm wide, so the two plateaus and the intermediate Ge-graded layer were located in the base. Note that this layer provided an internal drift field in the conduction band and enabled a short base transit time and a high Early voltage in a similar way to the conventional graded-Ge profile. The emitter–base junction was located at the 10%-Ge plateau, and the thickness of this plateau was sufficient to suppress changes in the effective base Gummel number caused by deviation in the emitter–junction depth. The SiGe HBT, with an emitter area AE of 0.2 2 mm, exhibited good I–V performance with a high current gain of 1400. The ideality factor of the base current IB was 1.10, and the base-recombination current was below 10 pA. The HBT yield, measured from 4000 parallel-connected transistors, was more than 99.9993%. These DC characteristics show that no defects were created in the strained Si/SiGe multilayer during the thermal cycles for the HBT formation. The slope of the Arrhenius plot of the normalized current gain indicates that the Ge-induced bandgap reduction for the strained SiGe base layer

NB = 2 1019 cm−3 w B = 15 nm

B

Ge content (%)

15

Ge2

10

Ge1 SEG I/F

5

0 0

20

40 60 Depth (nm)

80

100

FIGURE 3.7.3 A schematic view of the designed profile, featuring dual plateaus with intermediate Ge-graded slope (DPIG) for the SiGe layer after SEG. Ge1 is the Ge content of the lower plateau and Ge2 is that of the upper plateau. At the end of the process the base was about 30 nm wide, so both plateaus and the intermediate Ge-graded layer were located in the base. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-299

Industry Examples at the State-of-the-Art: Hitachi

was 110 meV, which verifies that there was no relaxation in the SiGe layer. The typical transistor characteristics of a SiGe HBT with an emitter area of 0.2 2 mm are summarized in Table 3.7.1. Figure 3.7.4 shows the dependence of the differential ECL gate-delay time on the switching current as measured from 53-stage ring oscillators with a fan-in and a fan-out of 1 at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The SiGe HBTs have an emitter area of 0.2 2 mm. A minimum ECL-gate delay time of 5.5 psec was measured at a switching current of 2 mA. Analysis of the delay components that made up this delay time showed that the contributions of load resistance, base resistance, forward transit time, and other factors were 1.48, 2.39, 0.93, and 0.70 psec, respectively. The power-delay product of the ECL circuit composed of a SiGe HBTwith an emitter area of 0.2 0.5 mm was low, i.e., 4.4 f J. The fast- and low-power performance of the ECL gate was attributed to the low collector capacitance and the low substrate capacitance enabled by the shallow-trench and dual-DTIs, high fT and fmax of the fully selfaligned SEG SiGe HBT structure, and the low parasitic resistance of the Ti–salicide electrodes. TABLE 3.7.1 Typical SiGe HBT Characteristics with an Emitter Area of 0.2 2 mm 0.2 2 mm2 1400 1.9 V 3.0 V 6.3 V 90 V 3.6 fF 1.8 fF 122 GHz 163 GHz 5.5 ps

Emitter area Current gain BVCEO BVCER BVCBO Base resistance Collector capacitance Substrate capacitance Cutoff frequency Max. oscillation frequency ECL min. gate delay

Source : From K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.

30 Differential ECL gate AE = 0.2 2 µm

53-stage R. O. 10

50 mV/div.

ECL gate delay time (ps)

20

VL = 250 mV

8 500 ps/div. 6 5.5 ps 4 0.3

3 1 Switching current (mA)

10

FIGURE 3.7.4 Dependence of the differential ECL gate-delay time on the switching current as measured from ring oscillators. Each SiGe HBT had an emitter area of 0.2 2 mm and ran at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The fan-in and fan-out were 1. The output waveform of a 53-stage ECL ring oscillator as measured at a switching current of 2 mA is also shown. A minimum ECL gate-delay time of 5.5 psec was measured. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-300

The Silicon Heterostructure Handbook

Optimization of the device structure and the intrinsic impurity profile were investigated [6, 7]. They are related to the collector–base and emitter–base junctions of the self-aligned SEG SiGe HBTs by varying the width of the SiGe SEG layer and the thickness of the Si-cap layer, respectively. The incorporation of carbon to suppress boron out-diffusion of the base was performed [8]. This is effective both to improve high-speed performance and to reduce fluctuations in device performance by alleviating the lattice strain. Furthermore, a thin and heavily-boron-doped base toward a thickness of 1 nm is applied [9]. As a result, a cutoff frequency of 174 GHz, a maximum oscillation frequency of 204 GHz, and an ECL-gate delay of 4.8 psec were obtained. For low-power and high-speed operation, a scaled-down SiGe HBT, structurally optimized for an emitter scaled-down towards 100 nm, was also developed [10].

3.7.3 SiGe BiCMOS Technologies A cross-sectional SEM image of the 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor, and a polySi resistor on an SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm) is shown in Figure 3.7.5 [11]. The SiGe HBT was fabricated in the manner described above. A 4 1019 cm3 boron-doped 10-nm-thick (as SEG) Si0.95Ge0.05 layer was used as the intrinsic base. A 0.5-mm-wide DTI reaches the buried SiO2. The drawn CMOS gate lengths were 0.25 mm (nMOS) and 0.3 mm (pMOS). The gate electrode was constructed of a layer of 50-nm-thick TiSi2 (formed simultaneously with the other electrodes) stacked on 300-nm-thick nþ-doped poly-Si. The process sequence of SiGe BiCMOS is shown in Figure 3.7.6. The standard steps of the bipolar fabrication process were carried out from the formation of the nþ buried collector layer to the deep trench isolation. A 0.3-mm CMOS process module was then inserted. The thickness of the gate oxide was 6.5 nm. A poly-Si resistor was also formed from nþ-doped gate poly-Si for low sheet resistance (LR). After CMOS formation, the process sequence returns to continue with the bipolar process sequence. During the fabrication of self-aligned SEG SiGe HBTs, the CMOS and poly-Si resistor areas are covered by SiO2. A poly-Si layer was deposited and patterned. Boron and germanium ions were then implanted

M4 (3µm)

M3 MIM-C M2 M1

via TiSi2 poly Si-R

SiO2 (0.3 µm)

SiGe HBT

HRS (1 kΩcm)

nMOS

pMOS

5 µm

FIGURE 3.7.5 Cross-sectional SEM image of a 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor (drawn gate lengths were 0.25 mm for nMOS and 0.3 mm for pMOS), and a poly-Si resistor on a 200-mm SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm). A four-level metal (M1–M4) layer structure was used for interconnection. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-301

Industry Examples at the State-of-the-Art: Hitachi

SiGe HBT n+ buried collector (Sb+) n− epitaxial growth (0.3 µm) Shallow (0.35 µm) trench isolation Collector plug Deep (1µm) trench isolation MR & HR poly-Si (w/ Ge I/I) Base poly-Si (0.2 µm) Emitter window & SIC1 SiGe SEG & SIC2 Emitter poly-Si (in-situ P-doped)

CMOS n & p well I/I Gate poly-Si (LR) PTS I/I & LDD n & p S/D I/I

Ti-salicide Contact & W plug 1st metal & via MIM capacitor 2nd to 4th metal

FIGURE 3.7.6 Process sequence for 0.2-mm SOI/HRS SEG SiGe HBT/CMOS. A 0.3-mm CMOS process module was inserted after formation of the trench isolations. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

to form pþ poly-Si resistors for medium (MR) and high (HR) sheet resistances. After the deposition of oxide, a 0.2-mm-thick poly-Si layer was formed for the base electrode. Phosphorous ions were implanted after the emitter window opening to form SIC1 and after the SiGe SEG to form SIC2. This can provide optimized collector profiles for both high-speed and high-voltage HBTs. The formation of the emitter poly-Si electrode is followed by the process sequence of an interconnection process module. Numbers of masks used were ten for the SiGe HBTs, ten for the CMOS transistors, and three for the poly-Si resistors. The effectiveness of the DPIG Ge profile was confirmed by the dependence of the current gain on Ge1, the Ge content of the lower plateau. As a result, even for HBTs with various Ge2 (the Ge content of the upper plateau) in the range from 7.5% to 15%, the collector current was well controlled by Ge1 and was independent of Ge2. This indicates that the collector current is mainly determined by the bandgap narrowing of the lower plateau. Therefore, the lower plateau suppresses the change in the effective base Gummel number, which occurs with the conventional graded-Ge profile because of the fluctuation in the emitter–junction depth. Good I–V performance, with a current gain of about 300, is confirmed in the Gummel plots for single and 104 parallel-connected HBTs with an emitter area AE of 0.2 1 mm. The averaged forward base tunneling current was about 2 pA/HBT. The respective ideality factors of the collector current IC and base current IB were 1.007 and 1.075. The current gain was higher than 100 in the zlow-collector-current region up to 1 nA. The HBT yield, as measured from sets of 104 HBTs connected in parallel, was about 99.9997%, which means the defect density was about 2000 defects/cm2 under the assumption of a relaxed-limited yield. This means that the limit on the number of HBTs that may be integrated is about 105. The reliability under the forward- and reverse-bias stressing was investigated and compared with manufactural Si BJTs with guaranteed 10-year operation as a control. No change in the collector and base current were viable at JC up to 60 mA/mm2 under forward-bias stress, and a similar behavior of the base current to that of a Si BJT under reverse-bias stress up to a VEB of 3.5 V were observed. As a result, high reliability of SiGe HBTs was confirmed. The HBT characteristics, breakdown voltage, and high-frequency performance were controlled by the collector sheet concentration NS through the double selective phosphorus implantations in the 0.3-mmthick Si epitaxial layer and in the undoped SiGe. The breakdown voltage BVCEO was 2.5 V for the HSHBT and 3.9 V for the HV-HBT. The high Early voltage VA of more than 100 V for both HBTs indicates that the collector current was determined by the drift field created by the bandgap grading. The dependence of the cutoff frequency fT and maximum oscillation frequency fmax on the collector current

© 2006 by Taylor & Francis Group, LLC

3.7-302

The Silicon Heterostructure Handbook

for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm are shown in Figure 3.7.7. The peak fT of the HS-HBT with an emitter area AE of 0.2 1 mm and the HVHBT with an AE of 0.2 4 mm were 76 and 47 GHz, respectively. The peak fT for the HV-HBT was about 60% of that for the HS-HBT, and the collector current density at the peak fT for the HV-HBT was about one fourth of that for the HS-HBT. The dependence of the peak fT on BVCEO was also investigated, and their product was about 190 GHz V. The peak fmax for the HS-HBT was 180 GHz and even that for

100 HS-HBT AE = 0.2 1 µm

Cutoff frequency (GHz)

80

60

40 HV-HBT AE = 0.2 4 µm

20

0 0.1

0.3

1

3

Collector current (mA)

(a)

40

150

HS-HBT AE = 0.2 1µm

30

10

10 100 Frequency (GHz)

40

50

0.3

fmax 180 GHz

VCE = 2 V IC = 0.7 mA 1

HV-HBT AE = 0.2 4 µm

U

MSG/ MAG

20

0 100

0 0.1 (b)

MSG/MAG, U (dB)

AE = 0.2 1 µm HS-HBT

1

Collector current (mA)

3

MSG/MAG, U (dB)

Maximum oscillation frequency (GHz)

200

HV-HBT AE = 0.2 4 µm

30

U

20

MSG/ MAG

10

VCE = 2 V IC = 0.7 mA

0 1

fmax 125 GHz

10 100 Frequency (GHz)

FIGURE 3.7.7 Dependence of the cutoff frequencies (a) and maximum oscillation frequencies (b) on collector current for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-303

Industry Examples at the State-of-the-Art: Hitachi TABLE 3.7.2 Typical Transistor Parameters for the HS-HBT with an Emitter Area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm

WE (mm) LE (mm) hFE n VA (V) BVCEO (V) BVCBO (V) RB (V) RE (V) CJE (fF) CJC (fF) CSUB (fF) fT (GHz) fmax (GHz) min ECL tpd (psec)

HS

HV

0.2 1 300 1.007 >100 2.5 10.0 120 27 3.7 1.9 1.1 76 180 7.8

0.2 4 300 1.007 >100 3.9 11.5 45 9 13.4 3.4 2.2 47 125 –

Source: From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

the HV-HBT was 125 GHz, thanks to both the low collector capacitance, which was a result of the selfaligned SEG structure and optimized collector profile, and the low base resistance. These results indicate that both HBTs are very suitable for high-frequency analog applications. Typical transistor parameters for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm are summarized in Table 3.7.2. Here, CSUB was reduced to about 60% of that without SOI [12]. This is because CSUB is given by the series connection of the depletion capacitance under the nþ buried collector and the capacitance of the buried oxide. To improve the functionality, scaled CMOS with gate lengths of 0.18 mm [13], 0.13 mm [14], and 80 nm [15] in SiGe BiCMOS technologies have been advanced by optimizing process flow and reducing thermal budgets.

3.7.4 Interconnection and Passive Elements A cross-sectional view of the four-level structure of metal layers with an MIM capacitor is also shown in Figure 3.7.5. The structure of metal layers for use in interconnection was fabricated by applying CMP to planarize the tungsten deposited for the 0.5-mm-wide contact plugs and 0.6 0.6-mm via holes and to planarize the plasma–SiO2 interlayer insulators. All of the metal layers were multilayered structures of Al, Ti, and TiN. A concave MIM capacitor with a capacitance of 0.7 fF/mm2 was formed between the first- and second-level metal layers by using a 50-nm-thick layer of plasma SiO2 as an insulator. The third- and fourth-level (3-mm-thick Al) metal layers made up high-Q spiral inductors. Eleven masks were used for the four-level structure of metal layers for interconnection, including the MIM capacitor. Precise resistors were formed from pþ poly-Si, with a ‘‘quasi-layer-on-layer’’ structure fabricated by Ge implantation, for medium and high sheet resistances (MR, HR) in the SiGe BiCMOS. A cross-sectional TEM image of a precise poly-Si resistor is shown in Figure 3.7.8. By using high-dose Ge implantation, roughly the upper half of the poly-Si layer with small grains as deposited (deposition temperature TD was higher than 6008C) became amorphous. It then changed to large-grain poly-Si by recrystallization after annealing. The ‘‘quasi-layer-on-layer’’ structure was thus fabricated. The temperature coefficient TC of resistance for large-grain poly-Si is positive, while that for small-grain poly-Si is negative. Therefore, these opposite characteristics act to cancel out the temperature dependence of the resistance. Further-

© 2006 by Taylor & Francis Group, LLC

3.7-304

The Silicon Heterostructure Handbook

Poly-Si deposition (TD>600C) Small-grain poly-Si

B and Ge I/I (high dose) Amorphous Si Small-grain poly-Si

Annealing (recrystallization)

Positive TC

Large-grain amorphous poly-Si Si Small-grain poly-Si Negative TC

Large grains

Small grains

50 nm FIGURE 3.7.8 Cross-sectional TEM image of a precise poly-Si resistor formed from pþ poly-Si with a ‘‘quasi-layeron-layer’’ structure fabricated by Ge implantation, for both medium sheet resistance (MR) and high sheet resistance (HR) in the SiGe BiCMOS. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

more, this ‘‘quasi-layer-on-layer’’ structure made the precise control of the sheet resistance possible; the sheet resistance was mainly determined by the thickness of the upper large-grain poly-Si layer with low resistivity, and its thickness could be controlled well by the Ge-implantation energy. The parameters of the passive elements are summarized in Table 3.7.3. An ordinary nþ poly-Si resistor, LR (low sheet resistance of 65 V/sq.), had a temperature coefficient of 600 ppm/8C. On the other hand, both types of pþ poly-Si resistors with a ‘‘quasi-layer-on-layer’’ structure, MR (medium sheet resistance of 220 V/sq.) and HR (high sheet resistance of 635 V/sq.), had low temperature coefficients of 330 and 180 ppm/8C, respectively. The MIM capacitor with an area of 50 100 mm and a capacitance of 4.2 pF, which is usually used to stabilize the supply voltage, had an adequate Q of 13 at 10 GHz. In 10 parallel-connected varactors, each with a SiGe-base and Si-collector junction area of 2.3 2.3 mm, the ratio of Cmax to Cmin for VCB of 0 to 3 V was 1.8 and Q was 45 at 10 GHz and a VCB of 1.5 V. This high-Q varactor is applicable to oscillators with a high-purity signal spectrum for use in mobile communications. A three-turn square (132 mm on the outer sides) spiral inductor with a cavity at the center and a line width/line-to-line space of 6/3 mm was formed on a standard low-resistivity substrate (LRS) in the SiGe HBT process. It had L value of 1.36 nH and Q of 8.8 at 5.8 GHz, and L of 1.45 nH and Q of 15.1 at 10 GHz. The octagonal spiral inductor on the SOI/HRS was compared with that on an SOI/LRS. The width and spacing were 9 and 3 mm, respectively. The frequency dependence of the

© 2006 by Taylor & Francis Group, LLC

3.7-305

Industry Examples at the State-of-the-Art: Hitachi TABLE 3.7.3 Resistor

Passive-Element Parameters nþ poly (LR) pþ poly (MR) pþ poly (HR)

Capacitor

MIM

Varactor

MOS SiGe/Si

Inductor

Oct. spiral

65 V/sq. 600 ppm/8C 220 V/sq. 330 ppm/8C 635 V/sq. 180 ppm/8C 0.7 fF/mm2 13 Q(10 GHz) 4.7 fF/mm2 1.8 (Cmax/Cmin) 45 Q(10 GHz) 0.95/19 nH/Q (10 GHz)

Source : From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

inductance was the same on the HRS and LRS; however, Q of the HRS became higher at frequencies above 5 GHz, and Q at 15 GHz on the HRS was about twice that on the LRS. These results indicate that the high-resistivity substrate is effective in reducing conductive loss through the Si substrate in the microwave band. The octagonal spiral inductor on the HRS, with an L value of 0.95 nH, showed a highQ of 19 at 10 GHz.

3.7.5 Summary Self-aligned SiGe HBT and BiCMOS technologies have been developed. A Si-cap/SiGe-base multilayer fabricated by the SEG method was applied to improve both high-speed and low-power performance of the SiGe HBTs. The process is almost completely compatible with well-established Si BiCMOS technology, and the SiGe HBT and BiCMOS were fabricated on a 200-mm wafer line. To meet the demand for the integration of sophisticated functions, high-quality passive elements, including a high-precision poly-Si resistor, a high-Q varactor, an MIM capacitor, and a high-Q spiral inductor, have also been developed.

Acknowledgments The author would like to express his sincere thanks to Dr. A. Anzai, Dr. Y. Hatta, and H. Hosoe at the Hitachi Device Development Center (HDDC), and Dr. O. Kanehisa, Dr. K. Seki, and K. Kimura at the Hitachi Central Research Laboratory (HCRL) for their encouragement. The author would also like to express his sincere thanks to Dr. T. Onai, E. Ohue, K. Oda, Dr. M. Kondo, H. Shimamoto, M. Tanabe, R. Hayami, Dr. Y. Kiyota, I. Suzumura, Dr. M. Miura, A. Kodama at HCRL, and to T. Harada, K. Mikami, T. Hashimoto, S. Wada, T. Tominari, K. Tokunaga at HDDC for their extensive contributions throughout this work.

References 1. K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. A 0.2-mm self-aligned selective-epitaxial-growth SiGe HBT featuring 107-GHz fmax and 6.7-ps ECL. IEEE Trans. Electron Devices 48:1989–1994, 2001. 2. K. Oda, E. Ohue, M. Tanabe, H. Shimamoto, T. Onai, and K. Washio. 130-GHz fT SiGe HBT technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 1997, pp. 791–794.

© 2006 by Taylor & Francis Group, LLC

3.7-306

The Silicon Heterostructure Handbook

3. K. Washio, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, T. Onai, and M. Kondo. A selectiveepitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay. IEEE Trans. Electron Devices 46:1411–1416, 1999. 4. K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Kondo, S. Kondo, Y. Homma, N. Owada, and T. Ikeda. A 0.2-mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 209–212. 6. E. Ohue, R. Hayami, K. Oda, H. Shimamoto, and K. Washio. 5.3-ps ECL and 71-GHz static frequency divider in self-aligned SEG SiGe HBT. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 26–29. 7. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, and H. Shimamoto. Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic Frequency Dividers. IEEE Trans. Electron Devices 49:1755–1760, 2002. 8. K. Oda, E. Ohue, I. Suzumura, R. Hayami, K. Kodama, H. Shimamoto, and K. Washio. Highperformance self-aligned SiGeC HBT with selectively grown Si1xyGexCy base by UHV/CVD. IEEE Trans. Electron Devices 50:2213–2220, 2003. 9. T. Tominari, S. Wada, K. Tokunaga, K. Koyu, M. Kubo, T. Udo, M. Seto, K. Ohhata, H. Hosoe, Y. Kiyota, K. Washio, and T. Hashimoto. Study on extremely thin base SiGe:C HBTs featuring sub 5-ps ECL gate delay. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 107–110. 10. K. Washio, E. Ohue, R. Hayami, A. Kodama, H. Shimamoto, M. Miura, K. Oda, I. Suzumura, T. Tominari, and T. Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Trans. Electron Devices 50:2417–2424, 2003. 11. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. 12. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Harada, and M. Kondo. 82GHz dynamic frequency divider in 5.5ps ECL SiGe HBTs. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 210–211. 13. S. Wada, Y. Nonaka, T. Saito, T. Tomonari, K. Koyu, K. Ikeda, K. Sakai, K. Sasahara, K. Watanabe, H. Fujiwara, F. Murata, E. Ohue, Y. Kiyota, H. Shimamoto, K. Washio, R. Takeyari, H. Hosoe, and T. Hashimoto. A manufacturable 0.18-mm SiGe BiCMOS technology for 40-Gb/s optical communication LSIs. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 84–87. 14. T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahara, T. Tomonari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washio, and H. Hosoe. Integration of a 0.13-mm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 779–782. 15. T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, and H. Hosoe. Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 129–132.

© 2006 by Taylor & Francis Group, LLC

3.8 Industry Examples at the State-of-the-Art: Infineon

T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck Infineon Technologies AG

3.8.1.

3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6

Introduction............................................................... 3.8-307 Process Concept......................................................... 3.8-308 Transistor Fabrication Process ................................. 3.8-309 Transistor Results ...................................................... 3.8-311 Additional Devices .................................................... 3.8-315 Circuit Performance .................................................. 3.8-316

Introduction

Recent advances [1–7] in state-of-the-art SiGe bipolar and BiCMOS technologies enabled impressive transistor parameters like maximum oscillation frequencies of 285 GHz [1], transit frequencies up to 350 GHz [2] and ring-oscillator gate delay times down to 3.5 psec [5, 7]. Therefore, even very highfrequency applications like wireless LANs at 60 GHz, optical communications at 80 Gbit/sec and automotive radar systems around 77 GHz, which can now only be achieved by expensive III–V technologies, seem to become feasible in a low-cost silicon-based technology in a highly integrated manner. The progress in the high-speed performance of SiGe HBTs has been achieved by impurity profile engineering in the SiGe base for improving forward transit time and base resistance as well as by the development of self-aligned transistor architectures providing low parasitic capacitances and low extrinsic series resistances. The different self-aligned emitter–base configurations, which are used in present state-of-the-art SiGe HBT technologies, are requiring either nonselective epitaxial growth (NSEG) [1, 2, 5] or selective epitaxial growth (SEG) [3, 4, 6, 7] for the integration of the SiGe base. As an example of such an advanced SiGe HBT technology, we describe here Infineon’s high-frequency SiGe bipolar technology. The SiGe technology is based on a double-polysilicon self-aligned (DPSA) transistor configuration, in which the shallow and highly boron-doped SiGe base layer is integrated by means of SEG. The first realizations of such transistors have used epitaxial silicon base layers which have been grown without Ge [8–10]. Because of the superior performance of the SiGe base over the epitaxial Si base, within the next couple of years processes for DPSA HBTs with selectively grown SiGe base layers have been developed [11–14]. Even the first of these DPSA HBTs that were fabricated in 1992 [11] exhibited a maximum oscillation frequency of 50 GHz and a ring oscillator gate delay time of 19 psec, which was state-of-the-art performance at that time. Using the DPSA HBT concept Infineon’s first SiGe bipolar technology, which has been taken into production for the wireless marketplace in the year 1999 [15], exhibited transit and maximum oscillation frequencies of about 75 GHz. In the meantime the transistor performance of DPSA HBTs with a selectively grown SiGe base could be improved considerably, resulting in bipolar and BiCMOS processes with transit and maximum

3.8-307 © 2006 by Taylor & Francis Group, LLC

3.8-308

The Silicon Heterostructure Handbook

oscillation frequencies of 200 GHz or above [3, 4, 6, 7]. These advancements have been achieved for example by improvements in shallow base formation technology, which has resulted in reduced base thickness even for significantly increased base boron doping levels, as well as by minimizing the size of the transistors for commensurate improvements of base resistance, emitter–base capacitance, and base– collector capacitance. In the following we describe the process concept, the fabrication process, and the electrical results of Infineon’s actual high-frequency SiGe bipolar technology. The technology provides a transit frequency of 200 GHz, a maximum oscillation frequency of 275 GHz, and a ring oscillator gate delay time of 3.5 psec [7]. The bipolar technology is presently under investigation for the realization of very demanding high-frequency applications like 77 GHz automotive radar and optical communications up to 80 Gbit/sec.

3.8.2.

Process Concept

A transmission electron microscopy (TEM) cross section of the npn transistor in the SiGe technology is shown in Figure 3.8.1. The transistor has a deep trench/shallow trench isolation which is commonly used in advanced SiGe HBT technologies. The transistor isolation has a completely planar surface topography which is of great advantage for the realization of small feature sizes and small lithographic alignment tolerances in order to minimize the sizes of the transistors. In addition the deep trenches are useful in enabling the realization of high transistor packing densities in circuits and also allow the realization of small subcollector dimensions for achieving low values of the collector–substrate capacitance. The transistor, which is built onto this transistor isolation, has a DPSA emitter–base structure, which uses highly boron-doped and silicided polysilicon layers for contacting the SiGe base of the active transistor. These pþ-polysilicon base electrodes are separated self-aligned by a thin oxide spacer from the heavily arsenic-doped emitter layer. As compared to transistor concepts realizing the separation of the emitter from the extrinsic base regions by a photolithographic alignment step, the self-alignment of the emitter–base structure is very advantageous for achieving low values of base resistance and base– collector capacitance. In our SiGe technology the SiGe base layer is integrated by SEG, which has also allowed the formation of a self-aligned base–collector structure [9–14]. Similar to the other most advanced high-frequency SiGe HBT technologies [1–7], the SiGe base contains a certain amount of carbon for realizing very thin and highly boron-doped base layers with steep doping profile gradients [16, 17]. Another feature of the SiGe technology is the heavily arsenic-doped monocrystalline emitter

FIGURE 3.8.1 TEM cross section of a fabricated transistor.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Infineon

3.8-309

contact [7, 18, 19], which, as compared with conventional polysilicon emitters, reduces the emitter resistance of laterally downscaled transistors considerably. Finally, since in high-frequency SiGe bipolar technologies the SiGe HBTs are operating at high current densities, we use a copper metallization system. In comparison with a conventional aluminum metallization, the copper metallization has the advantage of a significantly improved electromigration hardness and lifetime at high current densities. In the copper metallization, consisting of four metallization layers, also a high-precision TaN resistor, and an MIM capacitor have been integrated [20].

3.8.3 Transistor Fabrication Process After having described the basic process concept, the transistor fabrication sequence is given in this section. The main emitter–base fabrication steps are outlined in Figure 3.8.2. After the fabrication of the deep trench/shallow trench transistor isolation a CVD-oxide layer is deposited. Then the pþ-polysilicon base electrodes, a CVD-oxide layer, and a nitride layer are deposited. The stack made of these three layers is patterned by reactive ion etching (RIE) for forming the emitter window (Figure 3.8.2a). Then a nitride/oxide stack consisting of a 20-nm thick nitride and a 50-nm thick oxide layer is deposited and spacers — made of the material of the nitride/oxide stack — are formed inside the emitter window by RIE (Figure 3.8.2b). Outside the emitter window the nitride/oxide stack is protected during this RIE by resist. Now a phosphorus implantation into the emitter window is done for forming the selectively implanted collector. The collector implantation is automatically self-aligned to the active transistor region and therefore advantageous for realizing low base–collector capacitance. Moreover, since the spacers inside the emitter window significantly reduce the implantation area for collector implantation a reduction of base–collector capacitance of about 20% is observed as compared to a collector implantation through the whole emitter window [6]. Since the collector implantation is performed before SiGe base deposition any broadening of the boron impurity profile in the SiGe base layer due to implantation damage-induced point defects is avoided in this transistor concept. This is different from the transistor concepts using NSEG for base integration. In these transistors, a collector implantation, which is selfaligned to the active transistor region, can be only performed after the SiGe base deposition process. After collector implantation the CVD-oxide layer, which is covering the collector region, is removed by a wet etch in the active transistor region. The wet etch is performed until self-aligned adjusted pþpolysilicon overhangs of about 100 nm over the CVD-oxide layer beneath have been formed (Figure 3.8.2c). During this wet oxide etch, the nitride layer of the nitride/oxide stack serves to protect the isolation regions. Now the SiGe base layer is integrated by SEG. The deposition is performed in a radiation-heated single wafer reactor using a gas mixture of H2, SiH2Cl2, HCl, GeH4, B2H6, and SiH3CH3. The HCl is used for ensuring the selective growth conditions whereas the SiH3CH3 is added to achieve the incorporation of substitutional carbon in the SiGe base [16, 17] during SEG. The growth parameters of the SiGe base deposition process and their optimization for avoiding loading effects and for improving manufacturability are described in detail in Ref. [21]. Under these selective deposition conditions no growth takes place on the transistor and isolation regions which are covered by the nitride layers (Figure 3.8.2c). Monocrystalline growth of the SiGe base occurs only at the opened collector regions and polysilicon growth only at the overhanging parts of the extrinsic base polysilicon electrodes. During the selective base deposition process the intrinsic SiGe base layer, which is growing bottom up on the collector, is connected with the polycrystalline base link region, which is growing top down from the base electrodes. After base deposition the thin nitride spacers and the sacrificial nitride layers on top of the structure are removed in phosphoric acid (Figure 3.8.2d). Then the oxide spacers which serve for the self-aligned separation of the heavily doped emitter layer from the heavily borondoped extrinsic base regions are formed inside the emitter window. Now the heavily arsenic-doped emitter layer is deposited by NSEG in a radiation-heated CVD reactor. After the in situ removal of the native oxide layer on the silicon substrate by a bake in H2 atmosphere,

© 2006 by Taylor & Francis Group, LLC

3.8-310

The Silicon Heterostructure Handbook

CVD-Oxide

Nitride

p+-poly (a) n− CVD-Oxide Nitride/oxide stack

(b)

Nitride/oxide spacer

p+-poly n−

n

Nitride

n−

STI

p+-Poly overhang

p+-poly

p+-poly

(c) n−

n

n−

Monocrystalline SiGe base

STI

Polycrystalline base link

p+-poly

p+-poly P

(d) n

SiGe base

−

n

n+-mono

n−

STI

n+-poly

p+-poly

p+-poly

(e)

P n

−

n

n−

STI

FIGURE 3.8.2 Fabrication steps of emitter–base structure. (a) Formation of emitter window, (b) deposition of nitride/oxide stack, nitride/oxide spacer formation by RIE using a photomask, self-aligned collector implantation, (c) wet oxide etch for self-aligned formation of pþ-polysilicon overhangs, (d) SiGe base deposition by selective epitaxy, removal of nitride spacers, and sacrificial nitride layers by wet etching, and (e) formation of oxide spacers inside the emitter window, fabrication of emitter.

© 2006 by Taylor & Francis Group, LLC

3.8-311

Industry Examples at the State-of-the-Art: Infineon

this deposition is performed in the CVD reactor at a temperature of 5508C using disilane as silicon source and arsine as dopant source. Under these deposition conditions, the 1021 cm3 arsenic-doped emitter layer grows monocrystalline on the silicon area of the active transistor region and amorphous on the surrounding isolation regions with a high growth rate of about 70 nm/min. After patterning the NSEG grown nþ-emitter layer, a rapid thermal annealing (RTA) step is performed, which diffuses the emitter about 20 nm deep into the underlying silicon cap of the base. During this emitter drivein, the amorphous parts of the nþ-emitter layer become polycrystalline (Figure 3.8.2e). After the emitter drive-in, processing is completed by salicidation of the base electrodes and by forming the copper metallization.

3.8.4 Transistor Results A TEM cross section through the emitter–base configuration of the fabricated transistors is shown in Figure 3.8.3. The mask width of the emitter window is 0.3 mm and the width of the oxide spacers which are used for the self-aligned separation of the emitter from the pþ-polysilicon base electrodes is 80 nm. The resulting effective emitter width is only 0.14 mm. These small values of emitter width are effective for realizing low values of base resistance and emitter–base capacitance. The thin SiGe base layer is confined within the walls defined by the CVD-oxide layer, which lies under the pþ-polysilicon base electrodes. As already described in the fabrication process (Figure 3.8.2c) the overlay between the pþpolysilicon and the CVD-oxide layer below has been adjusted self-aligned to about 100 nm. In the final transistors this results in a self-alignment of the base/collector structure, which means that the size of the contact region between the extrinsic base electrodes and the SiGe base layer is adjusted independently on a photolithographic alignment step. This self-alignment is advantageous for realizing low values of base– collector capacitance. As seen from the micrograph in Figure 3.8.3 the heavily arsenic-doped nþ-emitter layer is monocrystalline in the active transistor region. The monocrystalline emitter has the advantage of the absence of any interfacial oxide layer between the nþ-emitter contact layer and the underlying silicon cap of the base where the active emitter is diffused in. This is different from polysilicon emitter transistors. In such transistors always a thin interfacial oxide layer is located between the nþ-polysilicon and the underlying silicon substrate, which often breaks up during the emitter drive-in [22]. The thickness of such an interfacial oxide layer is difficult to control and significantly affects the emitter resistance and base currents in polysilicon emitter transistors. The replacement of the polysilicon emitter by the monocrystalline emitter contact has therefore improved emitter resistance and manufacturability of our SiGe HBTs considerably. The emitter resistance has been measured on devices with an emitter length of 2.6 mm by using the modified open collector method described in Ref. [23]. Figure 3.8.4 compares the emitter resistances of transistors with monocrystalline and polycrystalline emitter contacts for various

CVD -oxide

p+-poly n+-mono Si

STI SiGe-base

100 nm

FIGURE 3.8.3 0.14 mm.

TEM cross section of the emitter–base complex of a transistor with effective emitter width of

© 2006 by Taylor & Francis Group, LLC

3.8-312

The Silicon Heterostructure Handbook

values of effective emitter widths. In the polysilicon emitter HBTs the thickness of the interfacial oxide layer has been kept as thin as possible. Nevertheless, for an effective emitter width of 0.18 mm the transistors with monocrystalline emitter exhibit an emitter resistance of only 2.6 V, which is more than 50% lower than the emitter resistance of the polysilicon emitter control HBTs. As can be also seen from Figure 3.8.4 this advantage of the transistors with monocrystalline emitter contact increases with decreasing emitter width and becomes most pronounced in devices with very small effective emitter width. Also, since the interfacial oxide in polysilicon emitter HBTs is a dominant 1/f noise source, it has been found in Ref. [18] that a monocrystalline emitter contact is very effective for improving 1/f noise in high-speed SiGe HBTs. The SIMS doping profile of the fabricated transistors is shown in Figure 3.8.5. By the self-aligned collector implantation which has been described in Section 3.8.3, a high collector doping level of 1 1018 cm3 has been employed for realizing high current-carrying capability of the transistors. In the SiGe base layer a maximum Ge fraction of 25% has been used. The Ge profile has been steeply graded across the base to achieve an accelerating drift field for the electrons to increase the transit frequency. In the base a boron spike with high concentration of 4 1019 cm3 has been grown to enable the low base sheet resistance of 2.8 kV/sq. At the emitter side the base is lowly doped with a concentration of 1 1018 cm3 in order to obtain a small emitter–base capacitance. For realizing high transit frequency the

Ω

n+-poly Si emitter n+-mono Si emitter

6

LE = 2.6 µm RE

4

2

0 0.1

0.2

0.3

0.4

WE (µm)

FIGURE 3.8.4 Emitter resistance RE vs. effective emitter width WE. 30 Base

Collector 25

1021 As

Ge 20 15

1019

C

10

B P 1017 0.05

0.10

0.15 Depth (mm)

FIGURE 3.8.5 SIMS doping profile of the fabricated transistors.

© 2006 by Taylor & Francis Group, LLC

0.2

5 0 0.25

Ge (%)

Concentration (cm-3)

Emitter

3.8-313

Industry Examples at the State-of-the-Art: Infineon

thickness of the boron spike must be kept as thin as possible during the processing steps and annealing cycles following SiGe base deposition for transistor fabrication. Therefore, as the incorporation of carbon on substitutional sites with typical concentrations between 1 1019 and 5 1019 cm3 reduces the diffusion of boron in Si and SiGe layers significantly [16, 17], the region around the boron spike has been carbon doped with a chemical concentration of 3 1019 cm3. From this chemical carbon concentration, about 80% was found to be substitutional by x-ray diffraction (XRD). This incorporation of substitutional carbon during SiGe base deposition has effectively reduced the broadening of the base boron dopant profile in the processing steps after SEG. In combination with low-temperature processing therefore steep boron doping profiles have been achieved, resulting in a final metallurgical base width of 27 nm. Despite the highly boron-doped and aggressively vertical-scaled SiGe base profile the transfer characteristics of the fabricated transistors are ideal. Figure 3.8.6 shows the typical transfer characteristics of transistors with an effective emitter size of 0.14 2.6 mm2. For a base–emitter voltage of 0.8 V the typical current gain is 250. Also shown in Figure 3.8.6 is the typical transfer characteristic of a transistor array. These transistor arrays are configured with 7000 transistors connected in parallel. The transistor arrays have an emitter area of 7000 0.18 2.6 mm2 and are used for monitoring the transistor yield. As shown in Ref. [7] the typical emitter–base yield of these transistor arrays is near 100% and the collector– emitter yield is about 80%. Figure 3.8.7 shows the common emitter output characteristics of transistors with an emitter area of 0.14 2.6 mm2. The collector–emitter breakdown voltage BVCE0, which is measured with open base is 1.7 V. The high-frequency performance of the SiGe HBTs has been evaluated using S-parameter measurements up to 30 GHz. The transit frequency fT has been extrapolated from the small signal current gain jh21j2 using transistors with an emitter area of 0.14 2.6 mm2. Figure 3.8.8 shows the dependency of transit frequency fT on the collector current IC for different base–collector voltages VBC. The transit frequency reaches its maximum of 200 GHz at VBC ¼ 0 and a collector current density of about 8 mA/mm2. The maximum oscillation frequency fmax has been extrapolated from Mason’s unilateral gain U [24] at 25 GHz with 20 dB/dec role-off. Figure 3.8.9 shows the dependency of the maximum oscillation frequency on collector current. At VBC ¼ 1 V the maximum oscillation frequency peaks at 275 GHz. Figure 3.8.10 shows the measured frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG and the unilateral gain U at the bias conditions (VBC ¼ 1 V, IC ¼ 3.5 mA) where the maximum oscillation frequency reaches its optimum. The transition from the maximum stable gain MSG to the maximum available gain occurs at a frequency higher than 30 GHz. The high values of fmax originate from the integration of the thin base layer into a self-aligned transistor

10−2

7000 transistor array

IC,IB (A)

10−4 10−6 10−8

single transistor

10−10 10−12 0

0.2

0.4

0.6 0.8 VBE (V)

1

1.2

FIGURE 3.8.6 Transfer characteristics of a transistor with AE ¼ 0.14 2.6 mm2 and a transistor array with AE ¼ 7000 0.18 2.6 mm2.

© 2006 by Taylor & Francis Group, LLC

3.8-314

The Silicon Heterostructure Handbook

4

I B = 0, 5, 10, 15, 20, 25 µA

IC (mA)

3

2

1

BVCE0 = 1.7 V 0 0

0.5

1

1.5 VCE (V)

2

2.5

3

FIGURE 3.8.7 Common emitter output characteristics of transistors with AE ¼ 0.14 2.6 mm2.

250

300

275 GHz

200 GHz

VCB = 1 V fmax (GHz)

f T (GHz)

200 VCB =1 V

150 100 50 0 0.01

200

100 VCB = 0 V VCB = 0 V 0.1 1 10 Collector current (mA)

0 0.01 100

FIGURE 3.8.8 Cut-off frequency fT vs. collector current for transistors with AE ¼ 0.14 2.6 mm2.

0.1 1 10 Collector current (mA)

100

FIGURE 3.8.9 Maximum oscillation frequency fmax vs. collector current for transistors with AE ¼ 0.14 2.6 mm2.

architecture, providing low capacitances and extrinsic series resistances. Furthermore the high fmax values could be achieved by careful optimization of the highly boron-doped base for achieving simultaneously high transit frequency and low base sheet resistance. Table 3.8.1 summarizes the most important transistor parameters. The tradeoffs between these transistor parameters have been optimized for a balanced compromise to enable high-frequency circuit applications. The high values of transit frequency have been combined with a low base resistance RB of 50 V. The open-base collector–emitter breakdown voltage BVCE0 is 1.7 V and the open-emitter collector– base breakdown voltage BVCB0 is 5.8 V. The maximum sustainable operating voltage of a SiGe HBT generally lies between BVCE0 (worst case) and BVCB0 (best case). The values for emitter–base capacitance CEB, base–collector capacitance CBC, and collector–substrate capacitance CCS in Table 3.8.1 refer to unbiased junctions and include the wiring parasitic capacitances up to the first metallization layer. Taking into account the high base and collector doping levels, which have been employed in the

© 2006 by Taylor & Francis Group, LLC

3.8-315

Industry Examples at the State-of-the-Art: Infineon

40 U

Gain (dB)

30 20

VCB = 1 V IC = 3.5 mA

MSG |h21|2

275 GHz

10 190 GHz

0 1

10 100 Frequency (GHz)

1000

FIGURE 3.8.10 Frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG, and the unilateral gain U for transistors with AE ¼ 0.14 2.6 mm2.

TABLE 3.8.1 Device Parameters of the High-Speed npn Transistor with AE ¼ 0.14 2.6 mm2 AE b RBI BVCE0 BVCB0 CEB CBC CCS RB RE fT fmax Gate delay

0.14 2.6 mm2 250 2.8 kV/sq. 1.7 V 5.8 V 6.3 fF 5.5 fF 3.7 fF 50 V 3.5 V 200 GHz 275 GHz 3.5 psec

technology for achieving high transit frequency, high current-carrying capability and low base resistance, the DPSA emitter–base configuration has provided reasonable low values for emitter–base and base–collector capacitances of 6.3 and 5.5 fF, respectively.

3.8.5.

Additional Devices

To enable high-performance circuit applications several additional devices have been added to the highfrequency npn transistor. Table 3.8.2 summarizes all devices which are available in the technology. In addition to the high-frequency npn transistors which have been described before, two other types of npn transistors are offered on the wafers. Table 3.8.3 summarizes the device parameters of the three different npn transistor types. These npn transistors have been optimized for different tradeoffs between transit frequency fT and base–collector breakdown voltage BVCB0. By using additional mask steps in the process flow, the npn transistors differ in the collector implantation doses. As compared to the high-frequency npn1 transistor, the reduction of the collector doping level in the additional npn transistors has resulted in increased base–collector breakdown voltages of 8.3 and 10.5 V, respectively. This is resulting in a transit frequency of 135 GHz for the npn2 transistor and in a transit frequency of 80 GHz for the npn3 transistor. As seen from Table 3.8.2 also three types of resistors and an MIM capacitor are available. The resistors poly R1 and poly R2 are made of the pþ-polysilicon base electrodes but with less boron doping. The two polysilicon resistors have sheet resistances of 150 and 1000 V/sq., respectively. The high-precision TaN

© 2006 by Taylor & Francis Group, LLC

3.8-316

The Silicon Heterostructure Handbook TABLE 3.8.2 Available Devices fT ¼ 200 GHz, BVCB0 ¼ 5.8 V fT ¼ 135 GHz, BVCB0 ¼ 8.3 V fT ¼ 80 GHz, BVCB0 ¼ 10.5 V 150 Ohm/sq. 1000 Ohm/sq. 20 Ohm/sq. 1.4 fF/mm2

npn1 npn2 npn3 Poly R1 Poly R2 TaN R3 MIM

TABLE 3.8.3 Device Parameters of the Three Different npn Transistor Types (AE ¼ 0.14 2.6 mm2)

fT (GHz) fmax (GHz) CBC (fF) BVCE0 (V) BVCB0 (V)

npn1

npn2

npn3

200 275 5.5 1.7 5.8

135 285 4.6 2.0 8.3

80 225 3.6 3.1 10.5

metal resistor and the MIM capacitor are described in more detail in Ref. [20]. The TaN metal resistor is placed between the first and the second copper metallization layer and has a sheet resistance of 20 V/sq. The MIM capacitor has a specific capacitance of 1.4 fF/mm2 and is integrated between the second and third metallization layer. The MIM capacitor uses a 50-nm thick Al2O3 dielectric layer, which has been deposited by atomic layer deposition.

3.8.6.

Circuit Performance

In this section we describe the ring oscillator gate delay performance. Additionally we discuss some of the circuit results which have been achieved in our SiGe bipolar technology. The ring oscillator gate delay performance is a very good figure-of-merit for the digital circuit speed of a bipolar technology since it accounts for the effects of all transistor parameters and local wiring parasitic elements on the performance of a gate. The gate delay of our SiGe technology has been evaluated by ring oscillators using the power-saving current-mode logic (CML) circuit principle. The CML ring oscillators operate with 2.2 V supply voltage and a differential voltage swing of 400 mV. The dependency of the gate delay time on switching current is shown in Figure 3.8.11 for a position in the center of a wafer. A minimum gate

Gate delay (psec)

30

20

10

0 0.1

td = 3.5 ps

1 Igate (mA)

10

FIGURE 3.8.11 CML ring oscillator gate delay vs. current per gate Igate (AE ¼ 0.14 2.6 mm2).

© 2006 by Taylor & Francis Group, LLC

3.8-317

Industry Examples at the State-of-the-Art: Infineon

delay time of 3.5 psec is achieved at a switching current density of 8 mA/mm2. This state-of-the-art result demonstrates the well-balanced compromise between the important device parameters in Table 3.8.1. Figure 3.8.12 shows the distribution of the minimum gate delay time over a wafer. The mean value is 3.63 psec at a standard deviation of only 1.5%. Figure 3.8.13 shows the trend of the minimum gate delay in the wafer center over a lot of 15 wafers. The minimum and maximum values over the lot are 3.49 and 3.59 psec, respectively. These results demonstrate that the technology has the performance, homogeneity, and reproducibility needed for advanced high-quality circuit fabrication. To give an impression of application fields which seem to become feasible with high-speed SiGe technologies, we now briefly summarize the results of some high-frequency circuits, which have been fabricated in our technology. The frequency divider results are shown in Table 3.8.4. The dynamic frequency divider uses the principle of regenerative frequency division and has a divide ratio of 2. The circuit operates with a total supply current of 62 mA up to 110 GHz [25]. The static frequency divider has a divide ratio of 32 and operates up to 86 GHz [25]. This divider is based on the E2CL circuit principle and uses no pretracking technique [26] for further enhancement of operating frequency. Such frequency dividers are key circuit elements in a wide variety of application fields as for example in optical communications and measurement equipment.

[psec]

3.67

3.68

3.75

3.67

3.65

3.62

3.66

3.69

3.67

3.65

3.61

3.54

3.60

3.66

3.71

3.69

3.65

3.58

3.50

3.55

3.63

3.67

3.65

3.59

3.54

3.58

3.65

3.68

3.66

3.60

3.60

3.63

3.62

3.58

3.57

FIGURE 3.8.12 Wafer map of the ring oscillator gate delay at a switching current density jC ¼ 8 mA/mm2 (AE ¼ 0.14 2.6 mm2).

4.0 3.8 Gate 3.6 delay (psec) 3.4 3.2 3.0 0

5

10

15

Wafer

FIGURE 3.8.13 Minimum gate delay over a lot of 15 wafers (AE ¼ 0.14 2.6 mm2, jC ¼ 8 mA/mm2).

© 2006 by Taylor & Francis Group, LLC

3.8-318

The Silicon Heterostructure Handbook TABLE 3.8.4

Frequency Divider Data

Divide ratio Frequency range Supply voltage Supply current

Static Frequency Divider

Dynamic Frequency Divider

32 86.2 GHz 5.0 V 180 mA

2 35–110 GHz 5.0 V 62 mA

Source : From H Knapp et al. 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology. International Microwave Symposium, 2003, pp. 1067–1070. With permission.

TABLE 3.8.5 Data of Lumped-Element Broadband Amplifier

Frequency range Gain Noise Total Output power Supply voltage Supply current

Broadband Amplifier

VCO with Integrated Buffer

3 dB-bandwidth: 62 GHz 16 dB — — 5.0 V 155 mA

74–80.5 GHz — Phase noise (1 MHz offset): <–95 dBc/Hz >18 dB m 5.5 V 218 mA

Active Mixer 72.3–82.5 GHz >24 dB SSB noise figure: <14 dB — 5.0 V 60 mA

(From W Perndl et al. A 60 GHz broadband amplifier in SiGe bipolar technology. Proceedings BCTM, 293–296, 2004.) VCO with Integrated Output Buffer (From H Li et al. Fully integrated SiGe VCOs with powerful output buffer for 77 GHz automotive radar systems and applications around 100 GHz. Journal of Solid-State Circuits, 263–266, 2004.) and Active Mixer (From W Perndl et al. A low-noise and high-gain double balanced mixer for 77 GHz automotive radar front-end in SiGe bipolar technology. Radio Frequency Integrated Circuits (RFIC) Symposium, 47–50, 2004. With permission.)

The results of a monolithic integrated broadband amplifier [27] are summarized in Table 3.8.5. The broadband amplifier is based on lumped elements and is designed for differential input and output signals. The amplifier has a differential gain of 16 dB, a 3-dB bandwidth of 62 GHz and consumes 155 mA at a supply voltage of 5 V. The clear output eye diagram at a data rate of 80 Gbit/s [27] demonstrates the feasibility of the circuit for optical communications at 80 Gbit/s. To investigate the suitability of high-speed SiGe technologies for automotive radar applications at 77 GHz, we have also fabricated first key building blocks like VCOs and mixers. The results of these circuits are also summarized in Table 3.8.5. The 77-GHz VCO [28] including the resonant circuit and the output buffer has been fully integrated on a single chip (1 mm2). The output buffer has two outputs and has been designed for achieving high output power, which is required in 77-GHz automotive radar applications. The VCO is operating in the frequency range between 74 and 80.5 GHz with a phase noise of 95 dBc/Hz at 1 MHz offset. The total signal power of both buffer outputs is as high as 18 dB m and the total power consumption of the circuit is 1.2 W. The active mixer [29] for down-conversion in Table 3.8.5 consists of a mixer core based on the Gilbert cell and an on-chip balun at the RF input in order to provide a single-ended input. In the frequency range of 72 to 82 GHz the mixer has a gain of more than 24 dB and a single-sideband (SSB) noise less than 14 dB. These results show that demanding application fields like 77-GHz automotive radar which seemed to be reserved for III–V semiconductor technologies in the past, are now feasible in high-speed SiGe bipolar technologies in a highly integrated manner.

References 1. B Jagannathan, M Khater, F Pagette, JS Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, SJ Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, S Subbanna, Self-aligned SiGe npn transistors with 285 GHz fmax and 207 GHz fT in a manufacturable technology. IEEE Electronic Device Letters, 24: 324–326, 2003.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Infineon

3.8-319

2. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, S Subbanna, SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest: 121–124, 2002. 3. T Tominari, S Wada, K Tokunaga, K Koyu, M Kubo, T Udo, M Seto, K Ohhata, H Hosoe, Y Kiyota, K Washio, T Hashimoto, Study on extremely thin base SiGe HBTs featuring sub 5 ps ECL gate delay, Proceedings BCTM: 107–110, 2003. 4. T Hashimoto, Y Nonaka, T Tominari, H Fujiwara, K Tokunaga, M Arai, S Wada, T Udo, M Seto, M Miura, H Shimamoto, K Washio, H Tomioka, Direction to improve SiGe BICMOS technology featuring 200 GHz SiGe HBT and 80nm gate CMOS. IEDM Technical Digest: 129–132, 2003. 5. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Hoppner, D Knoll, K Kopke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, HE Wulf, Y Yamamoto, SiGe:C BiCMOS technology with 3.6 ps gate delay. IEDM Technical Digest: 121–124, 2003. 6. TF Meister, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, A Mitchell, T Bo¨ttner, J Bo¨ck, SiGe bipolar technology with 3.9 ps gate delay. Proceedings BCTM: 103– 106, 2003. 7. J Bo¨ck, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, W Perndl, T Bottner, TF Meister, SiGe bipolar technology for automotive radar applications. Proceedings BCTM: 84–87, 2004. 8. JN Burghartz, BJ Ginsberg, SR Mader, TC Chen, DL Harame, Selective epitaxy base transistor (SEBT), Electron Device Letters, IEEE, 9: 259–261, 1988. 9. F Sato, H Takemura, T Tashiro, H Hirayama, M Hiroi, K Koyama, M Nakamae, A self-aligned selective MBE technology for high-performance bipolar transistors. IEDM Technical Digest: 607– 610, 1990. 10. TF Meister, R Stengl, HW Meul, R Weyl, P Packan, A Felder, H Klose, R Schreiter, J Popp, HM Rein, L Treitinger, Sub-20 ps silicon bipolar technology using selective epitaxial growth, IEDM Technical Digest: 401–404, 1992. 11. F Sato, T Hashimoto, T Tatsumi, H Kitahata, T Tashiro, Sub-20 ps ECL circuits with 50 GHz fmax self-aligned HBTs. IEDM Technical Digest: 397–400, 1992. 12. TF Meister, H Scha¨fer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, H Stolz, S Boguth, J Bo¨ck, SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. IEDM Technical Digest: 739–742, 1995. 13. A Pruijmboom, D Terpstra, CE Timmering, WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, JJEW Hageraats, Selective epitaxial base technology with 14 ps ECL gate delay for low power wide-band communication systems. IEDM Technical Digest: 747–750, 1995. 14. K Washio E Ohue, K Oda, M Tanabe, H Shimamoto, T Onai, A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3 ps ECL-gate delay, IEDM Technical Digest: 795–798, 1997. 15. W Klein, BUH Klepser, 75 GHz Bipolar production technology for the 21st century, Proceedings of the ESSDERC: 88–94, 1999. 16. LD Lanzerotti, JC Sturm, E Stach, R Hull, T Buyuklimanli, C Magee, Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation, Technical Digest IEDM: 249–252, 1996. 17. HJ Osten B Heinemann, D Knoll, G Lippert, H Ru¨cker, Effects of carbon on boron diffusion in SiGe: principles and impact on bipolar devices. Journal of Vacuum Science and Technology B, 16: 1750–1753, 1998. 18. S Jouan, R Planche, H Baudry, P Ribot, JA Chroboczek, D Dutartre, D Gloria, M Laurens, P Llinares, M Marty, A Monroy, C Morin, R Pantel, A Perrotin, J de Pontcharro, JL Regolini, G Vincent, A Chantre, A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices, 46: 1525–1529, 1999. 19. A Joseph, P Geiss, X Liu, J Johnson, K Schonenberg, A Chakravarti, D Ahlgren, J Dunn, Emitter resistance improvement in high-performance SiGe HBTs. Program of ISTDM, in Nagoya, Japan: 53– 54, 2003.

© 2006 by Taylor & Francis Group, LLC

3.8-320

The Silicon Heterostructure Handbook

20. M Schwerd, M Seck, T Huttner, T Bo¨ttner, S Drexl, B Hasler, A Mitchell, H Helneder, H Ko¨rner, V Kubrak, M Schrenk, R Lachner; A manufacturable 0.35 mm 150 GHz fT SiGe:C bipolar RF technology. Proceedings Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: 10– 13, 2003. 21. H Scha¨fer, J Bo¨ck, R Stengl, H Knapp, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, TF Meister, Selective epitaxial growth of SiGe:C for high-speed HBTs. Applied Surface Science, 224: 18– 23, 2004. 22. H Schaber, TF Meister, Technology and physics of polysilicon emitters, Proceedings BCTM: 75–81, 1989. 23. R Gabl; M Reisch, Emitter series resistance from open-collector measurements – influence of the collector region and the parasitic pnp transistor, IEEE Transactions on Electron Devices, 45: 2457– 2465, 1998. 24. JD Cressler and G Niu. Silicon germanium heterojunction bipolar transistors. Artech House, Inc: 162–164, 2003. 25. H Knapp, M Wurzer, TF Meister, K Aufinger, J Bo¨ck, S Boguth, H Scha¨fer, 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology. International Microwave Symposium: 1067–1070, 2003. 26. K Washio, R Hayami, E Ohue, K Oda, M Tanabe, H Shimamoto, M Kondo, 67 GHz static frequency divider using 0:2 mm self-aligned SiGe HBTs. IEEE Radio Frequency Integrated Circuits Symposium: 31–34, 2000. 27. W Perndl; W Wilhelm, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bock, W Simburger, AL Scholtz, A 60 GHz broadband amplifier in SiGe bipolar technology. Proceedings BCTM: 293–296, 2004. 28. H Li, HM Rein, T Suttorp, J Bock, Fully integrated SiGe VCOs with powerful output buffer for 77 GHz automotive radar systems and applications around 100 GHz. Journal of Solid-State Circuits, 39(10): 263–266, 2004. 29. W Perndl, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bo¨ck, W Simbu¨rger, AL Scholtz, A lownoise and high-gain double balanced mixer for 77 GHz automotive radar front-end in SiGe bipolar technology. Radio Frequency Integrated Circuits (RFIC) Symposium: 47–50, 2004.

© 2006 by Taylor & Francis Group, LLC

3.9 Industry Examples at the State-of-the-Art: IHP 3.9.1 3.9.2 3.9.3

Introduction............................................................... 3.9-321 History of IHP’s SiGe and SiGe:C HBT Technologies............................................................... 3.9-322 High-Performance SiGe:C BiCMOS Processes ....... 3.9-323 85 GHz SiGe:C BiCMOS (SGC25A) . 120 GHz SiGe:C BiCMOS (SGC25B) [11, 12] . 200 GHz SiGe:C BiCMOS (SGC25C) [13, 14]

3.9.4 3.9.5 3.9.6

Dieter Knoll IHP

High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology ......................................... 3.9-329 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) ..................... 3.9-332 Circuit Applications of IHP’s SiGe:C Technologies............................................................... 3.9-334 60 GHz Transceiver Circuits . Automotive Radar

3.9.7

Summary .................................................................... 3.9-339

3.9.1 Introduction IHP is an R&D institute mainly financed by the German federal and the Brandenburg state governments. The purpose of IHP’s R&D activities is to create innovative solutions for wireless and broadband communication systems by close cooperative work of competent teams working in the fields of material research, process technology, circuit design, and systems. Cooperation in all these fields with partners from industry, universities, or other R&D institutes is also a common practice. The institute currently operates a 1000 m2 class-1 cleanroom, equipped with a tool set capable for 8-inch Si wafer processing and sub-0.25 mm feature size. In this chapter, we will describe IHP’s modular SiGe:C RF BiCMOS technologies which have been developed to enable the realization of integrated mixed-signal systems-on-a-chip (SoC). These BiCMOS technologies provide several types of SiGe:C HBTs with parameters or features tailored to specific applications, combined with a 0.25 mm CMOS core and a variety of passive elements. We will primarily focus on the fabrication and parameters of the SiGe:C HBT modules, but also give an overview of the further BiCMOS devices. In Section 3.9.2, the history of IHP’s SiGe and SiGe:C HBT technologies is briefly summarized. The following sections (Sections 3.9.3 to 3.9.6) provide a detailed description of the SiGe:C BiCMOS processes presently available at IHP. These processes reflect two different approaches of HBT module development. The first one aims at highest HBT performance for applications such as optical fiber communications with transmission speeds of higher than 40 Gb/sec, very high data rate wireless links in the 60 GHz ISM band, or automotive radar at 77 GHz and beyond. The high-performance HBT modules developed for these applications are described in Section 3.9.3. They offer peak fT and fmax values of up to 3.9-321 © 2006 by Taylor & Francis Group, LLC

3.9-322

The Silicon Heterostructure Handbook

200 and 245 GHz, respectively, and ring oscillator delay times down to 3.6 ps, the lowest value obtained so far in a BiCMOS process. Section 3.9.4 deals with a promising process extension, the common integration of high-speed npn and pnp SiGe:C HBTs in a complementary BiCMOS process. The pnp transistors described show cutoff frequencies which are by a factor of 2 higher than ever-published for a Si-based pnp device. The second approach of IHP’s BiCMOS development aims at cost-sensitive applications, which, however, do not need highest HBT performance. A process, which particularly fulfills the low-cost requirement, is described in Section 3.9.5. In this process, only one mask step is added to the underlying RF CMOS flow to fabricate simultaneously three types of SiGe:C HBTs with BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. Finally, Section 3.9.6 deals with fabricated circuits. Both in-house designers but also many partners and customers from other institutes, companies, or universities made use of industry-standard design kits and took benefit from prototyping and shuttle services offered by IHP for its SiGe:C BiCMOS processes. Here, we focus on some recent results obtained with IHP’s high-performance HBT modules.

3.9.2 History of IHP’s SiGe and SiGe:C HBT Technologies IHP’s activities in the field of SiGe-based device technology began more than 10 years ago with the fabrication of simple double-mesa HBTs with SiGe base layers deposited by MBE or APCVD. These transistors were primarily used to study the particular device properties of HBTs and to learn how these properties can be affected. In the following time, the HBT fabrication process has been continuously improved, also including a change in the SiGe layer deposition process from MBE and APCVD to RTCVD [1]. IHP’s most advanced SiGe HBT technology was a 14-mask RF bipolar process offering three levels of Al and a suite of passive elements [2]. The SiGe HBTs fabricated in this process showed, at 2.7 V BVCEO, peak fT and fmax values of 45 and 60 GHz, respectively, i.e., an RF performance similar to that of IBM’s first generation of SiGe BiCMOS devices [3]. This performance, however, was reached with a much simpler HBT technology that did neither use an epitaxially buried subcollector (EBC), nor deep trench isolation (DTI), nor a self-aligned emitter–base structure. Instead, IHP’s SiGe transistors were fabricated as single-polysilicon transistors with collector wells produced by high-energy P implantation following LOCOS formation. The good RF performance of these devices resulted primarily from a special device construction featuring a minimized spacing between collector contact and internal transistor regions (Figure 3.9.1a). This construction allowed one to reach the low collector resistances necessary for high RF performance, despite the high sheet resistivity of the implanted wells. Moreover, the HBTs took benefit from a progressive SiGe layer structure featuring a half-graded, less than 30-nm

(b)

Salicided collector link

Field oxide Ch. stop

Extr. base implant

SiGe

20

(a)

Polysilicon emitter

Collector well

p-Substrate

[Ge] (%)

Pt silicide

16 12 8 4 0 60 80 100 Depth (nm)

FIGURE 3.9.1 HBT construction (a) and Ge profile (b) (extracted from x-ray measurement), as used in IHP’s first SiGe HBT technology. (From D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Low cost, 50 GHz fmax Si/SiGe heterojunction bipolar transistor technology with epi-free collector wells. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-323

thick Ge profile (Figure 3.9.1b). The Ge profiles used in newer IHP technologies, including the current, most advanced ones, exhibit only minor differences compared to this profile. The primary reason for choosing a relatively simple HBT technology was the aimed modular HBT integration in a state-of-the-art CMOS platform. That seemed to be, at this time, the best way to bring HBTs in the mainstream because allowing the combination of the high RF performance of HBTs with the VLSI capability of digital CMOS. For such a modular HBT integration, we considered single-polysilicon transistors with implanted, epi-free collectors as the most attractive candidates because they can be simply integrated, without altering the CMOS process or process flow, or disturbing the CMOS device characteristics. In the middle of the 1990s, IHP’s material research group began to investigate the properties of C-doped Si and SiGe layers. After learning that even the incorporation of relative low concentrations of C (typically 51019 to 11020 cm3) can significantly suppress B diffusion in these layers, technology development was focused more and more on HBTs with C-doped SiGe layers, leading to some pioneer results in this field: In 1997, the first SiGe:C transistors with competitive DC and RF parameters were presented [4, 5]. These transistors used MBE-grown SiGe:C base layers. After transferring C-doped Si and SiGe epi-layer deposition to an RTCVD tool, it was shown in detail that C incorporation has no negative effect on ‘impurity-sensitive’ device properties such as leakage currents and yield, low-frequency noise, or base recombination [6, 7]. In 1999, the first SiGe:C BiCMOS process was also presented by IHP [8]. The new SiGe:C HBTs resembled IHP’s C-free SiGe transistors in many features, such as the implanted wells, the LOCOS-based device isolation, the special collector construction, and the singlepolysilicon structure. Besides the C incorporation, they differed from the C-free HBTs primarily in the much higher base B doping, lowering the internal base sheet resistance (RSBi) by more than a factor of 2. Moreover, the low-doped collector (LDC) and emitter (LDE) regions of the SiGe:C HBTs were selectively doped after depositing the SiGe base and a Si cap layer by implantations directly through the emitter window. The SiGe:C devices in IHP’s first BiCMOS process showed peak fT and fmax values of 55 and 90 GHz, respectively, with 3.3 V BVCEO [8], i.e., both the (BVCEO fT) product and fmax increased by about 50%, in comparison to the C-free transistors presented in Ref. [2]. Clearly, the SiGe:C HBTs took benefit from the C incorporation which effectively suppresses B out-diffusion from a highly doped SiGe layer even under the strong TED impact of the high-dose implant used for doping the external base regions, and the low-dose implants applied for selectively doping the LDE and LDC regions [4, 9]. The reduced B diffusivity in Si:C and SiGe:C layers proved also to be advantageous with respect to a modular BiCMOS process integration. In IHP’s first SiGe:C BiCMOS process, the HBT module was inserted in the CMOS process flow before implantation of the PMOS S/D regions. In this way, the base epitaxy, which needs a high temperature H2-prebake, was prevented from influencing the PMOS parameters. However, the underlying CMOS process did not use a separately implanted drain extension for the PMOS, and a strong RTA had to be applied to drive in the PMOS S/D implant. This anneal was about 708C higher than the RTA of the pure SiGe:C bipolar process [6]. Nevertheless, it could be applied in the BiCMOS flow without degrading the HBT DC and RF characteristics.

3.9.3 High-Performance SiGe:C BiCMOS Processes 85 GHz SiGe:C BiCMOS (SGC25A) In 2000, a 0.25-mm digital CMOS process of an industrial partner was licensed and transferred to IHP’s new cleanroom, which had been completed and equipped some months before. This CMOS process was used as platform for the development of IHP’s second SiGe:C BiCMOS generation. In September 2001, the development was completed with an industry-standard qualification. The new process, called SGC25A, has been running since then as IHP’s BiCMOS ‘work-horse.’ It uses 25 mask steps to fabricate two types of SiGe:C HBTs, in combination with a triple-well, 2.5 V CMOS core. Among the passives are a varactor, polysilicon resistors, and an MIM capacitor. four layers of Al are available, including a 2 mm thick top layer. Table 3.9.1 summarizes the device menu offered by the SGC25A process. Figure 3.9.2

© 2006 by Taylor & Francis Group, LLC

3.9-324

The Silicon Heterostructure Handbook

TABLE 3.9.1 SGC25A HBT Parameters and MOS and Passives Parameters of the SGC Process Family Device

Parameter

Value

Unit

Remark

2

SGC25A HBT Parameters (AE ¼ 0.42 0.84 mm ) Current gain BVEBO

150 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

HBT1

Peak fT / fmax BVCEO BVCBO

60 / 90 3.2 >8

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBT2

Peak fT / fmax BVCEO BVCBO

85 / 100 2.5 >5

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBTs 1 and 2

MOS and Passives Parameters of IHP’s SGC Process Family NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

540 0.4 0.60 0.24

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

230 0.5 0.56 0.245

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

MOS Varactor

Tuning ratio Q factor (@ low/high C)

1:3.4 120/30

Salicide Resistor

Sheet resistance Temperature coefficient

6.6 2900

Vsq ppm/8C

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient

95 450

Vsq ppm/8C

Gate poly (nþ)

Poly-Si Resistor

Sheet resistance Temperature coefficient

350 50

Vsq ppm/8C

HBT base poly

MIM Capacitor

Unit capacitance Voltage coefficient Voltage coefficient Temperature coefficient Breakdown voltage Max. application voltage

1 14 1.6 <10 >30 10

fF/mm2 ppm/V ppm/V2 ppm/8C V V

Quality factors (examples)

4 16

Predefined Inductors

2.5 V
10 V
a

Extrapolation from the IC/AE ¼ (0.3–0.75)mA/mm2 part of the VCE(IC) characteristics.

shows the flow and essential features of the process. The HBT module is integrated after structuring the MOS gates and forming the gate spacers, i.e., in a similar way as described in Refs. [8, 10]. It adds four mask steps (M8–M11) to the underlying RF CMOS baseline and produces a first HBT type featuring 3.2 V BVCEO, and peak fT and fmax values of 60 and 90 GHz, respectively. A fifth additional mask (M4) is used to provide the second HBT type, which combines 2.5 V BVCEO with 85 GHz peak fT and 100 GHz peak fmax. Cross sections of both HBT types are shown in Figure 3.9.3. Note that the SGC25A-HBTs are also fabricated, as IHP’s former devices, with epi-free, implanted wells, and a nonself-aligned emitter– base structure. However, shallow trench isolation was introduced, and higher implantation energies were available. It allowed us to replace our previously used collector construction (Figure 3.9.1a) by a more conventional, planar one. Figure 3.9.4 shows a trend chart of HBT leakage currents demonstrating the high level of SGC25A process maturity.

© 2006 by Taylor & Francis Group, LLC

3.9-325

Industry Examples at the State-of-the-Art: IHP

SGC25A PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA Opening HBT regions + High dose collector implant (M4) MOS well implantations (M5, M6), RTA Gate oxidation, Gate poly deposition Gate etch (M7), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

• • • •

25 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide

HBT MODULES (M4), (M8) − (M11) Deposition of CMOS protection layers (M8): Opening active collector regions + Medium dose collector implant + RTA Non-selective Si/ SiGe:C/ Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch • • • • •

Co salicide Local interconnect (LI) CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

FIGURE 3.9.2 Flow and features of the SGC25A process.

Poly SiGe:C/Si

STI

Polysilicon emitter

HBT1 (a)

SIC SiGe:C

Coll. Well (M8)

Deep n-well (M3)

CMOS protection layer

n+ S/D n-Well

HBT2 (b)

SIC Extr. base Coll. Well (M8)

n+ S/D

High dose collector implant (M4)

FIGURE 3.9.3 Schematic cross sections of the SGC25A HBTs. HBT1 shows 3.2 V BVCEO and 60 GHz fT, while HBT2 combines 2.5 V BVCEO with 85 GHz fT.

The processes SGC25B and SGC25C, described below, are derivatives from SGC25A. They offer a strongly improved HBT performance, while RF CMOS baseline including BEOL, and hence CMOS libraries and passive elements are identical to SGC25A.

120 GHz SiGe:C BiCMOS (SGC25B) [11, 12] SGC25B uses the same HBT integration scheme (Figure 3.9.2) and the same basic HBT construction as SGC25A (Figure 3.9.3b). To get a higher HBT performance than offered by SGC25A, the conditions for the high-dose collector implantation were optimized and the SIC implantation dose was increased.

© 2006 by Taylor & Francis Group, LLC

3.9-326

The Silicon Heterostructure Handbook

AE = 4096⫻(0.42⫻0.84) µm2 log (Ic(A))

−4 −6

IC @VBE = 0.1 V; VCB=1 V

−8

Good device: log IC < −11 Total yield: 92.2%

−10 −12 0

FIGURE 3.9.4

2000

4000 6000 Measuring point

8000

SGC25A trend chart of leakage currents for 4k HBT arrays. 980 wafers from 97 lots were measured.

TABLE 3.9.2

SGC25B HBT Parameters

Parameter

Value

Unit

Remark

SGC25B HBT Parameters (AE ¼ 0.420.84 mm2) Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance a

150 120 140 5.9 >2.5 2.3 >4 >40 6.8 4.5 5.6 23 51 150

GHz GHz ps V V V V fF fF fF V V V

@ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VBE ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2) V.

b

Moreover, we reduced some transistor dimensions, such as the active enclosure of the emitter, the overlap of the polysilicon emitter to the emitter window, and the LDE width. Note that the changed SIC conditions are responsible that only one transistor type is available in SGC25B. The parameters of this HBT type are listed in Table 3.9.2, featuring 120 GHz peak fT, 140 GHz peak fmax, and a CML ring oscillator delay time of 5.9 psec.

200 GHz SiGe:C BiCMOS (SGC25C) [13, 14] SGC25C is IHP’s first BiCMOS process which offers bipolar transistors with 200 GHz cutoff frequencies to the design community. Two HBT variants were tested which differ in the emitter–base structure, as shown in Figure 3.9.5. Figure 3.9.6 illustrates both the full SGB25C process flow and the detailed flows for the different HBT modules. The standard HBT variant uses the same single-polysilicon construction as applied in SGC25A/B, featuring an implanted extrinsic base layer (Figure 3.9.5a). This layer is formed on isolator regions during the nonselective epi-process applied to grow the intrinsic SiGe:C base layer and a Si cap. The implantation step for doping the extrinsic base layer is carried out self-aligned to the

© 2006 by Taylor & Francis Group, LLC

3.9-327

Industry Examples at the State-of-the-Art: IHP

(a)

Emitter

Implanted extrinsic base

Collector contact

STI

Heavily doped collector

Emitter

Elevated extrinsic base

STI

(b) Collector contact

STI

Heavily doped collector

STI

FIGURE 3.9.5 Schematic cross sections of the SGC25C standard HBT with implanted extrinsic base (a) and an HBT with elevated extrinsic base (b). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

SGC25C PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA MOS well implantations (M4, M5), RTA Gate oxidation, Gate poly deposition Gate etch (M6), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

ELEVATED EXTRINSIC BASE FORMATION

HBT MODULE (M7) - (M11) Deposition of CMOS protection layers (M7): Opening HBT regions + High dose collector implant + RTA Oxide deposition (M8): Opening active collector regions Si / SiGe:C / Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch

Selective Si epitaxy followed by non-selective HBT base + LDE epitaxy

Sacrificial layer deposition (M9): Opening emitter windows + SIC Forming inside spacers Forming outside spacers + Wet etch sacrificial layer + Selective growth of the B-doped extrinsic base

As doped emitter deposition (M10): Structuring polysilicon emitters (M11): External base structuring Removing protection layers by wet etch

FIGURE 3.9.6 Flow of the SGC25C process with standard HBT module (implanted extrinsic base). The process flow for HBTs with elevated extrinsic base is shown below.

© 2006 by Taylor & Francis Group, LLC

3.9-328

The Silicon Heterostructure Handbook

outer edge of the polysilicon emitter, but not self-aligned to the emitter window. In contrast, the second process variant fabricates transistors with a self-alignment between extrinsic base and emitter window to minimize base resistance (Figure 3.9.5b). This self-alignment is achieved by selectively growing a highly B-doped, elevated extrinsic base layer after structuring the polysilicon emitter. Sacrificial and protection layer depositions as well as spacer processes are applied before, to make possible that this layer growth also occurs in the space between polysilicon emitter and that extrinsic base layer grown already during the nonselective epi-process for base and Si cap formation. Both SGC25C transistor variants reach 200 GHz fT, whereas the HBTs with elevated extrinsic base show fmax values of up to 245 GHz, which is about 50 GHz higher than reached with the implanted version. The strong fT gain, compared to SGC25B, results primarily from a novel collector design, which substantially reduces base–collector charging and transit times. Figure 3.9.6 shows that the SGC25C process flow differs from the SGC25A/B flow in the collector well fabrication. The HBT high-dose collector implantation is now carried out after the gate module. Moreover, conditions for this implantation step were found providing simultaneously a low sheet resistance and a junction depth, which is low enough that the lateral spreading of the highly doped collector wells is confined by the STI side walls. The key new SGC25C device features are the formation of the whole HBT structure in one active area without STI stripe between emitter and collector contacts, the complete lateral enclosure of the highly doped collector wells in the STI side walls, and the self-alignment of the collector contact region to the base poly edge (Figure 3.9.5). This allows us to achieve collector resistances, which are even lower than the emitter resistance. In addition, the new design reduces device dimensions and parasitic capacitances. So, the reduced collector area results in a 50% reduction in the collector– substrate capacitance compared to the SGB25B transistors. Furthermore, since the collector well fabrication is implemented after the critical thermal treatments, this device design allows us to produce extremely steep collector doping profiles and achieves better control of the width of the base–collector space charge regions. Finally, the absence of DTI improves the heat dissipation and reduces the thermal resistance. In addition to the introduction of a new collector design we also optimized the base–collector as well as the emitter–base depletion widths by adjusting the buffer and cap thicknesses of the epi-layer stack in order to maximize fT. Figure 3.9.7 compares the fT vs. IC curves of SGC25B and SGC25C HBTs and illustrates, by a comparison of transit time components, from what the SGC25C performance gain results in detail. Table 3.9.3 summarizes the parameters of the SGC25C HBTs. The standard devices, with implanted extrinsic base, show 200 GHz fT, about 185 GHz fmax, and a minimum CML ring oscillator delay of 4.3 ps. The devices with elevated extrinsic base reach fmax values in excess of 240 GHz and a ring oscillator delay of 3.6 ps (Figure 3.9.8), which is, to our knowledge, the lowest value reached so far in a BiCMOS process.

VCE = 1.5 V

150

SGC25C

100

SGC25B

50 AE = 2⫻(0.21⫻0.84) µm2 0.01

0.1 1 Collector current (mA)

10

Transit time (psec)

Transit frequency (GHz)

1.4 200

1.2

(CBC+CBE)kT/qIC

1.0

CBC(RE+RC)

0.8 0.6 wBC /2vsat

0.4 0.2

tE+tB

0.0 SGC25B

SGC25C

FIGURE 3.9.7 Transit frequency vs. collector current for SGC25B and SGC25C HBTs, and comparison of the transit time components of these transistors.

© 2006 by Taylor & Francis Group, LLC

3.9-329

Industry Examples at the State-of-the-Art: IHP TABLE 3.9.3 SGC25C HBT Parameters

Parameter Emitter dimensions Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

Selectively Grown Elevated Extrinsic Base

Standard: Implanted Extrinsic base

Value

Value

Value

0.1750.84 300 190 243 3.6 >1.5 1.9 5.1 >40 n.m. 2.4 n.m. 22 21 75

0.210.84 300 200 225 3.9 >1.5 1.9 5.0 >40 3.8 2.8 3.0 18 16 85

a

Unit

0.210.84 300 202 186 4.3 >1.5 >1.85 4.5 >40 3.8 3.3 3.0 19 16 110

2

mm

GHz GHz ps V V V V fF fF fF V V V

Remark Drawn dimensions @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2)V.

b

7 Gate delay time (ps)

T = 300 K 6

AE = 0.21⫻0.84 µm2

5

∆V = 300 mV VEE = −2.5 V

Impl. extr. base

4 AE = 0.175⫻0.84 µm

2 Elevated extr. base

3 1

10 Current per gate (mA)

FIGURE 3.9.8 CML ring oscillator gate delay vs. current per gate for oscillators with 53 stages. Devices with elevated extrinsic base and different emitter dimensions are compared with the standard SGC25C HBTs (with implanted extrinsic base). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

3.9.4 High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology The availability of both npn- and pnp-type bipolar transistors with matched performance in a complementary BiCMOS process (CBiCMOS) is a promising route to applications simultaneously requiring low voltage, low power, and high speed. IHP has developed a high-speed CBiCMOS process with bipolar parameters summarized in Table 3.9.4 [15]. This process offers pnp SiGe:C HBTs with peak fT/fmax values of 80 GHz/120 GHz (Figure 3.9.9) at 2.6 V BVCEO and a CML ring oscillator delay of 8.9 psec

© 2006 by Taylor & Francis Group, LLC

3.9-330

The Silicon Heterostructure Handbook TABLE 3.9.4

CBiCMOS HBT Parameters (From Ref. [15].) (AE ¼ 0.21 0.84 mm2) npn

pnp

Parameter

Value

Value

Unit

Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCES Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

160 180 185 4.6 >1.5 2.0 5.0 150 4.5 3.6 3.0 19 16 123

180 80 120 8.9 >2.5 2.6 5.5 40 5.3 3.0 4.0 22 50 147

GHz GHz ps V V V V fF fF fF V V V

fT or fmax (GHz)

200 150

Remark @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA @ 10 mA @ 10 mA @ VBE ¼ 0.7 V @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

A E = 2⫻ (0.21⫻0.84) µm2

npn

VCE = 1.5 V pnp-only

100

fmax pnp

50 fT 0

10−4

10−3 Collector current (A)

10−2

FIGURE 3.9.9 Transit frequency (fT) and maximum oscillation frequency (fmax) vs. collector current for pnp and npn HBTs fabricated on the same wafer in the CBiCMOS and for pnp devices from a pnp-only BiCMOS. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

(Table 3.9.4). The simultaneously fabricated npn SiGe:C HBTs show fT/fmax values of 180 GHz/185 GHz, i.e., a performance almost as high as that of the SGC25C process, despite a changed emitter construction and the additional thermal budget within the CBiCMOS process. A pnp-only, reference BiCMOS flow even produced peak fT/fmax values for the pnp devices of 115 GHz/115 GHz (Figure 3.9.9). This pnp RF performance of CBiCMOS and pnp-only BiCMOS surpasses the best reported values of this transistor type substantially. The strong performance gain of the pnp HBTs is mainly due to a highly tuned vertical doping profile, taking full advantage of the reduced P diffusion in the C-doped base [16] combined with the special collector construction of IHP’s 200 GHz npn transistors. This construction allows one to integrate an isolated pnp into a CMOS process easily, while simultaneously minimizing collector resistance and capacitance. CBiCMOS process flow and transistor cross sections are shown in Figure 3.9.10 and Figure 3.9.11. The RF CMOS baseline is the same as used for the SGC (npn-only) process family. Up to the npn base layer epitaxy the process flow is identical to SGC25C. Then, the collector regions of the pnp transistors are

© 2006 by Taylor & Francis Group, LLC

3.9-331

Industry Examples at the State-of-the-Art: IHP

CBiCMOS PROCESS FLOW

Gate etch (M6), Spacer formation BIPOLAR (NPN+PNP) MODULE (M7)-(M16) Deposition of CMOS protection layers (M7): Opening npn regions+ High dose npn collector implant + RTA Oxide deposition (M8): Opening active npn coll. regions npn base epitaxy

NPN

PNP

(M9): Opening pnp regions + High dose pnp collector implant + n-isolation implant + RTA Oxide deposition (M10): Opening active pnp coll. regions pnp base epitaxy (M11): Structuring pnp emitter window etch stop layer + base link implant

(M12): Opening npn em. window + SIC As doped npn emitter deposition (M13): Opening pnp em. window + SIC B doped pnp emitter deposition (M14): Structuring pnp poly emitters (M15): Structuring npn emitter + pnp base poly (M16): Implantation of npn base and pnp collector contacts Removing CMOS protection layers by wet etch S/D implantations (M17, M18) ... Passivation (M30)

FIGURE 3.9.10 Flow of the complementary BiCMOS process.

Base

Emitter

Collector

Base

Emitter

Collector

npn Emitter Poly pnp Base Poly SIC

n+ S/D

High doped collector

SIC

p+

n+ S/D

High doped collector

n-Isolation

n well

FIGURE 3.9.11 Schematic cross section of the npn HBT structure (left) and the pnp HBT structure (right) of the complementary BiCMOS process. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.9-332

The Silicon Heterostructure Handbook

formed in analogy with the npn flow. In addition to the collector well implant, a high-energy implantation is applied for the vertical isolation of the pnp. The pnp epitaxy stack consists of a Si buffer layer, the P-doped SiGe:C layer (30 nm thick), delivering a pinched sheet resistance of about 10 kV/sq, and a Si cap layer. A total of ten mask steps are used for the complementary bipolar module, five for the pnp and four for the npn, and one common mask step for structuring npn emitter poly and pnp base poly. The demonstrated RF performance, the high early voltages (Table 3.9.4) and further results, such as the only weak sensitivity of b and peak fT to the collector bias [15], indicate that valence band barrier effects, a serious problem of pnp HBTs, are largely suppressed before onset of the Kirk effect by a careful profile design at the base–collector junction. A major concern with such heavily doped, rapidly annealed devices, as produced in SGC25C and CBiCMOS is the defect density. The Gummel plots of both npn and pnp 4k HBT arrays, shown in Figure 3.9.12, prove that this problem has been successfully solved for both HBT types.

3.9.5 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) The majority of current BiCMOS applications, in particular in the wireless area, have more modest speed requirements, typically below 100 GHz, but are highly cost-sensitive. Therefore, IHP has developed, in addition to the technologies with high-performance HBTs, a very simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high-volume applications. The technology, called SGB25V, is a 0.25 mm BiCMOS SiGe:C HBT process with only 19 lithographic steps, offering four levels of Al and a full menu of active and passive devices (Table 3.9.5). Three different SiGe:C HBTs can be fabricated simultaneously by adding a single lithography level to the underlying RF CMOS process. These devices offer BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. The further device menu includes 2.5 V VDD MOS transistors for digital applications, an isolated NMOS device, an accumulation type MOS varactor, a junction varactor, three polysilicon resistors with sheet resistances ranging from 6 V/sq. to 2 kV/sq., a 2-mm thick upper Al layer for high-Q inductor fabrication, and a 1 fF/mm2 MIM.

10−1

10−1

10−2 Base, collector current (A)

npn

pnp

10−2

5 arrays AE = 4096⫻ (0.21⫻0.84) µm2

10−3 10−4 10−5

10−3 10−4 10−5

10−6

10−6

10−7

10−7

10−8

VCB = 0 V

10−8

10−9

T = 300 K

10−9

10−10

−0.8

−0.6

−0.4 0.4 0.6 Base−emitter voltage (V)

10−10 0.8

FIGURE 3.9.12 Gummel plots of pnp and npn HBT arrays fabricated in the CBiCMOS flow. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.9-333

Industry Examples at the State-of-the-Art: IHP TABLE 3.9.5

SGB25V HBT, MOS, and Passives Parameters

Device

Parameter

Value

Unit

Remark

2

SGB25V HBT parameters (AE ¼ 0.5 0.9 mm ) Current gain BVEBO

190 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

npn-H

Peak fT/fmax BVCEO BVCES

30 / 70 7 >20

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-S

Peak fT/fmax BVCEO BVCES

50 / 95 4.0 16

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-P

Peak fT/fmax BVCEO BVCES

80 / 95 2.4 7.7

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-H,S,P

SGB25V MOS and Passives Parameters NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

570 3 0.61 0.22

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

290 3 0.51 0.185

mA/mm pA/mm V mm

@ VDS ¼ 2.5V

MOS Varactor

Identical to SGC processes

pþn Varactor

Tuning ratio Q factors (@ low/high C)

1.7:1 35 / 20

Salicide Resistor

Sheet resistance Temperature coefficient

6.8 2950

V/sq. ppm/K

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

310 105 0.64

V/sq ppm/K ppm/K2

Gate poly (pþ) 408C to 1258C

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

2000 2760 6.1

V/sq ppm/K ppm/K2

Low-doped gate poly

MIM Capacitor Inductors

Identical to SGC processes Identical to SGC processes

@ 5 GHz

408C to 1258C

a

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm2 part of the VCE(IC) characteristics.

The CMOS backbone of SGB25V differs from that CMOS baseline used for the SGC25 processes and for a SGB25V pre-production version [17]. The process changes allowed us to release MOS devices with lower leff, and led to a strong yield increase for dense CMOS sections, which use the shorter devices. Moreover, a set of polysilicon resistors is now available, providing a wider range of sheet resistance values compared to the SGC process family. The SGB25V process flow is shown in Figure 3.9.13. HBT fabrication starts after depositing the MOS gates and a Si3N4 protection layer. The single HBT mask is used to remove by RIE the nitride film and the gate material from the HBT regions, and to carry out a chain of P implants. After wet etching the gate oxide, the SiGe:C base and a Si LDE layer are successively grown. L-shaped inside spacers are formed, a SIC implantation is carried out, and an As-doped emitter Si layer is deposited. Then, emitter and base

© 2006 by Taylor & Francis Group, LLC

3.9-334

The Silicon Heterostructure Handbook

SGB25V PROCESS FLOW

Shallow trench etch (M1) and fill Deep n-well implantation (M2), RTA MOS well implantations (M3, M4), RTA Gate oxidation, Gate poly deposition

Gate etch (M6), Spacer formation S/D implantations (M7, M8), RTA Salblock(M9), Co salicide formation Contact (M10), Met-1 (M11) Via-1 (M12), MIM (M13), Met-2 (M14) Via-2 (M15), Met-3 (M16) Via-3 (M17), Met-4 (M18) Passivation (M19)

FIGURE 3.9.13

• • • •

19 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide HBT MODULE (M5)

Nitride layer for CMOS protection (M5): Opening active collector regions + Low dose collector implants Non-selectiveSi/ SiGe:C/ Si epitaxy Forming oxide inside spacers + SIC As doped emitter deposition CMP (Si, SiGe) with stop on nitride Removing nitride layer by wet etch • • • •

Co salicide CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

Flow and features of the SGB25V process.

material are removed by CMP from the Si3N4 layer surface to isolate the emitter from the extrinsic base. After wet etching the nitride film from the gate stack, CMOS device fabrication is continued. The gate structuring process and the PMOS S/D implants are also used to form and dope the HBT extrinsic base regions, respectively. Note that using gate-poly as material for the HBT extrinsic base is not the only advantage of the special HBT integration scheme applied here. It also minimizes the impact of the HBT thermal steps on the MOS characteristics. However, we would not have been able to take advantage of these without doping the HBTs with C. This prevents B out-diffusion from SiGe, and thus HBT parameter degradation, by CMOS thermal steps such as poly-reoxidation and S/D RTA, which are carried out after HBT integration. Figure 3.9.14 shows fT vs. collector current curves for the HBTs simultaneously fabricated in SGB25V. The differences in the fT and BVCEO values are produced by varying the layout for the deep P implant for the CMOS triple-well option, and using the PMOS well implants (Figure 3.9.15). The SGB25V HBT yield (estimated for 4k device arrays) exceeds 90%, matching the numbers obtained with our other BiCMOS processes. VLSI ability of the process is controlled with an 1M SRAM as test vehicle. To study the impact of HBT integration on the yield of this 6-million transistor device, lots were fabricated with and without HBT module. Figure 3.9.16 demonstrates a typical SRAM yield of around 70% for both cases showing that the HBT integration scheme, used for SGB25V, is modular and has no negative impact on the yield of dense CMOS sections. Moreover, it shows that SGB25V guarantees high yield for VLSI CMOS segments necessary for a cost-effective fabrication of RF-SOCs.

3.9.6 Circuit Applications of IHP’s SiGe:C Technologies IHP’s BiCMOS technologies, described in the previous sections, differ in the level of maturity. SGC25A, SGC25B, SGC25C (implanted HBT version), and SGB25V are fully developed and characterized processes which we were able to release for the access of both in-house and external designers. These processes are also offered as EUROPRACTICE platforms. In contrast, the SGC25C version with elevated extrinsic base as well as the CBiCMOS process have pre-production status. Therefore, the access to these processes is presently restricted to in-house designers and a few longtime partners. For IHP’s BiCMOS technologies design kits are available which support a Cadence mixed signal platform. For HBT characterization, the VBIC model is applied [18].

© 2006 by Taylor & Francis Group, LLC

3.9-335

Industry Examples at the State-of-the-Art: IHP

Transit frequency (GHz)

80 70

npn-P

2.4V

60

VCE = 2 V

BVCEO

50 40

4.2 V

npn-S

30 20

npn-H

AE = 10⫻(0.5⫻0.9) µm2

7V

10 0.000

0.005

0.010

0.015

0.020

Collector current (A)

FIGURE 3.9.14 Transit frequency vs. collector current for the three HBT types fabricated in the SGB25V process (npn-P, npn-S, npn-H). The different curves for the same HBT type illustrate the typical scattering across a wafer.

Polysilicon emitter

Gate polysilicon npn-H n+ S/D

SIC

STI

n-Well Coll. well (M5) Poly SiGe:C/Si

Deep n-Well (M2)

SiGe:C base npn-S n+ S/D

SIC Coll. Well

n-Well

Deep n-Well Oxide spacer npn-P SIC Coll. Well

n+ S/D n-Well

Deep n-Well

FIGURE 3.9.15 Schematic cross sections of the three HBT types fabricated in the SGB25V process.

In the following section, we present some recent exemplary circuit results obtained with IHP’s highperformance BiCMOS processes because these technologies enable new product application areas. For demonstration, a series of benchmarking circuits were designed and tested successfully. The main results are summarized in Table 3.9.6. Intended applications are very high data rate wireless links in the 60 GHz ISM band and automotive radar at 77 GHz and beyond.

60 GHz Transceiver Circuits For demonstration of new wireless transmission systems with data rates >150 Mb/sec, key circuit blocks for a 60 GHz transceiver system were designed and fabricated [20, 21]. The proposed transceiver is based

© 2006 by Taylor & Francis Group, LLC

3.9-336

The Silicon Heterostructure Handbook

SRAMs measured on 45 wafer sites

1M SRAM wafer yield (%)

100

BEC = 0 (@2.5 V) 80

60

40

A

B

C

D

E

F G

H

I

J

K

L

BiCMOS lots

CMOS 20

Lot ID (A − L)

FIGURE 3.9.16 Wafer yield of 1M SRAMs with a bit error count (BEC) of zero, fabricated in the SGB25V process (BiCMOS lots) or a flow without the SGB25V HBT module (CMOS lots).

TABLE 3.9.6 Measurement Results of Benchmarking Circuits Fabricated in IHP’s High-Performance BiCMOS Processes Circuit

Parameter

Value

Technology

Ref.

Static frequency divider, 1:2

Maximum input frequency

62 GHz

SGC25B

[19]

Dynamic frequency divider, 1:2

Maximum input frequency

72 GHz

SGC25B

[19]

Low power frequency divider, 1:64, 1 V supply

Maximum input frequency Suppply current

2.4 GHz 0.6 mA

SGC25B SGC25B

[19] [19]

60 GHz LNA

Gain @ 61 GHz

9.6 dB

SGC25C

[20]

LC oscillators

Oscillation frequency

24 GHz 60 GHz 76 GHz 97 GHz 117 GHz

SGC25B SGC25B SGC25B SGC25C SGC25C

[21–23]

Ring oscillators

Gate delay

3.6 ps

SGC25C

[14]

on amplitude shift keying (ASK) modulation principle. The reasons for the selection of this modulation technique are its simplicity, the wide bandwidth of the 61 GHz ISM band, and that there is no need for high-performance A/D converters. The transmit path of the transceiver consists of a 61.25 GHz fundamental mode oscillator, a switch, and a power amplifier. Between the modulator and the power amplifier a filter is inserted to reduce spurs. The receiver path consists of a three-stage, lownoise amplifier (LNA), a mixer, a 56 GHz oscillator, a variable gain amplifier, and an ASK demodulator. One task of the LNA design was to get unconditional stability for both on-wafer measurements and for the use of the amplifier in test board modules together with the other receiver components. Especially the use of bond wires for the connection of the ground potential (and the associated inductance) causes serious stability problems if a single-ended configuration is used. That is why all the stages are designed in differential configuration. The input and output are trafo-coupled. The transformer coupling is useful in two ways. First, it acts as a balun for connection to a singleended antenna. Second, the primary and secondary windings of the transformer are tuned to get a band pass characteristic. With this, an additional input filter in the RX path can be omitted and this function is integrated in the LNA. The single stage of the LNA is a differential stage with inductive load and with matching network at the output. The LNA was measured on wafer with a 110 GHz vector network analyzer. The maximum gain is 9.6 dB. The gain-maximum is reached at 61 GHz, which is

© 2006 by Taylor & Francis Group, LLC

3.9-337

Industry Examples at the State-of-the-Art: IHP

exactly the target frequency of the requested ISM band (Figure 3.9.17). The LNA has a band pass characteristic, resulting from the tuned transformers at input and output. With this characteristic, no additional band pass filter is required.

Automotive Radar High-frequency oscillators are key components in modern low-cost radar systems for automotive and other sensor applications. Most of today’s automotive radar systems utilize the frequency bands at 24 and 77 GHz. For future developments, also higher frequency bands at 94 and 140 GHz are of interest. Reasons for the use of higher frequency bands are the further miniaturization of the radar systems and the better beam-forming prospects due to the shorter wavelength. Several LC oscillators for the different frequency ranges were designed and tested [21–23]. The circuit diagram of the oscillators is shown in Figure 3.9.18. The circuit is a common collector Colpitts oscillator in fully differential implementation. With the symmetric circuit, two advantages are reached: first, it gives reduced signal interference via the silicon substrate and, second, the coupling of the highfrequency energy to subsequent building blocks such as integrated amplifiers or mixers is more effective. 0 0 0 The tank is a symmetric circuit of two inductors L1 and L1 and the MIM capacitors C1, C2, C1 , and C2 . In parallel to the capacitor C1 acts the base–emitter capacitor of the bipolar transistor CBE. For explanation, the tank can be divided into two half circuits separated by the symmetry line shown in Figure 3.9.18. In operation, the oscillator-halves are working in the odd mode, such that the outputs are 1808 out of phase. The nodes of the tank, indicated by the symmetry line, have virtual ground. The oscillation frequency can then be estimated to a first order by the following equation: f ¼ 1=(2p

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ L1 {2CBC þ [C2 (CBE þ C1 )=(C1 þ C2 þ CBE )]})

where CBC is the base–collector capacitance of the transistors.

Tank circuit Vctrl L1

L⬘1

C1

C1⬘

C2

Out

C2⬘

10 s21

Gain (dB)

0

Symmetry line

−10 −20 −30

VEE

s12

−40 −50 0

20

40 60 80 Frequency (GHz)

100

120

FIGURE 3.9.17 Gain curves of the 60 GHz LNA.

© 2006 by Taylor & Francis Group, LLC

FIGURE 3.9.18 Circuit diagram of the high-frequency oscillator. (From W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

3.9-338

The Silicon Heterostructure Handbook

The oscillators were characterized using an on-wafer test system with GS probes. For determination of the output spectrum a Rohde & Schwartz spectrum analyzer FSEM30 with a mixer unit FS-Z110 was used. The measurement results of three oscillators are summarized in Table 3.9.7. The supply voltage of these oscillators is 3 V or 4 V. The output power is from 7 dB m (oscillator 1) to 12 dB m per output channel (oscillator 3). The frequency of oscillation can be tuned by applying a tuning voltage at the Vctrl input. For oscillator 2, intended for 94 GHz, the tuning range is from 97.5 to 95.2 GHz for the control voltage changing from 2.4 V to 0. Because the target frequency was not met in this design, a redesign has 0 to be done. The capacitance of C2 and C2 will be reduced by a modest amount to shift the frequency to 94 GHz. Figure 3.9.19 shows the measured output spectrum of oscillator 3, which reaches the highest frequency. The tuning range is from 117.2 to 113.7 GHz. The current consumption is within the range of 10 to 28 mA. Of course, the output power will also undergo a change with varying the current flowing through the oscillator. The maximum measured output power is 12 dB m. Within the tunable frequency

TABLE 3.9.7 Measurement Results of Experimental LC Oscillators Fabricated in IHP’s High-Performance BiCMOS Processes Parameter

Oscillator 1

Oscillator 2

Oscillator 3

Oscillation frequency Supply voltage Supply current Center frequency Tuning range Output power Phase noise at 1 MHz offset Chip size

76 GHz 4.0 V 32 mA 76.1 GHz — 7 dB m 91 dBc/Hz 750400 mm2

97 GHz 3.0 V 15–37 mA 96.15 GHz 2.3 GHz 11.2 dB m 88 dBc/Hz 750400 mm2

117 GHz 3.0 V 10–28 mA 115.1 GHz 3.5 GHz 12 dB m — 750400 mm2

Ref L vl −5 dBm

Marker-12.24 dB m 114.92457381 GHz

−10 −20 −30 −40 −50 −60 −70 −80 Center 114.9312472 GHz

10 MHz/

Span 100 MHz

FIGURE 3.9.19 Spectrum of single-ended output for oscillator 3. The center frequency is 114.3 GHz. (From W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-339

range, the output power is above 20 dB m. The phase noise of oscillators 1 and 2 was measured by using a spectrum analyzer. The phase noise is 91 dB c/Hz and 88 dB c/Hz at 1 MHz offset, respectively.

3.9.7 Summary We have described IHP’s modular SiGe:C RF BiCMOS technologies which provide several types of SiGe:C HBTs, combined with a 0.25 mm CMOS core and state-of-the art passive elements. Highperformance npn HBT modules with up to 200 GHz fT, a complementary HBT module with superior pnp performance, and a low-cost HBT module, providing simultaneously three HBT types, can be fabricated in IHP’s BiCMOS processes. This process menu ideally fulfills the technological requirements for the fabrication of modern fiber and wireless communication systems.

Acknowledgments The author would like to thank all IHP colleagues contributing to the HBT and BiCMOS work through the last years. Special thanks goes to B. Heinemann, K.-E. Ehwald, H. Ru¨cker, B. Tillack, and R. Barth who had the strongest impact in the field of process technology. P. Schley, Ha. Erzgra¨ber, and R. Scholz did great jobs in device measurement and characterization. I am also grateful to F. Fuernhammer and G. Grau (Advico) for the efforts to realize an adequate design environment for IHP’s technologies, and to W. Winkler who strongly supported all technology developments by providing suitable benchmark and verification circuits. Last but not least, the author thanks J. Osten who initiated SiGe:C material research at IHP, and A. Ourmazd for excellent management support and many valuable discussions.

References 1. G Ritter, B Tillack, and D Knoll. Successful preparation of high-frequency HBT by integrated RTCVD processes. MRS Symposium Proceedings, 1995, Vol. 387, Rapid Thermal and Integrated Processing IV, pp. 341–346. 2. D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Low cost, 50 GHz fmax Si/SiGe heterojunction bipolar transistor technology with epi-free collector wells. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. 3. D L Harame, E F Crabbe, J D Cressler, J H Comfort, J Y-C Sun, S R Stiffler, E Kobeda, J N Burghartz, M M Gilbert, J C Malinowski, A J Dally, S Ratanaphanyarat, M J Saccamango, W Rausch, J Cotte, C Chu, and J M C Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 4. B Heinemann, D Knoll, G Fischer, D Kru¨ger, G Lippert, H J Osten, H Ru¨cker, W Ro¨pke, P Schley, and B Tillack. Control of steep boron profiles in Si/SiGe heterojunction bipolar transistors. Proceedings of the European Solid-State Device Research Conference, Stuttgart, 1997, pp. 544–547. 5. H J Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe heterobipolar transistor performance and process margin. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1997, pp. 803–806. 6. D Knoll, B Heinemann, H J Osten, K E Ehwald, B Tillack, P Schley, R Barth, M Matthes, K S Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 7. H J Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116. 8. K E Ehwald, D Knoll, B Heinemann, K Chang, J Kirchgessner, R Mauntel, I S Lim, J Steele, P Schley, B Tillack, A Wolff, K Blum, W Winkler, M Pierschel, U Jagdhold, R Barth, T Grabolla, H J Erzgra¨ber,

© 2006 by Taylor & Francis Group, LLC

3.9-340

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

The Silicon Heterostructure Handbook

B Hunger, and H J Osten. Modular integration of high-performance SiGe:C HBTs in a deep submicron, epi-free CMOS process. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 561–564. D Knoll, B Heinemann, K E Ehwald, G G Fischer, and B Hunger. Emitter scaling of singlepolysilicon SiGe:C HBTs with highly doped base layers. Proceedings of the European Solid-State Device Research Conference, Cork, 2000, pp. 560–563. S A St Onge, D L Harame, J S Dunn, S Subbana, D C Ahlgren, G Freeman, B Jagannathan, S J Jeng, K Schonenburg, K Stein, R Groves, D Coolbaugh, N Feilchenfeldt, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, R Johnson, A Joseph, L Lanzerotti, J Malinowski, B Orner, and M Zierak. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm leff CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. B Heinemann, D Knoll, R Barth, D Bolze, K Blum, J Drews, K E Ehwald, G G Fischer, K Ko¨pke, D Kru¨ger, R Kurps, H Ru¨cker, P Schley, W Winkler, and H E Wulf. Cost-effective high-performance high-voltage SiGe:C HBTs with 100GHz fT and BVCEO fT products exceeding 220 V GHz. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2001, pp. 348–351. D Knoll, B Heinemann, K E Ehwald, H Ru¨cker, B Tillack, W Winkler, and P Schley. BiCMOS integration of SiGe:C heterojunction bipolar transistors. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 162–166. B Heinemann, H Ru¨cker, R Barth, J Bauer, D Bolze, E Bugiel, J Drews, K E Ehwald, T Grabolla, U Haak, W Ho¨ppner, D Knoll, D Kru¨ger, B Kuck, R Kurps, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, D Wolansky, H E Wulf, Y Yamamoto, and P Zaumseil. Novel collector design for high-speed SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 775–778. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. H Ru¨cker, B Heinemann, D Bolze, D Knoll, D Kru¨ger, R Kurps, H J Osten, P Schley, B Tillack, and P Zaumseil. Dopant diffusion in C-doped Si and SiGe: Physical model and experimental verification. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 345–348. D Knoll, K E Ehwald, B Heinemann, A Fox, K Blum, H Ru¨cker, F Fu¨rnhammer, B Senapati, R Barth, U Haak, W Ho¨ppner, J Drews, R Kurps, S Marschmeyer, H H Richter, T Grabolla, B Kuck, O Fursenko, P Schley, R F Scholz, B Tillack, Y Yamamoto, K Ko¨pke, H E Wulf, D Wolansky, and W Winkler. A flexible, low-cost, high performance SiGe:C BiCMOS process with a one-mask HBT module. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 783–786. B Senapati, R F Scholz, D Knoll, B Heinemann, and A Chakravorti. Application of the VBIC model for SiGe:C heterojunction bipolar transistors. Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, 2004. W Winkler, J Borngra¨ber, B Heinemann, P Weger, and H Gustat. High-performance and low-voltage divider circuits fabricated in SiGe:C HBT technology. Proceedings of the European Solid-State Circuits Conference, Firenze, 2002, pp. 827–830. W Winkler, J. Borngra¨ber, H Gustat, and F Korndo¨rfer. 60 GHz transceiver circuits in SiGe:C BiCMOS technology. Proceedings of the 30th European Solid-State Circuits Conference, Leuven, 2004, pp. 83–86.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-341

21. W Winkler, J Borngra¨ber, B Heinemann, and P Weger. 60 GHz and 76 GHz oscillators in 0.25 mm SiGe:C BiCMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, 2003, pp. 454–455. 22. W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. 23. W Winkler and J Borngra¨ber. LC-oscillator for 94 GHz automotive radar system fabricated in SiGe:C BiCMOS technology. Conference Proceedings of the 12th European Gallium Arsenide & other Compound Semiconductors Application Symposium, Amsterdam, 2004, pp. 45–46.

© 2006 by Taylor & Francis Group, LLC

3.10 Industry Examples at the State-of-the-Art: ST A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy ST Microelectronics

3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 3.10.6

Introduction........................................................... 3.10-343 Device Structures................................................... 3.10-344 Doping and Impurity Profiles.............................. 3.10-347 BiCMOS Integration Issues .................................. 3.10-348 High-Frequency Characteristics ........................... 3.10-351 Outlook for the Future ......................................... 3.10-353

3.10.1 Introduction The history of SiGe BiCMOS technology development in the ‘‘French silicon valley’’ goes back to the early 1990s [1], when a team of materials researchers at France Telecom CNET Laboratories near Grenoble started investigations in the Si/SiGe system using rapid thermal chemical vapor deposition (RTCVD). Application of this work to the development of heterojunction bipolar transistors (HBTs) soon became a major research theme for the local bipolar device group [2–4]. At the same time, the development of a 0.5-mm single-polysilicon BiCMOS technology was going on in the new 200 mm Crolles plant of STMicroelectronics, a few kilometers away. A joint development work was then initiated between the two teams, with the objective to bring SiGe HBTs into manufacturing when the performance potential of silicon-only bipolar transistors would be fully exhausted [5]. This eventually happened with the 25/40 GHz fT/fmax double-polysilicon self-aligned transistor embedded in the 0.35-mm BiCMOS process. When it was internally demonstrated that much better performance, e.g., 50/70 GHz fT/fmax, could be obtained at the same technology node using a low-complexity SiGe HBT architecture [6], SiGe BiCMOS technology development at ST became a reality. Several SiGe BiCMOS processes, covering the 0.35, 0.25, and 0.13 mm technology nodes, and addressing both wireless and broadband communications applications, have been developed since then, and are now in production or at prototyping level at the Crolles plant. Table 3.10.1 outlines the main technological features of these processes, in terms of device isolation scheme, SiGe epitaxial base process, emitter–base and collector architectures, and emitter material. Main static and dynamic parameters of the high-speed SiGe HBT in these technologies are also summarized. A common feature of all these processes is the use of RTCVD for the growth of the SiGe (or SiGe:C) base. As discussed in Chapter 2.3, RTCVD presents many advantages over competing approaches, and is today the dominant technique for conventional Si epitaxy as well as advanced SiGe processes in the semiconductor industry. Likewise, all technologies rely on a conventional collector structure, consisting of a heavily arsenic-implanted layer buried under lightly doped epitaxial silicon. In contrast with these longstanding technological options, Table 3.10.1 shows that several materials and architecture changes have been brought to the SiGe HBT while moving along the performance path from 45 to 160 GHz fT. The motivations for these structural changes and the accompanying evolutions of transistor doping and impurity profiles are discussed in Sections 3.10.2 and 3.10.3, respectively. Section 3.10.4 addresses some 3.10-343 © 2006 by Taylor & Francis Group, LLC

3.10-344

The Silicon Heterostructure Handbook

TABLE 3.10.1 ST SiGe BiCMOS Technologies: Main Process Features and Device Parameters Technology

BiCMOS6G

BiCMOS7

BiCMOS7RF

BiCMOS9

CMOS node Back-end

0.35 mm Al

0.25 mm Al

0.25 mm Al

0.13 mm Cu

Collector Isolation Base E/B architecture Emitter

BL/epitaxy LOCOS SiGe NSEG QSA single-poly As implant Poly

BL/epitaxy STI/DTI SiGe NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

WE (mm) RpB (kV/sq) Basewidth (nm)

0.4 10 —

0.25 6.5 50

0.25 1 —

0.17 3.6 25

Current gain BVCEO (V) VAF (V) fT (GHz) fmax (GHz) JC (mA/mm2) NFmin @ 2 GHz

100 3.6 60 45 60 1.0 0.8

120 2.6 >50 70 90 3.8 —

200 3.0 >150 60 120 1.8 <0.4

600 1.7 >150 160 160 7.5 —

Applications Status

RF Production

Broadband Production

RF, PA Prototyping

Broadband Prototyping

Refs.

[8]

[9]

[15,16]

[17]

of the issues that have been encountered while integrating these HBTs into the corresponding CMOS flows. Main high-frequency characteristics of the SiGe HBT in the various technologies are reviewed in Section 3.10.5. Finally, Section 3.10.6 concludes the chapter with early results from the development of next generation transistors, targeting 230 GHz cutoff frequencies for the 90-nm technology node.

3.10.2

Device Structures

Figure 3.10.1 displays SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies. The geometrical scale can be inferred from the contact size, i.e., 0.4 mm in (a), 0.25 mm in (b and c) and 0.16 mm in (d). A glance at the pictures shows that, in all technologies, the SiGe base is grown using nonselective epitaxy (NSEG). Compared to the alternative selective deposition process (SEG), this approach presents several advantages [7]: simpler chemistry, larger growth rates (or lower growth temperature), reduced macro- and microloading effects, and improved metrology. Unfortunately, these advantages on the manufacturability side come at the expense of a penalty on the performance side. Indeed, there is no simple way to build a SiGe HBT with fully self-aligned (FSA) emitter–base (E–B) regions on a nonselective base. As briefly discussed in Section 3.10.6, there are only complex solutions to this problem, which (at least partly) outbalance the advantages of NSEG over SEG structures. A pragmatic answer to this manufacturability vs. performance trade-off is provided by the family of quasiself-aligned (QSA) HBT structures implemented in ST SiGe BiCMOS technologies. As shown in Figure 3.10.1(a), a single-polysilicon QSA structure is used in BiCMOS-6G [8], which mainly addresses the RF mobile communications market. In this construction, the poly-SiGe extension of the base formed on the field oxide (here LOCOS) during epitaxy is used as the extrinsic base material. The emitter (width WE ¼ 0.4 mm) is defined by a window opened in a thin deposited nitride/oxide stack. The low topography of the structure enables the use of a conventional arsenic-implanted polysilicon emitter, which is subsequently patterned around the emitter window using a second

© 2006 by Taylor & Francis Group, LLC

3.10-345

Industry Examples at the State-of-the-Art: ST

(a)

(b)

(c)

(d)

FIGURE 3.10.1 SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies: (a) BiCMOS-6G, (b) and (c) BiCMOS-7 and -7RF, (d) BiCMOS-9. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.10-346

The Silicon Heterostructure Handbook

lithography level. An extrinsic base implant is then performed self-aligned to the polysilicon emitter block (i.e., not to the emitter), followed by dopant activation and salicidation. This single-polysilicon QSA structure is very simple and ideally meets the performance needs of BiCMOS-6G (45/60 GHz fT/fmax). However, several limitations have been foreseen when considering the significantly higher performances (70/90 GHz fT/fmax) targeted for the second generation technology, BiCMOS-7: (i) narrow emitter windows (below 0.3 mm) are difficult to obtain using this process, which penalizes base resistance-related parameters (e.g., fmax, NFmin) and power consumption; (ii) good silicidation of the poly/mono-SiGe/Si boundary region at the edge of the active area is difficult, which penalizes the base access resistance; (iii) point defects injected at the emitter periphery during extrinsic base implantation cause enhanced boron diffusion and base widening [3], which negatively impacts the forward transit time (fT). The double-polysilicon QSA structure developed for BiCMOS-7 successfully addresses all these limitations* [9]. As shown in Fig. 3.10.1b and c, shallow/deep trench isolation (STI/DTI) is used in this technology, which reduces parasitic capacitances and provides a flat topography after SiGe base epitaxy. A conventional double-polysilicon structure is constructed above the base, resulting in the following advantages regarding items (i) to (iii) above: (i) internal spacers reduce the effective emitter width from the emitter window opening, enabling narrow emitters (WE ¼ 0.25 mm) without specific lithography requirements; (ii) extrinsic base silicidation is greatly improved by the availability of a true polysilicon base layer (on top of the poly-SiGe extension of the base), and by the flat topography of the structure at the edges of the base active area; (iii) the extrinsic-to-intrinsic base contact region is formed by the out-diffusion of boron from the base polysilicon layer, avoiding base widening effects related to high-dose implants through the SiGe layer. In order to prevent overetching into the thin epitaxial base during emitter window opening, a polysilicon/oxide pedestal is patterned on the SiGe base prior to base polysilicon deposition, as visible in Figure 3.10.1(c). As a result, emitter and base regions are not self-aligned in this structure either. However, it has been found that a proper overlay strategy with present-day steppers allows enough process margin for the emitter window enclosure by this etch-stop layer, while easily meeting BiCMOS-7 performance targets. A closer look at Figure 3.10.1(c) also reveals a significant difference in the crystalline structure of the emitter, when compared with the first-generation transistor. Indeed, due to the larger topography of the structure at the emitter deposition step, in-situ arsenic-doped polysilicon is used in BiCMOS-7 to avoid emitter perimeter depletion and plug effects. This material is deposited in a commercial singlewafer CVD reactor. Load locks and a very clean ambient eliminate any unwanted oxide layer at the polySi–Si interface, resulting in monocrystalline structure on the active transistor region and in polycrystalline structure on the surrounding isolation regions at the end of the process (Figure 3.10.2). These socalled monoemitters have many advantages over conventional polyemitters [10, 11]: (i) very shallow and uniform E/B junction depths are obtained; (ii) manufacturability issues related to the control and reproducibility of the interfacial oxide layer are suppressed; (ii) emitter resistance and low frequency noise are significantly reduced; (iii) base current is increased, which translates into an improved emitterto-collector breakdown voltage, BVCEO. It should be pointed out that this monocrystalline emitter process was first described in Ref. [12], and is now becoming a standard in the SiGe BiCMOS technology industry. Extension to a SiGe emitter process has also been proposed recently [13]. The range of performances achievable with the double-polysilicon QSA HBT structure has been dramatically extended by introducing SiGe:C base technology [14]. The device used in BiCMOS-7RF, which addresses RF [15] and power amplifier [16] applications, is structurally and geometrically identical to the BiCMOS-7 transistor shown in Figure 3.10.1b and c. Here, carbon doping of SiGe is *It should be pointed out that the latter two effects (ii) and (iii) are minimized in more recent technologies using shallow trench isolation (STI) instead of LOCOS (this reduces the topography of the structure at the edges of the base active area), and carbon-doping of the SiGe base (which suppresses to a large extent transient enhanced diffusion effects caused by the extrinsic base implant).

© 2006 by Taylor & Francis Group, LLC

3.10-347

Industry Examples at the State-of-the-Art: ST

Poly

Epi

SiGe base 60 nm

FIGURE 3.10.2 TEM cross section showing the monocrystalline structure of the emitter in ST BiCMOS-7 technology (similar emitter structure is used in BiCMOS-7RF and -9).

leveraged to improve high-frequency noise figures by enabling much larger integrated base doping concentration. In contrast, the SiGe:C process developed for BiCMOS-9 aims at producing devices with ultrathin bases, in order to comply with the very high cutoff frequencies (160 GHz fT and fmax) required for broadband communications applications [17]. As shown in Figure 3.10.1(d), the transistor structure has been scaled vertically and laterally while moving to 0.13 mm technology node. Vertical scaling was imposed by CMOS compatibility constraints, as discussed in Section 3.10.4. Horizontal scaling, with final emitter widths of 0.17 mm, minimizes the intrinsic component of the base resistance, as well as parasitic elements such as collector resistance and collector/base (C/B) capacitance, which is needed to reach frequency performance targets. Moreover, a reduced emitter stripe width is mandatory to accommodate the increased current density at peak fT in this technology (see Figure 3.10.9).

3.10.3 Doping and Impurity Profiles Transistor doping and impurity profiles have also greatly evolved throughout these developments. The main features of these profiles and the motivations for these evolutions are discussed in this section, with the help of the schematic drawings shown in Figure 3.10.3. BiCMOS-6G and -7, which use a pure SiGe base (i.e., without carbon doping), rely on a ‘‘conventional’’ E/B dopant distribution, where the arsenic profile intercepts the boron profile close to its maximum value (Figure 3.10.3(a)). The doping level there is typically limited to 5 1018 cm3 to avoid tunneling currents and excessive E/B junction capacitance. A two-step germanium profile is used in the base, with larger concentration on the collector side than on the emitter side. This profile serves several purposes and is designed as follows: (i) the Ge content of the lower step sets (to a large extent) the current gain of the transistor; (ii) the flat Ge profile at the E/B junction stabilizes the current gain against fluctuations in the junction depth and improves the reverse Early voltage (as compared to a graded Ge profile); (iii) the larger Ge concentration on the collector side reduces boron diffusion and base widening during processing; (iv) the Ge step in the base creates a pseudoelectric field, which reduces base transit time and improves fT; and (v) the difference in the Ge content between C/B and E/B

© 2006 by Taylor & Francis Group, LLC

3.10-348

The Silicon Heterostructure Handbook

SiGe HBT

Ge B

SiGe:C HBT Ge

As

Concentration

Concentration

As

B

P

P

(a)

Depth

(b)

Depth

FIGURE 3.10.3 Schematic evolution of transistor doping and impurity profiles through ST SiGe BiCMOS technologies: (a) BiCMOS-6G and -7, (b) BiCMOS-7RF (dashed lines), and BiCMOS-9 (solid lines).

junctions increases the forward Early voltage of the transistor. It shoud be pointed out that the whole profile has been scaled down while moving from BiCMOS-6G to -7, in order to comply with the frequency performance increase (final basewidth WB is 50 nm in the latter process). This has been highly facilitated by the introduction of the monoemitter process discussed above. The collector doping, set by a masked implantation prior to SiGe base deposition, has also been adjusted (i.e., increased). No change has been brought to the collector epitaxy thickness. Doping and Ge profiles used in BiCMOS-9 and 7RF SiGe:C technologies are significantly different from the above discussed profiles (Figure 3.10.3(b)). Their main features can be summarized as follows: (i) a bell-shaped boron distribution with peak doping concentration significantly above 1019 cm3 is used in the base, which is made possible by the strong reduction of boron diffusion in SiGe:C [14]; (ii) there is no overlap between arsenic and boron profiles, which keeps E/B junction capacitance low despite the heavy base doping level; (iii) the Ge content is graded across the base on the emitter side, in order to compensate the retarding electric field associated with the retrograde boron profile; (iv) a flat Ge profile is used on the collector side, where an accelerating field is created by the boron distribution itself. Such trapezoidal Ge profile has been found optimum to avoid layer stability issues and high injection induced barrier effects in high-voltage transistors, which can been encountered with triangular Ge profiles. As shown in Figure 3.10.3(b), different optimizations of this generic SiGe:C HBT profile are used in BiCMOS-9 and -7RF. BiCMOS-9 favors a short forward transit time to reach the high fT target. This is obtained using a very thin base (WB 25 nm), a high collector doping, and a thin collector epitaxy. Despite the narrow base, pinched base resistance remains low (RpB 3.6kV/sq.) thanks to the heavy boron doping, enabling simultaneously high fT and fmax in this technology. In contrast, noise figure and analog characteristics are given prior attention in BiCMOS-7RF. To this end, the boron spike width (and the whole SiGe:C stack) has been enlarged, leading to very low base resistance (RpB 1 kV/sq). Also, larger spacing is used between arsenic and boron profiles (through the thickness of the silicon-capping layer), which reduces E/B junction capacitance and improves low current characteristics. The collector structure in this technology is similar to BiCMOS-7. As detailed in Refs. [15, 17], the carbon concentration in both SiGe:C technologies has been carefully optimized to effectively suppress boron diffusion during processing, while avoiding E/B and neutral base recombination effects observed at excessively large carbon contents.

3.10.4

BiCMOS Integration Issues

One major challenge of BiCMOS integration engineers is to design a process flow in such a way that bipolar transistors can be added without disturbing CMOS devices, in order to retain full compatibility

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

3.10-349

with existing logic libraries. This has become increasingly difficult, with the downscaling of CMOS gate lengths and the upscaling of bipolar cutoff frequencies. BiCMOS integration issues are briefly reviewed in this section, with special emphasis on ST’s most challenging technology in this respect, i.e., BiCMOS-9. Generally speaking, the integration of a high-speed HBT within an advanced CMOS technology raises several types of concerns: (i) Thermal cycle issues. The process flow must be designed to avoid substantial CMOS dopant motion due to the addition of the HBT fabrication steps. The hydrogen pre-bake used in RTCVD to clean the base active area prior to SiGe epitaxy is particularly critical in this regard. Symmetrically, high-temperature CMOS processing must be placed prior to the HBT formation to minimize base broadening. It should be pointed out that the use of SiGe:C is very helpful, due to the blocking effect of carbon on the diffusion of boron. Arsenic emitter doping (as opposed to phosphorous) is also favorable, since it is compatible with the final activation anneal of the CMOS process, that the HBT is usually exposed to. (ii) Structural integration issues. The fabrication of the HBT in the presence of CMOS gate topography requires careful choice of integration sequence. Numerous films are deposited during the HBT formation, as illustrated on Figure 3.10.4 which shows the accumulation of some of these films over closely spaced 0.13-mm gates in BiCMOS-9. Subsequent etch steps must isotropically remove these films without leaving unwanted spacers. Another difficulty encountered in the development of BiCMOS-9 is related to the thin photoresists used for critical lithography steps, such as gate patterning. The topography of the adjacent bipolar areas must then be low enough to ensure that sufficient resist be left there to avoid damaging the HBTs while processing CMOS gates. (iii) Back-end compatibility issues. Thin premetal dielectric layers are used in advanced CMOS technologies to reduce the contact hole aspect ratio. This raises concerns in a BiCMOS process, where bipolar transistors are usually higher than CMOS devices, and justifies the significant vertical scaling applied to the double-polysilicon QSA HBT structure while moving to 0.13-mm technology node (see Figure 3.10.1(c and d)). Electromigration issues must also be paid attention in high-speed SiGe BiCMOS technologies, where large current densities (JC) can be attained at peak fT. In BiCMOS-9 where JC 7.5 mA/mm2, full compatibility with the back-end rules of the core CMOS process has been maintained by developing a specific transistor layout, with two rows of contacts (and vias) on emitter and collector regions (see Figure 3.10.1(d)). A generic process flow for ST SiGe BiCMOS technologies is shown in Figure 3.10.5. In all processes, the fabrication starts with buried layer formation on a p-substrate, followed by collector epitaxy. The DTI module is then inserted (except in BiCMOS-6G). Next, the shallow trench module (or LOCOS for BiCMOS-6G) of the CMOS core process is implemented, and the collector reachthrough is formed. At

FIGURE 3.10.4 SEM cross section showing closely spaced 0.13-mm CMOS gates covered by SiGe:C HBT films in ST BiCMOS-9 technology.

© 2006 by Taylor & Francis Group, LLC

3.10-350

The Silicon Heterostructure Handbook

CMOS backbone

Bipolar steps

Shallow trench isolation

Buried layer and collector epitaxy Deep trench isolation Collector reachthrough

Well implants Gate oxide process Poly gate

Extension & S/D implants Activation anneal Salicidation and contacts Metal interconnect

SIC implant Base epitaxy Emitter−base structure

FIGURE 3.10.5 Schematic integration flow for ST SiGe BiCMOS technologies, showing insertion of bipolar modules into the CMOS core process.

FIGURE 3.10.6 Saturation current vs. threshold voltage for 1.2 V low leakage nMOS and pMOS transistors in 0.13 mm pure CMOS and BiCMOS-9 technologies. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and

this stage, the CMOS flow resumes with the formation of wells, gate oxides, and polysilicon gates. Deviations then exist regarding the fabrication of the emitter–base structure of the HBT. In BiCMOS6G, 7, and 7RF, where the main concern was the integrity of the pMOS transistor, the whole E/B module is inserted between extension and source/drain implants, in order to avoid boron penetration through the gate oxide. The situation is more complex in the case of BiCMOS-9, where both CMOS and bipolar devices have become very touchy. A novel integration scheme has been developed for this technology [17], in which E/B fabrication steps are split into two parts, in such a way that all integration issues discussed in concerns (i) and (ii) are solved. Finally, all fabrication sequences are completed by the activation anneal of dopants, salicidation, contact formation, and metallization. Figure 3.10.6 compares 0.13-mm pure CMOS and BiCMOS-9 technologies regarding the saturation current and the threshold voltage of nMOS and pMOS transistors. The results demonstrate the successful integration of the high-speed SiGe:C HBT with the newly developed BiCMOS integration scheme.

© 2006 by Taylor & Francis Group, LLC

3.10-351

Industry Examples at the State-of-the-Art: ST

3.10.5 High-Frequency Characteristics Figure 3.10.7 and Figure 3.10.8 summarize high-frequency figures-of-merit fT vs. BVCEO and fmax vs. fT for the low-voltage SiGe HBT in the various technologies discussed above, and for a high-voltage device obtained in BiCMOS-7RF and -9 by altering the collector doping profile. Shown values of fT and fmax are

A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.) 200

BC6G BC7 150

BC7RF

fT (GHz)

BC9 180

270

BC7RF-HV

100

BC9-HV

50 f T ⫻ BVCEO (GHz-V) 0 0

2

8

6

4 B V CEO (V)

FIGURE 3.10.7 fT vs. BVCEO data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies. Solid lines represent process design contours with constant fTBVCEO product.

200 fmax > fT 150

fmax (GHz)

fmax < fT BC6G

100

BC7 BC7RF 50

BC9 BC7RF-HV BC9-HV

0 0

50

100

150

200

f T(GHz)

FIGURE 3.10.8 fmax vs. fT data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies. © 2006 by Taylor & Francis Group, LLC

3.10-352

The Silicon Heterostructure Handbook

200 BC9 BC6G

150 f T (GHz)

BC7 BC7RF 100

50

0 0.01

0.1

1 JC

10

100

(mA/µm2)

FIGURE 3.10.9 Comparison of fT vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

derived from s-parameter measurements up to 110 GHz. Details on the procedure used to extract fmax from unilateral power gain data may be found in Ref. [17]. The fT vs. BVCEO plot in Figure 3.10.7 shows the classical trade-off between operation speed and breakdown voltage, with fT BVCEO products close to 180 GHz-V for most devices, except in BiCMOS-9 where this product rises up 270 GHz-V for the high-speed SiGe:C HBT. Figure 3.10.8 shows that fmax/fT ratios larger than unity have been maintained throughout the roadmap, which indicates that process enhancements used to increase fT have not been detrimental to fmax. This holds true for the high-speed HBT in BiCMOS-9, where fTfmax 160 GHz. This remarkable (and somewhat unexpected) result demonstrates that the combination of the robust double-polysilicon QSA HBT structure with a thin and heavily doped SiGe:C base can provide outstanding frequency performances. The various SiGe technology generations are further compared in Figure 3.10.9 and Figure 3.10.10, which plot the dependencies of fT and fmax on collector current density JC. Here again, a classical trend of increasing current density with peak fT value is observed: from 45 to 160 GHz, approximately eightfold increase in JC at peak fT is obtained. This reflects the delayed onset of Kirk effect at increasing collectordoping concentrations. The benefits of SiGe:C base technology and geometrical scaling for RF and broadband applications are highlighted by the following observations: (i) RF applications. Comparing BiCMOS-7RF and -7 characteristics in Figure 3.10.7 to Figure 3.10.10, one notices a large increase in fmax (from 90 to 120 GHz), despite a 10-GHz decrease in fT linked to a small BVCEO adjust. This results from the drastic reduction of base resistance (pinched base resistance decreases from 6.5 to 1kV/sq) achieved with heavy SiGe:C base doping. As shown in Figure 3.10.11, this translates into excellent HF noise characteristics: NFmin at 2 GHz is lower than 0.4 dB in BiCMOS-7RF, which is twice smaller than in the first RF SiGe process, BiCMOS-6G. Comparing further BiCMOS-6G and -7RF performances in Figure 3.10.10, it is found that fmax has been increased by a factor of 2 for similar current per unit transistor length (i.e., similar JC WE). This large performance improvement is explained by the combination of the heavily doped SiGe:C base and the reduced emitter width in BiCMOS7RF. As discussed in Ref. [16], the high-voltage SiGe:C HBT also benefits from these features, enabling the integration of power amplifiers with RF functions using this technology. (ii) Broadband applications. Similarly, the introduction of carbon-doped SiGe and the downscaling of emitter widths from 0.25 to 0.17 mm account for the large fmax performance jump (þ60 GHz) between BiCMOS-7 and -9 HBTs (Figure 3.10.10). In this case, the process has

© 2006 by Taylor & Francis Group, LLC

3.10-353

Industry Examples at the State-of-the-Art: ST

1.2

NF min(dB)

1.0

200 BC9 BC6 G

f max (GHz)

150

AE = 6⫻(0.25⫻9.85) µm2 f = 2 GHz VBC = 0 V VBC = −1 V

0.8 0.6 0.4 0.2

BC7

0 0

BC7RF

100

0.005

0.01

0.015

0.02

IC (A) 50

0 0.01

0.1

1

10

100

JC (mA/µm2)

FIGURE 3.10.10 Comparison of fmax vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

FIGURE 3.10.11 Noise figure vs. collector current at 2 GHz for BiCMOS-7RF SiGe:C HBT. (From H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. BiCMOS7RF: a highly manufacturable 0.25 mm BiCMOS RF-applications-dedicated technology using nonselective SiGe:C epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. With permission.)

been designed to provide similar fT enhancement simultaneously. As shown in Figure 3.10.9, the SiGe:C HBT in BiCMOS-9 has about twice the fT of the BiCMOS-7 device at its peak current density of 4 mA/mm2. Alternatively, this approximately twofold higher frequency can be traded for an approximately fivefold reduction in power consumption at the same frequency for applications not requiring the ultimate performance. It should be pointed out that, in addition to these remarkable frequency performances, excellent yield results and process reproducibility have been demonstrated for this technology, as detailed in Ref. [17].

3.10.6 Outlook for the Future In this chapter, the main features of ST 0.35, 0.25, and 0.13 mm SiGe BiCMOS technologies have been reviewed, with emphasis on SiGe HBT structures, profiles, and high frequency characteristics. Further details on these processes, including other available active and passive components, may be found in the literature [8, 15–17]. Circuit applications of these technologies for the mobile communications market are described in Chapter 9.14 of this book. As far as optical communications applications are concerned, available circuit results indicate that the 160 GHz fT/fmax BiCMOS-9 device is able to address the 40 Gb/s market [18, 19]. For more demanding applications, such as 77 GHz automotive radar, higher frequency performances will be required, e.g., >230 GHz fT/fmax. From the past experience in BiCMOS-9 technology optimization, we estimate that the double-polysilicon QSA HBT architecture can be extended over 200 GHz fT, but that aggressive design rules would be needed to reach 230 GHz fmax. Consequently, decision has been made to investigate a FSA HBT structure for 90-nm SiGe BiCMOS generation. As mentioned already, FSA HBT structures using nonselective base epitaxy are not straightforward. They require specific process modules, such as CMP or countermask lithography, which are not easy to implement and to integrate into a BiCMOS flow. For this and other reasons discussed in Refs. [20, 21], the approach used at ST is based on the selective epitaxial base (FSA-SEG) concept, which has the other advantage to be mask-compatible with the QSA-NSEG approach.

© 2006 by Taylor & Francis Group, LLC

3.10-354

FIGURE 3.10.12

The Silicon Heterostructure Handbook

SEM cross section through a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

400

55 K

f max fT, fmax (GHz)

300

fT 300 K

200

100

0 0.1

AE = 0.17⫻3.6 µm2 VC B = 0.5 V 1

10

100

JC (mA/µm2)

FIGURE 3.10.13 High-frequency characteristics at 300 and 55 K of a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

Figure 3.10.12 shows an SEM cross section through a FSA-SEG SiGe:C HBT fabricated using BiCMOS-9 reticles. The main difficulty with the selective epitaxy of SiGe:C is the higher growth temperature compared to nonselective epitaxy, which is detrimental to the carbon incorporation on substitutional sites. However, by proper optimization of the carbon and Ge profiles, this difficulty can be solved, and good process manufacturability and world class device performances (230 and 350 GHz fT/fmax at room and cryogenic temperatures, respectively) have been demonstrated, such as shown in Figure 3.10.13. It should be pointed out that these performances have been obtained for a device using an arsenic-doped monoemitter and sustaining a high thermal budget, which will facilitate its later integration with 90-nm CMOS.

Acknowledgments The authors are indebted to the many people at ST Microelectronics Crolles involved in the various aspects of this work. In particular, they wish to thank the members of the epitaxy teams of D. Dutartre (C. Fellous, F. Dele´glise, and L. Rubaldo) and D. Bensahel (Y. Campidelli and O. Kermarrec), and of the former CVD group of J.L. Regolini at France Telecom CNET Laboratories, for their contributions to making SiGe BiCMOS technology at ST a success story. The continuous support of B. Sautreuil and M. Roche is also gratefully acknowledged.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

3.10-355

References 1. D. Dutartre, G. Bre´mond, A. Souifi, and T. Benyattou. Excitonic photoluminescence from Si-capped strained Si1–xGex layers. Phys. Rev. B 44:11525–11527, 1991. 2. H. Boussetta, G. Giroult-Matlakowski, B. Le Tron, D. Dutartre, P. Warren, M.J. Bouzid, and A. Chantre. Identification of peripheral base currents in Si or SiGe epitaxial-base single-polysilicon self-aligned bipolar transistors. Proceedings 24th European Solid-State Device Research Conference, Edinburgh, 1994, pp. 63–66. 3. S. Denorme, H. Boussetta, A. Chantre, G. Vincent, and M. Mouis. Demonstration of enhanced base diffusion due to extrinsic base implantations in submicron, polysilicon-emitter, epitaxial base bipolar transistors. Proceedings 25th European Solid-State Device Research Conference, The Hague, 1995, pp. 513–516. 4. B. Le Tron, M.D.R. Hashim, P. Ashburn, M. Mouis, A. Chantre, and G. Vincent. Determination of bandgap narrowing and parasitic energy barriers in SiGe HBTs integrated in a bipolar technology. IEEE Trans. Electron Devices 44:715–722, 1997. 5. E. de Berranger, S. Bodnar, A. Chantre, J. Kirtsch, A. Monroy, M. Laurens, A. Granier, J.L. Regolini, and M. Mouis. Performance improvement in a 200 mm BiCMOS technology by Si/SiGe heterojunction bipolar transistor integration. Proceedings 26th European Solid-State Device Research Conference, Bologna, 1996, pp. 433–436. 6. A. Chantre, M. Marty, J.L. Regolini, M. Mouis, J. de Pontcharra, D. Dutartre, C. Morin, D. Gloria, S. Jouan, R. Pantel, M. Laurens, and A. Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–96. 7. D. Dutartre. Silicon epitaxy: new applications. In Semiconductors and Semimetals, vol. 72. Academic Press, New York, 2001, pp. 397–457. 8. A. Monroy, M. Laurens, M. Marty, D. Dutartre, D. Gloria, J.L. Carbonero, A. Perrotin, M. Roche, and A. Chantre. BiCMOS6G: a high performance 0.35 mm SiGe BiCMOS technology for wireless applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 121–124. 9. H. Baudry, B. Martinet, C. Fellous, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, J. Mourier, G. Troillard, A. Monroy, D. Dutartre, D. Bensahel, G. Vincent, and A. Chantre. High performance 0.25 mm SiGe and SiGe:C HBTs using non selective epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 52–55. 10. S. Jouan, R. Planche, M. Marty, D. Dutartre, J.A. Chroboczek, P. Llinares, H. Baudry, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. In-situ arsenic doped single-crystal emitters for low 1/f noise SiGe HBTs. Proceedings of the 29th European Solid-State Device Research Conference, Leuven, 1999, pp. 336–339. 11. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinare`s, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. A high speed low 1/f noise SiGe HBT technology using epitaxially aligned polysilicon emitters. IEEE Trans. Electron Devices 46:1525–1531, 1999. 12. S. Niel, O. Rozeau, L. Ailloud, C. Hernandez, P. Llinare`s, M. Guillermet, J. Kirtsch, A. Monroy, J. de Pontcharra, G. Auvert, B. Blanchard, M. Mouis, G. Vincent, and A. Chantre. A 54 GHz fmax implanted base 0.35 mm single-polysilicon bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington DC, 1997, pp. 807–810. 13. B. Martinet, F. Romagna, O. Kermarrec, Y. Campidelli, F. Saguin, H. Baudry, M. Marty, D. Dutartre, and A. Chantre. An investigation of the static and dynamic characteristics of high speed SiGe:C HBTs using a poly-SiGe emitter. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2002, pp. 147–150. 14. B. Martinet, H. Baudry, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, T. Schwartzmann, A. Monroy, D. Bensahel, and A. Chantre. 100 GHz SiGe:C HBTs using non selective base

© 2006 by Taylor & Francis Group, LLC

3.10-356

15.

16.

17.

18. 19.

20.

21.

The Silicon Heterostructure Handbook

epitaxy. Proceedings 31st European Solid-State Device Research Conference, Nuremberg, 2001, pp. 97–100. H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. BiCMOS7RF: a highly manufacturable 0.25 mm BiCMOS RF-applications-dedicated technology using nonselective SiGe:C epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. D. Muller, A. Giry, C. Arnaud, C. Arricastres, R. Sommet, B. Szelag, A. Monroy, and D. Pache. LDMOSFET and SiGe:C HBT integrated in a 0.25 mm BiCMOS technology for RF-PA applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 168–171. M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. T.O. Dickson, R. Beerkens, and S.P. Voinigescu. A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic. Proceedings Symposium on VLSI Circuits, Honolulu, 2004, pp. 206–209. S.P.Voinigescu, T.O. Dickson, R. Beerkens, and P. Westergaard. A comparison of Si CMOS, SiGe BiCMOS, and InP HBTs technologies for high-speed and millimeter-wave ICs. Proceedings Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 2004, pp. 111–114. P. Chevalier, C. Fellous, B. Martinet, F. Leverd, F. Saguin, D. Dutartre, and A. Chantre. 180 GHz fT and fmax self-aligned SiGeC HBT using selective epitaxial growth of the base. Proceedings European Solid-State Device Research Conference, Estoril, 2003, pp. 299–302. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, N. Ze´rounian, F. Aniel, and A. Chantre. 230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 225–228.

© 2006 by Taylor & Francis Group, LLC

3.11 Industry Examples at the State-of-the-Art: Texas Instruments Integration of a Complementary-SiGe BiCMOS Process for High-Speed Precision Analog Applications 3.11.1 3.11.2

Introduction........................................................... 3.11-357 Process Integration................................................ 3.11-358 Starting Material . Buried Layers, Collector Epitaxy . Lateral Isolation . Collector Sinkers, CMOS Wells . Base Modules . Emitter Modules . CMOS Module . Capacitors . Resistors

B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda Texas Instruments

3.11.3

Components and their Characteristics................ 3.11-362 Bipolars . CMOS . Capacitors . Resistors Thermal Resistance

3.11.4 3.11.5

.

Circuit Application................................................ 3.11-366 Summary ................................................................ 3.11-366

3.11.1 Introduction Extensive work has been published on RF SiGe [1–15] and SiGe:C [16–18, 22] npn transistors with impressive cutoff frequencies in the range 40–350 GHz. There are, however, very little data available on SiGe and SiGe:C pnp transistors [19–21]. The design of complementary npn and pnp transistors of high and comparable performance is important to linear analog circuits with symmetrical architectures. In addition, there is a tradeoff between gain (b), transistor breakdown (BVCEO), early voltage (VA), cutoff frequency (fT), and noise that must be met for every application. Finally, there are limitations to the thermal budget that must be considered when integrating SiGe-bipolar, CMOS, and passive components. These considerations were taken into account during the development of a novel, full dielectrically isolated modular complementary-SiGe BiCMOS process that is now in manufacturing for ultrahighspeed precision analog circuits [23]. The availability of SiGe and a controlled emitter interface oxide (IFO) provide added flexibility during the tradeoff. This chapter describes the integration of bipolar, 3.11-357 © 2006 by Taylor & Francis Group, LLC

3.11-358

The Silicon Heterostructure Handbook

CMOS, and passive process modules; their interactions; and integration issues. Active and passive components and their key parameters are then discussed. The chapter concludes with a summary of results obtained on a typical voltage feedback operational amplifier.

3.11.2

Process Integration

This section describes the integration of bipolar, CMOS, and passive process modules and their interactions. Table 3.11.1 summarizes key processing steps. A schematic cross-section of the completed bipolar transistors is shown in Figure 3.11.1 for illustration.

Starting Material The starting material is commercially available silicon on insulator (SOI) wafers with 1.25-mm top silicon and 0.1 to 0.4-mm buried-oxide (BOX) on high-resistivity p-type support wafers. The choice of buried oxide (BOX) thickness is a tradeoff between thermal resistance, maximum applied voltage, parasitic capacitance between collector and support wafer, and cost. For high-voltage applications, the BOX thickness is typically 0.4 mm. It is thinned down to 0.1–0.2 mm wherever applicable to reduce thermal resistance and self-heating, particularly during operation at maximum power. Reducing the BOX thickness, however, increases parasitic capacitance. For a typical p-type support wafer, this increase is particularly significant in pnp structures because of the accumulating applied voltage and workfunction difference between collector and support wafer. Increasing its resistivity to >100 Ohm-cm reduces the impact of thinner BOX on parasitic capacitance and also improves the quality factor of passive components. The latter is especially important in RF applications.

Buried Layers, Collector Epitaxy The n- and p-buried layers (NBL and PBL) are patterned, implanted, and diffused into the top silicon film. The implant and anneal conditions are critical to maintaining low collector resistances while minimizing defect density, surface roughness, and autodoping during epitaxy. An epitaxial film is then deposited. Its minimum thickness is primarily limited by the buried-layer updiffusion, the selectively implanted collector (SIC) and base profiles, and their impact on transistor breakdown. Tighter control of the epitaxial film allows reduction of its nominal thickness, improving fT (mainly the npn fT) while maintaining the minimum transistor breakdown of 5.5 V. For some applica-

TABLE 3.11.1

Key Process Modules

Starting material, SOI wafer Buried layer implants and anneal Collector epitaxy Isolation. Deep- and shallow-trench patterning and fill Collector sinker implants CMOS well implants npn base module pnp base module Precision polysilicon resistor patterning and implant npn emitter module pnp emitter module Patterning of CMOS gate, base, polysilicon resistors, polysilicon capacitor plates Source/drain implant and anneal MIM capacitor module Metal-1 and Metal-2 modules Thin-film resistor module Metal-3 and Metal-4 modules

© 2006 by Taylor & Francis Group, LLC

3.11-359

Industry Examples at the State-of-the-Art: Texas Instruments

17 16

14

5

9

13

3

11

4

2

12

15

5

7

5 4

8

10

3 1

5

6

5 4

Buried oxide PNP

NPN Support wafer

FIGURE 3.11.1 Schematic cross-section of npn and pnp transistors. 1: n-buried layer; 2: p-buried layer; 3: collector epitaxy; 4: deep trench; 5: STI; 6: npn sinker; 7: pnp sinker; 8: npn base; 9: pnp base; 10: npn SIC; 11: pnp SIC; 12: NEMIT POLY; 13: PEMIT POLY; 14: CoSi2; 15: BPSG; 16: contact; 17: first metal (second to fourth metal not shown).

tions, boron is implanted in an intermediate region under the base of the pnp. This allows tailoring the collector profile independently of epitaxial thickness, reducing the collector resistance and improving fT while maintaining low-impact ionization at the collector–base junction.

Lateral Isolation Oxide-filled, deep, and shallow trenches fully encapsulate components. This isolation technique minimizes parasitic capacitances, eliminates latch-up, increases packing density, and allows for separate CMOS body-bias and extensions to high-voltage applications. Deep trenches are first patterned and etched into silicon through a triple oxide–nitride-oxide (ONO) stack of suitable film thickness. After partially filling deep trenches, shallow trenches are patterned, straddling deep trenches, and etched into silicon. A thin oxide liner is grown in both trenches followed by conventional oxide-fill and chemical– mechanical polishing (CMP). The process is optimized to minimize stress [24], and provide a quasiplanar surface for subsequent processing steps.

Collector Sinkers, CMOS Wells Collector sinkers are patterned and implanted to reduce collector resistance. Several factors are considered when defining the sinker dose and energy: the collector resistance, the limited thermal budget, and the sinker surface concentration. The latter is an important factor when constructing a ‘‘highdensity’’ capacitor over an n-type sinker with polysilicon as the second plate and the gate-oxide film as the dielectric. As the surface concentration increases, the oxidation rate increases, reducing the capacitance per unit area. An increase in surface concentration also degrades the dielectric integrity. An advantage of full dielectric isolation over junction isolation is the capability of independently isolating the bottom plate of the polysilicon–oxide–silicon capacitor. After growing 11.5-nm CMOS gate oxide, an intrinsic polysilicon film is deposited that constitutes the first part of the CMOS polysilicon gate. The second part is deposited during the npn base formation.

Base Modules The bipolar base modules begin after the deposition of the CMOS intrinsic gate-polysilicon. The npn base is first patterned by removing the gate-polysilicon and gate oxide from the base region. The SiGe

© 2006 by Taylor & Francis Group, LLC

3.11-360

The Silicon Heterostructure Handbook

npn base is grown epitaxially in the patterned windows and as a polysilicon film over the first intrinsic polysilicon-gate. The film can be in-situ doped or implanted. The base-polysilicon and first gatepolysilicon form the final CMOS gate, capacitor plates, and one of the polysilicon precision resistors. While low in concentration, the presence of Ge in the CMOS gate slightly modifies its bandgap, and hence workfunction [25]. For a specified threshold voltage, a minor re-adjustment in channel profile may become necessary when the npn base Ge concentration is modified. Patterning the pnp base is critical. The npn base polysilicon/epitaxy is first covered with a thin film that will serve as an etch stop in a subsequent step. The pnp base region is patterned through the stack, and a SiGe pnp base epitaxy/polysilicon deposited. Similarly to the npn, the film can be in-situ doped or implanted. A tight control of emitter patterning and film undercut allows the reduction of base dose and energy, and hence of base width, increasing fT without impacting emitter–base leakage. The Ge profile is tailored to maximize VA. The positions of the SiGe/Si transitions strongly impact bipolar parameters. In this process, the pnp early voltage (VA) is dominated by the ratio of Ge concentration at the collector– base junction to that at the emitter–base junction [26, 27]. This limits the flexibility of increasing the Ge concentration at the emitter–base junction to increase gain without seriously impacting VA.

Emitter Modules The key feature of the emitter modules is the npn and pnp interface oxide (IFO) formed at the base surface immediately below the emitter polysilicon. The emitter modules start with a stack of grown/ deposited insulators into which emitter windows are patterned over the base. The thickness and composition of the stack is a tradeoff between patterning control and emitter–base overlap capacitance. The npn emitter openings are first patterned, leaving only a thin oxide film that serves as a screen oxide during the selectively implanted collector (SIC) with the photoresist in place. The SIC profile is tailored to maximize fT while satisfying requirements on impact ionization. A similar process is repeated for pnp emitters and SIC. The most critical step is the emitter surface preparation and interface oxide formation. After removing the thin screen oxide, a controlled IFO is grown over emitters. The interface oxide considerably reduces tunneling of carriers injected from the base into the emitter, resulting in a larger increase in gain and reduction in transistor breakdown voltage. An increase in interface oxide also increases flicker noise. Optimizing the interface oxide thickness offers the flexibility of increasing the gain without degrading the early voltage while minimizing the impact on noise, breakdown, and fT. After depositing a 200-nm polysilicon film over the entire surface, the npn emitters are implanted with arsenic, followed by an anneal step, and the pnp emitters with boron or BF2. The emitter polysilicon is patterned over both transistors.

CMOS Module The CMOS gate-polysilicon, npn base, pnp base, zero-TCR polysilicon resistor, and capacitor plates are patterned simultaneously with focus on controlling the CMOS polysilicon gate-length (LPOLY). A lightly doped drain (LDD) is implanted in NMOS, primarily to ensure adequate channel hot-electron reliability. A nitride film is then deposited, patterned, and directionally etched to form polysilicon-gate sidewall spacers, and also to block silicidation when patterned over selected regions, such as polysilicon resistors. This is followed by conventional masking and implant steps to dope source, drain, gate, and well contacts. The source/drain implants are also introduced into the bipolar base contact regions. Controlling the proximity of base contacts to the corresponding emitters is a critical tradeoff between extrinsic base resistance, VA and transistor breakdown. At close proximity, interactions between dopants can seriously impact the emitter and base profiles in the active region, as also predicted by simulations [28]. The structures are then subjected to a final high-temperature rapid-thermal anneal (RTA). This final anneal is the only high-temperature cycle that the pnp emitter is subjected to.

© 2006 by Taylor & Francis Group, LLC

3.11-361

Industry Examples at the State-of-the-Art: Texas Instruments

Capacitors Precision, MIM A schematic cross-section of the metal–insulator–metal (MIM) capacitor is shown in Figure 3.11.2. The capacitor dielectric is oxide (0.7 fF/mm2) or nitride (2 fF/mm2), depending on application. The dielectric is deposited on silicided polysilicon that acts as the bottom capacitor plate, and then covered by a titanium nitride film that, after patterning, serves as the top capacitor plate. Both plates exhibit metallic behavior. The deposition conditions of oxide dielectric and its interfaces with TiN and CoSi2 are optimized to reduce the trap density within the dielectric and its interfaces, reducing transient shifts in capacitance, an effect that is also known as ‘‘dielectric absorption’’ [29]. Stacked Capacitor A high-density capacitor is formed by stacking the MIM capacitor described in the previous section on a capacitor formed between polysilicon and sinker, whereby the gate oxide acts as the dielectric (Figure 3.11.3). While the voltage coefficient of such a stack is very high compared to that of the MIM capacitor, the capacitance density is increased to near 4.5 fF/mm2 without adding process complexity. Another advantage of the structure is the full isolation of the bottom plate (sinker, well, and buried layer), reducing the parasitic capacitance. When optimizing the sinker profile, it is important to consider the enhanced oxidation rate and oxide integrity as the sinker surface concentration is increased. With this

Capacitor dielectric

TiN, top capacitor plate

Cobalt silicide

Polysilicon

STI

BOX

Support wafer

FIGURE 3.11.2

Illustration of a precision TiN–oxide–polycide capacitor.

Metal

Contact

Gate oxide

Deposited oxide or nitride

TiN (plate 1)

CMOS gate poly (common plate)

STI

STI

N- or P-sinker (plate 2)

DT

DT NBL or PBL Box

Support wafer

FIGURE 3.11.3 Schematic cross-section of the stacked capacitor.

© 2006 by Taylor & Francis Group, LLC

STI

3.11-362

The Silicon Heterostructure Handbook

Oxide

Contacting pad Metal 2 NiCrAl thin flim

VIAI

Metal 1 Silicide

BPSG

Contact

FIGURE 3.11.4

Illustration of thin-film resistor placement. The TFR can also be placed on a planarized surface.

respect, a p-type sinker typically exhibits less enhanced oxidation rate than an n-type sinker, however, at the cost of increased series resistance.

Resistors Three types of precision resistors with sheet resistance ranging from 50 to 320 Ohm/square are available: Polysilicon resistors that are defined during emitter polysilicon patterning, a ‘‘medium-sheet’’ polysilicon resistor tailored to near-zero TCR, and a trimmable thin-film resistor (TFR). Polysilicon Resistors Precision resistors are formed by selectively blocking silicidation of polysilicon. The CMOS polysilicon gate is tailored by selective implantation to 100 Ohm/square and near-zero TCR. The npn and pnp emitter polysilicon films are also utilized to define resistors of near 300 Ohm/square sheet resistance. Silicidation is blocked by patterning the ‘‘sidewall nitride,’’ leaving a patterned nitride film over resistor areas after the directional sidewall etch. Thin-Film Resistor A precision thin-film resistor (TFR) of near 50 Ohm/square is integrated during metallization. The metal modules are standard back-end of the line processes. A laser-trimmable TFR is formed in two masking steps by first depositing an interlevel oxide film, depositing and patterning a thin NiCrAl film, and then patterning contacting pads to the TFR, as shown in Figure 3.11.4.

3.11.3

Components and their Characteristics

The components are optimized for 5 V applications. Their key characteristics are summarized in this section.

Bipolars Bipolar transistors are optimized for 5 V, low base resistance, and high b*VA products while maximizing fT. Key bipolar parameters are given in Table 3.11.2. npn and pnp fT plots are shown in Figure 3.11.5 and Figure 3.11.6. The main contributor to the increase in fT is the reduced base width. Decreasing the IFO thickness considerably suppresses noise, as shown in Figure 3.11.7 where a reduction in flicker noise by approximately one order of magnitude can be seen [30, 31].

© 2006 by Taylor & Francis Group, LLC

3.11-363

Industry Examples at the State-of-the-Art: Texas Instruments TABLE 3.11.2

Nominal npn and pnp Characteristics, AE ¼ 0.4 0.8 mm2 (258C)

Parameter

Unit

npn

pnp

b VA fTmax (VCE ¼ 5 V) fmax (VCE ¼ 3 V) NFmin BVCEO BVCBO BVEBO

V GHz GHz dB V V V

200 95 27 90 0.7 6.0 13 3.5

140 200 27 60 0.9 6.0 13 3.0

30 25

npn 2

f T (GHz)

20

4

3

Vce = 5 V

1

15 10 5 0 100

10,000

1000 JC

(µA/µm2)

FIGURE 3.11.5 npn fT for Vce ¼ 1 to 5 V. AE ¼ 0.4 0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized process.

30 25

pnp 2

f T (GHz)

20

3

4

Vce = 5 V

1

15 10 5 0 100

1000

10,000

Jc (µA/µm2)

FIGURE 3.11.6 process.

pnp fT for Vce ¼ 1 to 5 V. AE ¼ 0.4 0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized

© 2006 by Taylor & Francis Group, LLC

3.11-364

The Silicon Heterostructure Handbook

CMOS Table 3.11.3 summarizes the CMOS parameters. The values are shown for 5 and 3.3 V with reduced channel length. The CMOS performance meets or exceeds stand-alone 5 V CMOS processes, indicating that performance was not significantly sacrificed during integration into a BiCMOS flow.

Capacitors The MIM capacitor is formed between TiN and polysilicon-silicide, both exhibiting metallic characteristics. Key capacitor parameters are given in Table 3.11.4. One important property of precision capacitors is the transient drift caused by traps within the dielectric and at its interfaces. This effect manifests itself as a partial recovery of voltage across the capacitor when the terminals are instantaneously shortened. This drift causes errors in analog applications that are based on charging and discharging capacitors, such as sample-and-hold circuits [29]. Silicon dioxide exhibits lower VCC and dielectric absorption (voltage recovery <50 ppm) than silicon nitride, indicating a lower trap density in SiO2. The stack capacitor is partially formed over an n-sinker surface and hence exhibits higher VCC than the MIM capacitor.

Resistors Three types of precision resistors are available: a thin NiCrAl resistor (TFR), polysilicon resistors that are defined during emitter polysilicon patterning, and a medium-sheet resistor tailored to near-zero TCR. Some properties of the thin-film and polysilicon resistors are given in Table 3.11.5.

TABLE 3.11.3

Nominal CMOS Characteristics (258C)

Parameter

Unit

Drawn L Linear VT IDSAT Max Isub BVDSS Off current

mm V mA/mm mA/mm V pA/mm

TABLE 3.11.4

Capacitor Characteristics (258C)

NMOS, 5 V

NMOS, 3.3 V

PMOS, 5 V

PMOS, 3.3 V

0.6 0.75 520 2.0 12 <1

0.5 0.75 590 0.05 12 <1

0.5 0.80 290 0.08 9 <10

0.45 0.80 300 0.0004 12 <10

Type Dielectric thickness Capacitance per unit area Capacitance to support wafer Linear VCC, 1 MHz Quadratic VCC, 1 MHz Linear TCC Quadratic TCC Dielectric BV at 0.1 nA/mm2 Dielectric absorption, k

TABLE 3.11.5

MIM, SiO2

MIM, Si3N4

Stack SiO2/Si3N4

50 0.70 0.04 4 0.6 10 0.03 >40 <50

30 2.0 0.04 90 50 60 25 >40 1400

30/14 4.5 0.04 3500 500 — — >10 —

Unit nm fF/mm2 fF/mm2 ppm/V ppm/V2 ppm/8C ppm/8C2 V ppm

Resistor Characteristics (258C)

Type Sheet resistance Linear TCC Quadratic TCC

© 2006 by Taylor & Francis Group, LLC

TFR

PPOLY

NPOLY

48 25 0

320 40 0.8

100 100 0.6

Unit Ohm/square ppm/8C ppm/8C2

3.11-365

Industry Examples at the State-of-the-Art: Texas Instruments

10−19

S IB (A2/Hz)

10−20 NPN, ref. 23

10−21

NPN, optimized 10−22 10−23 ~1/f

10−24 10−25 100

FIGURE 3.11.7 reduces noise.

101

103 102 Frequency (Hz)

104

105

Flicker noise comparison of two IFO thicknesses. Decreasing the IFO thickness considerably

Hot spot

Emitter

Deep trench

Top silicon

Buried layer

Box

Heat-flow path

FIGURE 3.11.8 Simplified model to estimate thermal resistance.

Thermal Resistance Figure 3.11.8 is a schematic of the bipolar structure illustrating the major heat dissipation paths. Because the thermal conductance is considerably lower in silicon dioxide than in single-crystal silicon (0.014 W/ cm-K in SiO2 versus 1.47 W/cm-K in Si), the effective thermal resistance is strongly affected by the BOX thickness. The insulator film compositions above the structure limit the heat dissipation upward and toward bond-pads. Lateral heat dissipation is limited by the effective deep trench thickness and sidewall area, and balanced by heat transfer from adjacent structures. A simplified analytical spreading resistance model is developed to approximate the effective thermal resistance for DC conditions. The assumption is made that most of the heat dissipation occurs toward the support wafer of infinite dimensions compared to the size of the structure. The model predicts a reduction in thermal resistance by approximately 50% as the BOX thickness is decreased from 0.4 to 0.145 mm. More accurate 2D thermal simulations are in progress. The impact of reduced BOX thickness on self-heating is experimentally observed by tracing the base– emitter forward voltage as a function of collector reverse voltage for a fixed base current (Figure 3.11.9).

© 2006 by Taylor & Francis Group, LLC

3.11-366

The Silicon Heterostructure Handbook

0.88 0.87

Bulk

0.86

Box: 0.145 µm

V be (V)

0.85 0.84

Box: 0.4 µm

0.83 0.82 0.81 0.80 0.79 0.78 0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Vce (V)

FIGURE 3.11.9 Measurement of Vbe versus Vce at constant collector current showing the impact of BOX thickness on self-heating.

The drop of Vbe with increased power dissipation is a measure of self-heating. An appreciable reduction in self-heating is found when the BOX thickness is reduced from 0.4 to 0.145 mm. Thermal resistance and self-heating are also important considerations for CMOS, passive components, and temperature increase in adjacent structures.

3.11.4

Circuit Application

The process has been used to fabricate a prototype voltage feedback amplifier with characteristics summarized in Table 3.11.6 [32]. A simplified amplifier schematic is shown in Figure 3.11.10. This is a class AB-folded cascode input stage to achieve higher slew rate (lower distortion at higher frequencies) and class AB diamond driver output stage. The improved pnp and npn cutoff frequencies and reduced base resistance and parasitic capacitances increase the frequency of the nondominant poles, allowing a higher small-signal bandwidth (2500 MHz versus 1000 MHz for JI process). The complementary SiGe bipolar technology allows symmetrical architectures with very low distortion. A third-order intermodulation distortion (IMD3) of better than 100 dBc at 60 MHz, 90 dBc at 100 MHz, and 72 dBc at 300 MHz is achieved. These results stem from the complementary SiGe bipolar and the reduction in parasitic capacitances, especially at the high-impedance node of the circuit. Furthermore, the smaller base resistance of the fully dielectrically isolated transistors results in a lower equivalent input noise voltage. Another voltage feedback amplifier implemented on this technology is designed for low noise and included a class AB biased input stage. We p achieved 0.1 dB gain flatness of 500 MHz with an input referred noise of only 1 nV/ Hz in a gain of two. With this process, a unity gain stable general purpose amplifier with 2.6 GHz of bandwidth is achieved for the first time. Such general purpose amplifiers can be used for RF/IF applications with much less power consumption (due to class AB operation) and more flexible external gain setting than currently used class-A RF amplifiers.

3.11.5

Summary

A fully oxide-isolated 5 V complementary-SiGe BiCMOS technology with MIM capacitors and thin-film resistors has been developed for ultrahigh-speed analog applications. The technology provides high

© 2006 by Taylor & Francis Group, LLC

3.11-367

Industry Examples at the State-of-the-Art: Texas Instruments TABLE 3.11.6

Voltage Feedback Amplifier Characteristics

Parameter

Measured

Small-signal bandwidth Gain setting Noise IMD3* at 100 MHz IMD3 at 300MHz

2300 MHz Gain of 5 p 1.9 nV/ Hz 90dBc 72dBc

*IMD3: Third order intermodulation distortion.

VBIAS INP

OUT INN

Class AB Input stage

FIGURE 3.11.10

Folded cascode

Class AB output stage

Voltage feedback amplifier topology.

b*VA and fT*BVCEO npn and pnp transistors with well-matched characteristics. Passive components of very low voltage and temperature coefficients are realized. This process has been used to build an extremely fast voltage feedback amplifier and is now in production for high-speed analog circuits. It is modularly extendable to higher performance or higher voltage applications. By optimizing the npn and pnp emitter interfaces and base profiles in a complementary 5 V SiGe BiCMOS process, a nominal fT of 27 GHz is achieved for both transistors, and the npn noise is reduced by one order of magnitude. In addition, thinning down the SOI BOX thickness reduces the thermal resistance and self-heating, further improving bipolar parameters. Finally, the reduction in dielectric trap density and hence dielectric absorption in precision capacitors extends the applicability of the process.

Acknowledgments We thank the Freising manufacturing, engineering, characterization, and management teams and the Dallas characterization and modeling teams for their relentless support in completing this project.

References 1. JMC Stork, GL Patton, DL Harame, BS Meyerson, SS IYER, E Ganin, and EF Crabbe. SiGe heterojunction bipolar transistors. Symposium on VLSI Technology, Kyoto 1989, pp. 1–4.

© 2006 by Taylor & Francis Group, LLC

3.11-368

The Silicon Heterostructure Handbook

2. TC Chen, E Ganin, H Stork, B Meyerson, JD Cressler, J Warnock, DL Harame, G Patton, GP Li, CT Chuang, and TH Ning. Submicrometer Si and Si–Ge epitaxial-base double-poly self-aligned bipolar transistors. IEEE Trans. Elect. Dev. 38: 941–943, 1991. 3. E Crabbe, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 4. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 79–81. 5. D L Harame, JH Comfort, JD Cressler, EF Crabbe, JYC Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors—Part I: materials, physics and circuits. IEEE Trans. Elect. Dev. 42: 455– 468, 1995. 6. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JYC Sun, G Scilla, J. Warnock, BJ Ginsberg, K Jenkins, KY Toh, DL Harame, and SR Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300. 7. TF Meister, H Schaefer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, M Stolz, S Boguth, and J Boeck. SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 739–742. 8. A Schueppen, U Erben, A Gruhle, H Kibbel, H Schumacher, and U Koening. Enhanced SiGe heterojunction bipolar transistors with 160 GHz–fmax. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 743–746. 9. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Trans. Microwave Theory Tech. 46: 572–589, 1998. 10. M Kondo, K Oda, E Ohue, H Shimamoto, M Tanabe, T Onai, and K Washio. Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems. IEEE Trans. Elect. Dev. 45: 1287–1294, 1998. 11. FS Johnson, J Ai, S Dunn, B El-Kareh, J Erdeljac, S John, K Benaissa, A Bellaour, B Benna, L Hodgson, G Hoffleisch, L Hutter, M Jaumann, R Jumpertz, M mercer, M Nair, J Seitchik, C Shen, M Schiekofer, T Scharnagl, K Schimpf, U Schulz, B Staufer, L Stroth, D Tatman, M Thompson, B Williams, and K Violette. A highly manufacturable 0.25 mm RF technology utilizing a unique SiGe integration. Proceedings of the 1997 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 56–60. 12. J Boeck, H Schaefer, H Knapp, D Zoeschg, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, R Stengl, and TF Meister. Sub 5 ps SiGe bipolar technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 763–766. 13. JS Rieh, B Jaganathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 14. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. Technical Digest of the IEEE GaAs, 2003, pp. 183–186. 15. BA Orner, QZ Liu, B Rainey, A Stricker, P Geis, P gray, M Zierak, M Gordon, D Collins, V Ramachandran, W Hodge, C Willets, A Joseph, J Dunn, JS Rieh, SJ Jeng, E Eld, G Freeman, and D Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fmax) SiGe HBT. Proceedings of the 2003 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 203–206. 16. LD Lanzerotti, A St Amour, CW Liu, and JC Sturm. Si/Si1–x–y/Gex/Cy heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 930–932. 17. HJ Osten, D Knoll, B Heinemann, H Ruecker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the 1999 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 109–116.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Texas Instruments

3.11-369

18. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillak, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 19. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base PNP transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 20. J Warnock, PF Lu, JD Cressler, KA Jenkins, and JYC Sun. 35 GHz/35 PSEC ECL PNP technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 301–304. 21. D Nguyen-Ngoc, DL Harame, JN Burghartz, RC McIntosh, EF Crabbe, JD Warnock, CL Stanis, BS Meyerson, JM Cotte, and JH Comfort. Ion-implanted base SiGe PNP self-aligned SEEW transistors. Proceedings of the 1991 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 75–78. 22. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Grego, U Haak, W Hoeppner, D Knoll, R Kurps, S Marshmeyer, S Orlowski, H Ruecker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 23. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M Waitschull, JW Weijtmans, and C Willis. Proceeding of the BCTM, Toulouse, 2003, pp. 211–214. 24. R Jerome, I Post, K Huffstatter, G Wodek, P Travnicek, and D Williams. The effect of trench processing conditions on complementary analog devices with SOI/trench isolation. Technical Digest of the IEEE Bipolar Circuits and Technology Meeting, 1993, pp. 41–44. 25. T-J King, JR Pfiester, and KC Saraswat. A variable-work-function polycrystalline–Si1–xGex gate material for submicron CMOS technologies. IEEE Electron Dev. Lett., EDL-12: 533, 1991. 26. EJ Prinz and JC Sturm. Analytical Modeling of current-gain — Early voltage products in Si/Si1–x / Gex/Si heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1991, pp. 853–856. 27. JW Slotboom, G Streutker, A Pruijmboom, and D Gravensteijn. Parasitic energy barriers in SiGe HBT’s. IEEE Trans. Elect. Dev. 12: 486–488, 1991. 28. S Denorme, D Mathiot, P Dollfus, and M Mouis. Two-dimensional modeling of the enhanced diffusion in thin base n-p-n bipolar transistors after lateral ion implantation. IEEE Trans. Elect. Dev. 42: 523–527, 1995. 29. C Iorga, Compartmental analysis of dielectric absorption in capacitors. IEEE Trans. Dielectric Electrical Insulation, 7: 187–192, 2000. 30. JD Cressler, E. Zhao, Georgia Institute of Technology, joint project with Texas Instruments. To be published. 31. F Hou, Texas Instruments, Dallas. Private communication. 32. K Hayat-Dawoodi, Texas Instruments, Dallas. Private Communication.

© 2006 by Taylor & Francis Group, LLC

3.12 Industry Examples at the State-of-the-Art: Philips 3.12.1 3.12.2

Introduction........................................................... 3.12-371 Historical Background .......................................... 3.12-371 SiGe Pioneering Phase . QUBiC1 through QUBiC4

3.12.3

SiGe in Manufacturing — QUBiC4G ................. 3.12-373 Process Integration . Electrical Results . HBT Models . Circuit Results

Roy Colclaser and Peter Deixler Philips Semiconductors

3.12.4

Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X .......................................... 3.12-378 Process Integration . Electrical Results

3.12.5

Summary ................................................................ 3.12-384

3.12.1 Introduction Significant increases in the operating frequency range of silicon semiconductor devices over the past decade have made low-cost electronic equipment available to the consumers at spectacular performance levels. The development of techniques to make silicon-based heterojunction bipolar transistors (HBTs) using SiGe and, later, SiGe:C, was responsible for great strides forward in bipolar transistor performance. An important way to use HBTs is to combine them with high-performance CMOS and well-characterized passive components in monolithic integrated circuit processes designated BiCMOS. Philips has manufactured RF BiCMOS products in the QUBiC family since 1989. SiGe HBTs were added to the process in 2002 and SiGe:C HBTs were added in 2004.

3.12.2 Historical Background Philips Electronics is one of the very few manufacturing companies that made the transition from the vacuum tube era to the semiconductor integrated circuits era in the 1960s. Philips Research Laboratories in Eindhoven, the Netherlands, and, more recently, Leuven, Belgium, have made major contributions to the fundamental understanding of semiconductor materials and device physics. Philips Semiconductors manufactures a variety of integrated circuits using bipolar, MOS, and BiCMOS processes. Radio frequency integrated circuits are a major interest at Philips, and SiGe has become an important area for development.

SiGe Pioneering Phase Within Philips, the task of exploring new and exciting fabrication processes and device structures was assigned to Philips Research Laboratories. From 1988 to 2000, process modules were developed using 3.12-371 © 2006 by Taylor & Francis Group, LLC

3.12-372

The Silicon Heterostructure Handbook

low-temperature atmospheric and reduced pressure single-wafer epitaxial reactors for both selective and nonselective (differential) epitaxy of SiGe [1–4]. Selective epitaxy deposits as monocrystalline over exposed areas of single-crystal substrates and does not deposit over dielectric regions. Differential epitaxy is monocrystalline over exposed areas of single-crystal substrates and polycrystalline over dielectrics and polycrystalline regions. A team of device architects and process integration specialists worked with device physics experts to develop early versions of HBTs based on molecular beam epitaxy, and both selective and nonselective epitaxial growth [5–10]. Outstanding performance in SiGe HBTs was presented at IEDM in 1995 [7]. In parallel, the model development group extended the MEXTRAM bipolar model to include the parameters necessary to describe SiGe HBTs [11–13].

QUBiC1 through QUBiC4 During the same time span, project teams within Philips Semiconductors developed the QUBiC family of processes for the manufacture of silicon BiCMOS integrated circuits [14–17]. This process family is bipolar based with buried n-type and buried p-type layers, vertical npn and lateral pnp transistors, a selection of monocrystalline and polycrystalline silicon resistors, a variety of capacitor types (including metal–insulator–metal, [MIM], in QUBiC4), varicaps, inductors, and compatibility with a corresponding standard family of CMOS from the Philips roadmap. Key characteristics of the basic silicon QUBiC family are summarized in Table 3.12.1. The QUBiC4 [17] process evolved from the previous generations. QUBiC1 [14] utilizes fully recessed LOCOS, a single poly bipolar transistor, and three layers of metal. QUBiC2 [15] uses a modified LOCOS, a single poly bipolar transistor, and three layers of metal. The architecture of QUBiC3 [16] is a major change, using conventional LOCOS, separating CMOS and bipolar processing, adding a thick, fourth layer of metal for inductors, and introducing a double poly bipolar transistor with L-shaped oxide or nitride spacers to define the width of the emitter. The base in this device is implanted before the spacers are formed, and the emitter is diffused from polycrystalline silicon that is implanted with arsenic. The major changes for QUBiC4 are associated with isolation. The 0.25 mm CMOS process uses shallowtrench isolation (STI), and this is combined with deep-trench isolation (DTI) to reduce the parasitic capacitances and improve the RF isolation. The npn transistor is modified to use in situ arsenic-doped polycrystalline silicon. A 3 mm thick fifth layer of metal is added to the process to improve the inductors and provide more flexibility for interconnect. The features of this process include a variety of polycrystalline and monocrystalline silicon resistors with sheet resistances ranging from 25 to 2000 ohms/sq., poly–mono capacitors, poly–poly capacitors, and metal–insulator–metal capacitors, lateral pnp bipolar transistors, and varactors using either junctions or MOS capacitors.

TABLE 3.12.1 The QUBiC Family of Silicon BiCMOS Manufacturing Technologies Technology

QUBiC1

QUBiC2

QUBiC3

QUBiC4

Lithography (mm) npn fT (GHz) npn fmax (GHz) Substrate isolation CMOS Leff (mm) Metal layers

1.0 13

0.7 20

Fully recessed LOCOS 0.78 3

Partly recessed LOCOS 0.70 3

0.5 30 60 LOCOS 0.42 4

0.25 37 90 STI/DTI 0.14 5/6

Source : From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE. With permission.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Philips

3.12-373

3.12.3 SiGe in Manufacturing — QUBiC4G The development of QUBiC4 was well under way when it was decided to introduce a silicon–germanium heterojunction bipolar npn transistor (SiGeHBT) with QUBiC4 as a starting platform. A crossfunctional team was assembled from the research laboratories, product groups, and the manufacturing facilities to implement this development. We were able to reuse much of the work that had already been completed for QUBiC4 in the new project, which was designated QUBiC4G [18]. Many of the process modules could be transferred in total from QUBiC4, a few of the modules required small modifications, and some modules had to be developed specifically for the new process. We selected an architecture that enabled the use of the same set of design rules and layouts for essentially all the important devices, which meant that the databases for mask generation for the large arrays of test structures did not have to be altered. We were able to use algorithms to generate the mask layers in QUBiC4G that were different from those used for QUBiC4 without having to redesign the test structures. In fact, we are able to use the same physical masks for many of the layers, allowing us to mix QUBiC4 and QUBiC4G designs on the same multiproject tape-outs. This is a very cost-effective way to evaluate new test structures at the same time as new product designs. All the outstanding passive components that had been developed for QUBiC4 were easily transferred to QUBiC4G. The only major difference in design rules was due to a request from the design community to increase the thickness of the fourth metal layer from 1 to 2 mm so that lowresistivity orthogonal transmission lines could be implemented in the process.

Process Integration After formation of both n- and p-type buried layers beneath the thin collector epitaxial layer, we apply STI and DTI to significantly reduce the parasitic capacitance. We then complete the standard CMOS integration. The windows defining the active bipolar areas are etched, followed by the implanting of the subcollector doping profile. The high breakdown voltage device is obtained by selectively masking some of the collector implants. Extensive process and device simulations were used to guide the collector and base profile optimization and reduce the number of development cycles. The subcollector implants in QUBiC4 are self-aligned to the emitter opening. In QUBiC4G, we chose to do the subcollector implants before deposition of the base SiGe layer due to the possibility of implant damage to the base layer. At this point, in the process, the base layer of the HBT is deposited using reduced-pressure lowtemperature nonselective epitaxial growth in an ASM CVD reactor. The highly doped boron layer is embedded in a stepped germanium profile without intentional grading [10]. The base layer is monocrystalline over the exposed single-crystal silicon and polycrystalline over the regions that were covered with various dielectric materials. In QUBiC4, the boron-doped base region is implanted into the collector epitaxial layer through an opening in the base polycrystalline silicon and is self-aligned to the opening for the formation of the emitter. In QUBiC4G, the boron-doped portion of the base layer extends across the entire extent of the base, allowing for the formation of low resistance contacts to the extrinsic base region. The emitter in QUBiC4G is formed using a different procedure from QUBiC4 as well. A dielectric layer is deposited over the base layer and patterned, using deep-ultraviolet lithography and an advanced overlay feedback system. This layer serves as an etch stop during the reactive ion etching for the emitter opening to prevent etch damage to the base layer. At this point in the process, we form a similar type of double poly structure with L-shaped inside spacers as in QUBiC4 [16, 17]. The technology features in situ arsenic-doped polycrystalline silicon emitters. The mesa-like topography of the HBT structure (Figure 3.12.1) ensures that the silicide of the base poly and the intrinsic SiGe base are laterally at the same level. Combined with tight alignment, this guarantees that the etch-stop layer does not block the shortest current path from the active base via the highly boron-doped SiGe layer to the silicide of the base electrode. This results in a low base-link resistance and, therefore, low noise figure and high fmax.

© 2006 by Taylor & Francis Group, LLC

3.12-374

The Silicon Heterostructure Handbook

FIGURE 3.12.1 The SiGe-HBT combines robust nonselective epitaxial growth with a double-poly structure and deep- and shallow-trench isolation for high performance in a process based on 0.25 mm lithography. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The PMOS source–drain extensions are implanted just before the emitter drive-in anneal. This avoids PMOS degradation during the hydrogen bake cycle before the SiGe layer deposition. The NMOS characteristics are not affected by the limited bipolar thermal cycles due to the SiGe layer deposition and the in situ doped emitter polycrystalline silicon. A tungsten liner is used under each of the first three aluminum–copper layers to enhance the electromigration performance of the interconnect structures. This liner is necessary because of the higher current densities associated with peak fT for the HBT as compared to the npn device in the QUBiC4 process. The top two aluminum–copper metal layers are 2- and 3-mm thick, respectively. These low-resistance interconnect layers facilitate the fabrication of high quality-factor inductors and orthogonal transmission lines. A high-density metal–insulator–metal capacitor is located between the top two metal layers. The back-end structures are planarized using chemical–mechanical polishing and highdensity plasma dielectric layers.

Electrical Results Defining optimum performance parameters for a BiCMOS process is not a straightforward task. The art of device design is an exercise in compromise. A particular parameter may be dominant in one circuit application and superfluous in another. We worked closely with our product design teams to tailor the HBT performance to satisfy the needs for their applications. For instance, there are different requirements for HBTs that are optimized for current mode logic as compared to those optimized for analog RF power amplifiers.

© 2006 by Taylor & Francis Group, LLC

3.12-375

Industry Examples at the State-of-the-Art: Philips

1⫻100

250

1⫻10−2

200

hFE

150

1⫻10−6 100

1⫻10−8

50

1⫻10−10

Aem = 0.3⫻20.1 µm2

1⫻10−12

0 0.4

(a)

0.6 0.8 VBE (V)

1.0

IC,IB (A)

1⫻10−1

1⫻10−4 IC,IB (A)

1⫻101

1⫻10−3 1⫻10−5 Aem = 1000⫻0.3⫻0.9 µm2

1⫻10−7 0.4 (b)

0.6 0.8 VBE (V)

FIGURE 3.12.2 (a) Gummel plot of a standard HBT with Aem ¼ 0.3 20.1 mm2 (symbols are measured data and solid lines are simulated using a Mextram model) and (b) Gummel plot of an array of 1000 standard HBTs with Aem ¼ 0.3 0.9 mm2. Both the individual device and the array have near-ideal slopes for the base and collector currents. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The Gummel plots in Figure 3.12.2 show a comparison of a 0.3 20.1 mm2 standard HBT to a typical multiemitter array with 1000 0.3 0.9 mm2 transistors in parallel. Both the collector currents and base currents are near-ideal down to low base–emitter biases. The output characteristics shown in Figure 3.12.3 exhibit very high Early voltages (>200 V). The standard HBT has a BVCEO of 2.7 V when measured at VBE ¼ 0.65 V, well within the ideal base current regime and before the onset of high injection effects. BVCEO is maintained above the 2.5 V supply voltage set by the digital CMOS logic. The resulting unconditional circuit stability enables circuit design without concerns about breakdown phenomena during power supply transients. The technology also offers HV npn HBTs with a 3.9 V BVCEO for circuit applications where an increased power supply voltage is required. This device type has excellent RF characteristics with fT of 50 GHz and fmax of 110 GHz and complements the standard device with fT of 70 GHz and fmax of 100 GHz. The RF results are shown in Figure 3.12.4 and Figure 3.12.5. The measured RF characteristics have near-ideal slopes and high power gains. The fmax values are derived by extrapolation from the measured slopes, which, due to the low CCS and high Rsub, are observed to be always near 20 dB/decade. The minimum-sized HBT (Aem ¼ 0.25 mm2) draws less than 0.6 mA collector current at peak fT ¼ 70 GHz (as shown in Figure 3.12.4). On this small device, the deep-trench substrate isolation scheme with the low doping level in the substrate reduces the collector–substrate capacitance to less than 2 fF. As seen from Figure 3.12.3, even the deep-trench isolated HBTs biased near peak fT do not show significant self-heating effects. Basing the process integration on the proven QUBiC4 integration scheme allowed us to preserve characteristics of the 0.25 mm CMOS in QUBiC4G. With only minor implant adjustments, all the QUBiC4G CMOS parameters are closely matched to the parent CMOS technology. This ensures full compatibility with the standard CMOS library. The full suite of passive elements was also carried over from QUBiC4 [17]. The MIM capacitor from this process has a 5 fF/mm2 density based on a Ta2O5 dielectric layer. Only one masking step is added for this component. Two polycrystalline silicon capacitors types are also available. Five resistor types are included in the component list. Other features include varactor diodes, a lateral pnp transistor, and RFCMOS. Spiral inductors with quality factors above 20 at 20 GHz can be fabricated in the 3-mm thick top metal layer. Multilayer inductors using the top two metal layers can also be designed.

© 2006 by Taylor & Francis Group, LLC

3.12-376

The Silicon Heterostructure Handbook

60 50

∆IB = 40 nA

IC (µA)

40 30 20 10 IB = 40 nA 0 (a)

0

0.5

1

1.5

2

2.5

VCE (V) 30

IC (µA)

20 ∆IB = ⫻2

10

IB = 25 µA

0 (b)

0

0.5

1

1.5

2

2.5

VCE (V)

FIGURE 3.12.3 Output characteristics for the standard HBT (Aem ¼ 0.3 20.1 mm2) at T ¼ 258C biased at low power (a) and near peak fT (b). BVCEO is 2.7 V and VA exceeds 200 V. The solid lines are from Mextram 504 model simulations. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

Independent high-performance transmission lines can be realized using the two thick top metal layers. This enables the formation of transmission line grids such as those required for the cross-point switch matrix in one of our first products [18, 20].

HBT Models By the time the actual development of the QUBiC4G technology was started, there was already a product group ready to start designing. We provided the initial models for the project by doing a process

© 2006 by Taylor & Francis Group, LLC

3.12-377

Industry Examples at the State-of-the-Art: Philips

80 70

f T [GHz]

60

Std-HBT, BVceo = 2.7 V HV-HBT, BVceo = 3.9 V

50 40 30 20 10 0 0.01

Aem = 0.3⫻20 µm2 VCB = 1 V 0.1

1

10

Jc (mA/µm2)

FIGURE 3.12.4 Transition frequency as a function of collector current density for the standard and high-voltage HBTs (effective emitter width is 0.3 mm). (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

simulation using TSUPREM4 with the USIT applications module and a device simulation using MEDICI with the HBT module [19]. The first set of Mextram [13] models was made available by placing the QUBiC4G intrinsic transistor in a framework based on measurements of the extrinsic parameters of QUBiC4 transistors. These models were sufficient for the designers to get started, and the first models based on measurements of QUBiC4G material were available before the design was taped out for mask making. The first models were used for circuit prototyping, providing valuable input for the HBT development. In Figure 3.12.2 and Figure 3.12.3, the excellent agreement between electrical measurements and the silicon-based scalable Mextram 504 simulations is demonstrated.

Circuit Results 12.5 Gb/sec Asynchronous Cross-Point Switch The first product designed in QUBiC4G is a 20 20 cross-point switch [20] operating at 12.5 Gb/ sec with a peak-to-peak input swing of 100 mV and peak-to-peak output swing of 600 mV. This product has unicast, multicast, and broadcast switching capabilities used for routing data in optical networks. It utilizes the high-speed and low-noise performance of the inherently matched QUBiC4G technology to maintain highly symmetrical rise and fall times and to reduce jitter to less than 2 psec per switching operation. These switches can be cascaded without the need to insert clock–data recovery and retiming logic. The product operates from a 2.5 V supply and consumes less than 4 W. The die area is 36 mm2. LC-VCOs Fully integrated voltage-controlled oscillators based on varactors and spiral inductors have been fabricated in the QUBiC4G process. The measured output spectrum of a 20 GHz LC-VCO [21] is shown in Figure 3.12.6. The center frequency of this circuit is tunable from 19.8 to 22.7 GHz within a 3 V control range. A measured phase noise of 103 dB c/Hz at 2 MHz from the carrier frequency is achieved. A 35.2 to 37.6 GHz LC-VCO [22] has also been demonstrated.

© 2006 by Taylor & Francis Group, LLC

3.12-378

The Silicon Heterostructure Handbook

60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

Std-HBT Aem = 0.3⫻20.1

0 1⫻108

1⫻109

1⫻1010

1⫻1011

f (Hz)

(a)

60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

HV-HBT Aem = 0.3⫻20.1

0 1⫻108 (b)

1⫻109

1⫻1010

1⫻1011

f (Hz)

FIGURE 3.12.5 Measured AC-gains at VCB ¼ 1 V, biased at peak fT, as a function of frequency for (a) the standard HBT and (b) the high-voltage HBT. The fmax values of 100 GHz for the standard device and 110 GHz for the highvoltage device are derived by extrapolation with the measured slope. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

3.12.4 Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X The consumer-oriented microwave applications in the 8 to 30 GHz regime require even more RF capabilities than those provided by the QUBiC4G technology. Using the same basic QUBiC4 BiCMOS platform, we are able to substantially improve the RF performance by incorporating a vertically scaled, carbon-enhanced SiGe base, deposited with nonselective epitaxy. We have also replaced the polycrystalline silicon emitter by an epitaxially grown monocrystalline silicon emitter, with significantly lower emitter access resistance. The new process is called QUBiC4X [23]. This technology offers, on the same chip, npns optimized for either ultrahigh speed or high-voltage robustness. Both devices show near-ideal device characteristics combined with excellent RF and low power performance. We also offer a process derivative for power and analog application, featuring dedicated very-high breakdown SiGe:C power transistors.

© 2006 by Taylor & Francis Group, LLC

3.12-379

Industry Examples at the State-of-the-Art: Philips

10: 33: 14 JUL 17, 2002 hp REF −10 . 0 dB m

MKR 19.832233 GHz −19.30 dB m

# AT 0 dB

PEAK LOG 10 dB/

Center 19.832228 GHz

WA SB SC FS CORR

Center 19.832228 GHz #RES BW 30 KHz

#VBW 300 Hz

Span 2. 000 MHz SWP 667 msec

FIGURE 3.12.6 Measured output spectrum of a 20 GHz voltage-controlled oscillator at Vtune ¼ 0.5 V implemented in QUBiC4G. (From H Veenstra and E van der Heijden. A 19–23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE.)

We elected to stay with the same CMOS for this process development because it satisfies the needs of our product portfolio. The CMOS part of the process flow is relatively independent of the bipolar part, so it would be possible to migrate to more advanced CMOS in the future. We have added the capability to make depletion-mode MOS devices and isolated NMOS transistors to this process flow. RF-CMOS models have been added to the library. The on-chip passive components have also been enhanced for QUBiC4X and characterized over the anticipated frequency range. A SiCr thin-film resistor has been added in the back-end part of the flow and there are now seven silicon resistor styles. The titanium silicide has been replaced by cobalt silicide. New models have also been developed for the inductors [24].

Process Integration The QUBiC4X process is based on the established QUBiC4G technology described in the previous section. The significant process changes are associated with the npn HBT. Carbon has been added to the base layer. The carefully tailored carbon profile enables a thinner base with both a significantly higher boron and germanium content, while maintaining ideal base currents. Base resistance is minimized while ensuring sufficient current gain and good high-frequency noise. The extrinsic base is diffused from the boron-doped base polycrystalline silicon into the SiGe film. This procedure preserves HBT doping profile integrity and minimizes the extrinsic collector junction depth. The parasitic collector–base capacitance and the base-access resistance are both low as a result of this approach. The emitter structure, as in QUBiC4G, is based on L-shaped spacers. The upward expanding emitter electrode width [25] minimizes the emitter resistance on the smallest allowed geometries. This enables us to aggressively scale emitter sizes without any degradation in transition frequency. We have moved

© 2006 by Taylor & Francis Group, LLC

3.12-380

The Silicon Heterostructure Handbook

beyond emitters with amorphous silicon and epitaxially aligned polycrystalline silicon to a defect-free epitaxially grown arsenic-doped monocrystalline silicon emitter. This structure is shown in Figure 3.12.7. Optimized silane-based deposition chemistry, pressure, and temperature in the ASM Epsilon CVD reactor enable growth rates approaching the typical throughput of in situ arsenic-doped polycrystalline silicon emitters. By using an optimized clean in combination with a vacuum load lock, hightemperature hydrogen prebakes are not necessary. We use 0.18-mm lithography for the bipolar and CMOS steps that require tight overlay and line width manufacturing control. We decrease the minimum effective emitter stripe width and place dual rows of contacts at the collector and emitter to ensure reliable npn operation near peak transition frequency. The bipolar modules are combined with the CMOS steps in the same manner as QUBiC4G. The gate patterning and cobalt silicide modules from a 0.18 mm CMOS technology have been introduced. This results in a significant enhancement of the RF CMOS performance and tighter process control. The final rapid thermal anneal has been adjusted to a high-temperature spike to mitigate the traditional thermal budget mismatch between SiGe-HBTs and CMOS. We simultaneously achieve good MOS gate–source–drain activation, MOS transistor matching, minimized npn total base-resistance, and shallow or steep emitter diffusion, aided by the limited diffusivity of the arsenic in the monocrystalline silicon emitter.

FIGURE 3.12.7 The QUBiC4X HBT combines a nonselective epitaxial SiGe:C base, an epitaxially grown monocrystalline silicon emitter and a double-polycrystalline silicon structure for minimized parasitics and high performance. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-381

Industry Examples at the State-of-the-Art: Philips

The back-end integration is tailored to the specific needs of mixed-signal and radio frequency designs. It is based on the QUBiC4G technology, with three layers of thin aluminum–copper with tungsten under-liners and two layers of thick aluminum–copper. We have added a silicon–chromium thin-film resistor with low parasitic capacitance and excellent temperature stability.

Electrical Results The diverse portfolio of highly integrated RF and mixed-signal products demands considerable flexibility of BiCMOS technologies over a wide range of frequencies and voltages. We developed a balanced set of high-speed or high-voltage active devices and well-characterized passive components that will enable the designers to explore the considerable potential of SiGe:C BiCMOS technologies for monolithic microwave applications. A Gummel plot and output characteristics of a 0.15 20.1 mm2 standard SiGe:C npn HBT are shown in Figure 3.12.8. Both IC and IB are nearly ideal over several orders of magnitude of current while the Early voltage exceeds 50 V. The standard HBT has a collector–emitter breakdown voltage of 2.0 V, measured at VBE ¼ 0.65 V, which is well within the ideal base-current regime and before

1⫻100

IC,I B (A)

1⫻10−2 1⫻10−4 1⫻10−6 1⫻10−8 Aem = 0.15⫻20.1µm2

1⫻10−10 0.4

0.8

0.6

1.0

VBE (V)

(a)

IC, (mA)

1.0

0.5

∆/B =230nA

0.0 0 (b)

0.5

1 VCE (V)

1.5

2

FIGURE 3.12.8 The Gummel plot (a) and output characteristics (b) of a standard HBTwith Aem ¼ 0.15 20.1 mm2, showing near-ideal device characteristics. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-382

The Silicon Heterostructure Handbook

1

gm/(q.Ic/kT )

0.8

0.6

0.4 2 Monoemitter: RE = 2.5 Ω µm Polyemitter: RE = 20 Ω µm2

0.2

Identical collector architecture and grown SiGe:C base 0 1⫻10−4

1⫻10−3

1⫻10−2

Jc (A/µm2)

FIGURE 3.12.9 The epitaxially grown monocrystalline silicon emitter and optimized HBT doping profiles boost the transconductance to increase drive capability, especially near peak fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/ 140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

the onset of high injection effects. The epitaxially grown monocrystalline silicon emitter has an emitter resistivity of 2.5 ohm mm2. This provides a significant boost in the available transconductance per unit current (as shown in Figure 3.12.9). The transition frequency for the standard HBT is 131 GHz at a relatively low collector current density of 4.4 mA/mm2 (Figure 3.12.10). The maximum frequency of oscillation for this transistor exceeds 140 GHz. The RF minimum noise figure and associated gain are shown in Figure 3.12.11. These properties are useful for low-noise amplifiers operating at high frequencies. The output power specifications for many microwave applications require voltage swings in excess of 5 V, demanding devices with high breakdown voltages. Our technology offers a high-voltage HBT with BVCBO ¼ 13 V. The transition frequency for this device is 60 GHz at 1.1 mA/mm2 with BVCEO exceeding 3.2 V and fmax of 120 GHz. The combination of high-performance standard HBTs and high-voltage HBTs will enable the monolithic integration of high-speed circuitry and powerful antenna driver blocks. To successfully address some new applications [26] it is necessary to develop SiGe:C HBTs with even higher breakdown characteristics. We have demonstrated a customized very-high-breakdown version of QUBiC4X targeted for power amplifiers with 5 V power supplies and BiCMOS protection circuitry. The SiGe:C PA transistors have been optimized for high-temperature stability of transition frequency, minimized emitter–base capacitance for increased transition frequency at low currents and high collector–base breakdown voltages. The fT BVCEO and fT BVCBO products are outstanding and exceed 245 and 842 GHz V, respectively. We achieve 88% power-added efficiency with a 20 dB power gain at 1.8 GHz with 3.3 V supply voltage [27]. This combination of high-voltage ruggedness, device speed, and power performance, integrated in BiCMOS, illustrates the potential of silicon-based high-end power amplifiers. The characteristics of the SiGe:C HBT styles available in the QUBiC4X technologies are compared to those in QUBiC4 and QUBiC4G in Table 3.12.2.

© 2006 by Taylor & Francis Group, LLC

3.12-383

Industry Examples at the State-of-the-Art: Philips

160 Vbc = −0.5 V

140

Vbc = 0.0 V Vbc = 0.2 V

120

fT (GHz)

100

80

60

40

20

fT and fmax are derived by extrapolation from 50 GHz Aem = 0.15⫻20.3 µm2

0 0.0001

0.001 Jc (A/µm2)

0.01

2.5

2.5

2.0

2.0

1.5

1.5

1.0

1.0 NFMIN (dB) 0.5

0.5 0.0

Gass (dB)

Fmin (dB)

FIGURE 3.12.10 The transition frequency as a function of collector current density for the QUBiC4X standard HBT. Only VBE ¼ 0.81 V and IC ¼ 4 mA/mm2 are required to reach 130 GHz fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

Aem = 0.15⫻20.3 µm2 0

Gass (dB)

5 10 15 Frequency (GHz)

0.0 20

FIGURE 3.12.11 The NFMIN and associated gain for the QUBiC4X standard HBT is 0.4 dB at 2 GHz and 1.1 dB at 10 GHz. This is a result of the minimized parasitic capacitances and access resistances. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-384

The Silicon Heterostructure Handbook

TABLE 3.12.2 Electrical Results Obtained for the Standard HBT, the High-Voltage HBT and the Power Amp HBT (at Room Temperature for Aem ¼ 0.15 20.1 mm2) from the QUBiC4X Process Options [23] as Compared to the Standard and High-Voltage Devices from QUBiC4 [17] and QUBiC4G Parameters

QUBiC4 [17]

fT at VCB ¼ 0.5 fmax IC at peak fT hfe BVCEO BVCBO VA Rpinch REAE CCB/AE CCS/PCollector NFMIN at 2 GHz NFMIN at 10 GHz

QUBiC4G [18]

QUBiC4X [23]

Units

Std BT

HV BT

Std HBT

HV HBT

Std HBT

HV HBT

PA HBT

37 90 0.75 150 3.8 16 27 12 22 2.7 1.5

28 70 0.5 140 5.9 18 50 12 22 2.1 1.5

67 90 1.65 300 2.5 10.0 150 4 22 4.0 2.1

50 90 0.83 300 3.6 14.0 220 4 22 3.3 2.1

131 138 4.4 600 2.0 9.0 50 2.8 2.5 7.0 0.22 0.4 1.1

60 120 1.1 600 3.1 13.0 80 2.8 2.5 3.2 0.22

51 115 0.8 160 4.8 16.5 >250 3.2 20 3.0 0.22

GHz GHz mA/mm2 — V V V kohm/sq. ohm mm2 fF/mm2 fF/mm dB dB

Source : From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.

3.12.5

Summary

Philips has a long history in bipolar-based BiCMOS for RF applications. The QUBiC family has evolved through the years with a suite of well-characterized passive components that provide the designers with all they need to make fully integrated products for the consumer market. When a SiGe HBT replaced the silicon bipolar npn in QUBiC4G, a new frequency range was added to the process capabilities. The enhancement of this HBT by the addition of carbon to the HBT in QUBiC4X opens another set of applications to the silicon-based BiCMOS product arena. The remarkable improvements in SiGe:C HBTs make it possible to manufacture products at low cost that previously could only be made using III–V compound semiconductors. Modeling of both active and passive components had to keep pace with these developments in the technology, making it possible to supply the designers with the tools that are needed to make leading edge designs when the technologies are available.

Acknowledgments The authors acknowledge the teamwork within the Philips organization that made it possible for the development of the QUBiC family of process technologies and the incorporation of SiGe and SiGe:C HBTs in production. We thank the teams at Philips Research in Eindhoven and Leuven, Philips Semiconductors Technology Development in Sunnyvale, Albuquerque, Fishkill, San Jose, Nijmegen, Caen and Crolles, and Philips Semiconductors Product Design in Caen, Nijmegen, and San Jose, for all their efforts on these projects.

References 1. WB de Boer and DJ Meyer. Low-temperature chemical vapor deposition of epitaxial Si and SiGe layers at atmospheric pressure. Applied Physics Letters 58:1286–1288, 1991. 2. WB de Boer, D Terpstra, and JGM van Berkum. Selective versus non-selective growth of Si and SiGe. Materials Science and Engineering B 67:46–52, 1999.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Philips

3.12-385

3. WB de Boer and D Terpstra. Emissivity effects in low-temperature epitaxial growth of Si and SiGe. Proceedings ECS Spring Meeting, Seattle, 1999, pp. 309–318(99–10). 4. E Aksen, WB de Boer, and D Terpstra. Emissivity effects in differential epitaxial growth (DEG). Proceedings ECS Spring Meeting, Washington, 2001, Abstract No. 558(2001–1). 5. A Pruijmboom, JW Slotboom, DJ Gravesteijn, CW Fredriksz, AA van Gorkum, RA van de Heuvel, JML van Rooij-Mulder, G. Streutker, and GFA van de Walle. Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy. Electron Device Letters 12:357–359, 1991. 6. JW Slotboom, GFA Streutker, and A Pruijmboom. Parasitic energy barriers in SiGe HBTs. Electron Device Letters 12:486–488, 1991. 7. A Pruijmboom, D Terpstra, CE Timmering. WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, and JJEW Hageraats. Selective-epitaxial base technology with 14 ps ECL-gate delay, for low power wide-band communication systems. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 747–750. 8. RJE Hueting, JW Slotboom, A Pruijmboom, WB de Boer, CE Timmering, and NEB Cowern. On the optimization of SiGe-base bipolar transistors. IEEE Transactions on Electron Devices 43:1518–1524, 1996. 9. MS Peter, JW Slotboom, and D Terpstra. Impact ionization and neutral base recombination in SiGe HBTs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2000, pp. 126–129. 10. P Deixler, HGA Huizing, JJTM Donkers, JH Klootwijk, D Hartskeerl, WB de Boer, RJ Havens, R van der Toorn, JCJ Paasschens, WJ Kloosterman, JGM van Berkum, D Terpstra, and JW Slotboom. Explorations for high performance SiGe-heterojunction bipolar transistor integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 30–33. 11. JCJ Paasschens, WJ Kloosterman, and RJ Havens. Modeling two SiGe HBT specific features for circuit simulation. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 38–41. 12. JCJ Paasschens, WJ Kloosterman, RJ Havens, and HC de Graaff. Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. IEEE Journal of Solid-State Circuits 36:1390–1398, 2001. 13. Mextram Models, Level 504. www.semiconductors.philips.com/Philips_Models/bipolar/mextram/ index.html. 14. JL de Jong, R Lane, B van Schravendijk, and G Conner. Single polycrystalline silicon layer advanced super high-speed BiCMOS technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1989, pp. 182–185. 15. B van Schravendijk, JL de Jong, P van Wijnen, and G Conner. QUBiC2: BiCMOS technology for 17 GHz bipolar and 0.5 mm CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 158–161. 16. A Pruijmboom, D Szmyd, R Brock, R Wall, N Morris, K Fong, and F Jovenin. QUBiC3: A 0.5 mm BiCMOS production technology, with fT ¼ 30 GHz, fmax ¼ 60 GHz and high-quality passive components for wireless telecommunication applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 120–123. 17. D Szmyd, R Brock, N Bell, S Harker, G Patrizi, J Fraser, and R Dondero. QUBiC4: a silicon RFBiCMOS technology for wireless communication ICs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 60–63. 18. P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE. 19. Synopsis markets TSUPREM4 and MEDICI. www.synopsis.com.

© 2006 by Taylor & Francis Group, LLC

3.12-386

The Silicon Heterostructure Handbook

20. H Veenstra, P Barre, E van der Heijden, D van Goor, N Lecacheur, B Fahs, G Gloaguen, S Clamagirand, and O Burg. A 20-input 20-output 12.5 Gb/s SiGe cross-point switch with less than 2 ps RMS jitter. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2003, pp. 174–176. 21. H Veenstra and E van der Heijden. A 19–23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE. 22. H Veenstra and E van der Heijden. A 35.2–37.6 GHz LC VCO in a 70/100 GHz fT/fmax SiGe Technology. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2004. 23. P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE. 24. LF Tiemeijer, RJ Havens, R de Kort, Y Bouttement, P Deixler, and M Ryczek. Predictive spiral inductor compact model for frequency and time domain. Technical Digest of the International Electron Devices Meeting, Washington, 2003, pp. 875–878. 25. K Washio, E Ohue, R Hayami, A Kodama, H Shimamoto, M Miura, K Oda, I Suzumara, T Tominari, and T Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Transactions on Electron Devices 50:2417–2424, 2003. 26. K Nellis and P Zampardi. A comparison of bipolar technologies for linear handset power amplifier applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 3–6. 27. DMH Hartskeerl, HGA Huizing, P Deixler, W van Noort, and PHC Magnee. High performance SiGeC HBT integrated into a 0.25 mm BiCMOS technology featuring record 88% power-added efficiency. International Microwave Symposium, Fort Worth, 2004.

© 2006 by Taylor & Francis Group, LLC

4 SiGe HBTs 4.1

Overview: SiGe HBTs J.D. Cressler........................................................................... 4.1-389

4.2

Device Physics J.D. Cressler ...................................................................................... 4.2-391 Introduction . An Intuitive Picture . Current Gain . Output Conductance . Current Gain — Early Voltage Product . Charge Modulation Effects . AC Figures-of-Merit . Base and Emitter Transit Times . Operating Current Density Versus Speed . Summary

4.3

Second-Order Effects J.D. Cressler ........................................................................... 4.3-411 Introduction . Ge Grading Effect . Neutral Base Recombination . Heterojunction Barrier Effects . Summary

4.4

Low-Frequency Noise G. Niu ................................................................................... 4.4-427 Background . Measurement Methods . Physical Origins . SiGe Profile Impact and Modeling . Oscillator and Synthesizer Phase Noise Issues . Summary

4.5

Broadband Noise D.R. Greenberg............................................................................. 4.5-439 Introduction . HBT Noise Mechanisms and Modeling . Noise Performance Overview and Trends . Device Optimization for Low Noise . Circuit Performance . Summary

4.6

Microscopic Noise Simulation G. Niu .................................................................... 4.6-459 Introduction . Noise Source Density and Noise Propagation . Input Voltage and Current Noise Concentrations . A SiGe HBT Example . Summary

4.7

Linearity G. Niu ......................................................................................................... 4.7-475 Introduction . Basic Concepts . Physical Nonlinearities . Volterra Series Linearity Analysis . Summary

4.8

pnp SiGe HBTs J.D. Cressler ..................................................................................... 4.8-489 Introduction . Simulation of pnp SiGe HBTs . Profile Optimization Issues . Stability Constraints in pnp SiGe HBTs . Summary

4.9

Temperature Effects J.D. Cressler ............................................................................. 4.9-497 Introduction . The Impact of Temperature on Bipolar Transistors . Cryogenic Operation of SiGe HBTs . Design Constraints . Optimization of SiGe HBTs for 77 K . Helium Temperature Operation . High-Temperature Operation . Summary

4.1-387 © 2006 by Taylor & Francis Group, LLC

4.1-388

The Silicon Heterostructure Handbook

4.10

Radiation Effects J.D. Cressler .............................................................................. 4.10-511 Introduction . DC Effects . AC Small-Signal and Noise Effects . Origin of Radiation Hardness . Low-Dose-Rate Effects . SiGe HBT Circuit Tolerance . Single-Event Upset . Summary

4.11

Reliability Issues J.D. Cressler............................................................................... 4.11-525 Introduction . Technology-Driven Reliability and Yield Issues . Conventional Device Degradation Mechanisms . ‘‘Mixed-Mode’’ Stress Effects . Breakdown Voltage Constraints and Operating Point Instabilities . Low-Frequency Noise Variations . Summary

4.12

Self-Heating and Thermal Effects J.-S. Rieh ...................................................... 4.12-539 Introduction . Modeling of Self-Heating . Thermal Resistance Measurement and Trends . Thermal Effects and Device Reliability . Summary

4.13

Device-Level Simulation G. Niu .......................................................................... 4.13-553 Introduction . Semiconductor Equations . Physical Model Selection . Application Issues . Probing Internal Device Operation . Summary

4.14

SiGe HBT Performance Limits G. Freeman, A. Stricker, J.-S. Rieh, and D.R. Greenberg ................................................................................ 4.14-571 Performance . Intrinsic and Extrinsic Partitioning . Intrinsic Device Scaling . Extrinsic Device RC Delays . Practical Limitations . Summary

© 2006 by Taylor & Francis Group, LLC

4.1 Overview: SiGe HBTs

John D. Cressler Georgia Institute of Technology

SiGe HBTs are far and away the most mature Si heterostructure devices and not surprisingly the most completely researched and discussed in the technical literature. That is not to say that we completely understand the SiGe HBT, and new effects and nuances of operation are still being uncovered year-byyear as transistor scaling advances and application targets march steadily upward in frequency and sophistication. There is still much to learn. Nevertheless, a large body of literature on SiGe HBT operation does exist, across an amazingly diverse set of topics, ranging from basic transistor physics, to noise, to radiation effects, to simulation. This section’s comprehensive treatment of SiGe HBTs begins with Chapter 4.2, ‘‘Device Physics,’’ by J.D. Cressler of Georgia Tech., and addresses perturbations to that first-order theory in Chapter 4.3, ‘‘Second-Order Effects,’’ by J.D. Cressler of Georgia Tech. Chapters 4.4 to 4.7 address mixed-signal noise and linearity in SiGe HBTs, including: Chapter 4.4, ‘‘Low-Frequency Noise,’’ by G. Niu of Auburn University; Chapter 4.5, ‘‘Broadband Noise,’’ by D. Greenberg of IBM Microelectronics; Chapter 4.6, ‘‘Microscopic Noise Simulation,’’ by G. Niu of Auburn University; and Chapter 4.7, ‘‘Linearity,’’ by G. Niu of Auburn University. The very recent development of complementary (npn þ pnp) SiGe technologies for high-speed analog circuits makes the discussion in Chapter 4.8, ‘‘pnp SiGe HBTs,’’ by J.D. Cressler of Georgia Tech particularly relevant. Chapter 4.9, ‘‘Temperature Effects,’’ by J.D. Cressler of Georgia Tech addresses the impact of bandgap engineering on device behavior across temperature, as well as the inherent advantages enjoyed by SiGe HBTs for cryogenic electronics. The important and very recently emerging application associated with space-borne electronics operating in a hostile radiation-rich environment are addressed in Chapter 4.10, ‘‘Radiation Effects,’’ by J.D. Cressler of Georgia Tech. Reliability issues, of key importance to the deployment of SiGe HBT circuits and systems, are covered in Chapter 4.11, ‘‘Reliability Issues,’’ by J.D. Cressler of Georgia Tech, and the related and important topic of thermal phenomena are treated in Chapter 4.12, ‘‘Self-Heating and Thermal Effects,’’ by J.-S. Rieh of Korea University. Finally, subtleties associated with device-level (one-dimensional through three-dimensional) simulation of SiGe HBTs is presented in Chapter 4.13, ‘‘Device-Level Simulation,’’ by G. Niu of Auburn University, and this section concludes with a look at the ultimate limits of SiGe HBTs in Chapter 4.14, ‘‘Performance Limits,’’ by G. Freeman of IBM Microelectronics. In addition to this substantial collection of material, and the numerous references contained in each chapter, a number of review articles and books detailing the operation and modeling of SiGe HBTs exist, including Refs. [1–13].

4.1-389 © 2006 by Taylor & Francis Group, LLC

4.1-390

The Silicon Heterostructure Handbook

References 1. SS Iyer, GL Patton, JMC Stork, BS Meyerson, and DL Harame. Heterojunction bipolar transistors using Si–Ge alloys. IEEE Transactions on Electron Devices 36:2043–2064, 1989. 2. GL Patton, JMC Stork, JH Comfort, EF Crabbe´, BS Meyerson, DL Harame, and JY-C Sun. SiGe-base heterojunction bipolar transistors: physics and design issues. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 13–16. 3. C Kermarrec, T Tewksbury, G Dawe, R Baines, B Meyerson, D Harame, and M Gilbert. SiGe HBTs reach the microwave and millimeter-wave frontier. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1994, pp. 155–162. 4. JD Cressler. Re-engineering silicon: Si–Ge heterojunction bipolar technology. IEEE Spectrum, 1995, pp. 49–55. 5. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Transactions on Electron Devices 40:455–468, 1995. 6. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Transactions on Electron Devices 40:469–482, 1995. 7. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Transactions of Microwave Theory and Techniques 46:572–589, 1998. 8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. JS Yuan. SiGe, GaAs, and InP Heterojunction Bipolar Transistors. New York, NY: John Wiley & Sons, 1999. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 12. R Singh, DL Harame, and MM Oprysko. Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 13. P Ashburn. SiGe Heterojunction Bipolar Transistors. New York, NY: John Wiley & Sons, 2004.

© 2006 by Taylor & Francis Group, LLC

4.2 Device Physics

John D. Cressler Georgia Institute of Technology

4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10

Introduction............................................................. 4.2-391 An Intuitive Picture ................................................ 4.2-391 Current Gain............................................................ 4.2-393 Output Conductance .............................................. 4.2-396 Current Gain — Early Voltage Product ................ 4.2-399 Charge Modulation Effects..................................... 4.2-400 AC Figures-of-Merit................................................ 4.2-402 Base and Emitter Transit Times............................. 4.2-402 Operating Current Density Versus Speed ............. 4.2-406 Summary .................................................................. 4.2-408

4.2.1 Introduction The essential differences between the SiGe HBT and the Si BJT are best illustrated by considering a schematic energy band diagram. For simplicity, we consider an ideal, graded-base SiGe HBT with constant doping in the emitter, base, and collector regions. In such a device construction, the Ge content is linearly graded from 0% near the metallurgical emitter–base (EB) junction to some maximum value of Ge content near the metallurgical collector–base (CB) junction, and then rapidly ramped back down to 0% Ge. The resultant overlaid energy band diagrams for both the SiGe HBT and the Si BJT, biased identically in forward-active mode, are shown in Figure 4.2.1. Observe in Figure 4.2.1 that a Geinduced reduction in base bandgap occurs at the EB edge of the quasi-neutral base (DEg,Ge (x ¼ 0)), and at the CB edge of the quasi-neutral base (DEg,Ge (x ¼ Wb)). This grading of the Ge across the neutral base induces a built-in quasi-drift field ((DEg,Ge (x ¼ Wb) DEg,Ge(x ¼ 0))/Wb) in the neutral base. In this chapter, we examine the impact of Ge on the dc and ac properties of the transistor — the essential devices physics of the SiGe HBT.

4.2.2 An Intuitive Picture To intuitively understand how these band-edge changes affect the dc operation of the SiGe HBT, first consider the operation of the Si BJT. When VBE is applied to forward bias the EB junction, electrons are injected from the electron-rich emitter into the base across the EB potential barrier (refer to Figure 4.2.1). The injected electrons diffuse across the base, and are swept into the electric field of the CB junction, yielding a useful collector current. At the same time, the applied forward bias on the EB junction produces a back-injection of holes from the base into the emitter. If the emitter region is doped heavily with respect to the base, however, the density of back-injected holes will be small compared to the forward-injected electron density, and hence a finite current gain b / n/p results. As can be seen in Figure 4.2.1, the introduction of Ge into the base region has two tangible dc consequences: (1) the potential barrier to injection of electrons from emitter into the base is decreased. Intuitively, this will yield exponentially more electron injection for the same applied VBE, translating into 4.2-391 © 2006 by Taylor & Francis Group, LLC

4.2-392

The Silicon Heterostructure Handbook

∆E g,Ge (x = 0) ∆E g,Ge (x = W b)

e–

EC

p-SiGe base

n+ Si

h+

emitter EV

Ge n–Si p-Si

collector

FIGURE 4.2.1 Energy band diagram for a Si BJT and a graded-base SiGe HBT, both biased in forward active mode at low injection.

higher collector current, and hence higher current gain, provided the base current remains unchanged. Given that band-edge effects generally couple strongly to transistor properties, we naively expect a strong dependence of JC on Ge content. Of practical consequence, the introduction of Ge effectively decouples the base doping from the current gain, thereby providing device designers with much greater flexibility than in Si BJT design. If, for instance, the intended circuit application does not require high current gain (as a rule of thumb, b ¼ 100 is usually sufficient for most circuits), we can effectively trade the higher gain induced by the Ge band offset for a higher base-doping level, leading to lower net base resistance, and hence better dynamic switching and noise characteristics. (2) The presence of a finite Ge content in the CB junction will positively influence the output conductance of the transistor, yielding higher Early voltage. While it is more difficult to physically visualize why this is the case, in essence, the smaller base bandgap near the CB junction effectively weights the base profile (through the integral of intrinsic carrier density across the base), such that the backside depletion of the neutral base with increasing applied VCB (Early effect) is suppressed compared to a comparably doped Si BJT. This translates into a higher Early voltage compared to a Si BJT. To intuitively understand how these band-edge changes affect the ac operation of the SiGe HBT, first consider the dynamic operation of the Si BJT. Electrons injected from the emitter into the base region must diffuse across the base (for constant doping), and are then swept into the electric field of the CB junction, yielding a useful (time-dependent) collector current. The time it takes for the electrons to traverse the base (base transit time) is significant, and typically is the limiting transit time that determines the overall transistor ac performance (e.g., peak fT). At the same time, the applied forward bias on the EB junction dynamically produces a back-injection of holes from the base into the emitter. For fixed collector bias current, this dynamic storage of holes in the emitter (emitter charge storage delay time) is reciprocally related to the ac current gain of the transistor (bac). As can be seen in Figure 4.2.1, the introduction of Ge into the base region has an important ac consequence, since the Ge-gradient-induced drift field across the neutral base is aligned in a direction (from collector to emitter) such that it will accelerate the injected minority electrons across the base. We are thus able to add a large drift field component to the electron transport, effectively speeding up the diffusive transport of the minority carriers and thereby decreasing the base transit time. Even though the band offsets in SiGe HBTs are typically small by III–V technology standards, the Ge grading

© 2006 by Taylor & Francis Group, LLC

4.2-393

Device Physics

over the short distance of the neutral base can translate into large electric fields. For instance, a linearly graded Ge profile with a modest peak Ge content of 10%, graded over a 50-nm neutral base width, yields 75 mV/50 nm ¼ 15 kV/cm electric field, sufficient to accelerate the electrons to near saturation velocity (ns ’ 1 107 cm/sec). Because the base transit time typically limits the frequency response of a Si BJT, we would expect that the frequency response should be significantly improved by introducing this Ge-induced drift field. In addition, we know that the Ge-induced band offset at the EB junction will exponentially enhance the collector current density (and thus b) of a SiGe HBT compared to a comparably constructed Si BJT. Since the emitter charge storage delay time is reciprocally related to b, we would also expect the frequency response to a SiGe HBT to benefit from this added emitter charge storage delay time advantage.

4.2.3 Current Gain To understand the inner workings of the SiGe HBT, we must first formally relate the changes in the collector current density and hence current gain to the physical variables of this problem. It is also instructive to carefully compare the differences between a comparably constructed SiGe HBT and a Si BJT. In the present analysis, the SiGe HBT and Si BJT are taken to be of identical geometry, and it is assumed that the emitter, base, and collector-doping profiles of the two devices are identical, apart from the Ge in the base of the SiGe HBT. For simplicity, a Ge profile that is linearly graded from the EB to the CB junction is assumed (as depicted in Figure 4.2.2). The resultant expressions can be applied to a wide variety of practical SiGe profile designs, ranging from constant (box) Ge profiles, to triangular (linearly graded) Ge profiles, and including the intermediate case of the Ge trapezoid (a combination of box and linearly graded profiles) [2]. Unless otherwise stated, this analysis assumes standard lowinjection conditions, negligible bulk and surface recombination, Boltzmann statistics, and holds for npn SiGe HBTs. The theoretical consequences of the Ge-induced bandgap changes to JC can be derived in closed form (x) ¼ Nab ¼ constant) by considering the generalized for a constant base-doping profile (pb(x) ¼ Nab Moll–Ross collector current density relation (refer to Appendices A.2 and A.3), which holds for low injection in the presence of both nonuniform base doping and nonuniform base bandgap at fixed VBE and temperature (T ) [3]

Ge

Space charge n+

Wb

0 E

n−

p

B

x C

FIGURE 4.2.2 Schematic base doping and Ge profiles in a linearly graded SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

4.2-394

The Silicon Heterostructure Handbook

q(eqVBE =kT 1) , J C ¼ ð Wb pb (x)dx 2 0 Dnb (x)nib (x)

(4:2:1)

where x ¼ 0 and x ¼ Wb are the neutral base boundary values on the EB and CB sides of the base, respectively. In this case, the base doping is constant, but both nib and Dnb are position-dependent; the former through the Ge-induced band offset, and the latter due to the influence of the (positiondependent) Ge profile on the electron mobility (Dnb ¼ kT/qmnb ¼ f(Ge)). Note that JC depends only on the Ge-induced changes in the base bandgap. In general, the intrinsic carrier density in the SiGe HBT can be written as n2ib (x) ¼ (NC NV )SiGe (x)eEgb (x)=kT ,

(4:2:2)

where (NCNV)SiGe accounts for the (position-dependent) Ge-induced changes associated with both the conduction and valence band effective density-of-states. In Equation (4.2.2), the SiGe base bandgap can be broken into its various contributions (as depicted in Figure 4.2.3). app is the heavyIn Figure 4.2.3, Egbo is the Si bandgap under low-doping (1.12 eV at 300 K), DEgb doping-induced apparent bandgap narrowing in the base region, DEg,Ge(0) is the Ge-induced band offset at x ¼ 0, and DEg,Ge(Wb) is the Ge-induced band offset at x ¼ Wb. We can thus write Egb(x) as app Egb (x) ¼ Egbo DEgb þ [DEg;Ge (0) DEg;Ge (Wb )]

x DEg;Ge (0): Wb

(4:2:3)

Substitution of Equation (4.2.3) into Equation (4.2.2) gives n2ib (x) ¼ gn2io e

app DEgb =kT [DEg;Ge (Wb )DEg;Ge (0)]x=(Wb kT) DEg;Ge (0)=kT

e

e

,

(4:2:4)

where we have made use of the fact that for Si, we can define a low-doping intrinsic carrier density for Si as n2io ¼ NC NV eEgo =kT ,

(4:2:5)

and we have defined an ‘‘effective density-of-states ratio’’ between SiGe and Si according to [4] g¼

(NC NV )SiGe < 1: (NC NV )Si

(4:2:6)

∆E app gb

Egb (x)

Egbo ∆Eg, Ge (0)

∆Eg,Ge (W b)

n+ 0

FIGURE 4.2.3

n−

p Wb

Schematic base bandgap in a linearly graded SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

x

4.2-395

Device Physics

Equation (4.2.4) can be inserted into the generalized Moll–Ross relation (4.2.1) to obtain app

~ nb (eqVBE =kT 1)~ qD gn2io eDEgb =kT eDEg;Ge (0)=kT J C ¼ ð Wb , Nab e[DEg;Ge (Wb )DEg;Ge (0)](x=Wb kT ) dx

ð4:2:7)

0

˜ nb and g~ to be position-averaged quantities across the base profile, according to where we have defined D ð Wb ~ nb ¼ ð D Wb 0

dx 2 (x) n 0 ib : dx Dnb (x)n2ib (x)

(4:2:8)

Using standard integration techniques, and defining DEg;Ge (grade) ¼ DEg;Ge (Wb ) DEg;Ge (0),

(4:2:9)

we get app

JC;SiGe ¼

~ nb (eqVBE =kT 1)~ qD gn2io eDEgb =kT eDEg;Ge (0)=kT n o: Wb kT Nab DEg;Ge (grade)=kT 1e DEg;Ge (grade)

(4:2:10)

Finally, by defining a minority electron diffusivity ratio between SiGe and Si as h ~¼

~ nb )SiGe (D , (Dnb )Si

(4:2:11)

we obtain the final expression for JC,SiGe [2, 5] JC;SiGe

app ~h ~DEg;Ge (grade)=kTeDEg;Ge (0)=kT qDnb qVBE =kT 2 DEgb =kT g ¼ (e 1)nio e : Nab Wb 1 eDEg;Ge (grade)=kT

(4:2:12)

Within the confines of our assumptions stated above, this can be considered an exact result. As expected from our intuitive discussion of the band diagram, observe that JC in a SiGe HBT depends exponentially on the EB boundary value of the Ge-induced band offset, and is linearly proportional to the Ge-induced bandgap grading factor. Given the nature of an exponential dependence, it is obvious that strong enhancement in JC for fixed VBE can be obtained for small amounts of introduced Ge, and that the ability to engineer the device characteristics to obtain a desired current gain is easily accomplished. Note as well that the thermal energy (kT ) resides in the denominator of the Ge-induced band offsets. This is again expected from a simple consideration of how band-edge effects generally couple to the device transport equations. The inherent temperature dependence in SiGe HBTs will be revisited in detail in Chapter 4.9 [6]. If we consider a comparably constructed SiGe HBT and Si BJT with identical emitter contact technology, and further assume that the Ge profile on the EB side of the neutral base does not extend into the emitter enough to change the base current density, our experimental expectations are that for a comparably constructed SiGe HBT and Si BJT, the JB should be comparable between the two devices, while JC at fixed VBE should be enhanced for the SiGe HBT. Figure 4.2.4 confirms this expectation experimentally. In this case, we note that the ratio of the current gain between an identically constructed SiGe HBT and a Si BJT can be written as

© 2006 by Taylor & Francis Group, LLC

4.2-396

The Silicon Heterostructure Handbook

Collector and base currents (A)

10–2 AE = 0.8 ⫻ 2.5 µm2 RBI = 5−8kΩ/ 10–4

VCB = 0.0 V

SiGe HBT

Si BJT

10–6

IC

IB

4.51⫻ 10–8

10–10 0.4

0.5

0.6 0.7 0.8 Emitter−base voltage (V)

0.9

1.0

FIGURE 4.2.4 Comparison of current–voltage characteristics of a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

bSiGe JC;SiGe ﬃ , bSi JC;Si

(4:2:13)

and thus we can define a SiGe current gain enhancement factor as g~h ~DEg;Ge (grade)=kTeDEg;Ge (0)=kT bSiGe J ¼ : bSi VBE 1 eDEg;Ge (grade)=kT

(4:2:14)

Typical experimental results for J are shown for a comparably constructed SiGe HBT and Si BJT in Figure 4.2.5. Based on the analysis above, we can make several observations regarding the effects of Ge on the collector current and hence current gain of a SiGe HBT: .

.

.

.

The presence of any Ge, in whatever shape, in the base of a bipolar transistor will enhance JC at fixed VBE (hence b) over a comparably constructed Si BJT. The JC enhancement depends exponentially on the EB boundary value of Ge-induced band offset, and linearly on the Ge grading across the base. This observed dependence will play a role in understanding the best approach to profile optimization. In light of that, for two Ge profiles of constant stability, a box Ge profile is better for current gain enhancement than a triangular Ge profile, everything else being equal. The Ge-induced JC enhancement is thermally activated (exponentially dependent on reciprocal temperature), and thus cooling will produce a strong magnification of the enhancement.

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1].

4.2.4 Output Conductance The dynamic output conductance (@IC/@VCE at fixed VBE) of a transistor is a critical design parameter for many analog circuits. Intuitively, from the transistor output characteristics, we would like the output current to be independent of the output voltage, and thus ideally have zero output conductance (infinite output resistance). In practice, of course, this is never the case. As we increase VCB, we deplete the neutral base from the backside, thus moving the neutral base boundary value (x ¼ Wb) inward. Since

© 2006 by Taylor & Francis Group, LLC

4.2-397

Device Physics

Temperature (K) 300

200

130

100

77

100 AE = 0.8⫻2.5 µm2

b (SiGe)/b (Si)

VCB = 0.0 V IC = 30.0 µA data Theoretical 10

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.5 Measured and calculated current gain ratio as a function of reciprocal temperature for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

Wb determines the minority carrier density on the CB side of the neutral base, the slope of the minority electron profile, and hence the collector current, necessarily rises [7]. Thus, for finite base doping, IC must increase as VCB increases, giving a finite output conductance. This mechanism is known as the ‘‘Early effect,’’ and for experimental convenience, we define the Early voltage (VA) as (

( )1 )1 @JC @JC @Wb VA ¼ JC (0) VBE ’ JC (0) , @VCB VBE @Wb VBE @VCB

(4:2:15)

where JC(0) ¼ JC (VCB ¼ 0 V). The Early voltage is a simple and convenient measure of the change in output conductance with changing VCB. Simultaneously maintaining high current gain, high frequency response, and high VA is particularly challenging in a Si BJT. For a Si BJT, we can use Equation (4.2.1) together with Equation (4.2.15) to obtain ð Wb VA;Si ¼

pb (x)dx Q (0) ¼ b , @Wb Ccb pb (Wb ) @VCB 0

(4:2:16)

where Qb(0) is the total base charge at VCB ¼ 0 V, Ccb is the collector–base depletion capacitance, and we have assumed that VBE is negligible compared to VCB. Note that Ccb is dependent on both the ionized þ þ ) and the ionized base doping (Nab ). To estimate the sensitivity of VA on Ndc and Nab , collector doping (Ndc we can consider a Si BJT with constant base and collector-doping profiles. In this case, we can write (

VA;Si

)1 @Wb ¼ Wb (0) , @VCB VBE

(4:2:17)

where Wb(0) is the neutral base width at VCB ¼ 0 V. The dependence of Wb on voltage and doping can be obtained from [8]

© 2006 by Taylor & Francis Group, LLC

4.2-398

The Silicon Heterostructure Handbook

ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ s ﬃ þ Ndc 2« (fbi þ VCB ) Wb ’ Wm , (N þ N þ ) q Nab ab dc

(4:2:18)

where Wm is the metallurgical base width, and fbi is the CB junction built-in voltage. Using Equation , increasing (4.2.17) and Equation (4.2.18) we can calculate VA as a function of doping. Cleary, if we fix Nab þ degrades VA, physically because the amount of backside neutral base depletion per unit bias is Ndc þ , increasing Nab rapidly increases VA, which enhanced for a higher collector doping. If we instead fix Ndc makes intuitive sense given that the base is much more difficult to deplete as the base doping increases, everything else being equal. In real Si BJT designs, a given device generally has a specified collector-toemitter breakdown voltage (BVCEO) determined by the circuit requirements. To first order, this BVCEO sets the collector-doping level. While this may appear to favor achieving a high VA, we must recall that the current gain is reciprocally related to the integrated base charge (refer to Equation (4.2.1)). to improve VA results in a strong decrease in b. In addition, for a Si BJT, for a fixed Hence, increasing Nab will degrade the cutoff frequency of the transistor (due to the reduction in the base width, increasing Nab þ to buy back the ac minority electron mobility). We might imagine that we can then increase Ndc performance lost, this in turn degrades VA. This ‘‘catch-22’’ represents a fundamental problem in Si BJT design: it is inherently difficult to simultaneously obtain high VA, high b, and high fT. In practice one must then find some compromise design for VA, b, and fT, and in the process the performance capabilities of a given analog circuit suffer. Intuitively, this Si BJT design constraint occurs because b and VA are both coupled to the base-doping profile. The introduction of Ge into the base region of a Si BJT can favorably alter this constraint by effectively decoupling b and VA from the base-doping profile. To formally obtain VA in a SiGe HBT, we begin by combining Equation (4.2.1) with Equation (4.2.15) to obtain [9] pb (xÞdx 2 D nb (x)nib (x) 0 ¼ ð Wb , @ pb (x)dx @VCB 0 Dnb (x)n2ib (x)

VA;SiGe

ð Wb

(4:2:19)

from which we can write VA;SiGe ¼

ð Dnb (Wb )n2ib (Wb ) Wb pb (x)dx @Wb 1 : 2 pb (Wb ) @VCB 0 Dnb (x)nib (x)

(4:2:20)

Comparing Equation (4.2.16) and Equation (4.2.20) we can see that the fundamental difference between 2 VA in a SiGe HBT and a Si BJT arises from the variation of nib as a function of position (the variation of Wb with VCB is, to first order, similar between SiGe and Si devices). Observe that if nib is positionindependent (i.e., for a box Ge profile), then Equation (4.2.20) collapses to Equation (4.2.16) and there is no VA enhancement due to Ge (albeit there will obviously still be a strong b enhancement). On the other hand, if nib is position-dependent (i.e., in a linearly graded Ge profile), VA will depend exponentially on the difference in bandgap between x ¼ Wb and that region in the base where nib is smallest. That is, the base profile is effectively ‘‘weighted’’ by the increasing Ge content on the collector side of the neutral base, making it harder to deplete the neutral base for a given applied VCB, all else being equal, effectively increasing the Early voltage of the transistor. For a linearly graded Ge profile, we can use Equation (4.2.4) and Equation (4.2.20) to obtain the ratio of VA between a comparably constructed SiGe HBT and Si BJT (Q) to be [10] DEg;Ge (grade)=kT VA;SiGe DEg;Ge (grade)=kT 1 e : Q’e VA;Si VBE DEg;Ge (grade)=kT

© 2006 by Taylor & Francis Group, LLC

(4:2:21)

4.2-399

Device Physics

Temperature (K) 300

200

130

100

77

10 AE = 0.8⫻2.5 µm2 Forced–VBE

VA (SiGe)/VA (Si)

7

IC = 30.0 µA data Theoretical

5

3 2

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.6 Measured and calculated Early voltage ratio as a function of reciprocal temperature for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

The important result is that the VA ratio between a SiGe HBT and a Si BJT is an exponential function of Ge-induced bandgap grading across the neutral base. Typical experimental results for Q are shown for a comparably constructed SiGe HBT and Si BJT in Figure 4.2.6.

4.2.5 Current Gain — Early Voltage Product In light of the discussion above regarding the inherent difficulties in obtaining high VA simultaneously with high b, one conventionally defines a figure-of-merit for analog circuit design: the so-called ‘‘bVA’’ product. In a conventional Si BJT, a comparison of Equation (4.2.1) and Equation (4.2.16) shows that bVA is to first-order independent of the base profile, and is thus not favorably impacted by conventional technology scaling, as for instance, the transistor frequency response would be. For a SiGe HBT, however, both b and VA are decoupled from the base profile, and can be independently tuned by changing the Ge profile shape. By combining Equation (4.2.14) and Equation (4.2.21) we find that the ratio of bVA between a comparably constructed SiGe HBT and Si BJT can be written as [9] bVA;SiGe ¼ g~h ~eDEg;Ge (0)=kT eDEg;Ge (grade)=kT : bVA;Si

(4:2:22)

Typical experimental results for the bVA ratio for a comparably constructed SiGe HBT and Si BJT are shown in Figure 4.2.7. Observe that bVA is a thermally activated function of both the Ge-induced band offset at the EB junction and the Ge-induced grading across the neutral base. As can be seen in Figure 4.2.7, bVA in a SiGe HBT is significantly improved over a comparably designed Si BJT, regardless of the Ge profile shape chosen, although the triangular Ge profile remains the profile shape of choice for both VA and bVA optimization. Due to their thermally activated nature, both VA and bVA are strongly enhanced with cooling, yielding enormous values (bVA > 104) at 77 K for a 10% Ge triangular profile [10]. Based on the analysis above, we can make several observations regarding the effects of Ge on both the Early voltage and current gain — Early voltage product in SiGe HBTs:

© 2006 by Taylor & Francis Group, LLC

4.2-400

The Silicon Heterostructure Handbook

Temperature (K) 300

bVA (SiGe)/bVA (Si)

1000

200

130

100

77

AE = 0.8⫻2.5 µm2 IC = 30.0 µA data Theoretical

100

10

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.7 Measured and calculated ratio of the current gain–Early voltage product ratio as a function of reciprocal temperature for a comparably doped SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon– Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

.

.

Unlike for JC, only the presence of a larger Ge content at the CB side of the neutral base than at the EB side of the neutral base (i.e., finite Ge grading) will enhance VA at fixed VBE over a comparably constructed Si BJT. This VA enhancement depends exponentially on the Ge grading across the base. This observed dependence will play a role in understanding the best approach to profile optimization, generally favoring strongly graded (triangular) profiles. In light of this, for two Ge profiles of constant stability, a triangular Ge profile is better for Early voltage enhancement than a box Ge profile is, everything else being equal. The Ge-induced VA enhancement is thermally activated (exponentially dependent on reciprocal temperature), and thus cooling will produce a strong magnification of the enhancement. Given that b and VA have the exact opposite dependence on Ge grading and EB Ge offset, the bVA product in a SiGe HBT enjoys an ideal win–win scenario. Putting any Ge into the base region of a device will exponentially enhance this key analog figure-of-merit, a highly favorable scenario given the discussion above of inherent difficulties of achieving high bVA in a Si BJT. A reasonable compromise Ge profile design that balances the dc optimization needs of b, VA, and bVA would be a Ge trapezoid, with a small (e.g., 3% to 4%) Ge content at the EB junction, and a larger (e.g., 10% to 15%) Ge content at the CB junction (i.e., finite Ge grading).

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1].

4.2.6 Charge Modulation Effects At a deep level, transistor action, be it for a bipolar or field-effect transistor, is physically realized by voltage modulation of the charges inside the transistor, that in turn leads to voltage modulation of the output current. The voltage modulation of the charges results in a capacitive current, which increases with frequency. The bandwidth of the transistor is thus ultimately limited by various charge-storage effects in both the intrinsic and extrinsic device structure. Exact analysis of charge-storage effects requires the solution of semiconductor transport equations in the frequency domain. In practice, charge-storage effects are often taken into account by assuming that the charge distributions instantly follow the changes of terminal voltages under dynamic operation (i.e., a ‘‘quasi-static’’ assumption).

© 2006 by Taylor & Francis Group, LLC

4.2-401

Device Physics

The first charge modulation effect in a SiGe HBT is the modulation of space charges associated with the EB and CB junctions. Voltage changes across the EB and CB junctions lead to changes of the space–charge (depletion) layer thicknesses and hence the total space charge. The capacitive behavior is similar to that of a parallel plate capacitor, because the changes in charge occur at the opposing faces of the space charge layer (which is depleted of carriers under reverse bias) to neutral region transition boundaries. The resulting capacitances are referred to as EB and CB ‘‘depletion’’ capacitances. Under high-injection conditions, the modulation of charges inside the space charge layer becomes significant. The resulting capacitance is referred to as the ‘‘transition’’ capacitance, and is important for the EB junction since it is forward biased. Under low-injection conditions, the CB capacitance is similar to that of a reverse biased pn junction, and is a function of the CB biasing voltage. At high injection, however, even in forward-active mode, the CB capacitance is also a function of the collector current, because of charge compensation by mobile carriers as well as base push-out at very high injection levels. The second charge modulation effect is due to injected minority carriers in the neutral base and emitter regions. To maintain charge neutrality, an equal amount of excess majority carriers are induced by the injected minority carriers. Both minority and majority carriers respond to EB voltage changes, effectively producing an EB capacitance. This capacitance is historically referred to as ‘‘diffusion’’ capacitance, because it is associated with minority carrier diffusion in an ideal bipolar transistor with uniform base doping. What is essential in order to achieve transistor action is modulation of the output current by an input voltage. The modulation of charge is just a means of modulating the current, and must be minimized in order to maintain ideal transistor action at high frequencies. For instance, a large EB diffusion capacitance causes a large input current, which increases with frequency, thus decreasing current gain at higher frequencies. At a fundamental level, for a given output current modulation, a decreased amount of charge modulation is desired in order to achieve higher operating frequency. A natural figure-of-merit for the efficiency of transistor action is the ratio of total charge modulation to the output current modulation t ec ¼

@Qn , @IC

(4:2:23)

which has dimensions of time and is thus called ‘‘transit time.’’ Here, Qn refers to the integral electron charge across the whole device, and can be broken down into various components for regional analysis. The partial derivative in Equation (4.2.23) indicates that there is modulation of both charge and current, and is thus necessary. A popular but incorrect definition of transit time leaves out the derivatives in Equation (4.2.23), and instead uses the simple ratio of charge to collector current [1]. The problem with this common formulation can be immediately deduced if we consider the resultant tec of an npn bipolar transistor, where Qn is dominated by the total number of emitter dopants. The use of tec ¼ Qn/IC thus leads to an incorrect transit time definition, since it produces a transit time that is independent of the base profile design, and is clearly non-physical. Equation (4.2.23) can be rewritten using the input voltage as an intermediate variable tec ¼

@Qn =@VBE gm ¼ , @IC =@VBE Ci

(4:2:24)

where Ci is the total input capacitance, and gm is the transconductance. Ci can be divided into two components Cbe ¼ @Qn/@VBE and Cbc ¼ @Qn/@VBC. The transit times related to the neutral base and neutral emitter charge modulation are the base transit time and the emitter transit time, respectively. The base charge modulation required to produce a given amount of output current modulation can be decreased by introducing a drift field via Ge grading, thereby reducing the base transit time and extending transistor functionality to much higher frequencies. This Ge-grading-induced reduction in

© 2006 by Taylor & Francis Group, LLC

4.2-402

The Silicon Heterostructure Handbook

charge modulation is the fundamental reason why SiGe HBTs have better frequency response than Si BJTs. Ge grading is simply a convenient means by which we reduce the charge modulation.

4.2.7 AC Figures-of-Merit For low injection, a key SiGe HBT ac figure-of-merit, the unity-gain cutoff frequency ( fT), can be written generally as fT ¼

1 1 1 kT WCB ¼ (Cte þ Ctc ) þ t b þ t e þ þ rc Ctc , 2ptec 2p qIC 2vsat

(4:2:25)

where gm ¼ qIC/kT is the intrinsic transconductance at low injection (gm ¼ @IC/@VBE), Cte and Ctc are the EB and CB depletion capacitances, tb is the base transit time, te is the emitter charge storage delay time, Wcb is the CB space–charge region width, vsat is the saturation velocity, and rc is the dynamic collector resistance. Physically, fT is the common-emitter, unity-gain cutoff frequency (h21 ¼ 1), and is conveniently measured using S-parameter techniques. A formal derivation is given in Ref. [1]. In Equation (4.2.25), tec is the total emitter-to-collector delay time, and sets the ultimate limit of the switching speed of a bipolar transistor. Thus, we see that for fixed bias current, improvements in tb and te due to the presence of SiGe will directly translate into an enhanced fT and fmax of the transistor at fixed bias current. In terms of transistor power gain (i.e., using the transistor to drive a ‘‘load’’), one defines the ‘‘maximum oscillation frequency’’ figure-of-merit ( fmax) by [11]

fmax

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ fT ¼ , 8pCbc rb

(4:2:26)

where rb is the small-signal base resistance, and Cbc is the total collector–base capacitance. A derivation of fmax, together with relevant assumptions and discussion, can be found in Ref. [1]. Physically, fmax is the common-emitter, unity power gain frequency, and can also be measured using S-parameter techniques. Clearly, fmax represents a ‘‘higher-order’’ (and therefore potentially more relevant to actual circuit applications) figure-of-merit than fT, since the power gain depends not only on the intrinsic transistor performance (i.e., the device transit times), but also on the device parasitics associated with the process technology and its structural implementation. A larger fT, a smaller rb, and a smaller Cbc are clearly desired for increasing the maximum power gain and circuit operating frequency. Typical fmax data using the various definitions of power gain (i.e., U, MAG, MSG) for a second-generation SiGe HBT biased near peak fT (120 GHz in this case) are shown in Figure 4.2.8.

4.2.8 Base and Emitter Transit Times To understand the dynamic response of the SiGe HBT, and the role Ge plays in transistor frequency response, we must formally relate the changes in the base transit time and emitter transit time to the physical variables of this problem. It is also instructive to carefully compare the differences between a comparably constructed SiGe HBT and a Si BJT. In the present analysis, the SiGe HBT and the Si BJT are taken to be of identical geometry, and it is assumed that the emitter, base, and collector-doping profiles of the two devices are identical, apart from the Ge in the base of the SiGe HBT. The theoretical consequences of the Ge-induced bandgap changes to the base transit time (tb) can be (x) ¼ Nab ¼ constant) by derived in closed-form for a constant base-doping profile (pb(x) ¼ Nab considering the generalized Moll–Ross transit time relation, which holds for low injection in the presence of both non-uniform base doping and non-uniform base bandgap at fixed VBE and T [3]

© 2006 by Taylor & Francis Group, LLC

4.2-403

Device Physics

Cutoff frequency (GHz)

60 50 SiGe HBT

40

5.0⫻

1.7⫻

30 20

AE = 0.5⫻2.5 µm2 RBI = 5–8 kΩ/ VCB = 1.0 V

Si BJT 10 0 0.1

0.2

0.3 0.5 1.0 Collector current (mA)

2.0

3.0

FIGURE 4.2.8 Measured comparison of unity gain cutoff frequency fT as a function of bias current for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

tb ¼

ð Wb 0

n2ib (x) pb (x)

ð Wb 0

pb (y)dy dx: Dnb (y)n2ib (y)

(4:2:27)

We can insert Equation (4.2.3) into Equation (4.2.2) to obtain Equation (4.2.4), and substitute Equation (4.2.4) into Equation (4.2.27) to obtain tb;SiGe ¼

ð Wb 0

n2ib (x) Nab

ð Wb z

Nab 1 DEgbapp =kT DEg;Ge (0)=kT DEg;Ge (grade)y=Wb kT e e e dy dx: Dnb gn2io

(4:2:28)

Performing the first integration step yields tb;SiGe ¼

ð Wb 0

( ) h i app n2ib (x) Nab Wb kT DEgb =kT DEg;Ge (0)=kT DEg;Ge (grade)=kT DEg;Ge (grade)x=Wb kT e e e e dx ~ nb g~n2 DEg;Ge (grade) Nab D io (4:2:29)

where we have accounted for the position dependence in both the mobility and the density-of-states product. Substitution of n2ib from Equation (4.2.4) into Equation (4.2.29) and multiplying through gives ( t b;SiGe ¼

)ð i Wb h Wb kT g~n2io DEg;Ge (grade)x=Wb kT DEg;Ge (grade)=kT 1 e e dx; ~ nb g~n2io DEg;Ge (grade) 0 D

(4:2:30)

which can be integrated and evaluated to obtain, finally [2,5] t b;SiGe ¼

h i Wb2 kT kT 1 1 eDEg;Ge (grade)=kT : ~ nb DEg;Ge (grade) DEg;Ge (grade) D

(4:2:31)

As expected, we see that the base transit time in a SiGe HBT depends reciprocally on the amount of Ge-induced bandgap grading across the neutral base (i.e., for fixed base width, the band-edge-induced drift field). It is instructive to compare tb in a SiGe HBTwith that of a comparably designed Si BJT. In the case of a Si BJT (trivially derived from Equation (4.2.27) for constant base doping and bandgap), we know that

© 2006 by Taylor & Francis Group, LLC

4.2-404

The Silicon Heterostructure Handbook

t b;Si ¼

Wb2 , 2Dnb

(4:2:32)

and hence can write h i t b;SiGe 2 kT kT 1 1 eDEg;Ge (grade)=kT , ¼ h ~ DEg;Ge (grade) DEg;Ge (grade) t b;Si

(4:2:33)

where we have used the ratio of electron diffusivities between SiGe and Si (Equation (4.2.11)). Within the confines of our assumptions stated above, this can be considered an exact result. Figure 4.2.9 shows the theoretical calcuations based on this equation. As expected from our intuitive discussion of the band diagram, observe that tb and hence fT in a SiGe HBT depend reciprocally on the Ge-induced bandgap grading factor, and hence for finite Ge grading across the neutral base, tb is less than unity, and thus we expect enhancement in fT for a SiGe HBT compared to a comparably constructed Si BJT. Figure 4.2.10 confirms this expectation experimentally. Based on the analysis above, we can make several observations regarding the effects of Ge on the frequency response of a SiGe HBT: .

For fixed bias current, the presence of Ge in the base region of a bipolar transistor affects its frequency response through the base and emitter transit times.

50 MAG MSG Mason′s U (MUG) Potentially Unstable (K<1 )

MAG, MSG and Mason's U (dB)

40

Unconditionally Stable (K>1)

Mason′s U

30 MSG

20

10 −20 dB/decade

−20 dB/decade fitting

MAG

MUG

f max = 113.4 GHz

0 f MAG = 96.2 GHz max

−10 100

101 Frequency (GHz)

102

FIGURE 4.2.9 Measured MAG, MSG, and Mason’s U versus frequency for a second-generation SiGe HBT biased near peak fT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.2-405

Device Physics

% Ge (grade) 10

8

6

4

2

0

103

1.0 0.8

102 0.6 0.4 101

t b(SiGe) / t b(Si)

b(SiGe) / b(Si)

300 K 77 K

0.2 100

0.0 0

1

2 3 % Ge (x = 0)

4

5

FIGURE 4.2.10 Theoretical calculations of base transit time ratio G as a function of Ge profile shape. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

The fT enhancement for a SiGe HBT over a Si BJT depends reciprocally on the Ge grading across the base. This makes sense intuitively given the effects of the grading-induced drift field for the minority carrier transport. This observed dependence on Ge grading will play a role in understanding the best approach to profile optimization for a given application. For two Ge profiles of constant stability, a triangular Ge profile is better for cutoff frequency enhancement than a box Ge profile is, everything else being equal, provided tb is dominant over te in determining fT. While this is clearly the case in most first-generation SiGe HBTs, it is nonetheless conceivable that for a te-dominated transistor, a more box-like Ge profile, which inherently favors b enhancement and hence te improvement, might be a favored profile design for optimal frequency response. A compromise trapezoidal profile, which generally favors both tb and te improvement, is a logical compromise profile design point. Such tradeoffs are obviously technology generation dependent. Given that fT is improved across the entire useful range of IC, the fT versus power dissipation trade-off offers important opportunities for portable applications, where power minimization is often a premium constraint. The Ge-induced fT enhancement depends strongly on temperature, and for tb and te, is functionally positioned in a manner that will produce a magnification of fT enhancement with cooling, in stark contrast to a Si BJT.

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1]. As can be seen in Figure 4.2.10, since fT is increased across a large range of useful collector current, we can potentially gain dramatic savings in power dissipation for fixed frequency operation compared to a Si BJT. This power-for-performance tradeoff can in practice be even more important than the sheer increase in frequency response, particularly for portable applications. In this case, if we decided, for instance, to operate the transistor at a fixed frequency of 30 GHz, we could reduce the supply current by a factor of 5. Note as well, that as for the collector current density expression (Equation (4.2.12)), the thermal energy (kT ) plays a key role in Equation (4.2.31), in this case residing in the numerator, and will thus have important favorable implications for SiGe HBT frequency response at cryogenic temperatures, as will be discussed in detail in Chapter 4.9.

© 2006 by Taylor & Francis Group, LLC

4.2-406

The Silicon Heterostructure Handbook

4.2.9 Operating Current Density Versus Speed The fundamental nature of SiGe HBTs requires the use of high operating current density in order to achieve high speed. The operating current density dependence of fT is best illustrated by examining the inverse of fT [1] 1 Cbe þ Cbc ¼ : 2pfT gm

ð4:2:34)

Since Cbe ¼ gm tf þ Cte, Cbc ¼ Ctc, and gm ¼ qIC/kT, Equation (4.2.34) can be rewritten as 1 kT ¼ tf þ Ct , 2pfT qIC

(4:2:35)

where Ct ¼ Cte þ Ctc. Since both Cte and Ctc are proportional to emitter area, Equation (4.2.35) can be rewritten in terms of the biasing current density JC as 1 kT ¼ tf þ Ct , 2pfT qJC

(4:2:36)

where Ct ¼ Ct/AE is the total EB and CB depletion capacitances per unit emitter area, and JC ¼ IC/AE is the collector operating current density. Thus, the cutoff frequency fT is fundamentally determined by the biasing current density JC, independent of the transistor emitter length. For very low JC, the second term is very large, and fT is very low regardless of the forward transit time tf. With increasing JC, the second term decreases, and eventually becomes smaller than tf. At high JC, however, base push-out (Kirk effect, refer to Chapter 4.3) occurs, and tf itself increases with JC, leading to fT roll-off. A typical fT versus JC characteristic is shown in Figure 4.2.11 for a first-generation SiGe HBT. The values of tf and Ct can be easily extracted from a plot of 1/2pfT versus 1/JC (as shown in Figure 4.2.12). Near the peak fT, the 1/2pfT versus 1/JC curve is nearly linear, indicating that Ct is close to constant for this biasing range at high fT. Thus, Ct can be obtained from the slope, while tf can be determined from the y-axis intercept at infinite current (1/JC ¼ 0). To improve fT in a SiGe HBT, the transit time tf must be decreased by using a combination of vertical profile scaling as well as Ge grading across the base. At the same time, the operating current density JC must be increased in proportion in order to make the second term in Equation (4.2.36) negligible compared to the first term (tf ). That is, the high fT potential of small tf transistors can only be realized by using sufficiently high operating current density. This is a fundamental criterion for high-speed SiGe HBT design. The higher the peak fT, the higher the required operating JC. For instance, the minimum required operating current density has increased from 1.0 mA/mm2 for a first-generation SiGe HBT with 50-GHz peak fT to 10 to 15 mA/mm2 for >200-GHz peak fT third-generation SiGe HBTs. Higher current density operation naturally leads to more severe self-heating effects, which must be appropriately dealt with in compact modeling and circuit design. Electromigration and other reliability constraints (refer to Chapter 4.11) associated with very high JC operation have also produced an increasing need for copper metalization schemes. In order to maintain proper transistor action under high JC conditions, the collector doping must be increased in order to delay the onset of high injection effects. This requisite doping increase obviously reduces the breakdown voltage. At a fundamental level, trade-offs between breakdown voltage and speed are thus inevitable for all bipolar transistors (Si, SiGe, or III–V). Since the collector doping in SiGe HBT is typically realized by self-aligned collector implantation (as opposed to during epi growth in III–V), devices with multiple breakdown voltages (and hence multiple fT) can be trivially obtained in the same fabrication sequence, giving circuit designers added flexibility.

© 2006 by Taylor & Francis Group, LLC

4.2-407

Device Physics

60

f T (GHz)

50 40 High injection

30 20

SiGe Control A E = 0.5⫻2.5 µm2

10 0 0.0

1.0 2.0 J C (mA/µm2)

3.0

FIGURE 4.2.11 Typical measured fT JC characteristics of a first-generation SiGe HBT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

16 14

SiGe Control AE = 0.5⫻2.5 µm2

1/2pfT (ps)

12 10 8

C⬘t = slope/Vt = 0.01507 pF/µm2

6 4

tf = 2.9383 ps

2 0

5

10 15 20 1/JC (µm2/mA)

25

30

FIGURE 4.2.12 Illustration of Ct and tf extraction in a SiGe HBT.

Another closely related manifestation of Equation (4.2.36) is that the minimum required JC to realize the full potential of a small tf transistor depends on Ct. Both Cte and Ctc thus must be minimized in the device and are usually addressed via a combination of structural design, ground-rule shrink, and doping profile tailoring via selective collector implantation. This reduction of Ctc is also important for increasing the power gain (i.e., fmax). The record fT in SiGe HBT technology stands at present at 350 GHz [12]. From today’s vantage point, a combined 300þ GHz peak fT/fmax appears to be a very realistic performance goal for fully integrated, commercial SiGe BiCMOS processes (see Chapter 4.14). Clearly, breakdown voltages must decrease as the transistor performance improves. For the case depicted in Figure 4.2.13 [13], the 50, 120, and 210 GHz SiGe HBTs have an associated BVCEO of 3.3, 2.0, and 1.7 V, respectively. Achievable fT BVCEO products in the 350 to 400 GHz V range are realistic goals. The sub-1.5 V breakdown voltages required to reach 300 GHz should not prove to be a serious limitation for many designs, given that BVCEO does not present a hard boundary above which one cannot bias the transistor. Rather, one simply has to live with base current reversal and potential bias instabilities in this (above-BVCEO) bias domain [14]. In addition, on-wafer breakdown voltage tuning will provide an additional level of flexibility for circuit designs needing larger operating headroom.

© 2006 by Taylor & Francis Group, LLC

4.2-408

The Silicon Heterostructure Handbook

Cutoff frequency (GHz)

250 200

0.12 µm (3rd generation) 0.18 µm (2nd) 0.50 µm (1st)

VCB = 1.0 V

150 10⫻ 100 50 0 0.1

1.0 Collector current (mA)

10.0

FIGURE 4.2.13 Measured cutoff frequency data as a function of bias current for three different SiGe HBT technology generations. (From G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. IEEE Trans. Electron Dev. 50:645–655, 2003. With permission.)

4.2.10

Summary

In this chapter, I have detailed ‘‘first-order’’ device physics of SiGe HBTs, both from a dc and an ac perspective. This theoretical framework, while clearly simplistic in its assumptions, is nonetheless very useful in providing insight into the way that real SiGe HBTs operate, and how they are designed in practice in industry. Chapter 4.3 addresses additional subtle, but important, nuances in the operation of SiGe HBTs.

Acknowledgments I am grateful to G. Niu, A. Joseph, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxialbase transistors — Part I: Materials, physics, and circuits. IEEE Trans. Electron Dev. 42:455–468, 1995. 3. H Kroemer. Two integral relations pertaining to electron transport through a bipolar transistor with a nonuniform energy gap in the base region. Solid-State Electron. 28:1101–1103, 1985. 4. EJ Prinz, PM Garone, PV Schwartz, X Xiao, and JC Sturm. The effect of emitter–base spacers and strain-dependent density-of-states in Si/SiGe/Si heterojunction bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1989, pp. 639–642. 5. SS Iyer, GL Patton, JMC Stork, BS Meyerson, and DL Harame. Heterojunction bipolar transistors using Si–Ge alloys. IEEE Trans. Electron Dev. 36:2043–2064, 1989. 6. JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JY-C. Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part I: Transistor dc design considerations. IEEE Trans. Electron Dev. 40:525–541, 1993. 7. JM Early. Effects of space-charge layer widening in junction transistors. Proc. IRE 40:1401–1406, 1952.

© 2006 by Taylor & Francis Group, LLC

Device Physics

4.2-409

8. DJ Roulston. Bipolar Semiconductor Devices. New York, NY: McGraw-Hill, 1990. 9. EJ Prinz and JC Sturm. Current gain–Early voltage products in heterojunction bipolar transistors with nonuniform base bandgaps. IEEE Electron Dev. Lett. 12:661–663, 1991. 10. AJ Joseph, JD Cressler, and DM Richey. Optimization of Early voltage for cooled SiGe HBT precision current sources. J. Phys. IV 6:125–129, 1995. 11. SJ Mason. Power gain in feedback amplifiers. IRE Trans. Circuit Theory CT-1:20–25, 1954. 12. J-S Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–775. 13. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. Transistor design and application considerations for >200 GHz SiGe HBTs. IEEE Trans. Electron Dev. 50:645–655, 2003. 14. M Rickelt, HM Rein, and E Rose. Influence of impact-ionization-induced instabilities on the maximum usable output voltage of silicon bipolar transistors. IEEE Trans. Electron Dev. 48:774–783, 2001.

© 2006 by Taylor & Francis Group, LLC

4.3 Second-Order Effects

John D. Cressler Georgia Institute of Technology

4.3.1 4.3.2 4.3.3 4.3.4 4.3.5

Introduction............................................................... 4.3-411 Ge Grading Effect...................................................... 4.3-411 Neutral Base Recombination.................................... 4.3-415 Heterojunction Barrier Effects ................................. 4.3-421 Summary .................................................................... 4.3-426

4.3.1 Introduction While second-order deviations from the first-order theory presented in Chapter 4.2 will always exist in SiGe HBTs, their specific impact on actual SiGe HBT devices and circuits is both profile-design and application dependent, and thus they must be carefully appreciated and kept at the back of the mind by designers. We first analyze the so-called ‘‘Ge grading effect’’ associated with the position dependence of the Ge content across the neutral base found in SiGe designs. The influence of Ge grading effect on SiGe HBT properties is physically tied to the movement of emitter–base space–charge edge along the graded Ge profile with increasing base–emitter voltage. This Ge grading effect can present potential problems for circuit designs that require precise knowledge and control over the current dependence of both current gain and base–emitter voltage as a function of temperature. We then discuss the impact of neutral base recombination (NBR) on SiGe HBT operation. A finite trap density necessarily exists in the base region of all bipolar transistors, and while the impact is usually assumed to be negligible in Si BJTs, it can become important in SiGe HBTs, particularly when they are operated across a wide temperature range. NBR can strongly affect the output conductance (Early voltage) of SiGe HBTs, and is strongly dependent on the mode of base drive (i.e., whether the device is voltage- or current-driven), and hence the circuit application. Finally, we address high-injection heterojunction barrier effects (HBE) in SiGe HBTs. Barrier effects associated with the collector–base heterojunction under high current density operation are inherent to SiGe HBTs, and if not carefully controlled, can strongly degrade both dc and ac performance at the large current densities which SiGe HBTs are often operated. We conclude each section with a brief discussion of the implications and potential problems imposed by these design constraints on both device and circuit designers (‘‘the bottom line’’).

4.3.2 Ge Grading Effect To ensure the applicability of SiGe HBTs to precision analog circuits, parameter stability over both temperature and bias clearly must be ensured. Given the bandgap-engineered nature of the SiGe HBT, this can become an issue for concern, particularly for devices with non-constant (graded) Ge content across the neutral base. Even a cursory examination of the bias current dependence of the current gain in a graded-base SiGe HBT as a function of temperature, for instance, shows a profound functional difference from that of a Si BJT (Figure 4.3.1). In particular, for a graded-base SiGe HBT, the current gain peaks at low injection, and degrades significantly before the onset of high-injection effects. This 4.3-411 © 2006 by Taylor & Francis Group, LLC

4.3-412

The Silicon Heterostructure Handbook

250

Current gain

8% Ge Trapezoid A E = 0.8⫻2.5 µm2

90 K 111 K

150

140 K 2.75 mA/µm2

100 300 K 50

0 10−6

10−5

10−4 10−3 Collector current (A)

10−2

FIGURE 4.3.1 SiGe HBT current gain as a function of collector current at various temperatures, illustrating the Ge grading effect. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

E Doping concentration and Ge %

77 K 200

B

C

VBE = 0

VBE > 0

∆Eg,Ge(x) ∆Eg,Ge(0) 0 x xBE,met

xBC,met

FIGURE 4.3.2 Schematic diagram of the base profile of a SiGe HBT, illustrating the physical origin of the Ge grading effect.

medium-injection ‘‘collapse’’ of b is clearly enhanced by cooling, and thus can be logically inferred to be the result of a band-edge phenomenon. To understand the physical origin of this bias-dependent behavior in the current gain in SiGe HBTs, consider Figure 4.3.2, which shows a schematic doping and Ge profile in a graded-base SiGe HBT. As derived in Chapter 4.2, the collector current at any bias of a graded-base SiGe HBT is exponentially dependent upon the amount of Ge at the edge of the emitter–base (EB) space–charge region. Physically, as the collector current density increases, the base–emitter voltage must also increase, and hence from charge balance considerations the EB space–charge width necessarily contracts, thereby reducing the EB boundary value of the amount of Ge (DEg,Ge(0)), and producing a bias and temperature dependence different from that of a Si BJT [2]. Since this Ge grading effect is the physical result of the modulation of the base width with increasing base–emitter voltage (Wb(VBE)), it can be logically associated with the socalled inverse Early effect. The dependence of the collector current density on the Ge profile shape in a SiGe HBT is given approximately by JC;SiGe ’

app DEg;Ge (grade) DEg;Ge (0)=kT qDnb qVBE =kT 2 DEgb =kT ~ : e (e 1)n e g h ~ io W Nab kT b

(4:3:1)

The relationship between JC and Ge profile shape in Equation (4.3.1) highlights the dependence of the collector current density on Ge profile design. Since DEg,Ge(0) changes with increasing base–emitter bias, any changes in the amount of Ge seen by the device at that EB boundary will have a large impact due to the exponential relationship. Consequently, the more strongly graded the Ge profile, the more serious Ge grading effect can be expected to be. Given that Ge grading effect in SiGe HBTs impacts the bias-current dependence of the current gain, a logical test-case circuit for examining the circuit-level influence of Ge grading effect is the ubiquitous bandgap reference (BGR) circuit, since its functionality relies heavily on the identical dependence of VBE(IC) on temperature between transistors of differing size. Given two transistors with a (realistic) nonconstant base doping, and biased at the same collector current, two SiGe HBTs with a sufficiently strongly graded Ge profile might be expected to ‘‘feel’’ the Ge ramp effect differently, since the voltageinduced space–charge width changes would differ slightly between the two. The conceivable result would

© 2006 by Taylor & Francis Group, LLC

4.3-413

Second-Order Effects

0.95 Base−emitter voltage (V)

AE = 0.5⫻2.5 µm2 VCB = 1.0 V

0.90

IC = 100 µA 0.85

0.80 Si (EG = 1.1035) 0.75

15% Ge triangle (EG = 1.0927)

200

240

280 320 Temperature (K)

360

FIGURE 4.3.3 Base–emitter voltage as a function of temperature at fixed bias current for a Si BJT and a SiGe HBT. The lines represent a SPICE fit to the data using the EG fitting parameter. (From SL Salmon, JD Cressler, RC Jaeger, and DL Harame. IEEE Trans. Electron Dev. 47:292–298, 2000. With permission.)

be a slight mismatch in VBE over temperature between the two transistors, thereby degrading the output voltage stability of the BGR circuit over temperature [3]. In the context of SiGe HBT-based BGR implementations, it is key that detailed knowledge of the impact of Ge profile shape on the temperature dependence of the base–emitter voltage exists. Clearly, VBE in turn depends on the variation of IC across the desired temperature range of interest (e.g., 558C (218 K) to 858C (358 K)). As can be observed in Figure 4.3.3, the differences in VBE(T) between a Si BJT and a SiGe HBT are small, but clearly observable, and must be more carefully examined. The Ge grading effect in SiGe HBTs is primarily determined by the ‘‘steepness’’ of the Ge profile through the EB space–charge region, and the magnitude and shape of N ab (x) at the space–charge to quasineutral base boundary. We can roughly estimate the variation on the SiGe-to-Si current gain ratio (J ¼ bSiGe/bSi) with VBE for varying amounts of Ge grading by considering a linearly graded SiGe HBT with uniform doping levels in the emitter and base regions. From Chapter 4.2, we have g~h ~DEg;Ge (grade)=kT eDEg;Ge (0)=kT bSiGe , J ¼ bSi VBE 1 eDEg;Ge (grade)=kT

(4:3:2)

from which we can obtain @J ¼ @VBE

(

J fbi;BE VBE

)

xpE 2Wb0

DEg;Ge (grade)=kT , 1 eDEg;Ge (grade)=kT

(4:3:3)

where fbi,BE is the built-in potential of the EB junction, xpE is the EB space–charge width on the base side of the junction, and Wb0 is the neutral base width at zero-bias. As DEg,Ge(grade) gets small (i.e., approaching a Ge box profile), the Ge grading effect becomes negligible, yielding a flat b versus IC characteristic, as in a Si BJT. Equation (4.3.3) also predicts a weaker Ge grading effect in transistors with higher base doping, since xpE becomes negligible with respect to Wb0. However, in practical SiGe HBT base profiles, which typically have a retrograded base doping level in the vicinity of the EB junction to reduce the EB electric field, the Ge grading effect is enhanced, since xpE varies nonlinearly with VBE. Finally, we note that due to the band-edge nature of Ge grading effect, its impact on device performance should be greatly magnified at reduced temperatures.

© 2006 by Taylor & Francis Group, LLC

4.3-414

The Silicon Heterostructure Handbook

To determine the impact of the Ge grading effect on practical BGR circuits, we must recast the SiGe HBT collector current density into the familiar BGR design equation. First, the process-dependent parameters (B) and the Ge profile dependent terms (j) can be lumped together in IC as app

IC (T ) ¼ jBT m eEg0 =kT eEgb

=kT qVBE =kT

e

,

(4:3:4)

and rewritten in terms of the base–emitter voltage as VBE ¼

app Eg0 Egb kT IC : ln þ q q q jBT m

(4:3:5)

In practice, we can measure the base–emitter voltage at a reference temperature and collector current and solve for the lumped process parameters (B). Inserting the lumped parameters back into the original VBE equation and simplifying yields the desired SiGe HBT result [3] VBE;SiGe ¼

o o T 1n T n app app DEg;Ge (0) Eg0 Egb DEg;Ge (0) þ VBE;R Eg0 Egb q qTR TR kT IC kT T ln ln : þ m q q TR IC;R

(4:3:6)

The effects of Ge on the base–emitter voltage of the transistor can be gleaned directly from this more generalized result. Observe that the effective bandgap at the emitter–base junction is simply the Si result in the presence of doping-induced bandgap narrowing (Eg0 Eapp gb ), minus the bandgap reduction due to the amount of Ge at the EB junction (DEg,Ge(0)). In addition, the shape of VBE versus temperature in a SiGe HBT is changed from that of a Si BJT due to the addition of Ge, as is apparent in the last two terms of the equation. The ratio T/TR enhances this difference between Si BJTs and SiGe HBTs. For temperatures near the reference temperature, the last two terms of Equation (4.3.6) have little effect on VBE(IC,T), but as the temperature decreases, these effects can become more pronounced. Note that the effective bandgap parameters (Eg0 Eapp gb DEg,Ge(0)) and m correspond to the SPICE modeling parameters EG and XTI, respectively. The amount of curvature in VBE versus temperature is affected by the addition of Ge, as is apparent in the last two terms of Equation (4.3.6). Assuming that the Ge grading (DEg,Ge(grade)) does not change significantly with temperature, the deviation from linearity of VBE versus temperature (i.e., VBE curvature) using Equation (4.3.6) is actually reduced with increasing Ge grading across the base. In the curvature results presented, the deviation from linearity is calculated by drawing a line through the endpoints of VBE across the relevant temperature range, and then subtracting the actual VBE value from the value on the line at each temperature, according to VBE (TL ) VBE (TH ) (TL T ) , Dlinearity ðT Þ ¼ VBE (T ) VBE (TL ) TL TH

(4:3:7)

where in this case TL ¼ 218 K (558C) and TH ¼ 358 K (858C). While this Ge-grading-induced VBE curvature reduction might naively appear to be a good thing for BGR design, it in fact can worsen the performance of BGR circuits. Figure 4.3.4 shows the theoretical deviation from linearity that results from three different hypothetical Ge profiles: (1) no Ge grading; (2) 8.6% Ge grading; and (3) 18.6% Ge grading. Note that a box-shaped Ge profile (no Ge grading), in which the Ge concentration across the base is finite but constant, will have the same deviation from linearity as a Si BJT. Given sufficient Ge grading, it is clear that differences between Si BJTs and SiGe HBTs should be experimentally observable, and a combination of measurement and modeling results confirm this [1].

© 2006 by Taylor & Francis Group, LLC

4.3-415

Second-Order Effects

0.004 I C = 100 µA

Theoretical

TR = 300 K

∆ from linearity (V)

0.003

0.002

0.001

∆ Eg,Ge(grade) = 0 meV ∆ Eg,Ge(grade) = 65 meV

0.000 200

∆ Eg,Ge(grade) = 140 meV 240

280 320 Temperature (K)

360

FIGURE 4.3.4 Theoretical dependence of the peak VBE deviation from linearity as a function of temperature for various amounts of Ge grading. (From SL Salmon, JD Cressler, RC Jaeger, and DL Harame. IEEE Trans. Electron Dev. 47:292–298, 2000. With permission.)

When discussing any second-order effect in transistors, it is important to clearly understand both its physical origins and its potential implications for both device and circuit designers, so that it can be effectively ‘‘designed around.’’ We can summarize these implications for Ge grading effect as follows: .

.

.

.

.

.

Ge grading effect is likely to be important only in precision analog circuits, not in digital or RF/ microwave circuits. While the BGR circuit is a natural candidate for observing Ge grading effect, any analog circuit that depends strongly on current gain across a wide bias range, or that requires the matching of VBE between multiple devices across both bias and temperature, could be potentially affected. While the Ge grading effect exists only in compositionally graded Ge profiles, these graded profile designs typically achieve the best dc and ac performance, and thus represent the vast majority of commercially relevant SiGe technologies. As such, Ge grading effect should never be discounted. The impact of the Ge grading effect is expected to be highly dependent on the specifics of the Ge profile shape, and thus will vary from technology to technology. BGRs implemented in the firstgeneration SiGe HBT technology containing only modest amounts of Ge generally show little impact of Ge grading effect [4]. Since the seriousness of the Ge grading effect depends on the Ge grading, it is a phenomenon that will generally worsen with technology scaling, since for constant strained layer stability, the peak Ge content in a SiGe HBT (and hence the grading across the neutral base) will naturally rise. This scaling-induced enhancement, however, will be at least partially offset by the natural increase in base doping with scaling. Conventional modeling methodologies employed in Gummel–Poon (SPICE) compact transistor models appear to adequately capture the Ge grading effect. Due to its thermally activated nature, cooling clearly exaggerates Ge grading effect, and thus is potentially important for precision analog circuits required to operate across a very wide temperature range.

4.3.3 Neutral Base Recombination Physically, NBR in bipolar transistors involves the recombination of injected electrons transiting the neutral base with holes, via intermediate trap levels. Physically, NBR removes the desired injected

© 2006 by Taylor & Francis Group, LLC

4.3-416

The Silicon Heterostructure Handbook

electrons from the collector current via recombination (i.e., they do not exit the base), and increases the undesired hole density (required to support the recombination process), thereby degrading the base transport factor. Significant NBR thus leads to an increase in the base current and a simultaneous decrease in the collector current, thereby causing a substantial degradation in the current gain. For fixed trap density, the impact of NBR on transistor characteristics, which is generally considered to be negligible in modern Si BJTs, can be exaggerated due to the presence of an increased total base minority carrier charge concentration (Qnb) that participates with the trap recombination process. Because in a SiGe HBT the Ge-induced base bandgap reduction exponentially increases Qnb compared to that in a comparably constructed Si BJT, one would naively expect that the NBR would be strongly enhanced in a SiGe HBT compared to a Si BJT, even at identical trap base density. This situation is also expected to become especially important as the temperature changes, due to the thermally activated nature of Qnb in a SiGe HBT. It is essential, therefore, to understand the physical mechanism of NBR in SiGe HBTs, its impact on the transistor characteristics, and possible circuit implications. For an npn bipolar transistor with negligible EB space–charge region recombination, IB under arbitrary forward-active bias is the sum of the hole current back-injected into the emitter, the hole current due to impact ionization in the collector–base region, and the NBR current component under discussion. For small values of VCB, the additional hole current due to impact-ionization is negligible and thus IB is dominated by the other two components. As the electron diffusion length (Lnb) gets comparable to the neutral base width (Wb), the NBR component of IB becomes increasingly important. With negligible NBR (the ideal case), IB will be independent of VCB for any given VBE. However, under non-negligible NBR, any change in Wb with respect to Lnb will perturb the NBR component of IB. Thus, an easy way to estimate the impact of NBR in a given transistor is to observe the rate of decrease in IB with respect to varying VCB, at a fixed VBE. The base current in this case can be expressed as the sum of the drift-diffusion component and the NBR component as JB ¼ JB;diff þ Jnbr ¼ Jb0 eqVBE =kT þ Jnbr;0 eqVBE =kT :

(4:3:8)

Here Jb0 is assumed to be independent of VCB, while Jnbr,0 is a function of VCB: Jnbr;0 ðSiÞ ¼

qDnb n2ib cosh xSi 1 , sinh xSi Nab Lnb

(4:3:9)

where x ¼ Wb/Lnb. Since the diffusion component of IB is independent of VCB, the change in IB with VCB will only be due to the variation in Jnbr through the variations in Wb. Therefore, in general, the input conductance of the transistor (gm) can be written as @JB @Jnbr @Jnbr @Wb gm ¼ ¼ ¼ : @VCB VBE @VCB VBE @Wb VBE @VCB VBE

(4:3:10)

We can thus determine the gm in a Si BJT to be gm ðSiÞ ¼

qDnb n2ib qVBE =kT cosh xSi 1 1 @Wb e : Lnb @VCB Nab Lnb sinh2 xSi

ð4:3:11Þ

A more convenient way to compare the variations in Jnbr between devices and across temperature is to normalize gm to the base current at VCB ¼ 0 V (g 0m ). Therefore, by rewriting Equation (4.3.11) using the expressions for both JC and VA derived in Chapter 4.2, we finally obtain g 0m in a Si BJT

© 2006 by Taylor & Francis Group, LLC

4.3-417

Second-Order Effects

gm0 ðSiÞ ¼

gm (Si) bSi (VBE ; VCB ¼ 0)x 2Si ( cosh xSi 1) IB;Si (VBE ; VCB ¼ 0) VA;Si (forced-VBE ) sinh2 xSi

(4:3:12)

where bSi(VBE, VCB ¼ 0) represents the current gain measured at a given VBE and VCB ¼ 0 V and VA,Si(forced-VBE) represents the Early voltage at a fixed VBE. Observe that when xSi is zero (representing the ideal situation in the transistor with no NBR), Equation (4.3.12) predicts that g 0m will be zero, as one would expect. On the other hand, when xSi becomes large (i.e., significant NBR is present), then Equation (4.3.12) yields an increased value of g 0m . The g 0m in a SiGe HBT with a trapezoidal Ge profile is difficult to derive analytically. In order to qualitatively determine the device design parameters that strongly influence g 0m , one can consider a simple box Ge profile. In this case, it is easily shown that g 0m in a SiGe HBT is the same as Equation (4.3.12), except for the differences in b. This is expected, since both Jnbr and b in a SiGe HBT are determined primarily by the amount of Ge-induced bandgap reduction at the EB space–charge edge (i.e., DEg,Ge(0)). In general, however, the NBR current component and hence g 0m will be a function of the amount of Ge introduced into the base region of a SiGe HBT (i.e., EB boundary value as well as Ge grading). In addition, since the SiGe-to-Si Jnbr ratio is effectively amplified by cooling, it is expected that the SiGe-to-Si g 0m ratio will also exponentially increase with decreasing temperature. Figure 4.3.5 compares the variation in the normalized-IB as a function of VCB for both the Si and SiGe transistors at 358 and 200 K, respectively. In this case, the transistors are biased in the low-injection region where their collector and base currents are ideal. One can clearly observe the decrease in IB at low VCB due to the modulation of the NBR current component for both transistors, at 358 and 200 K, respectively. The strong decrease in IB at larger values of VCB is due to an increase in the impactionization base current component. By observing the variation in IB with VCB in the low-VCB range, one can easily conclude that the Si BJT shows a weak NBR component (0.5% decrease in IB), while the SiGe HBT shows not only a larger NBR base current component, but also an increase in the NBR with cooling, as anticipated from theory. It is important to note here that, although the NBR component in the SiGe HBT is clearly larger than that in the Si BJT, the magnitude of the NBR component is nevertheless still quite small (3% of IB at 200 K). The measured g 0m in SiGe HBTs is not only expected to be larger than for a comparably constructed Si BJT, but also thermally activated due to the presence of Ge band-offsets in the base region. Figure 4.3.6 confirms this expectation for both triangular and trapezoidal profile SiGe HBTs. 1.00

IB(VCB = 0.0 V)

IB(VCB)

0.99

T = 200 K T = 358 K VBE = 0.85 V VBE = 0.62 V

0.98 AE = 0.8⫻2.5 µm2

Impact Ionization

0.97

0.96

0.95 0.0

SiGe HBT Si BJT 0.2

0.4 0.6 0.8 Collector−base voltage (V)

1.0

FIGURE 4.3.5 Measured normalized-IB as a function of VCB for a SiGe HBT and a Si BJT, at both 358 and 200 K. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-418

The Silicon Heterostructure Handbook

Temperature (⬚C) 85

gµ⬘(SiGe) / gµ⬘(Si)

15

50

−20

27

SiGe HBT AE = 0.8⫻2.5 µm2 Forced-VBE

10 8 6

−55

Trapezoidal Ge Profile

4 EA ~ 60.0 meV

3 2

Triangular Ge profile

EA ~ 34.0 meV

1 2.5

3.0

3.5

4.0

4.5

5.0

1000/T (K−1)

FIGURE 4.3.6 Measured ratio of gm’ in a SiGe HBT and a Si BJT as a function of reciprocal temperature. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

IC and IB

IC and IB IC1 VCB = 0.0 V

IC0

IC0

VCB = 1.0 V

IB0

IB0

VBE

VBE

VBE0

VBE0

No NBR IC

With NBR VBE0 or IB0

IC1

IC0

IB0

IC

VBE0

IC0 Forced-VBE Forced-IB VCE VBE0

VCE VBE0

FIGURE 4.3.7 Illustration of the effects of NBR on the Gummel and output characteristics of a transistor.

A direct consequence of NBR is a difference in the slope of the common-emitter output characteristics of a transistor depending on whether the device is biased using forced-IB or forced-VBE conditions [1]. This can be explained by comparing the dc characteristics for a transistor under an ideal situation (no NBR) with that in the presence of NBR (see Figure 4.3.7). Without NBR, the increase in IC with VCB is the same whether the transistor is biased under forced-VBE or forced-IB input drive, yielding the same VA for both conditions. In the presence of NBR, however, VA measured using both techniques will differ because of the decrease in IB with VCB. In a forced-IB situation, VBE is allowed to change in such a way as

© 2006 by Taylor & Francis Group, LLC

4.3-419

Second-Order Effects

to maintain constant IB. Due to the fact that IB decreases with increasing VCB in the presence of NBR, VBE is forced to increase so as to maintain constant IB. This small increase in VBE exponentially increases IC, leading to a much smaller VA. In a forced-VBE situation, however, the IC increase is due only to the decrease in Wb for an increase in VCB, as one might expect in the ideal case. Thus, in the presence of NBR, VA(forced-IB) will be smaller than VA(forced-VBE), and the two quantities are related through g 0m , according to Ref. [1]: gm0

1 1 : VA (forced-VBE ) VA (forced-IB )

(4:3:13)

Since g 0m is small in a well-made Si BJT, the difference between VA(forced-VBE) and VA(forced-IB) is expected to be small. Equation (4.3.13) predicts that in SiGe HBTs, however, the difference between VA(forced-VBE) and VA(forced-IB) will be greater because of the larger g 0m compared to that in a Si BJT. Figure 4.3.8 shows VA obtained for both Si and SiGe transistors using forced-IB and forced-VBE conditions as a function of reciprocal temperature. Observe that the VA in a Si BJT, obtained using both techniques, yields similar results, thus confirming the presence of only a weak NBR component in the base current of these transistors. In the SiGe HBTs, however, we can clearly observe a quasiexponential degradation of VA(forced-IB) compared to a quasi-exponential improvement in VA(forcedVBE) with cooling. While it is the bandgap grading in the SiGe HBT that increases the VA(forced-VBE), it is the amount of DEg,Ge(x ¼ 0) that causes the exponential degradation in VA(forced-IB) with cooling. From these experimental results, it is clear that such a strong temperature and input-bias dependent situation for SiGe HBTs could potentially have important consequences on the performance of SiGe HBT analog circuits that depend critically on the output conductance of the transistor. This anticipated impact on circuit performance is confirmed in Figure 4.3.9, which uses SPICE models designed to properly account for NBR in SiGe HBTs and carefully calibrated to data, to assess the impact of NBR on precision current sources (refer to the discussion in Ref. [1]). The presumption in this section is that significant NBR exists in the SiGe HBTs under consideration.

Temperature (⬚C) 100

85

50

27

−20

−55

70 Early voltage (V)

Forced-VBE 50

30 20

Forced-IB

AE = 0.8⫻2.5 µm2 IC ~ 1.0 µA SiGe HBT Si BJT

10 2.5

3.0

3.5 4.0 1000/T (K–1)

4.5

5.0

FIGURE 4.3.8 Measured Early voltage as a function of reciprocal temperature for a SiGe BJT and a Si BJT, using both forced-IB and forced-VBE techniques. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-420

The Silicon Heterostructure Handbook

Output resistance (Rout in GΩ)

5.5 SiGe HBT AE = 0.8⫻2.5 µm2 SPICE simulation

4.5 3.5 2.5

Default SPICE Cascode CS Wilson CS Iout ~ 1.0 µA

Without NBR

1.5 With NBR 0.5 200

240

280 Temperature (K)

320

360

FIGURE 4.3.9 Comparison of calibrated SPICE modeling results both with NBR and without NBR for the output resistance of both Cascode and Wilson precision current sources as a function of temperature. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

In this situation we can say: .

.

.

. .

.

An observable difference between VA(forced-VBE) and VA(forced-IB) will exist in the SiGe HBT, and will be reflected in the output characteristics of the transistor. The measured VA(forced-VBE) value in the presence of NBR will be consistent with simple device theory (Chapter 4.2), but the VA(forced-IB) will be degraded (lower) compared to simple theoretical expectations. This input-drive dependent VA difference will be amplified in the SiGe HBT compared to a comparably constructed Si BJT. That is, Ge-induced bandgap engineering will always act to enhance the effects of NBR. This input-drive dependent VA difference will get larger (worse) as the temperature decreases. Careful two-dimensional simulations can be used to identify the physical location of the traps responsible for the NBR component, and correlated with the fabrication process. Accurate compact modeling of SiGe HBTs for circuit design, which includes NBR can be accomplished using existing Si BJT models, but may require an additional parameter to account for the inherently different temperature dependence in VA between a SiGe HBT and a Si BJT. Such NBR-compatible models can provide a detailed assessment of the role of NBR-induced VA changes on particular circuits.

NBR, while clearly inherent to bipolar transistor operation because finite trap densities necessarily exist in semiconductor crystals, does not necessarily strongly perturb the characteristics of modern SiGe HBTs. The experimental results presented in this chapter show a significant NBR base current component, and thus are instructive for understanding and modeling NBR in SiGe HBTs, but we have also measured devices from the other SiGe technologies which do not show appreciable NBRinduced VA changes. Thus, we do not consider NBR to be a ‘‘show-stopper’’ in SiGe HBTs, but rather something to be carefully monitored and assessed during technology development and qualification. In this case, a simple bench-top measurement of IB(VCB)/IB as a function of VCB at two different temperatures (e.g., 300 and 200 K) provides a simple and powerful tool for accurately assessing the presence of significant NBR in a given SiGe HBT technology generation. If present, appropriate steps can be taken to either try and correct the situation by process modification, or models can be developed which accurately account for the effect, thus ensuring that circuit designs are not negatively impacted.

© 2006 by Taylor & Francis Group, LLC

4.3-421

Second-Order Effects

4.3.4 Heterojunction Barrier Effects In order to achieve maximum performance, SiGe HBTs must be biased at very high collector current densities (typically, above 1.0 mA/mm2 for the first-generation SiGe HBTs). High-injection heterojunction barrier effects (HBE), which occur in all HBTs, can cause severe degradation in key transistor metrics such as, b, gm, VA, fT, and fmax, especially at reduced temperatures. Careful transistor optimization is therefore required to delay the onset of the HBE to well above the current density levels required for normal circuit operation. Since the severity of the HBE is mainly determined by the amount of Geinduced band offset at the SiGe–Si heterointerface and the collector doping level, one needs to carefully design the CB junction of the HBT. In order to delay the onset of Kirk effect and hence HBE, one can easily increase the collector doping level (Ndc). Increasing Ndc, however, decreases fmax and BVCEO due to the increase in CCB and the CB electric field, respectively, presenting serious design constraints. The shape and position of the Ge profile in the CB region of a SiGe are critical in determining the characteristics of the onset of HBE and the rate of degradation in HBT characteristics with increasing JC. While large Ge grading is desirable for increasing VA, fT, and fmax of a SiGe HBT, the increased Ge concentration at the CB junction increases the induced barrier associated with HBE. To reduce the impact of the barrier on device performance, one can either gradually decrease the Ge at the CB region or place the SiGe–Si heterointerface deeper inside the collector region, instead of having an abrupt SiGe–Si transition at the interface. Obviously, these methods lead to an increase in the total Ge content of the film, which imposes film stability (and hence manufacturing) constraints on the fabrication process. These device design trade-offs clearly indicate that there exists no specific design solution to completely eliminate HBE. One can, however, tailor the CB design to suit the application at hand, and offers testament to the versatility that can be achieved with bandgap engineering. In Si BJTs operated under high injection in the collector, there are several phenomena that can cause the collector and base currents to deviate from their ideal low-injection behavior (i.e., IC, IB / eqVBE =KT ), including Kirk effect [7], Webster–Rittner effect, the IR drop associated with the base and emitter resistances, and quasi-saturation due to collector resistance. Among these, Kirk effect (or ‘‘base push-out’’) is usually the most important in practical Si BJTs (and SiGe HBTs). The physical basis of Kirk effect lies in the fact that the increased minority carrier concentration in the CB region, at high injection, is sufficient to compensate for the doping-induced charge in the CB space–charge region, causing the space–charge region to first collapse, and then to be pushed deeper into the collector region as JC (hence nC) rises. The displacement of the CB space–charge region effectively increases the base width, which leads to a decrease in the collector current (JC / 1/Wb), and an increase in the base transit time (tb / 1/W 2b ), thus causing a premature degradation in both b and fT. The value of JC at the onset of Kirk effect (JC,Kirk) can be written generally as ( JC;Kirk qvs Ndc

) 2«(VCB þ fbi ) : 1þ 2 qNdc Wepi

(4:3:14)

The direct relationship between the onset of Kirk effect and the collector doping level is obvious. To get a feel for the numbers, if we assume realistic values for the uniformly doped collector (e.g., Ndc ¼ 11017 cm3), and an epi-layer thickness of 0.5 mm, we thus expect from Equation (4.3.14) that the onset of Kirk effect will occur at approximately 1.6 mA/mm2. Since maximum device performance is achieved at large current densities, one usually needs to increase Ndc to provide additional immunity to Kirk effect, thereby increasing the CB electric field, and decreasing the CB breakdown voltage. Thus, a fundamental trade-off exists in Si BJTs between device performance (i.e., peak fT) and maximum operating voltage (i.e., BVCEO), as reflected in the socalled ‘‘Johnson-limit’’ [8].

© 2006 by Taylor & Francis Group, LLC

4.3-422

The Silicon Heterostructure Handbook

Extrinsic transconductance (mS/µm2)

In SiGe HBTs, the transition from a narrow bandgap SiGe base layer to the larger bandgap Si collector layer introduces a valence band offset at the SiGe–Si heterointerface. Since this band offset is masked by the band bending in the CB space–charge region during low-injection operation, it has negligible effect on the device characteristics. At high injection, however, the collapse of original CB electric field at the heterointerface exposes the offset, which opposes hole injection into the collector. The hole pile-up that occurs at the heterointerface induces a conduction band barrier that then opposes the electron flow from base to collector, causing an increase in the stored base charge which results in the sudden decrease in both fT and fmax. The ‘‘pinning’’ of the collector current due to this induced conduction band barrier, and the simultaneous increase in the base current due to valence band offset, causes a rapid degradation in desirable characteristics of the SiGe HBT at a HBE onset current density, and can present serious device and circuit design issues. This effect was first reported in Ref. [9], and later addressed by other authors [10, 11]. In addition, since the transport currents are thermally activated functions of the barrier height, it is expected that the HBE will have a much more pronounced impact at reduced temperatures, raising important questions about operation over a wide temperature range [11]. It is therefore essential that the collector profile and the Ge profile be designed properly to reduce the impact of HBE on circuit performance. To experimentally investigate HBE, first-generation SiGe HBTs with three different Ge profiles were measured (a 15% Ge triangle, a 10% Ge trapezoid, and an 8% Ge trapezoid), along with a comparably designed Si BJT control. The collector profile was identical for all the transistors and was selectively implanted to simultaneously optimize fT (at high JC) while maintaining an acceptable BVCEO of about 3.3 V. The Gummel characteristics of all the transistors are ideal across the measured temperature range of 200 to 358 K. While the SiGe HBTs and Si BJTs have differing current gains, as expected, a normalization of b as a function of JC shows that there is a clear difference in high-injection behavior for the SiGe and Si devices, particularly at reduced temperatures. A sensitive test for clearly observing high-injection HBE in SiGe HBTs is to extract the transconductance (gm) at high JC from the Gummel characteristics, at high and low temperatures. As shown in Figure 4.3.10, a clear dip in the gm at 200 K at JC of about 2.0 mA/mm2 can be clearly seen. By comparing gm and b at JC ¼ 2.0 mA/mm2 between the SiGe HBT and the Si BJT at 358 and 200 K, respectively, one can easily deduce that the differences are associated with the Ge profile, and hence are a signature of high-injection HBE. In addition, Figure 4.3.10 suggests that the trapezoidal Ge profiles show a weaker degradation in gm at 200 K compared to the triangular Ge profile, because of the presence of a smaller Ge band offset in the CB junction (15% Ge versus 8% and 10% Ge, respectively), indicating that the specific design of the Ge profile plays a role, as expected.

40

A E = 0.8⫻2.5 µm2 VCB = 0.0 V

30 200 K 20

10 358 K 0 0.0

1.0

SiGe HBT (15% triangle) SiGe HBT (10% trapezoid) SiGe HBT (8% trapezoid) Si BJT (control) 2.0

3.0

4.0

Collector current density (mA/µm2)

FIGURE 4.3.10 Extrinsic transconductance as a function of collector current density for a Si BJT and three SiGe HBT profiles, at 358 and 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-423

Second-Order Effects

To shed light on both the physics of HBE in SiGe HBTs, as well as to determine the optimum doping and Ge profiles for scaled SiGe HBTs, numerical device simulation is required. Figure 4.3.11 shows the electric field distribution in the base–collector region of both calibrated SiGe and Si transistors at low and high JC. Observe that at low JC, the CB built-in electric field entirely covers the SiGe–Si heterointerface. At high injection (JC ¼ 4.0 mA/mm2, past peak fT), however, the CB space–charge region is pushed deep into the collector region in both transistors due to Kirk effect, and in the SiGe HBT a barrier is formed at the original SiGe–Si heterointerface and can be clearly seen in the high-JC field distribution. Figure 4.3.12 shows the evolution of the induced conduction band barrier to electrons in the SiGe HBT as a function of JC. Clearly, the electron barrier appears only at high injection and this can be correlated with the exposure of the SiGe–Si valence band offset (Figure 4.3.13). In addition, the magnitude of the induced conduction band barrier (fB) gets larger as the device is biased progressively

125

Electric field (kV/cm)

75

25

SCORPIO simulation calibrated profile VCB = 0.0 V T = 200 K JC ~ 4.0 mA/µm2

−25

SiGe HBT Si BJT

JC ~ 0.1 mA/µm2

SiGe Si Base

−75 Collector −125 160

260 360 Depth from emitter contact (nm)

460

FIGURE 4.3.11 Simulated electric field distribution in a Si BJT and SiGe HBT at both low and high current density at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

4.0 mA/µm2

Conduction band edge (eV)

1.10 qΦB 1.00

0.90

0.80

SiGe HBT Si BJT

2.0 mA/µm2

SCORPIO simulation calibrated profile VCB = 0.0 V T = 200 K JC ~ 0.1 mA/µm2

0.70 175

225 275 Depth from emitter contact (nm)

325

FIGURE 4.3.12 Simulated conduction band edge as a function of depth for a Si BJT and SiGe HBT, for various current densities at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-424

The Silicon Heterostructure Handbook

–0.00

Valence Band Edge (eV)

SCORPIO simulation –0.05 SiGe HBT Si BJT –0.10

Calibrated profile VCB = 0.0 V T = 200 K

4.0 mA/µm2 2.0 mA/µm2

–0.15 JC ~ 0.1 mA/µm2 –0.20 175

225 275 Depth from emitter contact (nm)

325

FIGURE 4.3.13 Simulated valence band edge as a function of depth for a Si BJT and SiGe HBT, for various current densities at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

into higher injection, while at very large current densities fB eventually saturates. Although fB at a fixed JC decreases with cooling due to the shift in operating point with temperature, its impact will be much greater at low temperatures due to its thermally activated nature as a band-edge phenomenon. The sudden increase in JB accompanying the barrier onset in a SiGe HBT is the result of the accumulation of holes in the base region due to HBE. At low injection, one clearly sees that the hole concentration in the base is unperturbed compared to a Si BJT. At high injection, however, not only is the hole profile pushed out into the collector region (Kirk effect) but also the presence of the barrier increases the hole concentration close to the CB junction. A fundamental trade-off in collector profile design exists between maximizing both BVCEO and fmax in SiGe HBTs. RF and microwave power amplifiers require large BVCEO, and therefore the collector doping must be reduced. Obviously, such a reduction in Ndc will adversely affect the large-signal performance due to the premature onset of HBE. One can also, in principle, ‘‘tune’’ the barrier onset by properly adjusting the Ge retrograde profile shape. A higher Ge grading in the base region of a SiGe HBT provides better high-frequency performance throughout the temperature range. Increasing the Ge grading, however, necessarily increases the Ge content in the CB junction, which leads to a stronger barrier effect at high injection. In order to reduce the impact of barrier effect in such cases, one can either more gradually decrease the Ge or push the Ge deeper into the collector. In either case, however, one is limited by the amount of Ge that can be added because of the stability constraints of the SiGe films. The successful insertion of SiGe HBTs into practical systems requires accurate compact circuit models for design. Because SiGe HBTs are typically modeled using Si BJT-based compact models (e.g., SPGP, VBIC, MEXTRAM, or HICUM), it is important to assess the accuracy of these models for capturing unique device phenomena such as high-injection HBE. In most compact models, the Kirk effect and HBE are lumped into a single function, assuming the Kirk effect and barrier effect occur simultaneously. This assumption, however, is no longer valid when the SiGe–Si heterojunction is located either in the neutral base region or deeper in the epitaxial collector. The latter, for instance, can be true in SiGe HBTs optimized for high breakdown voltage. Compact models can fail in this case to capture the functional form of the fT JC roll-off in SiGe HBTs (Figure 4.3.14). To accurately capture this phenomenon, a new transit time model that decouples the two effects is needed, and is discussed in detail in Ref. [12]. Due to the presence of SiGe–Si heterojunctions in SiGe HBTs, HBEs are inherent in SiGe HBT design and operation, and thus in some sense can be considered the most serious of the three second-order phenomena considered in this chapter. Given this situation, HBE must always be carefully ‘‘designed

© 2006 by Taylor & Francis Group, LLC

4.3-425

Second-Order Effects

fT (GHz)

20 High–breakdown SiGe HBT VCE = 0.8 V AE = 0.48⫻8.4 µm2 10

Measured data HICUM model VBIC model

0 0.1

1.0

5.0

JC (mA/µm2)

FIGURE 4.3.14 Comparison of measured fT–JC characteristics with the HICUM and VBIC compact models in a high breakdown voltage SiGe HBT. (From Q Liang, JD Cressler, G Niu, RR Murty, K Newton, and DL Harame. IEEE Trans. Electron Dev. 49:1807–1813, 2002. With permission.)

around.’’ This is not overly difficult for low-BVCEO transistors where the collector doping is relatively high, effectively retarding Kirk effect. For applications requiring higher breakdown voltage devices (e.g., power amplifiers), however, care must be taken to ensure that HBE do not adversely impact circuit designs, and that they are accurately modeled. For HBE in SiGe HBTs we can state the following: .

.

.

.

.

.

.

HBEs fall into two general categories: (1) induced barriers due to Ge misplacement; and (2) highinjection-induced barriers. The former can be corrected with proper growth and fabrication techniques, and are thus not inherent to a given SiGe technology. The latter, however, can be considered fundamental to the operation of SiGe HBTs, and must be carefully accounted for and accurately modeled by designers. High-JC HBE causes a rapid degradation in b, gm, and fT once the barrier is induced. The critical onset current density for HBE (JC,barrier) is thus a key device design parameter. HBEs are induced in the conduction band when the hole density in the pushed-out base under high-JC is effectively blocked from moving into the collector by the SiGe–Si heterojunction. Both JC and JB are strongly affected. For low-breakdown voltage devices, HBE and Kirk effect generally occur at similar current densities. In higher breakdown voltage devices, or devices with deep SiGe–Si heterojunctions, however, the two effects can occur at very different current densities, producing unusual structure in the fT –JC characteristics, which first-order compact models do not accurately capture. Changes to the Ge retrograde can be used to effectively retard the onset of HBE, but at the expense of reduced film stability. Changes to the collector doping profile can be used to effectively retard the onset of HBE, but at the expense of increased CB capacitance and reduced breakdown voltage. The impact of HBE on device and circuit performance will rapidly worsen as the temperature decreases, because they are band-edge phenomena.

For any SiGe HBT technology generation, it is a prudent exercise to carefully characterize the transistors and assess the significance of HBE on the overall device response, and determine JC,barrier. This is easily accomplished by plotting linear gm on linear JC at two temperatures (e.g., 300 and 200 K), and this knowledge can then be communicated to circuit designers. If JC,barrier is low enough for practical concerns, then Ge or collector profile modifications can be implemented to alleviate any problems. When moving to a new technology generation with different Ge and doping profiles, HBE should always be revisited.

© 2006 by Taylor & Francis Group, LLC

4.3-426

The Silicon Heterostructure Handbook

4.3.5 Summary Important second-order effects associated with: (1) Ge grading, (2) neutral base recombination, and (3) HBEs will always exist in SiGe HBTs, and their specific impact on actual SiGe HBT device and circuit operation is both profile-design- and application-dependent, and thus must be carefully considered by designers.

Acknowledgments I am grateful to A. Joseph, S. Salmon, Q. Liang, G. Niu, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. EF Crabbe´, JD Cressler, GL Patton, JMC Stork, JH Comfort, and JY-C Sun. Current gain rolloff in graded-base SiGe heterojunction bipolar transistors. IEEE Electron Dev. Lett. 14:193–195, 1993. 3. SL Salmon, JD Cressler, RC Jaeger, and DL Harame. The impact of Ge profile shape on the operation of SiGe HBT precision voltage references. IEEE Trans. Electron Dev. 47:292–298, 2000. 4. HA Ainspan and CS Webster. Measured results on bandgap references in SiGe BiCMOS. Electron. Lett. 34:1441–1442, 1998. 5. AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. Neutral base recombination and its impact on the temperature dependence of Early voltage and current gain — Early voltage product in UHV/CVD SiGe heterojunction bipolar transistors. IEEE Trans. Electron Dev. 44:404–413, 1997. 6. AJ Joseph, JD Cressler, and DM Richey. Optimization of Early voltage for cooled SiGe HBT precision current sources. J. Phys. IV 6:125–130, 1996. 7. CT Kirk. Theory of transistor cutoff frequency falloff at high current densities. IRE Trans. Electron Dev. 3:164–170, 1964. 8. EO Johnson. Physical limitations on frequency and power parameters of transistors. RCA Rev. 163–177, 1965. 9. S Tiwari. A new effect at high currents in heterostructure bipolar transistors. IEEE Electron Dev. Lett. 9:142–144, 1988. 10. PE Cottrell and Z Yu. Velocity saturation in the collector of Si/GexSi1x HBTs. IEEE Electron Dev. Lett. 11:431–433, 1990. 11. AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. Optimization of SiGe HBTs for operation at high current densities. IEEE Trans. Electron Dev. 46:1347–1356, 1999. 12. Q Liang, JD Cressler, G Niu, RR Murty, K Newton, and DL Harame. A physics-based, high-injection transit-time model applied to barrier effects in SiGe HBTs. IEEE Trans. Electron Dev. 49:1807–1813, 2002.

© 2006 by Taylor & Francis Group, LLC

4.4 Low-Frequency Noise 4.4.1 4.4.2 4.4.3 4.4.4

Background ................................................................ 4.4-427 Measurement Methods ............................................. 4.4-427 Physical Origins ......................................................... 4.4-429 SiGe Profile Impact and Modeling .......................... 4.4-431 1/f Noise KF Factor . Geometry Dependence . 1/f Corner Frequency . Impact of Collector–Base Junction Traps . Technology Scaling

4.4.5

1/f Noise in Oscillators . Phase Noise Implications . Synthesizer Phase Noise and Threshold K

Guofu Niu Auburn University

Oscillator and Synthesizer Phase Noise Issues........ 4.4-435

4.4.6

Summary .................................................................... 4.4-437

4.4.1 Background Because of Si-based processing, the low-frequency noise in SiGe HBTs is comparable to that in Si BJTs, which is typically much better (lower) than in III–V HBTs [1–3]. Of particular importance is the 1/f noise or flicker noise, which dominates at low frequency, and can be upconverted to phase noise in RF oscillators through nonlinear I–V and C–V relationships inherent to the transistor. This results in noise sidebands on the carrier frequency, which fundamentally limits spectral purity. Low-frequency noise is also very important for wireless receivers utilizing zero or very low intermediate frequency (IF) architectures. In this chapter, we will introduce the basics of 1/f noise measurement and modeling in SiGe HBTs, its dependence on technology scaling, implications of SiGe, and upconversion to phase noise. We will introduce a method to determine the maximum tolerable 1/f noise level for a given RF process, which can be used to aid process development, as the reduction of 1/f noise is quite challenging in manufacturing, particularly in scaled technologies with low thermal cycle.

4.4.2 Measurement Methods The major 1/f noise source in SiGe HBTs is in the base current, as it is in typical polysilicon emitter Si BJTs. In an equivalent circuit representation, this is described using a noise current source placed between the internal base and emitter nodes. One can measure this noise current either indirectly through measuring the collector noise voltage or directly through measuring the base noise current. The indirect method is relatively easier to implement in practice, and is illustrated in Figure 4.4.1. The potentiometers PB and PC set the dc bias at the base and collector, respectively. Batteries are the preferred power supplies as they have the least amount of spurious noise. The two large capacitors CB and CC provide dynamic ac grounding. They can be left out for simplicity, but care must be exercised in determining the effective source and load resistances seen by the transistor.

4.4-427 © 2006 by Taylor & Francis Group, LLC

4.4-428

The Silicon Heterostructure Handbook

RB is chosen to be much greater than transistor input impedance rp such that the base noise current flows into the transistor for amplification. The voltage noise at RC is further amplified by a low-noise preamp, and detected by a dynamic signal analyzer (DSA). The base current noise (SIB) is obtained from the measured collector voltage noise SVC as SIB ¼

SVC : (RC b)2

(4:4:1)

Strictly speaking, the small-signal b should be used in Equation (4.4.1). If capacitor CC is not used, the effective dynamic load resistance seen by the collector node is used in place of RC. The base bias resistance RB typically ranges from 50 kV to 10 MV, and the collector sampling resistance RC is on the order of 2 kV. Because of the RB >> rp requirement, very large RB is needed for measurement at low IB values. At low IB, the base current noise can be directly measured using a current amplifier (as shown in Figure 4.4.2). A large bypass capacitance CB short-circuits the noise from the base-biasing network, and creates a low impedance path for the base current 1/f noise. The key is to make sure that the input impedance of the current amplifier is much lower than the transistor input impedance (rp), so that all of

DSA

PB

Voltage amplifier

RB

ib

CB

RC CC

PC

FIGURE 4.4.1 Indirect measurement of 1/f noise.

1 MΩ

PB

CC CB

ib

2

S V = G i SIB DSA

GI :gain amplifier

FIGURE 4.4.2 Direct measurement of 1/f noise.

© 2006 by Taylor & Francis Group, LLC

Current amplifier

PC

4.4-429

Low-Frequency Noise

10−20 10−21 SiGe Control AE = 0.5⫻2.5 µm2 I B = 1 µA

SIB (A2/Hz)

10−22 10−23 1/f

10−24

2qIB

10−25 f C = 2.04 kHz

10−26 10−27 100

FIGURE 4.4.3 IB ¼ 1 mA).

101

102 103 Frequency (Hz)

104

105

A typical low-frequency noise spectrum of a first generation SiGe HBT (AE ¼ 0.5 2.5 mm2, and

the base noise current flows into the current amplifier. The current amplifier output voltage is proportional to the base noise current, and the gain of the current amplifier has units of V/A. Figure 4.4.3 shows a typical low-frequency base current noise spectrum (SIB) for a first-generation SiGe HBT. The noise spectrum shows a clear 1/f component as well as the 2qIB shot noise level. The corner frequency fC is determined from the intercept of the 1/f component and the 2qIB shot noise level. At higher IB values, the 2qIB shot noise level cannot be directly observed for various reasons. The calculated 2qIB value can be used to determine fC in this case.

4.4.3.

Physical Origins

The exact origins of 1/f noise are not well understood. A popular theory, proposed by McWhorter [4], describes 1/f noise as a superposition of individual generation–recombination (g–r) noise. Each interfacial trap generates g–r noise with a Lorentzian-shaped spectral density given by SI;i ¼

Ati , 1 þ (2pf p2i )

(4:4:2)

where A is the magnitude of the g–r noise, and ti is the time constant for the trapping–detrapping process. A large number of these traps and a particular statistical distribution of ti (1/t) give rise to 1/f spectral shape. Figure 4.4.4 shows such an example of Lorentzian spectra (dashed lines), and the superpositioned spectrum, which is approximately 1/f. This model assumes no interaction between trap levels at different energies. If the levels interact with each other, a Lorentzian spectrum instead of 1/f spectrum may be observed [5]. This model is expected to work well in devices with large emitter area, where a large number of traps exist. In small emitter area devices, however, one may expect to observe a Lorentzian shape of behavior. Experimental data support the above trapping origin of 1/f noise in SiGe HBTs [6]. Figure 4.4.5(a) and (b) shows the low-frequency noise spectra measured on SiGe HBTs with small and large emitter areas, 0.24 0.48 mm2 and 0.96 1.6 mm2, respectively. Three samples are measured for each area. The low-frequency noise spectra show a strong deviation from 1/f behavior and a larger statistical scatter in the small devices. The average of all samples, shown as solid lines, shows a close to 1/f frequency dependence.

© 2006 by Taylor & Francis Group, LLC

4.4-430

The Silicon Heterostructure Handbook

Noise spectral density (A2/Hz)

10−21 10−22

1/f

10−23 10−24 10−25 10−26 10−27 100

101

102 103 Frequency (Hz)

104

105

FIGURE 4.4.4 1/f noise as a superposition of Lorentzians. 10−19

SIB

(A2/Hz)

10−20 10−21 10−22 10−23

SiGe HBTIB = 1 µA AE = 0.24⫻0.48 = 0.12 µm2 δ = 0.56

10−24 10−25 100

101

(a)

102

103

104

Frequency (Hz)

10−19

SIB

(A2/Hz)

10−20

SiGe HBTIB = 1 µA AE = 0.96⫻1.6 = 1.54 µm2 δ = 0.18

10−21 10−22 10−23 10−24 10−25 100

(b)

101

102

103

104

Frequency (Hz)

FIGURE 4.4.5 Low-frequency noise spectra in three samples with emitter area of (a) AE ¼ 0.24 0.48 mm2 and (b) AE ¼ 0.96 1.6 mm2.

© 2006 by Taylor & Francis Group, LLC

4.4-431

Low-Frequency Noise

4.4.4 SiGe Profile Impact and Modeling 1/f Noise KF Factor In general, SIB is related to IB by SI B ¼ K F

IBa , f

(4:4:3)

where KF and a correspond to the KF and AF model parameters used in SPICE. a ¼ 1 is often viewed as indication of carrier mobility fluctuations, and a ¼ 2 is often viewed as for carrier number fluctuations [7–13]. The a for typical SiGe HBTs is close to 2, and varies only slightly with SiGe profile and collector doping profile (2 þ 0.2). An often-asked question is whether the introduction of SiGe in transistor base affects the 1/f noise KF factor. Assuming that the 1/f noise is solely a function of the number of minority carriers injected into the emitter, one may expect the same 1/f noise at a given VBE, which means the same IB for a SiGe HBT and its Si counterpart. Thus, the 1/f noise K factor is expected to be the same. This turns out to be true experimentally [14]. Figure 4.4.6 shows the SIB at 10 Hz versus IB for three experimental SiGe HBTs and a comparably fabricated Si BJT. The SiGe HBTs include a 10% peak Ge profile control, a 14% peak Ge low-noise design (LN1), and an 18% peak Ge low-noise design (LN2). The Si BJT is an epi-base device. All the devices were fabricated in the same wafer lot. A constant IC comparison is more meaningful in the context of RFIC design, because many RF figures-of-merit fundamentally depend on IC instead of IB (e.g., fT and fmax). In addition, NFmin, though dependent on IB, is often compared at the same operating IC as well. If we compare SIB at the same IC, however, SIB is significantly lower (better) in SiGe HBTs than in Si BJTs, because of the lower IB (higher b) found in SiGe HBTs, all else being equal. Since SIB / I2C /b2, the SIB for the LN1 and LN2 SiGe HBTs should be naturally lower than for the SiGe control and Si BJT because of their higher b. This is confirmed by the measured data shown in Figure 4.4.7.

Geometry Dependence The 1/f noise amplitude, as measured by the KF factor, scales inversely with the total number of carriers in the noise-generating elements, according to Hooge’s theory [15]. The 1/f noise generated by sources in the EB spacer oxide at the device periphery is inversely proportional to the emitter perimeter PE ¼ WE þ LE, while the 1/f noise generated by sources located at the intrinsic EB interface (i.e., the emitter 10−18

S IB (A2/Hz)

10−19 10−20 10−21

14% α IB2.08 18% α IB2.11 10% α IB2.24 Si α I B2.03 αIB2

10−22

AE = 0.5⫻2.5 µm2 f = 10 Hz VCB = 0 V

10−23 10−24 10−7

10−6 I B (A)

10−5

FIGURE 4.4.6 Measured SIB at 10 Hz as a function of IB for the Si BJT, the SiGe control, and the two low-noise SiGe HBTs.

© 2006 by Taylor & Francis Group, LLC

4.4-432

The Silicon Heterostructure Handbook

10−18 SiGe LN1 a IC2.42 SiGe LN2 a IC2.35 SiGe Control a IC2.45 Si BJT a IC2.19

S IB (A2/Hz)

10−19 10−20 10−21

aIC2

10−22 AE = 0.5⫻2.5 µm2 f = 10 Hz VCB = 0 V

10−23 10−24

10−4

10−3 IC (A)

FIGURE 4.4.7 SiGe HBTs.

Measured SIB at 10 Hz as a function of IC for the Si BJT, the SiGe control, and the two low-noise

polysilicon–silicon interface) across the emitter window is inversely proportional to the emitter area AE ¼ WELE. The KF factor is often examined as a function of the emitter area, the emitter perimeter, or the perimeter-to-area ratio as a means of locating the contributing 1/f noise sources [9–13]. For instance, for fixed frequency, the combination of 1/AE dependence with an IB2 bias dependence for SIB is consistent with a uniform area distribution of noise-generating traps across the emitter region. In practice, caution must be exercised in interpreting PE or AE scaling data, because test devices are often designed with the emitter width equal to the minimum feature size, and with an emitter length much larger than the emitter width. As a result, such data tend to scale with the emitter perimeter and area in a similar manner, making interpretation difficult. A wide distribution of device sizes and PE/AE ratios thus needs to be used when designing test structures for noise-scaling studies in order to make a clear distinction between PE and AE scaling in SiGe HBTs. For all the SiGe HBTs described in ‘‘1/f Noise KF Factor,’’ the 1/f noise KF factor is inversely proportional to AE. Equation (4.4.3) can thus be rewritten as SI B ¼

K IB2 K 1 IC2 ¼ 2 ; AE f b AE f

(4:4:4)

where K is a factor independent of the emitter area and is defined as K ¼ KFAE, where a ¼ 2 is assumed. Equation (4.4.4) is written as a function of IC to facilitate technology comparisons for RFIC circuit design, for reasons discussed above. Because the K factor for low-frequency noise is approximately independent of base profile design, a higher b SiGe HBT has a lower SIB, and hence generates lower phase noise when used in RF amplifiers and oscillators. For a given operating current, a larger device can clearly be used to reduce SIB. This tactic, however, reduces fT because of the lower JC. The maximum device size one can use is usually limited by this fT requirement. Optimum transistor sizing is thus important not only for reducing NFmin, but also for reducing phase noise [14].

1/f Corner Frequency Traditionally, 1/f noise performance is characterized by the corner frequency ( fC) figure-of-merit, defined to be the frequency at which the 1/f noise equals the shot noise level 2qIB. Equating (4.4.4) with 2qIB leads to fC ¼

© 2006 by Taylor & Francis Group, LLC

KIB KJC ; ¼ 2qAE 2qb

(4:4:5)

4.4-433

Low-Frequency Noise

where JC is the collector current density, and b is the dc b. Equation (4.4.5) suggests that fC is proportional to JC and K, and inversely proportional to b. We note that this conclusion differs from that derived in Ref. [16]. The derivation in Ref. [16] showed that fC is independent of bias current density, because a ¼ 1 was assumed (i.e., according to mobility fluctuation theory). This dependence of a, however, is not the case in typical SiGe HBTs, which show an a close to 2. Figure 4.4.8 shows the measured and modeled fC – JC dependence for the devices used here. As expected, fC is the lowest in the two low-noise SiGe HBTs, LN1 and LN2, and highest for the Si BJT. The modeling results calculated using Equation (4.4.5) fit the measured data well.

Impact of Collector–Base Junction Traps A subtle effect in SiGe HBTs is the carrier traps near the SiGe–Si growth interface, which are also referred to as collector–base junction traps, because the SiGe–Si growth interface is right in the collector–base junction depletion layer. These traps contribute to a recombination current in the CB ‘‘depletion’’ layer, which is small in magnitude but strongly modulated by the CB voltage, and is responsible for the output conductance degradation under forced-IB operation [17]. At high injection, when the electron concentration in the CB depletion layer becomes comparable to the depletion charge density, the electrical neutral base pushes out. The CB junction traps are now exposed to a large amount of electrons and holes, resulting in a large amount of recombination current. This effect is particularly severe in highbreakdown voltage (HBV) devices, in which collector doping is high and high injection occurs at lower current densities. A natural question is whether these CB junction traps contribute to low-frequency noise. By comparing the base current and base current noise of standard and HBV devices, it was recently found that these CB junction traps indeed produce additional 1/f noise [18]. Conceptually, one can divide the total 1/f noise in a HBV device into two components, one due to EB junction traps and the other due to CB junction traps. The EB noise component is a function of the emitter injection component of the base current, and the CB noise component is a function of the CB recombination current. Figure 4.4.9 shows the two 1/f noise components as a function of their respective base current components [18]. The EB and CB 1/f noises clearly show different dependences on their respective base current components, indicating that the 1/f noise process at the CB junction traps is different from that in the EB junction. For circuit modeling, however, one may continue to simply model the total base current 1/f noise as a function of the total base current, despite that there are two different 1/f noise processes. An accurate model for the CB junction trap-induced recombination current is necessary and has yet to be developed.

100 SiGe LN1 SiGe LN2 SiGe Control Si BJT

fC (kHz)

80 60 40 20 0 0

0.2

0.4

0.6 0.8 JC (mA/µm2)

1.0

1.2

FIGURE 4.4.8 Measured and modeled fC versus JC for the standard breakdown voltage Si BJT, the SiGe control, and the two low-noise SiGe HBTs.

© 2006 by Taylor & Francis Group, LLC

4.4-434

The Silicon Heterostructure Handbook

Technology Scaling The 1/f noise K factor has recently been found to increase with technology scaling [19, 20]. This is likely associated with the physical changes of the emitter–base junction composition during scaling. With scaling, a narrow and more heavily doped base profile is used, which requires a lower thermal cycle for the bipolar processing. The Ge grading often increases with scaling to create a higher accelerating electric field for minority carriers. The addition of carbon in scaled SiGe HBT technologies, though a small amount for suppressing boron outdiffusion, could inadvertently increase 1/f noise. The increase of the 1/f noise K factor with scaling tends to increase fC,1/f . However, depending on device design, b is often increased with scaling as well, which partially offsets the K factor increase. Figure 4.4.10 shows the measured fC a function of JC for HBTs with peak fT of 50 and 120 GHz. The nature of bipolar transistor operation necessitates a higher operating JC to realize the high-speed potential offered by scaling. A larger JC range is thus used for the 120 GHz HBT. For a given JC , an increase of fC,1/f is observed. At JC ¼ 2.5 mA/mm2, the 120 GHz HBT shows a fC,1/f of 1.6 MHz, which is relatively high compared to a 50 GHz HBT at JC ¼ 1 mA/mm2. Such an increase of 1/f corner frequency, however, does not necessarily cause an increase of the overall oscillator phase noise or the ultimate frequency synthesizer noise, due to different mechanisms of phase noise upconversion for the base current 1/f noise and base current shot noise [20].

SIpe (A2/Hz), SIcbsr (A2/Hz)

10−19 SIcbsr−Icbsr

10−20 10−21

HBV LN1

aCB = 1.92, KFCB = 0.52×10−9

Frequency = 10 Hz SIpe−Ipe

10−22

αEB = 2.06, KFEB = 1.35×10−9

10−23 10−24

10−6

10−5 Ipe (A), Icbsr (A)

FIGURE 4.4.9 SIpe – Ipe and SIcbsr – Icbsr dependencies. Frequency is 10 Hz.

fC,1/f (kHz)

1800

120 GHz HBT 50 GHz HBT

1200

600

0 0

FIGURE 4.4.10 Measured fC,1/f versus JC.

© 2006 by Taylor & Francis Group, LLC

0.5

1.0

1.5 2.0 JC (mA/µm2)

2.5

3.0

4.4-435

Low-Frequency Noise

4.4.5 Oscillator and Synthesizer Phase Noise Issues 1/f Noise in Oscillators So far we have considered 1/f noise measured under a given dc biasing IB. In oscillators, the situation is more complicated as [20]: .

.

The base terminal IB is different from the base–emitter junction transport current IBE, because of the capacitive charging and discharging of the junction capacitances. Only IBE generates noise. The noise generating IBE is ‘‘oscillating’’ by the very nature of oscillation.

Figure 4.4.11 compares the waveforms of the terminal IB and internal noise generating IBE in a 5.5 GHz SiGe HBT oscillator. Also shown is the VBE waveform. Clearly, a large difference exists between IBE and IB. Strictly speaking, one cannot simply determine the 1/f noise for an oscillating transistor from the small signal 1/f noise measurement. Measurement of 1/f noise with a periodic large signal biasing, however, is quite involved, particularly if high frequency is involved. In practice, the amount of 1/f noise for an oscillating transistor is assumed to be the same as the 1/f measured at a dc biasing current identical to the dc component of the oscillating noise generating current IBE. This is implemented in CAD tools such as Agilent ADS.

Phase Noise Implications In oscillators, 1/f noise is upconverted to a 1/f 3 phase noise, while all the white noise (shot noise and thermal resistance noise) are upconverted to 1/f 2 phase noises. Figure 4.4.12 shows simulated phase noise versus offset frequency for two HBTs with 50 and 120 GHz peak fT. With device scaling from 50 to 120 GHz technology, the 1/f 3 component increases by 11.4 dB, in part because of the increasing K factor. The 1/f 2 phase noise resulting from upconversion of white noises, however, improves (decreases) by 7.2 dB with HBT scaling. We now define the corner offset frequency, fC,offset, using the intersect of the 1/f 3 and 1/f 2 phase noises. fC,offset is a direct measure of the importance of the phase noise upconverted from 1/f noise with respect to the phase noise upconverted from the white noise sources. fC,offset is 595.4 Hz and 40.8 kHz for the 50 and 120 GHz technologies (as can be seen from Figure 4.4.13). Note that fC,offset itself does not contain any information on either the 1/f 3 or 1/f 2 phase noise level. A higher fC,offset does not necessarily mean higher phase noise. In this case, the fC,offset for the 120 GHz HBT is nearly 70 higher than for the 50 GHz HBT. The overall effect of scaling on oscillator phase

600 0.95 VBE

IB

200 0.90

IBE

0

VBE (V)

IB, IBE (µA)

400

–200 –400

0.85

50 GHz HBT fo = 5.5 GHz

–600 0

100

200 Time (ps)

300

400

FIGURE 4.4.11 Comparison of terminal IB and internal IBE for a SiGe HBT in a 5.5 GHz oscillator. The internal VBE is shown on the right y-axis.

© 2006 by Taylor & Francis Group, LLC

4.4-436

The Silicon Heterostructure Handbook

60 50 GHz HBT 120 GHz HBT

Phase noise (dBc/Hz)

30 0 −30

fo = 5.5 GHz 1/f 3

−60 −90

1/f 2

−120 −150 100

fc,offset 101

102 103 104 105 Offset frequency (Hz)

106

107

Within loop bandwidth

Outside loop bandwidth

LPLL

LVCO

FIGURE 4.4.12 Phase noise of oscillators designed using HBTs with 50 and 120 GHz peak fT.

1/f 3

Within loop bandwidth

Outside loop bandwidth

1/f 3 f loop = 10×f c,offfset L1/f 3 (f loop) =

1 L 2 (f ) 10 1/f loop VCO phase noise dominated

10⫻

1/f 2

10⫻

f c,offset

f loop

f offset

Reference phase noise dominated

10⫻

f loop

1/f 2

f offset

FIGURE 4.4.13 Illustration of the conversion process of VCO and reference phase noise to frequency synthesizer phase noise and the definition of Kth.

noise is a degradation at offsets below 10 kHz, but an improvement at higher offset frequencies. In a frequency synthesizer, if the loop bandwidth is much greater than 10 kHz, the overall synthesizer phase noise will improve with scaling, despite increased 1/f corner frequency, as the oscillator phase noise below 10 kHz is removed by loop feedback.

Synthesizer Phase Noise and Threshold K In frequency synthesizers, the VCO phase noise within the loop bandwidth is suppressed by the loop feedback mechanism. The out-of-band phase noise of the VCO, however, directly translates into synthesizer out-of-band phase noise. From an application standpoint, if the loop bandwidth is sufficiently higher than the corner offset frequency, the 1/f 3 phase noise can be completely suppressed by loop feedback. The out-of-band noise will then be the 1/f 2 phase noise due to white noises. Using 10

© 2006 by Taylor & Francis Group, LLC

4.4-437

Low-Frequency Noise

103

fc,offset (kHz)

102

50 GHz HBT 120 GHz HBT

f loop = 200 kHz

K 120G f c,offset = 20 kHz

101

100

K 50G

Kth = 2.784 µm2 Kth = 3.73×10−9 µm2

10−1

10−12

10−10

10−8

10−6

10−4

10−2

100

102

K factor (µm2)

FIGURE 4.4.14 fC,offset versus K factor. Kth is determined for a loop bandwidth of 200 kHz. The actual K values are shown as ‘‘*.’’

as a criterion, the 1/f 3 phase noise is only one tenth of the 1/f 2 phase noise at the loop bandwidth offset frequency, for a fC,offset that is one tenth of the loop bandwidth (as shown in Figure 4.4.14). For a given oscillator, fC,offset decreases linearly with K according to the analysis in Section 4.4.4. For a given process and loop bandwidth, a threshold K that makes fC,offset equal to one tenth of the loop bandwidth can be defined. Once K < Kth, the synthesizer phase noise no longer decreases with further decrease of K. One can also view this threshold K as the maximum tolerable K. This is very attractive from a semiconductor technology development standpoint, because the 1/f K factor is sensitive to defect level, and very challenging to minimize. Figure 4.4.14 shows fC,offset versus 1/f noise K factor for two technologies of 50 and 120 GHz peak fT. Assuming a loop bandwidth of 200 kHz, Kth is determined as K at which fC,offset ¼ 20 kHz, such that the 1/f 3 phase noise is only 10% of the 1/f 2 noise at 200 kHz. For the 50 GHz HBT, Kth ¼ 2.748 mm2, and the actual K (2.0 109 mm2) is well below Kth. Thus 1/f noise is not a concern for synthesizer phase noise, since practically all the 1/f 3 phase noise is suppressed by loop feedback, and the in-band noise is limited by reference oscillator. For the 120 GHz HBT, Kth ¼ 3.73 109 mm2, which is slightly smaller than the actual K of 8.6 108 mm2. The combination of decreasing Kth and increasing K with scaling makes 1/f noise an increasingly important concern for phase noise of frequency synthesizers.

4.4.6 Summary In this chapter, we have discussed the measurement, modeling, and system phase noise implications of 1/f noise. The 1/f noise K factor, which measures the amount of base current 1/f noise for a given IB, is shown to be a better measure for phase noise than the traditional 1/f noise corner frequency. SiGe HBTs with high corner frequency can still show excellent phase noise performance when used in oscillators. For a given process, the 1/f K factor only needs to be below a certain threshold, and any further reduction of the K factor does not help in reducing system phase noise. The threshold (Kth) is shown to decrease with scaling. This, together with the increase of K factor with technology scaling, makes 1/f noise an increasingly important concern with further scaling.

Acknowledgments The author would like to thank J. Tang for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ1133.

© 2006 by Taylor & Francis Group, LLC

4.4-438

The Silicon Heterostructure Handbook

References 1. L Vempati, JD Cressler, JA Babcock, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors. IEEE J. Solid-State Circ. 31:1458–1467, 1996. 2. B Van Haaren, M Regis, O Llopis, L Escotte, A Gruhle, C Mahner, R Plana, and J Graffeuil. Lowfrequency noise properties of SiGe HBTs and application to ultra-low phase-noise oscillators. IEEE Trans. Micro. Theory Tech. 46:647–652, 1998. 3. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, GG Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS Technology. IEEE Trans. Electron Dev. 48:2575–2594, 2001. 4. AL McWhorter. 1/f noise and germanium surface properties. Semicond. Surf. Phys. 207, 1980. 5. FN Hooge. 1/f noise sources. IEEE Trans. Electron Dev. 41:1926–1935, 1994. 6. Z Jin, JD Cressler, GF Niu, and AJ Joseph. Impact of geometrical scaling on low-frequency noise in SiGe HBTs. IEEE Trans. Electron Dev. 50:676–682, 2003. 7. LKJ Vandamme. Noise as a diagnostic tool for quality and reliability of electronic devices. IEEE Trans. Electron Dev. 41:2174–2187, 1994. 8. A Mounib, F Balestra, N Mathieu, J Brini, G Ghibaudo, A Chovet, A Chantre, and A Nouailhat. Low-frequency noise sources in polysilicon emitter BJTs: Influence of hot-electron-induced degradation and post-stress recovery. IEEE Trans. Electron Dev. 42:1647–1652, 1995. 9. MJ Deen, J Ilowski, and P Yang. Low frequency noise in polysilicon–emitter bipolar junction transistors. J. Appl. Phys. 77:6278–6285, 1995. 10. M Koolen and JCJ Aerts. The influence of non-ideal base current on 1/f noise behaviour of bipolar transistors. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, September 1990, pp. 232–235. 11. HAW Markus and TGM Kleinpenning. Low-frequency noise in polysilicon emitter bipolar transistors. IEEE Trans. Electron Dev. 42:720–727, 1995. 12. P Llinares, D Celi, and O Roux-dit-Buisson. Dimensional scaling of 1/f noise in the base current of quasi self-aligned polysilicon emitter bipolar junction transistors. J. Appl. Phys. 82:2671–2675, 1997. 13. MJ Deen, SL Rumyantsev, and M Schroter. On the origin of 1/f noise in polysilicon emitter bipolar transistors. J. Appl. Phys. 85:1192–1195, 1999. 14. GF Niu, Z Jin, JD Cressler, R Rapeta, AJ Joseph, and DL Harame. Transistor noise in SiGe HBT RF technology. IEEE J. Solid-State Circ. 36:1424–1427, 2001. 15. A van der Ziel. Noise in Solid State Devices and Circuits. Wiley, New York, 1986. 16. LKJ Vandamme and G Trefan. Review of low-frequency noise in bipolar transistors over the last decade. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, 2001, pp. 68–73. 17. GF Niu, JD Cressler, and AJ Joseph. Quantifying neutral base recombination and the effects of collector–base junction traps in UHV/CVD SiGe HBTs. IEEE Trans. Electron Dev. 45:2499–2503, 1998. 18. J Tang, GF Niu, AJ Joseph, and DL Harame. Impact of collector–base junction traps on low-frequency noise in high breakdown voltage SiGe HBTs. IEEE Trans. Electron Dev. 51:1475–1482, 2004. 19. JA Johansen, Z Jin, JD Cressler, and AJ Joseph. Geometry-dependent low-frequency noise variations in 120 GHz fT/SiGe HBTs. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 57–59. 20. GF. Niu, J Tang, Z Feng, AJ Joseph, and DL Harame. Scaling and technological limitations of 1/f noise and oscillator phase noise in SiGe HBTs. IEEE Trans. Micro. Theory Tech. 53:506–514, 2005.

© 2006 by Taylor & Francis Group, LLC

4.5 Broadband Noise

David R. Greenberg IBM Thomas J. Watson Research Center

4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6

Introduction............................................................... 4.5-439 HBT Noise Mechanisms and Modeling .................. 4.5-440 Noise Performance Overview and Trends............... 4.5-445 Device Optimization for Low Noise........................ 4.5-450 Circuit Performance .................................................. 4.5-453 Summary .................................................................... 4.5-455

4.5.1 Introduction The ultimate data rate of any communication channel is constrained by the bandwidth and the signalto-noise ratio (SNR) of the channel [1]. As a result, the quantity of noise at any point in a signal chain places a direct limit on how many bits per second can pass through that point for a given bandwidth and power level. In a typical system such as a wireless receiver, noise can be introduced in a variety of ways, including by the active devices (both bipolar and MOS) used to implement the circuits. Noise may be added directly in band with the signal, such as in the case of a low-noise amplifier (LNA) at the front end of a receiver chain or in the baseband amplifier near the end of the chain. In addition, nonlinearities may allow noise to enter the channel band indirectly. For example, transistor noise in a voltage-controlled oscillator (VCO) circuit introduces phase noise in the output sinusoid. When serving as a local oscillator, such a signal passed to a mixer along with the data signal can cause out-of-band (e.g., adjacent channel) energy to fold in-band, contributing interference that degrades channel capacity in a manner analogous to noise. While the effects of noise can be countered by increasing the energy per bit, which translates into signal power for a given bit rate, many applications, particularly portable systems such as cellular phones, GPS receivers, and WLAN-capable PDAs, are constrained in transmitted or received signal power by battery life limits, transmitter–receiver distance, feasible antenna and package size or standards and regulatory requirements. Supply voltage and amplifier gain compression can impose an upper signal power limit as well. Thus, communication system designers seeking an attractive trade-off between throughput, signal power, and bit-error rate demand technologies capable of processing high-frequency signals while introducing as little noise as possible. Both in discrete and integrated form, the SiGe HBT has emerged as an attractive low-noise solution, combining the performance of more expensive devices such as III–V FETs and HBTs with the process control, integration potential, and low cost associated with silicon [2, 3]. The technology has been penetrating the market steadily, beginning with cellular telephony and wireless networking parts built in the 0.5-mm node for the 0.8 to 2.4 GHz range and progressing toward emerging applications such as 77 GHz automotive radar using the 0.13-mm node. At the same time, the SiGe HBT has proven amenable to accurate analysis and modeling, enabling the circuit designer to achieve the cost and time to market advantages of first-pass design success.

4.5-439 © 2006 by Taylor & Francis Group, LLC

4.5-440

The Silicon Heterostructure Handbook

4.5.2 HBT Noise Mechanisms and Modeling The SiGe HBT is a vertical device, with carrier transport confined largely to low-defect bulk material. As a result, high-frequency noise in the device under typical bias conditions is well described by a simple, one-dimensional physical model containing five fundamental noise sources (as illustrated in Figure 4.5.1). In forward bias, a voltage VBE applied across the base–emitter junction creates a net flow of electrons over the junction energy barrier and into the base. For collector–base voltage VCB well below the collector–base breakdown voltage BVCBO, the collector current IC consists primarily of this electron flow. Since electrons arrive at and cross this energy barrier according to a random distribution, IC contains shot noise with noise power described by hinjci2 ¼ 2qICB, where B is the bandwidth over which noise power is measured [4]. Under the same conditions, the base current IB is composed primarily of holes injected from base to emitter and contains shot noise power similarly described by hinjbi2 ¼ 2qIBB. Although involving a common junction, each carrier type moves and crosses the E–B junction independently of the other. Further, the space–charge and neutral–base recombination components that contribute to both IC and IB are quite low in modern, low-defect SiGe HBTs and may typically be neglected except at very low temperatures. As a result, noise components injc and injb are almost entirely statistically uncorrelated [5]. Resistors are another source of thermal noise and all physically realized HBTs contain a resistance RB in series with the base, arising from both the nonzero lateral dimension of the pinched intrinsic base and from the extrinsic layers used to create electrical access and contact to this intrinsic region. The emitter polysilicon contributes a second parasitic series resistance RE. These resistances generate noise components that can be described using noise voltage sources with powers hjvnRBji2 ¼ 4kTRBB and hjvnREji2 ¼ 4kTREB [4]. Although a noise voltage on the emitter terminal adds to both VBE and VCE, IC in a HBT is quite insensitive to VCE and thus the indirect contribution of RE noise to IC via the creation of VCE noise can be neglected. As a result, RB and RE can be combined into a single noise voltage source hjvnRji2 ¼ 4kT(RB þ RE)B 4kTRB for a modern SiGe HBT in which RE RB. The overall noise voltage contribution from the collector resistance RC is negligible since it is divided by the transistor voltage gain as seen from the vantage point of the other parasitic resistances. At sufficiently high VCB, electrons crossing the space–charge region from base to collector can acquire enough energy to excite a valence electron to the conduction band and create an electron–hole pair. Since the timing of an impact ionization event is statistical in nature, the resulting electrons contribute an additional component noise to IC while the holes add a correlated component to IB. This impact ionization noise is often neglected, but we will later demonstrate its effect on minimum noise figure (Fmin) and describe a device design that reduces this component with few trade-offs [6].

B I/I holes

E

Recombining carriers

B-E injected holes

C

E-B injected electrons I/I electrons

FIGURE 4.5.1 Schematic cross section of an idealized one-dimensional bipolar transistor illustrating the components of current flow which contribute to noise.

© 2006 by Taylor & Francis Group, LLC

4.5-441

Broadband Noise

Relating device-modeling parameters such as RB and device performance metrics such as fT to circuitlevel noise parameters Fmin, Rn, and Gopt is essential for designing and optimizing both the structure and layout of a HBT. One method for doing so is to represent each physical noise source as a component in a small-signal equivalent circuit model and to then use this model to determine each noise parameter [7]. Figure 4.5.2 illustrates a common-emitter equivalent circuit noise model that is simple yet works remarkably well for capturing the essential bias and frequency behaviors of the HBT noise parameters. Collector and base shot noise are represented by noise current sources, while base resistance thermal noise is represented by a noise voltage source. For completeness at high VCB, the impact ionization noise contribution to IC is represented by current source inii. A noisy two-port, such as a HBT, can be represented in an equivalent manner by two noise sources, generally correlated, connected to an ideal, noiseless two-port [8, 9]. Figure 4.5.3 illustrates two possible options for doing so. Representation 1 features noise voltage source vnA and noise current source inA connected to port 1, while Representation 2 drives ports 1 and 2 with noise current sources in1 and in2, respectively. Either representation creates a path for calculating the noise source correlation matrix elements, such as hjvnAji2, hjinAji2, hjvnA inA*ji2, and hjinA vnA*ji2 for Representation 1, in terms of the four noise parameters. Casting these same matrix elements in terms of the equivalent noise circuit model Y-parameters and noise sources, in turn, creates the bridge between the noise and device-modeling parameters [5, 7, 10]. Circuit designers turn first to the minimum noise figure Fmin in evaluating the noise performance of an RF technology. Following the above methodology and employing the equivalent noise circuit model of Figure 4.5.2, Fmin can be expressed in terms of the device-modeling parameters as [5, 7, 10–12]

Fmin

n ﬃ1þ þ b

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 2IC f 1 n2 þ (RB þ RE ) 2 þ VT fT b b

(4:5:1)

which, after subtracting 1 from both sides and assuming that (RB þ RE) RB, 1/b 1 and E–B junction ideality factor n 1, simplifies to sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 2IC f 1 RB 2 þ Fmin 1 ﬃ VT fT b

(4:5:2)

This expression reveals exactly which device-modeling parameters are most critical to achieving low minimum noise figure: RB, fT, and b. The relative importance of each parameter is a function of frequency and of bias, which enters into the expression both explicitly as IC and implicitly in the bias dependencies of fT and, to a lesser extent, RB.

inii vnR

(M−1)ic’

Rb

B

vbe rbe injb

cbe

ccb

ic’ = gm vbe

C injc

vnA

Representation 1:

E

FIGURE 4.5.2 Small-signal equivalent circuit model for a bipolar transistor, including the dominant noise sources. Here, the total noise contributions of resistances RB and RE are lumped into RB (see text for additional discussion).

© 2006 by Taylor & Francis Group, LLC

inA

Noiseless HBT

in1

Representation 2: Noiseless HBT

in2

FIGURE 4.5.3 Two common representations of a noisy two-port as an ideal, noiseless two-port connected to two external noise sources.

4.5-442

The Silicon Heterostructure Handbook

Frequency sweeps are important for model assessment and evaluating a device against candidate applications as well as for providing a basis for interpolating or extrapolating to frequencies outside of the measured range. Equation (4.5.2) implies that the frequency dependence of Fmin divides into two regimes, illustrated in the linear-scale (non-dB) graph of (Fmin 1) versus frequency for a (0.12 4) 16 mm2 emitter-area SiGe HBT (200 GHz peak fT) plotted in Figure 4.5.4. For f 2/fT2 << 1/b (equivalently f 2 f 2T /b), frequency and fT drop out and Fmin simplifies to sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2IC Fmin 1 ﬃ RB VT b

(4:5:3)

In this low-frequency regime, Fmin depends only on RB, IC, and b, with fT not an explicit factor except in defining the boundaries of the regime. Low RB and high b are key to achieving low Fmin in this regime. The frequency dependence here is flat as long as IC is held constant. However, analysis (see below) shows that obtaining strictly optimized Fmin per frequency requires optimizing the bias for each frequency point, leading to Fmin decreasing as the square root of frequency. As frequency passes through the regime boundary, the behavior of Fmin shifts to sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ 2 IC RB 2 Fmin 1 ﬃ f VT fT

(4:5:4)

In this higher frequency regime (f 2 >> f 2T /b), Fmin rises linearly with frequency, with a slope dependent on RB and fT and with b no longer an important concern. In contrast with the low-frequency regime, a value of IC that minimizes Fmin at one frequency also minimizes Fmin over all frequencies, improving ease of test and increasing the utility of such a sweep in evaluating the device. Low RB remains essential for achieving low Fmin as at lower frequency but high fT now becomes important as well. When designing a low-noise circuit, a circuit designer will typically target an application-specific frequency and examine the bias dependences of the noise parameters in order to select an optimal bias. Although bias current IC appears in Equation (4.5.2) directly, fT contains an implicit IC dependence as well, which may be expressed in reciprocal form as 1 VT (CEB þ CCB ) ¼ 2p þ tF fT IC

(4:5:5)

0.7

Fmin −1 (Linear)

0.6

AE = (0.12⫻4) ⫻ 16 µm2 IC = 20 mA, VCE = 1.2 V

0.5 0.4

f << fT

0.3

β

f >> fT

β

f·

2 VT

RB

IC f T2

Proportional to frequency

0.2 2IC

0.1 0.0

VTb 05

RB

10 15 20 Frequency (GHz)

Flat with frequency 25

30

FIGURE 4.5.4 Fmin 1 (linear scale) versus frequency for a sample 0.13-mm node SiGe HBT, illustrating the characteristic behavior in the low-frequency ( f 2 << fT2/b) and high-frequency ( f 2 >> fT2/b) regimes. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-443

Broadband Noise

where input capacitance (CEB þ CCB) sets the fT versus IC slope at low bias and tF determines the upper limit that would be approached by fT at high IC if there were no high-level injection or Kirk effect. This relationship may be substituted into Equation (4.5.2) to yield an expression containing fully explicit references to IC, which may then be minimized with respect to IC to yield a minimum value of Fmin across all currents (an RB versus IC dependence may be inserted as well for those devices in which RB varies significantly with bias over the current range of interest). At low frequencies in which f 2 << f 2T /b, Equation (4.5.3) suggests that Fmin has no minimum and can be made arbitrarily low simply by reducing IC. The equation contains a hidden dependency on fT, however, in the form of the frequency regime boundary defining where the equation is valid. As a result, Equation (4.5.3) cannot be used directly to explore the Fmin bias dependency at a given low frequency. Rather, this dependency must be determined from Equation (4.5.2) and Equation (4.5.5) minimization, with the final result simplified for the low-frequency regime. In this manner, Fmin is found to have a minimum at a bias of pﬃﬃﬃ opt: IC ¼ fVT (CEB þ CCB ) b

(4:5:6)

This minimum depends on the capacitances looking into the base (which determine low-current fT) and on b and is an increasing function of frequency. The actual minimum value of Fmin at this optimal bias is given by

opt: Fmin

pﬃﬃﬃ ﬃ f

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 8p2 RB (CEB þ CCB ) b1=2

(4:5:7)

Figure 4.5.5 illustrates this behavior using a graph of (Fmin 1) versus IC for a (0.2 19.2) 2 mm2 emitter-area device (120 GHz peak fT) at 10 and 15 GHz. Good noise performance in this regime requires low RB, a ubiquitous requirement, as well as high b and good low-current fT optimization (low input capacitance).

1.0 AE = (0.219.2) 2 µm2, VC = 1.5 V

Fmin −1 (Linear)

Opt. Fmin ≅

8π2 RB (CEB+CCB)

f.

1

b

2

15 GHz

0.5

10

opt. IC = f . VT (CEB+CCB) b 0.0 0

5

10

15

IC (mA)

FIGURE 4.5.5 Fmin 1 (linear scale) versus IC for a sample 0.18-mm node SiGe HBT illustrating the bias dependencies, lowest Fmin, and noise-optimal IC in the low frequency ( f 2 << fT2/b) regime. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-444

The Silicon Heterostructure Handbook

The bias dependence of Fmin at higher frequencies differs significantly as noted earlier. While the optimal current for lowest Fmin is frequency dependent at low frequencies, Fmin is optimized by a single value of IC for f 2 >> f 2T /b: opt: IC ¼

VT (CEB þ CCB ) tF

(4:5:8)

This bias point is a function of both the input capacitances and the current-independent fT transit time term. Indeed, this optimal IC corresponds to a value of fT equal to one half the limit approached by fT asymptotically at high IC neglecting high-level injection and the Kirk effect. Since peak fT can approach 85% of this limit in an actual SiGe HBT optimized for fT, the optimal noise bias can be well approximated by finding IC corresponding to half of peak fT. The Fmin value at this IC is an increasing function of frequency given by opt: Fmin ﬃ f 4p

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2RB (CEB þ CCB )t F

(4:5:9)

Figure 4.5.6 illustrates this behavior using a graph of (Fmin 1) versus IC for a (0.2 19.2) 2 mm2 emitter-area device (120 GHz peak fT) at 15 and 20 GHz. Good noise performance in this regime requires low RB and good optimization of both low- and high-current fT (low input capacitance and short transit time tF). b does not affect noise in the higher frequency regime. In each expression for Fmin, a parameter that scales with emitter length LE, such as IC or (CEB þ CCB), appears in product with RB, a parameter that typically scales inversely with LE in device layouts employing a base contact finger on each side of the emitter finger. As a result, Fmin itself is generally insensitive to LE. The analysis used to connect Fmin with device and modeling parameters also yields the remaining three noise parameters, which include the real and imaginary parts of the optimal source impedance as well as the noise resistance Rn. These parameters are key to designing an optimal source match.

1.0 AE = (0.219.2) 2 µm2, VC = 1.5 V 2RB (CEB+CCB)τF

Peak

fT

Fmin −1 (Linear)

Opt. Fmin ≅ f . 4p

1/(2ptF) 2

20 GHz 0.5 15 IC Opt. IC =

Vt(CEB+CCB) τF

0.0 0

5

10

15

IC (mA)

FIGURE 4.5.6 Fmin1 (linear scale) versus IC for a sample 0.18-mm node SiGe HBT illustrating the bias dependencies, lowest Fmin, and noise-optimal IC in the high-frequency ( f 2 >> fT2/b) regime. Inset connects noise-optimal IC directly to the fT versus IC behavior (see text for details). (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-445

Broadband Noise

Under the same assumptions used to simplify the expressions for Fmin, Rn may be approximated as Rn ﬃ VT =2IC þ RB

(4:5:10)

This is merely the sum of the small-signal impedance of the emitter–base diode (as seen from the emitter terminal and assuming IE IC) and the base resistance. Rn is dominated by the former term at low currents and approaches RB as bias increases. Low values of RB, achieved through either process improvements or through layouts featuring long LE, can result in quite low noise resistances and thus to devices that are very tolerant of mismatch and thus more readily able to achieve circuit noise figures close to Fmin despite process variation. Shifting the real or resistive portion of the optimal source impedance toward the desired system impedance (typically 50 V) is the most challenging aspect of achieving a good match using integrated passives with values of Q that are low compared to discrete off-chip equivalents. This impedance component may, under a wide range of conditions, be simplified to Ropt ﬃ

2Rn ¼ Fmin 1

VT 2 þ RB Fmin 1 2IC

(4:5:11)

While Fmin, and thus the second factor in this expression, does not change with emitter finger length LE, both terms in the first factor scale inversely with this dimension, allowing the designer to target a value of Ropt as close to 50 V as is possible within limits set by additional sizing constraints such as available chip area and power budget (impacted by IC).

4.5.3 Noise Performance Overview and Trends Continuous progress in both vertical and lateral scaling as well as innovations in processing and structure have led to a steady increase in the peak fT and fMAX for the highest performance HBT at each SiGe BiCMOS lithography node [2, 3, 13–17, 19–22]. These improvements in fMAX have, in large part, stemmed from the steady reduction in normalized base resistance RB illustrated in Figure 4.5.7 and

400

Raised base

Shared base

Norm. RB (Ω-µm)

350 Normalized by LE (units : Ω-µm)

300 250 200 150 100 50 0 0.0

0.1

0.2 0.3 0.4 Lithography node (µm)

0.5

0.6

FIGURE 4.5.7 RB (normalized to emitter finger length LE) versus technology node for IBM SiGe HBTs, illustrating the improvement with generation from lateral scaling and structural innovation. (From D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-446

The Silicon Heterostructure Handbook

achieved through advancements such as the raised extrinsic base structure described elsewhere in this book [2, 3]. The fT and RB trends have reaped parallel rewards in noise performance, driving Fmin down and GA up with each generation. The result is a selection of SiGe BiCMOS technologies available to the circuit designer at a variety of cost-performance points and enabling the feasible use of silicon technology to implement noise-sensitive applications at an increasingly broader range of frequencies. The HBT performance at a given technology node is a function not only of the node, but of deliberate trade-offs designed to satisfy application requirements. A high-performance technology may not only a include a flagship HBT optimized for fT and fMAX but also additional variants trading some peak fT for other properties such as higher breakdown voltage. Furthermore, an entire technology may be tuned for a market niche, such as high-volume consumer wireless applications for which low cost is paramount over maximum performance. Noise performance varies with choice of technology node and application optimization as well (as illustrated in Figure 4.5.8) [13]. The figure plots minimum Fmin (optimized over IC bias) versus frequency for a sampling of high-performance technologies at the 0.5-, 0.18-, and 0.13-mm nodes, together with a cost-reduced variant at the 0.18-mm node. A performance range selected from commercial data sheets for the current industry low-noise favorite, the GaAs PHEMT, is also indicated for reference. With a peak fT of 45 GHz and a normalized base resistance of 400 V mm, the 0.5-mm node maintains Fmin values below 1 dB out to 5 GHz and below 2 dB out to 10 GHz. This level of performance is suitable for receiver front-ends for cost-sensitive, high-volume applications including GSM, CDMA, and 802.11b, as evidenced by the commercial availability of SiGe parts for these markets. At the 0.18-mm node, vertical scaling increases the peak fT of performance-optimized HBTs to 120 GHz while lateral scaling and process optimization reduce normalized RB by 30%, to below 280 V mm. The scaling of both parameters has a direct impact on Fmin, which decreases by more than 1 dB at 10 GHz and by more than 2 dB at 26 GHz [14]. This improvement means that Fmin remains below 1 dB at 12 GHz and below 2 dB at 23 GHz. As a result, the 0.18-mm node can address higher application frequencies while providing for greater digital content integration due to improved digital logic performance and density.

5 AE (µm2) VC (V) _________________ (0.520)2 2.0 (0.220)2 1.5 (0.124)16 1.2

Opt. Fmin (dB)

4

0.5 µm 45 GHz 0.18 µm 60 GHz

3

2

0.18 µm 120 GHz

1

0.13 µm 200 GHz GaAs PHEMT range

0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 4.5.8 HBT noise figure Fmin versus frequency for four SiGe BiCMOS technologies, including three highperformance ( fT emphasized) variants at the 0.5-, 0.18-, and 0.13-mm nodes as well as a cost-reduced (and slightly higher breakdown voltage) variant at the 0.18-mm node. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-447

Although the 0.18-mm node HBT may be tuned for high fT, cellular telephony, and wireless networking applications below 6 GHz may prioritize cost over high-frequency capability, such markets can be addressed through cost-reduced technology variants, which eliminate process steps and retune the collector doping for an application-optimized combination of peak fT and breakdown voltage. Although these modifications reduce peak fT by shifting the onset of the Kirk effect to lower IC, values of fT, and thus of Fmin, at currents below the Kirk effect onset is impacted to a much lower extent. As a result, Fmin for the cost-reduced process suffers only minor degradation (0.1 dB at 5 GHz and 0.5 dB at 26 GHz) compared with that of the high-performance process and still represents a significant advance over the 0.5-mm node. The 0.13-mm node introduces a leap in noise performance, due not only to an increase in fT to over 200 GHz but to a further 68% reduction in normalized RB to 90 V mm as well [2, 3]. This large RB improvement results in part from lateral scaling but stems primarily from a shift to a new HBT design featuring a separate, raised polysilicon layer as the extrinsic base [2]. The use of a separate layer rather than a layer shared with the intrinsic base decouples RB and CCB and allows the introduction of much more extrinsic base doping without increasing CCB and losing gain. As a result, Fmin remains below 0.4 dB beyond 12 GHz and rises to only 1.3 dB at 26.5 GHz [16, 17]. This level of performance falls within the range established using the data sheets for GaAs PHEMTs currently on the commercial market, placing silicon within one generation of this benchmark. Guidelines drawn atop the 0.13 mm data in Figure 4.5.8 highlight the frequency dependencies expected from Equation (4.5.2) and illustrated in Figure 4.5.4. Fmin is flat with frequency in the lowfrequency regime and rises linearly with frequency once f 2 exceeds f 2T /b. The flat region seems absent from the 0.5- and 0.18-mm nodes, but this is due simply to the lower fT of these nodes, which positions the regime boundary below the measured frequency range. The bias dependencies of both Fmin and associated gain GA are critical inputs to the design process. Figure 4.5.9 and Figure 4.5.10 explore the 0.18- and 0.13-mm nodes, plotting both Fmin and GA versus IC in order to compare high-performance (hollow symbols) and cost-reduced (solid symbols) variants from this important perspective [14–17]. As described analytically in Equation (4.5.6) and Equation (4.5.8), Fmin is indeed minimized at a particular bias for any given frequency, with this bias a function of frequency at low frequencies and independent of frequency at higher frequencies. Even at the highest plotted frequency of 25 GHz, this optimal collector bias for lowest Fmin in the 0.18-mm node occurs at only 5 mA, which is a mere 8% of the peak fT current for the illustrated device. This result emphasizes that noise performance is tied to low-current fT and not to peak values. Although Fmin is minimized at a unique current, associated gain rises monotonically with current. This behavior requires that the designer selects an optimal balance between achieving lowest Fmin and higher GA based on the requirements of the application. Reducing cost in the 0.18-mm node increases Fmin somewhat, with this degradation an increasing function of frequency. Since low-current fT is similar between the process variants, most of this difference is due to RB, which benefits from a more complex, self-aligned structure in the highperformance variant. Despite the modestly increased Fmin in the cost-reduced variant, however, GA is actually improved as the result of the reduced collector–base capacitance CCB that arises from reducing the collector doping to achieve higher breakdown voltage. Measuring noise at frequencies beyond 26.5 GHz is challenging and the means to do so may not yet be available on many test benches. The excellent correlation in the HBT between data and analytical prediction for Fmin versus frequency provides a means for accurate extrapolation of the data to frequencies beyond the testing boundaries, however, and thus a means for helping the designer evaluate the suitability of new technologies for emerging applications. As an example, Figure 4.5.11 plots (Fmin 1) versus frequency on a linear scale for a 0.13-mm HBT, with the axis taken out to 80 GHz and with data plotted out to 26 GHz. Fmin rises linearity with frequency above 8 GHz and is well-fit by a line using the least-squares method. The fit line may then be extended with reasonable accuracy for at least 1 to 2 octaves beyond the measured data and the resulting Fmin values expressed in dB form for more familiar reference. This method predicts Fmin values for the 0.13-mm HBT of 3.1 and 3.8 dB at 60

© 2006 by Taylor & Francis Group, LLC

4.5-448

The Silicon Heterostructure Handbook

4 Hollow: high-perf (HP) Solid: cost-reduced (CR) 3

Fmin (dB)

25 GHz 2 15 1

10

0.18 µm SiGe BiCMOS AE = (0.1820) 2

5

VCE = 1.5/2 V (HP/CR)

0 0

5

10 IC (mA)

15

20

25 5 GHz 20

GA (dB)

10 15 15 10

25

5

0 0

5

10 IC (mA)

15

20

FIGURE 4.5.9 HBT noise figure Fmin and associated gain GA versus IC at 5, 10, 15, and 26 GHz for highperformance and cost-reduced variants of 0.18-mm IBM SiGe BiCMOS technology (AE ¼ 0.18 20 2 mm2). (From DR Greenberg, D Ahlgren, G Freeman, S Subbanna, V Radisic, DS Harvey, C Webster, and L Larson. Digest IEEE MTT-S International Microwave Symposium, Boston, 2000, pp. 9–12; D Greenberg, S Sweeney, C LaMothe, K Jenkins, D Friedman, B Martin Jr, G Freeman, D Ahlgren, S Subbanna, and A Joseph. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 495–498. With permission.)

and 77 GHz, respectively [16, 17]. Such levels of performance are suitable for applications such as 60 GHz wireless LAN and 77 GHz automotive radar, opening a high-frequency regime to silicon that was once the exclusive domain of III–V devices. Recent circuit results verifying these noise figure values appear later in the chapter [40]. It is significantly more difficult to achieve noise figures close to Fmin after integrating a transistor into a circuit such as an LNA than when measuring the discrete device on the test bench. Part of this difficulty stems from the need for high Q passives to achieve the required source impedance match, especially when this match differs significantly from 50 V and resides near the outer edges of the Smith chart.

© 2006 by Taylor & Francis Group, LLC

4.5-449

Broadband Noise

0.13 µm SiGe BiCMOS AE = (0.124) 16 µm2 VCE = 1.2 V

2.5 26 GHz

Fmin (dB)

2.0 1.5

15

1.0 0.5 10 0.0 0

5

10

15

20

25

30

25

30

IC (mA) 18 16

10 GHz

14 15

GA (dB)

12 10

26

8 6 4 2 0 0

5

10

15 IC (mA)

20

FIGURE 4.5.10 Noise figure Fmin and associated gain GA versus IC at 10, 15, and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12 4 16 mm2). (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

The challenge is compounded by process variation, which introduces a random degree of mismatch into each sample. The impact of this design challenge is observed most readily when designing with FETs, which suffer from relatively high noise resistance and from largely capacitive optimum source impedances with very high real components. The HBT, however, fares much better in this regard, leading to LNA circuits that approach the measured device Fmin more closely. Figure 4.5.12 and Figure 4.5.13 illustrate the key matching parameters for a (0.2 4) 16 mm2 HBT, plotting Rn versus IC and showing Gopt in Smith chart form at 10, 15, 20, and 26 GHz [16, 17]. The very low RB at this technology node leads to correspondingly low Rn, an order of magnitude lower than observed in FETs at the same node. At the same time, Gopt remains comfortably away from the Smith chart edge, with the real portion of the optimum source impedance remaining within a factor of 5 of 50 V at the chosen device size. In practice, the LE scaling required to design a value of Ropt close to 50 V at a target application frequency is typically well within feasible limits for the SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

4.5-450

The Silicon Heterostructure Handbook

1.6 0.13 µm SiGe BiCMOS

[Fmin −1]

1.4

Est. Fmin = 3.8 dB

AE = (0.124) 16 µm2

1.2

IC = 20 mA

1.0

VCE = 1.2 V

3.1 dB

0.8 0.6 Least-squares fit

0.4 0.2 0.0 0

10

20

30 40 50 Frequency (GHz)

60

70

80

FIGURE 4.5.11 Fmin 1 (linear scale) versus frequency for a 0.13-mm IBM SiGe HBT illustrating a means for accurate extrapolation beyond the measured data and indicating Fmin estimates of 3.1 and 3.8 dB at 60 and 77 GHz, respectively. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

Noise resistance, Rn (Ω)

5 4

10 GHz

3

26

0.13 µm SiGe BiCMOS AE = (0.124) 16 µm2 VCE = 1.2 V

2 1 0 0

5

10

15 IC (mA)

20

25

30

FIGURE 4.5.12 Noise resistance Rn versus IC at 10 and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12 4 16 mm2). (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

4.5.4 Device Optimization for Low Noise SiGe HBT technologies, designed to suit the widest possible range of applications, are already achieving outstanding levels of noise performance suitable for use to beyond 60 GHz. Still, the relationships between the noise and device parameters explored in Section 4.5.2 suggest the means for optimizing noise performance even further.

© 2006 by Taylor & Francis Group, LLC

4.5-451

Broadband Noise

1.0 0.5

10 GHz

2.0

0.2

5.0

26

0.2

0.5

1.0

2.0

5.0

−5.0

−0.2

−2.0

−0.5 −1.0

FIGURE 4.5.13 Gopt bias traces on a Smith chart at 10 and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12 4 16 mm2). Position away from chart edge suggests relatively easy matching to 50 V. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

The use conditions for a modern HBT typically fall within the domain of Equation (4.5.9), which relates bias-optimized Fmin to the product of three parameters under the direct control of the device designer. At any given frequency, this Fmin can be improved by reducing RB, (CEB þ CCB) or tF, with each playing an equal role. The impact of RB on Fmin may be isolated empirically by varying the fabrication process so as to alter RB while keeping all other design parameters fixed. Figure 4.5.14 plots Fmin versus frequency for two variants of a 0.13-mm process employing a raised extrinsic base to decouple the trade-off between RB and CCB. Compared with baseline process no. 1, process no. 2 introduces significantly more extrinsic base doping and reduces RB by 40% from 140 to 85 V mm [2, 3]. This lone process improvement drops Fmin by an average of 0.3 to 0.4 dB at frequencies above 8 GHz (below which Fmin becomes too low for clean measurement) [16, 17]. Fmin may also be improved through the independent approach of reducing the several components of transit time, which limit f T at the optimal IC for lowest noise. Since Fmin occurs well below peak f T in a HBT, design choices aimed at peak f T may be traded for improved low-current f T instead. The SiGe composition profile in the base is one such design-tuning knob. In a graded-base HBT design optimized for operation at the higher currents required to reach peak f T, significant SiGe mole fraction is maintained not only through the neutral base, but into the base–collector space–charge region as well, where the composition transitions back to silicon. This positions the barrier from the steep profile retrograde within the space–charge region where it causes minimal carrier pileup and thus minimal performance impact at high IC. Although the total SiGe budget is limited by the maximum strain that can be tolerated in a base of given thickness, a noise-optimized HBT design, freed of the need to operate at high IC, can partition this budget differently and shift SiGe mole fraction from the collector side of the base toward the emitter [18]. As illustrated in the Figure 4.5.15 (inset), this creates a narrower profile, positioning the retrograde barrier closer to the neutral base but allowing for either a larger emitter–base heterojunction or, in the case of a graded-profile design, for a steeper SiGe ramp. A larger emitter–

© 2006 by Taylor & Francis Group, LLC

4.5-452

The Silicon Heterostructure Handbook

2.0 AE = (0.124) 16 µm2 VC = 1.2 V Fmin at opt. IC (dB)

1.5 Process #1: Baseline RB

1.0

0.5

Process #2: 40% RB Reduction

0.0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 4.5.14 HBT noise figure Fmin (optimized over IC) versus frequency for both baseline and low-RB variants of a 0.13-mm IBM SiGe device (noise-optimized layout with AE ¼ 0.12 4 16 mm2), indicating the improvement possible from a 40% reduction in base resistance. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

1.2

SiGe%

1.4

Control

NFmin (dB)

1.0 0.8

E-B B-C Vertical Depth

0.6 Optimized 0.4 AE = 0.5 20 2 µm2

0.2

f = 2GHz VCB = 0 V 0.0 1.0

2.0

5.0 IC (mA)

10

20

FIGURE 4.5.15 Fmin versus IC at 2 GHz comparing a graded-base SiGe HBT (AE ¼ 0.5 20 2 mm2) with control SiGe base profile with a noise-optimized device in which the SiGe base profile has been modified as per the inset. (From G Niu, S Zhang, JD Cressler, AJ Joseph, JS Fairbanks, LE Larson, CS Webster, WE Ansley, and DL Harame. IEEE Transactions on Electron Devices 47:2037–2044, 2000. With permission.)

base heterojunction can be leveraged to increase b (reducing Fmin in the low-frequency regime) or to increase intrinsic base doping and thus to decrease RB (reducing Fmin at all frequencies). A steeper SiGe ramp creates a strong quasielectric field for electrons in the base, increasing their speed and decreasing tF . Low-noise profile optimization has indeed been demonstrated. Figure 4.5.15 compares Fmin versus IC at 2 GHz for a standard high-fT (45 GHz) 0.5-mm device with a variant containing a noise-optimized graded SiGe base profile. The optimized profile reduces Fmin by as much as 0.3 dB. The data analysis presented to this point has ignored the effects of impact ionization, a source of noise included in the equivalent circuit model of Figure 4.5.2. This simplification is valid as long as the

© 2006 by Taylor & Francis Group, LLC

4.5-453

Broadband Noise

2.5 1.75 V

2.0

0V

Fmin (dB)

1.5 V

0.5 V

1.25 V

1.5

1.0 15 GHz AE = 0.1220 µm2

0.5

): VCB = 0, 0.5, 0.75, 1, 1.25, 1.5 and 1.75 V ): VCB = 0, 0.5, 1, 1.25, 1.5, 1.75 and 2 V

HP ( MP ( 0.0 0

1

2

3

4 IC (mA)

5

6

7

8

FIGURE 4.5.16 Fmin versus IC at 15 GHz for two 0.13-mm IBM SiGe HBT devices comparing a high-fT baseline device and a modified-collector variant with reduced impact ionization noise. (From DR Greenberg, S Sweeney, G Freeman, and D Ahlgren. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 113– 116. With permission.)

collector–base and collector–emitter voltages remain well below the respective two-terminal breakdown voltages BVCBO and BVCEO. As breakdown is approached, however, impact ionization can begin to contribute significantly to the noise figure. One goal in optimizing a HBT design for low noise is to suppress this phenomenon and its impact on noise. Reducing the collector doping is one approach to achieving this goal. As discussed in Section 4.5.3, lowering the collector doping decreases peak fT by shifting the onset of the Kirk effect toward lower IC yet has little impact on fT or Fmin prior to this onset. The fT for a device optimized for the least impact ionization noise should therefore peak at a value of IC at or just beyond the bias for best Fmin. Such a design minimizes the collector doping and maximizes the breakdown voltage [6]. Figure 4.5.16 plots Fmin versus IC for both a high-fT (200 GHz) HBT (with a BVCEO of 2 V) and a medium-performance (collector-doping-reduced) variant in the 0.13-mm node, comparing the noise performance as VCB is stepped from 0 to 2 V (i.e., VCE from 0.8 to 2.8 V). A reduced collector doping does create a large VCB dependence to the Kirk effect, requiring a VCB greater than 0.5 V (VCE >1.3 V) to position peak fT current beyond the optimum Fmin bias point. At larger VCB, however, Fmin for the medium-performance device maintains its value with further VCB increases while Fmin in the high-fT device degrades significantly from impact ionization, particularly at higher IC. At a VCB value of 1 V, VCE is approximately 1.8 V and thus below BVCEO. Yet, noise in the highfT HBT has already degraded measurably. By the time VCB reaches 1.75 V, impact ionization in the high-fT HBT is severe and minimum Fmin has increased by over 0.75 dB. The modified device shows no such excess noise contribution at these voltages, however, and actually enjoys improved associated gain from the reduction in CCB resulting from the lower collector doping. Thus, the high-breakdown HBT variant offered in the device libraries of many SiGe technologies, while not providing the highest peak fT, can actually be the preferred choice for low-noise operation at typical supply voltages.

4.5.5 Circuit Performance Device performance on the test bench does not always translate into performance in an integrated circuit. For example, LNA performance can be limited by the performance of available inductors which, due to their finite Q, may not always be able to achieve a noise-optimal match and which contribute noise of their own. The matching characteristics of the SiGe HBT, however, help ease good LNA design

© 2006 by Taylor & Francis Group, LLC

4.5-454

The Silicon Heterostructure Handbook

compared with those of FETs. HBT LNA noise figures, while still higher than those of the discrete device, can nevertheless come quite close. Figure 4.5.17 surveys both noise figure and gain for published or commercially available LNAs built in a variety of technology nodes ranging from 0.5 to 0.13 mm [22–39]. The results at any given node vary greatly due to differences in design priorities and the learning curve associated with design in newly available technologies. However, the bounding limits approach discrete device test bench values and demonstrate the levels of performance possible in silicon over a wide range of frequencies. At the high end of the frequency scale, an LNA noise figure of 3.8 dB has been achieved at 60 GHz, with a corresponding gain of 14.5 dB (including the impact of the bondpads) [40]. This noise figure falls within 0.7 dB of the device Fmin estimated in Figure 4.5.11. A more complete characterization of this result is shown in Figure 4.5.18, which plots the noise figure and gain as a function of frequency and presents a microphotograph of the actual measured chip.

30 25

4 3 Technology Node(µm): 0.13 0.2 0.25 0.35 0.5

2 1 0 10

20

30 40 50 Frequency (GHz)

60

70

Assoc. Gain,GA (dB)

Min. Noise Figure, Fmin (dB)

5

20 15

Technology Node(µm): 0.13 0.2 0.25 0.35 0.5

10 5 0 10

20

30 40 50 60 Frequency (GHz)

70

FIGURE 4.5.17 Noise figure and gain versus frequency for a sampling of published SiGe LNA data, illustrating the attained performance ranges for the 0.5- to 0.13-mm technology nodes. (From Refs. [22–39]. With permission.)

20

10 0.13 µm SiGe BiCMOS 60 GHz LNA

15

6 10 4

Gain (dB)

Noise Figure (dB)

8

5

2

0

0 59

60

61 62 Frequency (GHz)

63

FIGURE 4.5.18 Noise figure and gain versus frequency for a fully integrated 60 GHz LNA (complete chip, including pad parasitics) built in IBM’s 0.13-mm SiGe technology and demonstrating a sub-4 dB noise figure consistent with discrete device data extrapolation. (From S Reynolds, B Floyd, U Pfeiffer, and T Zwick. Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp. 442–443. With permission.)

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-455

4.5.6 Summary Each generation of SiGe HBT technology has leveraged scaling, process, and layout innovations to improve low-noise performance. The key contributors to these advances have been the increase in fT and decrease in RB at low to moderate current levels, factors which dovetail naturally with the drive to increase fMAX. As a result, the 0.5-mm generation has been able to penetrate the wireless telephony and networking markets in the 0.8 to 5.8 GHz bands while the latest 0.13-mm generation has demonstrated sub-4 dB performance in actual circuits in the 60 to 77 GHz regime targeted by emerging multimedia and automotive applications. Designers working on noise-sensitive systems have a choice of technology nodes with which to balance cost against performance and integration density. At the same time, the nature of the HBT as a vertical, bulk transistor has kept the device amenable to the detailed analysis and accurate modeling that has helped speed time to market through a strong record of first-pass design success. A variety of ideas have been proposed for optimizing noise still further, many of which will undoubtedly find their way into the technology as SiGe spreads out into the many untapped market niches.

Acknowledgments This chapter would not have been possible without the outstanding and invaluable contributions toward both test and hardware development by S. Sweeney, S. Parker, G. Freeman, D. Ahlgren, A. Joseph, S. St. Onge, P. Cottrell, J. Dunn, D. Harame, and each of the world-class members of IBM’s SiGe development and enablement teams.

References 1. CE Shannon. A mathematical theory of communication. Bell System Technical Journal 27:379–423, 623–656, 1948. 2. B Jagannathan, M Khater, F Pagette, J-S Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, S-J Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, and S Subbanna. Self-aligned SiGe NPN transistors with 285 GHz fMAX and 207 GHz fT in a manufacturable technology. IEEE Electron Device Letters 23:258–260, 2002. 3. A Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman Jr, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTS — expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–181. 4. W Shockley, JA Copeland, and RP James. Quantum Theory of Atoms, Molecules and the Solid State. New York, NY: Academic Press, 1966, pp. 537–563. 5. G Niu, JD Cressler, S Zhang, WE Ansley, CS Webster, and DL Harame. A unified approach to RF and microwave noise parameter modeling in bipolar transistors. IEEE Transactions on Electron Devices 48:2568–2574, 2001. 6. DR Greenberg, S Sweeney, G Freeman, and D Ahlgren. Low-noise performance near BVCEO in a 200 GHz SiGe technology at different collector design points. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 113–116. 7. SP Voinigescu, MC Maliepaard, JL Showell, GE Babcock, D Marchesan, M Schroter, P Schvan, and DL Harame. A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE Journal of Solid-State Circuits 32:1430–1439, 1997. 8. H Rothe and W Dahlke. Theory of noisy fourpoles. Proceedings of the Institute of Radio Engineers 44:811–818, 1956. 9. HA Haus, WR Atkinson, WH Fonger, WW Mcleod, GM Branch, WA Harris, EK Stodola, WB Davenport Jr, SW Harrison, and TE Talpey. Representation of noise in linear twoports. Proceedings of the Institute of Radio Engineers 48:69–74, 1960.

© 2006 by Taylor & Francis Group, LLC

4.5-456

The Silicon Heterostructure Handbook

10. O Shana’a, I Linscott, and L Tyler. Frequency-scalable SiGe bipolar RF front-end design. IEEE Journal of Solid-State Circuits 36:888–895, 2001. 11. G Niu, WE Ansley, S Zhang, JD Cressler, CS Webster, and RA Groves. Noise parameter optimization of UHV/CVD SiGe HBT’s for RF and microwave applications. IEEE Transactions on Electron Devices 46:1589–1598, 1999. 12. S Zhang, G Niu, JD Cressler, AJ Joseph, G Freeman, and DL Harame. The effects of geometric scaling on the frequency response and noise performance of SiGe HBTs. IEEE Transactions on Electron Devices 49:429–435, 2002. 13. D Greenberg. SiGe HBT Noise Performance. Workshop: High frequency noise in advanced siliconbased devices. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. 14. DR Greenberg, D Ahlgren, G Freeman, S Subbanna, V Radisic, DS Harvey, C Webster, and L Larson. HBT low noise performance in a 0.18 mm SiGe BiCMOS technology. Digest IEEE MTT-S International Microwave Symposium, Boston, 2000, pp. 9–12. 15. D Greenberg, S Sweeney, C LaMothe, K Jenkins, D Friedman, B Martin Jr, G Freeman, D Ahlgren, S Subbanna, and A Joseph. Noise performance and considerations for integrated RF/analog/mixedsignal design in a high-performance SiGe BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 495–498. 16. DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Noise performance of a low base resistance 200 GHz SiGe technology. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790. 17. D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Noise performance scaling in high-speed silicon RF technologies. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. 18. G Niu, S Zhang, JD Cressler, AJ Joseph, JS Fairbanks, LE Larson, CS Webster, WE Ansley, and DL Harame. Noise modeling and SiGe profile design trade-offs for RF applications. IEEE Transactions on Electron Devices 47:2037–2044, 2000. 19. B Mheen, D Suh, HS Kim, S-Y Lee, CW Park, SH Kim, K-H Shim, and J-Y Kang. RF performance trade-offs of SiGe HBT fabricated by reduced pressure chemical vapor deposition. Digest IEEE MTT-S International Microwave Symposium, Seattle, 2002, pp. 413–416. 20. FS Johnson, J Ai, S Dunn, B El Kareh, J Erdeljac, S John, K Benaissa, A Bellaour, B Benna, L Hodgson, G Hoffleisch, L Hutter, M Jaumann, R Jumpertz, M Mercer, M Nair, J Seitchik, C Shen, M Schiekofer, T Scharnagl, K Schimpf, U Schulz, B Staufer, L Stroth, D Tatman, M Thompson, B Williams, and K Violette. A highly manufacturable 0.25 mm RF technology utilizing a unique SiGe integration. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 56–59. 21. JG Tartarin, R Plana, M Borgarino, H Lafontaine, M Regis, O Llopis, and S Kovacic. Noise properties in SiGe BiCMOS devices. IEEE International Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications, Piscataway, 1999, pp. 131–136. 22. J Bock, TF Meister, H Knapp, D Zoschg, H Schafer, K Aufinger, M Wurzer, S Boguth, M Franosch, R Stengl, R Schreiter, M Rest, and L Treitinger. SiGe bipolar technology for mixed digital and analogue RF applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2000, pp. 745–748. 23. G Schuppener, T Harada, and Y Li. A 23 GHz low-noise amplifier in SiGe heterojunction bipolar technology. Digest IEEE Radio Frequency Integrated Circuits Symposium, Phoenix, 2001, pp. 177–180. 24. T Nakatani, J Itoh, I Imanishi, and O Ishikawa. A wide dynamic range switched-LNA in SiGe BiCMOS. Digest IEEE MTT-S International Microwave Symposium, Phoenix, 2001, pp. 281–284. 25. M Kamat, P Ye, Y He, B Agarwal, P Good, S Lloyd, and A Loke. High performance low current CDMA receiver front end using 0.18 mm SiGe BiCMOS. Digest IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 23–26. 26. A Schmidt and S Catala. A universal dual band LNA implementation in SiGe technology for wireless applications. IEEE Journal of Solid-State Circuits 36:1127–1131, 2001.

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-457

27. J Lee, G Lee, G Niu, JD Cressler, JH Kim, JC Lee, B Lee, and NY Kim. The design of SiGe HBT LNA for IMT-2000 mobile application. Digest IEEE MTT-S International Microwave Symposium, Seattle, 2002, pp. 1261–1264. 28. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. Digest IEEE GaAs Integrated Circuit Symposium, San Diego, 2003, pp. 183–186. 29. DYC Lie, J Kennedy, D Livezey, B Yang, T Robinson, N Sornin, T Beukema, LE Larson, A Senior, C Saint, J Blonski, N Swanberg, P Pawlowski, D Gonya, X Yuan, and H Zamat. A direct conversion W-CDMA front-end SiGe receiver chip. Digest IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 31–34. 30. G Zhang, A Dengi, and LR Carley. Automatic synthesis of a 2.1 GHz SiGe low noise amplifier. IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 125–128. 31. P-W Lee, H-W Chiu, T-L Hsieh, C-H Shen, G-W Huang, and S-S Lu. A SiGe low noise amplifier for 2.4/5.2/5.7GHz WLAN applications. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2003, pp. 349, 364–365. 32. P Chevalier, F De Pestel, H Ziad, M Fatkhoutdinov, J Ackaert, P Coppens, J Craninckx, S Guncer, A Pontioglu, P Tasci, F Yayil, BS Ergun, AI Kurhan, E Vestiel, E De Backer, J-L Loheac, and M Tack. An industrial 0.35 mm SiGe BiCMOS technology for 5 GHz WLAN featuring an improved selective epitaxial growth process. International Symposium on Electron Devices for Microwave and Optoelectronic Applications, Vienna, 2001, pp. 175–180. 33. B Foley, P Murphy, and A Murphy. A monolithic SiGe 5 GHz low noise amplifier and tuneable image-reject filter for wireless LAN applications. IEEE High Frequency Postgraduate Colloquium, Dublin, 2000, pp. 26–31. 34. E Imbs, I Telliez, S Detout, and Y Imbs. A low-cost-packaged 4.9–6 GHz LNA for WLAN applications. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1569–1572. 35. B Banerjee, B Matinpour, C-H Lee, S Venkataraman, S Chakraborty, and J Laskar. Development of IEEE802.11a WLAN LNA in silicon-based processes. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1573–1576. 36. J Sadowy, I Telliez, J Graffeuil, E Tournier, L Escotte, and R Plana. Low noise, high linearity, wide bandwidth amplifier using a 35 mm SiGe BiCMOS for WLAN applications. Digest IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 217–220. 37. S Chakraborty, SK Reynolds, H Ainspan, and J Laskar. Development of 5.8 GHz SiGe BiCMOS direct conversion receivers. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1551–1554. 38. J Bock, H Schafer, H Knapp, D Zoschg, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, R Stengl, and TF Meister. Sub 5 ps SiGe bipolar technology. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 763–766. 39. Y Li, M Bao, M Ferndahl, and A Cathelin. 23 GHz front-end circuits in SiGe BiCMOS technology. Digest IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 99–102. 40. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz receiver circuits in SiGe bipolar technology. Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp. 442–443.

© 2006 by Taylor & Francis Group, LLC

4.6 Microscopic Noise Simulation 4.6.1 4.6.2

Introduction............................................................... 4.6-459 Noise Source Density and Noise Propagation........ 4.6-460 Noise Source Density . Scalar and Vector Green’s Functions . Green’s Function Evaluation and Boundary Conditions . Noise Concentration

4.6.3 4.6.4

Macroscopic Input Noise . Macroscopic and Microscopic Connections . Input Noise Voltage and Current . NFmin, Yopt, and Rn

Guofu Niu Auburn University

Input Voltage and Current Noise Concentrations .......................................................... 4.6-464 A SiGe HBT Example ............................................... 4.6-465

4.6.5

Summary .................................................................... 4.6-471

4.6.1 Introduction The major noise sources in a bipolar transistor are the base resistance thermal noise, or Johnson noise, the base current shot noise, and the collector current shot noise. The base resistance thermal noise is typically described by a noise voltage with a spectral density of 4kTR, and the shot noise is described by a spectral density of 2qI, with I as the DC base current or collector current. These descriptions are based on macroscopic views. The standard derivation of the magic 2qI shot noise assumes a Poisson stream of an elementary charge q. These charges need to overcome a potential barrier, and thus flow in a completely uncorrelated manner. In a bipolar transistor, the base current shot noise 2qIB results from the flow of base majority holes across the EB junction potential barrier. The reason that IB appears in the base shot noise is that the amount of hole current overcoming the EB barrier is determined by the minority hole current in the emitter, IB. Similarly, the collector current shot noise results from the flow of emitter majority electrons over the EB junction potential barrier, and has a spectral density of 2qIC. Surprisingly, however, both the 4kTR resistor noise and the 2qI shot noise can be attributed to the same physical origin at the microscopic level — the Brownian motion of electrons and holes, also referred to as diffusion noise as the same mechanism is responsible for diffusion. The thermal motion of carriers gives rise to fluctuations of carrier velocities, and hence fluctuations of current densities. The density of such current density fluctuation is 4q2nDn according to microscopic treatment of carrier motion [1, 2]. The current density fluctuation at each location propagates toward device terminals, giving rise to device terminal voltage or current noise. The problem of noise analysis is now equivalent to solving the transfer functions of noise propagation at each location and summing over the whole device space. These transfer functions can be solved analytically for ideal transistor operation with simplified boundary conditions, or numerically for arbitrary device structures, and the latter process is referred to as microscopic noise simulation. 4.6-459 © 2006 by Taylor & Francis Group, LLC

4.6-460

The Silicon Heterostructure Handbook

Various mathematical methods have been developed, all based on the impedance field method developed by Schockley and his colleagues [1] and its various generalizations. A very satisfying early application is the successful derivation of the 4kTR Johnson noise, a macroscopic model result, from the microscopic 4q2nDn noise source density. The impedance field approach is equivalent to the Green’s function based approaches [3], which can be rigorously derived from the general master equation. Efficient numerical algorithms have been developed, which enabled the recent implementation of noise analysis in commercial device simulators, e.g., DESSIS from ISE and Taurus from TMA.

4.6.2 Noise Source Density and Noise Propagation The mathematical development of various microscopic noise simulation methods has been well treated in Refs. [4, 5]. We will focus on the aspects of using noise simulations instead. The key to successful application of microscopic noise simulation is to understand the following three concepts: 1. Noise source density, which is a measure of the local current density noise due to velocity fluctuation. This is a scalar, like the electron density, and is a function of position. 2. Vector noise transfer function, or vector Green’s function, which is the gradient of the scalar Green’s function. This is a vector like the electric field. 3. Scalar Green’s function, or scalar noise transfer function, is a ratio of the transistor terminal noise produced for a unity noise current injection into a location. All the three quantities are functions of location, like electron density n, electric field E, and potential c. We now derive the collector shot noise using ‘‘microscopic’’ theory as an example to illustrate the above concepts [6]. Like any other analytical theories, simplifying assumptions are inevitable to arrive at manageable solutions in our derivation. Many such assumptions can be removed using numerical noise simulation. We will consider one-dimensional, and neglect carrier recombination, which will necessitate including frequency in the small signal diffusion equation, in order to minimize complexity.

Noise Source Density Consider a one-dimensional semiconductor bar as shown in Figure 4.6.1. For purpose of analysis, we divide the bar into small sections. The current density is related to carrier concentration and velocity as Jn ¼ qnv,

(4:6:1)

where n is electron concentration and v is the net velocity. Because of velocity fluctuation, there is random charge transport within an incremental section. This can be equivalently described by

A

∆x x + ∆x

x

∆Jn

FIGURE 4.6.1 Equivalent circuit representation of the current density noise due to velocity fluctuations within an incremental section from x to x þ Dx.

© 2006 by Taylor & Francis Group, LLC

4.6-461

Microscopic Noise Simulation

placing a noise current source across the incremental section. A fundamental result of velocity fluctuation is that the spectrum density of the DJn fluctuation for an incremental section between x and x þ Dx is given by SDJn ¼ Kn

1 : ADx

(4:6:2)

The current density fluctuation increases with decreasing ADx, the volume of the incremental section. Here A is the cross-sectional area of the one-dimensional bar, Dx is the length of the incremental section in question, and Kn is the electron noise source density [1, 2]: Kn ¼ 4q2 nDn ,

(4:6:3)

where n is electron concentration and Dn is electron diffusivity. Equation (4.6.2) and Equation (4.6.3) are physically plausible, and consistent with our physical intuitions that statistical fluctuation increases with decreasing size, increasing diffusivity as well as increasing electron concentration. Now consider the neutral base of an ideal one-dimensional bipolar transistor. The purpose is to solve for the collector current noise resulting from current density fluctuations within all the incremental sections when the base and collector are AC shorted (as shown in Figure 4.6.2(a)).

Scalar and Vector Green’s Functions The first step is to consider the amount of JC noise resulting from the current density noise within (x, x þ Dx), DJn, the spectral density of which is described by Equation (4.6.2). This is equivalent to injecting DJn at x and extracting DJn at x þ Dx (as shown in Figure 4.6.2(b)). If we define the current gain G as the ratio of the DJn observed at Wb to a current excitation at x alone, the net DJn (Wb) can be written as DJn (Wb ) ¼ DJn G(x) DJn G(x þ Dx) ¼ DJn G 0 Dx

(4:6:4)

Neutral base ∆x x

∆JC x + ∆x

0

Wb ∆Jn (a) Neutral base

∆Jn(0)

∆Jn (Wb)

∆x x + ∆x

x 0

∆Jn

∆Jn

Wb

(b)

FIGURE 4.6.2 (a) Equivalent circuit for the the noise propagation from an incremental section (x , x þ Dx) toward the collector. (b) An alternative equivalent circuit for the noise propagation from an incremental section (x , x þ Dx) toward the collector.

© 2006 by Taylor & Francis Group, LLC

4.6-462

The Silicon Heterostructure Handbook

where G 0 dG(x)/dx is the vector Green’s function. G(x) is the scalar Green’s function. The collector current density noise is essentially DJn(Wb). Thus 2

DSJC ¼ SDJn jG 0 j Dx 2 :

(4:6:5)

Similarly, one can solve for the open-circuit noise voltage with an open-circuit boundary condition. The G(x) will then be the ratio of the voltage output at x ¼ Wb to a current excitation at x , an impedance. The vector defined by G 0 ¼ dG(x)/dx has the meaning of a field defined using the gradient of an impedance function, and is thus called impedance field. The open-circuit voltage and short-circuit current noises are equivalent to each other, similar to the equivalence between Norton and Thevenin equivalent circuits.

Green’s Function Evaluation and Boundary Conditions To evaluate G(x), we evaluate the amount of DJn (Wb) produced by an excitation DJn at x alone (as shown in Figure 4.6.3). At the neutral base boundaries, we assume that the quasi-Fermi levels remain fixed at the levels set by the applied voltages, which implies that the minority carrier concentration changes are zero: Dn(0) ¼ 0,

(4:6:6)

Dn(Wb ) ¼ 0:

(4:6:7)

To avoid confusion, we will use x 0 to denote the distance in the neutral base, and use x to denote the injection point. Assuming constant diffusivity, zero base electric field, zero recombination, the minority electron current in a homogeneous p-type base under small signal excitations can be obtained from linearization of its large signal expression as

∆n x

0

0

Wb

x

∆n (x ) ∆Jn(x ) ∆Jn(Wb)

∆Jn

∆Jn(0)

x 0

x

Wb

Neutral base ∆Jn(Wb)

∆Jn(0) x 0

∆Jn

Wb

FIGURE 4.6.3 Solution of the scalar Green’s function G(x) using an excitation of DJn at x 0 ¼ x.

© 2006 by Taylor & Francis Group, LLC

4.6-463

Microscopic Noise Simulation

DJn (x 0 ) ¼ qDn

dDn(x 0 ) , dx 0

(4:6:8)

DJn (x 0 ) is constant from x 0 ¼ 0 to x as there is no recombination, and must be equal to DJn(0). Using Equation (4.6.6) and integrating Equation (4.6.8) from 0 to x, DJn (0) (x 0) ¼ qDn ½Dn(x) 0:

(4:6:9)

DJn(0) is now related to Dn(x): DJn (0) ¼

qDn Dn(x) : x

(4:6:10)

Similarly, DJn (x 0 ) is constant from x to Wb, and must be equal to DJn(Wb). Using Equation (4.6.7) and integrating Equation (4.6.8) from x 0 ¼ x to Wb , DJn (Wb ) (Wb x) ¼ qDn ½0 Dn(x);

(4:6:11)

DJn(Wb) is thus obtained as DJn (Wb ) ¼

qDn Dn(x) : Wb x

(4:6:12)

A sudden change from DJn (0) to DJn (Wb) occurs at x 0 ¼ x, because of the DJn injection: DJn ¼ DJn (Wb ) DJn (0) ¼ qDn ( 1)Dn(x)

1 1 þ : Wb x x

(4:6:13)

Using Equation (4.6.12) and Equation (4.6.13), G(x) is obtained as

DJn (Wb ) G(x) ¼ ¼ DJn

1 x Wb x : ¼ 1 1 Wb þ Wb x x

(4:6:14)

We note that G(x) is dimensionless, as it represents a current gain. In this case, G(x) is simply x/Wb. In general, however, G(x) is a frequency-dependent complex number. G 0 is readily evaluated as G 0 (x) ¼

dG(x) 1 ¼ : dx Wb

(4:6:15)

G 0 (x) is position-independent in this case, and therefore, the final noise for each section is determined by the noise source density. Recall that the spectral density of DJn for the incremental section (x, xþDx) is given by Equation (4.6.2), which is rewritten as SDJn ¼ 4q2 Dn n(x)

© 2006 by Taylor & Francis Group, LLC

1 : ADx

(4:6:16)

4.6-464

The Silicon Heterostructure Handbook

Substituting Equation (4.6.16) and Equation (4.6.15) into Equation (4.6.5), DSJC ¼ 4q2 Dn n(x)

1 1 Dx: A Wb2

(4:6:17)

Replacing Dx by dx, and integrating from 0 to Wb, one obtains the total noise SJC as SJ C ¼ ¼

ð Wd dSJC 0 ð Wb

4q2 Dn n(x)

0

1 1 dx A Wb2

ð 1 1 Wb 1 1 n(0) Wb n(x)dx ¼ 4q2 Dn 2 A Wb 0 A Wb2 2 qDn n(0) 1 1 ¼ 2qJC ¼ 2q Wb A A ¼ 4q2 Dn

(4:6:18)

where we used: JC ¼

qDn n(0) , Wb

(4:6:19)

a direct result of linear minority carrier distribution in an ideal bipolar transistor. JC is related to IC by IC ¼ AJC, thus: SIC ¼ A2 SJC ¼ 2qIC :

(4:6:20)

The base current shot noise can be derived in the same manner: SIB ¼ 2qIB :

(4:6:21)

Noise Concentration In practice, one may only be interested in the terminal noise produced by a unit volume at a given location, that is, dSJC/dx in our one-dimensional bipolar example. Just like one can calculate the total number of electrons in the device by integrating electron concentration, one can calculate the total terminal noise current or voltage by integrating the noise concentration. A plot of the noise concentration immediately shows where most of the noise comes from within the physical structure of the device. Obviously, if one desires to understand the details of the noise concentration plot, one would have to examine the noise source density and the Green’s functions.

4.6.3 Input Voltage and Current Noise Concentrations The results of microscopic noise simulation are typically given for either the open-circuit noise voltages or the short-circuit noise currents. However, for noise optimization, the input noise current and voltage for a chain representation are the most convenient, and directly relate to NFmin, Yopt, and Rn. The microscopic noise concentrations for the input noise current, voltage, and their correlation Sia, Sva, and Sia va* facilitate identification of major noise sources within the transistor physical structure, leading to device-level optimization (e.g., doping profile, Ge profile, and device layout) with respect to the noise parameters, and can be obtained as follows [7].

© 2006 by Taylor & Francis Group, LLC

4.6-465

Microscopic Noise Simulation

Consider the transistor as a noisy linear two port. The open-circuit noise voltage parameters are obtained by integrating the ‘‘noise concentration’’ over the device volume Sn ¼

ð CSn dV;

(4:6:22)

V

where n is v1, v2, or v1v*2. For instance CSv 1 is the ‘‘concentration’’ (volume density) of Sv1 , and has a unit of V2/Hz/cm3. CSv 1CSv 2 and CSv * are solved in TCAD tools, including DESSIS and TAURUS [8, 9]. In 1 v2 principle, the boundary conditions can be modified to directly solve for the ‘‘concentration’’ of the chain representation noise parameters Sia, Sva, and Sia va* . This, however, has not been implemented in device simulators. The problem can be circumvented by postprocessing of CSv 1 , CSv 2 , and CSv v* which requires 1 2 no code development by TCAD vendors [7]: "

CSva C Si v * a a

C Sv i * a a C Si a

#

"

CSv1 ¼ T: C Sv * 2v1

# C Sv * 1 v2 T y; C Sv 2

(4:6:23)

where T¼

1 0

A11 , A21

(4:6:24)

where A11 and A21 are elements of the ABCD parameter matrix A. T y is the transposed conjugate of T. Integration of the obtained chain representation noise concentrations CSv a , CSi a , and CSi a v *a over the whole device gives the transistor Sva, Sia, and Sia va* , respectively. Each noise concentration consists of an electron contribution and a hole contribution, which account for electron and hole velocity fluctuations, respectively.

4.6.4 A SiGe HBT Example One major benefit of simulation is that it offers insight into internal device operation, which can be used to develop better compact model. The same principle applies to noise simulation and noise modeling. We now examine the classical bipolar transistor noise model using the simulation results as a reference for a SiGe HBT.

Macroscopic Input Noise Figure 4.6.4(a) and (b) shows the chain representation and an equivalent circuit containing the main macroscopic noise sources, respectively. Through noise-circuit analysis, Sva, Sia, and Sia va* are obtained as [10] Sva ¼

2qIC þ 2qIB rb2 þ 4kTrb , jY21 j2 2qIC , jh21 j2

(4:6:26)

Y11 þ 2qIB rb , jY21 j2

(4:6:27)

Sia ¼ 2qIB þ Sia va* ¼ 2qIC

© 2006 by Taylor & Francis Group, LLC

(4:6:25)

4.6-466

The Silicon Heterostructure Handbook

where h21 ¼ Y21/Y11. The Y parameters are for the whole transistor that includes both rb and the intrinsic transistor.

Macroscopic and Microscopic Connections The 4kTrb terms in the model equations account for velocity fluctuations of holes in the base. One can therefore compare the 4kTrb related terms with the integration of the base hole noise concentration. Similarly, the 2qIB terms account for emitter minority hole velocity fluctuation, and the 2qIC terms account for base minority electron velocity fluctuation [4]. Thus, connections between compact noise model and microscopic noise simulation can be established for Sva, Sia, and Sia va* , as shown in Table 4.6.1. Here the superscripts e and h stand for electron and hole contributions, respectively.

Input Noise Voltage and Current Figure 4.6.5(a) compares the modeled and simulated Sva, Svea , and Svha for JC ¼ 0.05 mA/mm2. Svea dominates over Svha . The model slightly underestimates Svea , and significantly underestimates Svha . The simulated Svea and Svha are both frequency dependent. Despite inaccurate modeling of Svha , the total Sva is well modeled, because of the dominance of Svea . At a higher JC of 0.65 mA/mm2, however, the hole contribution dominates over the electron contribution, as shown in Figure 4.6.5(b). With increasing JC, Svea decreases, while Svha stays about the same. The model underestimates Svha , and overestimates Svea . Observe that the simulated Svha is frequency dependent, while the modeled Svha (4kTrb) is frequency independent. Figure 4.6.6 and Figure 4.6.7 show the electron and hole noise concentration contours at 2 GHz (CSev a and CShv a ) at JC ¼ 0.65 mA/mm2. Both CSev a and CShv a are the highest in the SiGe base, indicating that transistor Sva mainly comes from the SiGe base. This provides guidelines to future noise model

I1

Va

I2 Noiseless two-port

+ V1

Ia

Y

_

I1 +

rb

I2

+

+ 2qIB

V2

V1

_

_

(a)

FIGURE 4.6.4

4kTrb

Intrinsic BJT

2qIC V2 _

(b)

(a) Chain representation of a noisy two-port. (b) The essence of noise modeling used in CAD tools.

TABLE 4.6.1

Connections between Noise Modeling and Simulation Model

Svea

2qIC/jY21j2

Svha

2qIBr2b

Siea

4kTrb 2qIC/jh21j2

Siha Siea va*

2qIB 2qICY11/jY21j2

Siha va*

2qIBrb

© 2006 by Taylor & Francis Group, LLC

Simulation Ð e base CSv a dV Ð h emitter CSv a dV Ð C h dV Ð base Sev a base CSi a dV Ð C h dV Ð emitter e Si a base CSia v * dV a Ð h emitter CSia v * dV a

4.6-467

Microscopic Noise Simulation

1017 Impedance Field Simulation Compact Noise Model

Total

Total (V2/Hz)

(V2/Hz)

1016

S va, S eva, and S hva

S va, S eva, and S hva

Electron contribution

JC = 0.05 mA/µm2

Hole contribution

1017

Hole contribution

Electron contribution

JC = 0.65 mA/µm2 Impedance Field Simulation Compact Noise Model

1018 5

10 15 Freq (GHz)

20

5

10 15 Freq (GHz)

(a)

FIGURE 4.6.5 Sva,

Svea ,

and

Svha

20

(b) 2

versus frequency at (a) JC ¼ 0.05 mA/mm . (b) JC ¼ 0.65 mA/mm2.

−0.1 0 0.1

E

Y (mm)

0.2

B

0.3 SvaConc. (V2/Hz/cm3)

0.4 0.5 0.6

1.13714341E-04 9.18461982E-05 6.99780558E-05 4.81099134E-05 2.62417709E-05 4.37362849E-06

C Electron contribution JC = 0.65 mA/µm2

0.7

1.5

2 X (mm)

FIGURE 4.6.6.

Two-dimensional distribution of CSeva (2 GHz, JC ¼ 0.65 mA/mm2).

development, that is, the transistor noise mainly originates from the EB junction. In the intrinsic base, and along the x-direction, CSev a is uniform, while CShv a is highly nonuniform, and shows a strong ‘‘base noise crowding’’ effect. Figure 4.6.8(a) shows the integrals of CSev a in the base, emitter, collector, and p-substrate, together with the 2qIC related term in the model at JC ¼ 0.65 mA/mm2. The model accounts for only the base contribution, which is reasonable, since the simulated base electron contribution overwhelmingly

© 2006 by Taylor & Francis Group, LLC

4.6-468

The Silicon Heterostructure Handbook −0.1 0 0.1

E

Y (mm)

0.2

B

0.3 SvaConc. (V2/Hz/cm3) 0.4

C

3.13664075E-04 2.53344060E-04 1.93024046E-04 1.32704032E-04 7.23840172E-05 1.20640029E-05

0.5 0.6

Hole contribution Jc = 0.65 mA/µm2

0.7

1.5

2 X (mm)

FIGURE 4.6.7.

Two-dimensional distribution of CShv a (2 GHz, JC ¼ 0.65 mA/mm2).

10−17

10−17

10−18

(V2/Hz)

10−19 Emitter electrons

10−20

10−21 Collector electrons

Base electrons Emitter electrons Collector electrons Substrate electrons 2qIC/IY21I2 0

5

Emitter holes

2qIBrb2 Collector holes

JC = 0.65 mA/µm2 Substrate holes

10−22

10−23

10−26

10−19

10−21

Substrate electrons

10−24

4kTrb

10−20

JC = 0.65 mA/µm2

10−22

Base holes

10−18

2qIC/|Y21|2

Regional contributions of S hva

Regional contributions of S eva

(V2/Hz)

Base electrons

10 Freq (GHz)

15

Base holes Emitter holes Collector holes Substrate holes 4kTrb2 2qIBrb

10−23

10−24

20

0

5

10 Freq (GHz)

(a)

FIGURE 4.6.8 Regional contributions of

© 2006 by Taylor & Francis Group, LLC

(b)

Svea

(a) and

Svha

2

(b) at JC ¼ 0.65 mA/mm .

15

20

4.6-469

Microscopic Noise Simulation

dominates over other electron contributions. The 2qIC description, however, overestimates Svea , and thus a better description is required. Figure 4.6.8(b) shows the integrals of CShv a in the base, emitter, collector, and p-substrate. Also shown are the 2qIB (emitter holes) and 4kTrb (base holes) related terms accounted for in the model. The collector and substrate hole noises are indeed negligible. The noise from the base majority holes dominates over the noise from the emitter minority holes. The base majority hole noise contribution is less than predicted by 4kTrb, and frequency dependent as well. The noise from the emitter minority holes increases with frequency, and is underestimated by 2qIB related term. Figure 4.6.9(a) compares modeled and simulated Sia, Siea , and Siha for JC ¼ 0.05 mA/mm2. Siea decreases with frequency and is slightly underestimated (by the model). Siha increases dramatically with frequency, and is significantly underestimated. At a higher JC of 0.65 mA/mm2, however, the Siea discrepancy between model and simulation becomes much more pronounced (as shown in Figure 4.6.9(b)). Thus, for Sia, 2qIC is not a good description for base minority electron noise. Like for Svha , the frequency dependence for Siha is not accounted for in the model. Siha dominates at lower frequencies, while Siea becomes dominant at higher frequencies. Figure 4.6.10(a) shows the integrals of CSei a in the base, emitter, collector, and p-substrate. JC ¼ 0.65 mA/mm2. The model only accounts for the base electron contribution, a 2qIC/jh21j2 term. Like for other noise parameters, the base minority electron contribution for Siea is poorly modeled by the 2qIC related term. Figure 4.6.10(b) shows the regional contributions of Siha . The model accounts for only the emitter hole contribution through the 2qIB term. Even though the collector and substrate hole contributions are indeed negligible, the base hole contribution is not negligible at higher frequencies. This emitter contribution constitutes the main discrepancy for the total Siha between modeling and simulation, and shows frequency dependence.

Impedance Field Simulation Compact Noise Model

JC = 0.65 mA/µm2

Total

1023

Sia, S eia, and S hia (A2/Hz)

Sia, S eia, and S hia (A2/Hz)

1023

Electron contribution

1024

Total

Hole contribution

1024

1025 JC = 0.05 mA/µm2

Electron contribution

Hole contribution Impedance Field Simulation Compact Noise Model

1026 5

10 15 Freq (GHz) (a)

20

5

10 15 Freq (GHz) (b)

FIGURE 4.6.9 Sia, Siea , and Siha versus frequency at (a) JC ¼ 0.05 mA/mm2. (b) JC ¼ 0.65 mA/mm2.

© 2006 by Taylor & Francis Group, LLC

20

4.6-470

The Silicon Heterostructure Handbook

10−23

10−22 2qIC/|h21|2

10−23

10−24

Emitter holes

Base electrons

10−25 10−26

Regional contributions of S hia (A2/Hz)

Regional contributions of S hia (A2/Hz)

10−24

Emitter electrons

10−27

JC = 0.65 mA/µm2 Collector electrons

10−28

Substrate electrons

10−29

2qIB

10−25 Base holes

10−26

JC = 0.65 mA/µm2

10−27

substrate holes

10−28 Collector holes

10−29

10−30 base electrons emitter electrons collector electrons substrate electrons 2qIC/|h21|2

10−31 10−32

0

5

10 Freq (GHz)

15

base holes emitter holes collector holes substrate holes 2qIB

10−30

20

10−31

0

5

10 Freq (GHz)

(a)

FIGURE 4.6.10.

15

20

(b)

Regional contributions of

Siea

(a) and

Siha

2

(b) at JC ¼ 0.65 mA/mm .

Similar analysis can be performed for Sia va* . The results also show that the noise from the base minority electrons is poorly described by the model. Similar problems exist with 4kTrb description of the base hole noise, and 2qIC description of the base minority electron noise.

NFmin, Yopt, and Rn NFmin, Yopt, and Rn are obtained from Sva, Sia, and Sia va* by [11] qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 3 Sva Sia ½I(Sia va* )2 þ R(Sia va* ) 5, ¼ 10 log41 þ 2kT 2

NFmin

Yopt

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ I(Sia va* ) 2 R(Sia va* ) Si a ¼ , j Sva Sva Sva Rn ¼ Sva =4kT :

(4:6:28)

(4:6:29) (4:6:30)

To compare the impact of electron and hole noise on circuit-level noise parameters, we examine NFemin and NFhmin, defined as the NFmin that the transistor would have when only electron velocity or only hole velocity fluctuates, respectively. NFemin is obtained by substituting Svea , Siea , and Siea va* into Equation (4.6.7). NFhmin is obtained similarly. Since NFmin is not a linear function of Sva, Sia, and Sia va* , e is similarly defined and obtained by substituting Svea , Siea , and Siea va* into NFmin 6¼ NFemin þ NFhmin. Y opt e h þ Y opt . Equation (4.6.8). Like NFmin, Yopt 6¼ Y opt

© 2006 by Taylor & Francis Group, LLC

4.6-471

Microscopic Noise Simulation

550

Impedance Field Simulation Compact Noise Model

Impedance Field Simulation Compact Noise Model

6

JC = 0.65 mA/µm2

JC = 0.65 mA/µm2

500

h NFmin, NFmin, and NFmin (dB)

400 350

Rhn

4 NFmin

e

Rn, Rne , and Rnh (Ω)

5

Rn

450

300 250

3

2

200 Rne

150

h NFmin

1 e NFmin

100 5

10 Freq (GHz) (a)

15

20

5

10 Freq (GHz) (b)

15

20

FIGURE 4.6.11 (a) Rn. (b) NFmin. JC ¼ 0.65 mA/mm2.

Figure 4.6.11(a) shows the simulated and modeled Rn, Ren, and Rhn for JC ¼ 0.65 mA/mm2. Figure 4.6.11(b) shows the modeled and simulated NFmin, NFemin, and NFhmin, also for JC ¼ 0.65 mA/mm2. Since Rn ¼ Sva/4kT, which is a linear function, Rn ¼ Ren þ Rhn. The problems with Sva modeling directly translate into Rn inaccuracy. Both NFmin and NFemin are overestimated by the model, and the discrepancies increase dramatically with frequency. NFhmin is poorly modeled. Note that the frequency dependence of NFhmin is not modeled. Figure 4.6.12(a) and (b) shows the real and imaginary parts of Yopt for JC ¼ 0.65 mA/mm2. Neither e h or Y opt is well modeled. The discrepancies increase with frequency. The frequency Yopt nor Y opt h dependence of Y opt is not accounted for by the model. The discrepancies of Rn, NFmin, and Yopt are all fundamentally caused by the inaccurate modeling of Sva, Sia, and Sia va* . In particular, the description of base minority electron noise using 2qIC is clearly responsible for the inaccuracy of the electron contributions, and the description of base majority hole noise using 4kTrb is responsible for the inaccuracy of the hole contributions.

4.6.5 Summary We have presented an overview of the concepts related to microscopic noise analysis. The key concepts involved are the noise source density, and the scalar and vector Green’s functions that describe noise propagation. These concepts are illustrated using analytical treatment of the collector current shot noise. Two-dimensional microscopic noise simulation results on a SiGe HBT are presented, and used to examine the validity of the widely used macroscopic transistor noise model.

© 2006 by Taylor & Francis Group, LLC

4.6-472

The Silicon Heterostructure Handbook

103 Impedance Field Simulation Compact Noise Model

2

0 h ℑ(Yopt )

JC = 0.65 mA/µm2 e h ℑ(Yopt ), ℑ(Yopt ), and ℑ(Yopt ) (Ω1)

2

ℜ(Yopt)

1.6

h

ℜ(Yopt), ℜ(Yopt), and ℜ(Yopt) (Ω1)

1.8

104

1.4

e

1.2

1

0.8

h ) ℜ(Yopt

6

8

e

ℑ(Yopt) 10

e

16 10

JC = 0.65 mA/µm2

14

ℜ(Yopt) 5

15

20

Impedance Field Simulation Compact Noise Model 5

Freq (GHz)

10

15

20

Freq (GHz)

(a)

FIGURE 4.6.12.

ℑ(Yopt)

12

0.6

0.4

4

(b) 2

(a) R(Yopt). (b) I(Yopt). JC ¼ 0.65 mA/mm .

Acknowledgments The author would like to thank Y. Cui for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ-1133.

References 1. W Shockley, J Copeland, and R James. The impedance field method of noise calculation in active semiconductor devices. Quantum Theory of Atoms, Molecules, and the Solid-State. Academic Press, New York, 1966, pp. 537–563. 2. A van der Ziel and KM van Vliet. H.f. thermal noise in space-charge limited solid state diodes — II. Solid-State Electron. 11:508–509, 1968. 3. KM van Vliet. General transistor theory of noise in PN junction-like devices — I. Three-dimensional Green’s function formulation. Solid-State Electron. 15:1033–1053, 1972. 4. F Bonani, G Ghione, M Pinto, and R Smith. An efficient approach to noise analysis through multidimensional physics-based models. IEEE Trans. Electron Dev. 45:261–269, 1998. 5. F Bonani and G Ghione. Noise in Semiconductor Devices: Modeling and Simulation. Springer-Verlag, Heidelberg, 2001. 6. GF Niu. Bridging the gap between microscopic and macroscopic theories of noise in bipolar junction transistors. Tech. Digest of IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. pp. 227–230, 2004.

© 2006 by Taylor & Francis Group, LLC

Microscopic Noise Simulation

4.6-473

7. Y Cui, GF Niu, Y Shi, and DL Harame. Spatial distribution of microscopic noise contributions in SiGe HBT. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, April 2003, pp. 170–173. 8. DESSIS device simulator. ISE Integrated Systems Engineering. 9. TAURUS-DEVICE simulator. Synopsys, Inc. 10. Y Cui, GF Niu, and DL Harame. An examination of bipolar transistor noise modeling and noise physics using microscopic noise simulation. Proceedings of the IEEE BCTM, September 2003, pp. 225–228. 11. HA Haus. Representation of noise in linear twoports. Proc. IRE 48:69–74, 1960.

© 2006 by Taylor & Francis Group, LLC

4.7 Linearity 4.7.1 4.7.2 4.7.3 4.7.4

Identifying Dominant Nonlinearity . Collector Current Dependence . Collector Voltage Dependence . Load Dependence and Nonlinearity Cancellation . Linearity Limiting Factors

Guofu Niu Auburn University

Introduction............................................................... 4.7-475 Basic Concepts........................................................... 4.7-476 Physical Nonlinearities.............................................. 4.7-479 Volterra Series Linearity Analysis............................. 4.7-480

4.7.5

Summary .................................................................... 4.7-485

4.7.1 Introduction ‘‘Linearity’’ is the counterpart of ‘‘distortion,’’ or ‘‘nonlinearity,’’ and refers to the ability of a device, circuit, or system to amplify input signals in a linear fashion. SiGe HBTs, like other semiconductor devices, are in general nonlinear elements. Most obviously, the collector current IC depends on the base– emitter voltage VBE exponentially, common to all bipolar transistors. This exponential I–V relation in fact represents the strongest nonlinearity found in nature, and underlies the ‘‘translinear principle,’’ which enables a large variety of linear and nonlinear functions to be realized using bipolar transistors. Despite our intuition, the distortion in translinear circuits is not caused by the exponential IC –VBE relationship, but rather is due to the departure from it, by various means (i.e., series resistance, high-level injection, impact ionization, early effect, and inverse early effect). SiGe HBTs can be used to build both ‘‘nonlinear’’ and ‘‘linear’’ circuits depending on the required application and the circuit topology used. In fact, transistor nonlinearity is both a blessing and a curse. Nonlinearity can be a blessing because we need nonlinearity to realize frequency translation; but can also be a curse, because it creates distortion in the various signals we are interested in preserving, amplifying, or transmitting. For instance, nonlinearity causes intermodulation (IM) of two adjacent strongly interfering signals at the input of a receiver, which can corrupt the nearby (desired) weak signal we are trying to receive. In the transmit path, nonlinearity in power amplifiers clips the large amplitude input, which causes power leaking (and thus interference) to adjacent channels in digitally modulated signals. Perhaps surprisingly, SiGe HBTs exhibit excellent linearity in both small-signal (e.g., LNA) and largesignal (e.g., PA) RF circuits, despite their strong I–V and C–V nonlinearities. Clearly, the overall circuit linearity strongly depends on the interaction (and potential cancellation) between the various I–V and C–V nonlinearities, the linear elements in the device, as well as the source termination, the load termination, and any feedback present, intentional or parasitic. These issues can be best understood using Volterra series [1–3], a powerful formalism for analysis of nonlinear systems. In this chapter, we focus on the intermodulation linearity of SiGe HBTs, a major concern in RF circuits.

4.7-475 © 2006 by Taylor & Francis Group, LLC

4.7-476

The Silicon Heterostructure Handbook

4.7.2 Basic Concepts We first introduce basic nonlinearity concepts using simple power series, which strictly speaking only applies to a memory-less circuit. Under small-signal input, the output voltage y(t) is related to its input voltage x(t) by y(t) ¼ k1 x(t) þ k2 x 2 (t) þ k3 x 3 (t):

(4:7:1)

Consider a two-tone input x(t) ¼ A cos v1t þ A cos v2t. The output has not only harmonics of v1 and v2, but also ‘‘intermodulation products’’ at 2v1 v2 and 2v2 v1. A full expansion of Equation (4.7.1) shows that the output contains signals at v1, v2, 2v1, 2v2, 3v1, 3v2, v1 þ v2, v1 v2, 2v2 v1, 2v2 þ v1, 2v1 v2, and 2v1 þ v2. When v1 and v2 are closely spaced, the third-order intermodulation products at 2v2 v1 and 2v1 v2 are the major concerns, because they are close to v1 and v2, and thus within the amplifier bandwidth. Consider a weak desired signal channel, and two nearby strong interferers at the input. One intermodulation product falls in band, and corrupts the desired component (as illustrated in Figure 4.7.1). The fundamental signal and intermodulation products in the output are given by y(t) ¼

3k3 A3 3k3 A3 3k3 A3 þ cos v1 t þ þ cos (2v2 v1 )t k1 A þ 4 2 4 þ fundamental intermodulation:

(4:7:2)

The ratio of the amplitude of the IM product to the amplitude of the fundamental output is defined as the ‘‘third-order intermodulation distortion’’ (IM3). Neglecting the higher order terms added to k1A, one has IM3 ¼

f1

f2

3k3 A3 4

k1 A ¼

3 k3 2 A: 4 k1

(4:7:3)

IM3

2f 2−f 1

FIGURE 4.7.1 Illustration of the corruption of desired signals by the intermodulation product of two strong interferers.

© 2006 by Taylor & Francis Group, LLC

4.7-477

Linearity

For small A, the fundamental output at v1 grows linearly with A, while the IM product at 2v2 v1 grows as A3. A 1-dB increase in the input results in a 1-dB increase of fundamental output, but a 3-dB increase of IM product. The extrapolation of the fundamental output and the IM3 versus the input intersect at a given input level, which is defined as the input third-order intercept point (IIP3). IIP3 is obtained from Equation (4.7.3) by letting IM3 ¼ 1 sﬃﬃﬃﬃﬃﬃﬃﬃ 4 k1 : IIP3 ¼ 3 k3

(4:7:4)

IIP3 is a widely used figure-of-merit because it does not depend on the input signal level. Because IM3 grows with A2 (Equation (4.7.3)), IIP3 can be measured at a single input level A0, IIP32 ¼

A20 , IM30

(4:7:5)

where IM30 is the measured relative intermodulation distortion. Note that IIP3 and A0 are voltages, and thus IIP32 and A20 are measures of power. Taking 10 log on both sides, one has 20 log IIP3 ¼ 20 log A0 10 log IM30 :

(4:7:6)

Here, 20 log IIP3 is the power expressed in dB at the intercept point, and 20 log A0 is now the input power level expressed in dB. The reference power level does not enter into the equation. Now Equation (4.7.6) can be rewritten in terms of power 1 PIIP3 ¼ Pin þ ðPo,1st Po,3rd Þ 2

(4:7:7)

1 POIP3 ¼ Po,1st þ ðPo,1st Po,3rd Þ: 2

(4:7:8)

and

In practice, IIP3 and OIP3 are used to denote the power at the intercept point. The IP3 data in commercial load-pull systems and CAD tools (e.g., ADS) are defined for each input power level according to the equations above. The following is the sample output of a load-pull measurement on a SiGe HBT amplifier. The two tones are at 2.000 and 2.001 GHz (i.e., 1-MHz spacing).

Pin (dB m) 30.00 29.00 28.00 27.00 26.00 25.00 24.00 23.00 22.00

© 2006 by Taylor & Francis Group, LLC

Pout,1st (dB m)

Gain (dB)

Pout,3rd (dB m)

POIP3 (dB m)

11.72 10.75 9.74 8.74 7.72 6.77 5.74 4.73 3.75

18.28 18.25 18.26 18.26 18.28 18.23 18.26 18.27 18.25

74.48 72.68 69.91 67.24 64.89 62.28 59.57 57.15 54.66

19.65 20.20 20.35 20.51 20.87 20.98 21.18 21.47 21.71

4.7-478

The Silicon Heterostructure Handbook

Frequency Source state Source imp. Load state Load imp. Vc Vb Date Time

2.00 GHz 1; #377 0.20–170.1 1; #550 0.70–14.9 3.001 V 0.816 V April 30, 1998 16:22:43

Figure 4.7.2 shows the measured fundamental and third-order IM product power versus input power data for the above SiGe HBT amplifier, along with gain. The measured slope of the IM product curve deviates from 3:1, because of the ‘‘high’’ input power level used in the measurement. As a result, the IP3 numbers measured at different input powers are different, as can be seen from the data output. One would obtain an OIP3 of 35 dB m by simply extrapolating the linear portions of the measured Pout,1st and Pout,3rd data. The OIP3 based on a theoretical 3:1 slope at Pin ¼ 30 dB m is only 20 dB m, however, and therefore, caution must be exercised in interpreting the IP3 numbers. The gain compression at very high input power level can also be clearly seen here. Clearly IIP3 is an important figure-of-merit for front-end RF–microwave low-noise amplifiers, because they must contend with a variety of signals coming from the antenna. The interfering signals are often much stronger than the desired signal, thus generating strong intermodulation products that can corrupt the weak but desired signal. To some extent, IIP3 is a measure of the ability of a handset, for instance, not to ‘‘drop’’ a phone call in a crowded environment. For many LNA applications, IIP3 is just as important (if not more so) as the noise figure. The dc power consumption must also be kept very low because the LNA is likely to be continuously listening for transmitted signals of interest and hence continuously draining power. The power consumption aspect is taken into account by another figure-of-merit, the linearity efficiency, which is defined as IIP3/Pdc, where Pdc is the dc power dissipation. First-generation SiGe HBTs typically exhibit excellent linearity efficiencies above 10, which is competitive with III–V technologies. We note, however, that IIP3/Pdc is not adequate for describing the Class AB operating mode for transistors in the driver and output stage of power amplifiers [4].

40

20

Gain

0 15 −20

Pout,1st

−40 −60 80 −40

Pout,3rd

−30

10

IC = 3 mA VCE = 3 V AE = 0.5⫻20⫻4 µm2 SiGe HBT 2 GHz −20 −10 P in (dBm)

0

Gain (dB)

Pout (dBm)

20

25

5 0 10

FIGURE 4.7.2 A typical Pout versus Pin curve for a first generation SiGe HBT (IC ¼ 3 mA and VCE ¼ 3 V). The input power at the 1-dB compression point is 3 dB m.

© 2006 by Taylor & Francis Group, LLC

4.7-479

Linearity

4.7.3 Physical Nonlinearities The major physical nonlinearities in a SiGe HBT are depicted in Figure 4.7.3, including: 1. ICE, the collector current transported from the emitter, ICE / exp(VBE/VT). 2. IBE, the hole injection current into the emitter. IBE tracks ICE through IBE ¼ ICE/b. 3. ICB, the avalanche multiplication current, and is a strong nonlinear function of both VBE and VCB [5]. The nonlinearity due to ICB can be minimized using a low VCB. 4. CBE, the EB junction capacitance, including the diffusion capacitance and depletion capacitance. CBE tracks ICE at high JC because diffusion charge is in proportion to the transport current ICE. 5. CCB, the CB junction capacitance. CCB is much smaller than CBE, because of reverse bias on the CB junction. The feedback position, however, makes CCB important for circuit linearity. A medium value VCB that makes CCB more linear and keeps the avalanche (breakdown) current ICB small is optimum for linearity [6]. Both the value and the bias dependence of CCB matter for the overall transistor linearity [7]. Among all the nonlinearities, the ICE–VBE nonlinearity often dominates in RF circuits. For relatively weak input signal, the nonlinear ICE–VBE relation can be approximated by a Taylor expansion. A direct consequence of the ICE–VCE nonlinearity is to make the effective transconductance a function of vbe (as opposed to a constant in a linear circuit) 0

gm,eff

1 nonlinear contributions zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ B C 2 ic 1 vbe 1 vbe B C ¼ ¼ gm B1 þ þ þ . . .C: 2 @ A 2 Vt 6 Vt vbe

(4:7:9)

Equation (4.7.9) indicates that the nonlinear contributions to gm,eff increase with the voltage drop across the EB junction vbe. In typical bipolar amplifiers, vbe decreases with increasing biasing current, making

(1-XCJC)CBC XCJC CBC

RB

ICB (VBE,VCB)

RC C

IBE(VBE)

CBE

ICE(VBE,VCB)

B

RE CBE - EB capacitance CBC - CB capacitance CCS - CS capacitance

CCS

Substrate ICB - Avalanche multiplication

E

ICE - Transport current IBE - Hole injection into emitter

FIGURE 4.7.3 Nonlinear I–V and C–V relations in a bipolar transistor.

© 2006 by Taylor & Francis Group, LLC

4.7-480

The Silicon Heterostructure Handbook

gm,eff closer to a constant like in a linear circuit. Linearity of bipolar circuits can therefore be improved by increasing the biasing current. The expense is, however, increased power consumption. Parasitic or intentionally used emitter resistance or inductance also helps improving linearity by decreasing vbe through negative feedback. All the capacitances, either internal or external CBE and CCB, help improving linearity through negative feedback at the expense of gain. The nonlinear contributions from various I–V and C–V nonlinearities cancel out each other to certain extent depending on circuit design, which further improves circuit overall linearity. In particular, for bipolar transistors, the exponential I–V and exponential C–V nonlinearities can be engineered to cancel out through tuning of harmonic impedance termination, which can be understood using Volterra series, as described below.

4.7.4 Volterra Series Linearity Analysis We now examine how the physical nonlinearities affect IP3 using Volterra series, a mathematical method of analyzing small-signal distortion. Compared to other distortion analysis methods, Volterra series allows us to easily identify the contribution of various individual nonlinearities, as well as identify the interaction between individual nonlinearities. Volterra series is an extension of the theory of linear systems to weakly nonlinear systems, its essence is summarized as follows: .

.

Volterra series approximate the output of a nonlinear system in a manner similar to the more familiar Taylor series approximation of analytical functions. Similarly, the analysis is applicable only to weak nonlinearities, or small inputs. The response of a nonlinear system to an input x(t) is equal to the sum of the responses of a series of transfer functions of different orders (H1, H2, . . . , Hn) Y ¼ H1 (x) þ H2 (x) þ H3 (x) þ :

.

(4:7:10)

In the time domain, Hn is described as an impulse response hi(t 1, t 2, . . . , t n). As in linear circuit analysis, frequency-domain representation is more convenient, and thus Hn(s1, . . . , sn), the nthorder transfer function or Volterra kernel in frequency domain, is obtained through a multidimensional Laplace transform of the time-domain impulse response Laplace transform

zﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄ{ time domain ð þ1 zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ ð þ1 Hn (s1 , , sn ) ¼ hn (t 1 , t 2 , . . . , t n ) e(s1 t1 þs2 t2 þþsn tn ) dt 1 dt n : frequency domain

1 . .

.

(4:7:11)

1

Here, Hn takes n frequencies as the input, from s1 ¼ jv1 to sn ¼ jvn. The first-order transfer function or Volterra kernel H1(s) is essentially the transfer function of the small-signal linear circuit at dc bias. Higher order transfer functions represent higher order phenomena. Solving the output of a nonlinear circuit is equivalent to solving the Volterra series H1(s), H2(s1,s2), and H3(s1,s2,s3), . . .

The mathematical derivation of Volterra kernels for nonlinear circuits has been well treated in Refs. [1, 2]. We will focus on its application to calculation of IIP3 in SiGe HBTs. Consider a single transistor amplifier shown in Figure 4.7.4. The first step is to linearize the largesignal equivalent circuit in Figure 4.7.3 at the bias point. The resulting linear circuit is then solved using compacted modified nodal analysis (CMNA) [8]: ~1 (s) ¼ ~ I1 , Y (s) H

© 2006 by Taylor & Francis Group, LLC

(4:7:12)

4.7-481

Linearity

LL

+ VBE

VCE

RL

Load inductance

CS

−

AC freq 2 AC freq 1

RS

IC

Load resistance

SiGe HBT

FIGURE 4.7.4 Circuit schematic of the single transistor amplifier used.

~ 1(s) is the vector of first-order where Y(s) is the CMNA [8] admittance matrix at frequency s(jv), H ~ Volterra kernel transforms of the node voltages, and I 1 is the vector of the node excitations. The admittance matrix Y and the excitation vector ~ I 1 are obtained by applying the Kirchoff ’s current law at every circuit node. The unknowns are the node voltages. The circuit output and the voltages that ~ 1(s). control nonlinearities can be expressed as a linear combination of the elements of H ~ With H 1(s) solved, we now excite the same circuit using the second-order nonlinear current sources ~ I 2, which are functions of the first-order voltages that control individual nonlinearities, and the secondorder derivatives of all the I–V and C–V nonlinearities. Every nonlinearity in the original circuit corresponds to a nonlinear current source in parallel with the corresponding linearized circuit element. ~ 2(s1,s2): The node voltages under such an excitation are the second-order Volterra kernels H ~2 (s1 ; s2 ) ¼ ~ I2 Y (s1 þ s2 ) H

(4:7:13)

where Y(s1 þ s2) is the same CMNA admittance matrix used in Equation (4.7.12), but evaluated at the frequency s1 þ s2. ~ 3 can be solved as response to excitations In a similar manner, the third-order Volterra kernels H specified in terms of the previously determined first- and second-order kernels: ~2 (s1 , s2 , s3 ) ¼ ~ I3 : Y (s1 þ s2 þ s3 ) H

(4:7:14)

Pout versus Pin, the third-order input intercept (IIP3) at which the first- and third-order signals have ~ 1. IIP3, the input power at which ~ 3 and H equal power, and the (power) gain can then be obtained from H the fundamental output power equals the intermodulation output power, is obtained as [6]: IIP3 ¼

1 jH1 ( jv1 )j , 6RS jH3 ( jv1 , jv1 ,jv2 )j

(4:7:15)

where RS is the source resistance. IIP3 is often expressed in dB m by IIP3dBm ¼ 10 log10(103IIP3). An inspection of the Volterra series procedure immediately shows that the Volterra kernels are strongly related to the properties of the circuit admittance matrix at various frequencies. For intermodulation (2v1 v2), the circuit admittance matrix at the second harmonic frequency and at very low frequency (v1 v2) are of particular importance. Harmonic tuning and low-frequency ‘‘traps’’ circuit techniques of linearity enhancement [9–11] are based on this concept.

© 2006 by Taylor & Francis Group, LLC

4.7-482

The Silicon Heterostructure Handbook

Identifying Dominant Nonlinearity An unique feature of the Volterra series approach is the ability to identify the dominant physical nonlinearity [2, 6]. This is realized by turning on and off each individual nonlinearity-related nonlinear ~ 3 [6]. An individual IIP3 is thus ~ 2 and H current sources in formulating the excitations for solving H obtained for each nonlinearity. The individual nonlinearity that gives the lowest IIP3 (the worst linearity) is identified as the dominant nonlinearity. We can then calculate the overall IIP3 by including all of the nonlinearities in the calculation of ~ 3. A comparison of the individual IIP3 and the overall IIP3 reveals the interaction ~ 2 and H both H between individual nonlinearities. As shown below, the overall IIP3 obtained by including all of the nonlinearities can be larger (better) than an individual IIP3, implying cancellation between individual nonlinearities [6, 12]. We now consider the Volterra series linearity analysis of a SiGe HBT with 50 GHz peak fT. The frequency is 2 GHz, and the tone spacing is 1 MHz. The SiGe HBT has four AE ¼ 0.5 20 mm2 emitter fingers. IC ¼ 3 mA, VCE ¼ 3 V, RS ¼ 50 V, CS ¼ 300 pF, RL ¼ 186 V, and LL ¼ 9 nH.

Collector Current Dependence Figure 4.7.5 shows the IIP3 and gain as a function of IC up to 60 mA at which fT and fmax peak. The collector biasing voltage is VCE ¼ 3 V. At low IC (<5 mA), the exponential ICE–VBE nonlinearity () yields the lowest individual IIP3, and hence is the dominant factor. For 5 mA < IC <25 mA, the ICB nonlinearity due to avalanche multiplication () dominates. For IC > 25 mA, the CCB nonlinearity due to the CB capacitance ( ) dominates. Interestingly, the overall IIP3 obtained by including all of the nonlinearities is close to the lowest individual IIP3 for all the IC in this case. The closeness indicates a weak interaction between individual nonlinearities. The overall IIP3 increases with IC for IC < 5 mA when the exponential ICE nonlinearity dominates. For IC > 5 mA where the avalanche current (ICB) nonlinearity dominates, the IC dependence of the overall IIP3 is twofold: 4

1. The initial current for avalanche ICE increases with IC. 2. The avalanche multiplication factor (M1) decreases with IC. The increase of the avalanche IIP3 and hence the overall IIP3 for IC > 17 mA is a result of the decrease of M 1 with increasing JC. For IC > 25 mA, ‘‘the overall IIP3 becomes limited by the CCB nonlinearity, and is approximately independent of IC.’’ The optimum biasing current is therefore IC ¼ 25 mA in this case (VCE ¼ 3 V). The use of a higher IC only increases power consumption, and does not improve

60 I BE I CE CBE CCB CCS I CB

IIP3 (dBm), Gain (dB)

50 40 30 20

all nonlinearities gain

10 0 −10

0

9

17 26 34 43 Collector current (mA)

FIGURE 4.7.5 IIP3 and gain as a function of IC.

© 2006 by Taylor & Francis Group, LLC

51

60

4.7-483

Linearity

linearity. The decrease of M 1 with increasing JC is therefore beneficial to the linearity of these SiGe HBTs. The low-noise biasing JC for this HBT is 0.1 to 0.2 mA/mm2, which corresponds to a IC of 4 to 8 mA in Figure 4.7.5. In this IC range, IIP3 is limited by avalanche multiplication for the circuit configuration in Figure 4.7.4. To further improve IIP3, a lower collector doping is desired, provided that the noise performance is not inadvertently degraded. The noise figure, for instance, is relatively independent of the collector doping as long as Kirk effect does not occur at the JC of interest [13]. Thus, there must exist an optimum collector-doping profile for producing low-noise transistors with the best linearity.

Collector Voltage Dependence An alternative way of reducing avalanche is to decrease the collector biasing voltage, which, however, also reduces the output voltage swing and hence the dynamic range. Another disadvantage from a linearity standpoint is that the CB capacitance nonlinearity is increased. Therefore, one must carefully optimize the collector biasing voltage for optimum IIP3. Figure 4.7.6 shows the overall IIP3 as a function of VCE up to 3.3 V, the BVCEO of the transistor. A peak of IIP3 generally exists as VCE increases. For IC ¼ 10 mA where noise figure is minimum, the optimum biasing VCE is 2.4 V, yielding an IIP3 of 9 dB m. The IIP3 obtained (9 dB m) is 11 dB higher than the IIP3 at VCE ¼ 3 V (2 dB m), illustrating the importance of biasing in determining linearity of these SiGe HBTs. The biasing current and voltage has significant impact on transistor linearity. Figure 4.7.7 shows the IIP3 as a function of IC for different VCE. At sufficiently high IC, IIP3 approaches a value that depends on VCE. The threshold IC where IIP3 reaches its maximum is higher for a higher VCE. For a given VCE, IC must be above this threshold to achieve good IIP3. On the other hand, the use of an IC well above the threshold does not further increase IIP3, and only increases power consumption. The optimum IC is thus at the threshold value, which is 10 mA for VCE ¼ 2 V. Figure 4.7.8 shows the contours of IIP3 as a function of IC and VCE, which can be used for selection of biasing current and voltage.

Load Dependence and Nonlinearity Cancellation Figure 4.7.9 shows the individual and overall IIP3 as a function of load resistance, together with gain. As expected, the gain varies with load, and peaks when the load is closest to conjugate matching. IIP3, however, is sensitive to load variation. The IIP3 with all nonlinearities (denoted by ) is noticeably !

15

IIP3 (dBm)

10

0

15

IC = 5 mA IC = 10 mA IC = 15 mA IC = 30 mA

−5

−10 1

1.5

2 VCE (V)

FIGURE 4.7.6 IIP3 as a function of VCE for different IC.

© 2006 by Taylor & Francis Group, LLC

2.5

3

4.7-484

The Silicon Heterostructure Handbook

15

10

IIP3 (dBm)

5

0

VCE = 1.5 V VCE = 2.0 V VCE = 2.5 V

−5

VCE = 3.0 V

−10 0

10

20

30 IC (mA)

40

50

60

FIGURE 4.7.7 IIP3 as a function of IC for different VCE.

IIP3 60 55 50 3 45

IC (mA)

40 35 30 9

10

25

0

20

−4

6

15 10 0

5

6

−4 1.2

1.4

−8 1.6

1.8

2

2.2 VCE (V)

FIGURE 4.7.8 Contours of IIP3 in dB m on the IC–VCE plane.

© 2006 by Taylor & Francis Group, LLC

−4

3

2.4

2.6

2.8

3

3.2

4.7-485

Linearity

50

IIP3 (dBm), Gain (dB)

40 I BE I CE CBE CCB CCS I CB

30 20 10 0

all nonlinearities gain

−10 −20

0

100

200 300 Load resistance (Ω)

400

500

FIGURE 4.7.9 IIP3 and gain as a function of load resistance at IC ¼ 13 mA and VCE ¼ 3 V.

higher than the IIP3 with the avalanche current (ICB) nonlinearity alone (denoted by ). The interaction between individual nonlinearities has improved the overall linearity through cancellation. In this case, the two most dominating nonlinearities are the avalanche current ICB nonlinearity and the CCB nonlinearity. The cancellation between the ICB and CCB nonlinearities leads to an overall IIP3 value that is higher (better) than the IIP3 obtained using the ICB nonlinearity alone. The degree of cancellation depends on the biasing, source and load conditions, as expected from the Volterra series theory. Physically, the load dependence of linearity in these HBTs results from the CB feedback [6]. The first kind of such feedback is the CB capacitance CCB, and the second kind is the avalanche multiplication current ICB that flows from the collector to base. Both feedbacks are nonlinear, though the load dependence would still exist for linear CB feedback [7] (for instance, externally connected linear CB capacitance).

Linearity Limiting Factors Figure 4.7.10 shows the dominant nonlinearity factor on the IC–VCE plane. The upper limit of IC is where fT reaches its peak value. Avalanche multiplication and CCB nonlinearities are the dominant factors for most of the bias currents and voltages. Both avalanche multiplication and CCB nonlinearities can be reduced by reducing the collector doping. This, however, conflicts with the need for high collector doping required to suppress Kirk effect and heterojunction barrier effects in SiGe HBTs. Therefore, multiple collector-doping profiles are needed to provide both high fT devices and high IIP3 devices for different stages of the same circuit. Typical SiGe processes offer HBTs with different collector-doping profiles through selective collector implantations. Circuit designs could use the higher breakdown voltage devices when fT is sufficient, which may provide better linearity.

4.7.5 Summary Despite the strong I–V and C –V nonlinearities, SiGe HBTs can be used to design highly linear RF amplifiers. The avalanche multiplication nonlinearity can be minimized by proper choice of biasing current density and voltage. Linearity in general can be improved by increasing the biasing current, and parasitic or intentionally used feedbacks also help improving linearity. All the capacitances, either internal or external CBE and CCB, help improving linearity through negative feedback at the expense of gain. The nonlinear contributions from various I–V and C–V nonlinearities cancel out each other to certain extent, depending on the impedance of the linear circuit admittance matrix at both the

© 2006 by Taylor & Francis Group, LLC

4.7-486

The Silicon Heterostructure Handbook

Dominant nonlinearity 60

50

CCB CB Capacitance

IC (mA)

40

30

ICB Avalanche Multiplication

20

10

ICE−VBE

0 1

1.5

2

2.5

3

3.5

VCE (V)

FIGURE 4.7.10

Dominant nonlinearity factor on the IC–VCE plane.

fundamental and harmonic frequencies, which can be utilized for further linearity improvement, e.g., through harmonic tuning. Both the CCB and ICB (avalanche) nonlinearities depend on the collectordoping profile, which can be optimized for linearity improvement. The higher breakdown voltage lower speed HBTs in commercial SiGe processes can be used in circuit design for linearity leverage.

Acknowledgments The author would like to thank Q. Liang for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ-1133.

References 1. DD Weiner and JE Spina. Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits. Van Nostrand Reinhold, New York, 1980. 2. P Wambacq and W Sansen. Distortion Analysis of Analog Integrated Circuits. Kluwer Academic, Dordrecht, 1998. 3. S Narayanan. Transistor distortion analysis using Volterra series representation. Bell Syst. Tech. J. 46:991–1024, 1967. 4. H Jos. Technology developments driving evolution of cellular phone power amplifiers to integrated RF front-end modules. IEEE J. Solid-State Circ. 36:1382–1389, 2001. 5. GF Niu, JD Cressler, S Zhang, U Gogineni, and DC Ahlgren. Measurement of collector–base junction avalanche multiplication effect in advanced UHV/CVD SiGe HBTs. IEEE Trans. Electron Dev. 46:1007–1015, 1999.

© 2006 by Taylor & Francis Group, LLC

Linearity

4.7-487

6. GF Niu, QQ Liang, JD Cressler, C Webster, and DL Harame. RF linearity characteristics of SiGe HBTs. IEEE Trans. Micro. Theory Tech. 49:1558–1565, 2001. 7. GF Niu, JD Cressler, WE Ansley, CS Webster, R Anna, and N King. Intermodulation characteristics of UHV/CVD SiGe HBTs. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, 1999, pp. 50–53. 8. G Gielen and W Sansen. Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer Academic, Dordrecht, 1991. 9. V Aparin and LE Larson. Analysis and reduction of cross-modulation distortion in CDMA receivers. IEEE Trans. Micro. Theory Tech. 35:1591–1602, 2003. 10. KL Fong. High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network. IEEE J. Solid-State Circ. 35:1249–1252, 2000. 11. QQ Liang, JM Andrews, JD Cressler, and GF Niu. General Analysis of the impact of harmonic impedance on linearity, with applications to SiGe HBTs. Proc. of IEEE Bipolar/BiCMOS Circ. Tech. Meeting, pp. 48–51, 2004. 12. S Maas, B Nelson, and D Tait. Intermodulation in heterojunction bipolar transistors. IEEE Trans. Micro. Theory Tech. 40:442–448, 1992. 13. GF Niu, WE Ansley, S Zhang, JD Cressler, C Webster, and R Groves. Noise parameter optimization of UHV/CVD SiGe HBTs for RF and microwave applications. IEEE Trans. Electron Dev. 46:1347– 1354, 1999.

© 2006 by Taylor & Francis Group, LLC

4.8 pnp SiGe HBTs

John D. Cressler Georgia Institute of Technology

4.8.1 4.8.2 4.8.3 4.8.4 4.8.5

Introduction............................................................... 4.8-489 Simulation of pnp SiGe HBTs.................................. 4.8-490 Profile Optimization Issues ...................................... 4.8-490 Stability Constraints in pnp SiGe HBTs.................. 4.8-494 Summary .................................................................... 4.8-495

4.8.1 Introduction At present, SiGe technology development is almost exclusively centered on npn SiGe HBTs. For highspeed analog and mixed-signal circuit applications, however, it is well known that a complementary (npn þ pnp) bipolar technology offers significant performance advantages over an npn-only technology [1]. Push–pull circuits, for instance, ideally require a high-speed vertical pnp transistor with comparable performance to the npn transistor [2]. The historical bias in favor of npn Si BJTs is due to the significantly larger minority electron mobility in the p-type base of an npn Si BJT, compared to the lower minority hole mobility in the n-type base of a pnp Si BJT. In addition, the valence band offset in SiGe strained layers is generally more conducive to npn SiGe HBT designs, because it translates into an induced conduction band offset and band grading that greatly enhance minority electron transport in the device, thereby significantly boosting transistor performance over a similarly constructed npn Si BJT. It has been shown that this band alignment is not as restrictive, however, as has been commonly assumed [3]. For a pnp SiGe HBT, on the other hand, the valence band offset directly results in a valence band barrier, even at low injection, which strongly degrades minority hole transport and thus limits the frequency response. Careful optimization to minimize these hole barriers in pnp SiGe HBTs is thus required, and has in fact yielded impressive device performance compared to Si pnp BJTs, as demonstrated in the pioneering work reported in Refs. [4–6]. Very recently, in fact, the first commercial complementary SiGe HBT BiCMOS technologies have been reported, in one case targeting high-speed and high-voltage analog circuit applications [7], and the other demonstrating impressive levels of pnp SiGe HBT performance, in this with a peak fT / fmax of 80/ 120 GHz at a BVCEO of 2.6 V [8]. Details of these impressive complementary SiGe technology demonstrations are given in Chapters 3.9 and 3.11, respectively. An analysis of the inherent profile design differences between npn and pnp SiGe HBTs is relevant in this context of complementary SiGe HBT technologies, as well as meaningful design guidelines for constructing pnp SiGe HBTs. Relevant questions include, for instance: . .

. .

How does SiGe npn and pnp profile design fundamentally differ? Can a single Ge profile design point be used for both npn and pnp transistors, for a given stability constraint? Is a graded-base Ge profile design preferable to a box-shaped Ge profile design for pnp HBTs? How much Ge retrograding in the collector–base junction is required to obtain acceptable SiGe pnp HBT performance?

4.8-489 © 2006 by Taylor & Francis Group, LLC

4.8-490

The Silicon Heterostructure Handbook

These issues are addressed using calibrated device simulations to shed light on the fundamental SiGe profile design differences between npn SiGe HBT and pnp SiGe HBTs that might be encountered, for instance, in developing such a viable complementary SiGe HBT technology [9].

4.8.2 Simulation of pnp SiGe HBTs One-dimensional MEDICI simulations [10] which were used to analyze the differences in intrinsic profile design between pnp and npn transistors are the central focus. To aid in interpretation of the results, simplistic hypothetical npn and pnp SiGe profiles with constant emitter, base, and collector doping, and a Ge content not subject to thermodynamic stability constraints, were initially adopted (Figure 4.8.1). These profile assumptions are clearly nonphysical for real SiGe technologies, but are very useful for comparing npn and pnp devices so that their differences can be more easily discriminated and not masked by doping-gradient-induced phenomena (stability issues will be addressed below). This artificial assumption on constant doping clearly yields ac performance numbers (e.g., fT) that are lower than what would be expected for a real complementary SiGe HBT technology, but relative comparisons between npn and pnp devices are nonetheless valid, and the comparison methodology widely applicable. MEDICI models of the devices were constructed using actual device layouts and measured SIMS data, and careful calibration of MEDICI simulations for both npn and pnp Si BJTs to measured complementary Si BJT hardware was performed. It was found that the default minority hole mobility modeling capability of MEDICI was deficient and tuning was required to obtain reasonable agreement between data and simulation, particularly under high-level injection. The SiGe model parameters determined from earlier calibrations of high-speed npn SiGe HBTs were used [3], and assumed to be the same for both npn and pnp transistors.

4.8.3 Profile Optimization Issues A comparison of the equilibrium conduction and valence band edges for both npn and pnp devices without any Ge retrograding into the collector (i.e., an abrupt transition from the peak Ge content to zero Ge content in the CB junction) is shown in Figure 4.8.2 and Figure 4.8.3 for: (1) a Si BJT; (2) a triangular (linearly graded) Ge profile with a peak Ge content of 10%; and (3) a triangular Ge profile with a peak Ge content of 25%. Observe that while there is no visible conduction band barrier present in the npn HBT, there is an obvious valence band barrier in the pnp HBT, even for low Ge content. This is

1020

30 25

E

Ge

1019

20

1018

15

1017

10

1016 1015 0.0

B

Ge Concentration (%)

Doping concentration (cm−3)

1021

5

C

0 0.2

0.4

0.6

0.8

1.0

Depth (µm)

FIGURE 4.8.1 Hypothetical doping and Ge profiles for both pnp and npn SiGe HBTs. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-491

pnp SiGe HBTs

1.0 Conduction band edge (eV)

Si 0.8

npn SiGe HBT

10% peak 25% peak

0.6

0.4

VBE = 0.0 V V BC = 0.0 V T = 300 K Ge profile

0.2

0.0 0.15

0.20

0.25

0.30

0.35

0.40

Depth (µm)

FIGURE 4.8.2 Valence band edge of an npn SiGe HBT for varying peak Ge content. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

Valence band edge (eV)

0.0 pnp SiGe HBT

−0.2 −0.4 −0.6

V BE = 0.0 V V BC = 0.0 V T = 300 K

Ge profile

10% peak

25% peak −0.8

qF B Si

−1.0 0.15

0.20

0.25

0.30

0.35

0.40

Depth (µm)

FIGURE 4.8.3 Simulated conduction band edge of a pnp SiGe HBT for varying peak Ge content. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

consistent with the fact that there is a valence band offset in strained SiGe on Si (refer to Chapter 4.2), and clearly indicates that pnp SiGe HBT design is inherently more difficult than npn SiGe HBT design. In addition, due to the inherent minority carrier mobility differences between electrons and holes, it is also clear that npn devices will consistently out-perform pnp devices, everything else being equal. Unlike for a well-designed npn SiGe HBT (i.e., Ge outside the neutral base edges), where conduction band barrier effects are uncovered only at high JC under Kirk effect [3] (refer to Chapter 4.3), the valence band barrier in pnp SiGe HBTs is in play even at low injection, and acts to block minority holes transiting the base. This pileup of accumulated holes produces a retarding electric field in the base, which compensates the Ge-grading-induced drift field, dramatically decreasing both JC, b, and fT. This effect worsens as the current density increases, since more hole charge is stored in the base. In this case, the fT of the pnp SiGe HBT is in fact significantly lower than that of the pnp Si BJT. As expected, however, retrograding of the Ge edge into the collector can ‘‘smooth’’ this valence band offset in the pnp

© 2006 by Taylor & Francis Group, LLC

4.8-492

The Silicon Heterostructure Handbook

SiGe HBT, and thus improve this situation dramatically, although at the expense of film stability [4, 5]. For an increase of the Ge retrograde from 0 to 40 nm, the pnp SiGe HBT performance is dramatically improved, yielding roughly a 2 increase in peak fT over the pnp Si BJT performance at equal doping. Figure 4.8.4 and Figure 4.8.5 show the variation in peak fT and b as a function of peak Ge content for both npn and pnp SiGe HBTs for both a 0-nm Ge retrograde and 100-nm Ge retrograde. At 100-nm retrograde, the performance of the pnp SiGe HBT monotonically improves as the Ge content rises, while the maximum useful Ge content is limited to about 10% without retrograding. Figure 4.8.6 indicates that 40–50 nm of Ge retrograding in the pnp SiGe HBT is sufficient to ‘‘smooth’’ the valence band barrier, and this is reflected in Figure 4.8.7, which explicitly shows the dependence of pnp peak fT on Ge retrograde distance, for both triangular and box Ge retrograde profile shapes. Observe that the box Ge retrograde is not effective in improving the pnp SiGe HBT performance, since it does not smooth

50 Peak cutoff frequency (GHz)

Base Collector Ge

40

100 nm retrograde

Retrograde 0 100 nm

30 npn 20

No retrograde

pnp

10 T = 300K 0 0

5

10 15 Peak Ge content (%)

20

25

FIGURE 4.8.4 Simulated peak cutoff frequency as a function of peak Ge content for different Ge retrogrades for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949– 1954, 2000. With permission.)

350 Base Collector

300

JC = 0.1 mA/µm2 Retrograde T = 300K

Ge Current gain

250 0

100 nm

200 100 nm retrograde 150 npn

100

No retrograde pnp

50 0 0

5

10 15 Peak Ge content (%)

20

25

FIGURE 4.8.5 Simulated current gain as a function of peak Ge content for different Ge retrogrades for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-493

pnp SiGe HBTs

−0.4 p+

Ge retrograde p

n

−0.6

25 20

100 nm 50 nm 40 nm

−0.8

−1.0 0.15

0.20

10

30 nm

qF B

10 nm 0 nm 0.25

0.30

0.35

0.40

15

Ge Concentration (%)

Valence band edge (eV)

30 V BE = 0.0 V V BC = 0.0 V T = 300 K

5

0.45

0 0.50

Depth (µm)

FIGURE 4.8.6 Valence band edge of a pnp SiGe HBT as a function of Ge retrograde distance. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

50 Peak cutoff frequency (GHz)

npn 40 Base Collector 30

Box-like extension

Ge

Triangle retrograde

20

0

10

100 nm Peak Ge = 25% V = 1.0 V T = 300 K

pnp

0 0

20

40

60

80

100

Retrograde distance (nm)

FIGURE 4.8.7 Simulated peak cutoff frequency as a function of both Ge retrograde distance and Ge profile shape for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949– 1954, 2000. With permission.)

the Ge barrier, but rather only pushes it deeper into the collector, where it is still felt at the high JC needed to reach peak fT. This box Ge retrograde is also clearly undesirable from a stability standpoint. The effects of Ge retrograding on the npn SiGe HBT performance, on the other hand, are minor, while the film stability is significantly worse due to the additional Ge content. This suggests that using one Ge profile design for both npn and pnp SiGe HBTs is not optimum for high-peak Ge content values. Note that while the peak fT is unchanged with Ge retrograding in the npn SiGe HBT, the fT response above peak fT does not roll off as rapidly due to the high-injection-induced barrier, consistent with the results in Ref. [3] (refer to Chapter 4.3). An examination of the frequency response of the npn and pnp SiGe HBTs as a function of front-side Ge profile shape (in this case, triangle versus box Ge profile, with a fixed retrograde of 100 nm for both) and peak Ge content shows that for the npn SiGe HBT, the base transit time reduction from the Gegrading-induced drift field of the triangle Ge profile shape gives a significant advantage above 10% peak

© 2006 by Taylor & Francis Group, LLC

4.8-494

The Silicon Heterostructure Handbook

Ge, indicating that the npn SiGe HBT is base transit time limited. Interestingly, for the pnp SiGe HBT, however, the differences between the box and triangle Ge profiles are much less pronounced, everything else being equal. The box Ge profile gives a slight advantage at low Ge content due to the low b and hence importance of the emitter transit time (tE / 1/b), but once the b is sufficiently high, the triangle Ge profile dominates at higher peak Ge content, where the base transit time limits the overall response. In both npn and pnp devices, the triangle Ge profile offers better performance and better stability (lessintegrated Ge content), and thus can be considered an optimum shape for both devices. This is even more apparent if we examine the Early voltage of the devices, a key figure-of-merit for complementary analog circuits. In this case, the triangle Ge profile has a clear advantage due to its graded bandgap, as expected, and both npn and pnp transistors show a significant improvement in VA with increasing Ge content.

4.8.4 Stability Constraints in pnp SiGe HBTs The total amount of Ge that can be put into a given SiGe HBT is limited by the thermodynamic stability criterion. Above the critical thickness, the strain in the SiGe film relaxes, generating defects. In general, varying peak Ge content or retrograde distance (i.e., film thickness) moves the profile along different contours in stability space (Figure 4.8.8). Under the SiGe stability constraint, the peak Ge content must be traded off for the Ge retrograde distance in the collector–base junction. Figure 4.8.9 shows that a 11% peak Ge profile with a 25-nm retrograde gives the highest fT for the pnp SiGe HBT at this design point. A similar exercise for the npn SiGe HBT shows that the ac performance is not sensitive to the SiGe profile shapes used, and, hence, without a significant loss of performance, the same Ge profile may in principle be used for both pnp and npn SiGe HBTs. This may be advantageous from a fabrication viewpoint. These results should be valid for current SiGe technology nodes with about 100-nm base width. If the base width is further reduced with technology scaling, the peak Ge content can be obviously increased, while maintaining film stability. The same optimization methodology employed here can be used in that case to determine the best SiGe profile for both devices.

400

Effective thickness (nm)

(1)

300

peak Ge from 8% to 13% (step = 1%)

(2)

(3) peak Ge = 11%

(4)

100 nm E B

25 nm C

200

Retrograde from 0 to 40 nm (step = 10 nm) 100 nm E B

40 nm C

100 0

0.0005

0.001 0.0015 Effective strain

0.002

FIGURE 4.8.8 SiGe stability diagram illustrating the various pnp profile design tradeoffs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-495

pnp SiGe HBTs

20 Base Collector Retrograde

Ge Cuttoff frequency (GHz)

(1) peak Ge = 10% Retro = 39 nm

15

(2) peak Ge = 11% Retro = 25 nm (3) peak Ge = 12.5% Retro = 9 nm (4) peak Ge = 13% Retro = 5 nm

0

pnp

10 SiGe

5

0

Si

10−5

10−4 JC

(A/µm2)

FIGURE 4.8.9 Simulated cutoff frequency as a function of collector current density for pnp SiGe HBTs with different Ge profiles. Refer to Figure 4.4.8 for the exact profile shapes. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

4.8.5 Summary In spite of the historical bias in favor of npn SiGe HBTs, complementary (npn þ pnp) SiGe HBT technology has recently emerged as a viable mixed-signal technology. In this chapter, we have examined the fundamental profile design constraints associated with pnp SiGe HBTs, and importantly, how those constraints differ from those faced in conventional npn SiGe HBT design.

Acknowledgments I am grateful to G. Zhang, G. Niu, and D. Harame for their contributions. This work was supported by the GEDC at Georgia Tech and IBM.

References 1. JD Cressler, J Warnock, DL Harame, JN Burghartz, KA Jenkins, and CT Chuang. A high-speed complementary silicon bipolar technology with 12 fJ power-delay product. IEEE Electron Device Letters 14:523–526, 1993. 2. CT Chuang, JD Cressler, and JD Warnock. ac-coupled complementary push-pull ECL circuits with 34 fJ power-delay product. Electronics Letters 29:1938–1939, 1993. 3. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 4. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base pnp transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest of the IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 5. DL Harame, BS Meyerson, EF Crabbe´, JM Cotte, JMC Stork, AC Megdanis, GL Patton, SR Stiffler, JB Johnson, JD Warnock, JH Comfort, and JY-C Sun. 55 GHz polysilicon-emitter graded SiGe-base pnp transistors. Technical Digest of the IEEE Symposium on VLSI Technology, Oiso, Japan, 1991, pp. 71–72.

© 2006 by Taylor & Francis Group, LLC

4.8-496

The Silicon Heterostructure Handbook

6. DL Harame, JH Comfort, EF Crabbe´, JD Cressler, JD Warnock, BS Meyerson, KY-J Hsu, J Cotte, CL Stanis, JMC Stork, JY-C Sun, DA Danner, and PD Agnello. A SiGe-base pnp ECL circuit technology. Technical Digest of the IEEE Symposium on VLSI Technology, Honolulu, 1993, pp. 61–62. 7. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schultz, L Swanson, D Tatman, M Waitschull, J Weijtmans, and C Willis. A 5 V complementary-SiGe BiCMOS technology for high-speed precision circuits. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 211–214. 8. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Hoppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Rucker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high-speed npn and pnp SiGe:C HBTs Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 9. G Zhang, JD Cressler, G Niu, and A Pinto. A comparison of npn and pnp profile design tradeoffs for complementary SiGe HBT technology. Solid-State Electronics 44:1949–1954, 2000. 10. MEDICI. 2-D Semiconductor Device Simulator, Avant!, Fremont, CA, 1997.

© 2006 by Taylor & Francis Group, LLC

4.9 Temperature Effects 4.9.1 4.9.2

John D. Cressler Georgia Institute of Technology

4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8

Introduction............................................................... 4.9-497 The Impact of Temperature on Bipolar Transistors .................................................................. 4.9-497 Cryogenic Operation of SiGe HBTs ........................ 4.9-498 Design Constraints .................................................... 4.9-500 Optimization of SiGe HBTs for 77 K....................... 4.9-501 Helium Temperature Operation .............................. 4.9-506 High-Temperature Operation .................................. 4.9-506 Summary .................................................................... 4.9-509

4.9.1 Introduction Bandgap engineering generally has a positive influence on the low-temperature characteristics of bipolar transistors [1]. SiGe HBTs operate very well, in fact, in the cryogenic environment (e.g., liquid nitrogen temperature ¼ 77.3 K ¼ 3208F ¼ 1968C), an operational regime traditionally forbidden to Si BJTs. At present, cryogenic electronics represents a small but important niche market, with applications such as high-sensitivity cooled sensors and detectors, semiconductor–superconductor hybrid systems, space electronics, and eventually cryogenically cooled computers systems. While the large power dissipation associated with conventional bipolar digital circuit families such as emittercoupled-logic (ECL) would likely preclude their widespread use in cooling-constrained cryogenic systems, the combination of cooled, low-power, scaled Si CMOS with SiGe HBTs offering excellent frequency response, low-noise performance, radiation hardness, and excellent analog properties represents a unique opportunity for the use of SiGe HBT BiCMOS technology in cryogenic systems. Furthermore, independent of the potential cryogenic applications that may exist for SiGe HBT BiCMOS technology, all electronic systems must successfully operate over an extended temperature range (e.g., 55 to 1258C to satisfy military specifications and 0 to 858C for most commercial applications), and thus, understanding how Ge-induced bandgap engineering affects SiGe HBT device and circuit operation is important. In this chapter, we address temperature effects in SiGe HBTs, by first reviewing the impact of temperature on bipolar transistor device and circuit operation. We then show how temperature couples to SiGe HBT dc and ac performance, how one optimizes SiGe HBTs specifically for cryogenic operation, and finally consider the operation of SiGe HBTs at elevated temperatures (to 3008C).

4.9.2 The Impact of Temperature on Bipolar Transistors The detrimental effects of cooling on homojunction bipolar transistor operation have been appreciated for many years [2–6]. While the precise dependence of Si BJT properties on cooling can be a strong function of technology generation and profile design, Si BJT device and circuit properties cooled to cryogenic temperatures typically exhibit [7–12]: 4.9-497 © 2006 by Taylor & Francis Group, LLC

4.9-498

.

.

.

. . .

. .

The Silicon Heterostructure Handbook

A modest increase (degradation) in the junction turn-on voltage with decreasing temperature (monotonic). A strong increase (improvement) in the low-injection transconductance with cooling (monotonic). A strong increase (degradation) in the base resistance with cooling (typically, quasi-exponential below about 200 K). A mild decrease (improvement) in parasitic transistor depletion capacitances (monotonic). A strong decrease (degradation) in b with cooling (quasi-exponential). A modest decrease (degradation) in frequency response with cooling, with fT typically degrading more rapidly than fmax with decreasing temperature (monotonic below about 200 K). An increase (degradation) in ECL circuit delay with cooling (monotonic below about 200 K). The noise margin of current-switch-based digital circuits (e.g., ECL) increases (improves) with cooling (monotonic), allowing reduced logic swing operation.

The impact of cooling of Si BJTs is typically largely one of serious device and circuit performance degradations, effectively precluding their use in cryogenic applications. The addition of SiGe to this problem can be used to change this situation dramatically.

4.9.3 Cryogenic Operation of SiGe HBTs Intuitively, we expect that band-edge effects induced by bandgap engineering will generally couple strongly to bipolar transistor properties. This strong coupling is physically the consequence of the fact that the bipolar transistor is a minority carrier device, and hence the terminal currents are proportional to ni02 via the Shockley boundary conditions, with ni02 in turn proportional to the exponential of the bandgap. Hence, changes to the bandgap will couple exponentially to the currents. Furthermore, from very general statistical mechanical considerations, these bandgap changes will inevitably be divided by the thermal energy (kT), such that a reduction in temperature will greatly magnify any bandgap changes. Not surprisingly, then, even a cursory examination of the SiGe HBT device equations suggests that both the dc and ac properties of SiGe HBTs should be favorably affected by cooling [13, 14]. In fact, the thermal energy (kT), in every instance, is arranged in the SiGe HBT equations such that it favorably affects the low-temperature properties of the particular performance metric in question, be it b(T), fT(T ), or VA(T ). The beneficial role of temperature in SiGe HBTs can be used to easily offset the inherent bandgapnarrowing-induced degradation in current gain of a Si BJT to achieve viable dc operation down to 77 K, even for a SiGe HBT that has not been optimized for the cryogenic environment. Figure 4.9.1 shows the evolution of peak current gain as a function of reciprocal temperature from early Si BJT technologies circa 1978 to SiGe technologies circa 1992. Clearly, the addition of Ge-induced bandgap engineering enables functional current gain down at least to 77 K with minimal effort. From a dynamic point of view, the Ge-grading-induced base drift field provides a means to offset the inherent tb degradation associated with cooled Si BJTs, yielding an fT that does not degrade with cooling. Since the reduced thermal cycle nature of epitaxial growth techniques are generally more conducive to maintaining thinner, more heavily doped base profiles than conventional ion-implanted bases used in modern Si BJTs, it is fairly straightforward to control base freeze-out in SiGe HBTs, at least down to 77 K, and hence Rb at cryogenic temperatures can be more easily controlled. If fT and Rb do not degrade significantly with cooling, then achieving respectable circuit performance down to 77 K becomes a reality unknown to Si BJT technologies. Figure 4.9.2 shows the evolution of unloaded ECL gate delay as a function of publication date. As expected, optimized 300-K technology scaling successfully improved circuit speed over time. More surprising, perhaps, is that the rate of improvement in low-temperature performance was significantly faster. The 1991 and 1992 cryogenic data points are for SiGe HBT technologies, and clearly demonstrate that one can no longer out of hand dismiss Si-based bipolar technologies for

© 2006 by Taylor & Francis Group, LLC

4.9-499

Temperature Effects

Temperature (K) 300

Norm. current gain (b/b 300 K)

10

200

150 125

100

77 1992 SiGe

1.0

1990

.10

1987 1984

RBI = 6–8 kΩ/(300 K)

1978

.01 2

4

6

8 10 1000/T (K−1)

12

14

FIGURE 4.9.1 Evolution of current-gain temperature dependence with Si-based bipolar technology generation. The last two generations are SiGe HBT technologies. (From JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JYC Sun. IEEE Trans. Electron Dev. 40:525–541, 1993. With permission.)

Bipolar ECL gate delay (ps)

500 84 K 300 K

200 100 50 20 10 1980

21.9 ps (84 K) 1983

1986 1989 Publication date

1992

1995

FIGURE 4.9.2 Evolution of unloaded ECL gate delay at 310 and 84 K with Si-based bipolar technology generation. The last two generations are SiGe HBT technologies. (From JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JYC Sun. IEEE Trans. Electron Dev. 40:525–541, 1993. With permission.)

the cryogenic applications. SiGe can thus be viewed as an effective means to extend Si-based bipolar technology to the cryogenic environment (with little or no effort). This scenario is particularly appealing if we consider the state-of-the-art SiGe HBT BiCMOS technologies, since Si CMOS also performs well down to 77 K, and provides a major advantage in the reduction in power dissipation, an often serious constraint given the limited efficiency of cryocoolers. While it is unlikely that one would develop SiGe technology explicitly for cryogenic applications, if (as is the case) one could simply take a room temperatureoptimized SiGe technology and operate it at low temperatures without serious modification, that prospect might prove cost-effective. With the present trend toward reduced-temperature operation of CMOSbased high-end servers as a performance and reliability enhancement vehicle (currently at 0 to 408C and going lower), the appeal of SiGe HBT BiCMOS technologies for the cryogenic environment may naturally grow over time, since HBTs can provide numerous advantages over CMOS in analog, RF, heavily loaded digital, and high-speed driver or receiver applications. We first examine the expected theoretical temperature dependence of the important SiGe HBT performance metrics. Compared to a comparably constructed Si BJT, b(T ) in a SiGe HBT should increase exponentially with decreasing temperature, since

© 2006 by Taylor & Francis Group, LLC

4.9-500

The Silicon Heterostructure Handbook

g~h ~DEg,Ge (grade)=kT eDEg,Ge (0)=kT bSiGe ’ : bSi VBE 1 eDEg,Ge (grade)=kT

(4:9:1)

As expected, a quasi-exponential increase in the SiGe-to-Si current gain ratio with decreasing temperature is typically observed experimentally. In addition, VA(T) and bVA(T) in a SiGe HBT should also increase exponentially with decreasing temperature compared to a comparably constructed Si BJT, since DEg,Ge (grade)=kT VA,SiGe DEg,Ge (grade)=kT 1 e ’e VA,Si VBE DEg,Ge (grade)=kT

(4:9:2)

bVA,SiGe ¼ g~h ~eDEg,Ge (0)=kT eDEg,Ge (grade)=kT : bVA,Si

(4:9:3)

and

This is again confirmed experimentally. The anticipated temperature dependence of the frequency response of a SiGe HBT can be gleaned from the temperature dependence of the base and emitter transit times, h i t b,SiGe 2 kT kT DEg,Ge (grade)=kT ¼ 1 1e h ~ DEg,Ge (grade) DEg;Ge (grade) t b,Si

(4:9:4)

and t e,SiGe JC,Si 1 eDEg,Ge (grade)=kT ’ ¼ : DEg,Ge (grade) DEg,Ge (0)=kT t e,Si JC,SiGe e g~h ~ kT

(4:9:5)

Both are favorably influenced by cooling, and thus, we expect that the influence of the graded SiGe base is sufficient to overcome the inherent electron diffusivity degradation on tb with cooling, and this is indeed the experimental case.

4.9.4 Design Constraints While SiGe HBTs designed for room temperature operation function acceptably down to 77 K, secondorder design constraints do, nonetheless, exist, and can impact profile optimization [15, 16]. The first such constraint centers on the base current and its impact on the current gain at low injection. While conventional Shockley–Read–Hall (SRH) recombination exponentially decreases with cooling, thereby effectively eliminating reverse leakage in the collector–base junction, the same is not true of carrier tunneling processes, whether they are band-to-band or trap-assisted. Given that the EB junction of high-speed bipolar transistors (either Si or SiGe) are typically quite heavily doped (often in the vicinity of 1 1018 cm3), the doping-induced electric field is high, and can result in substantial parasitic tunneling leakage. While this is generally easily designed around in 300-K designs, it is more problematic at low temperatures, given that the collector and base currents decrease strongly at fixed VBE as the temperature drops. In this case, as the base current decreases with cooling, any tunneling-induced leakage will remain roughly constant, hence uncovering a parasitic leakage ‘‘foot’’ on the base current (this effect can be clearly seen in Figure 4.9.3). This parasitic base leakage current can severely limit the current gain at low injection at cryogenic temperatures. Thus, as a rule of thumb, it can be safely stated that the ideality of the base current of a high-performance Si or SiGe bipolar transistor will never improve with cooling. If the base current is ideal (i.e., eqVBE/kT) down to a picoampere at 300 K, it may be ideal only to a nanoampere

© 2006 by Taylor & Francis Group, LLC

4.9-501

Collector and base currents (A)

Temperature Effects

10−2

10−4

1.0 mA/µm2 SiGe HBT "emitter–cap" profile AE = 1.4⫻4.4 µm2 VCB = 0.0 V

10−6

10−8

10−10 0.4

300 K

IC

77 K

5.84 K

IB

0.6

0.8 1.0 Base−emitter voltage (V)

1.2

FIGURE 4.9.3 Gummel characteristics at 300, 77, and 5.84 K for a 77-K optimized emitter-cap SiGe HBT. (From AJ Joseph, JD Cressler, and DM Richey. IEEE Electron Dev. Lett. 16:268–270, 1995. With permission.)

at 77 K. If it is even modestly non-ideal at 300 K, it will be quite leaky at 77 K. How serious a limitation this leakage is depends strongly on the circuit application. In digital logic, for instance, it is not an issue, given that the devices are biased well out of the leakage regime, and b does not strongly couple to circuit speed. For more sensitive analog circuits, however, it can in principle require careful design consideration. As discussed below, one can optimize a SiGe HBT to reduce this leakage effect, a feat much more easily accomplished using epitaxial growth rather than ion-implantation for the base layer formation. More worrisome than the base current at low temperatures, however, is the enhancement of highinjection, heterojunction barrier effects with cooling (refer to Chapter 4.3 for a detailed discussion of barrier effects in SiGe HBTs). Band-edge effects in bipolar transistors generally couple very strongly to the device properties, and barrier effects are no exception. In this case, given that barrier effects necessarily exist in all practical SiGe HBTs, cooling will make the situation decidedly worse. The consequences of barrier effects, as at room temperature, include a premature roll-off in both b and fT at high JC, and a limitation on maximum output current drive. What is different in the context of cryogenic operation, however, is that while a well-designed 300-K SiGe HBT may not show any clear evidence of barrier effect at 300 K, it will certainly show evidence of it at 77 K, and its impact on device performance will be correspondingly worse. That is, the design margin for 77-K operation is in essence narrower, always an undesirable situation. As discussed in Chapter 4.3, the device transconductance is a useful tool for assessing barrier effects in SiGe HBTs. A comparison of gm between comparably designed i–p–i SiGe HBTs and i–p–i Si BJTs clearly shows that while gm at low JC increases with cooling as expected, a dramatic drop in gm at a higher critical current density close to that of Kirk effect can be observed in the SiGe HBT. Fortunately, it is also true that this critical onset current density in fact increases with cooling, consistent with the fact that the saturation velocity rises at low temperatures, thus delaying Kirk effect until higher JC. As discussed below, this result can be traded off to optimize SiGe HBTs for 77 K operation. One would also expect that barrier effect would have a serious impact on transistor dynamic response, given that enhanced charge storage in the base couples strongly to fT. The approaches that can be used to design around barrier effects at cryogenic temperatures are the same as those outlined in Chapter 4.3, albeit with a narrower design margin than at 300 K.

4.9.5 Optimization of SiGe HBTs for 77 K While conventional 300-K SiGe HBT designs will inherently function reasonably well down to 77 K, it remains to be seen whether a SiGe HBT designed specifically for 77 K operation can achieve significantly

© 2006 by Taylor & Francis Group, LLC

4.9-502

The Silicon Heterostructure Handbook

better device and circuit performance at 77 K than it has at 300 K, and what the design issues and tradeoffs faced in achieving this goal would be. To address the explicit optimization of a SiGe HBT for 77 K operation, a new profile design point and fabrication scheme is required [17]. In this case an epitaxial ‘‘emitter-cap’’ layer doped with phosphorus at about 11018 cm3 was deposited in situ in a UHV/CVD deposition tool on top of the SiGe-base to form the EB junction. This 77-K optimized SiGe HBT will be referred to as an epitaxial ‘‘emitter-cap’’ SiGe HBT [18]. Because EB carrier tunneling processes depend exponentially on the peak junction field, the lightly doped emitter is expected to minimize the parasitic EB tunneling current compared to a conventional ‘‘i–p–i’’ SiGe HBT design. In addition, the increase in carrier saturation velocity with cooling, as well as the presence of velocity overshoot in the CB space–charge region at 77 K, results in an onset current density of base push-out (Kirk effect) that is about 50% larger at 77 K than at 300 K [15]. Thus, compared to a 300-K design, the collector doping level can be decreased in an optimized 77-K profile. In this case, the doping level at the metallurgical CB junction was lowered from 11017 cm3 for the conventional SiGe HBT design to about 21016 cm3, and ramped upward toward the subcollector to minimize freeze-out deep in the neutral collector. This 77-K collector profile is used to reduce the parasitic CB capacitance under the constraint that the onset current density of the SiGe–Si heterojunction barrier be above the maximum operating current density of about 1.0 mA/mm2. To ensure a low emitter resistance, a 200-nm in situ doped polysilicon contact was deposited on top of the composite EB profile (n-cap/p-SiGe). Because the arsenic out-diffusion from the heavily doped polysilicon layer is used only to contact the epitaxial phosphorus emitter and does not determine the metallurgical EB junction, only a very short rapid thermal annealing (RTA) step is required to activate and redistribute the emitter dopants, allowing the maintenance of a thin, heavily doped base. A metallurgical emitter-cap thickness of about 10 nm was achieved at the end of processing (estimated by subtracting the arsenic out-diffusion of the emitter poly from the total EB junction depth). The boron doping of the base profile was increased over a more conventional i–p–i SiGe design to improve its base freeze-out properties, and was deposited as a box 10 nm wide by 2.5 1019 cm3. At the end of processing the metallurgical base was about 75 nm wide with a peak concentration of about 8 1018 cm3, well above the Mott transition for carrier freeze-out. To minimize minority carrier charge storage in the emitter-cap layer, a large 77 K b is also desirable (te / 1/bac). Therefore, a trapezoidal Ge profile with 3 to 4% Ge at the EB junction (compared to about 0 to 1% for the standard design) and ramping to 8.5% at the CB junction (compared to about 8.5% for the standard design) was used. The resultant emitter-cap Ge profile was about 65 nm thick, and satisfied the thermodynamic stability criteria for UHV/CVD blanket films. This 77-K SiGe design point yields a transistor with reasonably ideal Gummel characteristics at low temperatures, with a maximum output current drive well above 1.0 mA/mm2 at 84 K (Figure 4.9.3). The higher Ge concentration at the EB junction, the beneficial effects of the emitter high–low (nþ/n cap) junction, and the bandgap narrowing of the heavily doped base, offset the bandgap narrowing of the heavily doped emitter region to yield a peak b that increases quasi-exponentially with cooling from 102 at 310 K to 498 at 84 K (Figure 4.9.4). This large b value at low temperatures serves to minimize the unwanted charge storage associated with the emitter-cap layer as well as to circumvent the degradation of b at medium injection levels due to bias-dependent Ge ramp effects (refer to Chapter 4.3), giving an ideal value of b of 99 at 84 K at a typical circuit operating point of 1.0-mA collector current [18]. An undesirable result of the high b at low temperature, however, is a decrease in the BVCEO from 3.1 V at 310 K to 2.3 V at 84 K, but it remains acceptable for most circuit applications. Depending on circuit requirements at 77 K, the low-temperature current gain can be easily tuned to a desired value. The reduction in overall thermal cycle compared to a conventional design is key to maintaining the abrupt, as-deposited boron base profile, and thus providing immunity to carrier freeze-out at cryogenic temperatures (Rbi only increases from 7.7 to 11.0 kV/sq. between 310 and 84 K). Importantly, this immunity to base freeze-out does not come at the expense of increased EB leakage, as it does, for instance, in a spacer-free SiGe profile with a very heavily doped base [15]. The lower doping level of the emitter-cap layer results in a reverse EB leakage at 1.0 V at 84 K, which is more than 500 times smaller

© 2006 by Taylor & Francis Group, LLC

4.9-503

Temperature Effects

1100

Current gain

880

SiGe HBT ("emitter–cap") AE = 1.4⫻4.4 µm2 VCB = 0.0 V

5.84 K

35 K 660 77 K 440 142 K 220 300 K 0 10−6

10−5

10−4 10−3 Collector current (A)

10−2

FIGURE 4.9.4 Current gain versus bias current as a function of temperature for a 77-K optimized emitter-cap SiGe HBT. (From AJ Joseph, JD Cressler, and DM Richey. IEEE Electron Dev. Lett. 16:268–270, 1995. With permission.) 80

Cutoff frequency (GHz)

AE = 0.7⫻19.4 µm2 VCB = 1.0 V

tEC = 2.3 ps (85 K) tEC = 3.2 ps (300 K)

60 85 K 40

20

300 K

0 1

10 Collector current (mA)

100

FIGURE 4.9.5 Cutoff frequency characteristics at 300 and 85 K for a 77-K optimized emitter-cap SiGe HBT. (From JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. IEEE Electron Dev. Lett. 15:472–474, 1994. With permission.)

than for the conventional SiGe design. The consequence is a much smaller forward tunneling component in the base current (much larger low-current b), a smaller EB capacitance, and an expected improvement in hot-carrier reliability at cryogenic temperatures. As shown in Figure 4.9.5, the transistor cutoff frequency ( fT) rises from 43 to 61 GHz with cooling to 85 K due to the beneficial effects of the Ge-grading-induced drift field. This improvement in fT, coupled to the low total base resistance and slightly decreased CB capacitance, yields an increase in maximum oscillation frequency with cooling as well, from 40 GHz at 310 K to 50 GHz at 84 K. To assess the 77-K circuit capabilities of this technology, unloaded ECL ring oscillators were measured (Figure 4.9.6). Highpower (12.45 mW) ECL circuits switch at a record 21.9 psec at 84 K, 3.5 psec faster than at 310 K. Circuits that were optimized for lower power operation achieve a minimum power-delay product of 61 fJ (41.3 psec at 1.47 mW) at 84 K, and are 9.6 psec faster than at 310 K. These 77-K optimized ECL circuits are expected to exhibit even more dramatic improvements in speed over room-temperature ECL circuits under heavy loading, due to the beneficial effects of cooling on metal interconnect resistance and

© 2006 by Taylor & Francis Group, LLC

4.9-504

The Silicon Heterostructure Handbook

70

ECL gate delay (ps)

60

VL = 500 mV

50

310 K

FI/FO = 1

40

84 K

CW = 6 fF

30 310 K 41.3 ps at 1.47 mW (61 fJ)

84 K

20 21.9 ps AE = 0.52⫻1.52 µm2 AE = 0.72⫻4.42 µm2 10 0.1

0.2

0.3 0.5 0.7 1.0 2 Average switch current (mA)

3

4 5 6

FIGURE 4.9.6 Unloaded ECL gate delay as a function of power at 310 and 84 K. (From JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. IEEE Electron Dev. Lett. 15:472–474, 1994. With permission.)

circuit logic swing [16]. The delay improvement at long interconnect wire lengths can be dramatic (2.7 faster at 84 K than at 300 K at 10 mm wire length), and suggests that SiGe HBT based line-drivers might be attractive for 77-K applications. Recent measurements on non-cryogenically optimized 200 GHz, third-generation SiGe HBTs, show even more impressive performance down to liquid nitrogen temperature [19]. Current–voltage measurements across the 300 to 85 K temperature range were made on SiGe HBTs with an emitter area of 0.12 10.0 mm2. In spite of the high peak base and emitter doping levels associated with these aggressively scaled SiGe HBTs (>1019 cm3), the base current remains reasonably ideal at 85 K. This is the result of the lightly doped epitaxial spacer layer inserted between the base and emitter regions, and helps limit field-assisted tunneling and recombination at low temperatures. The base and emitter regions in this device are both doped above the Mott-transition, and ensure that carrier freeze-out does not negatively impact the base or emitter resistance below 100 K. This device is capable of very high current density operation (>25 mA/mm2), and thus the high collector doping level effectively limits the impact of heterojunction barrier effects at low temperatures. The current gain increases monotonically with cooling, from 600 at 300 K to 3800 at 85 K (Figure 4.9.7). Two mechanisms are responsible for this improvement with cooling: (1) the (sizable) Ge-induced band offset in this device (exponentially) increases the current gain with cooling, and (2) the heavily doped base region partially offsets the doping-induced bandgap narrowing associated with the emitter region. There is a strong decrease in the current gain above its peak value at 85 K associated with the Ge-grading effect, but the current gain remains above 2000 at 85 K at the current density at which peak fT is reached, effectively minimizing any emitter charge storage at low temperatures. Figure 4.9.7 also shows the extracted peak cutoff frequency versus temperature for the 0.12 10.0 mm2 SiGe HBT. An increase in peak fT from 200 GHz at 300 K to 260 GHz at 85 K is observed. This increase in the peak fT with cooling is proportionately smaller than has been reported in first-generation SiGe HBTs (Figure 4.9.5) operated at 85 K. This is because in the present case, the base and emitter transit times in this 200 GHz device, which are favorably affected by both the Ge-grading and cooling, are already small compared to the collector delay time, and thus their relative influence on the total transit time with cooling is smaller. The extrapolated total emitter-to-collector delay decreases from 0.7 psec at 300 K to 0.6 psec at 150 K and 0.5 psec at 85 K, and the total depletion capacitance of the device decreases with cooling, as expected, since the junction built-in voltages increase with cooling.

© 2006 by Taylor & Francis Group, LLC

4.9-505

Temperature Effects

4000

400

3500

350 Peak current gain

3000 2500

300

2000 250 1500 1000

200

Peak cutoff frequency (GHz)

AE = 0.12 µm⫻10 µm VCE = 1.2 V

500 50

100

150 200 250 Temperature (K)

300

150 350

FIGURE 4.9.7 Peak current gain and peak cutoff frequency as a function of temperature for a third-generation SiGe HBT. (From B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. With permission.)

AE = 0.12 µm⫻10 µm

Minimum noise figure (dB)

85 K

VCE = 1.2 V IC = 12 mA

4

25

20

300 K 15

3

10

2 300 K

Associated gain (dB)

5

5

1 85 K 0 5

10 15 20 Frequency (GHz)

0 25

FIGURE 4.9.8 Minimum noise figure and associated gain as a function of frequency at 300 and 85 K for a third-generation SiGe HBT. (From B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. With permission.)

Figure 4.9.8 shows the measured minimum noise figure (NFmin) and associated gain (Gassoc) as a function of frequency at IC ¼ 12 mA (i.e., at peak fT), for a 0.12 10.0 mm2 SiGe HBT, at both 300 and 85 K. At 85 K, this device achieves a minimum NFmin of about 0.3 dB (with Gassoc ¼ 18 dB) at 14 GHz, and a minimum NFmin of about 0.75 dB (Gassoc ¼ 15 dB) at 20 GHz, record numbers for SiGe HBTs operating at cryogenic temperatures.

© 2006 by Taylor & Francis Group, LLC

4.9-506

The Silicon Heterostructure Handbook

4.9.6 Helium Temperature Operation Long-wavelength infrared focal-plane-arrays (FPA) and certain ultra-low-noise instrumentation amplifiers require transistors that operate down to liquid helium temperature (LHeT ¼ 4.3 K). In addition to evaluating SiGe HBT performance at these potential application temperatures, the below 77-K regime is ideally suited for investigating new device physics phenomena, as well as for testing the validity of conventional theoretical formulations of device operation (e.g., drift-diffusion). This is particularly true for a SiGe HBT, since many of the transistor parameters are thermally activated functions of the Geinduced band offsets, and are expected to change dramatically between 77 and 4 K. For instance, a simple calculation of the intrinsic carrier density, to which the terminal currents are proportional, shows that a nio changes by a factor of e3056 between 77 and 4 K. Initial results on (unoptimized) Si BJTs to 10 K [20] showed transistor functionality but poor performance in the LHeT regime (<10 to 15 K). More recent work [21] on SiGe HBTs optimized for 77-K operation shows more impressive performance results as well as reveals interesting new device physics effects. The emitter-cap SiGe HBT optimized explicitly for 77 K achieved a b of 500, fT of 61 GHz, fmax of 50 GHz, and a minimum ECL gate delay of 21.9 psec at 84 K. In cooling this transistor from 77 K to LHeT, the current gain increases monotonically from 110 at 300 K to 1045 at 5.84 K, although parasitic base current leakage limits the useful operating current to above about 1.0 mA at 5.84 K. Figure 4.9.3 shows the Gummel characteristics of a 1.4 4.4 mm2 emitter-cap SiGe HBT down to 5.84 K, and Figure 4.9.4 shows the current gain as a function of bias current down to 5.84 K. The severity of the base current leakage at low injection, and the Ge-ramp effect at medium injection, limits the current range where one obtains the peak current gain. The aggressive base profile design in close to 8 1018 cm3) leads to an Rbi of <18 kV/sq. at the emitter-cap SiGe HBT design (peak Nab 5.84 K, much lower than a more conventional SiGe HBT design. Base freeze-out below 77 K depends very strongly on peak base doping, and must be carefully optimized for LHeT applications. At temperatures as low as 5.84 K, this transistor has a maximum current drive in excess of 1.5 mA/mm2 (limited by quasi-saturation and heterojunction barrier effects), with a peak transconductance of 190 mS. Theoretical calculations based on measured SIMS data were compared to the experimentally observed variation of peak current gain with temperature. Above 77 K, the temperature variation of peak current gain for the SiGe HBT is close to that theoretically expected, while at temperatures below 77 K, the exponential increase in current gain is primarily limited by parasitic base leakage due to fieldenhanced tunneling. In contrast to this strong enhancement of current gain with cooling for the SiGe HBT, the current gain in a Si BJT fabricated with a comparable doping profile is significantly degraded at low temperatures, due to the strong bandgap narrowing in the emitter. A comprehensive discussion of other unique cryogenic phenomena in SiGe HBTs operating in the LHeT environment is presented in Ref. [1].

4.9.7 High-Temperature Operation While it has been demonstrated that SiGe HBTs operate well down to deep cryogenic temperatures, there was historically early concern about their suitability for operation at elevated temperatures. Given that all electronic systems must successfully operate at temperatures considerably above 300 K (e.g., 1258C to satisfy military specifications and 858C for many commercial applications), this is a potentially important issue. Given the narrow bandgap base region of the SiGe HBT compared to a Si BJT, and hence the expected negative temperature coefficient of the current gain (i.e., b decreases as temperature increases), it was often asked whether practical SiGe HBTs would have acceptable values of b at required high-end operational temperatures (e.g., 1258C). That this issue is not a valid concern for circuit designers is clearly demonstrated in Figure 4.9.9, which compares the percent change in peak current gain between 25 and 1258C for a Si BJT and a number or commercially relevant SiGe profiles. There are several important points to glean from these data:

© 2006 by Taylor & Francis Group, LLC

4.9-507

Temperature Effects

+25

Change in b from 25 to 125⬚C (%)

+20

VCB = 1.0 V

+15 +10 +5 0 −5 −10 −15 −20 −25 Si BJT

15%Ge Triangle

8%Ge 10%Ge 14%Ge Trapezoid Trapezoid Low-Noise

Ge profile shape

FIGURE 4.9.9 Percent change in peak current gain between 25 and 1258C for various Ge profiles. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

The current gain in SiGe HBTs does indeed have an opposite temperature dependence from that of a Si BJT, as expected from simple theory. These changes in b between 25 and 1258C, however, are modest at best (<25%), and clearly not cause for alarm for any realistic circuit. The negative temperature coefficient of b in SiGe HBTs is tunable, meaning that its temperature behavior between, say, 25 and 1258C can be trivially adjusted to its desired value by changing the Ge profile shape near the EB junction. In the case of the 15% Ge triangle profile, with 0% Ge at the EB junction, b is in fact temperature independent from 25 to 1258C. This points to a major advantage of bandgap engineering. Finally, it is well known that thermal-runaway in high-power Si BJTs is the result of the positive temperature coefficient of b (i.e., as the device heats up due to power dissipation, one gets more bias current since the b increases with temperature, leading to a positive feedback process, and hence thermal collapse). The fact that SiGe HBTs naturally have a negative temperature coefficient for b suggests that this might present interesting opportunities for power amplifiers, since emitter ballasting resistors (which degrade RF gain) could in principle be eliminated.

There is also an emerging interest in the operation of electronic devices above 1258C, for planetary space missions (e.g., Venus), or for on-engine electronics for both the automotive and aerospace sectors to support the ‘‘more-electric-vehicle’’ thrust of the military. In these cases, allowing the requisite electronic components to operate at relatively high temperatures (say 200 to 2508C) presents compelling cost-saving advantages, since the cooling system constraints can be dramatically relaxed. Conventional wisdom dictates that Si-based devices not be considered for these types of high-temperature applications, since Si is a fairly low-bandgap material, and thermal leakage (i.e., Ion/Ioff ratios) depends exponentially on Eg. The fact that SiGe HBTs are capable of operation in such high-temperature environments can be easily demonstrated experimentally (as shown in Figure 4.9.10 and Figure 4.9.11). While performance degradation generally results at high temperatures, in these second-generation SiGe HBTs the peak

© 2006 by Taylor & Francis Group, LLC

4.9-508

The Silicon Heterostructure Handbook

current gain remains above 125 at 3008C and the peak fT/fmax above 90 GHz at 2008C [22]. No serious reliability degradation mechanisms were identified at elevated temperatures. Thus, there is no fundamental reason why SiGe HBTs cannot satisfy this important emerging niche application of hightemperature electronics. 500 High-breakdown High-performance AE = 0.28⫻4.6 µm2 VCB = 0 V

400

Current gain

25⬚C

300 150⬚C 200 300⬚C 100

0 10−12

10−10

10−8 10−6 Collector current (A)

10−4

10−2

FIGURE 4.9.10 Current gain as a function of collector current at various temperatures for both high-performance (low-breakdown) and high-breakdown second-generation SiGe HBTs. (From T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004. With permission.) 150 fT 25⬚C fmax 25⬚C fT 100⬚C fmax 100⬚C fT 200⬚C fmax 200⬚C

fT/ fmax (GHz)

100

High-performance AE = 0.28⫻4.6 µm2 VCB = 1 V

50

0

10−4

10−3 10−2 Collector current (A)

10−1

FIGURE 4.9.11 Cutoff frequency as a function of collector current at various temperatures for a second-generation SiGe HBT. (From T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

Temperature Effects

4.9-509

4.9.8 Summary Bandgap engineering has a positive influence on the low-temperature characteristics of bipolar transistors, enabling conventionally designed SiGe HBTs to operate very well in the cryogenic environment. We have addressed the effects of temperature on SiGe HBT device and circuit operation, by showing how temperature couples to SiGe HBT dc and ac performance, addressing how one optimizes SiGe HBTs specifically for cryogenic operation, and finally by considering the operation of SiGe HBTs at high temperatures. We conclude that the operation of SiGe HBTs at extreme temperatures (both low and high) is a viable path for commercial SiGe technology, and of potential importance for a growing number of niche applications.

Acknowledgments I am grateful to A. Joseph, T. Chen, R. Krithivasan, Y. Lu, D. Richey, B. Banerjee, S. Nuttinck, G. Niu, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by Hypres, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. WL Kauffman and AA Bergh. The temperature dependence of ideal gain in double diffused silicon transistors. IEEE Trans. Electron Dev. 15:732–735, 1968. 3. ES Schlig. Low-temperature operation of Ge picosecond logic circuits. IEEE J. Solid-State Circuits 3:271–276, 1968. 4. D Buhanan. Investigation of current-gain temperature dependence in silicon transistors. IEEE Trans. Electron Dev. 16:117–124, 1969. 5. WP Dumke. Effect of minority carrier trapping on the low-temperature characteristics of Si transistors. IEEE Trans. Electron Dev. 17:388–389, 1970. 6. WP Dumke. The effect of base doping on the performance of Si bipolar transistors at low temperatures. IEEE Trans. Electron Dev. 28:494–500, 1981. 7. JD Cressler, DD Tang, KA Jenkins, GP Li, and ES Yang. On the low-temperature static and dynamic properties of high-performance silicon bipolar transistors. IEEE Trans. Electron Dev. 36:1489–1502, 1989. 8. JD Cressler, DD Tang, KA Jenkins, and GP Li. Low temperature operation of silicon bipolar ECL circuits. Technical Digest of the IEEE International Solid-State Circuits Conference, New York, 1989, pp. 228–229. 9. JMC Stork, DL Harame, BS Meyerson, and TN Nguyen. High performance operation of silicon bipolar transistors at liquid nitrogen temperature. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 405–408. 10. JCS Woo and JD Plummer. Optimization of bipolar transistors for low temperature operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 401–404. 11. K Yano, K Nakazato, M Miyamoto, M Aoki, and K Shimohigashi. A high-current-gain lowtemperature pseudo-HBT utilizing a sidewall base-contact structure (SICOS). IEEE Electron Dev. Lett. 10:452–454, 1989. 12. JD Cressler, TC Chen, JD Warnock, DD Tang, and ES Yang. Scaling the silicon bipolar transistor for sub-100-ps ECL circuit operation at liquid nitrogen temperature. IEEE Trans. Electron Dev. 37:680– 691, 1990. 13. EF Crabbe´, GL Patton, JMC Stork, JH Comfort, and BS Meyerson. The low-temperature operation of Si and SiGe bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20.

© 2006 by Taylor & Francis Group, LLC

4.9-510

The Silicon Heterostructure Handbook

14. JD Cressler, JH Comfort, EF Crabbe´, GL Patton, W Lee, JY-C Sun, JMC Stork, and BS Meyerson. Sub-30-ps ECL circuit operation at liquid-nitrogen temperature using self-aligned epitaxial SiGebase bipolar transistors. IEEE Electron Dev. Lett. 12:166–168, 1991. 15. JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JY-C Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part I. Transistor dc design considerations. IEEE Trans. Electron Dev. 40:525–541, 1993. 16. JD Cressler, EF Crabbe´, JH Comfort, JMC Stork, and JY-C Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part II. Circuit performance issues. IEEE Trans. Electron Dev. 40:542–556, 1993. 17. JH Comfort, EF Crabbe´, JD Cressler, W Lee, JY-C Sun, J Malinowski, M D’Agostino, JN Burghartz, JMC Stork, and BS Meyerson. Single crystal emitter cap for epitaxial Si- and SiGe-base transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 857–860. 18. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter-cap SiGe-base bipolar technology optimized for liquid-nitrogen temperature operation. IEEE Electron Dev. Lett. 15:472–474, 1994. 19. B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Cryogenic Performance of a 200 GHz SiGe HBT Technology. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. 20. AK Kapoor, HK Hingarh, and TS Jayadev. Operation of poly emitter bipolar npn and p-channel JFETs near liquid-helium (10 K) temperature. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1988, pp. 210–214. 21. AJ Joseph, JD Cressler, and DM Richey. Operation of SiGe heterojunction bipolar transistors in the liquid-helium temperature regime. IEEE Electron Dev. Lett. 16:268–270, 1995. 22. T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004.

© 2006 by Taylor & Francis Group, LLC

4.10 Radiation Effects

John D. Cressler Georgia Institute of Technology

4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 4.10.6 4.10.7 4.10.8

Introduction........................................................... 4.10-511 DC Effects .............................................................. 4.10-511 AC Small-Signal and Noise Effects ...................... 4.10-514 Origin of Radiation Hardness .............................. 4.10-515 Low-Dose-Rate Effects .......................................... 4.10-516 SiGe HBT Circuit Tolerance................................. 4.10-516 Single-Event Upset ................................................ 4.10-517 Summary ................................................................ 4.10-521

4.10.1 Introduction There are currently two recent but rapidly growing thrusts within the space electronics community: (1) the use of commercial-off-the-shelf (COTS) parts whenever possible for space-borne systems as a cost-saving measure; and (2) the use of system-on-a-chip integration to lower chip counts and system costs, as well as simplify packaging and lower total system launch weight. The ‘‘holy-grail’’ in the realm of space electronics can thus be viewed as a conventional terrestrial IC technology with a system-on-achip capability, which is also radiation-hard as fabricated, without requiring any additional process modifications or layout changes. It is within this context that we discuss SiGe HBT BiCMOS technology as potentially such a ‘‘radiation-hard-as-fabricated’’ IC technology with possibly far-ranging implications for the space community. Within the context of existing data for radiation exposure of SiGe HBTs, it is meaningful to distinguish between different SiGe HBT technology nodes, and is loosely defined by the ac performance of the SiGe HBT (e.g., peak fT, which is a very strong function of the vertical profile and hence nicely reflects the degree of sophistication in structural design, lateral dimensional scaling, profile scaling, and net thermal cycle). We thus label a SiGe HBT technology node having a SiGe HBT with a peak fT of roughly 50 GHz as ‘‘first-generation’’ (e.g., SiGe 5HP from IBM [1]), that with a peak fT of roughly 100 GHz as ‘‘secondgeneration’’ (e.g., SiGe 7HP from IBM [2]), that with a peak fT of roughly 200 GHz as ‘‘third-generation’’ (e.g., SiGe 8HP from IBM [3]), and that with a peak fT of roughly 300 GHz as ‘‘fourth-generation’’ (e.g., SiGe 9T from IBM [4]). For brevity, here we only discuss radiation effects in SiGe HBT. For discussion on the impact of radiation on the Si CMOS devices found the SiGe HBT CMOS, the reader is referred to Ref. [5]. More recent results on other commercial SiGe HBT technology platforms (than the IBM results presented here) can be found in Refs. [6, 7].

4.10.2 DC Effects The response of SiGe HBTs to a variety of radiation types has been reported, including gamma rays, neutrons, and protons [8–14]. Since protons induce both ionization and displacement damage, they can be considered the worst case for radiation tolerance. For the following results, relevant proton energy of 63 MeV was used. At proton fluences of 1 1012 p/cm2 and 5 1013 p/cm2, the measured equivalent 4.10-511 © 2006 by Taylor & Francis Group, LLC

4.10-512

The Silicon Heterostructure Handbook

total ionizing dose (TID) was approximately 135 and 6759 krad(Si), respectively, the latter being far larger than most orbital missions require. The typical response of a SiGe HBT to irradiation can be seen in Figure 4.10.1, which shows typical measured Gummel characteristics of a fourth-generation SiGe HBT, both before and after exposure to protons [8–14]. As expected, the base current increases after sufficiently high proton fluence due to the production of generation/recombination (G/R) trapping centers, and hence the current gain of the device degrades. There are two main physical origins of this degradation. The base current density is inversely proportional to the minority carrier lifetime in the emitter, so that a degradation of the hole lifetime will induce an increase in the base current. In addition, ionization damage due to the charged nature of the proton fluence produces interface states and oxide-trapped charges in the spacer layer at the emitter–base junction. These G/R centers also degrade IB, particularly if they are placed inside the EB space–charge region, where they will yield an additional non-ideal base current component (non-kT/q exponential voltage dependence). By analyzing a variety of device geometries, it can be shown that the radiation-induced excess base current is primarily associated with the EB spacer oxide at the periphery of the transistor, as naively expected, and is hence the radiation response is dominated by ionization damage rather than displacement damage. The radiation-induced degradation of the base current and current gain for four generations of SiGe technology are shown in Figure 4.10.2 and Figure 4.10.3. Less than 30% degradation in peak current gain is observed across all four technology nodes, to 1.0 Mrad(Si) equivalent radiation levels, suggesting that SiGe HBTs are robust to TID for typical orbital proton fluences for realistic circuit operating currents above roughly 100 mA without any additional radiation hardening. These results are significantly better than for conventional diffused or even ion-implanted Si BJT technologies (even radiation-hardened ones). Of particular interest is the inference of the spatial location of the proton-induced traps in these devices [10]. The existence of proton-induced traps in the EB space–charge region is clearly demonstrated by the G/R-induced increase in the non-ideal base current component shown in the Gummel

Collector and base current density (A/µm2)

10–1

Forward mode A E = 0.12⫻2.5 µm2 Low breakdown

10–3

VCB = 0 V 300 K

10–5

Pre-radiation 1⫻1012p/cm2 7⫻1012p/cm2 2⫻1013p/cm2 5⫻1013p/cm2 Self-anneal of post 5⫻1013p/cm2

10–7

10–9

10–11 0.4

0.5

0.6

0.7

0.8

0.9

1.0

Base−emitter voltage (V)

FIGURE 4.10.1 Forward-mode Gummel characteristics of a fourth-generation, 350 GHz SiGe HBT, during radiation exposure. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-513

Radiation Effects

I B(post)/I B(pre)

70 60

Forward mode

50

AE = 0.12⫻2.5 µm2(9T)

40

VBE = 0.6 V VCB = 0 V 300 K

30 20 10 0 1⫻1012

5HP (AE = 0.5⫻2.5 µm2) 7HP (AE = 0.16⫻1.6 µm2) 8HP (AE = 0.12⫻10 µm2) 9T Low BVCEO 9T High BVCEO

1⫻1013 Proton fluence

1⫻1014 (p/cm2)

FIGURE 4.10.2 Normalized base current degradation for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

1.1 AE = 0.12⫻2.5 µm2(9T)

1.0

VCB = 0 V 300 K

Peak bpost / bpre

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1⫻1012

5HP (AE = 0.5⫻2.5 µm2) 7HP (AE = 0.16⫻1.6 µm2) 9T Low BVCEO 9T High BVCEO 1⫻1013

1⫻1014

Proton fluence (p/cm2)

FIGURE 4.10.3 Current gain degradation for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-514

The Silicon Heterostructure Handbook

characteristics. The existence of radiation-induced traps in the collector–base space–charge region was verified by measuring the inverse mode Gummel characteristics of the device (emitter and collector leads swapped). In this case the radiation-induced traps in the CB junction now act as G/R centers in the inverse EB junction, with a signature non-kT/q exponential slope. Two-dimensional simulations were calibrated to both measured data for the pre- and post-irradiated devices at a collector–base voltage of 0.0 V. In order to obtain quantitative agreement between the simulated and measured irradiated results, traps must be located uniformly throughout the device, and additional interface traps must be located around the emitter–base spacer oxide edge. Most of the radiationinduced recombination occurs inside the EB space–charge region, leading to a non-ideal base current, as expected.

4.10.3

AC Small-Signal and Noise Effects

To assess the impact of radiation on the ac performance of the transistors, the S-parameters were measured to 40 GHz both before and after proton exposure [15]. From the measured S-parameters, the transistor cutoff frequency as a function of bias current density can be extracted, and is shown for four technology generations in Figure 4.10.4. Only a slight degradation in fT (and fmax) is observed, the latter expected from the minor increase of the base resistance with irradiation, due to either carrier removal, mobility and lifetime changes, or both. The broadband noise performance of SiGe HBTs is critical for space-borne transceivers and communications platforms. As shown in Figure 4.10.5, the minimum noise figure (NFmin) degrades only slightly at 2.0 GHz in a first-generation SiGe HBT after an extreme proton fluence of 51013 p/cm2 (from 0.95 dB to a still-excellent value of 1.07 dB, a 12.6% degradation). SiGe HBTs have the desirable feature of low 1/f noise commonly associated with Si bipolar transistors, which is of great importance because upconverted low-frequency noise (phase noise) typically limits the spectral purity of communication systems. Understanding the effects of radiation on 1/f noise in SiGe HBTs thus becomes a crucial issue for space-borne communications electronics. Physically, 1/f noise results from the presence of G/R center traps in the transistors, from which trapping–detrapping

400

Cutoff frequency (GHz)

350 300

VCB = 1.0 (5HP,7HP,8HP) VCB = 0.5 V (9T) 300 K

9T

250 8HP

200 150 100 50 0 0.1

Pre-radiation 7⫻1012p/cm2 5⫻1013p/cm2

7HP 5HP

1.0 10 Collector current density (mA/µm2)

100

FIGURE 4.10.4 Pre- and post-radiation cutoff frequency versus bias current density for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-515

Radiation Effects

3.5

NFmin (dB)

3.0

f = 10 GHz

2.5

AE = 0.5⫻20⫻2 µm2 VCB = 1 V IC = 2.6 mA

2.0 f = 4 GHz

1.5 1.0

f = 2 GHz 0.5 1012

Pre

1013

1014

Proton radiation fluence (p/cm2)

FIGURE 4.10.5 Extracted minimum noise figure as a function of proton fluence for multiple frequencies for firstgeneration SiGe HBTs. (From S Zhang, G Niu, SD Clark, JD Cressler, and M Palmer. IEEE Trans. Nuclear Sci. 46:1716–1721, 1999. With permission.) 10–19 SiGe HBT Ae = 0.5⫻1 µm2 I B = 4 µA Pre-irradiation 2⫻1013 p/cm2

S IB (A2/Hz)

10–20 10–21 10–22 10–23

∝1/f

10–24

2qIB

10–25 100

101

102

103

104

105

Frequency (Hz)

FIGURE 4.10.6 Input-referred base current low-frequency noise for a first-generation SiGe HBT, before and after irradiation. (From Z Jin, G Niu, JD Cressler, C Marshall, P Marshall, H Kim, R Reed, and D Harame. IEEE Trans. Nuclear Sci. 48:2244–2249, 2001. With permission.)

processes occur while carriers flow inside the device, thus modulating the number of carriers (and hence currents) to produce 1/f noise. The pre-irradiation low-frequency noise spectrum in these SiGe HBTs is typically 1/f, with an IB2 dependence, while SIB AE is almost independent of AE. The IB2 and 1/AE dependencies of SIB are strong indicators of uniformly distributed noise sources over the entire emitter area. After 2 1013 p/cm2 proton irradiation, the low-frequency noise spectrum in first-generation SiGe HBTs remains 1/f in frequency dependence, and free of G/R (burst) noise, and at roughly the same noise magnitude (i.e., no radiation-induced degradation) (as can be seen in Figure 4.10.6) [16].

4.10.4 Origin of Radiation Hardness We note that careful comparisons between identically fabricated SiGe HBTs and Si BJTs (same device geometry and wafer lot, but without Ge in the base for the epitaxial-base Si BJT) show that the extreme level of total dose tolerance of SiGe HBTs is not per se due to the presence of Ge [10]. That is, the proton response of both the epitaxial base SiGe HBT and Si BJT is nearly identical. We thus attribute the

© 2006 by Taylor & Francis Group, LLC

4.10-516

The Silicon Heterostructure Handbook

observed radiation hardness to the unique and inherent structural features of the device itself, which from a radiation standpoint can be divided into three major aspects: (1) in these epitaxial base structures, the extrinsic base region is very heavily doped (>5 1019 cm3) and located immediately below the emitter–base (EB) spacer oxide region, effectively confining any radiation-induced damage, and its effects on the EB junction; (2) the EB spacer, known to be the most vulnerable damage point in conventional BJT technologies, is thin (<0.20 mm wide) and composed of an oxide–nitride composite, the latter of which is known to produce an increased level of radiation immunity; (3) the active volume of these transistors is very small (emitter stripe width WE ¼ 0.5 mm, and base width Wb < 150 nm), and the emitter, base, and collector doping profiles are quite heavily doped, effectively lessening the impact of displacement damage. We also note that these SiGe HBTs compare very favorably in both performance and radiation hardness with (more expensive) GaAs HBT technologies that are often employed in space applications requiring both very high speed and an extreme level of radiation immunity [17].

4.10.5

Low-Dose-Rate Effects

Within the past few years, a pronounced low-dose-rate sensitivity to gamma irradiation that is not screened by the current test methods for ionizing radiation has been observed in Si bipolar technologies. The enhancement in device and circuit degradation at low gamma dose rates has come to be known as ‘‘enhanced low-dose-rate sensitivity’’ (ELDRS) [18–20]. The ELDRS effect was first reported in 1991, which demonstrated that existing radiation hardness test assurance methodologies were not appropriately considering worst-case conditions. The physical origins underlying ELDRS have been hotly debated for years, and numerous mechanisms proposed. Recent attempts to understand ELDRS include a model suggesting that the lower net radiation-induced trapped charge density at high-dose-rates is a result of a space–charge phenomenon, caused by delocalized hole traps that occur in heavily damaged oxides such as bipolar base oxides. These traps can retain holes on a timescale of seconds to minutes, causing a buildup of positive charge in the oxide bulk during high-dose-rate irradiation. This is in contrast to lowdose-rate irradiation, where the irradiation time is much longer, effectively allowing the holes in the trap centers to be detrapped. Thus, in the high-dose-rate case, the larger total trapped hole density forces holes near the interface to be trapped closer to the interface, where they can be compensated by electrons from the silicon. This lowers the resultant net trapped charge density. To assess ELDRS in first-generation SiGe technology, low-dose-rate (0.1 rad(Si)/sec) and high-doserate (300 rad(Si)/sec) experiments were conducted using Cobalt-60 [21]. As can be seen in Figure 4.10.7, low-dose-rate effects in these first-generation SiGe HBTs were found to be nearly non-existent, in striking contrast to reports of strong ELDRS in conventional Si bipolar technologies. We attribute this observed hardness to ELDRS to the same mechanisms responsible for the overall radiation hardness of the technology, and is likely more structural in nature than due to any unique advantage afforded by the SiGe base. Interestingly, an anomalous decrease in base current was also found in these devices at lowdose-rates, suggesting that a new physical phenomenon is present at low-dose-rates in these devices.

4.10.6

SiGe HBT Circuit Tolerance

For the successful deployment of SiGe technology into space-based systems, circuit-level radiation hardness is clearly more important than device-level hardness. As presented above, the TID device degradation is minor in the bias range of interest to most actual circuits (typically IC > 100 mA). In order to assess the impact of radiation exposure on actual SiGe HBT circuits, we have compared two very important, yet very different circuit types, one heavily used in analog ICs (the bandgap reference circuit), and one heavily used in RFICs (the voltage-controlled oscillator) [22, 23]. Each circuit represents a key building block for realistic SiGe ICs that might be flown in space. Each of these SiGe HBT circuits was designed using fully calibrated SPICE models, layed-out, and then fabricated on the same wafer to facilitate unambiguous comparisons. In addition, because any realistic RF IC must also

© 2006 by Taylor & Francis Group, LLC

4.10-517

Radiation Effects

600

X-ray 25⬚C (Nowlin et al.) Cobalt 25⬚C (Nowlin et al.) X-ray 60⬚C (Nowlin et al.) Cobalt 25⬚C (This Work)

500

∆I B/I B (%)

400 300 200

100 krad (SiO2) VBE = 0.6 V This Work − 0.5⫻2.5 µm2 SiGe HBT Nowlin et al. − 1.5⫻1.5 µm2 Si BJT

100 0 −100 0.1

1

10

100

1000

Dose rate [rad(SiO2)/S]

FIGURE 4.10.7 Normalized base current as a function of gamma radiation dose rate, for both Si BJTs and firstgeneration SiGe HBTs. (From G Banerjee, G Niu, JD Cressler, SD Clark, MJ Palmer, and DC Ahlgren. IEEE Trans. Nuclear Sci. 46:1620–1626, 1999. With permission.)

necessarily include passive elements such as monolithic inductors and capacitors, we have also investigated the effects of proton exposure on an RF LC bandpass filter. As can be seen from the data (Figure 4.10.8), the impact of even extreme proton fluences has minimal effect on either the output voltage or temperature sensitivity of BGRs, the phase noise or tuning range of VCOs or passive elements, and is indicative of the overall robustness of this SiGe technology for analog and RF circuit applications.

4.10.7 Single-Event Upset Clearly, a space-qualified IC technology must demonstrate sufficient SEU immunity to support highspeed circuit applications as well as possess TID tolerance. It is well known that even III–V technologies that have significant TID tolerance often suffer from poor SEU immunity, particularly at high data rates. Recently, high-speed SiGe HBT digital logic circuits were found to be vulnerable to SEU at even low linear energy transfer (LET) values [24–26]. In addition, successfully employed III–V HBT circuit-level hardening schemes using the current-sharing hardening (CSH) technique were found to be ineffective for these SiGe HBT logic circuits (Figure 4.10.9). To understand single-event effects in SiGe HBTs, one must use calibrated two-dimensional or three-dimensional device simulation to assess the charge collection characteristics of SiGe HBTs. These device-level simulation results can then be coupled to circuit-level modeling to better understand circuit-level mitigation approaches. From a device perspective, it is important to first assess the transistor charge collection characteristics as a function of terminal bias, load condition, substrate doping, and ion strike depth [27, 28]. Bias and loading conditions were chosen to mimic representative circuit conditions within an actual ECL/CML digital circuit. Figure 4.10.10 shows the charge collected by the collector versus time for different RC loads. The base and emitter terminals were grounded, the substrate bias was 5.2 V, the collector was connected to ground through an RC load, and the substrate doping was 5 1015 cm3. A uniform LET of 0.1 pC/mm (equivalent to 10 MeV cm2/mg) over 10-mm depth was used, which generates a total charge of 1.0 pC. The results clearly show that charge collection is highly dependent on the transistor load condition (i.e., circuit topology). As the load resistance increases, the collector-collected charge decreases. Note, however, that the emitter-collected charge increases correspondingly. The underlying physics is that more electrons exit through the emitter, instead of the collector. A larger load resistance presents a higher impedance to the electrons at the collector, and thus more electrons exit through the emitter.

© 2006 by Taylor & Francis Group, LLC

4.10-518

The Silicon Heterostructure Handbook

Pre-radiation After 5⫻1013 p/cm2 VCC 3.0 3.0 ICC 0.773 0.767 Bandgap 1.37416 reference Vout at 300 K 1.372096 Stability 81.7 81.2 (−55 to 85⬚C) 5.0 5.0 Frequency Vcc 3.3 3.3 Voltage ICC 22.5 22.5 controlled −5.0 −5.5 Outpout power oscillator −112.5 −111.8 Phase noise Tunning range 4,55−5,452 4,623−5,470 1.9 1.9 Frequency Filter Q 7.6 7.6 (at 3 dB BW) 16.8 16.8 LC bandpass Insertion Loss 2.5 2.5 L filter 7.4 7.4 Inductor Q 6.0 6.0 C 58 58 Capacitor Q SiGe HBT Circuit

Parameters

Units V mA V ppm/⬚C GHz V mA dBm dBc/Hz MHz GHz − dB nH − pF −

FIGURE 4.10.8 Summary of the measured radiation tolerance of some important first-generation SiGe HBT circuits and passives. (From JD Cressler, MC Hamilton, R Krithivasan, H Ainspan, R Groves, G Niu, S Zhang, Z Jin, CJ Marshall, PW Marshall, HS Kim, RA Reed, MJ Palmer, AJ Joseph, and DL Harame. IEEE Trans. Nuclear Sci. 48:2238–2243, 2001. With permission.)

Device cross-section (cm2)

1.0⫻10−3 1.0⫻10−4 1.0⫻10−5 C-12 at 1.6 Gbps F-19 at 1.6 Gbps

1.0⫻10−6

Si-28 at 1.6 Gbps CI-35 at 1.6 Gbps

1.0⫻10−7

Ni-58 at 1.6 Gbps Br-79 at 1.6 Gbps

1.0⫻10−8 1.0⫻10−9 0.0

10.0

20.0 30.0 40.0 50.0 LET (MeV ⫻ cm2/mg)

60.0

70.0

80.0

FIGURE 4.10.9 Experimental SEU cross-section test data on first-generation SiGe HBT shift registers. (From P Marshall, MA Carts, A Campbell, D McMorrow, S Buchner, R Stewart, B Randall, B Gilbert, and R Reed. IEEE Trans. Nuclear Sci. 47:2669–2674, 2000. With permission.)

The collector of the adjacent device only collects a negligible amount of charge, despite the transient current spikes of the strike. Nearly all the electrons deposited are collected by the collector and the emitter, although the partition between emitter and collector collection varies with the load condition. The impact on the SiGe base layer on the charge collection properties is a secondary effect. To better understand circuit-level SEU response, we combined these simulated charge–time profiles with circuit-level modeling in three different SiGe circuit architectures [29]. Circuit A is a

© 2006 by Taylor & Francis Group, LLC

4.10-519

Radiation Effects

Collector-collected charge (pC)

1.2 1.0

VB = 0 V, VE = 0 V VSUB = –5.2 V

R = 1.2 kΩ C = 15 fF R = 10 kΩ C = 2 fF R = 100 kΩ C = 2 fF R = 100 kΩ C = 15 fF

0.8 0.6 0.4 0.2 0.0 0

2

4

6

8

10

Time (ns)

FIGURE 4.10.10 Simulated collector-collected charge versus time for different RC loads. (From G Niu, R Krithivasan, JD Cressler, P Marshall, C Marshall, R Reed, and D Harame. IEEE Trans. Nuclear Sci. 48:1849–1854, 2001. With permission.)

straightforward ECL implementation of the standard rising edge-triggered flip-flop logic. Circuit B is the unhardened version of the D flip-flop used in the shift register results shown in Figure 4.10.9. Circuit B uses fewer transistors and thus less power than circuit A, and is also faster than circuit A, allowing operation at higher clock rates. Because of these advantages, circuit B is very popular in highspeed bipolar digital circuit design. The circuit consists of a master stage and a slave stage. The master stage consists of a pass cell, a storage cell, a clocking stage, and a biasing control. The slave stage has a similar circuit configuration. Circuit C is the current-sharing hardened version of circuit B. (Refer to Ref. [5] for circuit-level schematics for A, B, and C.) The circuit was used as a basic building block of the 32-stage shift-register data shown in Figure 4.10.9. In this case, the current source transistor is divided into five paths, and these paths are maintained separately through the clocking stage and through the pass and storage cells. In essence, the input and output nodes of five copies of the switching circuits, including the controlling switch, clock, master, and storage cells, are connected in parallel. The load resistance is shared by all the current paths. The quasi-three-dimensional simulated SEU-induced transient currents were activated on one of the sensitive transistors in the respective circuits. The SEU currents were activated at 5.46 nsec (within the circuit hold time), immediately after the clock goes from low to high, a sensitive time instant for SEU-induced transient currents to produce an upset at the output. The input data are an alternating ‘‘0’’ and ‘‘1’’ series with a data rate of 2 Gbit/sec. Under these conditions, circuit A shows no upset at all, while circuits B and C show five and three continuous bits of data upset, respectively (Figure 4.10.11). These results suggest that circuit A has the best SEU tolerance, while circuit C, the CSH hardened version, has better SEU tolerance than its unhardened companion version, circuit B. Circuit A, which shows no data upset at a switching current of 1.5 mA, does in fact show an upset when the switching current is lowered to 0.6 mA. This is consistent with our earlier observation that increasing switching current is effective in improving SEU performance for circuit C. The fundamental reason for the observed better SEU tolerance of circuit A than for circuits B and C is that only one of the two outputs of the emitter-coupled pair being hit is affected by the ion-strike SEU current transients. As long as the differential output is above the logic-switching threshold, the output remains unaffected, and no upset occurs. The collector voltage of the switching transistor decreases upon ion strike (compared to without SEU), however, and no upset is observed at the output, simply because the differential output remains above or below the relevant-switching threshold (Figure 4.10.12). These results suggest that circuit-level mitigation techniques can be used in SEU

© 2006 by Taylor & Francis Group, LLC

V1, V2 and clock (V)

4.10-520

The Silicon Heterostructure Handbook

0.2

V1

−0.2 −0.4 3

Data, Q, and clock (V) (V1−V2) and clock (V)

V2

0

4

5

6

7

8

9

10

7

8

9

10

Time (ns) 0.4 0.2 0 −0.2 −0.4 −0.6 3

138 mV

−113 mV 4

5

6 Time (ns)

0.5

No upset

Q

0 −0.5

Data

−1.5

3

Clock

Ion strike at 5.46 ns

−1 4

5

6

7

8

9

10

Time (ns)

V1, V2 and clock (V)

FIGURE 4.10.11 Simulated circuit A output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA. (From G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. With permission.)

V1

0 −0.2 −0.4 3

Data, Q, and clock (V) (V2−V1) and clock (V)

V2

0.2

4

5

6

7

8

9

10

7 Time (ns) Upsets

8

9

10

9

10

Time (ns) 0.4 0.2 0 −0.2 −0.4 −0.6

143 mV

113 mV 3

4

5

6

0.5 Q 0 −0.5

Clock

Ion strike at 5.46 ns

Data

−1 3

4

5

6

7

8

Time (ns)

FIGURE 4.10.12 Simulated circuit B output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA. (From G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

Radiation Effects

4.10-521

hardening of SiGe HBT logic, albeit at some level of additional power dissipation and circuit complexity. A potential SEU-hardening approach has been recently discussed in Ref. [30], but clearly more research is needed in the area of SEU mitigation before widespread deployment of SiGe circuitry in space is attempted.

4.10.8 Summary While ionizing radiation degrades both the dc and ac performance of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. While technology scaling can negatively impact the TID response of the SiGe HBT, it naturally improves the hardness of the CMOS devices, and thus 200 to 300 krad tolerance of the full BiCMOS technology can be achieved without radiation-hardening in second-generation SiGe HBT BiCMOS technology. Taken together, SiGe HBT BiCMOS technology offers many interesting possibilities for SoC applications of space-borne electronic systems.

Acknowledgments I am grateful to A. Sutton, B. Haugerud, Y. Lu, W.-M. Kuo, G. Niu, P. Marshall, R. Reed, C. Marshall, J.-S. Rieh, G. Freeman, D. Ahlgren, L. Cohn, K. LaBel, H. Brandhorst, H. Ainspan, J. Lee, S. Nuttnick, H. Kim, C. Palor, S. Clark, D. Emily, B. Randall, K. Jobe, M. Palmer, A. Joseph, D. Harame, D. Herman, B. Meyerson, and the IBM SiGe team for their contributions. This work was supported by DTRA under the Radiation Hardened Microelectronics Program, NASA-GSFC under the Electronics Radiation Characterization Program, IBM, and the Georgia Electronic Design Center at Georgia Tech.

References 1. DC Ahlgren, G Freeman, S Subbanna, R Groves, D Greenberg, J Malinowski, D Nguyen-Ngoc, SJ Jeng, K Stein, K Schonenberg, D Kiesling, B Martin, S Wu, DL Harame, and BS Meyerson. A SiGe HBT BiCMOS technology for mixed-signal RF applications. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1997, pp. 195–198. 2. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, M Gordon, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC compatible CMOS using copper interconnect. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 3. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 4. J-S Rieh, B Jagannathan, H Chen, K Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency near 300 GHz. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 2002, pp. 771–774. 5. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

© 2006 by Taylor & Francis Group, LLC

4.10-522

The Silicon Heterostructure Handbook

6. J Comeau, A Sutton, B Haugerud, JD Cressler, W-ML Kuo, P Marshall, R Reed, A Karroy, and R Van Art. Proton tolerance of advanced SiGe HBTs fabricated on different substrate materials. 2004 IEEE Nuclear and Space Radiation Effects Conference, Atlanta, to be presented July 2004. 7. E Zhao, A Sutton, B Haugerud, JD Cressler, P Marshall, R Reed, B El-Kareh, and S Balster. The effects of radiation on 1/f noise in complementary (npn þ pnp) SiGe HBTs. 2004 IEEE Nuclear and Space Radiation Effects Conference, Atlanta, to be presented July 2004. 8. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Trans. Nuclear Sci. 42:1558– 1566, 1995. 9. J Roldan, WE Ansley, JD Cressler, SD Clark, and D Nguyen-Ngoc. Neutron radiation tolerance of advanced UHV/CVD SiGe HBTs. IEEE Trans. Nuclear Sci. 44:1965–1973, 1997. 10. J Roldan, G Niu, WE Ansley, JD Cressler, and SD Clark. An investigation of the spatial location of proton-induced traps in SiGe HBTs. IEEE Trans. Nuclear Sci. 45:2424–2430, 1998. 11. JD Cressler, M Hamilton, G Mullinax, Y Li, G Niu, C Marshall, P Marshall, H Kim, M Palmer, A Joseph, and G Freeman. The effects of proton irradiation on the lateral and vertical scaling of UHV/CVD SiGe HBT BiCMOS technology. IEEE Trans. Nuclear Sci. 47:2515–2520, 2000. 12. JD Cressler, R Krithivasan, G Zhang, G Niu, P Marshall, H Kim, R Reed, M Palmer, and A Joseph. An investigation of the origins of the variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. IEEE Trans. Nuclear Sci. 49:3203–3207, 2002. 13. Y Lu, JD Cressler, R Krithivasan, Y Li, RA Reed, PW Marshall, C Polar, G Freeman, and D Ahlgren. Proton tolerance of third-generation, 0.12 mm 185 GHz SiGe HBTs. IEEE Trans. Nuclear Sci. 50:1811–1815, 2003. 14. A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. Proton response of 4th-generation 350 GHz UHV/CVD SiGe HBTs. 2004. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. 15. S Zhang, G Niu, SD Clark, JD Cressler, and M Palmer. The effects of proton irradiation on the RF performance of SiGe HBTs. IEEE Trans. Nuclear Sci. 46:1716–1721, 1999. 16. Z Jin, G Niu, JD Cressler, C Marshall, P Marshall, H Kim, R Reed, and D Harame. 1/f noise in proton-irradiated SiGe HBTs. IEEE Trans. Nuclear Sci. 48:2244–2249, 2001. 17. S Zhang, G Niu, JD Cressler, SJ Mathew, SD Clark, P Zampardi, and RL Pierson. A comparison of the effects of gamma irradiation on SiGe HBT and GaAs HBT technologies. IEEE Trans. Nuclear Sci. 47:2521–2527, 2000. 18. RL Pease. Total-dose issues for microelectronics in space systems. IEEE Trans. Nuclear Sci. 43:442–452, 1996. 19. EW Enlow, RL Pease, W Combs, RD Schrimpf, and RN Nowlin. Response of advanced bipolar processes to ionizing radiation. IEEE Trans. Nuclear Sci. 38:1342–1351, 1991. 20. DM Fleetwood, SL Kosier, RN Nowlin, RD Schrimpf, RA Reber Jr, M Delaus, PS Winokur, A Wei, WE Combs, and RL Pease. Physical mechanisms contributing to enhanced bipolar gain degradation at low dose rates. IEEE Trans. Nuclear Sci. 41:1871–1883, 1994. 21. G Banerjee, G Niu, JD Cressler, SD Clark, MJ Palmer, and DC Ahlgren. Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors. IEEE Trans. Nuclear Sci. 46:1620–1626, 1999. 22. JD Cressler, MC Hamilton, R Krithivasan, H Ainspan, R Groves, G Niu, S Zhang, Z Jin, CJ Marshall, PW Marshall, HS Kim, RA Reed, MJ Palmer, AJ Joseph, and DL Harame. Proton radiation response of SiGe HBT analog and RF circuits and passives. IEEE Trans. Nuclear Sci. 48:2238–2243, 2001. 23. S Zhang, JD Cressler, G Niu, C Marshall, P Marshall, H Kim, R Reed, M Palmer, A Joseph, and D Harame. The effects of operating bias conditions on the proton tolerance of SiGe HBTs. SolidState Electron. 47:1729–1734, 2003. 24. P Marshall, MA Carts, A Campbell, D McMorrow, S Buchner, R Stewart, B Randall, B Gilbert, and R Reed. Single event effects in circuit hardened SiGe HBT logic at gigabit per second data rates. IEEE Trans. Nuclear Sci. 47:2669–2674, 2000.

© 2006 by Taylor & Francis Group, LLC

Radiation Effects

4.10-523

25. R Reed, P Marshall, H Ainspan, C Marshall, H Kim, JD Cressler, and G Niu. Single event upset test results on an IBM prescalar fabricated in IBM’s 5HP germanium doped silicon process. Proceedings of the IEEE Nuclear and Space Radiation Effects Conference Data Workshop, Vancouver, 2001, pp. 172–176. 26. RA Reed, PW Marshall, J Pickel, MA Carts, T Irwin, G Niu, JD Cressler, R Krithivasan, K Fritz, P Riggs, J Prairie, B Randall, B Gilbert, G Vizkelethy, P Dodd, and K LaBel. Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20 mm silicon germanium heterojunction bipolar transistors and circuits. IEEE Trans. Nuclear Sci. 50:2184–2190, 2003. 27. G Niu, JD Cressler, M Shoga, K Jobe, P Chu, and DL Harame. Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs. IEEE Trans. Nuclear Sci. 47:2682–2689, 2000. 28. G Niu, R Krithivasan, JD Cressler, P Marshall, C Marshall, R Reed, and D Harame. Modeling of single event effects in circuit-hardened high-speed SiGe HBT logic. IEEE Trans. Nuclear Sci. 48:1849–1854, 2001. 29. G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. 30. R Krithivasan, G Niu, JD Cressler, SM Currie, KE Fritz, RA Reed, PW Marshall, PA Riggs, BA Randall, and B Gilbert. An SEU hardening approach for high-speed SiGe HBT digital logic. IEEE Trans. Nuclear Sci. 50:2126–2134, 2003.

© 2006 by Taylor & Francis Group, LLC

4.11 Reliability Issues 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5

John D. Cressler Georgia Institute of Technology

4.11.6 4.11.7

Introduction........................................................... 4.11-525 Technology-Driven Reliability and Yield Issues............................................................. 4.11-526 Conventional Device Degradation Mechanisms ........................................................... 4.11-527 ‘‘Mixed-Mode’’ Stress Effects................................ 4.11-528 Breakdown Voltage Constraints and Operating Point Instabilities ................................ 4.11-532 Low-Frequency Noise Variations ......................... 4.11-534 Summary ................................................................ 4.11-536

4.11.1 Introduction Clearly, any new integrated circuit technology (SiGe or otherwise) must be proven to be ‘‘reliable.’’ That is, under typical circuit-operating conditions, the circuits, and importantly, the systems constructed from those circuits, must not wear-out or degrade to a level at which they fail ‘‘in the field’’ over the functional life of the system. In integrated circuit circles, reliability of a given technology begins with assurance of the reliability of the underlying building block devices — the transistors certainly, but also the passive elements such as inductors or capacitors, and the interconnects linking the various elements. In this chapter, we will focus only on the reliability of the transistors; in this case SiGe HBTs. From a transistor perspective, one ensures adequate reliability by subjecting the devices to extreme operating conditions for a given length of time, which, for a bipolar technology, historically encompasses two different operational scenarios: (1) hot carrier (hot electron or hot hole or both) stressing associated with reverse-biasing of the emitter–base (EB) junction, and (2) high forward collector current density (JC) stressing. Both reliability ‘‘modes’’ will generally be conducted under ‘‘accelerated’’ conditions (‘‘over stress’’) consisting of higher VEB and JC than the device would normally encounter during ‘‘typical use’’ circuit conditions, and will likely be performed at either elevated (e.g., 1008C for high JC stressing) or reduced (e.g., 408C for reverse EB stressing) temperatures to invoke worst-case stress conditions. One then defines the ‘‘reliability’’ of the transistors in terms of the measured change in a given defined device metric after a given amount of time under stress (e.g., the stress time it takes to produce decrease in current gain of 10%). From this time-dependent stress data, which is by definition limited in scope due to practical testing demands, one then typically projects an extrapolated ‘‘lifetime’’ of the technology (e.g., >10 years), a procedure which clearly invokes a number of assumptions. If the projected lifetime greatly exceeds the intended system life of the part, then all is well. In practice, during technology ‘‘qualification’’ various process splits and fabrication cycle variations are often changed to improve this or that reliability metric as needed, until the checkered flag is finally raised. This is standard practice today for bipolar integrated circuit technologies. Interestingly, these basic bipolar reliability stress methodologies have been in place for well over 25 years in basically an unaltered form. Given the present reality that Si-based bipolar device performance has increased dramatically in recent years (largely due to the addition of Ge bandgap engineering), and classical bipolar circuit 4.11-525 © 2006 by Taylor & Francis Group, LLC

4.11-526

The Silicon Heterostructure Handbook

topologies have changed radically during this period from a high-speed digital ECL centric world to a wide variety of mixed-signal circuit types, it is logical to ask whether such reliability methodologies are in fact capturing all possible reliability degradation modes. As will be argued, they are not. For the purposes of this chapter, then, we define the concept of device ‘‘reliability’’ to be much broader than its standard usage in the industry, to include any possible degradation mechanism for any possible mixedsignal circuit application, in any of the various intended circuit application domains [1]. For instance, in addition to classical device reliability mechanisms associated with reverse EB and forward JC stress, new reliability issues for SiGe HBTs include, for instance, the impact of Ge film stability on technology yield, impact-ionization induced ‘‘mixed-mode’’ stress, concerns associated with scaling-induced breakdown voltage compression and operating point instabilities, and geometrical scaling-induced low-frequency noise variations. The impact of ionizing radiation on device and circuit reliability is also important in this context, but is discussed in Chapter 4.10.

4.11.2

Technology-Driven Reliability and Yield Issues

It is obviously key to the viability of SiGe HBT technology that it has a clearly demonstrated reliability and yield that are comparable to or better than existing Si BJT technology. That is, any reliability or yield loss due to the incorporation of strained SiGe films are potential technology ‘‘showstoppers.’’ Although published data on commercial SiGe technologies are sparse, there is no evidence to date that the use of thermodynamically stable SiGe films imposes any such reliability risk. Clearly, this is good news. Interestingly, the reverse-bias EB stress response of SiGe HBTs can actually be substantially better than that for aggressively scaled ion-implanted Si BJTs. This is because the very shallow, low-energy base implants needed to realize high-performance implanted Si BJTs inevitably place the peak of the base doping at the metallurgical EB junction, and thus increase the EB electric field. In contrast, for an epitaxial base device (Si or SiGe), the boron can be placed inside the base region as a boron ‘‘box’’ profile, and while the finite thermal cycle spreads the boron during processing, a boron ‘‘retrograde’’ is naturally produced at the EB junction, thereby lowering the EB electric field. Since hot electron injection under reverse-bias EB stress conditions depends exponentially on the EB electric field [2], a transistor with an epitaxial base will have a fundamental and decided advantage over an implanted base device in terms of reliability. Importantly, however, this boron retrograde at the EB junction itself produces a doping-gradient-induced electric field that retards electron transport through the base under forwardbias, degrading fT. In a SiGe HBT, this doping-induced retarding field is more than compensated by the Ge-induced accelerating field, but in an epi-base Si BJT, a performance penalty is inevitable. Thus, compositionally graded SiGe is clearly desirable for epi-base transistor design in Si technology. High yield on large wafers is key to the cost advantage Si enjoys over its III–V competition, and as in reliability, the presence of a strained SiGe layer must not unfavorably impact device and circuit yield. It does not. CMOS yield in a SiGe HBT BiCMOS technology is typically evaluated using a large embedded static random-access-memory (SRAM) yield monitor (e.g., several hundred kbit). If any of the HBT films or residuals are not properly removed, then this will be reflected in the SRAM yield. Yield values can also be easily compared with CMOS-only processes to gauge the robustness of the CMOS section of the BiCMOS process. Typical yield numbers for the 154 k SRAM in first- and second-generation SiGe technology are well above 75% [3]. SiGe HBT yield is typically quantified using large chains of small transistors wired in parallel. A chain yield ‘‘failure’’ is defined as the intersection of emitter-to-collector shorts (pipes), high EB leakage, or high CB leakage (i.e., any of the three occurrences is defined as a ‘‘bad’’ or ‘‘dead’’ device chain). For instance, 4000 0.42 2.3 mm2 SiGe HBTs is used as a yield monitor in a first generation technology, and typically has greater than 85% to 90% yield. Choice of CMOS integration scheme does not appear to affect this result. Interestingly, the primary yield failure mechanism in both the CMOS and SiGe HBTs is the same, and can be traced to the shallow-trench isolation [3]. By assuming an ideal Poisson distribution relating defect density and emitter area, one can infer the net defect density associated

© 2006 by Taylor & Francis Group, LLC

4.11-527

Reliability Issues

with a given SiGe HBT BiCMOS technology, in this case yielding numbers in the range of 100 to 500 defects/cm2. For orientation, a defect density of 426 defects/cm2 would ideally produce a 60% yield on a integrated circuit containing 100,000 0.5 2.5 mm2 SiGe HBTs, ample transistor count (and yield) to satisfy almost any imaginable mixed-signal application using SiGe technology [3]. The above yield considerations are clearly predicated on the use of thermodynamically stable SiGe films in the SiGe HBT BiCMOS technology. While stability considerations in the SiGe material system are not completely settled, and numerous ‘‘open issues’’ remain (see Ref. [4]), there do exist reasonably accurate simple theories for predicting film stability once film Ge content and dimensions are accurately known [5]. While not often openly discussed in the literature, there is a general consensus in industry that using stable SiGe films is a ‘‘good thing’’ from a yield perspective. The precise coupling of stability to local pattern density as well as local (added) strain associated with say the shallow- or deep-trench isolations, remain largely matters for conjecture, and should be quantified with dedicated research.

4.11.3 Conventional Device Degradation Mechanisms

Collector and base currents (A)

As discussed above, reliability stress and ‘‘burn-in’’ of bipolar transistors historically proceed along two different paths [2–9]: (1) reverse emitter–base (EB) stress, which is used to inject hot electrons (or holes) into the EB spacer oxide, thereby introducing generation/recombination (G/R) center traps which lead to excess non-ideal base current (Figure 4.11.1) and hence current gain degradation (Figure 4.11.2) as well as increased low-frequency noise [7]; and (2) high forward-current density stress, which also results in current gain degradation, but is generally attributed to electromigration-induced changes in the emitter contact, resulting in a decrease in collector current with increasing stress time. Accelerated lifetime testing of SiGe HBTs using reverse-bias EB stress is generally conducted under high reverse EB bias (e.g., 3.0 V) at reduced temperatures (e.g., 408C), where carrier velocities are higher due to reduced scattering, whereas high forward-current density stress is conducted under a large JC (e.g., three to four times of the JC at peak fT ¼ 3.0–4.0 mA/mm2 for a first-generation SiGe technology) at elevated temperatures (e.g., 1008C), where electromigration is inherently more severe. Typical reverse-bias EB burn-in data from first-generation SiGe HBTs (Figure 4.11.3) show less than 5% change in the current gain after a 500-hour, 408C reverse-bias EB stress at 2.7 V [3]. Comparison of reverse-bias EB stress data of SiGe HBTs having various Ge profile shapes with a comparably constructed epi-base Si BJT control (Figure 4.11.4) suggests that there is no enhanced reliability risk associated with the SiGe layer itself [9].

10−2 10−4 10−6

t = 0 sec t = 1 sec t = 10 sec t = 100 sec t = 1000 sec AE = 0.5⫻2.5 µm2 3 V stress VCB = 0 V

10−8 10−10 0.2

0.4

0.6 0.8 1.0 Base−emitter voltage (V)

1.2

FIGURE 4.11.1 Gummel characteristics of a first-generation SiGe HBT showing the effects of reverse-bias emitter– base stress. Time (t) is measured in seconds. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-528

The Silicon Heterostructure Handbook

120

t = 0 sec t = 1 sec t = 10 sec t = 100 sec t = 1000 sec

Current gain

100 80 60 40

AE = 0.5⫻2.5 µm2 3 V stress

20 0

10−12

10−10

10−8 10−6 Collector current (A)

10−4

10−2

FIGURE 4.11.2 Current gain as a function of bias current of a first-generation SiGe HBT showing the effects of reverse-bias emitter–base stress. Time (t) is measured in seconds. (From U Gogineni, JD Cressler, G Niu, and DL Harame. IEEE Trans. Electron Dev. 47:1440–1448, 2000. With permission.)

Change in current gain (%)

0.0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 0.0

Stress time = 500 h Stress temperature = −40⬚C AE = 0.5⫻2.5 µm2 b measured at IE = 100 µA 0.5

1.0 1.5 2.0 Emitter−base reverse bias (V)

2.5

3.0

FIGURE 4.11.3 Current gain degradation due to reverse emitter–base bias stressing of a first-generation SiGe HBT as a function of stress voltage. (From DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. IEEE Trans. Electron Dev. 48:2575–2594, 2001. With permission.)

Typical high forward-current burn-in data from first-generation SiGe HBTs (Figure 4.11.5) show less than 5% change in the current gain after a 500-hour, 1008C forward-current stress at 1.3 mA/mm2 [3]. Using empirically determined acceleration factors, this result is theoretically equivalent to a more-thanacceptable 10% current gain degradation after 100,000 power-on-hours (POH) under ‘‘normal use’’ conditions (1.25 mA/mm2 at 1008C).

4.11.4

‘‘Mixed-Mode’’ Stress Effects

Optimized transistor scaling leading to such rapid advances in SiGe HBT performance inevitably results in increased current density operation (i.e., the JC at which peak fT is achieved), in the presence of increased impact ionization due to the increased collector doping required to suppress both Kirk effect and high-injection heterojunction barrier effects [4].

© 2006 by Taylor & Francis Group, LLC

4.11-529

Reliability Issues

Avg. decrease in current gain (%)

60 Si BJT (8 samples) 8% SiGe HBT (7 samples) 10% SiGe HBT (4 samples) 15% SiGe HBT (3 samples)

50 40 30

AE = 0.5⫻2.5 µm2 3.0 V stress VBE = 0.7 V 300 K

20 10 0 10−7

10−6

10−5 10−4 Stress charge (C)

10−3

10−2

FIGURE 4.11.4 Percent current gain degradation as a function of injected stress charge for a variety of SiGe profiles and a comparably constructed epi-base Si BJT. (From U Gogineni, JD Cressler, G Niu, and DL Harame. IEEE Trans. Electron Dev. 47:1440–1448, 2000. With permission.)

Change in current gain (%)

0.0 Stress current density = 1.3 mA/µm2 Stress temperature = 100⬚C AE = 0.5⫻2.5 µm2 b measured at IE = 100 µA

−1.0 −2.0 −3.0 −4.0 −5.0 −6.0

0

200

400

600 800 Stress time (h)

1000

1200

FIGURE 4.11.5 Current gain degradation due to forward current density stressing of a first-generation SiGe HBT as a function of stress time. (From DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. IEEE Trans. Electron Dev. 48:2575–2594, 2001. With permission.)

A new reliability damage mechanism in SiGe HBTs was recently reported [10, 11], which was termed ‘‘mixed-mode’’ degradation, since it results from the simultaneous application of high JC and high VCB, and which differs fundamentally from conventional bipolar device reliability damage mechanisms associated with either reverse emitter–base stress [2, 9], or high forward current density stress [13, 14]. (We note parenthetically that the 120 GHz, second-generation SiGe HBTs used in this mixed-mode stress study [12] showed negligible (acceptable) degradation for conventional reverse EB and forward JC stressing.) To carefully control the total injected charge during mixed-mode stressing, a robust time-dependent stress methodology was used which operates the transistor in common-base mode under variable forced IE and VCB conditions. The stress times ranged from 1 msec to 1000 sec, with excellent repeatability. Both forward-mode and inverse-mode (emitter and collector swapped) Gummel characteristics were

© 2006 by Taylor & Francis Group, LLC

4.11-530

The Silicon Heterostructure Handbook

measured at specific (adjustable) time intervals, and the base current degradation determined at VBE ¼ 0.5 V (VCB ¼ 0 V). Typical forward-mode and inverse-mode Gummel characteristics as a function of cumulative stress time are shown in Figure 4.11.6 and Figure 4.11.7 for a JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V mixed-mode stress condition. The mixed-mode stressing produces interface traps and subsequent G/R base current leakage at both the emitter–base spacer (forward-mode), and the shallow-trench edge (inverse-mode), consistent with Ref. [10]. The latter effect is new and unexpected compared to conventional reliability stress modes. The specific JE and VCB dependence of the damage process is shown in Figure 4.11.8 and Figure 4.11.9. Damage thresholds can be observed in second-generation SiGe HBTs at about 25 mA/mm2 (3.0 V), and VCB ¼ 1.0 V (35 mA/mm2).

100

IC and IB (A)

10−2 10−4

AE = 0.2⫻4.0 µm2 JE = 40 mA/µm2, VCB = 3 V T = 300 K

Forward-mode

EB spacer

10−6 10−8

n+poly

Base contact p STI

+ −

n

p−SiGe n damage

10−10

Increasing stress time 0, 1, 10, 100, 800 sec

10−12 0.0

0.2

0.4

0.6

0.8

1.0

VBE (V)

FIGURE 4.11.6 Forward-mode Gummel characteristics showing the base current degradation with increasing mixed-mode stress time (JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V). (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

100

IC and IB (A)

10−2 10−4 10−6 10−8 10−10 10−12 0.0

AE = 0.2⫻4.0 µm2 JE = 40 mA/µm2, VCB = 3 V T = 300 K

Base contact p+ STI

n−

EB spacer n+ poly p−SiGe n

Increasing stress time 0, 1, 10, 100, 800 sec

damage

0.2

Inverse-mode

0.4

0.6

0.8

1.0

VBE (V)

FIGURE 4.11.7 Inverse-mode Gummel characteristics showing the base current degradation with increasing mixed-mode stress time (JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V). (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-531

Reliability Issues

We consistently observed random fluctuations in the base current during stress (both within a single device and device-to-device), which we believe are due to simultaneous creation and annealing of stresscreated interface traps. As argued in Ref. [13], base current fluctuations in the 1 to 100 pA range are quite consistent with reported hot-carrier-generated trap capture cross sections of 1013 to 1015 cm2 for Si–SiO2 interface traps. We have performed poststress annealing studies (at 4008C for 30 min in forming gas), which demonstrate that most of the mixed-mode-induced damage can be annealed, consistent with the known behavior of interface traps. To gain deeper insight into the mixed-mode damage physics, the hot-carrier injection current was simulated under mixed-mode conditions (35 mA/mm2, 3.0 V VCB) using fully calibrated (using SIMS, device layout, and dc and ac data), isothermal two-dimensional MEDICI simulations (with the ‘‘gate

IB post-stress/IB prestress

30.0 JE = 20 mA/µm2 JE = 35 mA/µm2 JE = 40 mA/µm2

25.0 20.0 15.0

AE = 0.2⫻4.0 µm2 VCB = 3 V T = 300 K

10.0 5.0 0.0 10−3

10−2

10−1

100 Time (s)

101

102

103

FIGURE 4.11.8 Base current damage ratio versus stress time for different emitter current densities (VCB ¼ 3.0 V). Poststress data are measured at VBE ¼ 0.5 V and VCB ¼ 0.0 V. (From From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

14.0 VCB = 0V VCB = 1V VCB = 3V

IB post-stress/I B prestress

12.0 10.0 8.0 6.0

AE = 0.2⫻4.0 µm2 JE = 35 mA/µm2 T = 300 K

4.0 2.0 0.0 10−3

10−2

10−1

100 Time (s)

101

102

103

FIGURE 4.11.9 Base current damage ratio versus stress time for different collector–base voltages (JE ¼ 35 mA/ mm2). Poststress data are measured at VBE ¼ 0.5 V and VCB ¼ 0.0 V. (From From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-532

The Silicon Heterostructure Handbook

Norm. injection current

1.0 0.8 Hot carrier

0.6 0.4 Hot carrier

0.2 0.0 0

Extrinsic base contact

0.05 0.1

EB Spacer

n+ Emitter p SiGe n Si

p+ Extrinsic Base

0.15 0.2 0.25 0.3

STI

n− Si

0.35 Depth (µm) 0.4

−0.4

Cross-section Cut

−0.3

−0.2

−0.1

0

0.1

Width (µm)

FIGURE 4.11.10 Simulated distribution of the local hot-carrier current (JE ¼ 35 mA/mm2 and VCB ¼ 3.0 V). The peak injection currents are located at the emitter–base spacer and the shallow-trench isolation edge. (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

current analysis’’ module invoked). The local carrier temperatures (electron and hole) were calculated using energy balance. As with the classical ‘‘lucky-electron’’ model [15], the Si–SiO2 interface trap production is correlated with the hot-carrier injection current density [16], and is the product of the local electron current density and the probability that these electrons reach the oxide interface with kinetic energy higher than the interface trap creation activation energy (taken here to be 2.3 eV [16]). Note that the emitter–base spacer (and the shallow-trench isolation edge) are well within a mean-free path length of the (randomly moving) hot carriers generated in the CB junction by impact ionization. Figure 4.11.10 shows the normalized distribution of the simulated local hot-carrier injection current density. For both the emitter–base spacer and shallow-trench damage regions, we find that injection current density is clearly present and dominated by hot electrons (hot holes exist but in smaller numbers), consistent with the data shown in Figure 4.11.6 and Figure 4.11.7. A comparison of these second-generation, 120 GHz SiGe HBT mixed-mode stress results with stress results on more aggressively scaled third-generation 200 GHz SiGe HBTs (peak fT in the 200 GHz devices occurs at a JC of nearly 20 mA/mm2) shows that transistor lateral and vertical scaling appears to improve the mixed-mode damage thresholds at fixed JE and VCB conditions, consistent with observations reported in Refs. [10, 17]. We believe that the observed improvement is likely to be a consequence of the new ‘‘raised extrinsic base’’ structure of the 200 GHz device, which has a reduced level of the impact ionization at the device edge due to its very shallow extrinsic base formation.

4.11.5 Breakdown Voltage Constraints and Operating Point Instabilities Optimized scaling of SiGe HBTs necessarily results in the decrease of maximum operating voltages as the technology evolves. For CMOS technology, the reduction in VDD is driven by hot-carrier reliability constraints. For SiGe HBTs, this voltage reduction has a different physical origin; namely,

© 2006 by Taylor & Francis Group, LLC

4.11-533

Reliability Issues

the increase in impact ionization as the collector doping is increased to support increasingly higher operating current densities. In the case of SiGe HBTs, BVCEO decreases, for instance, from 3.3 to 2.5 to 1.7 V for first-, second-, and third-generation SiGe technology, respectively. Operating voltage compression is rarely a good thing from a circuit design and system performance perspective, except for helping maintain power dissipation as operating frequencies rise. Particularly in high-speed analog and RFIC design, and even in cascoded digital circuits, all application arenas for which bipolar technology is more naturally suited than CMOS, voltage compression can present serious problems for maintaining adequate signal-to-noise ratio, voltage headroom for transistor ‘‘stacking,’’ and loss of efficiency. This voltage compression issue in SiGe HBTs is far more interesting in many ways than it is for CMOS, since the actual maximum operating voltages that the transistor can sustain depends very strongly on how the transistor is driven (i.e., its local circuit environment), and the static as well as dynamic bias currents which it sees as it is operated. This makes for a seriously complicated situation, particularly with regard to predictive modeling and robust reliability testing. The ubiquitous BVCEO of SiGe HBT technologies, for instance, represents the worst-case bias configuration, since it electrically opens the base, thereby providing a (bad) positive feedback path for the impact ionization induced currents originating in the CB junction, leading to premature breakdown. Even in such cases, however, BVCEO is of questionable relevance to real mixed-signal circuit design since all circuits will present a dynamically varying finite impedance between the base and emitter terminals (i.e., if the base is truly open the circuit cannot do very much!). Thus, the maximum sustainable operating voltage on a SiGe HBT generally lies between that of BVCEO (worst case) and the open-emitter collector–base breakdown voltage BVCBO (best case). For instance, in a first-generation SiGe HBT, BVCEO might be 3.3 V, while BVCBO might be 10 V, three times higher. Figure 4.11.11 shows the measured maximum sustainable collector-to-emitter voltage as a function of operating current density for different input bias configurations for a second-generation SiGe HBT with a 2.2 V BVCEO and 7.5 V BVCBO. Observe the substantial (worrisome) structure in these curves. This should give any reliability engineer food for thought; since in principle the operational bias configuration of the transistor is application driven, and can even vary by

Collector current density (mA/µm2)

7.0

SiGe HBT: 120 GHz peak f T AE = 0.2⫻4.0 µm2

6.0 5.0 4.0

common-emitter: forced IB

3.0

common-emitter: forced VBE

2.0

common-base: forced IE 1.0 0.0 0

2

4 6 8 Collector−emitter voltage (V)

10

12

FIGURE 4.11.11 Collector current density as a function of applied collector to emitter voltage for three different transistor drive conditions. The data are for a second-generation 120 GHz peak fT SiGe HBT. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-534

The Silicon Heterostructure Handbook

10.0 A E = 0.2⫻4.0 µm2 Common-base: forced IE Collector current (mA)

8.0

VBIC model measurement

6.0

4.0

2.0 SiGe HBT: 120 GHz peak fT 0.0 −1

0

1

2 3 4 5 Collector−base voltage (V)

6

7

FIGURE 4.11.12 Common-base output characteristics for forced emitter-current drive showing bias induced instabilities, and a comparison with results from a ‘‘calibrated’’ compact model. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

architecture within the same basic application. Said another way, ensuring reliability of the transistor building block is no solid guarantee of overall circuit and system reliability. Perhaps even more troubling is the fact that very complex operating bias point ‘‘instabilities’’ exist in SiGe HBTs (in all bipolar devices, actually) [18, 19]. Such instabilities are generally believed to be triggered by impact ionization, resulting in so-called ‘‘pinch-in’’ current constriction phenomena, but the simple truth is that they are both highly complex in nature and extremely difficult to both predict and test for. The simple and tempting proclamation of ‘‘do not design your circuits to operate the transistors anywhere near such instabilities,’’ may seem like a safe and reasonable approach, but this stance is increasingly problematic given the ever-shrinking voltage supplies of scaled IC technologies, and the ever-increasing need for circuit designers to maximize both performance and efficiency. In addition, even circuits that are well behaved with respect to such instabilities at dc may be inadvertently forced to dynamically switch through such unstable regimes, with unpredictable consequences. This is particularly true for certain of the myriad classes of amplifiers, for instance. Figure 4.11.12 shows a typical result for a second-generation SiGe HBT operating in forced IE mode. At VCE in the range of 3 V, the output characteristics develop a chaotic-like behavior, the potential circuit implications of which will be frightening to most designers. More alarming perhaps, even well-calibrated compact models cannot capture such instabilities in a robust manner, and hence such effects are effectively not modeled in even mature technology design kits. The open questions from a reliability perspective are: (1) how do we meaningfully test our devices for exposure to such instabilities, and (2) can we predict the results of such behavior on our circuits. These questions remain largely unanswered at present.

4.11.6

Low-Frequency Noise Variations

Low-frequency noise (LFN) is up-converted to phase noise (noisy sidebands on the carrier) through the nonlinearities of transistors, producing a fundamental limit on the achievable spectral purity of communications systems. While LFN is not traditionally considered to be a reliability issue, per se, its importance in mixed-signal circuit design makes it worthy of fresh consideration, within both the context of aggressive geometrical scaling, as well as the addition of SiGe to the problem. One of the unique merits of SiGe HBTs is that they can simultaneously provide very small broadband noise and low

© 2006 by Taylor & Francis Group, LLC

4.11-535

Reliability Issues

1/f noise, giving them a decided advantage over scaled CMOS and III–V devices for high-frequency wireless building blocks limited by phase noise (e.g., oscillators and mixers) [20, 21]. SiGe HBTs are in fact capable of extremely impressive levels of LFN, even when they are aggressively scaled in geometry, vertical profile, and thermal budget to improve the broadband performance. For instance, a 1/f noise corner frequency of 220 Hz (IB ¼ 1 mA) was achieved in a 0.12 0.50 mm2 (drawn) third-generation SiGe HBT with a peak fT of greater than 200 GHz and minimum NFmin of less than 0.5 dB at 10 GHz. This combined low-frequency plus broadband noise performance is superior to any semiconductor device technology, even InP pHEMT technology. This impressive performance noted, we must also point out that an unusual statistical variation (in effect, a device-to-device statistical ‘‘scatter’’) in the LFN spectra of small geometry SiGe HBTs has been recently reported [22]. We view such variations to be inherent reliability concerns, with largely unknown circuit implications, and are generally underappreciated in the reliability community. This LFN statistical variation with size has also been observed in MOSFETs, JFETs, and BJTs in small-sized devices [23–25]. Fundamentally, the noise-generating mechanism inside transistors is generally regarded as a superposition of individual trapping or detrapping processes due to the presence of G/R centers in the device. Each G/R center contributes a Lorentzian-type (1/f 2) noise signature, and given a sufficient number of traps (a statistical ensemble), these Lorentzian processes combine to produce the observed 1/f noise behavior. At sufficiently small device size, however, the total number of traps is small enough that non-1/f behavior, and hence large statistical variations, can be easily observed. Figure 4.11.13 compares a typical family of noise spectra measured on a ‘‘small’’ SiGe HBT, with those measured on a ‘‘large’’ SiGe HBT, at fixed base current density (to allow easy comparison). In these SiGe HBTs, the noise magnitude as a function of bias current (at 10 Hz) for the devices exhibiting ‘‘clean’’ 1/f behavior exhibit a classical IB2 plus 1/AE dependence across the useful bias range, independent of the technology generation, consistent with classical number fluctuation theory [26, 27]. The noise variation in these SiGe HBTs can be quantified using a classical standard deviation approach [22]. Cross-generational noise variation data in SiGe HBT technology are shown in Figure 4.11.14 (the effect is negligible in the first-generation 50 GHz SiGe HBTs due to their larger emitter size)

J B = 14.4 µA/µm2

10−16

Dotted lines: individual devices Solid lines: average

SIB (A2/Hz)

10−18 AE = 0.82⫻3.22 = 2.64 µm2 10−20 1/f 10−22 AE = 0.22⫻0.66 = 0.15 µm2 10−24 100

101

102 Frequency (Hz)

103

104

FIGURE 4.11.13 Base current noise spectra for a ‘‘large’’ area SiGe HBT and a ‘‘small’’ area SiGe HBT showing the large statistical variation from sample-to-sample for small geometry transistors. (From J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington, DC, 2003, pp. 12–13.)

© 2006 by Taylor & Francis Group, LLC

4.11-536

The Silicon Heterostructure Handbook

Variation coefficient (δ)

2.5

2.0

200 GHz fT non-ideal IB 210 GHz fT 350 GHz fT

120 GHz fT 90 GHz fT

1.5

1.0

0.5

0 0.03

0.1

1

3

AE (µm2)

FIGURE 4.11.14 Noise variation coefficient versus emitter area for multiple SiGe HBT technology generations. The base bias current is 1.0 mA. (From J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington DC, 2003, pp. 12–13.)

[28]. Interestingly, observe that the noise variation in the 200 GHz SiGe technology generation shows anomalous scaling behavior below about 0.2 to 0.3 mm2 emitter geometry, below which the noise variation rapidly decreases. Such LFN variations in very small geometry SiGe HBTs can be qualitatively explained by calculations based on the superposition of Lorentzian (1/f 2) G/R traps [22, 23]. Both simple calculations and more sophisticated microscopic noise simulations indicate that as the emitter geometry scales, the device-to-device LFN variation becomes larger due to the decreased number of G/R traps participating in the noise process. Conventional reverse-bias EB stressing, as well as exposure to ionizing radiation, can be used to further probe and understand the origins of this unique scalinginduced reliability issue [22, 29].

4.11.7

Summary

In this chapter, I have attempted to give a new (and hopefully refreshing) perspective on the reliability issues and concerns associated with emerging SiGe HBT technologies, particularly as they are increasingly used in a wide variety of mixed-signal circuit applications. As any honest reliability engineer will admit, the scariest scenarios are those reliability failure mechanisms that may loom beyond the horizon and remain unseen at present, even to the trained eye. While I have managed to address in this chapter the conventional reliability failure mechanisms, as well introduce a number of additional nonstandard reliability issues in SiGe HBTs, which are becoming increasingly important in the emerging mixed-signal application domain, it is impossible, by definition, to anticipate them all. Thermal effects, for instance, which are unavoidable in today’s high-performance technologies operating at very high current levels, will eventually come back to plague us in a major way (they already do). Such thermal issues couple in strong ways to virtually all failure mechanisms in devices, and importantly, are both difficult to measure, and even harder to predictively model. Impact ionization induced bias point instabilities are another concern of increasing importance, which demands attention. Operating voltages necessarily compress with scaling for optimal performance, and what effect such instabilities have on circuit and system-level reliability remains unclear, and hence is worthy of increased focus. We will likely soon reach a point in certain mixed-signal circuits when simply avoiding such operational bias regimes will not be a tractable solution. All of this said, I do not view any of the reliability issues addressed here as ‘‘show-stopping’’ in

© 2006 by Taylor & Francis Group, LLC

Reliability Issues

4.11-537

nature, and as with all reliability concerns, they must be understood, quantified, and then carefully but relentlessly ‘‘designed around.’’

Acknowledgments I am grateful to G. Niu, C. Zhu, Q. Liang, R. Al-Huq, J. Johansen, Z. Jin, T. Chen, U. Gogineni, C. Grens, J. Babcock, A. Joseph, D. Harame, G. Freeman, J.-S. Rieh, D. Ahlgren, F. Guarin, J. Dunn, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler. Emerging SiGe HBT reliability issues for mixed-signal circuit applications. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. 2. DD Tang and E Hackbarth. Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design. IEEE Trans. Electron Dev. 35:2101–2107, 1988. 3. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD. Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Trans. Electron Dev. 48:2575–2594, 2001. 4. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 5. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. Solid-State Electron. 44:869–873, 2000. 6. A Neugroschel, CT Sah, and MS Carroll. Current–acceleration for rapid time-to-failure determination of bipolar junction transistors under emitter–base reverse-bias stress. IEEE Trans. Electron Dev. 42:1380–1383, 1995. 7. A Neugroschel and CT Sah. Comparison of time-to-failure of GeSi and Si bipolar transistors. IEEE Electron Dev. Lett. 17:211–213, 1996. 8. JA Babcock, JD Cressler, LS Vempati, AJ Joseph, and DL Harame. Correlation of low-frequency noise and emitter–base reverse-bias stress in epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 357–360. 9. U Gogineni, JD Cressler, G Niu, and DL Harame. Hot electron and hot hole degradation of SiGe heterojunction bipolar transistors. IEEE Trans. Electron Dev. 47:1440–1448, 2000. 10. G Zhang, JD Cressler, G Niu, and A Joseph. A new ‘‘mixed-mode’’ reliability degradation mechanism in advanced Si and SiGe bipolar transistors. IEEE Trans. Electron Dev. 49:2151–2156, 2002. 11. C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. An investigation of the damage mechanisms in impact ionization-induced ‘‘mixed-mode’’ reliability stressing of scaled SiGe HBTs. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. 12. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, M Gordon, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC compatible CMOS using copper interconnect. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 13. RA Wachnik, TJ Bucelot, and GP Li. Degradation of bipolar transistors under high current stress at 300 K. J. Appl. Phys. 63:4734, 1988. 14. MS Carroll, A Neugroschel, and C-T Sah. Degradation of silicon bipolar junction transistors at high forward current density. IEEE Trans. Electron Dev. 44:110, 1997. 15. S Tam, PK Ko, and C Hu. Lucky-electron model of channel hot-electron injection in MOSFET’s. IEEE Trans. Electron Dev. 31:1116, 1984.

© 2006 by Taylor & Francis Group, LLC

4.11-538

The Silicon Heterostructure Handbook

16. D DiMaria and JW Stasiak. Trap creation in silicon dioxide produced by hot electrons. J. Appl. Phys. 65:2342, 1989. 17. Z Yang, F Guarin, E Hostetter, and G Freeman. Avalanche current induced hot carrier degradation in 200 GHz SiGe heterojunction bipolar transistors. Proceedings of the IEEE International Reliability Physics Symposium, 2003, pp. 339–343. 18. M Rickelt, HM Rein, and E Rose. Influence of impact-ionization-induced instabilities on the maximum usable output voltage of silicon bipolar transistors. IEEE Trans. Electron Dev. 48:774– 783, 2001. 19. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. Transistor design and application considerations for >200 GHz SiGe HBTs. IEEE Trans. Electron Dev. 50:645– 655, 2003. 20. LS Vempati, JD Cressler, JA Babcock, RC Jaeger, and DL Harame. Low-frequency noise in UHV/ CVD epitaxial Si and SiGe bipolar transistors. IEEE J. Solid-State Circ. 31:1458–1467, 1996. 21. R Plana, L Escotte, JP Roux, J Graffeuil, A Gruhle, and H Kibbel. 1/f noise in self-aligned Si/SiGe heterojunction bipolar transistors. IEEE Electron Dev. Lett. 16:58–60, 1995. 22. Z Jin, JD Cressler, G Niu, and A Joseph. Impact of geometrical scaling on low-frequency noise in SiGe HBTs. IEEE Trans. Electron Dev. 50:676–682, 2003. 23. M Sanden, O Marinov, and MJ Deen. A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs. IEEE Trans. Electron Dev. 49:514–520, 2002. 24. P Llinares, D Celi, and O Roux-dit-Buisson. Dimension scaling of 1/f noise in the base current of quasi-self-aligned polysilicon emitter bipolar junction transistors. J. Appl. Phys. 82:2671–2675, 1997. 25. MJ Deen, S Rumysantesev, R Bashir, and R Taylor. Measurements and comparison of low frequency noise in npn and pnp polysilicon emitter bipolar transistors. J. Appl. Phys. 84:625–633, 1998. 26. HAW Markus and TGM Kleinpenning. Low-frequency noise in polysilicon emitter bipolar transistors. IEEE Trans. Electron Dev. 42:720–727, 1995. 27. A Mounib, F Balestra, N Mathieu, J Brini, G Ghibaudo, A Chovet, A Chantre, and A Nouailhat. Low-frequency noise sources in polysilicon emitter BJTs: influence of hot-electron-induced degradation and post-stress recovery. IEEE Trans. Electron Dev. 42:1647–1652, 1995. 28. J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. On the scaling limits of low-frequency noise in SiGe HBTs. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington DC, 2003, pp. 12–13. 29. Z Jin, JA Johansen, JD Cressler, RA Reed, PW Marshall, and AJ Joseph. Using proton irradiation to probe the origins of low-frequency noise variations in SiGe HBTs. IEEE Trans. Nuclear Science, 50:1816–1820, 2003.

© 2006 by Taylor & Francis Group, LLC

4.12 Self-Heating and Thermal Effects 4.12.1 4.12.2

Introduction........................................................... 4.12-539 Modeling of Self-Heating ..................................... 4.12-540 Thermal Resistance Rth . Thermal Capacitance Cth . Thermal Impedance Zth

4.12.3

Thermal Resistance Measurement and Trends ..................................................................... 4.12-543 Measurement of Rth . Rth Trend in SiGe HBTs Device Layout for Reduced Rth

4.12.4

Jae-Sung Rieh Korea University

.

Thermal Effects and Device Reliability ............... 4.12-547 Thermal Runaway . Long-Term Reliability

4.12.5

Summary ................................................................ 4.12-549

4.12.1 Introduction Within semiconductor devices under external bias, the carriers experience successive scatterings while traveling under the influence of an electric field. In most scattering events, they give up kinetic or potential energy they retained, which is converted into various other forms of energy as a result of generating phonons, photons, or electron–hole pairs. Among these energy-conversion modes, the generation of phonons, or the increase of lattice vibration level, is the most frequently encountered mode and results in the generation of heat in the devices. The consequent junction temperature rise, or self-heating, significantly influences device behaviors. It modulates the device operation condition since the characteristics of semiconductors are inherently given as a function of temperature. Device reliability is also affected since the raised temperature promotes most of the long-term degradation mechanisms as well as the catastrophic failures of the devices. Therefore, an accurate characterization of self-heating is critical for the precise prediction of device operation and degradation as well as the prevention of device failures. Historically, self-heating has been a concern mainly for high-power devices in which extensive power consumption results in a great heat generation. However, recent aggressive scalings intended for speed enhancement, which usually accompany a considerable increase in operation current level, have made the self-heating in high-speed devices a major concern. Hence, self-heating has become a generic issue for semiconductor systems in general, and their thermal properties need to be properly analyzed along with the electrical properties. This chapter provides an overview of the issues related to self-heating and thermal effects in SiGe HBTs. As SiGe HBTs are nearly identical to conventional Si BJTs from the thermal point of view, except for a fractional amount of Ge included in the base, the analyses and discussions made in this review are for Si BJTs in general. Although SiGe in the base has a poorer thermal conductivity than Si [1], its impact will not be pronounced since the principal heat source in bipolar transistors is the base–collector space–charge region and most of the generated heat is dissipated downward through the substrate. Section 4.12.2 overviews the modeling of self-heating and its impact on device operation, followed by 4.12-539 © 2006 by Taylor & Francis Group, LLC

4.12-540

The Silicon Heterostructure Handbook

Section 4.12.3 in which thermal resistance measurement methods are introduced along with the trend of the thermal resistance for various SiGe HBT dimensions and structures. In Section 4.12.4, selected reliability issues related to self-heating are discussed.

4.12.2

Modeling of Self-Heating

Thermal Resistance Rth The heat conduction in a homogeneous isotropic solid is described by following time-dependent equation [2]: r2 T ¼

rc @T , k @t

(4:12:1)

where T is temperature, r is density, c is specific heat, k is thermal conductivity, and t is time. With appropriate initial and boundary conditions, the temperature is determined as a function of time and position within the conducting media. The thermal resistance Rth is defined as the ratio of the final value of the temperature at a given position ~ r and the dissipated power (Pdiss) from the heat source: r) ¼ Rth (~

T (~ r , t ¼ 1) T (~ r , t ¼ 0) DT (~ r) ¼ : Pdiss Pdiss

(4:12:2)

Although Rth is a function of position in general, Rth of a device conventionally refers to the thermal resistance at the region inside the device with the peak temperature, which is called the junction temperature Tj. Hence, following position-independent formula is widely accepted: Tj ¼ Rth Pdiss þ T0 ,

(4:12:3)

where Rth is the thermal resistance of the given device, and T0 is the temperature in the absence of power dissipation, or the ambient temperature. The simplest practical boundary condition for the heat dissipation in a device fabricated on a semiconductor substrate is a hemisphere with an adiabatic surface just above the heat source. Although the introduction of an image heat source above the surface simplifies such boundary condition [3], there exists no closed-form solution for this apparently simple geometry, implying the level of complexity involved in the proper modeling of Rth in practical devices. Joy and Schlig [3] proposed an approximate expression, based on numerical calculations, to best represent Rth for such boundary condition: Rth ¼

1 pﬃﬃﬃﬃﬃﬃﬃﬃ f (L, W , H, D) 2k LW ’

1 pﬃﬃﬃﬃﬃﬃﬃﬃ , 4k LW

(4:12:4a) (4:12:4b)

where f (L, W, H, D) is a function of the dimensions for the heat source: length (L), width (W), height (H), and the distance from the surface (D). For bipolar transistors, in which most of heat is generated within the base–collector space–charge region, the dimensions of this region suitably serve for the estimation when substituted. Equation (4.12.4a) can be further reduced to Equation (4.12.4b) based on the fact that f (L, W, H, D) typically falls in the proximity of 0.5 for most practical devices [3], which is valid even for the aggressively scaled devices of today. Therefore, Rth of plain bulk devices can be estimated from Equation (4.12.4b) with a reasonable accuracy.

© 2006 by Taylor & Francis Group, LLC

4.12-541

Self-Heating and Thermal Effects

While an ideal homogeneous medium was assumed for the substrate of the device in the analysis above, actual bipolar transistors typically employ oxide-based structures for improved isolation, such as deep trenches or buried oxides with SOI substrates. Since the thermal conductivity of silicon dioxide is only one hundredth of that of silicon (see Table 4.12.1 [1, 4, 5]), such oxide-based isolations severely impede heat dissipation, resulting in Rth significantly greater than predicted by Equation (4.12.4b) [6–11]. Therefore, modified approaches are necessary to accurately model the devices with oxide isolations, which is challenging as the oxide-based structures impose complicated boundary conditions. Despite the difficulty, there have been efforts to tackle the problem, which are briefly reviewed below. Deep trench is the predominant isolation scheme for modern bipolar transistors and the modeling of Rth for deep trench-isolated devices has been a subject of numerous studies. Walkey et al. [7, 12] treated the vertical trench walls as adiabatic boundaries and the trench bottom plane as a boundary with a constant temperature, and then applied the image source method similar to Ref. [3]. Pacelli et al. [10] introduced an additional Rth term to Equation (4.12.4b) to account for the thermal resistance increase that results from the blocking of radial heat propagation by the trench. Rieh et al. [11, 13] treated the trench as a perfect heatinsulator that limits the lateral extent of heat flux, and assumed that the flux below the trench is confined within a cone-shaped boundary [14]. In this work, the thermal resistance of the device was estimated based on the following general expression for Rth, applied to the geometrical heat flux boundary assumed: Rth ¼

ð

1 dz, k(z)A(z)

(4:12:5)

where k and A are the thermal conductivity and the cross section of the heat flux, respectively, both given as a function of z. Equation (4.12.5) implies that the increase in Rth for trench-isolated devices is more pronounced with deeper trenches and narrower trench-enclosed areas. This geometrical approach leads to a simple analytic expression of Rth in terms of the device dimensions, which can be readily implemented into device models. Despite the different approaches, all these thermal models predict a substantial increase in Rth for the deep trench-isolated devices compared to plain bulk devices (50% to 100% for typical trench dimensions), manifesting the adverse effects of the oxide trench isolations on heat dissipation. SOI-based bipolar transistors have gained increasing attention recently [15–17], owing to improved isolation or compatibility with SOI CMOS, or both. From the thermal point of view, however, such structure is detrimental because the buried oxide, often combined with oxide trenches and BEOL dielectric layers, severely impedes the heat dissipation. A few modeling approaches [8, 10] and measurements [6, 17] have been reported regarding the thermal characteristics of bipolar transistors on SOI substrates, consistently showing that SOI devices exhibit Rth values far larger (50% to 300%) than those of bulk devices of a similar dimension. It is noted that the increase of Rth in SOI structures is far more significant when combined with deep trenches, as verified by simulations in Ref. [17].

Thermal Capacitance Cth For steady-state conditions, the thermal resistance Rth alone is sufficient to describe the relationship between temperature and dissipated power. However, when the transient behavior of self-heating is important, the concept of the thermal capacitance Cth needs to be introduced, which will eventually constitute the thermal impedance Zth along with Rth. A general expression for the thermal capacity (heat capacity) in a solid is given by

TABLE 4.12.1

k (W/cm K)

Thermal Conductivity of Selected Semiconductors and Insulators at T ¼ 300 K [1, 4, 5] Si

GaAs

InP

SiC(6H)

GaN

Si0.7Ge0.3

SiO2

Si3N4

Diamond

1.41

0.46

0.68

4.6

1.3

0.08

0.014

0.19

2000

© 2006 by Taylor & Francis Group, LLC

4.12-542

The Silicon Heterostructure Handbook

Cth ¼ rcV ,

(4:12:6)

where V is the volume to be heated. It is assumed in Equation (4.12.6) that the temperature is uniform throughout the volume V. For practical device structures, however, thermal gradients always exist inside the device, and the volume V is not clearly defined since the substrate around the device is partially heated as well. Hence, Equation (4.12.6) is seldom employed to model the thermal capacitance for practical purposes. Instead, Cth is usually estimated from the measured time-dependent response of the junction temperature to the power dissipation, typically applied as a step function [18–20]. Together with Rth values, which can be readily measured as described in the next section, Cth is obtained from the estimated time delay t ¼ RthCth of the transient response. Reported values of t for typical bipolar transistors range from 50 ns to 1 ms [3, 20]. It is noted that this is the time delay associated with the local heating of an individual device. Another time delay related to the global heating of a chip, which arises from the averaged heat dissipation of all the devices embedded in the chip, is much larger and ranges from milliseconds to minutes depending on the packaging and air flow design around the package [21]. It is the global heating that causes the overall chip temperature rise, which typically ranges around 80 to 1208C. The local heating is superimposed onto the global heating, causing the junction temperature to rise above the chip temperature. The thermal modeling of individual devices generally pertains to the local heating and the chip temperature is considered as a fixed ambient temperature.

Thermal Impedance Zth The thermal impedance Zth is a generalized form of Rth to include the time dependence of the junction temperature rise. With a simple electrical circuit analogy, Zth can be represented as a parallel combination of Rth and Cth, with the dissipated power Pdiss replacing the current I as shown in Figure 4.12.1(a). Then the frequency domain expression of thermal impedance Zth(s) is given by

Zth Pdiss

Rth

Cth Zth =

Rth 1+sRthCth

(a)

Pdiss

Cth,1

Cth,2

Rth,1

Rth,2

Zth,1

Cth,n

Rth,n

Zth,2

Zth,n n

Zth =

Σ

i=1

Zth,i

(b)

FIGURE 4.12.1

Circuit analogy of thermal analysis: (a) monopole representation and (b) multipole representation.

© 2006 by Taylor & Francis Group, LLC

4.12-543

Self-Heating and Thermal Effects

Zth (s) ¼

1 þ sCth Rth

1 ¼

Rth : 1 þ sRth Cth

(4:12:7)

The corresponding time domain expression of thermal impedance Zth(t), assuming Pdiss is applied as a unit step function, can be obtained by taking the inverse Laplace transform of Equation (4.12.7) multiplied by 1/s : Zth (t) ¼ Rth 1 exp

t Rth Cth

:

(4:12:8)

This is a monopole approach with a single time constant (t ¼ RthCth), which is widely adopted by most bipolar models, including VBIC, largely owing to its simplicity. When a higher level of accuracy is required, multipole approaches with more than one time constant can be employed. The circuit representation for the multipole approximation is shown in Figure 4.12.1(b) and the corresponding Zth is given by Zth (t) ¼

X i

Rth,i 1 exp

t Rth,i Cth,i

:

(4:12:9)

It was shown that even two-pole approximations provide a significantly improved level of accuracy, in terms of match to measurement, compared to monopole approaches [8, 20]. For bipolar transistors, the dissipated power is given by Pdiss ¼ IBVBE þ ICVCE and the final junction temperature Tj is expressed in terms of Zth as Tj ¼ Zth (IB VBE þ IC VCE ) þ Tamb :

(4:12:10)

An accurate prediction of transistor operation in the presence of self-heating is then obtained by simultaneously solving Equation (4.12.10) and relevant electrical equations in which Tj is substituted for the temperature in electrical parameter expressions. Electrothermally self-consistent circuit simulators can thus be developed based on such relationship linking electrical and thermal properties of bipolar transistors [21–25].

4.12.3 Thermal Resistance Measurement and Trends Measurement of Rth The thermal resistance of a device can be extracted from the relation between the power dissipation and the junction temperature. Such relation is usually obtained by exploiting the temperature dependence of an electrical parameter of the device, in which the electrical parameter is measured for various power dissipation levels and then translated into temperature variations by a careful calibration. The most widely used such temperature-sensitive electrical parameters (TSEPs) for Rth extraction in bipolar transistors are the base–emitter voltage VBE [13, 26–30] and current gain b [30–32]. The temperature dependence of current levels can also be utilized for the extraction [33–35]. Here, an approach utilizing VBE as a TSEP is briefly introduced following the description in Ref. [13]. As a first step, the device is biased with a fixed emitter current IE and collector–base voltage VCB, and then VBE is measured for substrate temperature TS which is swept for the range of interest. The resultant VBE TS correlation, such as shown in Figure 4.12.2(a), is called the calibration curve. As a second step, the device is biased with the same IE as used in step 1 at a fixed substrate temperature (denoted as ambient temperature Tamb), and VBE is measured for different dissipated power (Pdiss ¼ ICVCE þ IBVBE) with varying VCB (Figure 4.12.2(b)). A moderate VCB range is suggested to avoid avalanche effects.

© 2006 by Taylor & Francis Group, LLC

4.12-544

The Silicon Heterostructure Handbook

1040

(a)

1000 980

360

960

350

940

IC,VCB fixed

920 280

300

320

340

360

Substrate temperature (K)

1020

330 320

298K-To

310 300

Before compensation

290 280

(b)

(c)

270

1010 VEB (mV)

After compensation

340 Temperature (K)

VEB (mV)

1020

To = 274 K

260 0

1000 990

10

20 30 40 Dissipated power (mW)

50

IC fixed

980 10

20 30 Dissipated power (mW)

40

FIGURE 4.12.2 The extraction procedure for Rth: (a) step 1: IE and VCB is fixed, and VBE is measured for various substrate temperature TS. (b) Step 2: IE is fixed and VBE is measured for a range of Pdiss with varying VCB. (c) Step 3: Pdiss–Tj relation is obtained by eliminating VBE from step 1 and step 2, and compensation is made to account for selfheating in step 1. The slope of the curve is Rth.

Now, by eliminating VBE from the two measurements obtained from step 1 and step 2, the relationship between temperature and power is obtained (as shown in Figure 4.12.2(c)). As a final step, a compensation is made in order to account for the self-heating in step 1, since it related VBE to the substrate temperature TS, not to the junction temperature Tj. This can be done by taking the y-axis intercept point of the obtained temperature–power relation, denoted by To in Figure 4.12.2(c), and shifting the entire curve upward by the difference between the ambient temperature Tamb and To [31]. This final curve presents the junction temperature as a function of power dissipation, and Rth can be extracted from its slope. If the self-heating in step 1 is significant enough to cause a considerable power dissipation variation due to the small VBE change over the TS variation (note that any increase in TS would slightly reduce VBE, resulting in a finite increase in the total power dissipation, which was assumed negligible above), an additional compensation is needed which involves a correction in the slope of the temperature–power curve [29].

Rth Trend in SiGe HBTs Several studies have been published which report the measured thermal resistance of SiGe HBTs [11, 13, 17, 28, 29, 34]. Here, results [11] obtained from the IBM’s deep trench-isolated 200 GHz SiGe HBTs [36] are introduced as an example, which were extracted based on the method described above. Figure 4.12.3 shows the measured Rth for different emitter lengths and a fixed emitter width of 0.12 mm. Also included as a solid line is a prediction from the analytical model in Ref. [13], in which the heat dissipation through the metal lines is treated as a fitting parameter. As is clear from Figure 4.12.3, shorter devices

© 2006 by Taylor & Francis Group, LLC

4.12-545

Self-Heating and Thermal Effects

20,000

Rth (K/W)

15,000 0

10,000

5000

0 0

2

4 6 8 Emitter length (µm)

10

12

FIGURE 4.12.3 Thermal resistance of deep trench-isolated SiGe HBTs with various emitter lengths [11]. Measurement (symbols) is compared with model prediction (solid line) where the heat dissipation through metal line is treated as a fitting parameter.

(with a smaller emitter length) exhibit larger Rth due to a smaller cross-sectional area enclosed by the deep trench, which effectively pinches the heat flux toward substrate. However, the deep trench-enclosed area per emitter area is larger for shorter devices, which results in a smaller junction temperature rise for shorter devices when a fixed power density is assumed over the various emitter lengths (Figure 4.12.4). An opposite trend is exhibited by the junction temperature rise for a fixed power, which closely follows the trend of thermal resistance (recall DTj ¼ PdissRth). However, the fixed power density assumption is more realistic since it is a similar current density, rather than current, that is shared for devices with different sizes. This indicates that shorter devices, despite their larger thermal resistances, tend to cause less self-heating effects and are favored from the thermal standpoint. A similar trend is observed for the variation of Rth with emitter width. With emitter length fixed, narrower devices exhibit smaller junction temperature rise for a fixed power density, despite the increasing trend of Rth with decreasing emitter width [13].

Device Layout for Reduced Rth Due to the considerable self-heating effects, the layout of today’s scaled high-speed devices needs to be optimized for both thermal and electrical performance. This section provides a couple of examples for such considerations. As the deep trenches significantly suppress the heat dissipation, Rth is expected to decrease with increasing deep trench-enclosed area. In order to verify such tendency experimentally, Rth was measured and compared for SiGe HBTs with various deep trench-enclosed areas, which was achieved by adjusting the distance from emitter finger to trench [11]. As shown schematically in the inset of Figure 4.12.5, the device used in the experiment has an emitter finger located off the center of the deep trench-enclosed area to allow for the collector contact, and two parameters are defined for the finger-to-trench distance: S1 (shorter distance) and S2 (longer distance). Rth was measured for various S1/S2 ratios for which S2 is fixed. Figure 4.12.5 clearly depicts a decreasing trend of Rth with increasing S1: 17% reduction when S1/S2 ratio is increased from 0.23 to 1. Also compared is a device without deep trench, which exhibits a 32% reduction in Rth by eliminating the trench. Another approach to improve the thermal resistance is to partition the emitter finger into segments, which effectively increases the cross section of the heat flux beneath the emitter fingers. To verify the effect, devices with segmented emitter fingers with various spacings between the segments and different

© 2006 by Taylor & Francis Group, LLC

4.12-546

The Silicon Heterostructure Handbook

18

Junction temp rise ∆Tj (K)

16 14 12 10 8 6 4 2 0

0

2

4 6 8 Emitter length (µm)

10

12

FIGURE 4.12.4 Junction temperature rise of deep trench-isolated SiGe HBTs with various emitter lengths [11]. Two difference conditions are assumed: fixed power (open symbols) and fixed power density (solid symbols).

4000

Rth (K/W)

3500

3000

2500 S1

2000

S1

Emitter finger

S2

Deep trench

1500 S1/S2 = 0.23

S1/S2 = 0.61

S1/S2 = 1.0

No DT

Structure

FIGURE 4.12.5 Schematic layout of a device showing the two distance parameters S1 and S2 (inset), and measured Rth with various S1/S2 ratios for which S1 is fixed. Also shown is the Rth for the device without deep trench. The error bars indicate minimum and maximum of the data acquired across the wafer.

numbers of the segments were fabricated [11]. First, the emitter finger was divided into two, three, and four segments with fixed total spacing and total emitter length, for which the deep trench-enclosed area remained unchanged. Then, for the same set of device structures, the total spacing was varied from 0 to 3 mm. Figure 4.12.6 shows that Rth decreases with increasing total spacing, which is a combined effect of increased deep trench-enclosed area and segmented emitter finger. More interestingly, when the total spacing is fixed, the devices with a larger number of segments (with smaller individual segment length) exhibit smaller Rth, an effect solely due to the segmented emitter finger (the deep trench-isolated area is fixed and its effect is isolated). Such reduction in Rth can be ascribed to the fact that the heat source is more evenly spread with more segments, although the total heat source area and deep trench-enclosed area are fixed.

© 2006 by Taylor & Francis Group, LLC

4.12-547

Self-Heating and Thermal Effects

3600 3400

Rth (K/W)

3200 3000 2800 2600 Spacing

Emitter segment

2400 Deep trench

2200 −1

0

1

2

3

4

Total spacing (µm)

FIGURE 4.12.6 Schematic layout of a device with segmented emitter finger (inset), and measured Rth for various total spacings and number of segments: two (solid circles), three (open squares), and four segments (solid triangles). Solid lines are model prediction, and the error bars indicate minimum and maximum of the data acquired across the wafer.

4.12.4 Thermal Effects and Device Reliability Thermal Runaway Thermal runaway is a phenomenon caused by the electrothermal positive feedback widely observed in bipolar transistors with an excessive junction temperature rise. The origin of the thermal runaway (or thermal instability) is closely related to the positive temperature dependence of collector current IC, which increases with increasing temperature for a fixed VBE. Consider a typical IC–VBE relation of a bipolar transistor in the presence of strong self-heating (as shown in Figure 4.12.7 [37]), and assume the device is biased near a critical regression point on the curves. Now, if VBE is forced to increase by a small amount of DVBE, then an increase in IC will follow, leading to an increase in power dissipation and thus temperature. The raised temperature, due to the positive temperature dependence of IC, will further increase IC, which results in yet another temperature rise. This mutual interaction would build up a positive feedback between temperature and IC, which may eventually lead to an instantaneous burn-out of the device. Since ambient electrical noise may cause fluctuations on VBE large enough to trigger the thermal runaway when a device is biased near the critical point, it is strongly suggested to keep devices away from such bias point with an enough margin. Such instability can be triggered by a perturbation in the spatial distribution of the current over the device also. If a certain location over a device develops a current density higher than surrounding area, the region will be selectively heated up and the local temperature will rise sharply, creating a ‘‘hot spot.’’ Then, this spot would further attract current from neighboring regions due to the aforementioned positive temperature dependence of IC, triggering a positive feedback similar to the one described above. In fact, this is a more commonly observed triggering mode of thermal runaway in practical devices. The thermal instability is also generally believed to be a direct cause of the second breakdown [38–40] (especially for forward mode second breakdown [41, 42]), in which an abrupt VCE reduction is observed with IC raised beyond a critical point. When the thermal instability results in an excessive level of local temperature rise in a device, an intrinsic zone may develop at the hot spot (which happens at Tj 0 1300 K) [43]. At this intrinsic zone, the carrier concentration is now determined by the intrinsic carrier

© 2006 by Taylor & Francis Group, LLC

4.12-548

The Silicon Heterostructure Handbook

10

Emitter current (mA)

VCB = 8.0 V

1

VCB = 10.0 V AE = 0.5⫻2.5 µm2 VCB in steps of 0.5 V VBE, breakover

0.1 0.75

0.8

0.85

0.9

0.95

Base emitter voltage (V)

FIGURE 4.12.7 Typical IC–VBE curves in the presence of a strong self-heating, obtained from IBM’s 50 GHz SiGe HBT [37]. (Copyright 2000 IEEE.)

concentration at the given temperature rather than the doping concentration. As the intrinsic carrier concentrations at such high temperatures are much larger than typically available doping concentrations, a highly conductive local region is created in the device, triggering an abrupt reduction in the voltages across junctions, notably VCE of bipolar transistors. This phenomenon is generally called the second breakdown. As a greater temperature increase is expected with a larger power dissipation, thermal runaway is in general more likely to take place with higher VCB and IC, and a safe operation boundary needs to be accordingly defined. As the junction temperature decreases with decreasing Rth for a given power dissipation, a reduction in Rth, either by structural modification or employing a heat sink, is favored to relax the safe operation boundary and lower the chance for thermal runaway. Alternatively, an emitter ballasting resistor can be employed [44], which is probably the most practical and widely accepted approach to suppress thermal runaway. With an extra resistance component inserted in series with the emitter, any increase in IC will cause a voltage drop across the inserted emitter resistance, leading to a reduction in the intrinsic VBE. The reduced intrinsic VBE will suppress any further increase of IC, thus providing a negative feedback that counterbalances the electrothermal positive feedback.

Long-Term Reliability Most of the device degradation mechanisms are accelerated with temperature, and self-heating imposes negative impacts on the long-term reliability of devices. In general, accelerated degradations with temperature follow an Arrhenius relation, and the mean time to failure (MTTF) can be estimated in terms of activation energy E0 and junction temperature Tj as following: MTTF ¼ C exp

E0 kTj

¼ C exp

E0 , k(Tj0 þ DTj )

(4:12:11)

where Tj0 is the junction temperature without self-heating, DTj is the junction temperature rise due to self-heating, k is the Boltzmann constant, and C is a coefficient. It is clear from Equation (4.12.11) that any junction temperature rise will lead to a reduction in MTTF. Such effects are illustrated in Figure 4.12.8 in which the normalized MTTF is plotted as a function of DTj up to 200 K, for various E0 values within the practical range. The chip temperature was fixed at 1008C (373 K), a typical value for commercial chips, and C is assumed constant implying MTTF is dominated by temperature. The plot

© 2006 by Taylor & Francis Group, LLC

4.12-549

Self-Heating and Thermal Effects

1⫻101

MTTF normalized

1⫻100 E0 = 0.5 eV

1⫻10−1 1⫻10−2

E0 = 1 eV

1⫻10−3

E0 = 1.5 eV

1⫻10−4 Tamb = 373 K

1⫻10−5

E0 = 2 eV

1⫻10−6 0

20 40 60 80 Junction temperature rise ∆Tj (K)

100

FIGURE 4.12.8 Calculated MTTF plotted as a function of junction temperature rise DTj based on Equation (4.12.11), with various activation energies in the practical range.

shows a rapid reduction in MTTF with increasing Tj, which is more pronounced with larger activation energies. According to the plot, DTj of a few tens of kelvins, which is realistic for modern high-speed SiGe HBT operation, may lead to a reduction in MTTF by multiple orders of magnitude depending on the activation energy. It is obvious from this simple calculation that self-heating has a significant impact on the long-term device degradation and any effort for Rth reduction will lead to a substantial improvement in the device lifetime.

4.12.5 Summary In this chapter, the general issues regarding the self-heating and thermal effects in Si-based bipolar transistors, particularly for SiGe HBTs, were reviewed, which covered the modeling of self-heating, the measurement of the thermal resistance, the trend of Rth for various device structures, and the effect of self-heating on device reliability. As stressed in this chapter, the proper consideration and analysis of the self-heating effects are critical for an accurate prediction of device operation and understanding of device reliability. Although extensive knowledge on this field has been accumulated owing to decadeslong efforts, there still exist unexplored territories to be investigated for better understanding and control of the thermal effects.

Acknowledgments The author would like to thank Andreas Stricker, Ping-Chuan Wang, and Kim Watson for helpful discussions and is also grateful to Thomas Adam and Greg Freeman for the careful review of the manuscript.

References 1. KL Wang and X Zheng. Thermal properties of SiGe. In Properties of Strained and Relaxed Silicon Germanium, E. Kasper, Ed. London: INSPEC, 1995. 2. HS Carslaw and JC Jaeger. Conduction of Heat in Solids, 2nd ed. Oxford: Oxford University Press, 1959. 3. R Joy and E Schlig. Thermal properties of very fast transistors. IEEE Transactions on Electron Devices 17:586–594, 1970.

© 2006 by Taylor & Francis Group, LLC

4.12-550

The Silicon Heterostructure Handbook

4. R Muller and T Kamins. Device Electronics for Integrated Circuits, 2nd ed. New York: John Wiley & Sons, 1986. 5. O Madelung. Semiconductors: Group IV Elements and III–V Compounds. Berlin: Springer-Verlag, 1991. 6. PR Ganci, J-JJ Hajjar, T Clark, P Humphries, J Lapham, and D Buss. Self-heating in high performance bipolar transistors fabricated on SOI substrates. Technical Digest of Electron Devices Meeting, 1992, pp. 417–420. 7. D Walkey, T Smy, H Tran, D Marchesan, and M Schro¨ter. Prediction of thermal resistance in trench isolated bipolar device structures. Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, 1998, pp. 207–210. 8. JS Brodsky, RM Fox, and DT Zweidinger. A physics-based dynamic thermal impedance model for vertical bipolar transistors on SOI substrates. IEEE Transactions on Electron Devices 46:2333–2339, 1999. 9. P Palestri, A Pacelli, and M Mastrapasqua. Thermal resistance in Si1–xGex HBTs on bulk-Si and SOI substrates. Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, 2001, pp. 98–101. 10. A Pacelli, P Palestri, and M Mastrapasqua. Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates. IEEE Transactions on Electron Devices 49:1027–1033, 2002. 11. J-S Rieh, J Johnson, S Furkay, D Greenberg, G Freeman, and S Subbanna. Structural dependence of the thermal resistance of trench-isolated bipolar transistors. Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, 2002, pp. 100–103. 12. D Walkey, T Smy, C Reimer, M Schro¨ter, H Tran, and D Marchesan. Modeling thermal resistance in trench-isolated bipolar technologies including trench heat flow. Solid-State Electronics 46:7–17, 2002. 13. J-S Rieh, D Greenberg, B Jagannathan, G Freeman, and S Subbanna. Measurement and modeling of thermal resistance of high speed SiGe heterojunction bipolar transistors. Proceedings of Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2001, pp. 110–113. 14. D Kennedy. Spreading resistance in cylindrical semiconductor devices. Journal of Applied Physics 31:1490–1497, 1960. 15. K Washio, E Ohue, H Shimamoto, K Oda, R Hayami, Y Kiyota, M Tanabe, M Kondo, T Hashimoto, and T Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. Technical Digest of International Electron Devices Meeting, 2000, pp. 741–744. 16. J Cai, A Ajmera, C Ouyang, P Oldiges, M Steigerwalt, K Stein, K Jenkins, G Shahidi, and T Ning. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI. Digest of Symposium on VLSI Technology, 2002, pp. 172–173. 17. M Mastrapasqua, P Palestri, A Pacelli, GK Celler, MR Frei, PR Smith, RW Johnson, L Bizzarro, W Lin, TG Ivanov, MS Carroll, IC Kizilyalli, and CA King. Minimizing thermal resistance and collector-tosubstrate capacitance in SiGe BiCMOS on SOI. IEEE Electron Device Letters 23:145–147, 2002. 18. RT Dennison and KM Walter. Local thermal effects in high performance bipolar devices/circuits. Proceedings of Bipolar Circuits and Technology Meeting, 1989, pp. 164–167. 19. DT Zweidinger, RM Fox, JS Brodsky, T Jung, and S-G Lee. Thermal impedance extraction for bipolar transistors. IEEE Transactions on Electron Devices 43:342–346, 1996. 20. DJ Walkey, TJ Smy, D Marchesan, H Tran, C Reimer, TC Kleckner, MK Jackson, M Schroter, and JR Long. Extraction and modelling of thermal behavior in trench isolated bipolar structures. Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, 1999, pp. 97–100. 21. RM Fox, S-G Lee, and DT Zweidinger. The effects of BJT self-heating on circuit behavior. IEEE Journal of Solid-State Circuits 28:678–685, 1993. 22. RM Fox and S-G Lee. Scalable small-signal model for BJT self-heating. IEEE Electron Device Letters 12:649–651, 1991. 23. DT Zweidinger, S-G Lee, and RM Fox. Compact modeling of BJT self-heating in SPICE. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12:1368–1375, 1993.

© 2006 by Taylor & Francis Group, LLC

Self-Heating and Thermal Effects

4.12-551

24. CC McAndrew. A complete and consistent electrical/thermal HBT model. Proceedings of Bipolar/ BiCMOS Circuits and Technology Meeting, 1992, pp. 200–203. 25. RS Vogelsong and C Brzezinski. Extending SPICE for electro-thermal simulation. Proceedings of Custom Integrated Circuits Conference, 1989, pp. 21.4/1–21.4/4. 26. MG Adlerstein and MP Zaitlin. Thermal resistance measurements for AlGaAs/GaAs heterojunction bipolar transistors. IEEE Transactions on Electron Devices 38:1553–1554, 1991. 27. BM Cain, PA Goud, and CG Englefield. Electrical measurement of the junction temperature of an RF power transistor. IEEE Transactions on Instrumentation and Measurement 41:663–665, 1992. 28. M Pfost, V Kubrak, and P Brenner. A practical method to extract the thermal resistance for heterojunction bipolar transistors. Conference on European Solid-State Device Research, 2003, pp. 335–338. 29. T Vanhoucke, HMJ Boots, and WD van Noort. Revised method for extraction of the thermal resistance applied to bulk and SOI SiGe HBTs. IEEE Electron Device Letters 25:150–152, 2004. 30. DE Dawson, AK Gupta, and ML Salib. CW measurement of HBT thermal resistance. IEEE Transactions on Electron Devices 39:2235–2239, 1992. 31. JR Waldrop, KC Wang, and PM Asbeck. Determination of junction temperature in AlGaAs/GaAs heterojunction bipolar transistors by electrical measurement. IEEE Transactions on Electron Devices 39:1248–1250, 1992. 32. N Bovolon, P Baureis, J-E Muller, P Zwicknagl, R Schultheis, and E Zanoni. A simple method for the thermal resistance measurement of AlGaAs/GaAs heterojunction bipolar transistors. IEEE Transactions on Electron Devices 45:1846–1848, 1998. 33. W Liu and A Yuksel. Measurement of junction temperature of an AlGaAs/GaAs heterojunction bipolar transistor operating at large power densities. IEEE Transactions on Electron Devices 42:358– 360, 1995. 34. H Tran, M Schroter, DJ Walkey, D Marchesan, and TJ Smy. Simultaneous extraction of thermal and emitter series resistances in bipolar transistors. Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, 1997, pp. 170–173. 35. SP Marsh. Direct extraction technique to derive the junction temperature of HBTs under high selfheating bias conditions. IEEE Transactions on Electron Devices 47:288–291, 2000. 36. B Jagannathan, M Khater, F Pagette, J-S Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, SJ Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, and S Subbanna. Self-aligned SiGe NPN transistors with 285 GHz fmax and 207 GHz fT in a manufacturable technology. IEEE Electron Device Letters 23:258–260, 2002. 37. J Dunn, D Harame, SS Onge, A Joseph, N Feilchenfeld, K Watson, S Subbanna, G Freeman, S Voldman, D Ahlgren, and R Johnson. Trends in silicon germanium BiCMOS integration and reliability. Proceedings of International Reliability Physics Symposium, 2000, pp. 237–242. 38. CG Thornton and CD Simmons. A new high current mode of transistor operation. IRE Transactions on Electron Devices 5:6–10, 1958. 39. HA Schafft and JC French. A survey of second breakdown. IEEE Transactions on Electron Devices 13:613–618, 1966. 40. HA Schafft. Second breakdown — a comprehensive review. Proceedings of the IEEE 55:1272–1288, 1967. 41. PL Hower and VGK Reddi. Avalanche injection and second breakdown in transistors. IEEE Transactions on Electron Devices 17:320–335, 1970. 42. M Jovanovic. A transistor model for numerical computation of forward-bias second-breakdown boundary. IEEE Transactions on Power Electronics 6:199–207, 1991. 43. F Bergmann and D Gerstner. Some new aspects of thermal instability of the current distribution in power transistors. IEEE Transactions on Electron Devices 13:630–634, 1966. 44. G-B Gao, MS Unlu, H Morkoc, and DL Blackburn. Emitter ballasting resistor design for, and current handling capability of AlGaAs/GaAs power heterojunction bipolar transistors. IEEE Transactions on Electron Devices 38:185–196, 1991.

© 2006 by Taylor & Francis Group, LLC

4.13 Device-Level Simulation 4.13.1 4.13.2 4.13.3

Introduction........................................................... 4.13-553 Semiconductor Equations..................................... 4.13-553 Physical Model Selection ...................................... 4.13-554 NC , NV, and Eg . Mobility and Velocity Saturation . Incomplete Ionization . BGN, Statistics, and Mobility

4.13.4

Application Issues.................................................. 4.13-557 Device Structure Specification . Meshing Guidelines . Mesh Quality Assurance . I–V Simulation . High-Frequency Simulation . Qualitative versus Quantitative Simulations

4.13.5

Guofu Niu Auburn University

Probing Internal Device Operation ..................... 4.13-563 Regional Analysis of Transit Time . High-Injection Barrier Effect

4.13.6

Summary ................................................................ 4.13-568

4.13.1 Introduction Device simulation is now an integral part of SiGe technology development, and is routinely used for understanding SiGe HBT operation and device optimization. All the major commercial device simulators support SiGe devices, including MEDICI from Avant (now Synopsys), DESSIS from ISE, and ATLAS from Silvaco. They are typically part of a technology computer-aided-design (TCAD) package, which includes process simulation, device simulation, and parameter extraction programs. Fortunately or unfortunately, these device simulators were historically developed as general semiconductor equation solvers, and the user must choose his or her model of physics, such as mobility, carrier statistics (Fermi–Dirac or Boltzmann), bandgap narrowing (BGN), that best suit the device in question. The default physical models are usually the simplest ones, and often give inaccurate results, particularly for advanced device technologies such as SiGe. Users are also responsible for the ‘‘meshing’’ of the device structure, which can affect the simulation results significantly. This chapter addresses these practical issues of device-level simulation for SiGe HBTs, and presents techniques of simulation results analysis.

4.13.2 Semiconductor Equations The basic set of equations solved in device simulation are Poisson’s equation and the current continuity equations for electrons and holes: r «rf ¼ q(p n þ C)

(4:13:1) 4.13-553

© 2006 by Taylor & Francis Group, LLC

4.13-554

The Silicon Heterostructure Handbook

1 @n ! r Jn R ¼ , q @t

(4:13:2)

1 @p ! , r Jp R ¼ q @t

(4:13:3)

where f is potential, n and p are electron and hole concentrations, Jn and Jp are the electron and hole current densities, C is the net concentration of ionized dopants and charged traps, and R is the net rate of recombination (including impact ionization). The fundamental variables are f, n, and p. All the other variables are functions of f, n, and p that need to be modeled based on semiconductor physics. For simple drift-diffusion model of carrier transport, Jn and Jp are given by ! ! Jn ¼ qnmn En þ qDn rn,

(4:13:4)

! ! Jp ¼ qpmp Ep qDp rp,

(4:13:5)

where mn and mp are electron and hole mobilities, Dn and Dp are diffusivities which are related to mn and ! ! mp by Einstein relation, and En and Ep are the effective fields for electron and hole drift: EC kT NC x kT NC ! r ln 3=2 ¼ r f þ ln 3=2 , En ¼ r þ q q q q T T EV kT NV x Eg kT NV ! Ep ¼ r r ln 3=2 ¼ r f þ þ þ ln 3=2 , q q q q q T T

(4:13:6) (4:13:7)

where x is electron affinity, and NC and NV are the effective conduction and valence band density of states, and Eg is the bandgap. The band edges EC and EV are determined by f, x, and Eg: EC ¼ qf x þ D,

(4:13:8)

EV ¼ qf x þ D Eg ,

(4:13:9)

where D is a constant depending on the choice of energy reference. In a SiGe HBT, the Ge mole fraction is a function of position, and thus both x and Eg vary with position. Boundary conditions are required for solving the equations described above. Two types of boundary conditions are of particular importance: 1. The ‘‘Dirichlet’’ boundary condition at ohmic contacts, such as the base, emitter, and collector contacts. The values of f, n, and p are fixed at their equilibrium values, which are then determined by the applied voltages and doping, as well as the carrier statistics chosen. 2. The ‘‘Neumann’’ boundary condition at other edges of simulation domain (except for ohmic contacts). The fluxes of electric field and currents are assumed to be zero. The user needs to make sure the simulation domain is large enough so that the ‘‘Neumann’’ boundary condition implemented in the simulator is consistent with reality.

4.13.3

Physical Model Selection

A number of physical parameters are required in the semiconductor equations, including NC and NV, x, Eg, mn, and mp, and R. In commercial simulators such as MEDICI, only x and Eg are modeled as a function of Ge mole fraction. For parameters such as the mobilities, a number of models are available from which the user must choose. The model equations can be found in the user manuals, but the

© 2006 by Taylor & Francis Group, LLC

Device-Level Simulation

4.13-555

relevant question is which parameter models to select, and sometimes, which model parameters can be tuned in a meaningful way if needed.

NC, NV, and Eg The Ge dependence of Eg is relatively well understood and accounted for in device simulators, at least at low doping levels. The Ge dependence of NC and NV, however, are not well understood, particularly at heavy doping. Strictly speaking, the use of a single effective NC or NV is only meaningful for Boltzmann statistics in case of multiple conduction band minima or valence band maxima at different energy levels, like in strained SiGe. Due to strained, induced band splitting, NC and NV decreases with increasing Ge mole fraction first, and then ‘‘saturates’’ when the band split exceeds a couple of kT. This assumes no change of the effective mass for each band minima. At heavy doping, which is of practical interest, the situation becomes quite complicated, due to the complicated interaction of NC/NV change, BGN, and Fermi–Dirac statistics. For practical purposes, one may modify NC and NV so that the NCNV product in SiGe is about 40% of that in Si (or other numbers necessary to fit measured I–V).

Mobility and Velocity Saturation For bipolar transistor simulations, the so-called ‘‘Philips unified mobility model’’ [1] should be chosen, as this model distinguishes majority and minority carrier mobilities. Velocity saturation, which is not accounted for by default, should be turned on, as it is important in determining at what current density the peak f T is reached.

Incomplete Ionization Complete ionization of dopants in Si and SiGe is typically assumed. At heavy doping levels found in the base and emitter of SiGe HBTs, the simulation results with and without incomplete ionization can be quite different if the simplest models of incomplete ionization are used. This difference is not truly physical because the dopants should be completely ionized at all temperatures for concentrations above a certain doping level known as the ‘‘Mott’’ or ‘‘metal–insulator’’ transition. If one continues to use the incomplete ionization relations for such heavy doping levels, the majority carrier concentration is significantly underestimated, and the minority carrier concentration is equally significantly overestimated. Significant shifts of both IC and IB are then observed on the Gummel characteristics for a typical SiGe HBT. This situation has been corrected in later versions of MEDICI by applying incomplete ionization relations for doping levels below a defined low-valued threshold, and applying complete ionization for doping levels above a defined high-valued threshold, and then interpolating between the two thresholds. This option is chosen by specifying ‘‘high.dop’’ together with ‘‘incomplete’’ in the MEDICI model statement.

BGN, Statistics, and Mobility It is well known that the bandgap Eg narrows at heavy doping, which increases the pn product at equilibrium. This is often referred to as heavy doping induced BGN. Another heavy doping effect is that Boltzmann statistics is no longer accurate, and Fermi–Dirac statistics is needed instead. Naturally, one may attempt to select both BGN and Fermi–Dirac statistics for SiGe HBT simulations, as the doping levels are heavy. This, however, is not necessarily correct, depending on the BGN model chosen and the device simulator chosen, as detailed below. Perhaps the most widely used BGN model is the Slotboom BGN model. The idea is to artificially decrease the apparent electrical bandgap so that one can continue to apply Boltzmann statistics to describe the equilibrium pn product at heavy doping [2],

© 2006 by Taylor & Francis Group, LLC

4.13-556

The Silicon Heterostructure Handbook

pn ¼ n 2i0 eDG=kT ,

(4:13:10)

where ni0 is the intrinsic carrier concentration at low doping levels. The pn product changes due to a combination of degeneracy (Fermi–Dirac statistics), doping-induced rigid BGN, and density-of-states perturbations, which can all be lumped into a single parameter DG, commonly called the ‘‘apparent BGN.’’ DG is modeled as a function of doping N [2]: 2

N DG ¼ DG0 4ln þ N0

3 s ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ N 2 ln þC 5: N0

(4:13:11)

The model parameters were first reported in Ref. [2], and later updated in Ref. [3] by reinterpreting the same data using the Philips unified mobility model: DG0 ¼ 6.92 meV, N0 ¼ 1.3 1017 cm3, and C ¼ 0.5 for Si. One should, therefore, always use this set of model parameters when the Philips unified mobility model is used. The underlying reason is that the pn product at equilibrium is not directly measured, and is instead inferred from the Gummel characteristics. For instance, the base current is given by JB ¼ kT mn

n 2i0 DG=kT qVBE =kT e e , þ Nde We

(4:13:12)

þ and We are the emitter doping level and the emitter depth. The effects of degeneracy (i.e., where Nde Fermi–Dirac statistics), rigid BGN, and the NCNV changes are all lumped into the DG term. To þ are needed. Rigorous derivation of the above familiar transport determine DG from JB, mn, and Nde equation including the effects of degeneracy, rigid BGN, and NCNV changes can be performed, as was reviewed in Ref. [4], and the same analysis can be applied to derive the collector current in SiGe HBTs [5]. The equations derived by including advanced physics share the same functional form as the older equations derived using simplified physics, but differ in substance. The Ge dependence of DG is largely unknown. Experimental determination of DG involves the NC and NV of SiGe, as well as minority carrier mobilities in SiGe, whose Ge dependences are not well understood yet. Experimental results in Ref. [6] suggest that the apparent BGN is different for SiGe and Si, and the true BGN (after Fermi–Dirac correction) in SiGe and Si are close. The later, however, could potentially cause negative apparent BGN at heavy doping and large Ge mole fraction in the experience of this author. Before systematic measurement and modeling of BGN in SiGe becomes available, one may assume that the apparent BGN for SiGe is the same as for Si. Since Boltzmann statistics is used in obtaining the apparent BGN expression, one should also use Boltzmann statistics in device simulation if the apparent BGN parameters are used ‘‘as is.’’ Otherwise, the effect of degeneracy on the pn product is effectively accounted for twice. For a doping level of 1020 cm3, the DG due to degeneracy is 31.2916 meV, and is thus significant for SiGe HBTs. Therefore, Boltzmann statistics should be used as opposed to the more accurate Fermi–Dirac statistics for SiGe HBTs when the default Boltzmann-statistics-based BGN model is used. This approach, however, may potentially cause other problems in cases where Fermi–Dirac statistics is necessary, either in another region of the device where the doping level is moderate, or at low temperatures. Another potential problem is that the Einstein relations depend on the carrier statistics, which can affect minority carrier diffusivity and hence f T. One solution is to automatically adjust the value of DG based on the user’s choice of the statistics, as was done in DESSIS for the Slotboom BGN model. Figure 4.13.1 shows the apparent BGN DG as a function of n-type doping using the Slotboom model. We show two curves; the dashed curve is calculated ‘‘as is’’ (i.e., as found in most simulators), while the solid curve is calculated by applying a correction factor to remove the degeneracy effect [7]. If Boltzmann statistics is used for device simulation, the dashed curve should be used, since the degeneracy

© 2006 by Taylor & Francis Group, LLC

4.13-557

Device-Level Simulation

0.4 0.35 0.3

For use with Fermi statistics For use with Boltzmann statistics

∆G (eV)

0.25 0.2 0.15 0.1 0.05 0 1016

1016

1016 1016 N-type doping (cm−3)

1016

1016

FIGURE 4.13.1 Apparent bandgap narrowing DG for n-type doping. For device simulation using Fermi–Dirac statistics, the solid curve should be used. For device simulation using Boltzmann statistics, the dashed curve should be used.

effect is already lumped into the DG term. If Fermi–Dirac statistics is used for device simulation, however, the solid curve should be used, since it does not contain the degeneracy effect. The amount of correction needed to account for Fermi statistics is in principle dependent on NC and NV, for n- and p-type dopants, which are in turn dependent on the Ge mole fraction. The distribution of the heavy-doping-induced BGN between the conduction and valence bands is also important, as it affects the high-injection potential barrier effects [7]. This issue becomes increasingly important in scaled devices with heavy base doping. In simulators, an equal split between conduction and valence bands is assumed by default.

4.13.4 Application Issues Device Structure Specification The basic input to a device simulator is the doping and Ge profiles, which can be obtained either from process simulation or SIMS measurement. Figure 4.13.2 shows an example of doping and Ge profiles measured by SIMS. The polysilicon–silicon interface can be identified by the As segregation peak. The measured As doping ‘‘tail’’ into the Si is apparently higher than the base doping across the entire base, which is not real. In fact it is simply the result of the finite resolution limit of SIMS in following very rapidly changing doping profiles. The true metallurgical EB junction can be determined from the ‘‘dip’’ in the B SIMS profile of the base. The dopant activation percentage in the polysilicon emitter is quite low for As due to As clustering. A 5 to 10% activation rate is often assumed. The As profile in the single crystalline silicon emitter is Gaussian-like and falls from the polysilicon–silicon interface toward the base. The SIMS measured Ge profile has limited accuracy, and should be compared with the intended Ge profile during SiGe epitaxial growth. An example of the net doping profile and Ge profile used for simulation is shown in Figure 4.13.3. For two-dimensional and three-dimensional simulations, the vertical doping profile in the extrinsic base region can be obtained using SIMS in a similar manner. The lateral doping transition between extrinsic and intrinsic device, however, can only be estimated from device layout and fabrication details, since two-dimensional doping profile information is typically unavailable. For vertical profile design, onedimensional simulations can be used first because of the low simulation overhead, since one-dimensional

© 2006 by Taylor & Francis Group, LLC

4.13-558

The Silicon Heterostructure Handbook

10.0 SiGe HBT (Trapezoidal profile) X j(EB) = 35 nm WB(metallurgical) = 90 nm

As poly

1020 1019

7.5

As

Ge

5.0 P

1018 B

2.5

1017 1016 0

Germanium (%)

Dopant concentration (cm−3)

1021

200

400

0 800

600

Depth (nm)

1021

10

1020

8

1019

6

1018 4

1017

2

1016 1015 0.0

0.1

0.2

0.3

0.4

0.5

0.6

Ge percentage (%)

Doping concentration (cm−3)

FIGURE 4.13.2 Typical doping and Ge profiles measured by SIMS for a first-generation SiGe HBT. The true emitter As profile is much less abrupt than the SIMS measurement suggests.

0 0.7

Depth (µm)

FIGURE 4.13.3

Typical doping and Ge profiles used for device simulation.

simulation involves much easier gridding, easier transit time analysis, much shorter simulation time, and easier debugging. The resulting design can then be refined using two-dimensional simulation, which is necessary when accurate fmax or noise analysis is desired. Full three-dimensional simulation becomes necessary for problems which are inherently three-dimensional in nature, such as in single-event upset.

Meshing Guidelines The next step is to define the coordinate values of the points (nodes) at which the semiconductor equations are discretized. Even though commercial simulators all provide some means of regridding (e.g., based on the doping gradient), taking extra time to specify a reasonably good initial mesh usually pays off in the end. Regridding, if not well controlled, can easily generate a large number of obtuse triangle elements, which can cause numerical problems. A popular meshing method is to use a rectangular grid (e.g., in MEDICI and ATLAS). The optimum grid in a given problem depends strongly on the device metric of most interest. To simulate the forward-mode SiGe HBT operation, for instance, the EB spacer oxide corner mesh does not need to be fine. However, to simulate the reverse emitter–base junction band-to-band-tunneling current for an EB reliability study, the grid at the oxide corner needs to be very fine in order to accurately locate the peak electric field.

© 2006 by Taylor & Francis Group, LLC

4.13-559

Device-Level Simulation

A number of empirical criteria can be applied in meshing. In general, fine meshing is necessary where the space-charge density and its spatial gradient are large, e.g., in the depletion layers of the EB and CB junctions. Placing nodes along the physical junction interfaces is important for accurate simulation. In addition, grid lines must be placed at the critical points defining the SiGe profile in order to avoid creating artificial SiGe profiles that inadvertently differ from what one has in mind. When a simulator such as MEDICI is used, for instance, the initial grid lines must be placed with the SiGe and doping profiles in mind. Figure 4.13.4 shows an example of bad mesh line specification, while Figure 4.13.5 shows an example of mesh lines placed properly with the intended Ge profile in mind. Initial coarse meshes are often refined based on where the physical properties of the device structure dictate it. That is, the mesh must be refined where a given variable or change in that variable across an element exceeds a given defined tolerance. If breakdown voltage is the concern, for instance, the impact ionization rate can be used. Because of the strong nonlinearities in semiconductor problems, the doping concentration at the newly generated nodes should be determined from the original doping profile specification, instead of interpolation from the existing mesh. Theoretically speaking, the potential difference or quasi-Fermi potential difference between two adjacent nodes should generally be kept less than the thermal voltage kT/q in order to minimize discretization error. In practice, this requirement is often relaxed to about 10 to 15 kT/q between adjacent nodes. The doping concentration change between adjacent nodes should be less than two to three orders of magnitude. In high-level injection, very fine meshing is often required where the minority carrier concentration exceeds the doping concentration (e.g., in the CB space–charge region of a SiGe HBT).

Mesh Quality Assurance For assurance of mesh validity, the electrical parameters of interest (e.g., f T –IC for a SiGe HBT) should always be resimulated using a finer mesh to check for grid sensitivity effects. Identical results using

Low-noise SiGe HBT design (18% peak) 0.200

Mole fraction

0.150

0.100

0.050

0.000 0.000

0.050

0.100

0.150

0.200 0.250 0.300 Distance (Microns)

0.350

0.400

0.450

FIGURE 4.13.4 Ge mole fraction from a mesh improperly specified without the Ge profile in mind.

© 2006 by Taylor & Francis Group, LLC

0.500

4.13-560

The Silicon Heterostructure Handbook

Low-noise SiGe HBT design (18% peak)

Mole fraction

0.150

0.100

0.050

0.000 0.000

FIGURE 4.13.5

0.050

0.100

0.150

0.200 0.250 0.300 Distance (Microns)

0.350

0.400

0.450

0.500

Ge mole fraction profile from a mesh correctly specified with the Ge profile in mind.

different gridding can generally be taken to imply that a robust mesh has been achieved. In MEDICI, an overall finer mesh can be obtained conveniently using the statement ‘‘Regrid potential factor ¼ 1.5 smooth ¼ 1.’’ The ‘‘factor’’ parameter requests an automatic increase of the number of nodes by a factor of 1.5. The ‘‘potential’’ parameter indicates that the refinement is performed where the potential change between adjacent nodes is large. One can have more confidence in the mesh used if the various simulated metrics no longer change with further mesh refining. This technique can also be applied to determine the acceptable coarse meshing limit for a particular problem before running extensive parametric analysis, and can dramatically minimize overall simulation time. Since one-dimensional simulation is quite fast, very fine (finer than necessary) mesh can be used, which adds little extra simulation time, but may save time in the end spent on generating an accurate mesh with fewer nodes.

I–V Simulation DC simulations are used to capture the transistor I–V behavior, which for a SiGe HBT usually means the Gummel characteristics. A number of parameters can affect the simulated Gummel characteristics, including carrier statistics, recombination parameters, BGN model parameters, mobility models, as well as the doping and Ge profiles. All these models must be considered when attempting to obtain agreement between simulation and experimental data (we refer to this (iterative) process as ‘‘calibration’’ of the simulator). A few general guidelines for simulator-to-data calibration are given below. The collector current is mainly determined by the intrinsic carrier concentrations and base doping. The NC and NV can be adjusted, and made smaller than in Si. The detailed dependence on Ge mole fraction may not be necessary, and an average can be used. The majority carrier (hole) concentration in the base at equilibrium, however, can be inferred from the intrinsic base sheet resistance Rbi data, which

© 2006 by Taylor & Francis Group, LLC

4.13-561

Device-Level Simulation

is readily available from simple measurements on ‘‘ring-dot’’ test structures. Slight changes to the SIMS measured doping profile can be made to match measured IC, at least to the range of accuracy of the SIMS data. This calibration technique is particularly useful when no ‘‘dip’’ exists in the base boron profile to indicate the precise EB junction location, as in a SiGe HBT with a phosphorous-doped emitter or a pnp SiGe HBT. The base current is primarily determined by the emitter structure in a SiGe HBT. Practically all viable SiGe HBT technologies have polysilicon emitter contacts. The polysilicon region can be either modeled as a Schottky contact or simply as an extension of the crystalline silicon emitter (the so-called ‘‘extended emitter’’ structure). The default model parameters for polysilicon are the same as those for silicon, and need to be modified by the user. The work function and surface recombination velocities can be adjusted as fitting parameters in order to calibrate the IB if using a Schottky contact. For the extended emitter approach, the hole lifetime parameters can be adjusted to obtain agreement. The two approaches, however, can result in different emitter charge storage. For highly scaled HBTs where the emitter transit time is significant, the extended emitter approach is recommended, as it accounts for charge storage in polysilicon. Figure 4.13.6 shows a calibration example for the SiGe HBT Gummel characteristics using the techniques described above. The model parameters were calibrated to 200 K data and then used to reproduce the 300 K data as is (i.e., no further tuning of parameters). Accurate simulation of the Gummel characteristics can be quite challenging, particularly for the high VBE range when high injection occurs, and the impact of emitter and base resistance is not negligible.

High-Frequency Simulation

Collector and base currents (A)

High-frequency two-port parameters can be simulated using small-signal ac analysis. Here, f T, fmax, as well as the various noise parameters can all be extracted from the simulated two-port parameters [8, 9]. Although there are many parameters that one can adjust, determining a single set of simulation parameters for a SiGe HBT that can reproduce the four complex network parameters at all biases of interest for frequencies up to f T requires substantial effort. An in-depth understanding of the interaction between the physics underlying the simulation models and the device operation is important for achieving sensible results. For instance, at low currents, the total transit time is dominated by the time constants related to the EB space–charge region capacitance rather than the diffusion capacitance. Therefore the adjustment of extrinsic device structure as well as the intrinsic EB junction is needed to match the measured f T at low JC. Even though mobility model parameters (including parameters for both the low field mobility and the velocity saturation models) can be modified for f T calibration at high

10−2 10−4 10−6

Measurement Simulation Coeff.tuned to 200 K data 2–8%Ge profile AE = 0.8⫻2.5 µm 300 K VCB = 0 V

10−8 10−10 0.3

200 K

0.5 0.7 Base−emitter voltage (V)

0.9

FIGURE 4.13.6 A calibration example for the Gummel characteristics of a SiGe HBT using the described calibration strategy. The same set of model parameters was used for both the 300 and the 200 K simulations.

© 2006 by Taylor & Francis Group, LLC

4.13-562

The Silicon Heterostructure Handbook

JC near the f T peak, it should be used as a last resort. Instead, adjustments to the two-dimensional structure and lateral doping profile transitions should first be attempted. Because exact matching of the Gummel characteristics is difficult, high-frequency calibration of ac parameters such as f T should always be made at fixed JC, and not at fixed VBE. For efficient calibration of the Y-parameters across a wide frequency range and a large JC range, one can first calibrate the f T –JC and fmax–JC curves. For state-of-the-art SiGe HBTs with narrow emitters, the shallow-trench isolation and extrinsic CB capacitances can often be comparable to the intrinsic CB capacitance, and are therefore nonnegligible. For accurate Y-parameter simulation, all the twodimensional lateral structure must be included. The extrinsic base and collector structures (geometric overlap as well as lateral doping profile transition) can then be modified to calibrate fmax–JC. Typically, once f T –JC and fmax–JC are calibrated, the simulated Y-parameters will match the measured Y-parameters reasonably well. For accurate separation of the intrinsic and extrinsic base resistances and CB capacitances, transistors with different emitter widths (if available on the test die) can be measured. By simulating and measuring devices with different emitter widths, the contribution of the extrinsic and intrinsic elements can be accurately separated. A useful technique for high-frequency SiGe HBT calibration is to extract the equivalent circuit parameters such as CBE, CBC, and rb as a function of JC. Analytical extraction methods, which use only single frequency data, are highly desirable because they are efficient, since we only need a rough picture to guide us on the appropriate changes to make in our device structure or model coefficients. The parameter extraction method proposed in Ref. [10], for instance, can be used. By comparing the simulated and measured CBE, CBC, rb, re, and rc, one can readily identify the dominant factors for any simulation-to-measurement discrepancy, and adjust the lateral doping extension accordingly. The diffusion capacitance component of CBE is proportional to JC at relatively low current densities (i.e., before the f T roll-off), and can thus be distinguished from the depletion capacitance component. Figure 4.13.7 shows an example of f T –JC calibration for a typical firstgeneration SiGe HBT obtained using the techniques described above. This calibration was successfully achieved using two-dimensional MEDICI simulations without modifying the model parameters of the Philips unified mobility model and the velocity saturation model. The intrinsic base and collector doping profiles from SIMS were also used as measured. Most of the required adjustments were instead made in the extrinsic device regions.

80 Measurement 2-D Simulation

fT (GHz)

70 60

SiGe HBT

50

0.5×20×2 µm2 VCB = 1 V

40 30 20 10 0 10−2

10−1

100 JC

FIGURE 4.13.7

(mA/µm2)

An example of fT –JC calibration for a typical first-generation SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

101

4.13-563

Device-Level Simulation

Qualitative versus Quantitative Simulations Obviously, qualitative simulation is much easier and quicker than quantitative simulation. Doing a rough relative comparison between two device structures is much easier than simulating a single device structure to high accuracy. An advantage of qualitative simulation is that fewer grid points can be used and hence simulation time can be dramatically reduced. For instance, the comparison of current gain and cutoff frequency between Si BJT and SiGe HBT can be made using a coarse grid. An ‘‘exact’’ simulation, however, is obviously quite involved.

4.13.5 Probe Internal Device Operation The fundamental reason for the degradation of transistor performance at higher frequency is charge storage. The resulting capacitive current, typically at the transistor input, increases with frequency, leading to the degradation of current gain and power gain. The most effective way to examine the details of charge storage is to perform a small-signal ac simulation in the frequency domain. The small signal electron concentration (nac) profile contains information on the spatial distribution of the total transit time. nac is in general a complex number, but reduces to a real number at low frequency. Using nac and the small-signal collector current density JC,ac, the ‘‘effective transit time velocity’’ (nt) can be defined as nt ¼

JC,ac : qnac

(4:13:13)

The ‘‘accumulated transit time’’ can then be defined for a given position along the path of electron transport according to t acc (x) ¼

Z 0

x

1 1 dx ¼ nt JC,ac

Z

x

qnac dx:

(4:13:14)

0

Figure 4.13.8 shows tacc versus depth at the peak f T point calculated using 1 MHz ac simulation results. The f T estimated from tec ¼ tacc(x ¼ xcc) (i.e., the transit time defined from quasi-static analysis) is 42.3 GHz, with xcc being the location of the collector contact. The f T extrapolated from h21, however, is 45 GHz. In general, there is a good correlation between the f T determined from h21 and the f T

3

⫻10−12 1 MHz AC simulation

2.5

tacc (sec)

2

tec = 2.77 psec

1.5 1/2πtec = 57 GHz 1 fT from h21 extraction = 45 GHz

0.5 0 0

0.1

0.2

0.3 0.4 Depth (µm)

FIGURE 4.13.8 Accumulated transit time versus depth in a SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

0.5

0.6

0.7

4.13-564

The Silicon Heterostructure Handbook

5

⫻1010

fT (Hz)

4

|h21| gm/jwC ac n (real)

3

2

1

0 10−3

10−2

10−1 JC

FIGURE 4.13.9

100

101

(mA/µm2)

Comparison of three methods of determining fT using numerical simulation.

determined from 1/2ptec. A comparison of the f T extracted using the above two methods is shown in Figure 4.13.9, together with that extracted using fT ¼

gcb , 2pCbb

(4:13:15)

where gcb is the real part of Y21, Cbb is defined by the imaginary part of Y11, and Y11 ¼ g11 þ jvCbb. Here, Cbb was evaluated at 1 MHz in the above example, and is nearly independent of the frequency used in the simulation as long as the frequency chosen is well below f T. For comparison with experimental f T data, the value from jh21j extrapolation should be used, as opposed to that from the accumulated transit time, which uses the quasistatic approximation. The practical reason for this is that experimental f T data are all obtained from h21 extrapolation. Despite the fact that the resulting f T value may be off compared to the value obtained from h21 extrapolation, the transit time analysis of nac and the tacc(x) profiles provide information of the local contribution to the total transit time, and can be very useful in identifying the transit time limiting factor in a given device design (i.e., for profile optimization). Since nac and JC,ac are nearly independent of frequency up to f T, we can evaluate tacc(x) at any frequency below f T. In this example, the results are nearly the same from 1 MHz to 60 GHz. This insensitivity to frequency proves useful in practice.

Regional Analysis of Transit Time The total transit time defined by tacc(x ¼ xcc) can be divided into five components to facilitate physical interpretation [11]. Two boundaries, the electrical EB and CB junction depths x*eb and x*cb are defined to be the in-most intersections of the nac and pac curves inside the junction space–charge regions (as illustrated in Figure 4.13.10). The same SiGe HBT with a 2 to 8% graded base was used in this case. The peaks of nac and pac can be understood as the approximate space–charge region boundaries on the emitter and base sides, respectively, even though the results clearly show that no abrupt space–charge region boundary can be identified (i.e, the depletion approximation is invalid). The ‘‘neutral base’’ that corresponds to traditional bipolar theory can be approximately identified as where nac pac. The ‘‘neutral’’ base width is clearly smaller than the electrical base width defined by x*cb x*eb . With scaling of base width into the nanometer regime, the region where nac pac eventually disappears, and the

© 2006 by Taylor & Francis Group, LLC

4.13-565

Device-Level Simulation

Magnitude nac, pac (cm3)

5

* xcb

x*eb

⫻1016

nac pac

4

3

C

B

E 2

Neutral base 1

0 0.12

0.14

0.16

0.18 0.2 Depth (µm)

0.22

0.24

0.26

FIGURE 4.13.10 Definition of the electrical EB and CB junctions from the simulated nac and pac profiles. The bias is chosen at the peak fT point.

electrical base width should be used instead for device analysis. The electrical EB and CB junction locations (x*eb and x*cb ) are in general different from the metallurgical junctions (xeb and xcb), as expected. The total tec can be divided into five components with the help of pac [11]: 1. The emitter transit time due to minority carrier storage in the emitter t *e ¼

Z

q JC,ac

* xeb

pac dx:

(4:13:16)

0

2. The EB depletion charging time due to the storage of uncompensated mobile carriers t *eb ¼

Z

q JC;ac

* xeb

(nac pac )dx:

(4:13:17)

0

3. The base transit time due to electron charge storage in the electrical base (which includes the traditional ‘‘quasineutral base’’) t *b ¼

Z

q JC,ac

* xeb

nac dx:

(4:13:18)

(nac pac )dx:

(4:13:19)

* xeb

4. The CB depletion charging time t *cb ¼

Z

q JC,ac

xcc * xeb

5. The collector transit time

t *c ¼

© 2006 by Taylor & Francis Group, LLC

q JC,ac

Z

xcc

* xeb

pac dx:

(4:13:20)

4.13-566

The Silicon Heterostructure Handbook

Note that t*c , as defined above, is different from the traditional tc, and t*c is important only when holes are injected into the collector after the onset of high injection. The sum of all the transit time components is equal to tec t ec ¼

q

Z

JC,ac

0

xcc

nac dx ¼ t *e þ t *eb þ t*b þ t*cb þ t *c

(4:13:21)

The transit time due to electron charge storage in the EB space–charge region is not treated separately, but is instead included in the modified transit times of the emitter and base (the ‘‘*’’ transit times above). Under high injection, however, the whole transistor from emitter to collector is flooded with a high concentration of electrons and holes, and hence no clear boundaries can be identified. Strictly speaking, the concepts of base, emitter, and collector consequently lose their conventional meanings, and thus the concept of regional transit times is no longer meaningful. In SiGe HBTs, the SiGe-to-Si transition at the CB junction causes additional electron charge storage at high injection. In this case, the x*eb and x*cb definitions discussed above cannot be applied.

High-Injection Barrier Effect We now examine the evolution of the small-signal qnac/JC,ac and qpac/JC,ac profiles with increasing current density JC from well below the peak f T current density to slightly above the peak f T current density. The simulated qnac/JC,ac and qpac/JC,ac profiles at three current densities representing low to high injection levels are shown in Figure 4.13.11(a)–(c). The small-signal magnitude of the VBE increase is 2.6 mV. At a typical low-injection JC of 0.127 mA/mm2, well below the peak f T point, nac is positive across most of the device. Most of the charge modulation occurs in the EB space–charge region. The transit time related to this component of the charge storage decreases with increasing JC because of increasing JC,ac, which can be seen by comparing the magnitude of the first peak on the curves for the electrons in Figure 4.13.11(a) and (b). Note that different scales are used on the y-axis for different injection levels to help visualize the details of the profiles. At JC ¼ 1 mA/mm2, near peak f T, the base and collector transit time contributions become dominant compared to the EB space–charge region contribution (as shown in Figure 4.13.11(b)), mainly due to a decrease of the EB space–charge region transit time. One consequence of high-level injection is that the

qnac/JC,ac, qpac/JC,ac (sec/µm)

3.5

⫻10−10 qnac/JC,ac qpac/JC,ac

3 2.5 2 1.5

fT = 29 GHz

1 0.5 0 −0.5 0.1

0.15

0.2

0.25

0.3

Depth (µm) (a) Well below peak f T (JC = 0.127 mA/µm2)

© 2006 by Taylor & Francis Group, LLC

0.35

0.4

0.45

0.5

4.13-567

Device-Level Simulation

qnac/JC,ac, qpac/JC,ac (sec/µm)

10

⫻10−11 qnac/JC,ac qpac/JC,ac

8 6 near peak fT 4

fT = 43 GHz

2

negative

0 −2 0.1

0.15

0.2

0.25

0.3 0.35 Depth (µm) (b) Near peak f T (JC = 0.999 mA/µm2) ⫻10−11 8

0.4

0.45

0.5

0.45

0.5

qnac/JC,ac, qpac/JC,ac (sec/µm)

7 6

SiGe/Si transition induced electron charge storage

5 4 3 2 1

electrons holes

0 −1 0.1

0.15

0.2

(c) Just above peak f T

FIGURE 4.13.11 injection.

0.25

0.3 0.35 Depth (µm) (JC = 1.760 mA/µm2)

0.4

Simulated qnac/JC,ac and qpac/JC,ac profiles at (a) low injection, (b) medium injection, and (c) high

CB space–charge region pushes toward the collector nþ buried layer much more obviously than at lower JC, despite a decrease of VCB. This is manifested as a large negative nac and hence negative nac/JC,ac around 0.37 mm. Physically, this corresponds to the extension of the CB space–charge region towards the nþ buried layer, which causes a decrease of electron concentration at the front of the space–charge region. In the simulation, the base voltage is increased while the collector and emitter voltages are fixed. Because of the existence of negative nac, the real part of the simulated nac, as opposed to the absolute value of the simulated nac, should be used for calculation of the total transit time. A significant error can be introduced under high injection when the integral over the negative nac portion becomes significant to the total integral. We note that this negative-going nac component under high-injection is generally not treated properly in the literature. Figure 4.13.11(c) shows the qnac/JC,ac and qpac/JC,ac profiles at a slightly higher JC of 1.76 mA/mm2, just past the peak f T. The SiGe–Si interface, which was buried in the CB space–charge region under low

© 2006 by Taylor & Francis Group, LLC

4.13-568

The Silicon Heterostructure Handbook

qnac/JC,ac, qpac/JC,ac (sec/µm)

3

⫻10−10 qnac/JC,ac qpac/JC,ac

2.5 2 1.5 1 0.5 fT = 8 GHz

0 −0.5 0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Depth (µm)

FIGURE 4.13.12

Simulated nac and pac profiles at JC ¼ 3.56 mA/mm2.

injection, is now exposed to the large density of electrons and holes. The valence band potential barrier to holes induces a conduction band potential barrier to electrons as well. The most important consequence is increased dynamic charge storage, as seen from the high qnac/JC,ac and qpac/JC,ac peaks near the SiGe–Si transition in Figure 4.13.11(c). This additional charge storage results in a significant increase of the total transit time and hence a strong decrease of f T to 29 GHz, even though the current density is just above the value needed to reach the peak f T (1.0 mA/mm2). At an even higher JC of 3.56 mA/mm2, both qnac/JC,ac and qpac/JC,ac are very large, and nearly equal to each other (as shown in Figure 4.13.12). No clear space–charge regions can be identified from the qnac/ JC,ac and qpac/JC,ac profiles. The conventional concepts of emitter, base, and collector no longer apply in this situation. The majority of the overall transit time, however, is contained inside the SiGe ‘‘base,’’ as intuitively expected.

4.13.6

Summary

We have introduced the basics of semiconductor device simulation, and practical aspects of SiGe HBT simulation using commercial device simulators, including structure specification, meshing, and physical model selection. Strategies for calibration of dc and RF device characteristics are presented and illustrated. The spatial distributions of small signal ac electron and hole concentrations and the transit time velocity provide insight into the mechanisms of charge storage. The high-injection barrier effect in SiGe HBTs is illustrated using ac simulation results.

Acknowledgment This work is supported by NSF under ECS-0112923 and ECS-0119623 and by SRC under SRC-2001-NJ937 and SRC-2003-NJ-1133.

References 1. DBM Klaassen. A unified mobility model for device simulation I. Model equations and concentration dependence. Solid-State Electron. 35:953–959, 1992.

© 2006 by Taylor & Francis Group, LLC

Device-Level Simulation

4.13-569

2. JW Slotboom and HC de Graaff. Measurements of bandgap narrowing in Si bipolar transistors. Solid-State Electron. 19:857–862, 1976. 3. DBM Klaassen, JW Slotboom, and HC de Graaff. Unified apparent bandgap narrowing in n- and p-type silicon. Solid-State Electron. 35:125–129, 1992. 4. CM van Vliet. Bandgap narrowing and emitter efficiency in heavily doped emitter structures revisited. IEEE Trans. Electron Dev. 40:1141–1147, 1993. 5. GF Niu. Modeling and Simulation of SiGe Microelectronic Devices. M.S. Thesis, Fudan University, 1994. 6. Z Matutinovic-Krstelj, V Venkataraman, EJ Prinz, JC Sturm, and CW Magee. Base resistance and effective bandgap reduction in npn Si/SiGe/Si HBTs with heavy base doping. IEEE Trans. Electron Dev. 43:457–466, 1996. 7. Y Shi, GF Niu, and JD Cressler, On the modeling of BGN for consistent device simulation of highly scaled SiGe HBTs. IEEE Trans. Electron Dev. 50:1370–1377, 2003. 8. G Niu, S Zhang, JD Cressler, AJ Joseph, JS Fairbanks, LE Larson, CS Webster, WE Ansley, and DL Harame. Noise modeling and SiGe profile design tradeoffs for RF applications. IEEE Trans. Electron Dev. 47:2037–2044, 2000. 9. GF Niu, WE Ansley, S Zhang, JD Cressler, C Webster, and R Groves. Noise parameter optimization of UHV/CVD SiGe HBTs for RF and microwave applications. IEEE Trans. Electron Dev. 46:1347– 1354, 1999. 10. P Baureis and D Seitzer. Parameter extraction for HBTs temperature dependent large signal equivalent circuit model. Technical Digest of IEEE GaAs IC Symposium, 1993, pp. 263–266. 11. JJH van den Biesen. A simple regional analysis of transit times in bipolar transistors. Solid-State Electron. 29:529–534, 1986.

© 2006 by Taylor & Francis Group, LLC

4.14 SiGe HBT Performance Limits Greg Freeman, Andreas Stricker, and David R. Greenberg IBM Microelectronics

Jae-Sung Rieh Korea University

4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 4.14.6

Performance ........................................................... 4.14-571 Intrinsic and Extrinsic Partitioning ..................... 4.14-572 Intrinsic Device Scaling ........................................ 4.14-575 Extrinsic Device RC Delays .................................. 4.14-577 Practical Limitations ............................................. 4.14-579 Summary ................................................................ 4.14-580

4.14.1 Performance How high a performance can be achieved in silicon-based bipolar transistors? An answer to such a question surely considers many assumptions. New discoveries continue to affect the critical aspects of device operation such as charge storage, carrier transport, and parasitics. Other discoveries affect the processing of the device, leading to even better ways to make the device structurally ideal. One example of a historic discontinuity in device fabrication and operation is the development of production-ready SiGe epitaxy. Before the advent of SiGe epitaxy, predictions toward device limits would likely have made certain assumptions regarding emitter charge storage or minority carrier diffusion and this would clearly be off the mark due to the significant advancement in SiGe band engineering. More recently, the incorporation of carbon has provided a boost, strongly affecting the diffusion of dopants and thus providing a greater control over the device structure. Similar innovations are expected to continue to provide a boost to the device operation, and so continually change the assumptions that may go into predicting limits of device operation. It is common to think principally of the f T figure-of-merit in discussion of performance limits, yet this figure-of-merit in itself is a poor predictor of most circuit performance. Depending on the application, other device figures-of-merit such as collector–emitter breakdown voltage (e.g., BVCES), linearity, power added efficiency, or fMAX, may be preferred for predicting circuit performance. Most broadly applicable is the fMAX figure-of-merit, which more strongly takes into account key parasitic elements and better predicts the power capability and digital switching delay, and is to first order related to f T through the following relation:

fMAX

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ fT ﬃ 8pRB CCB

(4:14:1)

where RB and CCB are the total base resistance and collector–base capacitance, respectively. f T then is not only a figure-of-merit, but also a key component of fMAX, and so it is important to understand f T limitations since they are also limitations to other figures-of-merit. A simplified expression for the f T delay components of a SiGe bipolar transistor is 4.14-571 © 2006 by Taylor & Francis Group, LLC

4.14-572

The Silicon Heterostructure Handbook

1 kT kT W 2 WCSCL ¼ t EC ¼ t E þ t C þ t B þ t CSCL ﬃ CEB þ þ RC þ RE CCB þ B þ 2pf T qIC qIC gDn 2vSAT

(4:14:2)

where CEB and CCB are emitter–base and base–collector capacitance, RC and RE are collector and emitter resistance, WB and WCSCL are neutral base and base–collector space–charge layer width, respectively, k is the Boltzmann constant, T is temperature, q is unit electron charge, g is field factor, and vSAT is the electron saturation velocity. This clearly illustrates the complex nature of the transit time, which includes neutral base and collector space–charge layer transit times tB and tCSCL, as well as R * C delays. These R * C delay terms are improved by transconductance (qIC/kT) improvements and improvements in parasitic resistances. Limitations to performance come from the physical reality in achieving narrow base width, narrow collector–base space–charge layers, low resistances, low capacitances, and the ability to achieve high current densities with acceptable device self-heating and reliability. We assert that performance advancement has taken place uniformly across the various limiting parameters and device structures over time, and so the performance continues to be limited by the same effects as prior generation devices. This means for instance that unwanted diffusion still has a major impact on transit times and parasitic capacitances. Also, base widths are much larger than deposited and collector pedestals are wider than implanted due to dopant diffusion. Yet dopant diffusion is not always bad, since diffusion is needed to define required junction depths and to improve device properties such as base resistance and junction leakage [1]. With reduced dimensions, the constraints in device design only become tighter with increased sensitivity to dopant profile details, such as implant tails and two-dimensional effects. Therefore, the engineering of a device becomes a complex tradeoff of such effects, and is highly constrained by the device structures chosen and process steps available. One should expect improvements along the same line as previously established — e.g., that the base will become more narrow and more highly doped, that the collector will become more narrow (vertically and laterally) and self-aligned for lower parasitic capacitance as well as lower resistance, and that the emitter and base will become lower resistance. Numerous process steps not implemented into the SiGe HBT processes are already available for such improvements, including anneals, silicides, self-alignment techniques [2, 3]. This chapter takes the approach of considering a nearly ideal device structure, which all these improvements will continue to approach, and provide discussion of the remaining effects limiting performance, in order to provide some insight into the eventual device limitations and effects to be overcome for continued improvements. By this approach, the more practical effects are considered and eventual limits may be better understood.

4.14.2

Intrinsic and Extrinsic Partitioning

To understand the constraints to device performance, consider the ‘‘intrinsic’’ versus the ‘‘extrinsic’’ portion of the device. By understanding to what extent the performance of the complete device is impacted by the extrinsic portion of the device, we can better understand what structural improvements may influence the device performance. The intrinsic portion is commonly considered the region of the device defined vertically between the neutral emitter to the neutral collector. The lateral dimension of this intrinsic region, approximately 100 nm, is considerably smaller than the complete device, which is typically over 1 mm in width. The exact partitions between the intrinsic and extrinsic regions are somewhat arbitrary, and for the purposes of the study to follow, we wish to define these partitions such that the more fundamental aspects of the device operation are contained in the intrinsic portion of the device. This means that the intrinsic portion contains as little as possible of the resistive elements in the neutral emitter and collector, since one may improve these by structural changes in the device such as with silicides or improved dopant levels. The shape of this intrinsic region is generally shown to be rectangular, as a sort of expanded one-dimensional device operation. As shown by the current flow lines in Figure 4.14.1, actual intrinsic

© 2006 by Taylor & Francis Group, LLC

4.14-573

SiGe HBT Performance Limits

device operation takes place in a very much two-dimensional fashion and so the shape of the intrinsic region is not necessarily a rectangle. The electron flow from the emitter spreads laterally from the actual emitter–base junction due to the lateral potential drops in the base and the complex injection from the edges of the emitter–base junction. This flow becomes vertical and more one-dimensional through the neutral base, and then spreads to a wider region of the device as it traverses the collector–base space– charge region because the low resistance portion of the collector is generally wider compared to the emitter opening. Structural improvements may be made to either the intrinsic or the extrinsic device. The intrinsic device structure changes result in relatively predictable performance benefits and tradeoffs. The extrinsic device provides the performance-enhancing opportunity without significant tradeoff, since this portion of the device is not fundamental to the device operation and so parasitic reductions are not generally accompanied with other performance losses. Consider the trend in RB and CCB versus the advancements in f T as shown in Figure 4.14.2 [4–11]. The CCB values continue to increase with increasing f T because the intrinsic portion is a majority portion of the total CCB for the device (where the pedestal is defined). The RB has been dominated by the extrinsic portion of the device and so is not fundamental to achieving the higher f T and is shown to be more suited to improvement with structural modifications [6, 9].

Emitter

Base

Collector

FIGURE 4.14.1 Current flow lines from TCAD simulations illustrating strong two-dimensional behavior of the SiGe HBT device.

400

4

3

200

2

100

1

CCB (fF/µm)

R B (Ohm µm)

C CB 300

RB 0

0

50

100 150 f T (GHz)

200

0 250

FIGURE 4.14.2 Base resistance RB (open symbols) and collector–base capacitance CCB (solid symbols) trend with f T. Values are normalized to emitter length. Values reported here are limited to those published results where fMAX > f T and where RB and CCB are both reported [4–11].

© 2006 by Taylor & Francis Group, LLC

4.14-574

The Silicon Heterostructure Handbook

We have performed process and device (TCAD) simulations in order to estimate the performance of the intrinsic-only device without the extrinsic device [12, 13]. In order to estimate the two-dimensional nature of device operation described above, yet stay within the straightforward implementation of the simulator, we define the intrinsic region of the device as a rectangle, and this is approximately twice the width of the emitter opening. This allows for the realistic injection of the carriers from the emitter junction edge, and the spreading of these carriers to the pedestal portion of the collector. The region is also bounded at the emitter side approximately 2 nm into the neutral emitter and at the collector side approximately 40 nm into the neutral collector. Figure 4.14.3 shows the cross section of the intrinsic device within the complete device. Note that the intrinsic device contains ohmic contacts to the base, emitter, and collector as if the rectangle were in free space connected by nonresistive contacts at the four access points. These four contacts also provide a thermal sink to reduce the intrinsic-only device heating, and we will discuss the thermal issues in real devices in the last section of this chapter. The simulator attempts to mimic the process steps and the electrical characteristics of the f T ¼ 350 GHz device reported in Ref. [14], and as such the simulation parameters have been calibrated to achieve good predictability in the fabrication of this device and its electrical behavior. The simulators and methods used are similar to that used in prior generation devices [12]. Figure 4.14.4 shows the results of the simulation comparison (dark arrows). Compared to the parasitic values that would be present in an intrinsic-only device, we observe that the extrinsic device contributes significantly to the overall parasitics, at an additional 35%, 180%, 124%, and 42% in CBE, CCB, RC, and RB, respectively. This extrinsic device strongly reduces the device performance. f T and fMAX comparisons also shown in Figure 4.14.4 indicate that values of 557 and 630 GHz respectively become 332 and 224 GHz, which correspond approximately to measured values reported in Ref. [14]. From this analysis, it is clear that contributed parasitic resistances and capacitance from the extrinsic device degrades performance as measured in f T and fMAX. Other device designs will show different partitioning of performance. Namely, devices with lower intrinsic base sheet resistance will exhibit a lesser portion of the total base resistance from the intrinsic device. Due to the thermal contacts at the base, emitter, and collector of the intrinsic-only device, we observe similar self-heating characteristics between the simulations. Without the thermal sinks, the performance would significantly degrade. The thermal issue will only become more acute with increasing device performance (due to the increasing current density), with increasing need for effective thermal conductivity away from the device. The intrinsic device scenario depicted here, where the electrical contacts provide a thermal sink, may be realistic in some small-integration device configurations (e.g., power amplification devices), but in a more general configuration of highly integrated chips, a thermal sink through the substrate will be

Extrinsic emitter

Extrinsic base

Extrinsic collector

Intrinsic device with contacts

FIGURE 4.14.3 Intrinsic device portion of full extrinsic device represented in TCAD simulations. The intrinsic dimension is approximately twice the emitter-opening dimension in order to capture the two-dimensional nature of the device operation.

© 2006 by Taylor & Francis Group, LLC

4.14-575

SiGe HBT Performance Limits

required. For such highly integrated chips, the extrinsic device has the significant function of conducting heat away from the intrinsic device, and this aspect cannot be ignored in device optimization. Thus, in consideration of the device limits, the intrinsic device cannot be considered independent of the extrinsic device. One should consider both what can practically be done to improve performance reducing effects of the extrinsic device, and the thermal benefits provided by the extrinsic device. In the next two sections, we consider the scaling aspects of the intrinsic and extrinsic devices separately.

4.14.3 Intrinsic Device Scaling Classical scaling, with the reduction in delay elements captured in Equation (4.14.2), is expected to continue to improve SiGe HBT device performance. As mentioned previously, SiGe HBT vertical profiles, while in the range of 10 nm, are still dominated by practical processing effects such as diffusion and growth constraints. As in the past, improved device structures, process integration techniques, and tooling are expected to open up new performance territory through continued device scaling. We explore issues and unknowns related to intrinsic device scaling above 1 THz in this section. Experience has shown that, in the graded-base SiGe HBT, the carriers travel in the range of saturation velocity through most of the neutral base and collector space–charge region. Therefore, transit time is largely a function of carrier velocity and dimensions. Clearly, one goal is the reduction in base dimension WB and collector–base space–charge layer WCSCL. However, the ever-reduced dimensions begin to put the commonly assumed drift–diffusion physics, which determine the effective vSAT, into question. In transistors with large critical dimensions (e.g., base widths), the acceleration of carriers in an electric field is counteracted by impurity and phonon scattering, which act toward randomizing the momentum and bringing the carriers into thermal equilibrium with the lattice. This balance results in a steady-state velocity for any given field, characterized by the mobility and saturation velocity of the sample. Since scattering takes place at a finite rate, however, a carrier may not scatter at all over a sufficiently short interval of time. As a result, carriers crossing a sufficiently small base may be able to do so with very little scattering and thus with very little change in their initial velocity. In silicon, acoustic phonons scatter

1400

600

1200

500 % Increase with extrinsic portion added

600 400 200

Intrinsic

800

Whole device

fT, fMAX (GHz)

1000

400

300

200

100

0

0 fT

fMAX

CBE

CCB

RC

RB

FIGURE 4.14.4 Electrical parameter shifts with addition of the device extrinsic portion as predicted by TCAD simulation. Thick arrows are the 350 GHz device as reported in Ref. [14]; thinner arrows are simulated 1.16 THz (intrinsic) device.

© 2006 by Taylor & Francis Group, LLC

4.14-576

The Silicon Heterostructure Handbook

electrons between sixfold-generate conduction band minima with a time constant on the order of 1013 to 1014 sec. Based on an electron velocity in the range of 106 to 107 cm/sec, ballistic transport across a HBT base becomes possible as base widths shrink below 10 nm. To maximize the benefits of ballistic transport, a HBT design must provide a method for electrons to attain and maintain a high velocity for a large fraction of their trip across the base. One such method is to introduce a very high electric field at the emitter side of the base, rapidly accelerating electrons to ‘‘overshoot’’ velocities greater than predicted by the scattering-driven steady-state velocity versus field curve. Since accelerating electrons from low velocity can consume an appreciable portion of the base transit and reduce the overall effective velocity, however, an improved method involves the inclusion of a ‘‘launcher’’ capable of injecting electrons from the emitter into the base at high initial velocities. Studies of source velocity in nanoscale NFETs illustrate that injection over a simple energy barrier, such as in the emitter–base junction of a homojunction BJT or of a graded SiGe HBT with no SiGe mole fraction at the junction, limits the injection velocity to the average thermal velocity of electrons moving in the desired direction. Such velocities may exceed 1.2 107 cm/sec, reducing the transit time across a 10 nm base to less than 0.08 psec [15]. Bandgap engineering, commonly used in III–V device design, can be used to increase injected carrier velocity still further. One possible design is an abrupt conduction band discontinuity at the emitter–base junction, with a lower conduction band energy in the base. Such a heterojunction can be realized with a strained Si emitter grown atop an unstrained SiGe base, for example. As an electron crosses this junction, the conduction band ‘‘floor’’ drops out from under it, converting potential energy into a large kinetic energy. Since electrons injected in this manner will cover a wide range of velocities, the average velocity is reduced by the slowest of the population. A tunneling barrier, such as a very thin layer of SiO2, can be inserted between the emitter and base to filter the carrier population and pass only the highest energy members of the population. A quantum well can be used for the same purpose, with the energy levels of the well tuned by well width to form a ‘‘pass band’’ for the desired electron energies. Using these structures, and with the ever-reduced dimensions of the SiGe HBT, transit time benefits may be obtained through increased effective carrier velocity. In consideration of the capacitance charging time reduction with scaling, the principal benefit is higher Kirk-effect current, which results from the collector design scaling. This translates to higher current densities and higher device transconductance qIC/kT before the base-push-out effect reduces the microwave performance of the transistor. Lateral scaling typically accompanies the device current density increase, and because the dimensions scale down at a similar rate to the current density increase, a similar net device current is obtained between generations. Unit collector–base capacitance also fundamentally increases with the increasing current density, since collector doping must be increased or the collector epi layer must be decreased to accommodate the current density increase. Like with the current density increase, lateral scaling can decrease the effect of the higher unit capacitance by reducing the effect at the device level. By reviewing again Equation (4.14.1) and Equation (4.14.2), a fundamental tradeoff between increasing IC and increasing CCB and their impact to fMAX and f T is apparent. In f T, one can see that a CCB increase offsets the collector scaling benefit in WCSCL reduction and IC increase. Assuming that the CCB capacitance dominates the total device capacitance (today surpassing CEB in the highest speed SiGe HBT devices), and assuming the (RE þ RC)CCB term remains small due to resistance reduction, we note that in the CCB and WCSCL tradeoff, the f T improvement is favored with collector doping increase. Consider CCB are related to doping NC through the well-known relations that the Kirk current JCP andpdevice ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃ JCP ¼ qvSATNC and CCB ¼ qNC «S =2(VBI þ VCB ) [16]. Therefore, the ratio of JCP/CCB / NC will increase with scaling, which will be favorable to increasing f T. The effect of the tradeoff on fMAX is not as clear. In the extreme case wherein CCB dominates the capacitance portion in the f T expression (such as in many III–V devices), fMAX sees diminishing returns with vertical scaling as approximated by fMAX2 / f T/ pﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃ CCB / ( NC þ K )= NC , where K represents the remaining terms of the f T expression unaffected by the collector scaling.

© 2006 by Taylor & Francis Group, LLC

SiGe HBT Performance Limits

4.14-577

Other authors have performed simulations of intrinsic-only devices above 1 THz [17]. While that report does provide useful insight into the operation of the device, we wish to include certain phenomena not included in that simulation. For instance, as previously mentioned, we wish to utilize a calibrated simulation deck to a high-speed device, as well as capture the two-dimensional device behavior with the two-dimensional current injection from the emitter and the lateral spreading of the current into the collector. We also wish to understand the effects of self-heating and of the extrinsic device. We still rely on drift–diffusion device simulations, and inaccuracies are likely in this regime as a result. However, we have found surprising predictability over many generations of devices, and so believe that these same simulation techniques should (to first order) continue to provide insights into the device scaling. Following this approach, we have simulated the fabrication and operation of a complete device, and when the intrinsic portion of this device is separated and measured in the device simulator, an f T of 1165 GHz is obtained. The device geometry corresponds to the two-dimensional intrinsic device cutout and contact configuration shown in Figure 4.14.3 and discussed previously. Note that, as before, the full two-dimensional device construction is defined in the process simulator environment, and the cutout is made and contact made to represent the intrinsic device. Vertical scaling was used to increase f T, and realistic fabrication steps were utilized in the process simulator to define the dopant profiles and diffusion. Accompanying the higher f T and reduced transit times are approximately three times higher peak f T current density, three times higher CCB, and 1/3 times RC compared to the previously discussed device. Thus, when considering the intrinsic portion of the device only, we may expect that over 1 THz f T operation may be obtained. Very importantly, we have neglected two very critical elements to the device, which are device reliability and extrinsic parasitics. In the next two sections, we build on the results from this section and describe the impact of these effects on device performance and the challenges to device scaling imposed.

4.14.4 Extrinsic Device RC Delays To gauge the effects of the extrinsic device, we simulate the THz intrinsic device of the last section and add its extrinsic portion, which is similar to the device of the previous section. The impact of the extrinsic device is shown in Figure 4.14.4 (as the more narrow arrows), adjacent to the same analysis of the 350 GHz device. Clearly, the extrinsic device has a greater impact on the THz device than on the lower performance device. The largest impact is on the parasitic RC, where the intrinsic device has a reduced value from the increased doping concentration, and the extrinsic device has not been reengineered to commensurately reduce the extrinsic resistance. Also impacted severely is the CCB parasitic, because the high performance is achieved in part from a reduced vertical spacing between the heavily doped subcollector and the base region of the device. This increases the extrinsic capacitance as well as the intrinsic capacitance. The net result is a more severe reduction in both f T and fMAX, when the extrinsic region is added to the THz intrinsic device. Compared to the parasitic values that would be present in an intrinsic-only device, we again observe that the extrinsic device contributes significantly to the overall parasitics, at an additional 55%, 300%, 525%, and 44% in CBE, CCB, RC, and RB. f T and fMAX comparisons shown in Figure 4.14.4 indicate that values of 1165 and 525 GHz become 798 and 193 GHz, respectively. f T becomes 45% of the 1165 intrinsic device value, and fMAX becomes 24% of its intrinsic device value. With the higher performance, the device operation is more sensitive to the parasitic resistance and capacitance compared to the lower performance intrinsic device. This is a result of the need to reduce all the terms in Equation (4.14.2), and with the reduction in the intrinsic portions, the extrinsic portions become more significant. As scaling of the intrinsic device is critical to achieving higher performance, improvements in the extrinsic device need to be commensurate. Moreover, like the advancements in the intrinsic device follow material and structure advances, so do the advancements in the extrinsic device, but often with a different set of material and structure advances.

© 2006 by Taylor & Francis Group, LLC

The Silicon Heterostructure Handbook

300

1⫻10−1

250 Capacitance (pF/cm2)

1⫻100

1⫻10−2 1⫻10−3 1⫻10−4

200

150

100

FIGURE 4.14.5

17

1⫻10

18

Si

1⫻10

19

1⫻10

20

Ti

Cr

Species

1⫻10

(a)

Ni

0 W

1⫻10−6 AI

50

Cu

1⫻10−5

Ag

Resistivity [ohm-cm]

4.14-578

(b)

300 nm 50 nm 50 nm 50 nm1⫻1016 1⫻1011 1⫻1018 SiO2 air SiO2 Si3N4 Si Structure

Resistance and capacitance of different materials and structures.

Challenges for extrinsic device improvement are found in many places. Resistive parasitics are found in the conducting layers leading to the device. Where the emitter, base, and collector connecting layers into the device are relatively low resistivity at a distance from the device (i.e., the metal interconnect layers) these layers increase in resistivity approaching the intrinsic device (i.e., silicides, then heavily doped semiconductors, and then less heavily doped semiconductors). Shown in Figure 4.14.5(a) are the resistivities of various layers typical in semiconductor devices. The device designers and integration engineers are challenged to choose lower resistance layers and to fabricate them as close as possible to the intrinsic device. This is typically achieved through lithography advances and through self-aligned processes, such as described in an earlier chapter. Other resistive elements that challenge the device engineers are the interfaces. These interfaces are often found between the polysilicon and the single-crystal emitter, between polysilicon and epitaxy base layers, and in work function differences between layers. Reducing the impact of these interfaces involves careful process integration [18–20] or material advances such as silicides with reduced contact resistance [3]. Capacitive parasitics are also reduced. As discussed in the previous section, the intrinsic device design involves performance versus capacitance tradeoffs, both in the emitter and the collector side junctions. Regarding the extrinsic device, shrinking lateral device dimensions, especially related to the active area and the pedestal dimensions, is probably the most significant technical advancement to provide capacitance reduction. However, to approach the intrinsic device performance, the extrinsic capacitive elements need to continue to reduce. The shrinking emitter lateral dimensions make this particularly difficult due to the increased device perimeter to area ratio that results, and because the extrinsic capacitances are scaled with the device perimeter. For instance, the emitter–base perimeter junction and fringing capacitances become ever more significant. In addition, the collector capacitance perimeter becomes more significant, because the polysilicon base contact area does not shrink at the same rate as the emitter dimension. One solution is to employ increasing amounts of (preferably selfaligned) low dielectric constant materials, such as replacing portions of the active area with silicon dioxide or even air or vacuum. Shown in Figure 4.14.5(b) is a comparison of unit capacitances of typical device insulating structures. Typical films are for instance a 300 nm SiO2 for the shallow trench material and thickness. Fifty nanometers is a typical spacer dimension, which can be made of different materials as shown. Note that the choice of different materials may result in significantly different capacitances in the device. New processing techniques and materials will permit incorporation of such improvements.

© 2006 by Taylor & Francis Group, LLC

SiGe HBT Performance Limits

4.14-579

While techniques such as described will take the device toward the intrinsic-only device, there will always be practical limitations to the implementation. For instance, a relatively radical approach to reducing collector resistance and capacitance components has been tried by different groups. This approach, called ‘‘transferred substrate,’’ has been applied with significant performance enhancement in III–V devices [21] and with limited improvement to silicon devices [22]. The intent of this approach is to address the resistive element and the excess capacitance in the collector, because the collector typically needs to be contacted through a large relatively resistive and capacitive region from the bottom of the device. By removing the substrate and providing a contact to the collector from the device bottom, performance advancements may be achieved. However, thermal issues begin to dominate as shown in Ref. [22], and practical solutions would require replacement of the substrate function as a thermal sink.

4.14.5 Practical Limitations Performance capability is not the only concern in understanding the limits. One must also consider avalanche and thermal properties, both may degrade device or circuit performance, and may affect the device reliability. Understanding of these effects has recently been improved with the advent and characterization of devices with f T over 200 GHz [23]. Avalanche current, which is responsible for the device breakdown, or BVCEO and BVCES, is a result of the higher electric fields in the scaled collector–base space–charge region (i.e., reduced WCSCL of Equation (4.14.2)). BVCEO (collector–emitter breakdown with the base terminal open) is often cited as a limit to device biasing voltage. This parameter is now generally below 2 V for devices with f T > 100 GHz, to a value of 1.4 V for the 350 GHz device [14]. However, a typical transistor within a circuit has relatively low impedance connected to the base terminal, such that the breakdown is more closely related to BVCES, which is with the base terminal tied to the emitter. An evaluation of the f T * BVCES product scaling has been performed. This parameter is shown to be collector-doping dependent and significantly greater than the f T * BVCEO product [24]. Reliability in SiGe HBTs appears to be robust to degradation resulting from avalanche current. This contrasts to some III–V devices, which exhibit crystal degradation through carrier recombination and generation. For example, 200 GHz SiGe HBTs have been shown to exhibit increased base current nonideality as a result of operation above BVCEO, yet this degradation is expected to remain negligible for most applications over typical product lifetimes [25]. Furthermore, the avalanche current is expected to continue to increase with increased device performance, yet the voltage causing the same avalanche multiplication factor is found to reduce only a small amount looking to future generations of devices [23]. This indicates that the avalanche will not provide a significant limitation to the performance of the SiGe HBT. Voltage and current limits are also related to device self-heating. We have already discussed this aspect of performance scaling with relation to its impact to performance degradation. However, as with most semiconductor devices and integrated circuits, reliability is impacted with greater temperatures, which can be caused by increased power density in a device [23]. In particular, electromigration in the metal interconnects is highly sensitive to increased temperatures. Unlike in CMOS devices, which have exhibited linear currents in the range of 700 mA/mm, with recent maximum voltages in the range of 1 V, the SiGe HBTs with f T > 100 GHz have called for currents in the range of 1500 mA/mm achieved at voltages in the range of 1.5 V. For small devices, this does not present much of an issue due to their relatively smaller thermal resistance power product, but designs with larger devices require attention to self-heating and robust wiring for reliable operation. Looking ahead, device designers must continue to focus on linear current and thus the power density reduction, through such techniques as dimension reduction. Accordingly, ever-higher current densities are anticipated to be acceptable and reliable with respect to device self-heating. Another issue with respect to higher current densities is the well-established base current degradation accelerated by higher current densities [26–28]. Due to the requirement for higher current densities for

© 2006 by Taylor & Francis Group, LLC

4.14-580

The Silicon Heterostructure Handbook

performance enhancement, these current densities once again challenge the device designer and integration engineers, since they must find materials and processes that decrease base current degradation. Low hydrogen-containing materials have been shown to improve the base current degradation [28], and it has been shown that advanced devices may be fabricated with degradation substantially less than the prior generation devices at similar current densities [23]. New solutions through materials and experimentation must be established to propel the SiGe HBT to continued reliable high performances.

4.14.6

Summary

The industry will continue to demonstrate SiGe HBT performance improvements. In achieving these further advancements, the intrinsic performance improvements will be a relatively straightforward continuation of recent advancements in materials and processes. Techniques made available through CMOS processing will be leveraged for such progress, and ballistic effects will start to be seen in devices with sub-10 nm transit dimensions. The extrinsic portion of the device is perhaps the most challenging, due to the practical availability of construction methods and materials in semiconductor fabrication facilities. Thus, limits are mainly due to practical ability to implement the structures needed for reduced parasitics and thermal conduction within a generalized application technology.

References 1. D Terpstra and WB de Boer. Anomalous collector base leakage in selectively grown SiGe base heterojunction bipolar transistors. Proceedings of the 29th European Solid State Device Research Conference, Leuven, 1999, pp. 720–723. 2. SK Earles, ME Law, J Kevin, S Talwar, and S Corcoran. Nonmelt laser annealing of 5 keV and 1 keV boron implanted silicon. IEEE Transactions on Electron Devices 49:1118–1123, 2002. ¨ ztu¨rk, J Liu, and H Mo. Low resistivity nickel germanosilicide contacts to ultra-shallow 3. MC O Si1xGex source/drain junctions for nanoscale CMOS. Proceedings of the International Electron Devices Meeting, Washington, DC, 2003, pp. 497–500. 4. G Freeman, D Greenberg, K Walter, and S Subbanna. SiGe HBT performance improvements from lateral scaling. Proceedings of the European Solid-State Device Research Conference, Leuven, 1999. 5. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, and S Subbanna. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fMAX) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings of the 2001 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 143–146. 6. B Jagannathan, M Khater, F Pagette, J-S Rieh, D Angell, H Chen, J Florkey, F Golan, D R Greenberg, R Groves, S J Jeng, J Johnson, E Mengistu, K T Schonenberg, C M Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, and S Subbanna. Self-aligned SiGe NPN transistors with 285 GHz fMAX and 207 GHz f T in a manufacturable technology. IEEE Electron Device Letters 23:258–260, 2002. 7. J Bock, H Schafer, H Knapp, D Zoschg, K Aufinger, M Wurzer, S Boguth, R Stengl, R Schreiter, and TF Meister. High-speed SiGe:C bipolar technology. Proceedings of the International Electron Devices Meeting, Washington, DC, 2001, pp. 344–347. 8. K Washio, M Kondo, E Ohue, K Oda, and R Hayami. A 0.2 mm self-aligned SiGe HBT featuring 107-GHz fMAX and 6.7-ps ECL. Proceedings of the International Electron Devices Meeting, Washington, DC, 1999, pp. 557–560. 9. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, H-E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Proceedings of the International Electron Devices Meeting, Washington, DC, 2003, pp. 121–124. 10. P Deixler, R Colclaser, D Bower, N Bell, W De Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, Mv Houdt , JCJ Paasschens , H Veenstra , Evd Heijden, JJTM Donkers, JW Slotboom. QUBiC4G:

© 2006 by Taylor & Francis Group, LLC

SiGe HBT Performance Limits

11.

12.

13. 14.

15. 16. 17. 18.

19.

20. 21.

22.

23. 24.

25.

26.

4.14-581

a f T/fMAX ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar and BiCMOS Circuits and Technology Meeting, 2002, pp. 201–204. S Wada, Y Nonaka, T Saito, T Tominari, K Koyu, K Ikeda, K Sakai, K Sasahara, K Watanabe, H Fujiwara, F Murata, E Ohue, Y Kiyota, H Shimamoto, K Washio, R Takeyari, H Hosoe, and T Hashimoto. A manufacturable 0.18-mm SiGe BiCMOS technology for 40-Gb/s optical communication LSIs. Proceedings of the Bipolar and BiCMOS Circuits and Technology Meeting, 2002, pp. 84–87. J Dunn, DC Ahlgren, DD Coolbaugh, NB Feilchenfeld, G Freeman, DRGreenberg, RA Groves, FJ Guarin, A Joseph, LD Lanzerotti, SA St Onge, BA Orner, J-S Rieh, KJ Stein, S Voldman, P-C Wang, MJ Zierak, S Subbanna, DL Harame, DA Herman Jr, BS Meyerson, and Y Hammad. Foundation of RF CMOS and SiGe BICMOS technologies. IBM Journal of Research and Development 47:101–138, 2003. M Ieong and P Oldigies. Technology modeling for emerging SOI devices. International Conference on Simulation of Semiconductor Processes and Devices, September 2002, pp. 225–230. J-S Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. Proceedings of the International Electron Devices Meeting, 2002, pp. 771–774. M Lundstrom and Z Ren. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans. Electron Devices 49:133–141, 2002. SM Sze. Physics of Semiconductor Devices. John Wiley & Sons, New York, 1981. Y Shi and G Niu. Vertical profile design and transit time analysis of nano-scale SiGe HBTs for terahertz f T. Proceedings Bipolar and BiCMOS Circuits and Technology Meeting, 2004, pp. 213–216. M Kondo, T. Kobayashi, and Y Tamaki. Hetero-emitter-like characteristics of phosphorus doped polysilicon emitter transistors — Part I. Band structure in the polysilicon emitter obtained from electrical measurements. IEEE Transactions on Electron Devices 42:419–426, 1995. S Jouan, R Planche, H Baudry, P Ribot, JA Chroboczek, D Dutartre, D Gloria, M Laurens, P Llinares, M Marty, A Monroy, C Morin, R Pantel, A Perrotin, J de Pontcharro, JL Regolini, G Vincent, and A Chantre. A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices 46:1525–1531, 1999. K Oda, E Ohue, T Onai, and K Washio. Heterojunction Bipolar Transistor. U.S. Patent 5,962,880, October 5, 1999. MJW Rodwell, M Urteaga, T Mathew, D Scott, D Mensa, Q Lee, J Guthrie, Y Betser, SC Martin, RP Smith, S Jaganathan, S Krishnan, SI Long, R Pullela, B Agarwal, U Bhattacharya, L Samoska, and M Dahlstrom. Submicro scaling of HBTs. IEEE Transactions on Electron Devices 48:2606–2624, 2001. LK Nanver, N Nenadovic, V d’Alessandro, H Schellevis, HW van Zeijl, R Dekker, DB de Mooij, V Zieren, and JW Slotboom. A back-wafer contacted silicon-on-glass integrated bipolar process — Part I. The conflict electrical versus thermal isolation. IEEE Transactions on Electron Devices 51: 42–50, 2004. G Freeman, J-S Rieh, Z Yang, and F Guarin. Reliability and performance scaling of very high speed SiGe HBTs. Microelectronics Reliability 44:397–410, 2004. J-S Rieh, B Jagannathan, D Greenberg, G Freeman, and S Subbanna. A doping concentrationdependent upper limit of the breakdown voltage–cutoff frequency product in Si bipolar transistors. Solid-State Electronics 48:339–343, 2004. Z Yang, F Guarin, E Hostetter, and G Freeman. Avalanche current induced hot carrier degradation in 200 GHz SiGe heterojunction bipolar transistors. Proceedings of International Reliablity Physics Symposium, March 2003, pp. 339–343. J-S Rieh, K Watson, F Guarin, Z Yang, P-C Wang, A Joseph, G Freeman, and S Subbanna. Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density. IEEE Transactions on Device and Materials Reliability 3:31–38, 2003.

© 2006 by Taylor & Francis Group, LLC

4.14-582

The Silicon Heterostructure Handbook

27. MS Carroll, A Neugroschel, and C-T Sah. Degradation of silicon bipolar junction transistors at high forward current densities. IEEE Transactions on Electron Devices 44:110–117, 1997. 28. K Hoffmann, G Bruegmann, and M Seck. Impact of inter-metal dielectric on the reliability of SiGe NPN HBTs after high temperature electrical operation. IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, April 2003, pp. 126–129.

© 2006 by Taylor & Francis Group, LLC

5 Heterostructure FETs 5.1

Overview: Heterostructure FETs J.D. Cressler........................................................ 5.1-585

5.2

Biaxial Strained Si CMOS K. Rim ........................................................................... 5.2-587 Introduction . Mobility Characteristics . Deep Submicron Strained Si MOSFETs . Device Physics and Design Issues . Material and Integration Issues . Summary

5.3

Uniaxial Stressed Si MOSFET S.E. Thompson........................................................ 5.3-601 Introduction . Uniaxial Strained Silicon . Electrical Properties: Uniaxial versus Biaxial Stressed Silicon . Summary

5.4

SiGe-channel HFETs S. Banerjee .............................................................................. 5.4-615 Introduction . Bandstructure and Transport . Buried Si1 xGex Channel pHFETs with Si Cap . Strain-Compensated Si1 x yGexCy Buried-Channel pMOSFET . Surface-Channel Si and Si1 xGex/High-k pHFETs . n-Channel Devices for CMOS . Vertical HFETs . Summary

5.5

Industry Examples at the-State-of-the-Art: Intel’s 90 nm Logic Technologies S.E. Thompson .......................................................................... 5.5-629 Introduction . 90 nm Strained Silicon Technology . Future Direction of Strained Silicon . Summary

5.1-583 © 2006 by Taylor & Francis Group, LLC

5.1 Overview: Heterostructure FETs

John D. Cressler Georgia Institute of Technology

Ironically, despite the fact that SiGe HBTs at present dominate the commercial silicon heterostructure world, the first Si-based heterostructure field effect transistor was demonstrated in 1986, predating the first SiGe HBT by over 1 year. These earliest FETs were Schottky-gated, III–V-like n- and p-channel modulation doped devices, which rapidly gave rise to a variety SiGe-based MOSFET topologies. More recently, the field has centered on strained Si MOSFETs, because of its better compatibility with mainstream CMOS, and the impressive mobility enhancements that can be realized in that system at aggressively scaled gate lengths. Two fundamentally different ways of producing strained Si CMOS exist, utilizing both biaxial and uniaxial strain techniques. In Chapter 5.2, K. Rim of IBM Research discusses ‘‘Biaxial Strained Si CMOS,’’ while in Chapter 5.3, by S. Thompson of the University of Florida gives an overview of ‘‘Uniaxial Strained Si CMOS.’’ More conventional SiGe-channel FETs, of various flavors, are presented in Chapter 5.4, ‘‘SiGe-Channel HFETs,’’ by S. Banerjee of the University of Texas at Austin. Finally, in Chapter 5.5, ‘‘Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies,’’ by S. Thompson of the University of Florida, an overview of the world’s first commercially available strained Si CMOS technology is presented. In addition to this substantial collection of material, and the numerous references contained in each chapter, a number of review articles and books detailing the operation and modeling of SiGe and strained Si FETs exist, including Refs. [1–8].

References 1. R People. Physics and applications of GexSi1 x/Si strained layer heterostructures. IEEE Journal of Quantum Electronics 22:1696–1710, 1986. 2. B Meyerson. UHV/CVD growth of Si and SiGe alloys: Chemistry, physics, and device applications. Proceedings of the IEEE 80:1592–1608, 1992. 3. U Ko¨nig and H Daembkes. SiGe HBTs and HFETs. Solid-State Electronics 38:1595–1602, 1995. 4. CK Maiti, LK Bera, and S Chattopadhyay. Strained-Si heterostructure field-effect transistors. Semiconductor Science and Technology 13:1225–1246, 1998. 5. U Ko¨nig, M Gluck, and G Hock. Si/SiGe field-effect transistors. Journal of Vacuum Science and Technology B 16:2609–1614, 1998. 6. CK Maiti and GA Armstrong. Applications of Silicon–Germanium Heterostructure Devices. London: Institute of Physics Publishing, 2001.

5.1-585 © 2006 by Taylor & Francis Group, LLC

5.1-586

The Silicon Heterostructure Handbook

7. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. London: The Institution of Electrical Engineers, 2001. 8. JL Hoyt, HM Nayfeh, S Eguchi, I Aber, G Xia, T Drake, EA Fitzgerald, and DA Antoniadis. Strained silicon MOSFET technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 23–26.

© 2006 by Taylor & Francis Group, LLC

5.2 Biaxial Strained Si CMOS

Kern (Ken) Rim IBM Thomas J. Watson Research Center

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6

Introduction............................................................... 5.2-587 Mobility Characteristics............................................ 5.2-588 Deep Submicron Strained Si MOSFETs .................. 5.2-592 Device Physics and Design Issues ............................ 5.2-595 Material and Integration Issues................................ 5.2-596 Summary .................................................................... 5.2-597

5.2.1 Introduction Scaling of Si CMOS devices has fueled the exponential growth in the electronics industry. Along with continued increase in density of integration (e.g., number of devices per area), CMOS scaling has also enabled circuit speed enhancements at the rate of 1.2 times per year or higher. CMOS logic circuit speed is determined by the current drive of MOSFETs and the load capacitance, and is often described by a simple expression for circuit delay, t ¼ CL(V/I), where CL is the load capacitance, V the voltage swing, and I the MOSFET current drive. The load capacitance has been reduced by miniaturization of device dimension and innovations such as silicon-on-insulator (SOI), while the intrinsic current drive capability of a MOSFET is determined by the channel carrier density and carrier velocity. As the channel length has scaled to the deep submicron regime, impact of channel length scaling on the carrier velocity and current drive has diminished, and the industry has heavily relied on the increase of gate capacitance, which is achieved through aggressive reduction of gate oxide thickness, in order to maximize the channel carrier density and MOSFET current drive. However, gate oxide scaling has recently neared the physical limit where the direct tunneling leakage current is now a major component of the total leakage in a transistor. The current drive of MOSFET can also be enhanced by modifying the carrier transport properties of silicon. Current drive enhancement obtained by such material property change is in addition to that induced by the geometric scaling of CMOS, and can be combined with the advantage obtained by continued scaling of CMOS. For applications where power consumption is a concern, the current drive increase can be traded off to reduce the standby leakage current by allowing higher threshold voltage VT while maintaining equivalent current drive. Alternatively, the enhancement can be traded off to control active power consumption by enabling lower supply voltage VDD [1]. Strain is an effective mechanism to modify the carrier transport properties of silicon. Strained Si/SiGe MOSFETs take advantage of strain-induced changes of carrier transport in silicon and obtain current drive enhancements [2]. Figure 5.2.1(a) illustrates the structure of MOSFETs fabricated on strained Si on relaxed SiGe. When a thin layer of Si is pseudomorphically grown on a thick, relaxed SiGe layer (Figure 5.2.1(b)), the lattice mismatch leads to biaxial tensile strain in the Si layer. If the SiGe layer is fully relaxed and the Si layer fully strained (i.e., the in-plane lattice constants of Si conform to those of the underlying relaxed SiGe layer), the amount of strain in Si is approximately (4.2x)% where x is the Ge 5.2-587 © 2006 by Taylor & Francis Group, LLC

5.2-588

The Silicon Heterostructure Handbook

High mobility strained Si Electron/hole channel

Relaxed SiGe

Gate oxide

Relaxed SiGe

Graded SiGe buffer (a) n-FET

Si substrate

p-FET

Strained Si

Relaxed Si1−x Gex (b) Tensile-strained Si on Si1−x Gex

FIGURE 5.2.1 heterolayers.

Typical structures of (a) strained Si–relaxed SiGe bulk MOSFETs and (b) strained Si–relaxed SiGe

mole fraction in the SiGe layer. So, for instance, a pseudomorphic Si layer grown on fully relaxed SiGe with 25% [Ge] would be under 1% biaxial tensile strain. In a strained Si MOSFET, a surface channel is formed at the oxide–Si interface. This is in contrast to a buried channel structure formed in a SiGe/Si/SiGe FET [3, 4], or a SiGe surface channel in a SiGe MOSFET where gate oxide is formed on SiGe [5]. Compared to the buried channel or the SiGe surface channel alternatives, strained Si surface channel MOSFETs have the following advantages: a single epi layer can potentially enhance both electron and hole mobilities, the surface channel structure leads to better scaling behavior in deep submicron channel lengths, and advanced gate oxides can be thermally grown on pure Si as opposed to on SiGe. Obtaining high-quality oxide interface through thermal oxidation of SiGe is difficult. As can be seen in Figure 5.2.1, the essential structure and operation principle of a strained Si/SiGe MOSFET is identical to typical Si MOSFETs, except that the inversion channel is formed in the thin Si layer under biaxial tension, and much of the MOSFET body and source– drain junctions are located within the underlying SiGe layer.

5.2.2 Mobility Characteristics Theoretical calculations [6–11] have predicted electron and hole mobility enhancements in strained Si. In the conduction band of silicon (Figure 5.2.2(a)), biaxial tensile strain splits the six-fold degeneracy in the D-valleys, and lowers the two-fold degenerate perpendicular D-valleys with respect to the four-fold in-plane D-valleys in energy space. Such energy splitting suppresses intervalley carrier scattering between the two-fold and four-fold degenerate valleys, and causes preferential occupation of the two-fold valleys

© 2006 by Taylor & Francis Group, LLC

5.2-589

Biaxial Strained Si CMOS

Bulk Si

Strained Si

D 2 valleys

D4 D6

EC

ml

∆E ≅ 67 D2

meV 10%Ge

mt

ml D 4 valleys

mt

mt Bulk Si

Strained Si

E

k

HH

∆E ≅ 38

E Out-ofplane

In-plane

G

mt < ml

meV

k

10%Ge

LH Spin−orbit

FIGURE 5.2.2 In-plane biaxial tension-induced changes in (a) conduction and (b) valence bands in strained Si.

where the in-plane conduction mass is lower. These two effects combine and lead to increased electron mobility in strained Si. Similarly, strain splits the valence band degeneracy (Figure 5.2.2(b)) between the heavy and light hole bands (HH and LH) at the G-point and shifts the spin–orbit band. The resulting band deformation effectively lowers the in-plane conduction mass, and the splitting suppresses interband scattering between the two bands, improving the in-plane hole mobility. Observation of high electron mobility in two-dimensional electron gas formed in strained Si was reported in late 1980s and early 1990s [12, 13]. Application of strained Si in MOSFET channel was proposed by Keyes as early as in 1986 [14], and the first demonstration of strained Si MOSFET was reported by Welser et al. using relaxed SiGe graded buffer [15, 16]. Electron mobility measured in NFET is plotted against vertical effective field in Figure 5.2.3 [17]. Effective inversion mobility is extracted using I–V and split C–V measurements on long-channel MOSFETs, and effective field is calculated by counting depletion and inversion charges as described in Ref. [18]. Amount of strain increases with the Ge mole fraction in the relaxed SiGe layer increases, and strained Si NFET mobility is enhanced by as much as 110% over the mobility of the unstrained control device. Even with the modest amount of strain (0.5% strain, 13% [Ge]), over 50% electron mobility enhancement is observed. Figure 5.2.4 [17] shows the typical PFET mobility characteristics as a function of tensile strain. Similar PFET mobility behaviors have been reported by various publications [19–21]. Compared to electron mobility, the amount of hole mobility enhancement is modest, and shows a strong vertical effective field dependence. Figure 5.2.5 compares the strain dependence of electron and hole mobilities in strained Si MOSFETs. With 1% strain, NFET mobility is enhanced by more than two times. On the other hand, hole mobility is slightly degraded with small strain before it begins to increase at larger amounts of strain. Both electron and hole mobility characteristics exhibit interesting deviations from the theoretical predictions. For electrons in NFETs, quantum mechanical confinements in the inversion layer result in D2D4 energy splitting even in unstrained Si devices. Strong strain dependence of electron mobility suggests that the intervalley phonon scattering has a strong influence on the mobility of electron inversion layer [7], and the additional energy splitting caused by strain further reduces the intervalley

© 2006 by Taylor & Francis Group, LLC

5.2-590

The Silicon Heterostructure Handbook

1000 Strained Si / Relaxed SiGe 28% Strained Si / Relaxed SiGe 13% Effective electron mobility (cm/V*sec)

Strained Si / Strained SiGe 30% / Relaxed SiGe 13% 800

600

400

110% 200 Control Universal mobility 0 0.0

500.0 k 1.0 M Effective field, Eeff (V/cm)

1.5 M

FIGURE 5.2.3 Effective electron inversion mobility versus vertical effective field as a function of strain in strained Si NMOSFETs. (From K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. With permission.) 140 Control Universal mobility

Effective hole mobility (cm/V*sec)

120

100

80

60

40

Strained Si / Relaxed SiGe 35% Strained Si / Relaxed SiGe 28%

20

Strained Si / Relaxed SiGe 13% Strained Si / Strained. SiGe 30% / Relaxed SiGe 13%

0 200.0 k

400.0 k

600.0 k

800.0 k

1.0 M

1.2 M

Effective field, Eeff (V/cm)

FIGURE 5.2.4 Effective hole inversion mobility versus vertical effective field as a function of strain in strained Si NMOSFETs. (From K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. With permission.)

© 2006 by Taylor & Francis Group, LLC

5.2-591

Biaxial Strained Si CMOS

Strain = (a SiGe−a Si)/a Si (%) 0.0

0.5

1.0

1.5

2.0

500 2.0 400

1.5 300

N inv = 1⫻1013 cm−2

200

0

10 20 30 40 Equivalent [Ge] in fully relaxed SiGe (%)

Mobility enhancement factor

Effective electron mobility (cm2/V*sec)

2.5

1.0

50

Strain = (a SiGe−a Si)/a Si (%) 0.0

0.5

1.0

1.5

2.0

1.4 80 1.2 70 1.0

60

50

13

N inv = 1⫻10

cm−2

Mobility enhancement factor

Effective hole mobility (cm2/V*sec)

90

0.8

40 0

10 20 30 40 Equivalent [Ge] in fully relaxed SiGe (%)

50

FIGURE 5.2.5 Strain-dependence of electron and hole inversion mobility in strained SiMOSFETs.

scattering. On the other hand, surface scattering, which dominates MOSFET mobility at high vertical fields, is expected to be similar in strained and unstrained Si devices, and so the observed strong electron mobility enhancement even at high vertical field is an unexpected trend in this regard. Strain-dependence of hole mobility can also be described by the interplay of energy splittings induced by strain and confinement effects. Quantum-mechanical confinement in the hole inversion layer splits the HH–LH band degeneracy, but in the opposite direction compared to the splitting induced by tensile strain, moving the HH-associated band toward the midgap. As tensile strain increases in a strained Si PFET, strain-induced changes in LH and HH bands first compensate the confinement-induced splitting

© 2006 by Taylor & Francis Group, LLC

5.2-592

The Silicon Heterostructure Handbook

and degrade hole mobility, and eventually reverse the band-splitting direction and increase the amount of splitting and mobility [22]. Smaller mobility enhancement observed in high vertical fields can also be explained by this mechanism — at high vertical fields, the confinement is stronger, and strain-induced splitting needs to overcome larger initial confinement-induced splitting.

5.2.3 Deep Submicron Strained Si MOSFETs Various groups have reported demonstration of sub-100 nm channel length MOSFETs on strained Si– relaxed SiGe heterostructures [23–27, for example]. Figure 5.2.6 shows the TEM micrograph of a strained Si MOSFET [17] with cobalt silicide formed on selective epi raised source drain. In most of the reported cases, relaxed SiGe layer is created by a graded buffer technique [13, 28] where SiGe is epitaxially grown on Si wafer and Ge content is graded up slowly over the thickness of several microns. Such graded buffer structure is known to reduce dislocation defect density in the top layer by orders of magnitude in comparison to a thick layer of SiGe directly grown on Si without grading. Strained Si channel layer with thickness of 10 to 20 nm is epitaxially grown on SiGe before modified CMOS process steps are used to fabricate MOSFETs. Figure 5.2.7 shows a typical NFET IonIoff characteristics comparison for devices with channel lengths as short as 50 nm [17]. For a moderate amount of strain (13% [Ge]), NFET Ion is enhanced by 15% to 20% at a given off current Ioff over that of the unstrained Si counterpart. Similar characteristics were obtained by other reports. As described in the previous section, enhancement of PFET mobility requires larger amount of strain than enhancement of NFET mobility. Figure 5.2.8 shows the comparison of PFET IonIoff characteristics between unstrained Si and strained Si devices with 28% [Ge] (i.e., 1.2% strain). About 7% to 10% enhancement is observed in strained Si PFETs. At lower strain, minimal or no performance gain is observed as expected from strained dependence of hole mobility. In both NFET and PFETs, the electrostatic design of the strained Si device is very similar to the conventional Si MOSFETs. So with careful design that takes into account some of the issues that are described in the following sections, short channel effects that are equivalent to the unstrained Si devices can be obtained in strained Si MOSFETs.

Co salicide formed on raised S/D

Strained Si Channel Relaxed SiGe

FIGURE 5.2.6 TEM micrograph of strained Si MOSFET with selective epi raised source–drain structure. (From K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. With permission.)

© 2006 by Taylor & Francis Group, LLC

5.2-593

Biaxial Strained Si CMOS

1⫻10−6 Strained Si/SiGe (13% [Ge])

I off (A/µm)

1⫻10−7

Control

1⫻10−8

1⫻10−9

1⫻10−10

1⫻10−11

400.0 µ

600.0 µ I on (A/µm)

800.0 µ

FIGURE 5.2.7 Ion–Ioff comparison between strained Si and unstrained Si NFETs. (From K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. With permission.) 1⫻10−6

I off (A/µm)

1⫻10−7

1⫻10−8

1⫻10−9 Strained Si/SiGe (28% [Ge]) Control 1⫻10−10

200.0 µ

400.0 µ

600.0 µ

I on (A/µm)

FIGURE 5.2.8 Ion–Ioff comparison between strained Si and unstrained Si PFETs. (From K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. With permission.)

© 2006 by Taylor & Francis Group, LLC

5.2-594

The Silicon Heterostructure Handbook

Strained Si-relaxed SiGe heterostructures can be formed on a layer of insulator. Such structures, which are called SiGe-on-insulator (SGOI), combine the enhanced carrier transport in strained Si with the advantages of SOI MOSFETs. One major difference between SGOI devices and bulk strained Si devices on graded buffer is that the SiGe layer in SGOI needs to be significantly thinner (a few thousand angstroms or less). Figure 5.2.9 describes the various techniques to create SGOI structures. By transferring a layer of relaxed SiGe from buffer, bonded SGOI (BSGOI) can be formed [21, 29]. This approach utilizes the well-established SiGe buffer technique to create relaxed SiGe to supply layers to transfer, but is expected to be costly as it combines epitaxial process with wafer bonding. A variation of the SIMOX process can be applied to SiGe layers to achieve a potentially economic method of forming SGOI [20], but Ge out-diffusion into the silicon substrate can be difficult to control during the hightemperature oxidation step to form buried oxide, and the quality of buried oxide formed in SiGe is a concern. A bilayer approach that addresses these concerns has been proposed [30]. Finally, the Ge condensation or mixing technique [31] utilizes Ge diffusion and rejection during high-temperature

Handle wafer

Handle wafer

Oxide

Oxide

Oxide SiGe

(a)

Strained Si Epi Relaxed SiGe buffer

Relaxed SiGe buffer Si substrate

Si substrate (1) Bonding

(2) SmartCut or grinding back

(3) Strained Si layer epi growth

O+ Strained Si Epi

Relaxed SiGe buffer

Oxide Relaxed SiGe buffer

Oxide Relaxed SiGe buffer

Si substrate

Si substrate

Si substrate

(1) Oxygen implant

(2) SIMOX anneal

(3) Strained Si layer epi growth

Oxide

(b)

Strained SiGe (c)

SOI

Relaxed SiGe

Strained Si Epi Relaxed SiGe

Oxide

Oxide

Oxide

Si substrate

Si substrate

Si substrate

(1) Strained SiGe epi on SOI

(2) Relaxation and Ge condensation by dry oxidation

(3) Oxide strip and strained Si epi

FIGURE 5.2.9 Various techniques to fabricate SiGe-on-insulator (SGOI). (From K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, J Chu, K Jenkins, T Kanarsky, S Koester, B Lee, K Lee, V Mazzeo, A Mocuta, D Mocuta, PM Mooney, P Oldiges, J Ott, P Ronsheim, R Roy, A Steegen, M Yang, H Zhu, M Ieong, and H-SP Wong. Solid-State Electronics 47:1133–1139, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

5.2-595

Biaxial Strained Si CMOS

+

H2 Thermal + Deposited oxide Strained Si SiGe

Handle wafer Handle wafer Oxide Strained Si

Strained Si Buried Oxide FIGURE 5.2.10 Fabrication of strained-Si directly on insulator (SSDOI) by layer transfer and selective etch of SiGe. (From K Rim, K Chan, L Shi, D Boyd, J Ott, N Klymko, F Cardone, L Tai, S Koester, M Cobb, D Canaperi, B To, E Duch, I Babich, R Carruthers, P Saunders, G Walker, Y Zhang, M Steen, and M Ieong. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 49–52. With permission.)

oxidation to form ultrathin SGOI. This is a very promising approach, but the mechanism that governs the relaxation of SiGe lattice is not well understood at this point. Sub-100 nm MOSFETs have been demonstrated on SGOI substrates fabricated using thermal mixing technique [32], which is similar to the Ge condensation technique. Excellent MOSFET characteristics and NFET current drive enhancement have been reported. The extreme case of ultrathin SGOI is strained Si directly on insulator (SSDOI) [29, 33, 34]. Tensile strained Si layer can be directly formed on buried oxide by a combination of layer transfer and selective etch removal of relaxed SiGe (Figure 5.2.10). Retention of strain and electron and hole mobility enhancements have been demonstrated on SSDOI MOSFETs [34].

5.2.4 Device Physics and Design Issues In order to realize the strain-enhanced CMOS performance to the fullest extent in ULSI applications, both fundamental and technological challenges need to be addressed. As discussed above, biaxial tension-induced hole mobility enhancement requires large amounts of strain (i.e., [Ge]), and the amount of enhancement diminishes at high vertical field, consistent with the theoretical calculation in Ref. [10]. High strain and high Ge content increase the difficulty of various process integration issues, and due to the small hole mobility enhancement at high vertical fields, strained Si is expected to provide

© 2006 by Taylor & Francis Group, LLC

5.2-596

The Silicon Heterostructure Handbook

only limited enhancement in the future bulk and PDSOI PFETs with high channel doping and vertical field. On the other hand, for device structures such as symmetric double gate or FDSOI pMOSFETs in which the vertical field is inherently low during operation, strained Si can provide a significant hole mobility enhancement. Recent experimental results [35] suggest that a significant hole mobility enhancement at high vertical field might be possible with an optimized epi layer preparation technique, but further investigation is needed for verification. The electron mobility of strained Si FET, on the other hand, exhibits unexpectedly large enhancements even at high vertical fields as described in the previous section. Presently, few theoretical explanations have been proposed to account for this observation. Although low field mobility is a property that can be measured and compared with relatively little ambiguity and is an essential parameter for device and circuit modeling, it is inadequate in quantitatively predicting the actual saturation current drive of the deep submicron devices. Velocity saturation effect strongly influences device characteristics in short channel lengths, and the observed impact by the changes in low field mobility is limited. Modern day NFETs operate at roughly 50% of the ballistic limit, and so only about half of the impact observed in low field mobility is observed in saturation current [36]. In addition, accurately extracting the intrinsic enhancement in device performance is difficult because short-channel FET characteristics are sensitive functions of many device design parameters such as the junction- and channel-doping profiles as well as the extrinsic resistance. Even so, strain-induced energy splitting may influence the transport of ‘‘warm’’ carriers in addition to the low-field mobility, improving saturation current in short-channel devices [1]. Smaller density of states in strained Si should contribute to the reduction of scattering rates even at carrier energies several times larger than kT, contributing to enhanced nonequilibrium transport and deep submicron NMOSFET current drive. In order to maximize the impact of strain-induced enhancement of intrinsic device performance, device scaling and design have to be achieved without compromise to the optimization of the parasitics in the extrinsic parts of device. This point is illustrated with a simple estimation of expected enhancements in the device on-resistance RON (which is inversely proportional to the drain current in the linear region) and the saturation transconductance gm,sat [37]. For instance, assuming RON ¼ 300 V mm for the control device and parasitic resistance Rext ¼ 200 V mm for both the control and SS devices, a 70% increase in mobility will be diluted to provide only 16% improvement in RON. Similarly, assuming gm,sat ¼ 1000 mS/mm for the control device, Rext of 200 V mm (equally divided between source and drain) dilutes a 30% enhancement in intrinsic gm to 26% even in a simplified (neglecting the impact of a finite drain conductance in saturation) and optimistic estimation. Due to the low thermal conductivity of the thick SiGe layer, the SS MOSFETs exhibit significant selfheating [38], analogous that observed in SOI MOSFETs. In typical CMOS digital logic circuits, device duty cycle is expected to be much shorter than the thermal time constant of self-heating. However, in analog applications, self-heating will in effect induce a significant rise in device operation temperature, affecting the performance. Techniques to reduce the SiGe layer thickness in the structure can improve the self-heating characteristics. Band offsets at the Si/SiGe interface that lower the conduction band edge in strained Si, along with the narrower energy gap in SiGe, lower VT of strained Si NFETs. VT lowering can be close to 100 mV in strained Si NFETs on SiGe with 20% [Ge]. Additional well and halo doping can offset the VT lowering, but the extra doping can diminish the mobility gain [39].

5.2.5 Material and Integration Issues The foremost critical challenge in the SS CMOS technology is the control of dislocation defects in the epitaxial layers. A finite density of misfit and threading dislocations are present in the SiGe buffers grown by the graded buffer growth techniques. Such dislocations can cause increase in junction leakage and device OFF current Ioff (as in Refs. [25, 26]). For ULSI implementation, innovations and optimizations are required to minimize the propagation of dislocations in strained Si-relaxed SiGe structures.

© 2006 by Taylor & Francis Group, LLC

Biaxial Strained Si CMOS

5.2-597

Thermal processing during CMOS fabrication steps can cause relaxation of the strain in the Si layer, or out-diffusion of Ge. In thermal stability experiments [40], where Raman spectroscopy was used to measure the changes in strained Si-relaxed SiGe structure before and after annealing steps, the position of the strained Si peak did not shift distinctly, while the signal strength decreased with increasing amounts of thermal annealing. This indicated that while thermal annealing at 10008C does not cause measurable strain relaxation, it effectively reduces the Si thickness by Ge out-diffusion. The thermal budget during device fabrication has to be optimized carefully to avoid strain relaxation and Ge outdiffusion into the channel layer. Optimal thickness of strained Si channel for a given amount of strain needs to be thick enough to allow such process window against Si consumption and Ge out-diffusion, and thin enough to prevent random nucleation and propagation of dislocation defects. In addition, geometric effects and interaction with process-related stress have to be understood and controlled. Understanding in this area is very limited at this time. Doping diffusion in SiGe affects device design. While the well-known suppression of boron diffusion in SiGe is beneficial to the formation of abrupt junction in strained Si PFETs, arsenic diffusion in SiGe is significantly enhanced in comparison to that in Si [23, 41]. In device design to control short-channel effects, such difference must be taken into account for the proper design of junction depth, overlap capacitance, and VT. SiGe also interacts with silicide formation. For the cobalt salicide process, Ge hinders transition to the low-resistivity disilicide phase. When a typical cobalt silicide process is used on SiGe, a rough cobalt germano-silicide film can result with ten times higher sheet resistance. Alternative material or integration schemes, such as raised source drain as in Figure 5.2.3 [17], are required to achieve acceptable salicide properties.

5.2.6 Summary Strained Si MOSFET is a case example of how Si–SiGe heterostructure can make direct and significant impact on today’s Si device technology, following the success of SiGe HBTs. Significant challenges remain before the realization of a manufacturable strained Si CMOS technology, but the potential of geometric scaling-independent performance enhancement provides a strong motivation. One interesting application is a combination of strained Si and high-k dielectrics. Strain can be used to recover the mobility degraded in devices with high-k dielectrics [42, 43], combining the advantage of strained Si with gate leakage reduction in high-k gate dielectrics. As CMOS scaling continues on, such material innovations that can complement geometric scaling and enable performance boost will play an increasingly important role in Si technology.

References 1. K Rim, JL Hoyt, and JF Gibbons. Fabrication and analysis of deep submicron strained Si n MOSFETs. IEEE Transactions on Electron Devices 47: 1406–1413, 1998. 2. JL Hoyt, HM Nayfeh, S Eguchi, I Aberg, G Xia, T Drake, EA Fitzgerald, and DA Antoniadis. Strained Si MOSFET technology. Technical Digest IEEE International Electron Devices Meeting, San Francisco, CA, 2002, pp. 23–26. 3. K Ismail. Si/SiGe high speed field effect transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 1995, pp. 509–512. 4. VP Kesan, S Subbana, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, and JA Ott. High performance 0.25 mm p-MOSFETs with silicon–germanium channels for 300 K and 77 K operation. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 1991, pp. 977–980. 5. T Tezuka, N Sugiyama, T Mizuno, and S Takagi. Novel fully-depleted SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 1991, pp. 946–948. 6. MV Fischetti and SE Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. Journal of Applied Physics 80:2234–2252, 1994.

© 2006 by Taylor & Francis Group, LLC

5.2-598

The Silicon Heterostructure Handbook

7. S Takagi, JL Hoyt, JJ Welser, and JF Gibbons. Comparative study of phonon limited mobility of two dimensional electrons in strained and unstrained Si metal oxide semiconductor field effect transistors. Journal of Applied Physics 80:1567–1577, 1994. 8. JB Roldan, F Gamiz, JA Lopez-Villanueva, and JE Carceller. A Monte Carlo study on the electron transport properties of high performance strained Si on relaxed SiGe channel MOSFETs. Journal of Applied Physics 80:5121–5128, 1994. 9. GF Formicone, D Vasileska, and DK Ferry. Transport in the surface channel of strained Si on a relaxed Si1xGex substrate. Solid State Electronics 41:879–885, 1997. 10. R Oberhuber, G Zandler, and P Vogl. Subband structure and mobility of two dimensional holes in strained Si/SiGe MOSFET’s. Physical Review B 58:9941–9948, 1998. 11. D Nayak, JCW Woo, JS Park, L Wang, and KP MacWilliams. High-mobility p-channel metal-oxidesemiconductor field-effect transistor on strained Si. Applied Physics Letters 62:2853–2855, 1993. 12. SF Nelson, K Ismail, JO Chu, and BS Meyerson. Room-temperature electron mobility in strained Si/SiGe heterostructures. Applied Physics Letters 18:435–437, 1997. 13. EA Fitzgerald, YH Xie, D Monroe, PJ Silverman, JM Kuo, AR Kortan, FA Thiel, and BE Weir. Relaxed GeSi structures for III–V integration with Si and high mobility two-dimensional electron gases in Si. Journal of Vacuum Science & Technology B 10:1807, 1992. 14. RW Keyes. High-mobility FET in strained silicon. IEEE Transactions on Electron Devices 33:863, 1986. 15. J Welser, JL Hoyt, and JF Gibbons. NMOS and PMOS transistors fabricated in strained silicon/ relaxed silicon–germanium structures. Technical Digest IEEE International Electron Devices Meeting, San Francisco, CA, 1992, pp. 1000–1002. 16. J Welser, JL Hoyt, S Takagi, and JF Gibbons. Strain dependence of the performance enhancement in strained-Si n-MOSFETs. Technical Digest IEEE International Electron Devices Meeting, San Francisco, CA, 1994, pp. 947–950. 17. K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, R Roy, J Newbury, J Ott, K Petrarca, P Mooney, D Lacey, S Koester, K Chan, D Boyd, M Ieong, and H-S Wong. Characteristics and device design of sub-100 nm strained Si N- and pMOSFETs. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 98–99. 18. S Takagi, A Toriumi, M Iwase, and H Tango. On the universality of inversion layer mobility in Si MOSFETs: Part I — Effects of substrate impurity concentration. IEEE Transactions on Electron Devices 41:2357–2362, 1994. 19. K Rim, J Welser, JL Hoyt, and JF Gibbons. Enhanced hole mobilities in surface channel strained Si p MOSFETs. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 1995, pp. 517–520. 20. T Mizuno, S Takagi, N Sugiyama, J Koga, T Tezuka, K Usuda, T Hatakeyama, A Kurobe, and A Toriumi. High performance strained Si p MOSFETs on SiGe on insulator substrates fabricated by SIMOX technology. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 1999, pp. 934–937. 21. LJ Huang, JO Chu, S Goma, CP D’Emic, SJ Koester, DF Canaperi, PM Mooney, SA Cordes, JL Speidell, RM Anderson, and H-S P Wong. Carrier mobility enhancement in strained Si on insulator fabricated by wafer bonding. Digest Symposium on VLSI Technology, Kyoto, Japan, 2001, pp. 57–58. 22. K Rim, K Chan, L Shi, D Boyd, J Ott, N Klymko, F Cardone, L Tai, S Koester, M Cobb, D Canaperi, B To, E Duch, I Babich, R Carruthers, P Saunders, G Walker, Y Zhang, M Steen, and M Ieong. Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 49–52. 23. K Rim, JL Hoyt, and JF Gibbons. Transconductance enhancement in deep submicron strained Si nMOSFETs. Technical Digest IEEE International Electron Devices Meeting, San Francisco, CA, 1998, pp. 707–710.

© 2006 by Taylor & Francis Group, LLC

Biaxial Strained Si CMOS

5.2-599

24. K Rim, S Koester, M Hargrove, JO Chu, PM Mooney, J Ott, T Kanarsky, P Ronsheim, M Ieong, A Grill, and H-SP Wong, Strained Si NMOSFETs for high performance CMOS technology. Digest of Symposium on VLSI Technology, Kyoto, Japan, 2001, pp. 59–60. 25. Q Xiang, J-S Goo, J Pan, B Yu, S Ahmed, J Zhang, and M-R Lin. Strained silicon NMOS with nickel– silicide metal gate. Digest of Technical Papers — Symposium on VLSI Technology, Kyoto, Japan, 2003, pp. 101–102. 26. HC-H Wang, Y-P Wang, S-J Chen, C-H Ge, SM Ting, J-Y Kung, R-L Hwang, C-K Chiu, LC Sheu, P-Y Tsai, L-G Yao, S-C Chen, H-J Tao, Y-C Yeo, W-C Lee, and C Hu. Substrate-strained silicon technology: process integration. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 61–64. 27. T Sanuki, A Oishi, Y Morimasa, S Aota, T Kinoshita, R Hasumi, T Takegawa, K Isobe, H Yoshimura, M Iwai, K Sunouchi, and T Noguchi. Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 65–68. 28. FK LeGoues, BS Meyerson, JF Morar, and PD Kirchner. Mechanism and conditions for anomalous strain relaxation in graded thin films and superlattices. Journal of Applied Physics 71:4230–4243, 1992. 29. K Rim, L Shi, K Chan, J Chu, D Boyd, K Jenkins, J Ott, D Lacey, P Mooney, M Cobb, N Klymko, F Jamin, S Koester, and T Kanarsky. Strained Si MOSFETs on bulk and SiGe-on-insulator (SGOI) substrates. Program and Abstracts of First International SiGe Technology and Device Meeting (ISTDM 2003), Nagoya, Japan, 2003, pp. 9–10. 30. T Mizuno, N Sugiyama, T Tezuka, and S Takagi. Novel SOI p-channel MOSFETs with higher strain in Si channel using double SiGe heterostructures IEEE Transactions on Electron Devices 49:7–14, 2002. 31. T Tezuka, N Sugiyama, T Mizuno, M Suzuki, and S Takagi. A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub 100 nm strained silicon on insulator MOSFETs. Japanese Journal of Applied Physics 40:2866–2875, 2001. 32. BH Lee, A Mocuta, S Bedell, H Chen, D Sadana, K Rim, P O’Neil, R Mo, K Chan, C Cabral, C Lavoie, D Mocuta, A Chakravarti, RM Mitchell, J Mezzapelle, F Jamin, M Sendelbach, H Kermel, M Gribelyuk, A Domenicucci, KA Jenkins, S Narasimha, SH Ku, M Ieong, IY Yang, E Leobandung, P Agnello, W Haensch, and J Welser. Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2002, pp. 946–948. 33. TA Langdo, A Lochtefeld, MT Currie, R Hammond, VK Yang, JA Carlin, CJ Vineis, G Braithwaite, H Badawi, MT Bulsara, and EA Fitzgerald. Preparation of novel SiGe-free strained Si on insulator substrates. IEEE International SOI Conference, 2002 , pp. 211–212. 34. TS Drake, N Chleirigh, ML Lee, AJ Pitera, EA Fitzgerald, DA Antoniadis, DH Anjum, JL Hoyt, DH Anjum, J Li, R Rull, N Klymko, and JL Hoyt. Fabrication of ultra-thin strained silicon on insulator. Journal of Electronic Materials 32:972–975, 2003. 35. N Sugii, D Hisamoto, K Washio, N Yokoyama, and S Kimura. Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 737–740. 36. DA Antoniadis. MOSFET scalability limits and ‘‘new frontier’’ devices. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 2–5. 37. K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, J Chu, K Jenkins, T Kanarsky, S Koester, B Lee, K Lee, V Mazzeo, A Mocuta, D Mocuta, PM Mooney, P Oldiges, J Ott, P Ronsheim, R Roy, A Steegen, M Yang, H Zhu, M Ieong, and H-SP Wong. Strained Si CMOS (SS CMOS) technology: opportunities and challenges. Solid-State Electronics 47:1133–1139, 2003. 38. KA Jenkins and K Rim. Measurement of the effect of self-heating in strained-silicon MOSFETs. IEEE Electron Device Letters 23:360–362, 2002. 39. HM Nayfeh, C Leitz, A Pitera, EA Fitzgerald, JL Hoyt, and DA Antoniadis. Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs. IEEE Electron Device Letters 24:248–250, 2003.

© 2006 by Taylor & Francis Group, LLC

5.2-600

The Silicon Heterostructure Handbook

40. SJ Koester, K Rim, JO Chu, PM Mooney, JA Ott, and MA Hargrove. Effect of thermal processing on strain relaxation and interdiffusion in Si/SiGe heterostructures studied using Raman spectroscopy. Applied Physics Letters 79:2148–2150, 2001. 41. S Eguchi, JL Hoyt, CW Leitz, and EA Fitzgerald. Comparison of arsenic and phosphorus diffusion behavior in silicon-germanium alloys. Applied Physics Letters 80:1743, 2002. 42. K Rim, EP Gusev, C D’Emic, T Kanarsky, H Chen, K Chu, J Ott, K Chan, D Boyd, V Mazzeo, BH Lee, A Mocuta, J Welser, SL Cohen, M Ieong, and H-S Wong. Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectrics. Digest of Symposium on VLSI Technology, Honolulu, HI, 2002, pp. 12–13. 43. S Datta, G Dewey, M Doczy, BS Doyle, B Jin, J Kavalieros, R Kotlyar, M Metz, N Zelick, and R Chau. High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack. Technical Digest — IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 653–656.

© 2006 by Taylor & Francis Group, LLC

5.3 Uniaxial Stressed Si MOSFET 5.3.1 5.3.2 5.3.3

Strain-Induced Hole Mobility Enhancement versus Vertical Electric Field . Hole Mobility Enhancement at Low Strain . Strain-Induced n-Channel MOSFET Threshold Voltage Shift

Scott E. Thompson University of Florida

Introduction............................................................... 5.3-601 Uniaxial Strained Silicon .......................................... 5.3-602 Electrical Properties: Uniaxial versus Biaxial Stressed Silicon.............................................. 5.3-603

5.3.4

Summary .................................................................... 5.3-610

5.3.1 Introduction Over the past 40 years [1–7], to improve MOSFET performance, strain introduced via biaxial tensile stress using a Si–SiGe heterostructure has received substantial attention. Little attention, however, has been paid to uniaxial stress created via heterostructures [8]. Both biaxial and uniaxial stress offer large enhanced electron and hole mobility and great potential to continue Moore’s law when conventional scaling slows. Since biaxial tensile stress introduces advantageous strain for both n- and p-type MOSFETs, it has potential importance to CMOS logic technologies. However, biaxial stress has not yet been adopted into high-volume manufacturing due to cost and integration complexity. The use of uniaxial stress for CMOS logic is not without its own complexities, as will be described in Chapter 5.5, but has been adopted at the 90 nm technology generation [8–10] including heteroepitaxy introduced for the first time in commercial CMOS chips. This chapter summarizes and quantitatively explains some advantageous electrical characteristics for uniaxial (as compared to biaxial) in-plane stressed MOSFETs fabricated on conventional (0 0 1) wafers. These advantages originate because of (i) favorable uniaxial stress-induced valence band warping and (ii) the often unrecognized benefit of straining both the gate and Si channel with process strain versus just the Si channel with wafer substrate strain. Using the Luttinger–Kohn [11, 12] and Bir–Pikus [13, 14] strain Hamiltonian, and Herring and Vogt deformation potential theory [15], three key advantages observed in the uniaxial stress experimental data are explained: large hole mobility enhancement at low stress and high vertical electric field and a small n-channel threshold voltage shift. The hole mobility enhancement is experimentally observed to reduce to near zero at high vertical fields for biaxial stress but is maintained for uniaxial stress. Band curvature calculations show this can be explained by the relative magnitude of the out-of-plane light and heavy hole conductivity effective masses. For biaxial stress, smaller light than heavy hole mass reduces the strain-induced band splitting at high vertical field (lattice strain is ‘‘canceled’’ by surface confinement band splitting [16]). For uniaxial strain, the larger out-of-plane light than heavy hole mass increases the band splitting at high vertical fields (strain and surface confinement splitting is ‘‘additive’’). Second, the technologically important question of why uniaxial stress hole mobility enhancement is present at low strain (and not present for 5.3-601 © 2006 by Taylor & Francis Group, LLC

5.3-602

The Silicon Heterostructure Handbook

biaxial) is shown to result from more favorable band warping. In-plane effective mass calculations show that the light hole mass is 50% smaller for uniaxial than biaxial stress. Finally, for biaxial stress, the undesirably large n-channel threshold voltage shift [2, 17, 18] is shown to be due to two effects. The first effect is differences in the gate and Si channel electron affinity. The difference arises since uniaxial process strain is present in both the nþ poly-Si gate and Si channel while biaxial stress introduced via the substrate only strains the Si channel. The second effect is strain-induced bandgap narrowing [19], which is larger for biaxial than uniaxial tensile stress. This chapter is organized as follows: Section 5.3.2 briefly covers how uniaxial stress is created in the CMOS transistor structure. Section 5.3.3 quantifies the key electrical differences for uniaxial versus biaxial stress. Chapter 5.5 describes the industry examples for uniaxial stressed Si in nanoscale CMOS logic technologies.

5.3.2 Uniaxial Strained Silicon There are several ways to introduce uniaxial stress into the Si lattice: a tensile or compressive capping layer over the device [20, 21], high-stress shallow-trench isolation fill [22], or heteroepitaxy in the source and drain of nanoscale transistors [1, 6–10, 23]. Heteroepitaxy offers the greatest potential due to the ability to create large strain. A schematic diagram of heteroepitaxy is shown in Figure 5.3.1 for the recently proposed uniaxial stress (a) and conventional biaxial stress (b) [8–10] device structures. For the case shown in Figure 5.3.1(a), Si1XGeX in the source–drain creates uniaxial compressive stress in the silicon channel in the direction of current flow. Alternately, Si1Y CY in the source and drain would create tensile stress in the silicon channel. The mismatch strain is given by «mismatch ¼

asub afilm afilm

(5:3:1)

where asub and afilm are the lattice constants of the substrate and heteroepitaxy film, respectively the stress in the layer is given by so ¼ 2g

nþ1 «mismatch n1

(5:3:2)

where g is the shear modulus of elasticity and n is Poisson’s ratio. A key technology question is how much strain can be introduced into the silicon channel by heteroepitaxy in the source and drain. Direct physical measurement of the side-induced uniaxial channel stress is difficult since the strain depends on channel length and is only present in the small nanoscale devices. At present, three-dimensional finite element simulations are the best-known method for

Si1−y Gey

Si

Si1−x Cx

N or P-channel

P-channel Si1−xGex

Si σ

Si

(a) Uniaxial stress

Si1−xGex

σ σ

(b) Biaxial stress

FIGURE 5.3.1 Device structures for uniaxial and biaxial stress.

© 2006 by Taylor & Francis Group, LLC

Classic papers: Fitzgerald (1991), Welser (1994), Rim (1998), Hoyt (2002)

5.3-603

Uniaxial Stressed Si MOSFET

quantifying the channel stress in small devices. Using FLOOPs [24, 25] three-dimensional finite element analysis, for Si0.83Ge0.17 on a Si substrate [8–10], 1.4 GPa of compressive stress is introduced into the Si0.83Ge0.17 layer. This creates 500 MPa of uniaxial compressive stress in the 45-nm gate length MOSFET channel [26]. A TEM micrograph of a 45-nm p-channel MOSFET is shown in Figure 5.3.2, which will be described in Chapter 5.5 [10].

5.3.3 Electrical Properties: Uniaxial versus Biaxial Stressed Silicon To understand the electrical differences between uniaxial and biaxial stressed Si MOSFETs, it is required to formulate how strain changes the position and shape of the energy bands. The classic papers on this subject can be found in the references [11–15, 27–31]. The topic of strain on electronic states is broad so this discussion will be restricted to the technologically important biaxial and uniaxial stressed Si MOSFETs on (0 0 1) wafers and h1 1 0i channel orientation (the dominant orientation used by the microelectronics industry). Figure 5.3.3 lists the key properties for one and two axis stresses. As a note, stress and strain are often confused. Stress is the force per unit area. Strain is the resulting deformation of the lattice. For uniaxial tensile stress, strain is present in all three directions (see Figure 5.3.3), with the sideways contraction (direction perpendicular to the stress) given by Poisson’s ratio (n). For a good review of these concepts, see Ref. [32]. Due to space considerations, derivations for most statements cannot be given but are cited in references. The change in electronic states due to strain starts with a strain Hamiltonian proposed by Luttinger– Kohn [11, 12] and Bir–Pikus [13, 14]. To evaluate the strain Hamiltonian, the strain tensor is equivalently decomposed into three matrices («ij ¼ «ijtrace þ «ijshear100 þ «ijshear111): a diagonal hydrostatic strain matrix with trace Tr(e) ¼ «x þ «y þ «z which is identical to the fractional change of the volume, dV/V ¼ «x þ «y þ «z, and two traceless matrices that represent shear strain created by stress along h1 0 0i and h1 1 1i, respectively:

«trace ij

2 « þ «yy þ «zz 1 4 xx 0 ¼ 3 0

0 «xx þ «yy þ «zz 0

Type of Stress Uniaxial

45nm Biaxial

Si1−xGex

Principal Stresses s1 = −Ee1 s2 = 0 s3 = 0

e3 = − ne1

s1 =

Thompson, Elec. Dev. Lett. 1994.

FIGURE 5.3.2 TEM micrograph of 45 nm transistors with uniaxial stress.

© 2006 by Taylor & Francis Group, LLC

s3 = 0

FIGURE 5.3.3

e1 =

E(e1+ne2) 2

e1 =

2

e2 =

1−n E(e2+ne1) 1−n

(5:3:3)

Principal Strain s1 E e2 = − ne1

s2 =

p-type

3 0 5 0 «xx þ «yy þ «zz

e3 =

DV/V (Silicon) e = e1 (1−2n)e1 0.44e1

s1−us2

e = e1 = e2

E s2−us1

2(1−2n)

E −us1−us2 E

Relationships for uniaxial and biaxial stress.

1−n 1.22e

e

5.3-604

The Silicon Heterostructure Handbook

«shear100 þ «shear111 ij ij

2 3 2« («yy þ «zz ) 0 0 1 4 xx 5 0 2«yy («zz þ «xx ) 0 ¼ 3 0 0 2«zz («xx þ «yy ) 2 3 0 «xy «xz þ 4 «xy 0 «yz 5 «xz «yz 0

(5:3:4)

This decomposition simplifies the evaluation of the Hamiltonian. The effect of hydrostatic and shear strains on the electronic states is different [33]. From simple symmetry arguments, hydrostatic strain maintains the same symmetry, therefore, only shifts the energy position of the bands (changes the bandgap and electron affinity but does not split the degeneracy). Shear strain removes symmetry, and thus, splits degenerate states in the conduction and valence bands. Also, as pointed out by Herring and Vogt in 1955 [15] and still valid today [31], the experimental error in determining the hydrostatic energy shifts is large while the error in determining the shear splitting is small. Deformation potential theory (first proposed by Bardeen and Shockley [34] and then modified for indirect many-valley semiconductors (Si,Ge) by Herring and Vogt [15]) expresses the conduction band edge shifts and splitting as a function of strain. For the valence band, Pikus and Bir developed analytical expressions for energy levels and effective mass near k ¼ 0 using perturbation theory and the strain Hamiltonian [13, 14]. The band edge shifts are given by Ehh ; Elh ¼ a(«x þ «y þ «z ) DEc ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 («x «z )2 þ d 2 «2xy

(5:3:5)

D2 ¼ (J d þ J u =3)(«x þ «y þ «z ) þ (2=3)J u («z «x ) D4 ¼ (J d þ J u =3)(«x þ «y þ «z ) (1=3)J u («z «x )

(5:3:6) (5:3:7)

where Ehh, Elh, D2, D4 are the heavy and light hole valence bands and two-fold and four-fold conduction band edge states, and the relationship «x ¼ «y 6¼ «z is used for simplification. The terms Jd þ (1/3)Ju in Equation (5.3.6) and Equation (5.3.7) (called E1 by Bardeen and Shockley [34]) and a are the hydrostatic deformation potentials for the conduction and valence bands, respectively. Ju, b, and d (needed for h1 1 0i stress since «xy is nonzero) are shear deformation potentials. As seen from Equation (5.3.5) to Equation (5.3.7), the hydrostatic term shifts while the shear term splits the valence and conduction band states. It is the shear term that modulates conductivity and mobility. The shear deformation potentials are well known with good accuracy from piezoresistance measurements (J u ¼ 9.16, b ¼ 2.35, and d ¼ 5.0) [15]. The hydrostatic deformation potential affects important electronic properties such as energy gap and electron affinity. However, the hydrostatic deformation cannot be directly measured and a very wide range of values from 2 to 10.7 have been reported [31]. Some optical experimental techniques can directly measure differences in the conduction and valence band deformation potential, which reduces the uncertainty for strain-induced bandgap narrowing. However, at present, there is still large uncertainty in the electron affinity of strained Si. This uncertainty (as will be shown in section ‘‘Strain-induced n-Channel MOSFET Threshold Voltage Shift’’) makes it difficult to calculate the threshold voltage shift for biaxial strained Si MOSFETs. The shape of the energy bands determines the effective mass. Neglecting spin–orbit coupling, analytical expression for in-plane and out-of-plane effective mass is given by Hensel and Feher [28] and Chao and Chuang [27] at k ¼ 0, m*hh,? 1 ¼ , g1 2g 2 m0

© 2006 by Taylor & Francis Group, LLC

m*lh,? 1 ¼ , g1 þ 2g2 m0

m*hh,k m0

¼

1 , g1 þ g2

m*lh,k m0

¼

1 g1 g2

(5:3:8)

5.3-605

Uniaxial Stressed Si MOSFET

where g1 and g2 are material band parameters in the Kohn–Luttinger strain Hamiltonian. The above results are for biaxial stress but similar results are obtained by Hensel and Feher for uniaxial stress along h1 1 0i (by swapping k with ? in Equation (5.3.8) and replacing the A, B, and C band parameters with the Kohn–Luttinger parameters [28]). Including spin–orbit coupling, Chao and Chuang [27] have derived expressions at k ¼ 0. As a note of caution, the effective mass at k ¼ 0 should only be used as a guide. The valence band is not a parabolic function of k, hence the effective mass is not constant. The effective mass can be determined at higher k by diagonalizing the 6 6 strain Hamiltonian. Within this band shift and effective mass description, we now review the current understanding of uniaxial and biaxial stress on MOSFETs.

Strain-Induced Hole Mobility Enhancement versus Vertical Electric Field One of the biggest differences for biaxial tensile and uniaxial compressive stressed p-channel MOSFETs is the field dependence of the mobility enhancement. The hole mobility enhancement at large vertical fields is important in nanoscale CMOS since aggressive gate oxide scaling has dramatically increased the oxide field to about 5 MV/cm and silicon inversion effective vertical field (EEFF) to greater than 1 MV/cm [35]. For uniaxial stress introduced by Si1xGex in the source and drain, the hole mobility for a 45 nm gate length transistor increases 50% as shown in Figure 5.3.4 [8]. An important observation in Figure 5.3.4 is that the uniaxial stress hole mobility enhancement is present at large vertical fields unlike that of biaxial stress [8, 26]. This important feature will now be discussed in more detail. Figure 5.3.5 summarizes what is known about the hole band structure for unstrained and strained Si. The valence bands are plotted in the in-plane direction of the MOSFET channel [36]. For the unstrained lattice, the valence bands are degenerate and are the primary reason for the low bulk hole mobility. The unstrained valence band structure consists of a degenerate heavy hole and light hole band at k ¼ 0 and a slightly offset spin–orbit split-off band. The large valence band degeneracy is undesirable and creates an opportunity for larger hole than electron mobility enhancement [7]. An important factor in the field dependence of the mobility is how the stress-induced light to heavy hole band separation changes with surface confinement (triangular surface potential setup by the MOSFET vertical field). Uniaxial compressive and biaxial tensile stress cause a similar magnitude separation in the light to heavy hole band at k ¼ 0 as calculated from Equation (5.3.5) to Equation (5.3.7) [37]. Hole mobility enhancement can result when additional holes populate the ‘‘light hole like’’ band [13, 14, 16, 38] since it potentially has lower conductivity effective mass. However, the situation, as will be shown in the next section, is more complex due to band warping.

Mobility/cm2/V sec)

140

Thompson (2002) (Uniaxial)

Rim et al. (1995)

120 100 80

Universal hole mobility

60

Rim et al. (2002) biaxial

40 0

0.2

0.4

0.8 0.6 Eeff/(MV/cm)

1

1.2

FIGURE 5.3.4 Enhanced hole mobility versus vertical electric field for uniaxial and biaxial stress.

© 2006 by Taylor & Francis Group, LLC

5.3-606

The Silicon Heterostructure Handbook

Longitudinal in-plane direction

E Heavy holes

Light holes like

E

k Light holes

∆ LH-HH k <110>

Split-off holes (b) Stressed (biaxial tensile or uniaxial compression)

(a) Unstrained

FIGURE 5.3.5 Simplified hole valence band structure for longitudinal in-plane directions: (a) unstrained and (b) strained Si.

For biaxial tensile stress, the reduction in hole mobility enhancement with vertical electric field is caused by surface confinement [16]. Fischetti showed numerically that the strain-induced separation between the light and heavy hole bands decreases at high vertical field. The reduced splitting can be understood from the difference in the light and heavy hole out-of-plane effective mass (Equation (5.3.8)). The out-of-plane mass along with surface confinement shifts the energy levels as shown by Stern [39] and qualitatively in Figure 5.3.6. The energy level shift for the light and heavy hole bands can be approximated by Ej ¼

2hqEs 3 2=3 pﬃﬃﬃﬃﬃﬃﬃﬃ j þ , 4 4 2mz

j ¼ 0, 1, 2, . . .

(5:3:9)

where E s is the vertical electric field in the silicon. The important observation from Equation (5.3.9) is a band with a low out-of-plane effective mass (m?) will shift and become depopulated with increasing vertical field. Biaxial stress is known to have a low out-of-plane effective mass for the light hole band [31, 40]. Thus, the biaxial strain-induced band splitting (DLH–HH in Figure 5.3.5) will decrease (‘‘be canceled’’) with vertical field. The physical origin for the favorable uniaxial stress mobility enhancement at high field results from the same mechanism [41]. For uniaxial stress, due to favorable band warping, the surface confinement increases the band splitting. This can be quantified by solving for the out-of-plane conductivity mass using the Hensel–Feher formulation [28, 42] and band parameters extracted from cyclotron resonance data [28, 42]. The results show that the out-of-plane light hole mass is larger than the heavy hole mass (opposite to the biaxial case). The out-of-plane effective masses are quantitatively shown in Figure 5.3.6 near k ¼ 0 along with a qualitative energy versus k plot. Thus for uniaxial strain, the out-of-plane mass relation mlh > mhh increases the splitting and further populates the light hole band, which helps maintain the high vertical field mobility enhancement. Finally, not all biaxial stress shows the loss of high-field hole mobility enhancement, as is the case with biaxial compressive stress [16]. This result can be understood from Equation (5.3.5) since compressive strain removes the valence band degeneracy by shifting the heavy hole band to higher energy (as opposed to light hole). Since holes already primarily populate the heavy hole band, the vertical electric field does not cause a light to heavy hole repopulation due to surface confinement. However, biaxial compressive stress is less interesting since the maximum hole mobility enhancement is less [16].

© 2006 by Taylor & Francis Group, LLC

5.3-607

Uniaxial Stressed Si MOSFET

Out-of-plane direction(z) E

E

Heavy holes

E

mIh < mhh

Ih k Light holes

Ih

mIh < mhh

mIh = 0.20m0

mIh = 0.26m0

mhh = 0.28m0

mhh = 0.21m0

Split-off holes (a) Unstrained

(b) Biaxial strain

E0(Ih) E0(hh)

Ej = V(z)

(c) Uniaxial strain

2hqEs 4 2mz

3 (j + -) 2/3 4

FIGURE 5.3.6 Simplified hole valence band structure for out-of-plane directions: (a) unstrained and (b) biaxial strained Si, and (c) uniaxial strained Si.

Hole Mobility Enhancement at Low Strain The next important question is why biaxial tensile versus uniaxial compressive stress hole mobility enhancement is different at low strain. At low strain, biaxial stress shows little if any mobility enhancement [2] versus large uniaxial stress-induced mobility improvement [8]. Band warping is again responsible for this effect. Band warping leads to more favorable curvature [37] and population in k space [41] for uniaxial than biaxial stress. In the low-strain region, the well-studied piezoresistance effect in Si can be used to determine how bands warp and repopulate with strain. Piezoresistance coefficients are valid for strain less than approximately 250 to 500 MPa, where the piezoresistance varies linearly with strain. Yamada et al. found the nonlinearity in the piezoresistance to be small (1% for longitudinal compression) up to 250 MPa [43]. For this discussion, we assume industry standard Si wafers with (0 0 1) surface and wafer notch on the [1 1 0] axis. The effect of mechanical stress on the mobility can then be expressed as follows: Dm p k Tk þ p ? T? m

(5:3:10)

where the subscripts k and ? refer to the directions parallel and transverse to the current flow in the plane of the MOSFETs. Tk and T? are the longitudinal and transverse stresses, and pk and p? are the piezoresistance coefficients expressed in Pa1. The pk and p? can be expressed in terms of the three fundamental cubic piezoresistance coefficients p11, p12, and p44. For the case of the technologically important (0 0 1) wafer, the longitudinal and transverse piezoresistance coefficients for the standard layouts are given in Figure 5.3.7. For simplicity, we use the bulk values for p11, p12, and p44 first measured 50 years ago by Smith [44], though technically piezoresistance coefficients should take into account the two-dimensional nature of transport in the MOSFET and depend on temperature, gate voltage, and doping [45, 46]. Using the bulk coefficients, pk and p? are calculated in Figure 5.3.7 and the following can be concluded. Both biaxial tensile and uniaxial compressive stress split and repopulate the light and heavy hole bands by similar amounts [37]. However, the enhanced mobility as calculated from Equation (5.3.10) and plotted in Figure 5.3.8 shows large differences for biaxial versus uniaxial stress. For biaxial stress,

© 2006 by Taylor & Francis Group, LLC

5.3-608

The Silicon Heterostructure Handbook

<100> πII

Polarity

<110>

πI −

πII

πI −

N or P

π11

π12

(π11+π12+π44)/2

(π11+π12−π44)/2

N-type

−102

53.4

−31.6

−17.6

P-type

6.6

−1.1

71.8

−66.3

Biaxial stress

Uniaxial stress

FIGURE 5.3.7 Longitudinal and transverse piezoresistance coefficients evaluated for standard layout and wafer orientation (units of 1012 dyn1).

40 <110> channel orientation (001 surface)

35

% Hole ∆m /m

30 Uniaxial longitudinal compressive

25 20

Uniaxial transverse tensile

15 10

Compressive stress <100> (Biaxial in plane tension)

5 0

~ 12.5% Ge Rim (2002, 2003)

−5 0

200 400 s /stress MPa

600

FIGURE 5.3.8 Mobility versus stress calculated from the piezoresistance coefficients.

the negligible mobility improvement in the low-strain regime results from the low p12 coefficients 1.1 (compared to 71.8 1012 cm2 dyn1 for uniaxial stress). The results in Figure 5.3.8 can be understood by realizing how biaxial and uniaxial stresses warp the bands causing changes in the in-plane conductivity mass. The strain-altered in-plane effective masses are calculated from the Luttinger–Kohn and Bir–Pikus 6 6 strain Hamiltonian for the p3/2 [27]. The results for biaxial and uniaxial stress near k ¼ 0 are summarized in Figure 5.3.9. In Figure 5.3.9, the uniaxial stress-altered light hole in-plane conductivity mass is 50% smaller than for biaxial stress [37]. In summary, similar to the out-of-plane effective mass, biaxial stress band warping causes less desirable in-plane mass. For biaxial stress, the ‘‘light’’ hole mass is actually slightly larger than the heavy hole mass. Thus, repopulation creates a slight negative resistance which is in good agreement with the slight negative piezoresistance coefficient and the biaxial MOSFET data at low Ge concentration (see Figure 5.3.8 and Ref. [2]). Biaxial stress can enhance the hole mobility at high Ge concentration and strain since large band splitting reduces interband scattering [16]. However, high strain is more difficult to integrate since it requires additional reduction to the midsection thermal cycles to avoid strain relaxation.

Strain-Induced n-Channel MOSFET Threshold Voltage Shift Biaxial and uniaxial stress-enhanced electron mobility is better understood and results from conductivity effective mass improvement due to increased electron concentration in the D2 valleys (Equation (5.3.6)) and reduced intervalley scattering [47]. However, less attention has been paid to strain-induced

© 2006 by Taylor & Francis Group, LLC

5.3-609

Uniaxial Stressed Si MOSFET

Unstrained

Strained

z [001]

(near k = 0) (a) Biaxial (tension)

y [010] Heavy holes

(b) Uniaxial (compression)

[110] x [100] 0.26m0

E

0.15m0

K <110> 0.52m0 0.21m0 Light holes

FIGURE 5.3.9 Effective mass calculated from the Luttinger–Kohn and Bir–Pikus 6 6 strain Hamiltonian to illustrate quantitatively how uniaxial compressive and biaxial tensile stress alter the valence band structure.

threshold voltage shifts. Recent literature [2, 17–19] suggests that large threshold voltage shifts occur for biaxial stressed n-channel MOSFETs, while much smaller shifts are observed for uniaxial tensile stress [8, 10, 26]. Large threshold voltage shifts are undesirable for high-performance logic transistors since it increases off-state leakage or if retargeted by increasing the well doping degrades mobility and subthreshold slope [19]. There is some confusion over the exact origin of the threshold voltage shift but changes in the electron affinity and strain-induced bandgap narrowing are key contributors [48]. These two effects can be quantified using Equation (5.3.5) to Equation (5.3.7) following an approach used by Van de Walle and Martin [49, 50] and People [30] for biaxial stressed heterostructures. Figure 5.3.10 plots the conduction and valence band edge versus strain for longitudinal uniaxial and biaxial tensile stress. For simplicity, a MOSFET with h1 0 0i channel orientation is chosen but the results are similar for h1 1 0i devices. The strain-induced bandgap narrowing is 3 less for uniaxial stress (see Figure 5.3.10). In the bandgap narrowing calculations, it is necessary to include spin–orbit coupling [51], which causes the light hole band shift to be approximately twice as large as the heavy hole shift. The conduction band edge shift also gives the change in the electron affinity, which is simply the shift in the D2 valleys. The decrease in D2 valleys produces a large negative (lower) threshold voltage shift directly proportional to the shift in D2 [48] (providing no electron affinity change in the gate which is the case for biaxial stress). Using the range of reported hydrostatic deformation potential, 2 to 10.7 eV, and Equation (5.3.6), approximately 100 to 400 mV threshold voltage shifts occur for 1% biaxial strain, respectively, which negatively affects performance. As a final note in this uniaxial versus biaxial comparison, longitudinal uniaxial tensile stress is chosen since this type of stress is widely adopted in 90-nm logic technologies [8, 26] (as will be discussed in Chapter 5.5). Since the implementation of uniaxial stress with a capping layer also strains the nþ gate, the electron affinity change has no effect on the threshold voltage. Thus, the threshold voltage shift for uniaxial stress is smaller and dominated by bandgap narrowing, which is also smaller compare to biaxial stress. However, the significantly less bandgap narrowing for uniaxial tensile stress in the n-channel MOSFET comes at a price since it results from the heavy hole band shifting up. This is undesirable for

© 2006 by Taylor & Francis Group, LLC

5.3-610

The Silicon Heterostructure Handbook

1.4

Band edge / (eV)

1.2 1.0 Biaxial

0.8 0.6

Uniaxial

Bandgap

0.4 LH band

0.2 0.0

HH band

−0.2 0

FIGURE 5.3.10

0.005

0.01 Strain e

0.015

0.02

Conduction and valence bands shifts and bandgap narrowing due to uniaxial and biaxial strain.

hole transport; p-channel MOSFETs would be significantly degraded if nothing was changed to compensate for the tensile stress in the p-channel transistor.

5.3.4 Summary Both biaxial and uniaxial stress provide significant enhanced mobility to improve MOSFET performance. Using the strain Hamiltonian, equations are given for the conduction and valence band edge shifts, which explain the differences observed in biaxial and uniaxial stressed nanoscale MOSFETs. The key advantage for biaxial stress is that both hole and electron mobilities can be enhanced for the same strain. The key advantages of uniaxial stress are larger hole mobility enhancement at low strain, mobility enhancement at high vertical electric field, and less n-channel threshold voltage shift due to less bandgap narrowing and the nþ gate also strained.

Acknowledgments The author would like to thank the efforts of his former colleagues in the Portland Technology Development, Technology Computer Aided Design, and in the Corporate Quality and Reliability Groups of Intel. The author also acknowledges the support and encouragement from Mark Bohr, Robert Chau, and William Holt and many helpful discussions with Professor C.T. Sah, Philippe Matagne, Borna Obradovic, Lucian Shifren, Toshi Nishida, and Kehuey Wu.

References 1. K. Rim, S. Koester, M. Hargrove, J. Chu, P. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, H.- S.P. Wong. Strained Si NMOSFETs for high performance CMOS technology. Symp. VLSI Tech. Dig., Kyoto, Japan, 2001, pp. 59–60. 2. K. Rim, J. Chu, H. Chen, K.A Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney; D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong and H.-S Wong. Characteristics and device design of sub-100 nm strained Si n- and p-MOSFETs. Symp. VLSI Tech. Dig., Hawaii, 2002, pp. 98–99. 3. K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong. Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp. 49–52.

© 2006 by Taylor & Francis Group, LLC

Uniaxial Stressed Si MOSFET

5.3-611

4. K. Rim, J. Welser, J.L. Hoyt, and J.F. Gibbons. Enhanced hole mobilities in surface-channel strainedSi p-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 517–520. 5. C.W. Leitz, M.T. Currie, M.L. Lee, C. Zhi-Yuan, D.A. Antoniadis, and E.A. Fitzgerald. Channel engineering of SiGe-based heterostructures for high mobility MOSFETs. Materials Issues in Novel Si-Based Technology. Symposium (Materials Research Society Symposium Proceedings, Vol. 686), 2002, pp. 113–118. 6. M.L. Lee, C.W. Leitz, C. Zhiyuan, A.J. Pitera, G. Taraschi, D.A. Antoniadis, and E.A. Fitzgerald. Strained Ge channel p-type MOSFETs fabricated on Si1xGex/Si virtual substrates. Materials Issues in Novel Si-Based Technology. Symposium (Materials Research Society Symposium Proceedings, Vol. 686), 2002, pp. 39–43. 7. J.L. Hoyt, H.M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E.A. Fitzgerald, and D.A. Antoniadis. Strained silicon MOSFET technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 23–26. 8. S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Zhiyong Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr and Y. El-Mansy. A logic nanotechnology featuring strained silicon. IEEE Electron Dev. Lett. 25, 191–193, 2004. 9. S. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber and M. Bohr. A 90 nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1mm2 SRAM cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64. 10. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson and M. Bohr. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp. 978–980. 11. J.M. Luttinger. Quantum theory of cyclotron resonance in semiconductors: general theory. Phys. Rev. 102, 1030–1041, 1956. 12. J.M. Luttinger and W. Kohn. Motion of electrons and holes in perturbed periodic fields. Phys. Rev. 97, 869–883, 1955. 13. G.E. Pikus and G.L. Bir. Effect of deformation on the energy spectrum and the electrical properties of imperfect germanium and silicon. Sov. Phys. Solid-State 1, 136–138, 1959. 14. G.E. Pikus and G.L. Bir. Cyclotron and paramagnetic resonance in strained crystals. Phys. Rev. Lett. 6, 103–105, 1961. 15. C. Herring and E. Vogt. Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering. Phys. Rev. 101, 944–961, 1956. 16. M.V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim. Six-band k. p calculation of the hole mobility in silicon inversion layers: dependence on surface orientation, strain, and silicon thickness. J. Appl. Phys. 94, 1079–1095, 2003. 17. J. Goo, X. Qi, Y. Takamura, F. Arasnia, E.N. Paton, P. Besser, J. Pan, and L. Ming-Ren. Band offset induced threshold variation in strained-Si nMOSFETs. IEEE Electron Dev. Lett. 24, 568–570, 2003. 18. J. Goo, Qi Xiang, Y. Takamura, Haihong Wang, J. Pan, F. Arasnia, E. N. Paton, P. Besser, M. V. Sidorov, E. Adem, A. Lochtefeld, G. Braithwaite, M. T. Currie, R. Hammond, M. T. Bulsara and Ming-Ren Lin. Scalability of strained-Si nMOSFETs down to 25nm gate length. IEEE Electron Dev. Lett. 24, 351–353, 2003.

© 2006 by Taylor & Francis Group, LLC

5.3-612

The Silicon Heterostructure Handbook

19. J.G. Fossum and W. Zhang. Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels. IEEE Trans. Electron Dev. 50, 1042–1048, 2003. 20. A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato and F. Ootsuka. Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2001, pp. 433–436. 21. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh and T. Horiuchi. Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2000, pp. 247–250. 22. H. Cheng-Liang, H. Soleimani, G. Grula, N.D. Arora, and D. Antoniadis. Isolation process dependence of channel mobility in thin-film SOI devices. IEEE Electron Dev. Lett. 17, 291–293, 1996. 23. C.K. Maiti, L.K. Bera, S.S. Dey, D.K. Nayak, and N.B. Chakrabarti. Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field. Solid-State Electron. 41, 1863–1869, 1997. 24. M.E. Law and S.M. Cea. Continuum based modeling of silicon integrated circuit processing: an object oriented approach. Comput. Mater. Sci. 12, 289–308, 1998. 25. S. Cea and M. Law. Multidimensional nonlinear viscoelastic oxidation modeling. Simulation of Semiconductor Devices and Processes, H. Ryssel and P. Pichler, Eds., Erlangen, Germany, Vol. 6, 1995, pp. 139–142. 26. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, k. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, R. Shaheed, L. Shifren, S. Sivakumar, B. Tuffs, S. Tyagi, M. Bohr and Y. El-Mansy, ‘‘A 90 nm logic technology featuring strained silicon,’’ IEEE Trans. Elec. Devices, vol. 51, pp. 1790–1797, 2004. 27. C.Y.-P. Chao and S.L. Chuang, Spin-orbit-coupling effects on the valence-band structure of strained semiconductor quantum wells. Phys. Rev. B 46, 4110–4122, 1992. 28. J.C. Hensel and G. Feher. Valence band parameters in silicon from cyclotron resonances in crystals subjected to uniaxial stress. Phys. Rev. Lett. 5, 307–309, 1960. 29. F. Herman. The electronic energy band structure of silicon and germanium. Proc. IRE 40, 1703– 1732, 1955. 30. R. People. Indirect band gap of coherently strained GexSi1x bulk alloys on (0 0 1) silicon substrates. Phys. Rev. B: Cond. Matter 32, 1405–1408, 1985. 31. M.V. Fischetti and S.E. Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys. 80, 2234–2252, 1996. 32. W.A. Brantley. Calculated elastic constants for stress problems associated with semiconductor devices. J. Appl. Phys. 44, 534–535, 1973. 33. C.-T. Sah. Fundamentals of Solid-State Electronics and Fundamentals of Solid-State Electronics, World Scientific Publishing, 1995. 34. J. Bardeen and W. Shockley. Deformation potentials and mobilities in non-polar crystals. Phys. Rev. 80, 72–80, 1950. 35. S. Thompson. Technology performance: trends and challenges. IEDM short cource, Washington, DC, 1999. 36. G. Dresselhaus, A.F. Kip, and C. Kittel. Cyclotron resonance of electrons and holes in silicon and germanium crystals. Phys. Rev. 98, 368–384, 1955. 37. K. Wu. Comparison of hole mobility in uniaxial and biaxial strained pMOSFETs. IEEE Electron Dev. Lett. submitted. 38. R. Oberhuber, G. Zandler, and P. Vogl. Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFETs. Phys. Rev. B 58, 9941–9948, 1998. 39. F. Stern. Self-consistent results for n-type Si inversion layers. Phys. Rev. B: Solid State 5, 4891–4899, 1972. 40. M.L. Lee and E.A. Fitzgerald. Hole mobility enhancements in nanometer-scale strained-silicon heterostructures grown on Ge-rich relaxed Si1xGex. J. Appl. Phys. 94, 2590–2596, 2003.

© 2006 by Taylor & Francis Group, LLC

Uniaxial Stressed Si MOSFET

5.3-613

41. M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber and K. Zawadzki. Understanding stress enhanced performance in Intel 90nm CMOS technology. Symp. VLSI Tech. Dig., Hawaii, 2004. 42. J.C. Hensel and G. Feher. Cyclotron resonance experiments in uniaxially stressed silicon: valence band inverse mass parameters and deformation potentials. Phys. Rev. 129, 1041–1062, 1963. 43. K. Yamada. Temperature dependence of the piezoresistance effects of p-type silicon diffused layers. Trans. IEE Japan 103A, 555–562, 1983. 44. C.S. Smith. Piezoresistance effect in germanium and silicon. Phys. Rev. 94, 42–49, 1954. 45. G. Dorda. Effective mass change of electrons in silicon inversion layers observed by piezoresistance. Appl. Phys. Lett. 17, 406–408, 1970. 46. G. Dorda. Piezoresistance in quantized conduction bands in silicon inversion layers. J. Appl. Phys. 42, 2053–2060, 1971. 47. S.-i. Takagi, J.L. Hoyt, J.J. Welser, and J.F. Gibbons. Comparative study, of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 80, 1567–1577, 1996. 48. W. Zhang and J.G. Fossum. On the threshold voltage of strained-Si/SiGe MOSFETs. IEEE Trans. Electron Dev. 52(2): 263–268, 2005. 49. C.G. Van de Walle. Band lineups and deformation potentials in the model-solid theory. Phys. Rev. B 39, 1871–1883, 1989. 50. C.G. Van de Walle and R.M. Martin. Theoretical calculations of heterojunction discontinuities in the Si/Ge system. Phys. Rev. B 34, 5621–5634, 1986. 51. H. Hasegawa. Theory of cyclotron resonance in strained silicon crystals. Phys. Rev. 129, 1029–1040, 1963.

© 2006 by Taylor & Francis Group, LLC

5.4 SiGe-Channel HFETs 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5

Sanjay Banerjee University of Texas

5.4.6 5.4.7 5.4.8

Introduction............................................................... 5.4-615 Bandstructure and Transport ................................... 5.4-615 Buried Si1xGex Channel pHFETs with Si Cap ...... 5.4-618 Strain-Compensated Si1xyGexCy Buried-Channel pMOSFET ...................................... 5.4-619 Surface-Channel Si and Si1xGex/High-k pHFETs....................................................................... 5.4-621 n-Channel Devices for CMOS ................................. 5.4-624 Vertical HFETs ........................................................... 5.4-624 Summary .................................................................... 5.4-625

5.4.1 Introduction Since the earlier chapters have provided excellent overviews of the materials and bandstructure issues of SiGe, in this chapter we will focus on their application in heterostructure FETs (HFETs). We will briefly discuss the transport issues of SiGe and SiGeC alloys that are relevant to HFETs. Then will discuss their applications in buried- and surface-channel HFETs, with an emphasis on pHFETs. We will conclude by briefly describing the vertical HFETs and implications for n-channel devices and CMOS.

5.4.2 Bandstructure and Transport The main motivation for grafting Ge and C onto Si technology is that the use of such heterostructures enables one to do ‘‘bandgap’’ and ‘‘strain’’ engineering to achieve enhanced transport properties [1–5]. Seminal work in this area was done by Meyerson and his group at IBM [1]. There is initially a gradual decrease of the bandgap with increasing Ge mole fraction x as the valleys in unstrained Si1xGex are lowered, but the overall bandstructure remains Si-like. For higher Ge mole fractions above 0.85, there is a more rapid decrease of the energy gap with x, corresponding to the L-valleys decreasing more rapidly with x, and the bandstructure of Si1xGex becomes Ge-like. In the presence of biaxial compressive strain of a Si1xGex layer grown on a Si substrate, the six-fold degeneracy of the conduction band (for low x, where the bands are still Si-like) is broken into lower energy four ‘‘in-plane’’ valleys, and higher energy valleys in the growth direction. Similarly, the degeneracy in the valence band is also split, and the heavy hole band is lifted relative to the light hole band (Figure 5.4.1) [6]. The bandgap in compressively strained Si1xGex grown on an Si substrate is reduced compared to the bulk, unstrained system, and is determined by the transition from the heavy hole (HH) to the fourfold in-plane degenerate conduction bands D [4, 7]. For this case, one has a Type I band alignment where most of the band discontinuity is in the valence band, and DEc ﬃ 0. This results in effective hole confinement in the Si1xGex layer, but no electron confinement [8]. Because of the warped nature of the spheres in the valence band, according to the Luttinger–Kohn parameters, the heavy hole band actually presents a lower in-plane effective mass than the light hole 5.4-615 © 2006 by Taylor & Francis Group, LLC

5.4-616

The Silicon Heterostructure Handbook

L

∆2

HH k

Energy (eV)

1.17 E

∆4 0.84

hh lh

LH so

0.0 (a)

SO

0.25 (b)

0.5

0.75

Ge Fraction, x

FIGURE 5.4.1 (a) Valence bandstructure in Si1xGex with compressive strain. The heavy hole band is occupied. The deformation increases the curvature of the heavy hole (HH) band, and increases hole mobility. (b) With increasing Ge mole fraction (compressive strain), the degeneracies in the conduction and valence band are broken, as shown.

band. There is, thus, an increase of the in-plane hole mobility, which is attractive for pHFETs (Figure 5.4.2) [6, 9]. There are additional strain-related factors such as the lifting of the degeneracy between heavy and light holes, which reduces inter-subband scattering. On the other hand, several factors reduce the mobility. These include alloy scattering in random Si1xGex alloys. If there are misfit dislocations generated in these strained heterolayers, there can be dislocation scattering. Finally, for in-plane transport, there can be surface roughness scattering at the heterointerfaces, where strain and surface free energies play a role in the morphology of the heterointerface. Obviously, for ultrasmall HFETs the mobility alone (especially low field m) is not the only important parameter, which determines speed and drive current. The saturation drift velocity, VSAT, and velocity overshoot can have a big impact on performance [10, 11]. Although the VSAT is slightly higher in strained Si1xGex than in bulk Si the enhancement is not very dramatic. In spite of this, there are significant advantages from a device point of view by increasing mobility. That is because VSAT is achieved at a lower field in Si1xGex than in Si, i.e., carriers would travel at VSAT over a longer portion of the channel in Si1xGex devices than in Si. In such heterostructures, it is also possible to do ‘‘modulation doping’’ to increase carrier mobilities further in MODFETs. For example, if the acceptors are introduced only in Si, the holes would spill over to the adjacent Si1xGex layers if the layers are sufficiently thin. Then for in-plane transport, the holes would not undergo ionized impurity scattering. For strained Si1xGex channel HFETs or MODFETs [12, 13], the critical device parameters can be identified by first examining the drain current expression in a long-channel MOSFET, IDSAT ¼

W mCOX ½VG VT 2 L 2

(5:4:1)

where W and L are the width and length, m is the effective channel mobility, COX, the gate dielectric capacitance per unit area, is the ratio of the dielectric constant over the gate oxide thickness ( ¼ «OX / tOX), VT is the threshold voltage, and VG and VD are the gate and drain biases, respectively. As discussed earlier, the attraction of introducing strained Si1x–yGexCy channels in HFETs or modulation-doped layers in MODFETs is the increase of m [10–13]. In a short-channel MOSFET, because of the high

© 2006 by Taylor & Francis Group, LLC

5.4-617

800

300

600

200

2

400 100

200

ND = 1017 0.0 0.0 0.1 0.2

ND = 1018 0 0.0 0.1 0.2

0.3

200

200

100

100

ND = 1019 0 0.0 0.1 0.2 (a)

3

Hole mobility (cm2 / Vs)

Drift mobility (cm2/(Vs))

SiGe-Channel HFETs

0.3

1049 8 7 6 5 4

m−l

3 2

mll

1039 8 7 6 5 4

m−l

Alloy scattering

3

1020

ND = 0 0.3 0.0 0.1 Ge content

mll

No alloy scattering

0.2

0.0

0.3

0.2

(b)

0.4 0.6 0.8 Ge mole fraction

1.0

3 Electron mobility (103 cm2 / Vs)

Si1−x Gex on <001> Si 300 k

2

ml − No alloy scattering

mll

1 ml − mll

0 (c) 0.0

0.2

0.4

Alloy scattering 0.6

0.8

1.0

FIGURE 5.4.2 (a) Monte Carlo calculations of minority hole mobilities of Si1xGex for four doping levels (in cm3) at 300 K: dot-dashed line is the vertical mobility of strained Si1xGex, solid line is the mobility of unstrained Si1xGex , dashed line is the planar mobility of strained Si1xGex [9]. (b) Hole mobility with or without alloy scattering in-plane and out-of-plane. (c) Electron mobility with or without alloy scattering in-plane and outof-plane [6].

longitudinal electric field along the channel, the carriers tend to travel at the saturation drift velocity, VSAT, over a large fraction of the channel. Here the drain current is given by IDSAT ¼ WCOX ½VG VT VSAT

(5:4:2)

rather than the expression in Equation (5.4.1). In that case the benefits of using Si–Ge alloys in the channel are a little less clear because VSAT is very similar in Si and these alloys. However, a higher m still helps somewhat because the carriers then attain VSAT earlier on in the channel where the channel is not yet pinched off. More interesting is another viewpoint of drain current limitation in extremely short channel, ‘‘quasiballistic’’ MOSFETs [14]. In this ‘‘scattering’’ picture, based on the so-called Landauer–Buttiker formalism for transport in mesoscopic systems, the drain current in such devices is limited by carrier injection from the source across the source–channel potential barrier, rather than velocity saturation in the pinchoff region near the drain.

© 2006 by Taylor & Francis Group, LLC

5.4-618

The Silicon Heterostructure Handbook

IDSAT ¼ WCOX Vth

1r ½VG VT 1þr

(5:4:3)

where Vth is the thermal velocity of carriers in the source, and r is the reflection coefficient of carriers at the source–channel barrier. Increasing the channel mobility in long-channel MOSFETs reduces the reflection coefficient and should provide benefits in these very-short-channel alloy-based HFETs. Unfortunately, there are other factors that complicate the drive current issue. Because of the fact that it is difficult to grow a high-quality gate oxide on a high Ge content layer, it is necessary to have a thin Si ‘‘buffer’’ layer on top of the Si1xGex channel to enable the growth or deposition of the gate dielectric. The undoped Si buffer layer, however, is tantamount to adding to the gate dielectric thickness, resulting in lower COX, and hence the drive current. Of course, m tends not to be degraded as much in such structures as in surface channel devices due to surface roughness scattering. However, it is important that the reduction of COX is more than compensated by the increase of m in such strained channel HFETs. The buffer layer also determines the gate bias ‘‘window’’ where conduction is in the highermobility buried strained channel, and not in the top Si cap layer. Another design factor that is critical is the subthreshold slope that, in turn, determines the ratio of the ON (or drive) current to the OFF (or leakage) current. It turns out that often for deep submicron devices, a high drive current is less of a problem than achieving low leakage current. Here also, having a buffer layer and buried-channel operation hurts one in terms of the ability to turn the channel OFF. In addition, defects such as misfit dislocations in these heterolayers would also tend to increase the leakage current.

5.4.3 Buried Si1xGex Channel pHFETs with Si Cap Compressively strained Si1xGex provides an avenue to improve hole mobility and thus increase pHFETs drive current. The first report of enhanced mobility Si1xGex pHFET was by Nayak et al. [12]. This was subsequently validated by other groups, with reports as early as 1993 showing 90% mobility enhancement for Si0.7Ge0.3 SIMOX HFETs over identical Si control devices. In 1995, Widener et al. [15] reported 70% mobility enhancement over Si at room temperature for Si0.8Ge0.2 pMOSFETs using a standard 0.6 mm technology process flow. They also reported a 20% drive current enhancement for these devices. The Si1xGex device is buried channel because a high-quality gate oxide cannot be grown on Si1xGex ; thus a Si cap has to be grown on top of the Si1xGex to enable the growth of a thermal gate oxide (Figure 5.4.3) [16, 17]. In order to maximize performance in buried-channel Si1xGex pHFETs, the Si cap needs to be as thin as possible, though there are trade-offs. Thicker Si caps degrade gate capacitance, but very thin caps lead to increased surface roughness scattering [13]. Si0.9Ge0.1 pHFETs show that mobility-enhanced drive current as well as improved short-channel effects can be achieved in buried-channel Si1xGex pHFETs with an optimized Si cap and relatively modest amounts of Ge (up to 20%) (Figure 5.4.4) [18, 19]. The gate-to-channel inversion capacitance difference for the Si0.9Ge0.1 and Si control devices results from the unconsumed Si cap layer in Si0.9Ge0.1 HFETs. The inversion equivalent oxide thickness (EOT) is 4.6 and 5.0 nm for Si control and Si0.9Ge0.1, respectively, including polydepletion and quantum-mechanical effects. The slightly higher inverse subthreshold slope (SS) in the long-channel Si1xGex HFET is due to buried-channel operation, but when LG < 0.2 mm, the SS for Si and Si1xGex is about the same due to the improved short-channel effects (SCE) in the Si1xGex devices. The improved SCE is due to the reduction of B diffusivity in Si1xGex , from the source–drain (S–D) regions. If the Si cap is completely consumed, then the gate–oxide interface reaches the Si0.9Ge0.1 layer, and a much higher SS is observed due to the poor gate–oxide interface quality. The transistor IDSVGS characteristics for LG ¼ 70 nm show that the turn-off characteristics are good for both Si and Si1xGex pHFETs (Figure 5.4.4(a)), with Ioff ¼ 25 nA/mm, and SS for Si and Si1xGex pHFETs are both 107 mV/dec. Si0.9Ge0.1 shows a slightly smaller DIBL, and this could be due to shallower S–D junctions because of reduced B diffusivities in SiGe, that would lead to an increased effective channel length. The p–n junction leakage level for Si0.9Ge0.1 device is only slightly higher than the Si control, and more importantly, the OFF current at normal device operation condition

© 2006 by Taylor & Francis Group, LLC

5.4-619

SiGe-Channel HFETs

Poly

SiGe

Si substrate (a)

Ec

Energy

Oxide

Ev ∆Ev Depth (b)

FIGURE 5.4.3 (a) pHFET structure with compressive Si1xGex or partially strain compensated Si1xyGexCy channel, Si cap and pþ source–drains. (b) The band diagram as a function of depth indicates that the holes will be confined in the Si1xGex or Si1xyGexCy layer due to the valence band offset, as long as we operate in a suitable gate voltage operating window.

(VGS ¼ 0 V, VDS ¼ VDD) for Si0.9Ge0.1 device is about the same, or can be slightly lower than for the Si control device if VT differences are normalized. The IDSVDS characteristics for the LG ¼ 70 nm, as seen in Figure 5.4.5(b), show that Si0.9Ge0.1 has 17% higher drive current than Si even for such shortchannel lengths and modest Ge mole fractions, indicating that the improved long-channel mobility translates to better source injection of carriers into the channel. The linear VT (defined by IDSVGS curve at VDS ¼ 100 mV, extrapolated to zero from maximum transconductance, Gm, point) as a function of channel length shows minimal VT roll-off for both Si and Si0.9Ge0.1 devices. The VT for Si0.9Ge0.1 is about 90 mV lower than for Si. This is due to the valence band offset between Si and Si0.9Ge0.1 [20, 21]. X-ray diffraction (XRD) scans for Si0.9Ge0.1 before and after processing show no shift of the Ge peak. This suggests that the Si0.9Ge0.1 channel is still under compressive strain after processing. This is critical for strained Si1xGex HFET integration since for low Ge mole fractions the benefits of strained Si1xGex channel HFET are lost once the Si1xGex layer is relaxed. These results show that modest amounts of Ge (10% to 20%) in Si1xGex films can be used to fabricate high-performance buried-channel pHFETs. By carefully engineering a triangular Ge profile in Si1xGex [22], and the Si cap in these devices, it is possible to fabricate buried-channel Si1xGex pHFETs that have higher drive currents than surface channel Si pMOSFETs [23]. Since the mobility of holes in Si is lower than electrons, by using this approach, it is possible to obtain a more balanced CMOS process than is currently achieved in conventional Si CMOS processes.

5.4.4 Strain-Compensated Si1xyGexCy Buried-Channel pMOSFET The first application of a partially strain-compensated ternary Si1xyGexCy alloy in a pHFET was by Ray et al. [24]. Since C is smaller than both Si and Ge, it can introduce local tensile strain and compensate

© 2006 by Taylor & Francis Group, LLC

5.4-620

The Silicon Heterostructure Handbook −1000

Si Si0.9 Ge0.1

Si Si0.9 Ge0.1

−800 Drive current, IDS (A)

Drive current IDS (A)

10−3

10−5

SS = 107 mV/dec W/L = 4 µm/0.07 µm VDS = 0.1, −1.5 V

10−7

10−9

W/L = 4 µm/0.07µm −600

−400

−200 VGS−V = −0, −0.5, −1, −1.5 V

10−11

(a)

1

0.5

0 −0.5 −1 Gate voltage, VGS (V)

−1.5

0

−2

−0.5 −1 Drain voltage, VDS (V)

0

(b)

−1.5

Effective hole mobility (cm2/VS)

150

100

50 Universal mobility Si Si0.9 Ge0.1 0 0

(c)

0.2

0.4

0.6

0.8

1

Effective field, Eeff (MV/cm)

FIGURE 5.4.4 (a) IDS–VGS characteristics for LG ¼ 70 nm for Si0.9Ge0.1–SiO2 buried-channel pHFET. (b) IDS–VDS characteristics for LG ¼ 70 nm for Si0.9Ge0.1–SiO2 buried-channel pHFET. (c) Effective hole mobility versus field for Si0.9Ge0.1–SiO2 buried-channel pHFET.

the compressive strain introduced by Ge, leading to complete strain compensation at a Ge-to-C ratio of 8:1 [25, 26]. Carbon seems to have a lesser impact on band structure than on strain. Thus, with ternary Si1xyGexCy alloys, another degree of freedom is possible where C can, somewhat independently, adjust the bandgap and strain to some extent, which is not possible with Si1xGex alone. It also makes the Si1xyGexCy layers more robust in terms of the allowable thermal budget during processing, and allows higher levels of Ge incorporation.

© 2006 by Taylor & Francis Group, LLC

5.4-621

SiGe-Channel HFETs

−3⫻10−3 Bare Si 0% C, 40% Ge 1% C, 40% Ge 1.5% C, 40% Ge

−2.5⫻10−3

VG−VT = −4 V

ID (A)

−2⫻10−3 −1.5⫻10−3 −1⫻10−3 −5⫻10−4 VG−VT = −2 V 0⫻100 0

−1

−2

−3

−4

−5

V D (V)

FIGURE 5.4.5 Si0.585Ge0.4C0.015 shows 55% drive current enhancement over bulk Si and 42% enhancement over Si0.6Ge0.4; W/L ¼ 10/0.5 mm; tox ¼ 6 nm.

Results for pHFETs with high (40%) Ge show that incorporation of dilute levels of C (1.5%) allows the compressive strain to be retained much better than for the binary alloys, leading to higher drive currents. The Si1xyGexCy pHFETs have higher drive current than both control Si and Si1xGex devices (Figure 5.4.5). This is believed to be due to the fact that for these high levels of Ge, C helps maintain the compressive strain even after high-temperature device processing better than Si1xGex alone. Carbon also yields a smoother heterointerface as seen by atomic force microscopy, which improves channel mobility compared to that in binary Si1xGex alloys. The results showed that by partially compensating the strain, it is possible to enhance mobility and drive currents for Si1xyGexCy pHFETS with high Ge mole fractions. A key point is that for the range of Ge mole fractions studied, the optimal amount of C depends on the amount of Ge in the Si1xyGexCy pMOSFETs, as well as the channel length. In particular, for x ¼ 0.15 and y ¼ 0.006, there is mobility degradation, while for x ¼ 0.2 and y ¼ 0.007 there is enhanced drive current. Other results have also shown for higher amounts of Ge, an increased amount of C can be used to enhance mobility and drive current. The conclusion that can be drawn from these studies is that while C can be used to compensate strain, full strain-compensation is undesirable; instead C should be used to relax thermal budget constraints while maintaining sufficient compressive strain for mobility enhancement. Alloy scattering is especially critical for these ternary alloys because of the high deformation potential for C in Si [27–29]. Obviously, there are trade-offs in terms of the Ge and C mole fractions and the strained channel layer thickness in terms of how it impacts the allowable thermal budget [22, 23]. An obvious extension is to go to much higher Ge mole fractions up to 100% Ge where Fitzgerald’s group [30] has shown dramatic enhancements of hole mobility. Perhaps Ge:C layers can be grown directly on Si, without having to grow thick relaxed SiGe buffer layers, which present their own manufacturing and device challenges.

5.4.5.

Surface-Channel Si and Si1xGex/High-k pHFETs

We have seen that by careful engineering of the sacrificial Si cap on Si1xGex, which is required for a high-quality thermal gate oxide, it is possible to obtain device performance enhancement in nanometer

© 2006 by Taylor & Francis Group, LLC

5.4-622

The Silicon Heterostructure Handbook

scale buried-channel Si1xGex and Si1xyGexCy pHFETs. An alternate approach is to remove the need for the Si cap by using a deposited gate oxide, such as a high dielectric constant (high-k) gate dielectric, thereby rendering a surface channel device [31, 32]. This is particularly attractive for a Si1xGex or pure Ge channel because it avoids the problems of Ge segregation during thermal gate oxidation. HfO2 is considered to be one of the most promising high-k gate dielectrics to replace SiO2 and achieve lower leakage currents at a comparable EOT. With a deposited HfO2 gate dielectric replacing thermally grown SiO2, SCE associated with buried-channel MOSFETs, and Si cap layer control challenges would no longer exist. In addition, one could harness the benefits associated with having a high-k gate dielectric, namely higher drive currents and lower off-state leakage currents. One drawback with HfO2 is that it causes channel mobility degradation. The use of a higher mobility channel layer could recover some of this mobility and drive current degradation. Compared to a Si–SiO2 pMOSFET, a Si–HfO2 pMOSFET exhibits a peak mobility degradation of about 25%, and 12% degradation at Eeff ¼ 1 MV/cm (Figure 5.4.6(a)). However, the Si0.8Ge0.2 pHFET channel mobility with high-k is significantly higher than the Si–SiO2 pMOSFET control sample, maintaining a 30% mobility enhancement at Eeff ¼ 1 MV/cm. These results show that the use of a compressively strained Si1xGex channel can provide a means to overcome the mobility degradation on Si caused by using HfO2 as a gate dielectric. This mobility enhancement enables a higher drive current, even at channel lengths down to 180 nm. Unfortunately, the subthreshold characteristics of such 180 nm devices (Figure 5.4.6(b)) show that while the drain-induced barrier lowering (DIBL) is comparable for both Si0.8Ge0.2 and Si control devices, the SS and junction leakage is significantly worse for Si0.8Ge0.2 pHFETs. The higher junction leakage may be caused by the narrower bandgap in Si0.8Ge0.2 or defects such as misfit dislocations. The degraded SS, 105 mV/dec for the Si0.8Ge0.2 device versus 85 mV/dec for the Si device is indicative of a higher interface trap density (DIT). This is probably due to the Si1xGex–HfO2 having higher dangling bond density than the Si–HfO2 interface. Another possibility is that Ge segregates out of the strained lattice and accumulates at the Si1xGex–HfO2 interface in a manner similar to the Si1xGex–(Si/Ge)O2 case causing increased DIT.

150

Effective hole mobility (cm2/Vs)

W/L = 18 µm/15 µm

100

50 Si with SiO2 Si with HfO2 Si0.8Ge0.2 with HfO2 Universal Mobility 0 0

(a)

0.2

0.4 0.6 0.8 Effective field, Eeff (MV/cm)

1

FIGURE 5.4.6 (a) IDS–VGS characteristics for LG ¼ 180 nm for Si0.8Ge0.2–HfO2 pHFET.

© 2006 by Taylor & Francis Group, LLC

5.4-623

SiGe-Channel HFETs

Si Si0.8 Ge0.2

10−3

Drive current, IDS (A)

10−5

SS = 105 mV/dec

10−7

SS = 85 mV/dec W/L = 4 µm/0.18 µm VDS = 0.1, −1.6 V

10−9

10−11

10−13

1.2

0.8

0.4

0

−0.4

−0.8

−1.2

Gate voltage, VGS (V)

(b)

190 180

SS (mV/Dec)

170 160

Si Epi Control Si0.875Ge0.125

150

Si0.8Ge0.2

140 130 120 110 0

(c)

2

4

8 6 Lchannel (µm)

10

12

FIGURE 5.4.6 (continued )(b) Effective hole mobility versus effective field for Si0.8Ge0.2–HfO2 pHFET. (c) SS versus channel length for the Si0.875Ge0.125 and Si0.8Ge0.2 samples compared to an epitaxial Si control device.

The significant difference in VT between the Si0.8Ge0.2 and Si devices (210 mV) can be attributed to the bandgap difference between Si0.8Ge0.2 and Si. The bandgap difference is manifested mostly in the valence band and for Ge mole fraction of 0.2 represents a 168 mV valence band offset. Finally, if Ge is segregating to the surface during processing, as in the Si1xGex–(Si/Ge)O2 case, this could represent an increase in fixed negative oxide charge that would correspond to a further reduction in VT for the Si0.8Ge0.2 device.

© 2006 by Taylor & Francis Group, LLC

5.4-624

The Silicon Heterostructure Handbook

There is an anomalous dependence of VT and SS on channel length, L, with HfO2 gate dielectrics (Figure 5.4.6(c)). While VT becomes more positive with decreasing L, SS decreases with reduction in L. SS changes from 144 to 105 mV/dec as the channel length decreased from 8 to 0.18 mm for the Si1xGex pHFETs, and 128 to 85 mV/dec for the Si pMOSFETs. These observations indicate that the longer channel length devices must have an increased DIT and fixed oxide charges. There are reports that HfO2 may be impervious to H2 at the 4008C forming gas anneal temperature that was used for sintering. It is possible that the diffusion of H2 during sintering occurs laterally from the contact holes along the channel, rather than through the polysilicon gate and then through the HfO2, which can explain these anomalous results in terms of SS dependence on L. For long-channel devices, a significant portion of the channel would remain unsintered, as H2 would only diffuse into a small portion of the channel, thus rendering devices with high SS.

5.4.6 n-Channel Devices for CMOS We have so far focused on pHFETs in Si1xGex channels. The rationale used here is that in CMOS, since hole channel mobility is roughly 2.5 times lower than electron mobility, improving the PFET performance would enable a more balanced CMOS layout. However, while this is valid for static logic, in dynamic CMOS, one uses a PFET to precharge the nodes, and the speed depends more on the pull-down NFETs. Even for static CMOS, for many applications, one is often interested in improving the ratio of (IDsat,n-ch þ IDsat,p-ch) over the sum of the OFF currents. Unfortunately, the in-plane electron mobility decreases with compressive strain in Si1xGex, for modest Ge mole fractions; thus it would be expected that the NFET drive current would also decrease. However, Yeo et al. [33] have shown that while this is the case for long-channel devices, as the channel length is scaled below 0.4 mm, enhanced drive current is obtained in Si1xGex NHFETs compared to similarly processed Si control devices. They attributed this to the reduced scattering caused by conduction band splitting. They postulated that this reduced scattering would yield higher optical phononlimited carrier saturation velocity. As the Ge mole fraction is increased, all the way to pure Ge, clearly the electron mobility in Si1xGex or Ge is higher than in Si [30]. Hence, it should lead to improvement of both p- and n-channel devices. However, such high Ge mole fraction or pure Ge layers can currently only be grown defect-free on thick relaxed SiGe buffer layers. However, the problems with such thick SiGe buffer layers (as with tensile strained Si on SiGe relaxed buffers) include cost, manufacturability challenges, isolation issues with shallow-trench isolation along the SiGe layers, lower thermal conductivity of the SiGe leading to self-heating effects in the FETs, and threading dislocation propagation into the channel regions during device fabrication. Perhaps a more palatable solution may be to avoid growing thick SiGe buffer layers, and instead use the compressively strained thin Si1xGex-on-Si channels only in the pHFET active regions (unfortunately requiring selective epitaxy or etching). Clever ideas include a dual-channel CMOS concept proposed by O’Neil and Antoniadis [34], where in the n-channel devices, conduction is in a Si channel while in the PFETs it is in the Si1xGex layer.

5.4.7 Vertical HFETs Yet another solution that may prove to be attractive is to grow a thin, compressively strained Si1xGex channel directly on a Si substrate without requiring a thick SiGe relaxed buffer, etch mesas, and fabricate vertical HFETs on the sidewalls of the Si1xGex islands [35–39]. As shown in Figure 5.4.7, one can achieve significant enhancement of drive currents over control Si PFETs. As seen, it is important for current enhancement that the compressive strain be maintained which causes the splitting of the heavy and light hole bands, leading to lower interband scattering. These FETs were on large mesas, leading to partially depleted FETs with nonoptimized short-channel effects. However, it should be possible to achieve much better DIBL using fully depleted FETs.

© 2006 by Taylor & Francis Group, LLC

5.4-625

SiGe-Channel HFETs

−40 Si Rel. SiGe

ID (mA)

−30

Str. SiGe W/L = 120 µm/70 nm Tox = 4 nm

−20

−10

0

VGS−VT = −1.5 V

−0.5 V

0V 0

−0.5

−1

−1.5 VDS (V)

−2

−2.5

FIGURE 5.4.7 Vertical Si, relaxed and strained Si1xGex pHFETs showing the enhancement of drive current over control Si MOSFETs only in the presence of strain.

In this case, it also leads to an enhancement of the n-channel drive current [38, 39]. This is because, as mentioned in Section 5.4.2, the four in-plane conduction band valleys are lowered in energy. While that leads to an increase of in-plane electron effective mass, obviously it leads to a lower (transverse) out-ofplane effective mass. This, along with a reduction of the f-type intervalley electron scattering, leads to an improvement of electron mobility and NFET drive currents. Of course, vertical FETs pose their own process integration challenges compared to planar devices.

5.4.8 Summary As challenges to scaling continue to grow, it is prudent to examine nontraditional methods of improving CMOS performance. Because hole mobility is lower than electron mobility in silicon, it would be attractive to use materials that could enhance hole over electron mobility, and thus, provide a balanced CMOS process that reduces the total area used for a circuit as well as improves its performance. This chapter has presented results and discussion of buried-channel Si1xGex, and Si1xyGexCy pHFETs. It has been shown that with even modest amounts of Ge (10% to 20%), buried-channel Si1xGex pHFETs can be used in deeply scaled devices and provide performance enhancement over Si. For much higher Ge mole fraction channels grown on Si without a SiGe buffer layer, partially strain-compensated Si1xyGexCy may be a viable option. It may be possible that for higher amounts of Ge, up to pure Ge, the increased hole and electron mobilities may enable improved pHFETs as well as NHFETs. Experimental results presented in this chapter show that Si1xGexHfO2 surface channel pHFETs provide a means to recover the mobility degradation that occurs in Si–HfO2 pMOSFETs. Vertical HFETs are another intriguing device structure in our repertoire that should be considered. Unfortunately, all these options have their pros and cons.

Acknowledgments The author would like to acknowledge his former doctoral students, D. Onsongo, S. John, E. Quinones, Z. Shi, K. Jayanarayan, X. Chen, and post-docs, Dr. Samit Ray and Dr. Freek Prins, for their invaluable contributions. The work has been supported over the years by SRC, NSF, DARPA, Texas Advanced Technology/Research Program, Intel, TI, Micron Foundation, and Applied Materials.

© 2006 by Taylor & Francis Group, LLC

5.4-626

The Silicon Heterostructure Handbook

References 1. BS Meyerson. UHV/CVD growth of Si and Si:Ge alloys: chemistry, physics and device applications. Proc. IEEE 80: 1592–1608, 1992. 2. SK Banerjee. Bandgap and strain engineered SiGeC vertical and planar MOSFETs. Microelectr. Eng. 69(2–4): 106–117, 2003 (invited paper). 3. JC Bean. Silicon-based semiconductor heterostructures: column IV bandgap engineering. Proc. IEEE 80: 571–587, 1992. 4. KL Wang, SG Thomas, and MO Tanner. SiGe band engineering for MOS, CMOS and quantum effect devices. J. Mater. Sci.: Mater. Electron. 6: 311–324, 1995. 5. C Li, S John, and SK Banerjee. Cold-wall UHVCVD of doped and undoped Si and Si1xGex epitaxial films using SiH4 and Si2H6. J. Vac. Sci. Technol. A 14: 170–183, 1996. 6. MV Fischetti and SE Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge and SiGe alloys. J. Appl. Phys. 80: 2236–2252, 1996. 7. JM Hinckley and J Singh. Hole transport theory in pseudomorphic Si1xGex alloys grown on Si (0 0 1) substrates. Phys. Rev. B 41: 2912–2926, 1989. 8. CG Van de Walle and RM Martin. Theoretical calculations of heterojunction discontinuties in the Si/Ge system. Phys. Rev. B 34: 5621–5634, 1986. 9. FM Bufler, P Graf, B Meinerzhagen, G Fischer, and H Kibbel. Hole transport investigation in unstrained and strained SiGe. J. Vac. Sci. Technol. B 16(3), 1667–1669, 1998. 10. A Sadek and K Ismail. Si/SiGe CMOS possibilities. Solid State Electron. 38: 1731–1736, 1995. 11. A Sadek, K Ismail, MA Armstrong, D Antoniadis, and F Stern. Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors. IEEE Trans. Electron Dev. 43: 1224–1232, 1996. 12. D Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. Enhancement-mode quantum-well GeSi MOSFET. IEEE Electron Dev. Lett. 12: 154–156, 1991. 13. S Verdonck-Vandebroek, EF Crabbe, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Trans. Electron Dev. 41: 90–101, 1994. 14. M Lundstrom. Elementary scattering theory of the Si MOSFET. IEEE Electron Dev. Lett. 18, 361–363, 1997. 15. JO Widener, KR Hofmann, F Hormann, and L Risch. Characterization of SiGe quantum-well p-channel MOSFETs. J. Mater. Sci. — Mater. Electron. 6(5): 325, 1995. 16. SK Ray, S Maikap, SK Samanta, and S Banerjee. Charge trapping characteristics of ultrathin oxynitrides on Si/Si1xyGexCy /Si heterolayers. Solid State Electron. 45(11): 1951–1955, 2001. 17. S Maikap, SK Ray, and SK Banerjee. Electrical properties of O2/NO-plasma grown oxynitride films on partially strain compensated Si/Si1xyGexCy /Si heterolayers. Semicond. Sci. Technol. 16(3): 160– 163, 2001. 18. ZH Shi, D Onsongo, and SK Banerjee. Mobility and performance enhancement in compressively strained SiGe channel pMOSFETs. Appl. Surf. Sci. 224(1–4): 248–253, 2004. 19. GS Kar, SK Ray, T Kim, and SK Banerjee. Estimation of hole mobility in strained Si1xGex buried channel heterostructure pMOSFET. Solid State Electron. 45(5): 669–676, 2001. 20. CG Van de Walle. Band lineups and deformation potentials in the model-solid theory. Phys. Rev. B 3: 1871–1883, 1989. 21. X Wang, DL Kencke, KC Liu, F Register, and SK Banerjee. Band alignments in sidewall strained Si/strained SiGe heterostructures. Solid State Electron. 46(12): 2021–2025, 2002. 22. SP Voingescu, CAT Salama, JP Noel, and TI Kamins. Optimized Ge channel profiles for VLSI compatible Si/SiGe p-MOSFETs. Proc. IEDM 369–372, 1994. 23. Z Shi, X Chen, D Onsongo, E Quinones, and SK Banerjee. Simulation and optimization of strained Si1xGex buried channel p-MOSFETs. Solid State Electron. 44(7): 1223–1228, 2000. 24. SK Ray, S John, E Quinones, SK Oswal, and SK Banerjee. Heterostructure p-channel metal-oxidesemiconductor transistor utilizing a Si1xGexCy channel. IEEE IEDM Tech. Dig. 261–264, 1996; also Appl. Phys. Lett. 74: 847, 1999.

© 2006 by Taylor & Francis Group, LLC

SiGe-Channel HFETs

5.4-627

25. SS Iyer, K Ebert, AR Powell, and BA Ek. SiCGe ternary alloys-extending Si-based heterostructures. Microelectron. Eng. 19: 351–354, 1992. 26. K Ebert, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Appl. Phys. Lett. 60: 3033–3035, 1992. 27. GS Kar, A Dhar, LK Bera, and SK Banerjee. Effect of carbon on lattice strain and hole mobility in Si1xGex alloys. J. Mater. Sci. — Mater. Electron. 13(1): 49–55, 2002. 28. GS Kar, S Maikap, SK Ray, and SK Banerjee. Effective mobility and alloy scattering in the strain compensated SiGeC inversion layer. Semicond. Sci. Technol. 17(5): 471–475, 2002. 29. GS Kar, S Maikap, SK Banerjee, and SK Ray. Series resistance and mobility degradation factor in C-incorporated SiGe heterostructure p-type metal-oxide semiconductor field-effect transistors. Semicond. Sci. Technol. 17, 938–941, 2002. 30. ML Lee and EA Fitzgerald. Electron mobility characteristics of n-channel metal-oxidesemiconductor field-effect transistors fabricated on Ge-rich single- and dual-channel SiGe heterostructures. J. Appl. Phys. 95(3): 1550–1555, 2004. 31. ZH Shi, D Onsongo, K Onishi, J Lee, and SK Banerjee. Mobility enhancement in surface channel SiGe pMOSFETs with HfO2 gate dielectrics. IEEE Electron Dev. Lett. 24(1): 34–36, 2003. 32. T Ngai, WJ Qi, R Sharma, and SK Banerjee. Transconductance improvement in surface-channel SiGe p-metal-oxide-silicon field-effect transistors using a ZrO2 gate dielectric. Appl. Phys. Lett. 78(20): 3085–3087, 2001. 33. YC Yeo, Q Lu, T King, C Hu, T Kawashima, M Oishi, S Mashiro, and J Sakai. Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial Si–Ge. IEEE IEDM Tech. Dig. 753–756, 2000. 34. AG O’Neill and DA Antoniadis. Deep submicron CMOS based on silicon germanium technology. IEEE Trans. Electron Dev. 43(6): 911–918, 1996. 35. XD Chen, QQ Ouyang, SK Jayanarayanan, F Prins, and S Banerjee. Vertical p-type high-mobility heterojunction metal-oxide-semiconductor field-effect transistors. Appl. Phys. Lett. 78(21): 3334– 3336, 2001. 36. XD Chen, Q Ouyang, SK Jayanarayanan, and SK Banerjee. An asymmetric Si/Si1xGex channel vertical p-type metal-oxide-semiconductor field-effect transistor. Solid State Electron. 45(2): 281– 285, 2001. 37. X Chen, KC Liu, SK Jayanarayanan, and S Banerjee. Electron mobility enhancement in strained SiGe vertical n-type metal-oxide semiconductor field-effect transistors. Appl. Phys. Lett. 78(3), 377, 2001. 38. XD Chen, QC Ouyang, G Wang, AF Tasch, and SK Banerjee. Improved hot-carrier and shortchannel performance in vertical nMOSFETs with graded channel doping. IEEE Trans. Electron Dev. 49(11): 1962–1968, 2002. 39. XD Chen, KC Liu, QC Ouyang, and SK Banerjee. Hole and electron mobility enhancement in strained SiGe vertical MOSFETs. IEEE Trans. Electron Dev. 48(9): 1975–1980, 2001.

© 2006 by Taylor & Francis Group, LLC

5.5 Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies 5.5.1 5.5.2

Introduction............................................................... 5.5-629 90 nm Strained Silicon Technology.......................... 5.5-631 Process Flow . Strained Si Process Flow: Results and Discussion . Yield and Integration . Need for Strained Si in the 90 nm Technology Generation

Scott E. Thompson University of Florida

5.5.3 5.5.4

Future Direction of Strained Silicon ....................... 5.5-636 Summary .................................................................... 5.5-638

5.5.1 Introduction This chapter describes uniaxial strained Si and Si1xGex heteroepitaxy introduced for the first time at the 90 nm technology generation into high-volume manufacturing. For more than 30 years, CMOS device technologies have improved at a dramatic rate due to dimension scaling. Scaling the vertical and horizontal MOSFET dimension reduces channel resistance through increased inversion charge and lower source to drain resistance, respectively. It is this unique property of higher performance and lower cost through dimension scaling that has established the MOSFET as the clearly dominant solid-state device. The semiconductor and microelectronic industry has made remarkable and nearly unprecedented progress during the last 30 years. During this time, the MOSFET gate length scaled from 10 mm to 45 nm and now contains many features at the nanoscale. Figure 5.5.1 shows the evolution pictorially with Lilenfield’s MOSFET concept, the first experimental transistor in 1947, and the present day 45 nm transistor which incorporates Si1xGex in the source and drain to strain the Si channel [1–3]. Equally impressive are the improvements in cost and density made by the industry. For the 90 nm technology generation, greater than 200 billion transistors are fabricated on a standard 300 mm wafer. Hundreds of millions of transistors can be fabricated on a single chip with a manufacturing cost of only a few dollars. Figure 5.5.2 shows the wafer size history for the semiconductor industry and the size of the 300 mm wafers now state-of-the-art for 90 nm technology manufacturing. Because of these massive improvements in productivity, Gordon Moore observed that transistors are basically free [4]. The introduction of strained Si at the 90 nm technology generation with selective heteroepitaxy represents a significant departure from the historical feature size scaling. This deviation from traditional scaling is needed because conventional MOSFETs have reached some atomic-level limits. During the early years of transistor scaling, Gordon Moore (in 1965) observed that the number of transistors on a chip increased exponentially over time [5, 6], which has become known as Moore’s Law. However, 5.5-629 © 2006 by Taylor & Francis Group, LLC

5.5-630

The Silicon Heterostructure Handbook

FIGURE 5.5.1 History of transistor development.

FIGURE 5.5.2 History of production wafer size.

according to Moore himself, ‘‘no exponential is forever’’ [4]. Because of high off-state leakage, the scaling limit for the planar MOSFET is approximately 20 nm. Planar MOSFETs as small as 10 nm have been fabricated; however, they do not appear practical due to high leakage [7]. The undesirable off-state leakage results from many mechanisms with source-to-drain subthreshold and gate tunneling current as the largest contributors. Aggressive gate oxide scaling during the last 30 years has resulted in a 1.2 nm physical oxide at the 90 nm generation [3], which is at the gate tunneling leakage limit for SiO2. This is significant since some consider SiO2 (as opposed to the Si channel) the foundation of the modern MOSFET. At present, high k gates are not ready for manufacturing due to degraded mobility [8] especially at low gate bias. Thus, the semiconductor industry needs some other material change to continue MOSFET scaling. Starting at the 90 nm technology generation, strained Si is one such material change which has been widely adopted [1–3, 9]. At present, strained Si offers performance gains much larger than any other new material options. Figure 5.5.3 plots the feature size progress during the last 30 years and highlights the unprecedented number of new materials needed to maintain historical improvements going forward.

© 2006 by Taylor & Francis Group, LLC

5.5-631

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

Technology feature size SiGe, NiSi Low K

1 µm

Source Intel Technology

Cu CoSi2

100 µm

Higher strain High K? Metal gates? Double gate? Tri-Gate SiC s/d? 90nm Ge channel?

TiSi 2,W Ti, TiN

Si, SiO 2 Poly-Si

# New materials

Nominal feature size

10 µm

Gate length Si3N4

10 µm 1970

1980

1990

2000

2010

2020

FIGURE 5.5.3 Technology and gate feature size and new materials needed versus time.

This chapter is organized as follows. Section 5.5.2 describes a strained silicon process flow in commercial production at the 90 nm logic technology generation. This section also shows the industry power and leakage trends and justifies why new materials like strained Si are needed. Section 5.5.3 briefly looks at the future of strained Si concepts and direction.

5.5.2 90 nm Strained Silicon Technology Smith first measured the mobility enhancement through lattice strain of single-crystal silicon and germanium in 1954 [10]. Since then p-type Si has found wide application in mechanical sensors. However, until recently strain has not been incorporated into a production CMOS logic technology for several reasons. First, for the last 30 years, gate oxide and shallow junction scaling obtained adequate MOSFET improvement. Second, biaxial and uniaxal stress are difficult to integrate. The difficulty with biaxial stress is that it is introduced early in the process flow before gate formation requiring significant adjustments to lower the entire midsection thermal cycles. The difficulty with uniaxial mechanical stress is failure to improve both n-type and p-type MOSFETs simultaneously. Finally, heteroepitaxy processes are high-yield risk due to threading dislocations. In this section, the strain silicon process flow used in a 90 nm CMOS logic technology is discussed along with yield and process integration issues. The unique advantage of this uniaxial stressed Si process flow is that (on the same wafer) compressive strain is introduced into the p-type and tensile strain in the n-type MOSFETs to improve both the electron and hole mobilities. The flow differs from past uniaxial stress work by introducing heteroepitaxy Si1xGex in the p-channel source and drain. The use of heterojunctions in the p-channel MOSFET has previously been proposed [11–16] for several reasons. Ozturk [14, 15] first introduced Si1xGex into the source–drain for the purposes of higher boron activation and abrupt profile. Banerjee [11, 12, 16] introduced strained Si1xGex into the source and drain for bandgap engineering. These past advantages are valid and provide some additional benefit in this work. However, heteroepitaxy in the source and drain in nanoscale devices results in uniaxial Si channel stress, which can significantly enhance the mobility.

Process Flow Only slight modifications to a standard CMOS logic technology process flow are required to insert the compressive strain into the p-type and tensile strain into the n-type MOSFETs.

© 2006 by Taylor & Francis Group, LLC

5.5-632

The Silicon Heterostructure Handbook

For uniaxial stress and assuming standard wafer and transistor orientation, lattice compression for p-channel and tension for n-channel MOSFETs are needed for mobility enhancement. To fabricate the strained Si, the process flow is nearly unchanged until after source–drain extension and spacer formation. Postspacer etch, an Si recess etch is inserted followed by selective epitaxial Si1xGex deposition (Figure 5.5.4(a)). The silicon etch is blocked from n-channel devices and poly-Si gates. The Si recess etch removes 100 nm vertically and 70 nm laterally from the p-channel source and drain. The etch is intentionally targeted to laterally under cut the spacer to bring the Si1xGex closer to the channel. Fabricating the Si1xGex closer to the channel has two benefits. First the channel stress is increased for larger mobility enhancement. Second, and equally important, the external resistance is reduced. However, stringent controls of the lateral etch are needed to maintain drive current and performance uniformity across all structures [17]. Next, epitaxial Si1xGex is grown in the source and drain (Figure 5.5.4(b)). The Si1xGex growth is targeted to be raised above the gate plan such that for the first time raised source and drains are introduced at the 90 nm technology generation. Raising the source and drains requires little extra cost or complexity during the Si1xGex deposition but offers significant improvement to the external resistance. As seen in the device cross section and mentioned previously, the Si1xGex is blocked from the poly-Si gates even though Si1xGex gates offer improved p-channel performance. The Si1xGex is blocked from the poly-Si gate out of concern for mushroom growth and degraded contact to gate design rule margin. The remaining process flow is conventional except for the salicide (Figure 5.5.4(c)). Si1xGex in the source and drain requires extensive changes to the salicide since Ge inhibits the CoSi2 transition to the low-resistivity disilicide phase [18]. To solve this problem, NiSi instead of CoSi2 is used. Nickel silicide requires extensive changes since all formation and postformation process steps need to be less than 5008C. After salicide formation, longitudinal uniaxial tensile strain is introduced into the n-type MOSFET by engineering the tensile stress and thickness of the Si nitride-capping layer [19, 20] present to support unlanded contacts (Figure 5.5.4(d)). Stress-induced tensile capping films are widely adopted at the 90 nm technology generation [1, 2, 9] and can improve n-channel device saturated drive current 10 to 15% [1, 9, 19, 20]. However, the tensile stress from the capping layer needs to be relaxed from the p-channel device since it causes significant degradation [1, 9, 19, 20]. There are several techniques to almost completely neutralize the capping layer strain; one is the use of a Ge implant and masking

FIGURE 5.5.4 Strained Si process flow.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

5.5-633

High stress film 45nm

Si1−x Ge x

Si1−x Ge x

p-type MOSFET

FIGURE 5.5.5 generation.

n-type MOSFET

Transistor cross section of 45 nm gate length strained Si transistors used at 90 nm technology

layer [20]. Raising the p-channel source and drain also reduces the negative effect of the tensile capping layer on the p-MOSFET. At the 90 nm technology generation, the thickness of the capping layer is approximately 80 nm and chosen as a balance between transistor performance and contact etch integration requirements. The use of (i) Si1xGex in the p-channel source and drain, (ii) a tensile capping film, and (iii) capping film strain relaxation off the p-MOSFET, allows independent targeting of the n- and p-type MOSFET Si channel strain (by adjusting capping films stress for n-type and Ge source–drain concentration for p-type). Also, the n- and p-channel stresses are predominantly uniaxial, which are desirable since uniaxial stress offers many advantages in electrical performance over biaxial stress (see Chapter 5.3).

Strained Si Process Flow: Results and Discussion TEM micrographs of 45 nm p- and n-type MOSFETs are shown in Figure 5.5.5, which are patterned with 193 nm lithography. At the 90 nm technology generation, 17% germanium concentration (Si0.83Ge0.17) is used, which has a lattice spacing 1% larger than Si. The mismatch in the Si1xGex to Si lattice causes the smaller lattice constant Si channel to be under compressive strain. The tensile capping layers’ stress on the n-channel is more complicated. The capping layer introduces longitudinal tensile and compressive out-of-plane (z) stress. Using Florida object oriented process simulator (FLOOPS) threedimensional finite element analysis [21, 22], the channel stress is calculated for the n- and p-channel MOSFETs. For the nominal 45 nm transistor used at the 90 nm technology generation, 500 MPa of uniaxial longitudinal compressive stress is introduced into the p-channel MOSFET in the inversion layer. Stress contours for the p-channel device are shown in Figure 5.5.6. For the n-channel MOSFET, 300 MPa of longitudinal tensile and out-of-plane compressive stress is present in the silicon inversion layer. Fortunately, both tensile longitudinal stress and out-of-plane compressive stress raise the energies of the x and y conduction band valleys and lowers the energy of the z valleys. Once the energy separation of the valleys is greater than kT, valley repopulation to the z valleys occurs. The z valleys have the desirable low in-plane and high out-of-plane effective mass and enhance the electron mobility. As a point of comparison, the uniaxial stress process flow described here introduces significantly less nand p-channel stress compared to biaxial (1 to 2 GPa) stress. For hole mobility enhancement the uniaxial stress level is adequate since uniaxial stress offers much larger hole mobility enhancement (as compared to biaxial stress) for reasons described in Chapter 5.3. Hole mobility enhancements greater than 50% occur in the 90 nm generation strained Si process flow. Even higher hole mobility enhancements have been demonstrated on experimental flows but have not yet been integrated into a production flow [23]. The uniaxial stress electron mobility enhancement is significant at 20% [1–3] but less than the best reported biaxial stressed n-channel MOSFETs. For short-channel devices, 10 and 25% improvements in the saturated drive current are obtained for the n- and p-channel MOSFETs, respectively.

© 2006 by Taylor & Francis Group, LLC

5.5-634

The Silicon Heterostructure Handbook

FIGURE 5.5.6 Stress contours for 45 nm gate length transistor with Si0.83Ge0.17 in the source and drain.

Yield and Integration New technology features used to introduce strained silicon (selective strained Si1xGex and NiSi) all have unique yield issues but can be resolved, leading to historical defect density trends. Introducing selective heteroepitaxy has many yield risks: dislocations, loss of selectivity, and blocked Si1xGex epitaxial growth. Since a uniaxial strained silicon structure requires a thick strained Si1xGex layer (100 nm), misfit dislocations in the strained-layer are a major concern. Three yield vehicles using 90 nm design rules have been previously described: 52 Mbit CMOS SRAM [3] and two next generation microprocessors [1]. Figure 5.5.7 shows an SEM die photo of the SRAM and microprocessors. The SRAM contains 330 million transistors. Strained Si is fabricated on all transistors in the die including the transistors in the 6T–SRAM cell. Strained silicon and nickel silicide can yield at historical levels as shown in Figure 5.5.8 [1]. The defect density trend for the 90 nm technology compares favorably to past technology nodes with a two-year offset. Perhaps the biggest yield risk for selective heteroepitaxy is dislocation in the strained layer. Thus for any strained Si structure, it is important to have a device structure that can tolerate slip dislocations without yield loss. Energy is required to form dislocations and this sets the slip system which is {1 1 1} h1 1 0i for heteroepitaxial grown on (1 0 0) silicon [24]. For this system, the dominant type of misfit dislocation is the so-called 608 dislocations that form 608 from the (1 0 0) plane (h1 1 0i dislocation-line direction). An example is shown in Figure 5.5.9 obtained from a 90 nm microprocessor construction report [25]. Since these misfit dislocations are contained in the neutral region of the source and drain, they are expected to have minimal impact on yield, performance, or reliability.

Need for Strained Si in the 90 nm Technology Generation The end of transistor scaling and Moore’s Law has been the topic of many discussions starting in 1970 just shortly after Moore proposed the law [26–29]. This work will not be another prediction about the end of Moore’s law, rather a look at key limiting factors which highlight the need for new material

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

5.5-635

90 nm microprocessors

52 Mbit SRAM Source: 2002 and 2003 IEDM

(~300+ Million transistors) FIGURE 5.5.7 Die photo of 90 nm SRAM and two microprocessors.

Defect reduction trend 0.13 µm 200 mm

0.13 µm 300 mm

90 µm 300 mm

Yield

0.18 µm 200 mm

Source: Ghani, 2003 IEDM

Time FIGURE 5.5.8 yields.

Defect density trend showing 90 nm technology with strained Si and nickel silicide at historical

solutions for continued scaling. As pointed out earlier, planar MOSFETs as small as 10 nm have been fabricated. The MOSFET does not have a hard limit, rather practical considerations require the leakage to be less than 10 to 25% of the total power. Product data show that we are approaching this leakage power limit in the 90 nm technology generation for 45 nm MOSFETs due to a combination of gate and subthreshold leakage [3]. Figure 5.5.10 plots the active power and leakage power for Intel microprocessors [3]. In Figure 5.5.10, from 1960 to 1990, the gate and subthreshold leakage were negligible, which allowed CMOS to dissipate near zero power in the standby mode and resulted in an ideal Si technology. However, in the decade since 1990s, gate silicon dioxide and channel length scaling to the nanoscale region resulted in the off-state leakage approaching 10 to 25% of the total power. Figure 5.5.11 shows the

© 2006 by Taylor & Francis Group, LLC

5.5-636

The Silicon Heterostructure Handbook

FIGURE 5.5.9 Dislocation in epitaxial strained Si0.83Ge0.17.

1000 Processor power (Watts) - Active and leakage

Power / (W)

100 Active power

10

Projected change?

1 Leakage

0.1 0.01 0.001 1960

L GATE = 45 nm

Source: Intel Technology (Thompson, 1999 IEDM) 1970

1980

1990

2000

2010

FIGURE 5.5.10 Active and leakage power versus time.

SiO2 gate-scaling trend, which has reached a tunneling leakage limit at 1.2 nm. Fortunately, new materials can circumvent the gate and subthreshold leakage limits by improving performance without oxide or channel length scaling (strained Si being one technique).

5.5.3 Future Direction of Strained Silicon In the current 90 nm generation, moderate levels of strain have resulted in mobility enhancements of 20 and 50% for n and p channels, respectively. Experimental and theoretical work suggests much larger mobility enhancement is achievable at higher strain. Ratios of stressed-to-unstressed mobilities of 4 and 1.7 have been reported experimentally for holes and electrons [30], respectively. Thus, an obvious evolution of this process flow going forward is integrating higher levels of strain. Higher channel strain is possible by increased strain in the (i) nitride-capping layer, (ii) epitaxial Si1xGex by higher Ge concentration, or (iii) fabrication of the epitaxial Si1xGex closer to the Si channel. More complex

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

5.5-637

FIGURE 5.5.11 SiO2 gate oxide thickness versus time.

Si1−y Gey Si

Si1−x Cx

N-channel

N-channel Si1−y Gey

Si1−x Cx Silicon

Germanium

FIGURE 5.5.12 Two new device structures to introduce channel stress.

structures to integrate strain are also possible. Two examples are shown in Figure 5.5.12. Epitaxial SiC in the source and drain of n-channel MOSFETs offer higher channel strain than the capping-layer approach. Similarly, strained Si1xGex in the source and drain of a Ge channel device can be used for uniaxial tensile stress. There are also numerous other techniques and process steps to introduce strain. A few examples are high-strain capping layers introduced before poly-Si gate crystallization [31], high-stress shallow-trench isolation, and silicide [32]. In the near term for future technology generations, combinations of all these techniques will be used. This will place additional restrictions and requirements on new structures and materials. For example, for alternate device structures and materials such as FinFET, tri-gate and high k-gate dielectrics to be competitive with strained planar CMOS, strain or some other mobility enhancing technique [33] is needed in these structures as well. After integrating high levels of strain for significant mobility enhancement, the external resistance of the MOSFET will next need to be addressed. This can be seen already in Figure 5.5.13 where the strained, improved linear drive current is plotted versus channel length [34]. As seen in Figure 5.5.13, for channel

© 2006 by Taylor & Francis Group, LLC

5.5-638

The Silicon Heterostructure Handbook

60 Source: 2004 Trans. ED

600 % I DLIN gain

40 500 30

400 300

NMOS

20

200 P-channel Stress

10

Average channel stress / MPa

700

PMOS

50

100

0 10

102

103

104

Channel length (nm)

FIGURE 5.5.13

Strained Si improved linear drive current and average p-channel stress versus channel length.

lengths below 40 nm, the linear current improvement saturates, even though the Si1xGex and capping layer increases the strain at smaller channel lengths. Part of the reason this occurs is the growing importance of the external resistance. Until recently, state-of-the-art MOSFETs had low external resistance due to the adoption of selfaligned silicide for contact resistance reduction and near solubility limited abrupt source–drain extensions made possible by shallow dopant implants, co-implantation [35], and ultrashort rapid thermal processing [36]. Typical n-channel MOSFET external resistances for the 250 to 180 nm technology generations are 200 V mm, which is small compared to the 1500 to 2000 V mm channel resistance at these nodes. However, significant enhanced mobility via strain along with channel length scaling is dramatically reducing the channel resistance to a point where the external resistance can no longer be neglected. Including external resistance, the MOSFET switch can be represented as shown in Figure 5.5.14. The total resistance (performance) of the MOSFET switch can be expressed as VDS LEFF þ RSD ¼ RCHANNEL þ RSD ¼ ID WEFF mCOX ðVGS VT Þ LEFF þ RSD ¼ WEFF mCOX (VGS VT )

RTOTAL ¼

Historically, the ratio of RSD/RCHANNEL has been less than 20%. However, as pointed out in the previous sections, standard channel length scaling and strained Si all significantly lowered RCHANNEL. The net effect of these trends is MOSFETs soon will be severely limited by the source–drain resistance. Extrapolation of the current trends shows that in a few year the ratio of RSD/RCHANNEL will be greater than 1.

5.5.4 Summary The era of simple MOSFET dimension scaling for improved performance is over. Strained Si is the next material change to extend Moore’s law. At the 90 nm technology generation, selective strain epitaxial Si1xGex and a tensile capping layer are used to introduce strain.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

VGS

Gate

Salicide

G D

S

K. K. Ng (1986.)

Source

SDE

ID VDS

5.5-639

Current flow Raccumulation

Rcontact

Rspreading Rshunt

FIGURE 5.5.14 MOSFET switch include extrinsic and intrinsic resistance.

In the near term, advance logic technologies mobility enhancement through strain is expected to be a key performance enabler. The addition of strained Si to the planar MOSFET raises the bar for any nonclassical device structure to replace the industry workhorse.

Acknowledgments The author would like to thank the efforts of his former colleagues in the Portland Technology Development, Technology Computer Aided Design, and in the Corporate Quality and Reliability Groups of Intel. The author also acknowledges the support and encouragement from Melanie PecinsThompson, Mark Bohr, Robert Chau, Tahir Ghani, Kaizad Mistry, Sunit Tyagi, and William Holt.

References 1. T Ghani et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp. 978–980. 2. SE Thompson et al. A logic nanotechnology featuring strained silicon. IEEE Electron Dev. Lett. 25:191–193, 2004. 3. S Thompson et al. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm2 SRAM Cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64. 4. GE Moore. No exponential is forever. ISSCC, San Francisco, CA, 2003. 5. GE Moore. Progress in digital integrated electronics. IEDM Tech. Dig. 11–13, 1975. 6. GE Moore. Cramming more components onto integrated circuits. Electronics 38:114–117, 1965. 7. B Doyle, R Arghavani, D Barlage, S Datta, M Doczy, J Kavalieros, A Murthy and R Chau. Transistor elements for 30nm physical gate lengths and beyond. Intel Technol. J., Vol.6, 2002. 8. Z Ren, MV Fischetti, EP Gusev, EA Cartier, and M Chudzik. Inversion channel mobility in high[kappa] high performance MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp. 33.2.1–33.2.4. 9. V Chan et al. High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003, pp. 77–80. 10. CS Smith. Piezoresistance effect in germanium and silicon. Phys. Rev. 94:42–49, 1954. 11. C Xiangdong, L Kou-chen, S Ray, and S Banerjee. Bandgap engineering in vertical P-MOSFETs. Solid-State Electron. 45:1939–1943, 2001. 12. C Xiangdong, L Kou-Chen, QC Ouyang, SK Jayanarayanan, and SK Banerjee. Hole and electron mobility enhancement in strained SiGe vertical MOSFETs. IEEE Trans. Electron Dev. 48:1975–1980, 2001.

© 2006 by Taylor & Francis Group, LLC

5.5-640

The Silicon Heterostructure Handbook

13. B Hoeneisen and CA Mead. Fundamental limitations in microelectronics — I. MOS technology. Solid-State Electron. 15:819–829, 1972. 14. MC Ozturk, L Jing, M Hongxiang, and N Pesovic. Advanced Si1xGex source/drain and contact technologies for sub-70 nm CMOS. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 375–378. 15. MC Ozturk, N Pesovic, I Kang, J Liu, H Mo, and S Gannavaram. Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon–germanium technology. Extended Abstracts of the Second International Workshop on Junction Technology, 2001, pp. 77–82. 16. O Qiqing et al. A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current. IEEE Trans. Electron Dev. 47:1943–1949, 2000. 17. K Mistry et al. Delaying forever: Uniaxail strained silicon transistors in a 90 nm CMOS technology. Symp. VLSI Tech. Dig., Hawaii, 2004. 18. K Rim et al. Characteristics and device design of sub-100 nm strained Si N- and pMOSFETs. Symp. VLSI Tech. Dig., Hawaii, 2002, pp. 98–99. 19. S Ito et al. Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2000, pp. 247–250. 20. A Shimizu et al. Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2001, pp. 433–436. 21. ME Law and SM Cea. Continuum based modeling of silicon integrated circuit processing: an object oriented approach. Computat. Mater. Sci. 12:289–308, 1998. 22. S Cea and M Law. Multidimensional nonlinear viscoelastic oxidation modeling. Simulat. Semicond. Dev. Process. 6: 139–142, 1995. 23. PR Chidambaram et al. 35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS. Symp. VLSI Tech. Dig., Hawaii, 2004. 24. EA Fitzgerald. Dislocations in strained-layer epitaxy: theory, experiments, and applications. Mater. Sci. Rep. 7:88–142, 1991. 25. www.chipworks.com. Intel BX80546PG2800E PentiumTM 4 Prescott Microprocessor Structural Analysis, 2004. 26. B Hoeneisen and CA Mead. Limitations in microelectronics — II. Bipolar technology*1. Solid-State Electron. 15:891–897, 1972. 27. B Hoeneisen and CA Mead. Limitations in microelectronics — II. Bipolar technology. Solid-State Electron. 15:891–897, 1972. 28. B Hoeneisen and CA Mead. Fundamental limitations in microelectronics — I. MOS technology*1. Solid-State Electron. 15:819–829, 1972. 29. B Hoeneisen and CA Mead. Fundamental limitations in microelectronics — I. MOS technology. Solid-State Electron. 15:819–829, 1972. 30. JL Hoyt et al. Strained silicon MOSFET technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 23–26. 31. C-H Chen et al. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application. Symp. VLSI Tech. Dig., Hawaii, 2004. 32. A Steegen et al. Silicide induced pattern density and orientation dependent transconductance in MOS transistors. IEDM Tech. Dig. 497–500, 1999. 33. M Yang et al. High performance CMOS fabricated on hybrid substrate with different crystal orientations. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2003. 34. SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, T Ghani, G Glass, T Hoffman, CH Jan, C Kenyon, J Klaus, K Kuhn, Z Ma, B Mcintyre, K Mistry, A Murthy, B Obradovic, R Nagisetty, P Nguyen, S Sivakumar, R Shaheed, L Shifren, B Tufts, S Tyagi, M Bohr,

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Intel’s 90 nm Logic Technologies

5.5-641

and Y El-Mansy. A 90-nm logic technology featuring strained-silicon. IEEE Electron Dev. Lett. 51(11): 1790–1797, 2004. 35. ME Law, GH Gilmer, and M Jaraiz. Simulation of defects and diffusion phenomena in silicon. MRS Bulletin 25:45–50, 2000. 36. R Singh, M Fakhruddin, and KF Poole. Rapid photothermal processing as a semiconductor manufacturing technology for the 21st century. Appl. Surf. Sci. 168:198–203, 2000.

© 2006 by Taylor & Francis Group, LLC

6 Other Heterostructure Devices 6.1 Overview: Other Heterostructure Devices J.D. Cressler ....................................... 6.1-645 ¨ and U. Gennser.......... 6.2-647 6.2 Resonant Tunneling Devices S. Tsujino, D. Grutzmacher, Introduction . Principle of Resonant Tunneling . Applications of Resonant Tunneling Devices . Resonant Tunneling in Si–SiGe Heterostructures . Resonant Interband Tunneling Diodes 6.3

IMPATT Diodes E. Kasper and M. Oehme .............................................................. 6.3-661 Introduction . Structure and Principle Function . SiGe — SIMMWIC . Extensions of the Concept . Growth and Process Requirements . Summary

6.4

Engineered Substrates for Electronic and Optoelectronic Systems E.A. Fitzgerald .............................................................................................. 6.4-679 Lattice-Matched Substrate World . Limitations of Lattice-Matched Systems . Age of Lattice-Mismatched Substrate Engineered Materials . Nanoengineered Substrates for MOSFETS . Engineered Substrates for III–V–Si Integration . Future Engineered Substrates . Market Adoption of Engineered Substrates

6.5

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy R. Hull................................................................................................ 6.5-699 Scope of this Chapter . Introduction . Roughening and Islanding as a Strain-Relief Mechanism . Equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System . Non-equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System . Controlled Growth of Quantum Dot Arrays . Potential Nanoelectronic and Nanophotonic Device Applications . Summary

6.1-643 © 2006 by Taylor & Francis Group, LLC

6.1 Overview: Other Heterostructure Devices

John D. Cressler Georgia Institute of Technology

It is perhaps not surprising that when crystal growers begin to achieve even moderate success in producing device-quality films, device engineers swoop down and rush to demonstrate a host of devices from such materials. In practice, the proof that crystal growers have achieved success often lies in the ability of such functional devices to be realized! While, clearly, transistors are the core building blocks of modern electronic systems, there are a number of other novel device types that become accessible with bandgap engineering techniques. Two such examples are represented here. In Chapter 6.2, ‘‘Resonant Tunneling Devices,’’ S. Tsujino of the Paul Scherrer Institute discusses achieving negative differential resistance in Si–SiGe heterostructures and the types of devices that can be produced from them. In Chapter 6.3, ‘‘IMPATT Diodes,’’ by E. Kasper et al. of the University of Stuttgart, gives an overview of this important class of microwave sources. Clearly, it is a healthy sign for the silicon heterostructure field that success has been achieved in a number of such novel devices. While those devices may not as yet challenge the performance of their III–V cousins, refinements are underway, and much work remains to be done. Substrate engineering is an important subject in all of bandgap engineering, regardless of the material system. For silicon heterostructures, in particular, the underlying substrate lies at the very core of the FET performance, and bandgap engineering is unique in the sense that enormous crystals can be grown (300 mm in 2005 and counting), potentially giving rise to new and interesting applications. In Chapter 6.4, ‘‘Engineered Substrates for Electronic and Optoelectronic Applications,’’ by E. Fitzgerald of MIT, a number of unique substrate techniques are described for potential electronic and optoelectronic applications. Finally, the cliched buzzword ‘‘nanotechnology’’ means many things to many people, but it is worthwhile noting that nanostructures can in fact be produced in Si–SiGe. In Chapter 6.5, ‘‘SelfAssembling Nanostructures in Ge(Si)/Si Heteroepitaxy,’’ by R. Hull of the University of Virginia, discusses self-assembled nanostructures and their potential for applications.

6.1-645 © 2006 by Taylor & Francis Group, LLC

6.2 Resonant Tunneling Devices 6.2.1 6.2.2 6.2.3 6.2.4

Resonant Tunneling in Double Barrier Structures . Resonant Tunneling in Strain-Compensated and High-Ge Concentration Si–SiGe Superlattices and Quantum Cascade Structures . Resonant Tunneling in Quantum Dot Structures

Soichiro Tsujino and Detlev Gru¨tzmacher Paul Scherrer Institute

Ulf Gennser CNRS-LPN

Introduction............................................................... 6.2-647 Principle of Resonant Tunneling.............................. 6.2-648 Applications of Resonant Tunneling Devices ......... 6.2-650 Resonant Tunneling in Si–SiGe Heterostructures ........................................................ 6.2-651

6.2.5

Resonant Interband Tunneling Diodes.................... 6.2-653

6.2.1 Introduction When electrons are confined within a semiconductor thin film with a thickness of the order of the de Broglie wavelength, the wave nature of the electrons becomes important, thus quantum size and tunneling effects will influence the optical and electronic properties of the material. In semiconductor heterostructures, fabricated by stacking films of several compatible semiconductor materials with different bandgaps, one can create almost arbitrary potential profiles. Suitable designs of semiconductor heterostructures permit the observation of various tunneling effects, in particular resonant tunneling. The principle of resonant tunneling has been known for a long time [1]. To realize semiconductor resonant tunneling devices such as resonant tunneling diodes (RTDs), the control of the film deposition with atomic layer thickness accuracy and the realization of semiconductor quantum well–superlattice structures with planar and sharp heterointerfaces are essential prerequisites. These are warranted by modern crystal growth technology such as molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). In Si–SiGe heterostructures, the band alignment has been shown to be of type-II, i.e., the electrons and holes are confined in different layers. The built-in strain has a large influence on the band alignment. Therefore, the potential profile can be tailored by depositing heterostructures on Si substrate or on relaxed SiGe buffer layers. The majority of Si–SiGe tunneling devices have been fabricated in the valence band or through interband tunneling. Fewer papers have reported on electron RTDs since the conduction band offset is too small unless heterostructures are deposited on relaxed buffers and because of the large electron tunneling mass, a factor of 4 to 5 larger than hole mass, which may require very thin barriers. This chapter is organized in the following manner. In Section 6.2.2, we describe the principle of resonant tunneling in a simplified model, and in Section 6.2.3 possible applications of the resonant tunneling devices are summarized. In Section 6.2.4, we review reported studies on resonant tunneling in 6.2-647 © 2006 by Taylor & Francis Group, LLC

6.2-648

The Silicon Heterostructure Handbook

double barrier structures, superlattices, and quantum dots. Finally, in Section 6.2.5, we summarize recent developments on resonant interband tunneling devices.

6.2.2 Principle of Resonant Tunneling Here, we briefly describe the resonant tunneling observed in the current–voltage (I–V) characteristics of double barrier RTDs [2–5]. In a quantum well, i.e., in a thin film sandwiched by two barrier layers, quasi-confined states are formed at energies determined by the thickness W of the center layer, that is, when half integer multiples of the electron wavelength are approximately equal to W. A typical situation of a double barrier RTD at a small bias is sketched in Figure 6.2.1(a). When a bias is applied to the structure, a small current (Jex) flows, which is attributed to tunneling through the whole stack of layers comprising two barriers and the quantum well. The current increases strongly (JRT in Figure 6.2.1(b)), whenever the energy of the incident electron coincides with the energy of one of the confined states, for example the Er state in Figure 6.2.1(a). This resonance enhancement of the electron transmission is analogous to that for photons in Fabry–Perot interferometers. At resonance, the amplitude of the incident wave builds up in the center layer by the positive interference between the incident wave and the wave reflected from the second barrier, and consequently the transmission through the structure is reinforced. Further increase of the bias detunes the resonance and the current decreases sharply, creating the negative differential resistance (NDR), which is sketched in Figure 6.2.1(b). The transmission function for a carrier at an energy close to the resonance E Er can be written approximately by a Lorenzian, T (E)

GL GR G G L þ G R (E Er )2 þ (G=2)2

(6:2:1)

The width G ¼ GL þ GR of the level is given by the decay rate of the resonant state. GL/h ¯ and GR/h ¯ represent the tunneling escape rate of a carrier in the confined state via the left and the right barrier, respectively [3, 4]. In layered structures, the motion of the carriers in the plane of the layer is characterized by plane waves and the tunneling process conserves the in-plane momentum ¯hkk in the absence of scattering [2, 4]. For ECL < Er < EFL, where ECL is the band edge in the emitter and EFL is the Fermi level of the emitter, tunneling is possible only for carriers whose momenta ¯hkz lie in a disk corresponding to kz ¼ qR (shaded disk in Figure 6.2.1(c)), where qR is given by {2m*(Er ECL)/h ¯ 2}1/2 and m* is the effective mass of the carrier. In this range, the current is approximately given by (2e/h ¯ )T0N(DE) where T0 ¼ GLGR/(GLþ GR), L 2 N(DE) ¼ m* DE /(ph ¯ ) the supply function and DE ¼ (EF Er). As the emitter potential rises, the

(a)

(b)

(c)

E LF E LC

Er

ER F

eV z

ER C

Current density, J

kz = qR JRT

kF

kz

Jex Bias voltage, V

FIGURE 6.2.1 (a) Schematic band-diagram of a double barrier resonant tunneling diode when bias V is applied between the emitter (denoted by L) and the collector (denoted by R). (b) Expected current–voltage characteristics of the device. (c) A Fermi sphere of electrons in the emitter.

© 2006 by Taylor & Francis Group, LLC

6.2-649

Resonant Tunneling Devices

number of available electrons increases and N(DE) reaches the maximum value equal to m* (EFL ECL)/ L 2 (ph ¯ ) when qR is equal to 0. When EC rises above Er , there are no electrons in the emitter at zero temperature, which can tunnel while conserving ¯hkk. In real devices, the external voltage V needed to shift the emitter states relative to the quantum well states, DE, depends not only on the thicknesses of the different layers (quantum well, barriers, and doping offset), but also on space–charge effects due to charge accumulation in the emitter and in the quantum well. A linear relationship is often assumed, DE / aV, with the lever factor a determined empirically. The first Si–SiGe RTDs were grown on (1 0 0) oriented Si substrates and consisted of a compressively strained Si1xGex quantum well, Si barriers and SiGe emitter and collector layers [6]. An example of the heavy hole valence band potential profile of such a device (x ¼ 0.26) calculated self-consistently at a bias of 0.13 V is shown in Figure 6.2.2 [7]. The Ge compositions of the emitter and the collector layers of the device are graded toward the surface and the substrate, respectively, in order to create a smooth potential profile. The IV character of the RTD shows resonances induced by the confined heavy and light hole states in the quantum well (Figure 6.2.3). By varying the thickness of the quantum well, the resonant peak positions shift systematically (Figure 6.2.4). A good agreement between the calculated peak positions (solid curves in Figure 6.2.4) and the experiment is achieved by using a lever factor a of 4.2. Although the above description of the IV characteristics of RTDs is simple and intuitive, a quantitative description of the IV curves requires the inclusion of other effects [5], such as nonresonant background current (Jex in Figure 6.2.1(b)), elastic and inelastic scattering during the tunneling processes [3, 4], charge build-up and multiband effects. The inclusion of band mixing in the presence of strain and scattering is important, especially for hole tunneling, since the quantized states of holes in quantum wells originate from three different bands: heavy hole (HH), light hole (LH), and split-off hole (SO). The in-plane dispersions of these states are strongly influenced by the interaction between the

(a)

0.4

Doping (p+) SiGe ramp 5%→26%

26%

SiGe well Si

Doping (p+) SiGe spacer SiGe ramp Si

0% 26% 0% 26% 26%→ 5%

E (eV)

0.2

Ge:

SiGe spacer

0.0

(b) −0.2 400

600 800 Distance (A)

1000

O

FIGURE 6.2.2 (a) A TEM picture of a cross section of an RTD with asymmetric spacer layers. (b) The layer sequence and the valence band edge calculated self-consistently for a bias of 0.13 V, including heavy hole states only. (From G. Dehlinger, U. Gennser, D. Gru¨tzmacher, T. Ihn, E. Mu¨ller, and K. Ensslin. Thin Solid Films 369: 390–393, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

6.2-650

The Silicon Heterostructure Handbook

Current (mA)

10.0 5.0

HH2 HH1 LH1

0.0 −15.0

⫻100

−10.0 −0.6 −0.4 −0.2 0.0 0.2 Voltage (V)

0.4

0.6

FIGURE 6.2.3 Current–voltage characteristics of a symmetric RTD measured at 4 K. The low voltage region is enlarged by a factor of 100 to show the HH1 peak. (From G. Dehlinger, U. Gennser, D. Gru¨tzmacher, T. Ihn, E. Mu¨ller, and K. Ensslin. Thin Solid Films 369: 390–393, 2000. With permission.)

LH2 HH2 LH1 HH1

Peak voltage (mV)

800 600 400 200 0

20 30 40 50 60 70 80 90 100 o

Well width (A)

FIGURE 6.2.4 Relation between confinement shift and the well width for a series of RTDs. Dots show the measured resonance-positions and the solid lines are calculated values. (From G. Dehlinger, U. Gennser, D. Gru¨tzmacher, T. Ihn, E. Mu¨ller, and K. Ensslin. Thin Solid Films 369: 390–393, 2000. With permission.)

three valence bands [8]. Furthermore, a triangular potential is often formed in the emitter, leading to the formation of quantized emitter states. Therefore, the supply function has to be modified accordingly [5].

6.2.3 Applications of Resonant Tunneling Devices RTDs have been an important instrument for exploring the physics of semiconductor nanostructures. At the same time, because of the extreme nonlinearlity of the IV characteristics and high operation frequencies, up to THz [9], RTDs have been intensively studied for several high-speed logic circuit applications [4, 5, 10] and in high-frequency oscillator-switching applications [11]. The employment of RTDs in integrated circuits has several advantages, including reduced number of components and circuit complexity for a given function, reduced power consumption, and high speed. Therefore, many applications have been studied: a low power consumption SRAM cell with a single transistor [12], multivalued logic [13], monostable–bistable transition logic gates [14], a compact RTD/HBT circuit with highfrequency and low power consumption operation for wireless communication [15], and analog-to-digital converters [16]. Two-terminal logic circuits can be constructed using solely RTDs [17], but lack of current gain restricts the fan-out of the circuits and limits the applications. Most promising is the integration of RTDs with high-frequency transistors such as heterobipolar transistors (HBT) and heterostructure fieldeffect transistors (HFET), which would offer flexibility in circuit design, and enable a more extensive basic function library [10].

© 2006 by Taylor & Francis Group, LLC

Resonant Tunneling Devices

6.2-651

One of the figures-of-merit of RTDs for device application is the peak-to-valley current ratio (PVR), which measures the ratio of a current maximum (at resonance) to the following current minimum at higher bias. High PVRs (>100) have been achieved in III–V semiconductor RTDs and using those, working prototypes of RTD-based circuits have been demonstrated. For commercial applications, however, technical challenges such as the uniformity of the layer deposition across the wafers have to be surmounted [5, 10]. The PVR of Si–SiGe double barrier RTDs has not reached a competitive level, mainly due to rather low band offsets and high effective carrier masses compared to III–V semiconductors, even though high-speed SiGe transistors, especially HBTs, have been successfully developed (see the chapter on HBTs). As an alternative approach to RTDs, several groups have developed a SiGe resonant interband tunneling diode (RITD) (see section ‘‘Resonant Interband Tunneling Diodes’’). Another important application of resonant tunneling is in quantum cascade lasers based on intersubband optical transitions [18]. In this unipolar device, the active layer consists of a series connection of several cells. Each cell is essentially a four-level system, where population inversion is realized by resonant tunneling to the upper transition state, and the upper state itself is spatially confined by Fabry–Perot reflection between superlattice barriers to achieve a high injection efficiency and long lifetime. Si–SiGe quantum cascade structures have been studied to realize Si-based lasers [19–21].

6.2.4 Resonant Tunneling in Si–SiGe Heterostructures Resonant Tunneling in Double Barrier Structures Resonant tunneling in Si–SiGe double barrier structures has been reported for both electrons and holes. Among these, most have focused on hole transport in the valence band. In fact, the first SiGe RTDs were demonstrated in p-type double barrier structures by Liu et al. [6] and by Rhee et al. [22] by taking advantage of the larger valence band discontinuity compared to the conduction band offset. Devices have been prepared either by MBE or by various CVD methods. For example, Zaslavsky et al. [23] reported a double barrier diode with a 2.3-nm thick compressibly strained Si0.75Ge0.25 quantum well and 5-nm thick unstrained Si barriers deposited by atmospheric CVD on Si substrates. This RTD showed a PVR of 4 at 4.2 K, comparable to the best results observed in MBE-grown devices. The observation of NDR at room temperature has not been possible in p-type Si–SiGe structures, due to the increased valley current at high temperature by thermally assisted tunneling through higher resonant states [24, 25]. Compared to the hole transport, the resonant tunneling of electrons in the conduction band has attracted less attention [26–31]. Although observation of NDR at room temperature has been reported in these devices, the physics of electron resonant tunneling is not well understood and requires further study. In particular, a demonstration of confinement shifts of the resonances is still lacking. Electron RTDs using alternative barriers such as SiO2 [32, 33] or CaF2 lattice matched to Si(1 1 1) substrates [34] have been studied because of the large conduction band offsets available in those systems. Momentum conservation of the tunneling process has been studied by magnetotunneling experiments. Magnetotunneling is especially useful in valence band RTDs because the mixing between HH, LH, and SO bands leads to highly nonparabolic and anisotropic subbands [8, 35]. Resonant tunneling with a magnetic field B applied parallel to the current, along the growth direction, is supposed to occur between Landau levels having the same Landau-level index. A modulation of the IV characteristics of n-type RTDs has been explained by phonon-assisted tunneling which breaks the Landau-level index conservation. In p-type Si–SiGe RTDs Landau-level tunneling has been shown to occur even without phonons due to the mixing of Landau levels in the valence bands [23, 36, 37]. With the B-field perpendicular to the current, the resonant tunneling peak is shifted because the conservation of the canonical momentum in the tunneling process results in a displacement of the energy dispersion in the emitter states with respect to the quantum well states (Figure 6.2.5, left). This has allowed the mapping of the dispersion relations of the hole-subbands. The anisotropy of the hole-subbands has been studied by following the relation between the resonant peak position and the angle of the B-field within the

© 2006 by Taylor & Francis Group, LLC

6.2-652

The Silicon Heterostructure Handbook

160

<100>

HH0

<110>

EF

(1)

∆VP (mV)

120 <100> 80

(2) <110>

40 ∆k−l ~ B−l

0 8

14

20 B−l (T)

26

32

FIGURE 6.2.5 Schematic diagram (left) of the energy alignment of the occupied heavy-hole states in the emitter (shaded) and a HH0 subband in the quantum well under magnetic field B? applied parallel to the quantum well plane, and HH0 peak voltage shift (right) DVp versus in-plane B?-field oriented along the h1 1 0i and h1 0 0i directions in a pseudomorphic Si–SiGe RTD. (From A. Zaslavsky, T.P. Smith III, D.A. Gru¨tzmacher, S.Y. Lin, and T.O. Sedgwick. In-plane valence-band nonparabolicity and anisotropy in strained Si–Ge quantum wells. Phys. Rev. B 48: 15112–15115, 1993.)

quantum well plane [38, 39]. Using this technique, a large anisotropy of the dispersion between h1 0 0i and h1 1 0i direction was detected as shown in Figure 6.2.5 (right). To describe the hole tunneling properly, a multiband model must be employed. In such models, the momentum ¯hkk parallel to the layers needs to be taken into account since the mixing between HH, LH, and SO states is very sensitive to it, and mixing changes the transmission probability dramatically [8, 35]. Band mixing occurs between HH and LH subbands only at kk 6¼ 0 and depends strongly on the separation of the states and their nonparabolicity, thus the strain, the quantum well width, and the band offset have an impact on the strength of the band mixing. The dominant peak in the IV characteristics of pseudomorphic RTDs (see Figure 6.2.3) that is assigned to tunneling via light hole states is susceptible to severe band-mixing effects. It has been shown that the peak current in p-type GaAs–AlGaAs RTDs is dominated by tunneling via off-zone center (kk 6¼ 0) states [40], though a similar demonstration for SiGe RTDs has not yet been done. In contrast to the pseudomorphic RTDs, recent experiments in high-Ge concentration strain-compensated RTDs suggest that the resonant tunneling from HH emitter states through LH quantum well states is extremely weak. This might be attributed to the difference in strain and to the splitting of the HH and LH/SO band by more than 80 meV [41].

Resonant Tunneling in Strain-Compensated and High-Ge Concentration Si–SiGe Superlattices and Quantum Cascade Structures Resonant tunneling and miniband transport are key ingredients for quantum cascade structures [18, 42]. Recently, vertical hole transport in high Ge content strain-compensated SiGe–Si quantum wells and superlattices on relaxed buffer substrates have been studied for application in Si-based quantum cascade lasers for the midinfrared wavelength range [21, 43]. The samples are composed of alternating compressively strained QWs and tensile strained Si barriers with an average Ge concentration equal to the value in the relaxed buffer substrate [44]. In this way, it is possible to grow a thick active layer without suffering from the critical thickness limitation [45–47]. Strain-compensated superlattices and quantum cascade structures exceeding 1 to 2 mm in thickness have been demonstrated by depositing Si–Si0.2Ge0.8 layers on Si0.5Ge0.5 relaxed buffer substrates using solid source MBE. By employing low growth temperatures of 3008C, islanding within the high germanium content SiGe layers was kinematically suppressed. Consequently, highly planar and atomically sharp Si–Si0.2Ge0.8 interfaces were realized (Figure 6.2.6). The interface roughness of the samples was found to be less than 0.3 to 0.4 nm [48, 49].

© 2006 by Taylor & Francis Group, LLC

6.2-653

Resonant Tunneling Devices

Si Si0.2Ge0.8 Si Si0.2Ge0.8 Si

20 nm

FIGURE 6.2.6 High-resolution cross-sectional TEM picture of a strain-compensated superlattice with 30 periods of 8.3-nm thick Si0.2Ge0.8 quantum wells separated by 5-nm thick Si barriers deposited on (1 0 0) Si0.5Ge0.5 relaxed buffer substrate by molecular beam epitaxy at low temperature. Overview (left) and magnified view (right). (Courtesy of E. Mu¨ller.)

Vertical transport in symmetrically strained superlattices was first studied by Park et al. [50]. They observed NDR in their p-type Ge0.4Si0.6Si superlattice on Ge0.2Si0.8 relaxed buffer, which was ascribed to the tunneling via LH minibands. Tsujino et al. [43] studied strain-compensated SiSi0.2Ge0.8 superlattices on Si0.5Ge0.5 relaxed buffers having different tunneling coupling strength (Figure 6.2.7). They observed current peaks originating from sequential resonant tunneling between neighboring quantum wells in weakly coupled superlattices and transport via 50 meV wide HH miniband in strongly coupled superlattices [51].

Resonant Tunneling in Quantum Dot Structures Resonant tunneling through quantized states at lower dimensions has been explored by reducing the lateral dimension of RTDs. When the diameter of a p-type pseudomorphic SiSi0.75Ge0.25 RTD was reduced below 0.1 mm, the differential conductance showed additional structure, ascribed to the quantization of the in-plane motion [52, 53]. Further study revealed that these conductance peaks are due to the resonant tunneling through quantum ring states along the rim of the mesas created by inhomogeneous strain relaxation on the lateral surface of the device [54]. In a smaller device with a diameter of 45 nm, single-hole tunneling and Coulomb blockade via quantum ring states were observed [55]. Resonant tunneling through self-assembled Si quantum dots buried in SiO2 [56] and self-assembled Ge quantum dots [57] has been reported (see the chapter on self-assembled quantum structures in SiGe–Si). Tunneling and Coulomb blockade through laterally defined SiGe quantum dots have also been detected by in-plane transport [58, 59].

6.2.5 Resonant Interband Tunneling Diodes The main idea of resonant interband tunneling diodes (RITD) is to combine interband tunneling in degenerately doped p–n diodes, i.e., Esaki tunnel diodes [60], with the confined states in quantum wells [61]. At a bias close to zero, resonant current flows from a quantized electron state in the n-side to a quantized hole state in the p-side by interband tunneling. When the bias is set at the out-of-resonance condition, the large interband energy gap blocks the current. Therefore, a large PVR is expected in RITDs compared to RTDs where the available barrier heights are only a fraction of the bandgap.

© 2006 by Taylor & Francis Group, LLC

6.2-654

The Silicon Heterostructure Handbook

0.15 V-LH top 0.10

LH-2

0.00 Energy (eV)

Current density (A/cm2)

0.05

−0.05 HH-3 LH-1

−0.10

700 600 500 400 300 200 100 0 40

Current

Sample A φ6 µm, 77 K

HH1-HH2/LH1

Sample B 30

Differential conductance (dl/dv)

HH-miniband

φ6 µm, 77 K

20

16 A/cm2

10 0 16

−0.15

Sample C 12

HH-2 HH-1

φ10 µm, 77 K

3 20

3 A/cm2

8

−0.20

4 −0.25 (a)

A

B

C 0

1

2 3 4 5 6 7 8 Quantum well thickness, L (nm)

9 (b)

0

1

2 Voltage (V)

3

4

FIGURE 6.2.7 (a) The dependence of energetic position of hole states on the quantum well thickness W in straincompensated Si Si0.2Ge0.8 superlattices on Si0.5Ge0.5 relax buffer substrates with constant ratio between W and the thickness Lb of the Si barriers (Lb ¼ 0.6W). The energies are with respect to the valence band edge of unstrained Si0.5Ge0.5. Shaded area shows the miniband formation. (b) Current–voltage (I–V) characteristics of strain-compensated Si–Si0.2Ge0.8 superlattice samples A, B, and C with 30 periods of quantum wells (W ¼ 2, 5, and 8.3 nm respectively) at 77 K. Their expected hole states are marked by vertical lines in (a). The observed I–Vs show peaks originating from sequential resonant tunneling between neighboring wells (samples B, C) and periodical peaks indicating the formation of the electrical field domains (sample C in the range of 1–2 V). When W and Lb are further reduced, HH1 states form a 50 meV wide miniband, giving rise to a conductance peak around 0 V (sample A).

Recently SiGe RITDs have been intensively studied because of their potential to fulfill the requirements of room temperature operation and high-peak current densities [62–68]. A basic structure consists of an undoped SiGe tunneling layer, sandwiched by d-doped p and n layers with or without spacer layers (Figure 6.2.8). Two-dimensional states are formed at the d-doped layers due to the Coulomb potential. Very high sheet doping concentrations of the order of 1014 cm2 with sharp doping profiles are realized by MBE at low growth temperatures. Maximum dopant incorporation with sufficiently sharp profiles is achieved at growth temperatures of 4608C for Si:B and 3708C for Si:P [67]. Because of the low growth temperature, postgrowth annealing at moderate temperatures (6008C) has proven to be crucial to lower the valley current and obtain diodes exhibiting pronounced NDR at room temperature (Figure 6.2.9). Duschl et al. [67] reported SiGe RITDs with a PVR of 4.8 and a peak current density Jp of 30 kA cm2. They also fabricated RITDs with PVR of 6 but at reduced Jp of 1 kA cm2 [68]. The trade-off between PVR and Jp was systematically studied by Jin et al. (Figure 6.2.10) [69]. Narrowing down the film thickness between the two d-doped layers leads to an increase of Jp but to a reduction of the PVR due to enhanced tunneling via defect states. By optimizing the sample structure, they fabricated SiGe RITD having Jp up to 151 kA cm2 with a PVR of 2 at room temperature.

© 2006 by Taylor & Francis Group, LLC

6.2-655

Resonant Tunneling Devices

100 nm n+Si P delta-doping plane L1 nm undoped Si L2 nm undoped Si0.6Ge0.4

B delta-doping plane

1 nm p+ Si0.6Ge0.4 80 nm p+ Si p+ Si

(100) Substrate

V = 0.4 V

1

Xz Xxy

Energy (eV)

0.5

HH> LH>

0 Xxy>

−0.5

HH

Xz >

LH SO

−1 −1.5 45

50

55

60

Position (nm)

FIGURE 6.2.8 Sample structure (top) and (b) band diagram of a Si–SiGe resonant interband tunneling diode at an applied bias of 0.4 V showing conduction band longitudinal (Xz) and transverse (Xxy) valleys and HH, LH, and SO bands. (From N. Jin, S.-Y. Chung, A.T. Rice, P.R. Berger, R. Yu, P.E. Thomson, and R. Lake. Appl. Phys. Lett. 83: 3308–3310, 2003. With permission.)

200 Extracted intrinsic RITD

Current density (kA/cm2)

Measured RITD 150

100

Si/SiGe RITD (2 nm Si0.6 Ge0.4/1 nm Si) Sharpened P peak 5 µm diameter diode 575⬚C 1 min anneal

50

0 0.0

0.2

0.4 0.6 Voltage (V)

0.8

1.0

FIGURE 6.2.9 Measured and extracted intrinsic I–V characteristics of a Si–SiGe RITD with elevated and sharpened P d-doping. (From N. Jin, S.-Y. Chung, A.T. Rice, P.R. Berger, R. Yu, P.E. Thomson, and R. Lake. Appl. Phys. Lett. 83: 3308–3310, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

6.2-656

The Silicon Heterostructure Handbook

Requirement of memory of logic function (PVCR ⱖ 2)

Peak current density (A/cm2)

Si/SiGe RITD (Jin-APL, 2003)

100 k

Esaki diode (Dashiell, 2000)

RITD (Duschl,2000) SiGe RITD (Rommel-IEDM, 1998)

10 k

SiGe RITD (Rommel-APL, 1998) Si-only RITD (Rommel-EDL, 1999)

1k

RITD (Duschl, 2001) Esaki diode (Jorke, 1993)

SiGe RITD (Jin-Eastmen, 2002)

Requirement for high speed or mixed-signal circuitry (Jp>10 kA/cm2)

1M

100 1

2

3 4 5 Peak-to-valley ratio (PVCR)

6

FIGURE 6.2.10 A graph of PVR plotted against the peak current density of a number of Si-based interband tunnel diodes. (Adapted from From N. Jin, S.-Y. Chung, A.T. Rice, P.R. Berger, R. Yu, P.E. Thomson, and R. Lake. Appl. Phys. Lett. 83: 3308–3310, 2003. With permission.)

Due to the required narrow spacing of the n- and p-type d-doped layers, the capacitance of RITD devices is large. Therefore, the operation of these interband-tunneling devices will be limited at the high frequency and most likely be slower than double barrier RTDs. However, as summarized in Figure 6.2.10, the performance of reported RITDs has achieved the requirements for digital device applications, a PVR larger than 2 and Jp larger than 10 kA cm2, in a wide range [69].

Acknowledgments The authors would like to thank H. Sigg for helpful discussions and careful reading of the manuscript, and A. Borak, J. Gobrecht, J.F. van der Veen, and M. Ru¨fenacht for careful reading of the manuscript. This work is partially supported by the Swiss National Foundation and the European community within the SiGeNET project and the SHINE project.

References 1. D. Bohm. Quantum Theory. New York, NY: Prentice-Hall, 1966. 2. L. Esaki. Long journey into tunneling. Rev. Mod. Phys. 46: 237–244, 1974. 3. S. Datta. Electronic Transport in Mesoscopic Systems. Cambridge, UK: Cambridge University Press, 1995. 4. H. Mizuta and T. Tanoue. The Physics and Applications of Resonant Tunneling Diodes. Cambridge, UK: Cambridge University Press, 1995. 5. J.P. Sun, G.I. Haddad, P. Mazumder, and J.N. Schulman. Resonant tunneling diodes: models and properties. Proc. IEEE 86: 641–661, 1998. 6. H.C. Liu, D. Landheer, M. Buchanan, and D.C. Houghton. Resonant tunneling in Si/Si1xGex double-barrier structures. Appl. Phys. Lett. 52: 1809–1811, 1988. 7. G. Dehlinger, U. Gennser, D. Gru¨tzmacher, T. Ihn, E. Mu¨ller, and K. Ensslin. Investigation of the emitter structure in SiGe/Si resonant tunneling structures. Thin Solid Films 369: 390–393, 2000.

© 2006 by Taylor & Francis Group, LLC

Resonant Tunneling Devices

6.2-657

8. R. Wessel and M. Altarelli. Analytic solution of the effective-mass equation in strained Si–Si1xGex heterostructures applied to resonant tunneling. Phys. Rev. B 40: 12457–12462, 1989. 9. T.C.L.G. Sollner, W.D. Goodhue, P.E. Tannenwald, C.D. Parker, and D.D. Peck. Resonant tunneling through quantum wells at frequencies up to 2.5 THz. Appl. Phys. Lett. 43: 588–590, 1983. 10. P. Mazumder, S. Kulkarni, M. Bhattacharya, J.P. Sun, and G.I. Haddad. Digital circuit applications of resonant tunneling devices. Proc. IEEE 86: 664–686, 1998. 11. H.C. Liu and T.C.L.G. Sollner. High-frequency resonant-tunneling devices. In Semiconductor and Semimetals High Speed Heterostructure Devices, Vol. 41, R.A. Kiehl and T.C.L. Gerhard Sollner, eds. San Diego, CA: Academic Press, 1994, pp. 359–419. 12. P. van der Wagt, A. Seabaugh, and E. Beam III. RTD/HFET low standby power SRAM gain cell. IEDM Tech. Dig. 1996: 425–428, 1996. 13. F. Cappaso. Quantum electron devices: physics and applications. In Semiconductor and Semimetals, High Speed Heterostructure Devices, Vol. 41, R.A. Kiehl and T.C.L. Gerhard Sollner, eds. San Diego, CA: Academic Press, 1994, pp. 1–77. 14. K.J. Chen, K. Maezawa, and M. Yamamoto. InP-based high-performance monostable–bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devices. IEEE Electron Dev. Lett. 17: 127–129, 1996. 15. H.J. De Los Santos, K.K. Chui, D.H. Chow, and H.L. Dunlap. An efficient HBT/RTD oscillator for wireless applications. IEEE Microwave. Wireless. Comp. Lett. 11: 193–195, 2001. 16. T.P.E. Broekaert, B. Brar, J.P.A. van der Wagt, A.C. Seabaugh, F.J. Morris, T.S. Moise, and E.A. Beam III. A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter. IEEE Solid-State Circuits 33: 1342–1349, 1998. 17. RCA tunnel diode manual. Sommerville, NJ: RCA Semiconductor and Materials Division, 1963. 18. J. Faist, F. Capasso, D.L. Sivco, C. Sirtori, A.L. Hutchinson, and A.Y. Cho. Quantum cascade laser. Science 264: 553–556, 1994. 19. G. Dehlinger, L. Diehl, U. Gennser, H. Sigg, J. Faist, K. Ensslin, D. Grutzmacher, and E. Muller. Intersubband electroluminescence from silicon-based quantum cascade structures. Science 290: 2277–2280, 2000. 20. S.A. Lynch, R. Bates, D.J. Paul, D.J. Norris, A.G. Cullis, Z. Ikonic, R.W. Kelsall, P. Harrison, D.D. Arnone, and C.R. Pidgeon. Intersubband electroluminescence from Si/SiGe cascade emitters at terahertz frequencies. Appl. Phys. Lett. 81: 1543–1545, 2002. 21. L. Diehl, S. Mentese, E. Muller, D. Grutzmacher, H. Sigg, U. Gennser, I. Sagnes, Y. Campidelli, O. Kermarrec, D. Bensahel, and J. Faist. Electroluminescence from strain-compensated Si0.2Ge0.8 /Si quantum-cascade structures based on a bound-to-continuum transition. Appl. Phys. Lett. 81: 4700– 4702, 2002. 22. S.S. Rhee, J.S. Park, R.P.G. Karunasiri, Q. Ye, and K.L. Wang. Resonant tunneling through a Si/GexSi1x /Si heterostructure on a GeSi buffer layer. Appl. Phys. Lett. 53: 204–206, 1988. 23. A. Zaslavsky, D.A. Gru¨tzmacher, S.Y. Lin, T.P. Smith III, R.A. Kiehl, and T.O. Sedgwick. Observation of valence-band Landau-level mixing by resonant magnetotunneling. Phys. Rev. B 47: 16036–16039, 1993. 24. U. Gennser, V.P. Kesan, S.S. Iyer, T.J. Bucelot, and E.S. Yang. Temperature dependent transport measurements on strained Si /Si1xGex resonant tunneling devices. J. Vac. Sci. Technol. B 9:2059– 2063, 1991. 25. G.D. Schen, D.X. Xu, M. Willander, G.V. Hansson, and Y.M. Wang. Temperature effects for current transport in resonant tunneling structures. Appl. Phys. Lett. 58: 738–740, 1991. 26. K. Ismail, B.S. Meyerson, and P.J. Wang. Electron resonant tunneling in Si /SiGe double barrier diodes. Appl. Phys. Lett. 59: 973–975, 1991. 27. Z. Matutinovic-Krstelj, C.W. Liu, X. Xiao, and J.C. Strum. Symmetric Si/Si1xGex electron resonant tunneling diodes with an anomalous temperature behavior. Appl. Phys. Lett. 62: 603–605, 1993. 28. D.J. Paul, P. See, I.V. Zozoulenko, K.-F. Berggren, B. Kabius, B. Holla¨nder, and S. Mantl. Si /SiGe electron resonant tunneling diodes. Appl. Phys. Lett. 77: 1653–1655, 2000.

© 2006 by Taylor & Francis Group, LLC

6.2-658

The Silicon Heterostructure Handbook

29. P. See and D. J. Paul, The scaled performance of Si /Si1xGex resonant tunneling diodes. IEEE Electron Device Lett. 22: 582–584, 2001. 30. D.J. Paul, P. See, R. Bates, N. Griffin, B.P. Coonan, G. Redmond, G.M. Crean, I.V. Zozoulenko, K.-F. Berggren, B. Holla¨nder, and S. Mantl. Si /SiGe electron resonant tunneling diodes with graded spacer wells. Appl. Phys. Lett. 78: 4184–4186, 2000. 31. Y. Suda and H. Koyama. Electron resonant tunneling with a high peak-to-valley ratio at room temperature in Si1xGex /Si triple barrier diodes. Appl. Phys. Lett. 79:2273–2275, 2001. 32. R. Tsu. Silicon-based quantum wells. Nature 364: 19, 1993. 33. Y. Wei, R.M. Wallace, and A.C. Seabaugh. Controlled growth of SiO2 tunnel barrier and crystalline Si quantum wells for Si resonant tunneling diodes. J. Appl. Phys. 81: 6415–6424, 1997. 34. M. Watanabe, Y. Iketani, and M. Asada. Epitaxial growth and electrical characteristics of CaF2 /Si / CaF2 resonant tunneling diode structures grown on Si(1 1 1) 18-off Substrate. Jpn. J. Appl. Phys. 39: L964–L967, 2000. 35. C.Y.-P. Chao and S.L. Chuang. Resonant tunneling of holes in the multiband effective-mass approximation. Phys. Rev. B 43: 7027–7039, 1991. 36. H.C. Liu, D. Landheer, M. Buchanan, D.C. Houghton, M. D’Iorio, and S. Kechang. Hole resonant tunneling in Si /SiGe heterosturctures. Superlattices Microstruc. 5: 213–217, 1989. 37. G. Schuberth, G. Abstreiter, E. Gornik, F. Scha¨ffler, and J.F. Luy. Resonant tunneling of holes in Si / SixGe1x quantum-well structures. Phys. Rev. B 43: 2280–2284, 1991. 38. U. Gennser, V.P. Kesan, D.A. Syphers, T.P. Smith III, S.S. Iyer, and E.S. Yang. Probing band structure anisotropy in quantum wells via magnetotunneling. Phys. Rev. Lett. 67: 3828–3831, 1991. 39. A. Zaslavsky, T.P. Smith III, D.A. Gru¨tzmacher, S.Y. Lin, and T.O. Sedgwick. In-plane valence-band nonparabolicity and anisotropy in strained Si–Ge quantum wells. Phys. Rev. B 48: 15112–15115, 1993. 40. Y.C. Chung, T. Reker, A.R. Glanfield, and P.C. Klipstein. Dominance of Fermi-surface holes in p-type tunneling. Phys. Rev. Lett. 88: 126802-1–126802-4, 2002. 41. U. Gennser, M. Scheinert, L. Diehl, S. Tsujino, A. Borak, C.V. Falub, D. Gru¨tzmacher, A. Weber, D.K. Maude, Y. Campidelli, O. Kermarrec, and D. Bensahel. Total angular momentum conservation during tunnelling through semiconductor barriers. cond-mat/0501212. 42. C. Sirtori, F. Capasso, J. Faist, A.L. Hutchinson, D.L. Sivco, and A.Y. Cho. Resonant tunneling in quantum cascade lasers. IEEE J-QE 34: 1722–1729, 1998. 43. S. Tsujino, S. Mentese, L. Diehl, E. Mu¨ller, B. Haas, D. Ba¨chle, S. Stutz, D. Gru¨tzmacher, Y. Campidelli, O. Kermarrec, and D. Bensahel. Resonant tunneling in Si–SiGe superlattices on relaxed buffer substrates. Appl. Surf. Sci. 224: 377–381, 2004. 44. D. Gru¨tzmacher, S. Mentese, E. Mu¨ller, L. Diehl, H. Sigg, Y. Campidelli, O. Kermarrec, D. Bensahel, T. Roch, J. Stangl, and G. Bauer. Strain compensated Si /Si0.2Ge0.8 quantum cascade structures grown by low temperature molecular beam epitaxy. J. Cryst. Growth 251: 707–717, 2003. 45. E. Kasper, H.-J. Herzog, H. Jorke, and G. Abstreiter. Strained layer Si /SiGe superlattices. Superlattice Microstruct. 3: 141–146, 1987. 46. E.A. Fitzgerald, Y.H. Xie, M.L. Green, D. Brasen, A.R. Kortan, J. Michel, Y.J. Mii, and B.E. Weir. Totally relaxed GexSi1x layers with low threading dislocation densities grown on Si substrates. Appl. Phys. Lett. 59: 811–813, 1991. 47. E. Koppensteiner, P. Hamberger, G. Bauer, A. Pesek, H. Kibbel, H. Presting, and E. Kasper. X-raydiffraction investigation of single step and step-graded SiGe alloy buffers for the growth of shortperiod Si(m)Ge(n) superlattices using reciprocal space mapping. Appl. Phys. Lett. 62: 1783–1785, 1993. 48. M. Meduna, J. Novak, G. Bauer, V. Holy, C.V. Falub, S. Tsujino, E. Mu¨ller, D. Gru¨tzmacher, Y. Campidelli, O. Kermarrec, and D. Bensahel. Annealing studies of high Ge composition Si /SiGe multilayers. Z. Kristallogr. 219: 195–200, 2004. 49. S. Tsujino, C.V. Falub, E. Mu¨ller, M. Scheinert, L. Diehl, U. Gennser, T. Fromherz, A. Borak, H. Sigg, D. Gru¨tzmacher, Y. Campidelli, O. Kermarrec, and D. Bensahel. Hall mobility of narrow Si0.2Ge0.8-Si quantum wells on Si0.5Ge0.5 relaxed buffer substrates. Appl. Phys. Lett. 84: 2829–2831, 2004.

© 2006 by Taylor & Francis Group, LLC

Resonant Tunneling Devices

6.2-659

50. J.S. Park, R.P.G. Karunasiri, K.L. Wang, S.S. Rhee, and C.H. Chern. Hole transport through minibands of a symmetrically strained GexSi1x /Si superlattice. Appl. Phys. Lett. 54: 1564–1566, 1989. 51. S. Tsujino, C.V. Falub, E. Mu¨ller, and D. Gru¨tzmacher, unpublished. 52. A. Zaslavsky, K.R. Milkove, Y.H. Lee. B. Ferland, and T.O. Sedgwick. Strain relaxation in silicon– germanium microstructures observed by resonant tunneling spectroscopy. Appl. Phys. Lett. 67: 3921–3923, 1995. 53. P.W. Lukey, J. Caro, T. Zijlstra, E. van der Drift, and S. Radelaar. Observation of strain-relaxationinduced size effects in p-type Si /SiGe resonant-tunneling diodes. Phys. Rev. B 57: 7132–7140, 1998. 54. J. Liu, A. Zaslavsky, and L.B. Freund. Strain-induced quantum ring hole states in a gated vertical quantum dot. Phys. Rev. Lett. 89: 096804-1–096804-4, 2002. 55. J. Liu, A. Zaslavsky, B.R. Perkins, C. Aydin, and L.B. Freund. Single-hole tunneling into a straininduced SiGe quantum ring. Phys. Rev. B 66: 161304-1–161304-4, 2002. 56. M. Fukuda, K. Nakagawa, S. Miyazaki, and M. Hirose. Resonant tunneling through a self-assembled Si quantum dot. Appl. Phys. Lett. 70: 2291–2293, 1997. 57. O.G. Schmidt, U. Denker, K. Eberl, O. Kienzle, F. Ernst, and R.J. Haug. Resonant tunneling diodes made up of stacked self-assembled Ge /Si islands. Appl. Phys. Lett. 77: 4341–4343, 2000. 58. U. Do¨tsch, U. Gennser, C. David, G. Dehlinger, D. Gru¨tzmacher, T. Heinzel, S. Lu¨scher, and K. Ensslin. Single-hole transistor in a p-Si /SiGe quantum well. Appl. Phys. Lett. 78: 341–343, 2001. 59. X.-Z. Bo, L.P. Rokhinson, H. Yin, D.C. Tsui, and J.C. Sturm. Nanopatterning of Si /SiGe electrical devices by atomic force microscopy oxidation. Appl. Phys. Lett. 81: 3263–3265, 2002. 60. L. Esaki. New phenomenon in narrow germanium p–n junctions. Phys. Rev. 109: 603–604, 1958. 61. M. Sweeny and J. Xu. Resonant interband tunnel diodes. Appl. Phys. Lett. 54: 546–548, 1989. 62. H. Jorke, H. Kibbel, K. Strohm, and E. Kasper. Forward-bias characteristics of Si bipolar junctions grown by molecular beam epitaxy at low temperatures. Appl. Phys. Lett. 63: 2408–2410,1993. 63. M.R. Sardela Jr., H.H. Radamson, and G.V. Hansson. Negative differential resistance at room temperature in d-doped diodes grown by Si-molecular beam epitaxy. Appl. Phys. Lett. 64: 1711– 1713, 1994. 64. S.L. Rommel, T.E. Dillon, M.W. Dashiell, H. Feng, J. Kolodzey, P.B. Berger, P.E. Thompson, K.D. Hobart, R. Lake, A.C. Seabaugh, G. Klimeck, and D.K. Blanks. Room temperature operation of epitaxially grown Si /Si0.5Ge0.5 /Si resonant interband tunneling diodes. Appl. Phys. Lett. 73: 2191– 2193, 1998. 65. S.L. Rommel, T.E. Dillon, P.R. Berger, P.E. Thompson, K.D. Hobart, R. Lake, and A.C. Seabaugh. Epitaxially grown Si resonant interband tunnel diodes exhibiting high current densities. IEEE Electron Dev. Lett. 20: 329–331, 1999. 66. R. Duschl, O.G. Schmidt, G. Reitemann, E. Kasper, and K. Eberl. High room temperature peak-tovalley current ratio in Si based Esaki diodes. Electron. Lett. 35: 1111–1112, 1999. 67. R. Duschl, O.G. Schmidt, and K. Eberl. Room temperature I–V characteristics of Si /Si1xGex /Si interband tunneling diodes. Physica E 7: 836–839, 2000. 68. K. Eberl, R. Duschl, O.G. Schmidt, U. Denker, and R. Haug. Si-based resonant inter- and intraband tunneling diodes. J. Cryst. Growth 227–228: 770–776, 2001. 69. N. Jin, S.-Y. Chung, A.T. Rice, P.R. Berger, R. Yu, P.E. Thomson, and R. Lake. 151 kA /cm2 peak current densities in Si /SiGe resonant interband tunneling diodes for high-power mixed signal applications. Appl. Phys. Lett. 83: 3308–3310, 2003.

© 2006 by Taylor & Francis Group, LLC

6.3 IMPATT Diodes 6.3.1 6.3.2 6.3.3

Introduction............................................................... 6.3-661 Structure and Principle Function ............................ 6.3-661 SiGe — SIMMWIC................................................... 6.3-665 Layout Examples of Waveguides, Antenna, and Passive Circuits . Electrical Characterization of Integrated IMPATTs

6.3.4

Erich Kasper and Michael Oehme University of Stuttgart

Extensions of the Concept........................................ 6.3-671 Resonance-Phase Operation of HBT . Terahertz Oscillations from Optical Hot Carrier Injection

6.3.5 6.3.6

Growth and Process Requirements.......................... 6.3-673 Summary .................................................................... 6.3-676

6.3.1 Introduction Impact avalanche transit time (IMPATT) devices diodes are known from silicon and III–V material. As discrete devices mounted on special heatsinks, they are very powerful sources of microwave radiation. At 100 GHz CW-power of 1 W and pulsed power of 50 W can be obtained. The technology is complicated but well established after three decades of development. The negative resistance level of these discrete devices is rather low (at the order of a few ohms), which causes high efforts in designing appropriate resonators. With increasing demand on mm-wave electronics for contactless sensors, security systems, and automobile applications, the pull for monolithic integration rises due to cost, weight, accuracy, and reliability issues. SiGe-SIMMWICs (silicon monolithic mm-wave integrated circuits) offer competitive responses onto these requirements. Planar IMPATTs can be monolithically integrated into SIMMWICs. The integrated IMPATTs aim to a much lower power level (mW regime) and offer much higher negative resistances (typically 10 to 100 V), which allows easier resonator and oscillator design. Small and simple designs are demonstrated up to 100 GHz operation frequency. Research activities focus on the implementation of heterostructures, on the replacement of the noisy avalanche multiplication by other injection mechanism, on the transfer of the delay concept to transistors, and on extension into the terahertz frequency regime. In this chapter, we report the activities of integrated devices. Discrete classical IMPATTs are not treated.

6.3.2 Structure and Principle Function In common diodes and transistors the output phase delay between voltage and current is kept small because with increasing phase delay the output power decreases. The IMPATT diode stands for a separate class of devices where a large phase delay is intentionally aimed. The preferred delay is around 1808 (p), which characterizes a negative resistance used to overcome the positive load resistance. 6.3-661 © 2006 by Taylor & Francis Group, LLC

6.3-662

The Silicon Heterostructure Handbook

Generally, the phase delay in this class of devices consists of two contributions: one from an injection phase F and one from a transit angle Q. The total phase delay w is given by w¼Fþ

Q 2

(6:3:1)

The transit angle Q counts only half because a displacement current occurs during the whole transit of a current pulse. For a space–charge region with electrical fields high enough for saturated carrier velocity the transit angle Q is simply given by [1] Q¼v

ld vS

(6:3:2)

with v ¼ 2pf representing frequency, ld the length of drift region, and vS the saturation velocity of carriers. All transit angles may be realized by a proper choice of the length ld, but the amplitude decreases because of the pulse broadening by the displacement current. Therefore, the injection phase F is essential for a large-phase delay w and a large negative amplitude. In the IMPATT diode the injection phase F ¼ p/2 is produced by the avalanche multiplication process in a rather small avalanche region with width la (Figure 6.3.1). The frequency-dependent impedance Z ¼ R þ jX of such a simple diode structure with la << ld is given by R ¼ Re(Z) ¼ RS

vS (1 cos Q) 1 A«v2 v2 =v2a 1

(6:3:3)

la sin Q þ vA« sin Q Q ld ¼ X 1 ld Q (va =v)2 1

(6:3:4)

The avalanche frequency va depends on material constants as velocity vS, permittivity «, ionization coefficient a (E), and on the current density J0. The avalanche frequency is slightly temperature dependent because of the temperature dependence of vS(T) and a(T) v2a ¼ 2

da vS J0 =« dE

(6:3:5)

The principle structure of a single drift diode and the resulting impedance levels are given in the following figures. Single drift is the term when only one carrier type — as in Figure 6.3.2, the electrons — contributes to the drift current. The doping sequence given in Figure 6.3.2 is known as Read structure where avalanche multiplication and drift are rather clearly separated (Read).

la Avalanche region

ld Drift region

RS Series resistance

FIGURE 6.3.1 IMPATT diode with carrier injection by an avalanche region and a drift region with saturation velocity.

© 2006 by Taylor & Francis Group, LLC

6.3-663

IMPATT Diodes

p+

n

n−(n)

n+

1

2

3

4

la

ld

NA1

NA−ND

x ND3

ND2

ND4

E E12 E23

E34

x

FIGURE 6.3.2 Structure, doping sequence, and field strength in a single drift Read structure.

150

100 Real part Imaginary part Impedance (Ω)

50

0

−50

−100

−150 0

FIGURE 6.3.3 85 GHz).

20

40

60

80 100 Frequency (GHz)

120

140

160

Impedance (real part R solid line, imaginary part X broken line) as a function of frequency (fa ¼

At the avalanche frequency, the sign of the impedance switches from positive to negative values. Usually at frequencies slightly above the avalanche frequency the IMPATT is utilized as oscillator or amplifier. The idealized (loss less) impedance curve is characterized by a rapid decay of the negative impedance at frequencies above fa (see Figure 6.3.3). The injection mechanism may be changed to tunneling (TUNETT), thermoionic emission across a barrier (BARITT), or coherent transport [2] in a resonance-phase transistor (RPT) [3]. Figure 6.3.4

© 2006 by Taylor & Francis Group, LLC

6.3-664

The Silicon Heterostructure Handbook

log (N) (cm−3) SiGe P+

1021

N+ 1019

1017 0

20

40

Distance (nm)

FIGURE 6.3.4 Injection region of a MITATT with a mixed tunneling and avalanche multiplication injection.

E

Emax ∆E

x=0

20 lo

hi

Avalanche, tunneling

Distance (nm) lo Drift

FIGURE 6.3.5 Electric field strength in a lo–hi–lo IMPATT.

exhibits the typical profile of a MITATT (mixed tunneling and impact avalanche transit time device) diode [4]. The tunneling probability may be adjusted [5] by the distance of the pþ and nþ regions and by the germanium content of the SiGe layer in between. The electrical field distribution in such a low–high–low (lo–hi–lo) active region is shown in Figure 6.3.5. The maximum field strength Emax (around 5 107 to 108 V/m) is obtained at the intrinsic region between the doping spikes. At the Nþ-doping spike the field strength is reduced by DE and the electric field enters the drift region with a field strength Emax DE. The field step DE is correlated with the sheet concentration NS in the spike by NS ¼ ND dD ¼

DE« l

(6:3:6)

Sheet concentration in the order of 2 to 3 1016 m2 is required to obtain the necessary field steps of 3.2 to 4.8 107 V/m.

© 2006 by Taylor & Francis Group, LLC

6.3-665

IMPATT Diodes

6.3.3 SiGe — SIMMWIC SIMMWIC were already proposed in 1984 [6] but the availability of silicon-based high-speed devices added recently to the attractiveness of integration concepts. Due to the reduced wavelength in the mmwave regime (30 to 300 GHz) the nature of waveguide propagation has to be considered for the design of SIMMWICs. For example, at 100 GHz the wavelength in silicon is roughly 1 mm and so much smaller than the typical chip dimensions. In the full version the SIMMWIC contains antenna, different planar waveguides, passive devices, active semiconductor devices, and sometimes also microelectromechanical (MEMS) devices integrated on a low-loss silicon substrate. Usually the low-loss substrate is obtained by a highpurity float zone (FZ) growth technique, resulting in specific resistivities of 1000 V cm and more. Often only subsystems are monolithically integrated and described as SIMMWIC. In the following, some examples of typical layouts are given for the illustration of the reader and only the breakdown behavior and negative differential resistance (NDR) of monolithic-integrated IMPATTs is treated in depths.

Layout Examples of Waveguides, Antenna, and Passive Circuits The most appropriate planar waveguide for integration is the coplanar waveguide (CPW), which consists of a central signal line separated on both sides by slots from the surrounding ground plate (Figure 6.3.6). The signal line has to be considered as a MOS varactor to understand the propagation losses of the transmission line [7], which are only low if inversion or accumulation layers are suppressed below the lines. Resistors, different types of capacitors (Figure 6.3.7), and spiral inductors belong to the passive devices used in SIMMWIC circuits for filtering, frequency adjustment, and impedance adjustment. Packages and hybrid connections require sophisticated efforts with higher frequencies. A possible integration of the antenna is therefore an attractive option of SIMMWIC designs for both receiver and transmitter circuits. A simple example (Figure 6.3.8) is a rectenna [9] where a Schottkydetector is integrated with a planar antenna (rectifying antenna) and the detector signal is amplified by an operation amplifier. Only low- or medium-speed signals are treated at the package pins, and therefore, a commercial package could be used. Integrated Schottky diodes may be designed for RC-frequency limits in excess of 1 THz [10]. Schottky diodes especially when driven in the so-called Mott operation are excellent candidates for detecting, mixing, frequency multiplication in the upper mm-wave frequency regime. Mott operation means that even under forward conditions the epitaxial layer is depleted which requires good control of dopant background and abrupt transitions. Silicide Schottky-barriers well developed in Si-technology [11] need an improved understanding of mixed silicide and germanide formation on SiGe layers.

Ground

Signal

Ground

er,Si

FIGURE 6.3.6 Coplanar waveguide with an insulating layer beneath the transmission lines.

© 2006 by Taylor & Francis Group, LLC

6.3-666

The Silicon Heterostructure Handbook

MIM connection

Capacitor

Viahole

FIGURE 6.3.7 Metal–insulator–metal (MIM) capacitor in the intermediate frequency (IF) port of a harmonic 38 GHz mixer [7].

FIGURE 6.3.8

90 GHz receiver module consisting of a rectenna and an amplifier mounted on a multichip module.

Electrical Characterization of Integrated IMPATTs Integrated IMPATT diodes are operated in the avalanche breakdown. They deliver a negative differential resistance above an avalanche frequency. The width of the frequency band with negative resistance is mainly determined by the series resistance because the amount of negative resistance provided by the diode decreases rapidly above the avalanche frequency. In the following, the report concentrates on breakdown behavior, S-parameter measurements of 75 to 110 GHz impedance and analysis of series resistance. In a single drift silicon IMPATT the onset of breakdown (typically around 10 V for a 100 GHz IMPATT) is very sharp (Figure 6.3.10) and agrees roughly with predictions from ionization coefficients and breakdown field strengths. The predictions are explained on the example of a uniformly doped (ND) single drift structure of thickness dn. The electric field distribution is given in Figure 6.3.9. Assumed is

© 2006 by Taylor & Francis Group, LLC

6.3-667

IMPATT Diodes

E p+

n+

n

Ebr ∆E

dE qND = dx e

x

dn ln

FIGURE 6.3.9 Trapezoidal field distribution in a single drift structure at breakdown.

a single drift structure with a reach through factor F > 1. The reach through factor F is defined by the ratio between projected depletion length ln and technologically realized active layer thickness dn F¼

ln dn

(6:3:7)

Onset of breakdown is obtained when the maximum field at the pþn junction reaches the dopingdependent breakdown field strength Ebr(ND). The breakdown voltage Vbr is essentially equal to the area under the field function. Vbr þ Vbi ¼

Z

dn

Edx ¼

0

2 (ND ) 2F 1 « Ebr qND 2 d ¼ Ebr dn 2q ND F2 2« n

(6:3:8)

(Vbi — built in voltage, q — electron charge, « — permittivity). The breakdown field Ebr is a function slowly varying with doping and approximately given by 4 107 V=m

Ebr ¼ 1

1 log (ND =1016 cm3 ) 3

(6:3:9)

At the high current densities where the IMPATT is operated (Figure 6.3.10) one sees a bend of the breakdown curve to higher voltages. This bending is mainly caused by two effects: heating and injection of carriers. The avalanche breakdown has a positive temperature coefficient because at higher temperature phonon scattering retards the carrier speed necessary for impact ionization. The injection of carriers into the space–charge region reduces the space–charge density in the depletion layer, which — like a lower doping — increases the breakdown voltage. The increase is proportional to the current and can be expressed as space–charge resistance RSC: RSC ¼

dn2 2A«vS

(6:3:10)

The avalanche breakdown characteristics of pseudomorphic SiGe are similar to that of silicon. But for thicker SiGe layers or higher Ge contents the SiGe layers have to be grown on virtual substrates

© 2006 by Taylor & Francis Group, LLC

6.3-668

The Silicon Heterostructure Handbook

10−1 10−2 Reverse current

Absolute current (A)

10−3

Thermal effect

10−4 10−5 10−6 10−7 10−8 10−9 −14

FIGURE 6.3.10

−12

−10

−8 −6 Voltage (V)

−4

−2

0

Reverse characteristics of the IMPATT diode.

10−3

X=0 X = 10% X = 20% X = 27% X = 50% X = 100%

Current (A)

10−4

10−5

10−6 −18

−16

−14

−12

−10 −8 Voltage (V)

−6

−4

−2

0

FIGURE 6.3.11 Breakdown of SiGe p–n junctions on virtual substrates. The Ge content X is varied between 0% and 100%. The shift in the absolute value of the breakdown is partly also caused by slight variations of the doping and thickness.

consisting of a relaxed SiGe buffer layer onto the silicon substrate. For monolithic integration with silicon circuits this buffer layer has to be thin, ideally below 100 nm [12]. The threading dislocation density of these thin buffers is in the order between 105 and 107 cm2, which degrades the breakdown behavior (Figure 6.3.11). The breakdown characteristic (look at the slope, the absolute value shift is partly caused by different layer parameters) of low Ge content layers (X ¼ 0.1 to 0.27) is rather similar to silicon at current levels

© 2006 by Taylor & Francis Group, LLC

6.3-669

IMPATT Diodes

above 0.1 mA. Even the 50% Ge layer demonstrates acceptable breakdown behavior above 1 mA current. In the 100% Ge layer on a thin virtual substrate, the breakdown is masked by high reverse current levels and these layers cannot be used for IMPATT operation. Progress in virtual substrate technology for high Ge content is necessary. Proper dc-characteristics of the breakdown are a rapid test but the ultimate confirmation of the phase delay is given by S-parameter measurement in the selected microwave region. For a comparison and judgment of the results the S-parameter values are recalculated to impedance values (Figure 6.3.12). At the avalanche frequency fa the imaginary part of the impedance switches sign and the negative real part obtains its maximum value. The negative impedance of the integrated IMPATT is quite high, for example 7000 V for the 18 mA current curve at 77.5 GHz. Another important property of the frequency curves of the impedance values is the strong current dependency, which can be used to adjust the impedance level of the device. The operation in an oscillator circuit is above the avalanche frequency where the NDR is typically in the order of several tenths of ohms (Figure 6.3.13). The oscillating conditions require that the NDR of the device surpasses the load resistance to allow for undamped oscillations ZD þ ZL ¼ 0

(6:3:11)

Stable oscillation is obtained when the sum of diode impedance ZD and load impedance ZL equals zero. A frequency increase above the avalanche frequency reduces strongly the NDR. Up to which frequency an NDR is offered by the IMPATT depends also on the series resistance RS. A low series resistance RS is essential for a wide NDR regime. The series resistance in an integrated IMPATT consists of three different contributions (Figure 6.3.14): contact resistance RC, epitaxy resistance REPI, and buried layer resistance RBL. Low contact resistance RC is obtained with a highly doped semiconductor on the surface (1020 cm3) and a metal system with a fairly low Schottky barrier. The examples given in this chapter are with NiSi contacts a silicide metal, which also shows promises for sub-100 nm device dimensions. The buried layer resistance RBL is low for a high-doped uniform layer, which is made in the given

Imaginary part (Ω)

0 −2000 −4000

I = 14 mA I = 16 mA I = 18 mA

−6000 −8000 −10000 75

76

77

78

79

80

81

82

83

84

85

76

77

78

79 80 81 Frequency (GHz)

82

83

84

85

Imaginary part (Ω)

6000 4000 2000 0 −2000 −4000 75

FIGURE 6.3.12 IMPATT impedance in the frequency band 75 to 85 GHz as a function of the current.

© 2006 by Taylor & Francis Group, LLC

6.3-670

The Silicon Heterostructure Handbook

0 NDR

NDR = -40W −50

Real part (Ω)

−100

−150

−200

Oscillator frequency

−250

−300

86

88

90

92

94 96 98 Frequency (GHz)

100

102

104

106

FIGURE 6.3.13 Impedance (real part) of the IMPATT around the oscillator frequency. Negative differential resistance (NDR) is 40 V at an oscillation frequency of 100 GHz.

RM

tMetal

RLZ

WRLZ

REpi

n-epilayer

dEpi

RC

RC RBL

RBL n++-Buried layer

FIGURE 6.3.14

nþ buried layer for integration techniques.

examples by molecular beam epitaxy (MBE). The epitaxy resistance REPI is zero for breakdown operation because the epitaxy layer is depleted. But the extraction of the series resistance is done under forward voltage where the epitaxy layer contributes. The extracted value of the series resistance has to be reduced by REPI ¼ rEPI dn =A to account for the RS value seen at breakdown.

© 2006 by Taylor & Francis Group, LLC

(6:3:12)

6.3-671

IMPATT Diodes

The circuit test is performed by placing the integrated IMPATT diode into a planar resonator (Figure 6.3.15) on a silicon substrate. A rather straightforward coplanar resonator design matched the impedance level of the IMPATT. The spectrum of the 93 GHz oscillator is shown in Figure 6.3.16.

6.3.4.

Extensions of the Concept

For circuit design the decoupling of the output terminal from the input by a three terminal device is considered as advantageous. Extensions of the phase delay concept to transistors could enhance the acceptance of these devices in more complex circuits. Recently, the successful test of a SiGe RPT was reported [13] and the basics of this transistor will be explained below. The separation of carriers in the high field of a reverse-biased junction is utilized for carrier injection in the drift region of an IMPATT. It is one of the mechanisms of the device, which together with a properly designed resonator allows for oscillations in the 100 GHz regime. A much more direct conversion in high-frequency radiation would

FIGURE 6.3.15 Planar oscillator with integrated IMPATT diode. The resonator is designed for an oscillating frequency near 93 GHz. 0

Output power (dBm)

−10 −20 −30 −40 −50 92.8

92.9

93 Frequency (GHz)

93.1

93.2

FIGURE 6.3.16 Spectrum of the oscillator depicted in Figure 6.3.15, with an oscillating frequency of 93 GHz.

© 2006 by Taylor & Francis Group, LLC

6.3-672

The Silicon Heterostructure Handbook

be obtained by the separation of photogenerated electron–hole couples into a Hertzian dipole. Very recent and preliminary results give hints for a terahetz source [14]. The basics will be explained in the second part of this section.

Resonance-Phase Operation of HBT The operation frequency of integrated circuits (IC) may be extended — depending on complexity and requirements — up to a certain fraction (typically 1/20 to 1/2) of the frequency limits of the transistor type used in the IC. Commonly considered frequency limits are the transit frequency fT and the maximum oscillation frequency fmax. Within the common transistor paradigm the frequency limits have to be increased to allow higher circuit operation frequencies. Remarkable research results well beyond 100 GHz have been obtained with silicon-based transistors by lateral shrinking of dimensions and by use of SiGe–Si heterostructures [15]. Approaching the frequency limit, the output signal of these transistors is reduced and a phase shift between input and output takes place. In the newly proposed transistor type, the operation frequency should be increased far above the transit frequency fT by an intentionally introduced large phase shift between output and input signal [16]. Similar principles are known from diode-type devices (e.g., IMPATT diodes) but never successfully transferred to transistors. In order to get the resonance effect within the 40 GHz setup we reduced the transit frequencies of the experimental versions to below 15 GHz. The RPT concept is based on the achievement of NDR in a defined frequency band by a large phase delay of at least an angle p. The phase shift is obtained by a delayed injection (Figure 6.3.17) into a drift region [17]. Delayed injection may be obtained by tunneling or carrier diffusion [18]. Using for the technological realization a SiGe heterobipolar structure [19] we adopted a bipolar nomenclature for the electrodes emitter, base, collector for the more general terms cathode, injector, anode in Figure 6.3.17. The layer structure of the processed RPT is shown in Table 6.3.1. To obtain the necessary phase shift both base and collector layers are chosen to be very thick. After the simulations in Ref. [18] the base layer thickness is 120 nm. Incorporated in the base is a linearly graded Ge profile from about 5% Ge at the emitter–base junction to 30% Ge at the base–collector junction to enhance the forward diffusion transport. The whole bandgap difference is about 170 meV. We use the term ultrametastable when

Anode

Injector exp( jwt ) Input

f

q

Injection

Drift

exp(j(wt+j)) Output

j=f+q/2 Cathode

FIGURE 6.3.17 Two port representation of the resonance-phase transistor with the terminals cathode (emitter), injector (base), anode (collector). TABLE 6.3.1 Vertical Layer Structure of the Processed RPT (Wafer A) Structure Buried layer Collector Spacer SiGe-base Spacer Emitter Emitter contact

© 2006 by Taylor & Francis Group, LLC

Thickness (nm)

Doping (cm3) þþ

wC ¼ 1200 D ¼ 10 wB ¼ 120 d ¼ 2 d ¼ 70 d ¼ 230

n ; 12 V/sq. NC, n ¼ 3 1016 Intrinsic NB, pþþ; 2 1019 Intrinsic n; 1 1018 nþþ; 2 1020

Ge content (%) Si Si Si1XGeX, X ¼ 30% Gradient Si1XGeX, X ¼ 5% Si Si

6.3-673

IMPATT Diodes

8 H21 (dB)

3

6

H21 (dB)

lC 4

Wafer B

0 −3 −6 −9

Wafer A

1

10 Frequency (GHz)

2 8 mA 4 mA 2 mA 1 mA

0

−2 1

10 Frequency (GHz)

FIGURE 6.3.18 Common emitter current gain H21 over frequency for a 225 mm2 emitter size RPT of wafer B, UCE ¼ 4 V. The inset shows a comparison between two wafers (IC ¼ 1 mA, UCE ¼ 4 V) with different collector dopings.

thickness and Ge content are not only above the critical values of pseudomorphic growth but also beyond that of metastable growth at 5508C as measured by People and Bean [20]. Epitaxy below 5508C and low-temperature processing are necessary to get devices from ultrametastable structures. In Figure 6.3.18, the current gain H21 in dB is shown in common emitter configuration. For frequencies below the transit frequency fT the behavior is common. For low frequencies, the current gain approaches a constant value. Increasing the frequency results in the typical roll off of H21. Up to a collector current IC ¼ 10 mA fT is increasing, for higher currents the modified Kirk effect limits fT because of the low collector doping concentration. For frequencies higher than fTH21 first is decreasing partly even below 0 dB. But for still higher frequencies the resonant-phase effect turns H21 to increase again, reaching H21 > 0 dB at 23 GHz and so active transistor operation at frequencies beyond fT seems possible. At low currents (IC ¼ 0.5 mA) the maximum gain of the resonance peak is seen with H21 ¼ 2.3 dB at 36 GHz. The used measurement setup allowed measurements up to 40 GHz and demonstrated clearly the onset of resonance-phase effect. As expected by the model the resonance-phase effect is less current dependent than the transit frequency fT.

Terahertz Oscillations from Optical Hot Carrier Injection Under high electric fields photogenerated electron–hole pairs are separated with increasing velocity up to the saturation velocity or even above when velocity overshoot occurs. The ultrafast separation of the photogenerated electron–hole pairs creates a sheet of accelerating charges. The emitted radiation depends on the transport properties of the hot carriers. Basic experiments with femtosecond laser pulse excitation demonstrated oscillations around 4.5 THz. The preliminary study [14] was mainly aimed at investigating the hot carrier properties and to understand the mechanism. But obviously, carrier separation in a high electric field is a new candidate for terahertz radiation.

6.3.5 Growth and Process Requirements For the integration of the IMPATT diodes a buried layer with a low sheet resistance and a good contact is required. Buried layers can be realized with different methods for example with ion implantation. We use a uniform buried layer with very high doping in the range of 1 1020 cm3. The layers are grown

© 2006 by Taylor & Francis Group, LLC

6.3-674

The Silicon Heterostructure Handbook

with the physical deposition method MBE (see Chapter 2.4). This method allowed p-type and n-type doping over a wide range of concentration and with abrupt doping transitions. In the MBE system boron is used for p-type doping. This element has a large equilibrium solid solubility and a low surface segregation. For n-type doping antimony is used in MBE because this material can be directly coevaporated from a low-temperature-controlled effusion source during the growth. Because Sb has an extreme temperature sensitivity of surface segregation [21] we use for sharp doping transitions special doping strategies such as prebuild-up, flash-off techniques [22], or the doping by secondary ions (DSI) [23]. Figure 6.3.19 shows the layer stack for the monolithic-integrated IMPATT diode. The challenges for the growth are the abrupt doping transitions from 1 1020 to 1 1017 cm3 in the n-region and from 1 1017 to 1 1020 cm3 on the pn junction. Very sharp profiles over three orders of magnitudes are essential for the high-frequency performance. For the application in integrated high-frequency circuits a silicon (1 0 0) substrate with a high specific resistance greater than 1000 V cm is of advantage. The complete doping structure is shown in Figure 6.3.20. After the thermal cleaning of the substrate [24] the growth starts with an intrinsic silicon buffer. For the doping of the 500-nm thick buried layer a prebuild-up growth strategy with constant Sb-flux at low growth temperatures (4308C) is applied. This procedure starts with the supply of an antimony adlayer of a fraction of a monolayer. At the end of the buried layer (see point 1 in Figure 6.3.20) one monolayer of antimony sticks on the surface. By higher growth temperatures, the segregation length DS of antimony increases dramatically [21], for example, by increasing the temperature from 5008C to 6008C DS increases by a factor of 1000. The bulk concentration, nB, is determined from the ratio between surface density nS and DS. For constant nS, nB decreases as DS increases. This is used for an abrupt dopant profile nþ/n. The temperature is increased during a growth interruption. Then the antimony level decreases abruptly over four to five decades and it is adjusted in the following n-silicon layer to 1017 cm3 with the DSI method. A defined negative voltage of 100 V is applied on the substrate. By this, silicon ions are extracted from the electron gun and are accelerated to the substrate. The incoming silicon ions collide with the surface antimony atoms, so that they are incorporated in the growing layer. For a sharp doping transition on the pn junction the highboron-doped uniform cap layer is also grown with the prebuild-up method (see point 3 in Figure 6.3.20). For providing the exact segregating adlayer density, we developed a method to measure this density at a fixed doping level [25]. The growth is monitored with different in situ analyzing methods. One powerful method is the reflection-supported pyrometric interferometry (RSPI) measurement [26]. RSPI has been proven to be capable of providing in situ real-time information concerning temperature and film thickness for

200 nm B-contact layer (1020 cm−3) 450 nm active region (Sb 1017 cm−3) 500 nm Sb-buried layer (1020 cm−3) Silicon buffer p−-substrate (> 1000 Ωcm)

FIGURE 6.3.19

Layer stack for a 100 GHz integrated IMPATT diode with n-doped buried layer.

© 2006 by Taylor & Francis Group, LLC

6.3-675

IMPATT Diodes

log (N ) (cm−3) High doping

3

1 NA

1020

ND 2

Defined n-level

1017 p-contact

Interface Active region

Buried layer

Buffer

Substrate

1013 0

200

650

1150

1300

Depth (nm)

Abrupt doping transition (3 order of magnitudes)

FIGURE 6.3.20 Vertical doping structure of the integrated IMPATT diode in Figure 6.3.19.

p-contact

Active region

Buried layer

Buffer

0.40

600

0.39

550

0.38

500

0.37

0.36

450 growth temperature reflectivity at 670 nm reflectivity at 950 nm

Reflectivity at 670 nm and 950 nm

Growth temperature (⬚C)

650

0.35

400 0

2000

4000

6000 8000 Time (sec)

10,000

12,000

FIGURE 6.3.21 Interferometry measurement of the complete growth process sequence.

numerous applications in semiconductor manufacturing. Figure 6.3.21 shows the RSPI measurement over the complete growth process of an integrated IMPATT diode. The growth direction is from the right to the left side. After the intrinsic silicon buffer the growth temperature is decreased during a growth interruption. The reflectivity of both wavelengths decreases because the index of refraction decreases with lower temperature. During the growth of the buried layer oscillations appear, which result from the change in the index of refraction between intrinsic and very-high-doped silicon. From the distance between two maxima respectively minima the layer thickness is calculated. From the example shown in Figure 6.3.21, the buried layer thickness is 535 nm. With the same calculations the drift region and the p-contact are analyzed.

© 2006 by Taylor & Francis Group, LLC

6.3-676

The Silicon Heterostructure Handbook

Pre-build up

Small overshoot

Concentration (cm−3)

1020

Interface 1019 boron antimony carbon

1018

1017

0

FIGURE 6.3.22

200

400

600 800 Depth (nm)

1000

1200

1400

SIMS depth profile of a realized IMPATT structure.

A secondary ion mass spectroscopy (SIMS) depth profile of the elements boron, antimony, and carbon from the integrated IMPATT diode (Figure 6.3.22) proves the intended structure. The growth direction is from right to left in this figure. From the interface position (carbonand boron-peak) the total layer thickness is determined as 1388 nm. The silicon rate is calculated from thickness and growth time as rSi ¼ 0.107 nm/sec. From this result, the thickness of the buried layer is with 535 nm the same as on the RSPI analysis. The antimony profile exhibits clearly the veryhigh-doped buried layer with 1 1020 cm3 but not the active region, because the antimony SIMS background is too high. The transition between the nþ/n layers is dominated by the SIMS depth resolution. At the start of the buried layer, the submonolayer prebuild-up causes a faint step in the profile upraise. In the boron profile a small overshoot at the start of the very-high-doped p-contact proves the prebuild-up is too high. But the transition between drift region and p-contact is very sharp over three decades.

6.3.6 Summary Monolithic integration [27–30] of semiconductor devices with passive circuits [31–38] will allow radar systems with chip dimensions. Monolithic-integrated IMPATTs offer NDR within a wide mmwave frequency regime (30 to 150 GHz). These integrated devices strengthen the competitiveness of SiGe-SIMMWIC solutions by robust, simple and small oscillator, resonator and amplifier designs. SiGe heterostructures are especially used for alternative injection mechanisms (tunneling) and for three terminal device versions (resonance-phase transistor). Recent basic experiments on emission from field separated electron–hole pairs gave hints for extension of the frequencies into the terahertz regime.

Acknowledgments The device processing group and the microwave group provided unpublished material, we thank especially C. Schoellhorn, M. Morschbach, and M. Jutzi. J. Hasch from Robert Bosch GmbH advised in high-frequency characterization and we acknowledge his help. We are grateful to H. Pfizenmaier for his early application driven interest in SIMMWIC realizations beyond 100 GHz.

© 2006 by Taylor & Francis Group, LLC

IMPATT Diodes

6.3-677

References 1. S.M. Sze. Physics of Semiconductor Devices. John Wiley, New York (1981). 2. A.A. Grinberg and S. Luryi. Coherent transistor. IEEE Trans. Electron Dev. ED-40, 1537–1539 (2003). 3. E. Kasper and J.F. Luy. State of the Art and Future Trends in Silicon IMPATT Diodes for mm Wave Seeker Requirements, Military Microwaves Conference Proceedings. Microwave Exhibitions and Publishers, London, pp. 293–298 (1990). 4. J.F. Luy, H. Jorke, H. Kibbel, A. Casel, and E. Kasper. Si/SiGe heterostructure MITATT diode. Electron. Lett. 24, 1386–1387 (1988). 5. R. Duschel, O.G. Schmidt, G. Reitemann, E. Kasper, and K. Eberl. High room temperature peak to valley current ratio in Si based Esaki diodes. Electron. Lett. 35, 1–2 (1999). 6. P.J. Stabile, A. Rosen, W.M. Janton, A. Gombar, and M. Kolan. Millimeter wave silicon device and integrated circuit technology. IEEE MTT-S, Int. Microwave Symp. Digest, pp. 448–450 (1984). 7. W. Zhao, C. Scho¨llhorn, and E. Kasper. Interface loss mechanism of millimeter-wave coplanar waveguides on silicon. IEEE Trans. Microwave Theory Tech. 50, 407–410 (2002). 8. W. Zhao, C. Scho¨llhorn, E. Kasper, and C. Rheinfelder. 38 GHz coplanar harmonic mixer on silicon. Proceedings of the Third Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Ann Arbor, Michigan, pp. 138–141 (2001). 9. M. Herrmann, D. Beck, E. Kasper, J.-F. Luy, K.M. Strohm, and J. Buechler. Hybrid 90 GHz rectenna chip with CMOS preamplifier. Proceedings of the 26th European Solid State Research Conference, ESSDERC, Bologna, Italy, pp. 527–530 (1996). 10. M. Morschbach, C. Scho¨llhorn, M. Oehme, E. Kasper, A. Mu¨ller, and T. Buck. Integrated Schottky mixer diodes with cut off frequencies above 1 THz2. Proceedings of the 34th European Microwave Conf., Amsterdam, Netherlands. October 2004, pp. 1133–1136. 11. C. Schoellhorn and E. Kasper. Recent Res. Devel. Microwave Theory Tech. 2, 155–182 (2004). 12. K. Lyutovich, E. Kasper, F. Ernst, M. Bauer, and M. Oehme. Relaxed SiGe buffer layer growth with point defect injection. Mater. Sci. Eng. B 71, 14–19 (2000). 13. E. Kasper, J. Eberhardt, H. Jorke, J.-F. Luy, H. Kibbel, M.W. Dashiell, O.G. Schmidt, and M. Stoffel. SiGe resonance phase transistor: Active transistor operation beyond the transit frequency fT. SolidState Electron. 48, 837–840 (2004). 14. A. Brodschelm, C. Schoellhorn, E. Kasper, and A. Leitensdorfer. Ultrafast high-field transport after 10 fs hot carrier injection in Si and SiGe. Semicond. Sci. Technol. 19, 267–269 (2004). 15. J. Eberhardt and E. Kasper. Modelling of SiGe hetero-bipolar transistor: 200 GHz frequencies with symmetrical delaytimes. Solid State Electron. 45, 2097–2100 (2001). 16. J. Weller, H. Jorke, K.M. Strohm, J.-F. Luy, and R. Sauer. Transistor action by transit time shift — a study for SiGe based devices. 28th European Microwave Conference Proceedings, pp. 745–750 (1998). 17. E. Kasper and G. Reitemann. Physics of future ultra high speed transistors: new concepts. 29th European Microwave Conference Proceedings, Vol. 1, pp. 155–157 (1999). 18. H. Jorke, M. Scha¨fer, and J.-F. Luy. Resonance phase transistor — concepts and perspectives. Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, IEEE, pp. 149–156 (2001). 19. E. Kasper. Silicon germanium trends on process integration. ULSI Process Integration II, ECS Proc., Vol. 2, pp. 143–154 (2001). 20. R. People and J.C. Bean. Calculation of critical thickness versus lattice mismatch for SiGe/Si strained layer heterostructures. Appl. Phys. Lett. 47, 322–324 (1985) and 49, 229 (1986). 21. H. Jorke. Surface segregation of Sb on Si(100) during molecular beam epitaxy growth. Surf. Sci. 193, 569–578 (1988). 22. S.S. Iyer, R.A. Metzger, and F.G. Allen. Sharp profiles with high and low doping levels in silicon grown by molecular beam epitaxy. J. Appl. Phys. 52, 5608–5613 (1981). 23. H. Jorke, H.-J. Herzog, and H. Kibbel. Secondary implantation of Sb into Si molecular beam epitaxy layers. Appl. Phys. Lett. 47, 511–513 (1985).

© 2006 by Taylor & Francis Group, LLC

6.3-678

The Silicon Heterostructure Handbook

24. E. Kasper, M. Bauer, and M. Oehme. Quantitative secondary ion mass spectrometry analysis of SiO2 desorption during in situ cleaning. Thin Solid Films 321, 148–152 (1998). 25. M. Oehme, M. Bauer, T. Grasby, and E. Kasper. A novel measurement method of segregating adlayers in MBE. Thin Solid Films 369, 138–142 (2000). 26. M. Bauer, M. Oehme, M. Sauter, G. Eifler, and E. Kasper. Time resolved reflectivity measurements of silicon solid phase epitaxial regrowth. Thin Solid Films 369, 228–232 (2000). 27. A. Rosen, M. Caulton, P. Stabile, A.M. Gombar, W.M. Janton, C.P. Wu, J.F. Corboy, and C.W. Magee. Silicon as a millimeter-wave monolithically integrated substrate. RCA Rev. 42, 633–660 (1981). 28. P. Russer. Si and SiGe millimeter-wave integrated circuits. IEEE Trans. Microwave Theory Tech. 46(5) (1998). 29. Y. Konishi, ed. Microwave Integrated Circuits. Marcel Dekker, New York (1991). 30. N.K. Das and H.L. Bertoni, eds. Direction for the Next Generation of MMIC Devices and Systems. Plenum Press, New York (1997). 31. W. Heinrich, J. Gerdes, F.J. Schmu¨ckle, C. Rheinfelder, and K.M. Strohm. Coplanar passive elements on Si for frequencies up to 110 GHz. IEEE Trans. Microwave Theory Tech. 46(5), 709–712 (1998). 32. K.C. Gupta, R. Garg, I. Bahl, and P. Bhartia. Microstrip Lines and Slotlines. Artech House, Boston (1996). 33. H. Hasegawa, M. Furukawa, and H. Yanai. Properties of microstrip line on Si–SiO2 system. IEEE Trans. Microwave Theory Tech. MTT-19(11), 869–881 (1971). 34. Interdigital capacitors and their application to lumped-element microwave integrated circuits. IEEE Trans. Microwave Theory Tech. MTT-18, 1028–1033 (1970). 35. A. Gopinath. Losses in coplanar waveguides. IEEE Trans. Microwave Theory Tech. MTT-30, 1101– 1104 (1982). 36. R.K. Ulrich, W.D. Brown, S.S. Ang, F.D. Barlow, A. Elshabini, T.G. Lenihan, H.A. Naseem, D.M. Nelms, J. Parkerson, L.W. Shaper, and G. Morcan. Getting aggressive with passive devices. IEEE Circ. Dev. 16, 17–25 (2000). 37. J.N. Burghartz, D.C. Edelstein, K.A. Jenkins, and Y.H. Kwark. Spiral inductors and transmission lines in silicon technology using copper–damascene interconnects and low-loss substrates. IEEE Trans. Microwave Theory Tech. 45, 1961–1968 (1997). 38. H.A. Wheeler. Simple inductance formulas for radio coils. Proc. IRE 16, 1398–1400 (1928).

© 2006 by Taylor & Francis Group, LLC

6.4 Engineered Substrates for Electronic and Optoelectronic Systems 6.4.1 6.4.2 6.4.3

Lattice-Matched Substrate World ............................ 6.4-679 Limitations of Lattice-Matched Systems ................. 6.4-680 Age of Lattice-Mismatched Substrate Engineered Materials................................................. 6.4-681 Strain-Relaxed Layers on Substrates through Composition Grading . Transfer of Relaxed Lattice Constants via Wafer Bonding of Virtual Substrates . Low-Temperature CVD Device Layers

6.4.4

Nanoengineered Substrates for MOSFETS ............. 6.4-683 Single Strained Si Channels on Relaxed Si1xGex . Dual-Channel Heterostructures on Relaxed Si1xGex . Nanostructured SiGe Channels . SiGe Nanostructured Channels on Insulator . Future Potential of Nanoengineered SiGe MOSFETs

6.4.5

Eugene A. Fitzgerald Massachusetts Institute of Technology

6.4.6 6.4.7

Engineered Substrates for III–V–Si Integration ................................................................. 6.4-692 Future Engineered Substrates................................... 6.4-694 Market Adoption of Engineered Substrates ............ 6.4-694

6.4.1 Lattice-Matched Substrate World Contemporarily, we analyze the semiconductor systems by a substrate materials class, i.e., ‘‘Si’’ or ‘‘III–Vs.’’ The III–V classification is ultimately split into ‘‘GaAs’’ or ‘‘InP,’’ for example. This nomenclature contains two subtle but important connotations. First, we recognize the importance of the material on the performance of the system. Second, it is assumed inherently that materials choices are confined to a particular bulk substrate material, e.g., a Si substrate. Bulk is defined here as a substrate grown by a bulk crystal growth technique, which in general employs pulling a crystal from a melt. Semiconductor compounds that form elemental or binary compounds, referred to below as ‘‘bulk semiconductors,’’ are amenable to bulk crystal growth, but miscible alloys of the bulk compounds are not. Thus, all current semiconductor-based systems are built on particular lattice constants allowed by nature. Early in epitaxial growth research, many lattice-mismatched films (i.e., films composed of materials that are alloys of bulk semiconductors) were deposited on bulk semiconductors, but the lattice-mismatch between the film and substrate led to poor material quality in the thin film. A consequence of this epitaxial research was that lattice-mismatched epitaxy, i.e., achieving lattice constants in-between bulk 6.4-679 © 2006 by Taylor & Francis Group, LLC

6.4-680

The Silicon Heterostructure Handbook

semiconductors, was considered impractical. Thus, nearly all electronic and optoelectronic systems are built on lattice constants of the bulk semiconductors. These materials combinations can be seen in Figure 6.4.1 by following the vertical lines of constant lattice-constant up and down the diagram. In Si technology, today a ‘‘silicon wafer’’ is often a silicon epitaxial layer on a bulk substrate. In CD lasers and other applications involving optoelectronics near the 870 nm wavelength, the AlGaAs alloy system on GaAs was employed, as heterostructure devices could be designed without creating lattice mismatch. And for telecommunications applications, InP substrates became the bulk semiconductor of choice, as InGaAsP alloys could be grown lattice-matched to the InP lattice constant and also achieve the desired 1.3 and 1.55 mm wavelength emission required for low-loss transmission in optical fiber. Thus, all commercial and defense semiconductor systems have been developed on bulk semiconductors using lattice constants of the substrate.

6.4.2 Limitations of Lattice-Matched Systems There are limitations of lattice-matched semiconductor systems. The first and most obvious is the rich nature of semiconductor bandgaps and lattice constants in Figure 6.4.1 that have not been accessed due to the restriction of building on the lattice constant of the substrate. In general, electronic performance improves as the lattice constant increases within a class of semiconductor materials. For long wavelength applications, optical properties improve as well, in that the bandgap shrinks as lattice constants increase, allowing ultra-long-wavelength detection. Yet electronic complexity (i.e., device integration density) of the semiconductor system decreases as lattice constant is increased, leading to a forced trade-off between integration density and performance. A related but somewhat different limitation is that the electronic and optoelectronic systems built on these platforms create a separation of platforms throughout the system. For example, Si is the basis for all digital computation, whereas III–V and II–VI materials are the basis for most high-frequency RF and optical interfaces. Thus, electronic systems are now limited by board-level consequences induced by the separation of semiconductor platforms. For example, even if a system is created with the capability of gathering a large amount of optical or RF data with a III–V-based platform, getting that information into Si-based computing platforms is a board-level performance and cost issue.

2.6

AIP

0.477

CdS ZnTe

2.2

0.563

GaP

1.8

0.689 CdSe GaAs

1.4

CdTe

AISb

0.885

InP

Si

1.0

1.240 Ge

GaSb

0.6

2.067

Wavelength (µm)

Energy gap (eV)

AIAs

InAs InSb

0.2 HgS

5.4

5.6

5.8

HgTe

HgSe

−0.2 6.0

6.200

6.2

6.4

−6.200 6.6

Lattice constant (Å) FIGURE 6.4.1 Laboratories.)

Energy gap versus lattice constant of most II–VI, III–V, and IV semiconductors. (From Bell

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-681

The performance limitations described above can be seen in the forced evolution of lattice-matched systems. Staying within the constraints of lattice-matching, researchers in the mid-1980s began to explore incorporating slightly mismatched semiconductor films by keeping the level of mismatch and the film thickness below the critical thickness for dislocation introduction. This effort to squeeze even the slightest enhancement from materials with slightly different lattice constant is evidence of the immense desire to move away from mature, common-lattice-constant systems. Examples of such materials and devices that have migrated into applications are the strained SiGe base heterojunction bipolar transistor (covered extensively elsewhere in this volume), and the pseudomorphic strained InGaAs channel HEMT (pHEMT). In optoelectronic applications, the 980 nm strained InGaAs pump laser is an example of pushing the limit on strained layer critical thickness. It is important to realize that the added performance in these devices is severely limited by the critical layer thickness constraint, and highlights the need for the increased performance that can be released by new materials with new lattice constants.

6.4.3.

Age of Lattice-Mismatched Substrate Engineered Materials

Parallel research efforts over the past 20 years in epitaxy, strain-relaxed semiconductor epitaxy, and wafer-bonding technology are ushering in a new age of lattice-mismatched substrate engineering. Advances in fundamental materials science as well as an increase in demand for electronic and optoelectronic systems uninhibited by lattice-constant constraints show that new engineered substrates can have a large impact in the near and far term. We are entering an age of ‘‘anything on anything,’’ i.e., relaxed buffer technology and wafer bonding together allow a limitless ability to move laterally in Figure 6.4.1. The age of lattice-mismatched materials will allow the integration of any material on any bulk semiconductor substrate. In particular, the most visible area of engineered substrates is currently in relaxed SiGe–Si. The lattice constants in between Si and Ge offer a host of materials and devices that can be constructed in the Si CMOS manufacturing infrastructure, such as low-power or high-frequency CMOS and the integration of III–V photonics with Si. We first describe the three cornerstones that have created this opportunity in engineered substrates, and then describe potential future devices and systems, which may be constructed on these nanoengineered substrates.

Strain-Relaxed Layers on Substrates through Composition Grading About 15 to 30 years ago, the field of lattice-mismatched semiconductors was dominated by experiments and theory elucidating the critical layer thickness. When a slightly lattice-mismatched semiconductor film is grown on top of a substrate, a certain thickness of strained material is deposited before it is energetically favorable to introduce misfit dislocations to relieve the strain, and this thickness is termed the critical thickness. Much of the experimental data collected to elucidate the concept of critical thickness were collected in the InGaAs/GaAs [1] and SiGe/Si [2] materials systems, such experiments focusing on exploring when small levels of mismatch resulted in dislocation formation. This focus arose from the interest in the science of lattice-mismatch, as well as realization that high levels of strain in a film, without relaxation, may be beneficial to devices [3]. This early research led to some eventual commercial successes like the InGaAs pHEMT and the SiGe HBT [4]. Early progress in lattice-mismatched semiconductors has been previously reviewed [5]. As strained layer devices were approaching serious commercial interest, research continued into the critical thickness issue. How misfit dislocations are introduced, i.e., the kinetics of dislocation introduction, became an active area of research, especially experimentally measuring the velocities of dislocations in strained layers [6]. In addition to the velocity of dislocations, it was also shown that nucleation plays an important role, specifically the presence or absence of heterogeneous nucleation sources [7]. It was shown that the critical thickness could be extensively exceeded if a substrate area lacked a nucleation site for dislocation introduction. At the time, this result was still of interest only to extend the degree of strain or thickness that one could contain in a completely strained film. However,

© 2006 by Taylor & Francis Group, LLC

6.4-682

The Silicon Heterostructure Handbook

the experiments showed a path to creating completely relaxed layers with low threading dislocation density, a long-sought goal that was evasive due to the previous lack of understanding in dislocation kinetics. Using this new dislocation information, it was shown in 1991 that it was possible to create low threading dislocation density relaxed SiGe layers on Si [8]. This result opened the door to high mobility strained Si [9] as well as the potential of creating relaxed Ge and GaAs layers on Si for the integration of optoelectronic devices on Si [10]. The key to creating the relaxed alloys like SiGe on Si with low threading dislocation density at the top surface was the use of layers of graded composition grown at relatively high temperatures. Such a structure minimizes dislocation nucleation and encourages maximum threading dislocation propagation, leading to high levels of strain relaxation with relatively low threading dislocation density. In early work, it was recognized that maximum threading dislocation flow in the material during graded buffer deposition was critical to obtaining the combined desire of high relaxation and low threading density. A model was created, predicting a counter-intuitive feature, which was that higher growth temperatures would lead to lower threading dislocation density [10]. Under conditions of gradual grading and relatively thick layers, the model can produce a practical result that can be used to predict threading dislocation density in relaxed buffers [11]: rt ¼

2Rg Rgr eU =kT bBY m «m eff

(6:4:1)

where rt is the threading density at the surface of the relaxed buffer layer, Rg is the growth rate, Rgr is the grading rate (i.e., strain relieved per unit thickness), U is the activation energy for dislocation glide, b is the Burgers vector, B is a constant, Y is the biaxial modulus, m is a number typically between 1 and 2, and «eff is the effective strain the threading dislocation experiences during glide. Note that the strongest factor in reducing threading dislocation density is temperature, since temperature is in the exponent of Equation (6.4.1). The model was first confirmed in the InGaP/GaP [12] system and later in the SiGe/Si system [13]. There are important consequences of Equation (6.4.1) with regard to typical threading dislocation densities as well as the cost of producing relaxed SiGe substrates (also referred to as ‘‘virtual substrates,’’ as the wafer is Si, but the graded composition layer converts the surface to a relaxed SiGe lattice constant, thus creating a surface which would be reminiscent of a bulk SiGe substrate). First, once the highest temperatures are achieved from a practical perspective, the threading dislocation density cannot be influenced drastically by any other variable. For example, at temperatures of 8508C and higher, it is typical that relaxed SiGe layers on Si have threading dislocation densities on the order of 104 to 105 cm2, and further significant reduction just by manipulating growth variables is not possible. Fortunately, this threading dislocation density is low enough for both majority carrier devices in SiGe and also low enough for minority carrier devices in GaAs–SiGe–Si [14]. Second, the lowest cost SiGe substrates will have the greatest perfection, i.e., lowest threading dislocation density. This relationship is embedded in Equation (6.4.1) since the growth rate can increase drastically with increased temperature as long as the activation energy for CVD decomposition is less than the activation energy for dislocation glide. Thus, increased temperature lowers threading dislocation density and increases growth rate, leading to less costly wafers. Recently, relaxed SiGe–Si has been produced commercially using Clbased chemistry at higher growth temperatures, leading to low-cost substrates with threading dislocation densities less than 105 cm2.

Transfer of Relaxed Lattice Constants via Wafer Bonding of Virtual Substrates In addition, moving laterally in between bulk semiconductor substrate lattice constants, the relaxed epitaxial layers on a conventional substrate offer another advantage: the potential usefulness of wafer bonding is released. Traditionally, there were hopes that wafer bonding could be used to at least create engineered substrates with one lattice constant of a bulk substrate on another. For example, a bulk GaAs

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-683

wafer might be bonded to a Si wafer, and a thin layer of GaAs could be transferred by using processing techniques to remove much of the original GaAs substrate, for example. There are application limitations in traditional wafer bonding, such as not being able to create any lattice constant in between bulk substrate lattice constants. In addition, there are processing limitations that limit even the possible applications like GaAs on Si. First, the end markets that drive Si and GaAs are different, and therefore, the scaling of the industry infrastructure is different, resulting in Si wafers being substantially larger than GaAs wafers at any point in time. Thus, economies of scale are not captured as the area of usable Si substrate would be less since the bonded GaAs wafer would be of smaller width. Of course, one could always use smaller Si wafers, but then the CMOS fabrication facility used for the CMOS electronics would be trailing edge and have larger transistors, thus limiting the combined integrated platform from using the best computation platform. Second, the bonding of two bulk substrates with different lattice constants leads to problems due to the materials also having a different coefficient of thermal expansion. For example, InP–Si wafer bonding at high bonding temperatures leads to a shattering of the material due to the fusion of thick materials with differing coefficients of thermal expansion; upon cooling to room temperature, tremendous stress is created, shattering the material or creating a high degree of curvature or fragility in the composite. The use of high-quality relaxed epitaxial layers circumvents the issues that originally faced waferbonding technology. The bulk of both wafers can be of the same material, and second, the substrates are the same size. We have been able to demonstrate that this relaxed buffer bonding is possible even for virtual Ge on Si [15]. We have transferred Ge from the surface of a virtual Ge wafer on Si to an SiO2–Si substrate, creating Ge–oxide–Si, called germanium-on-insulator (GOI). Other examples are silicon– germanium-on-insulator (SGOI) and strained-silicon-on-silicon (SSOS). Both are structures that can only be created with relaxed buffer bonding. With further research in this area, one could potentially create any semiconductor material on another, at any wafer diameter [16]. Furthermore, judicious selection of the virtual substrate platform could allow the transferred layer to be in either relaxed or strained form, thereby adding another degree of freedom to the process.

Low-Temperature CVD Device Layers The third area that has allowed the creation of nanoengineered substrates is low-temperature CVD epitaxy [17]. We have demonstrated that at low enough growth temperatures, thin, flat 2% compressive and 2% tensile films can be created in the SiGe materials system. An example of why low-temperature growth is needed to suppress adatom surface migration is shown in Figure 6.4.2. As previously shown [18] and reconfirmed here, compressive layers are difficult to deposit in a very planar way for significant strains. Compressed layers of Si1yGey on relaxed buffers of Si1xGex (y > x) are required for very high hole mobility as shown below. Flat layers are critical for obtaining high hole mobility, as coherent strain relaxation will produce a roughened interface that degrades hole mobility drastically. Figure 6.4.2 shows that for a compressively strained Ge layer on relaxed Si0.3Ge0.7, a growth temperature of 4008C or less is needed to prevent relaxation through surface roughening, which can then also lead to dislocation nucleation as seen in Figure 6.4.2. Figure 6.4.2(c) shows that flat, thin, highly compressed Ge layers are possible to deposit at low enough temperatures.

6.4.4 Nanoengineered Substrates for MOSFETS Epitaxial relaxed Si1xGex buffer layers [19] create a larger lattice constant on a Si substrate, allowing subsequently grown Si1yGey layers to be strained in tension (y < x) or compression (y > x). Early work in application of strain via relaxed SiGe concentrated on investigating elevated carrier mobility in pure tensile Si layers deposited on relaxed Si1xGex [20, 21]. Relatively short-channel MOSFETs containing strained Si have shown that higher mobility and drain current measured in long-channel devices are retained at shorter channel lengths [22, 23]. Also, recently a strained Si ring oscillator composed of 35-nm gate transistors operated 20% to 40% faster than the control Si ring oscillator [24]. A quantitative

© 2006 by Taylor & Francis Group, LLC

6.4-684

The Silicon Heterostructure Handbook

FIGURE 6.4.2 XTEM of «-Ge grown on Si0.3Ge0.7 at (a) 5508C, (b) 4508C, and (c) 4008C showing evolution of morphology with T («-Ge is the dark layer). The heterostructure in (c) is appropriate for use in surface-channel devices.

method to correlate the effect of mobility enhancement in long and short channels shows that approximately 50% of the long-channel drain current enhancement is obtained in shorter channels [25]. Thus, large MOSFET devices can be used to rapidly probe heterostructures for channel enhancement, as well as limits to processing [26–29]. In this summary, we report on probing advanced SiGe MOSFETs on nanoengineered substrates imparting tensile and compressive strains. The MOSFET fabrication process was selected to speed processing and allow extraction of real channel mobility through measurement of MOSFET drain current [30]. The long-channel MOSFETs were formed in a single mask step and utilized thick (300 nm) deposited gate oxide. No other aspects of the MOSFET were optimized. As demonstrated in many benchmarks to date, these large MOSFETs produce channel mobility data versus effective vertical field or inversion charge identical to more fully processed devices [26].

Single Strained Si Channels on Relaxed Si1xGex The most common strained Si structure for surface-channel MOSFETs is a 10 to 20 nm strained Si layer deposited on a relaxed Si1xGex buffer with x 0.20. nMOSFETs fabricated from such a structure show

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-685

an enhancement in electron mobility of about 1.8 times as compared to the Si control nMOSFETs [22– 26]. With very low-temperature processing, pMOSFETs can show 10% to 20% enhancement [26], although short-channel MOSFETs processed in more commercial processes show the same performance as control Si [25]. Thus, the ‘‘first generation’’ of strained Si substrate will give nMOSFETs an 80% increase in electron mobility and a 20% to 40% increase in nMOS drive current, but the pMOSFET will not see much of an enhancement. Further increases in strain do not increase the electron mobility enhancement in strained Si; however, hole mobility enhancement continues to increase with increasing strain. Early recognition of this potential enhancement for holes had led to investigations using higher Ge compositions in the relaxed buffer to enhance the hole mobility in pMOSFETs. Figure 6.4.3 is a plot of hole mobility enhancement (as compared to control Si MOS devices) for relaxed buffer Ge concentrations greater than x ¼ 0.3 [27]. For structures with x 0.40, the strained Si layer thickness exceeds the critical thickness for misfit dislocation introduction at the strained Si–SiGe interface. In Figure 6.4.3, first note that in the strained Si–Si0.65Ge0.35 structure, the mobility enhancement of holes in the channel decreases as the vertical field (i.e., the inversion charge) is increased (such a decrease is not seen in the electron mobility enhancement). This decrease is the typical problem associated with hole mobility enhancement in strained Si. At high fields in strongly scaled devices (>1 MV/cm), one can see that there will only be a small enhancement remaining, if at all. For x ¼ 0.4 to 0.5, hole mobility enhancement as large as two times can be seen, and it is likely some enhancement will be retained at higher fields despite the presence of misfit dislocations at the strained Si–SiGe interface. Since the enhancements are equal for all buffer concentrations at Eeff 0.6 MV/cm, there appears to be no incentive for further increases in buffer Ge concentrations. However, note for the first time that the rate of enhancement decreases with vertical field has somehow been affected in the strained Si–Si0.5Ge0.5 structure.

Dual-Channel Heterostructures on Relaxed Si1xGex In investigating the potential source of the hole mobility decrease with vertical field, we have noticed that the out-of-plane hole effective mass (m?) is as light, and can be even lighter, than the in-plane effective mass (mk) in strained Si [31, 32]. For the electron in strained Si, m? > mk, the preferred situation for an inversion charge at the SiO2–Si interface. Thus, as the hole mass is lightened by the strain, so is the vertical mass, and, in fact, it may be very light and difficult to contain the DeBroglie wavelength in the

Mobitity enhancement over Cz−Si

ε-Si on Si0.65 Ge0.35

2.4

ε-Si on Si0.6 Ge0.4

2.3

ε-Si on Si0.55 Ge0.45 ε-Si on Si0.5 Ge0.5

2.2 2.1 2.0 1.9 1.8 1.7 1.6 0.3

0.4

0.5 0.6 E eff (MV/cm)

0.7

FIGURE 6.4.3 The mobility enhancement of holes versus vertical field under the gate in pMOSFETs in strained Si for different Ge concentrations in the relaxed Si1xGex buffer.

© 2006 by Taylor & Francis Group, LLC

6.4-686

The Silicon Heterostructure Handbook

strained Si layer. Therefore, it seems reasonable to try and contain the hole wave function in the vertical direction. Inserting a compressed Si1yGey layer (y > x) below the strained Si layer accomplishes this goal, and further increases the in-plane mobility additionally. The compressive strain breaks the degeneracy of the hole valence band, increasing the scattering time. We term the strained Si-compressed SiGe structure a ‘‘dual-channel’’ heterostructure. Figure 6.4.4 is a graph showing the mobility enhancement for a set of dual-channel MOSFETs as well as single-channel MOSFETs for comparison (data from Ref. [28]). Figure 6.4.4 shows that indeed, the dual-channel heterostructures can support very high hole mobility at relatively high vertical fields. Also, the slope of the hole enhancement decrease with field can be less as well, further showing the scalability of these structures. A significant observation of enhancement versus field plots for dual heterostructures is that the rate of hole degradation with field is decreased when the dual-channel layers are kept thin. For example, the maximum hole enhancement for the dual-channel structure on Si0.7Ge0.3 shown in Figure 6.4. was obtained in a structure in which both the strained Si layer and buried compressed SiGe layer were 4 nm. At this thickness, we estimate the hole wave function must be spread across both the strained Si layer and compressed SiGe layer, even at the largest vertical fields we can create in these structures. Thus, it appears that the mixed character of the hole spread across both layers is beneficial. When the structure has thicker layers (8.5 nm), and therefore, a structure closer to true buried-channel structure, the mobility enhancement is less at high field and the slope of the mobility decrease with field is similar to conventional strained Si. Note also in Figure 6.4.4 that the dual-channel structures were created with the same strain level incorporated into the compressed SiGe layer (the difference between the buffer composition and compressed SiGe composition is always held at x ¼ 0.30). The comparison of the data shows that when there is enough strain present to split the valence band degeneracy, the Ge concentration in the compressed layer is the most important factor for hole enhancement. The increased curvature of the valence bands from the increased Ge concentration leads to much lighter holes and increased hole mobility. The two observations noted above led to more advanced single-channel structures: hole wave function hybridizing across two layers and high valence band curvature from Ge. The dual-channel data suggest

% Ge in buried layer (dual-channels only) 60

65

70

75

80

35 40 45 % Ge in relaxed buffer

60

Mobility enhancement over Cz−Si

4.0 Dual-channel Single-channel

3.5

Eeff ~ 0.6 MV/cm 3.0

2.5

2.0

1.5 30

FIGURE 6.4.4 The mobility enhancement of holes versus concentration of Ge in the relaxed buffer. The data for single channels are shown in the open squares, whereas the dual-channel structures are the filled squares. The data are taken with approximately Eeff ¼ 0.6 MV/cm.

© 2006 by Taylor & Francis Group, LLC

6.4-687

Engineered Substrates for Electronic and Optoelectronic Systems

that single-channel heterostructures with very high concentrations of Ge and thin strained Si surface layers may support high enhancements at high field. Finally, we note here that dual-channel structures with a compressed pure Ge layer and a dislocated Si cap layer have shown PMOS mobility enhancement factors greater than eight times [29].

Nanostructured SiGe Channels

Mobility enhancemenr over Cz−Si

We speculate that a hole forced to exist across a thin strained Si layer and a relaxed high-Ge content film will have a character similar to a hole that exists in a structure with a compressed SiGe layer (dual channel). This behavior will occur at a relatively high vertical field, in which the hole can be forced to occupy both the surface strained Si channel and the relaxed SiGe alloy below. The wave function should be hybridized between the two layers. Thus, a split valence band from the strained Si is hybridized with a degenerate high curvature band from the relaxed SiGe alloy. The result should be a split valence band with high curvature, which resembles a compressed SiGe layer band structure. To test this hypothesis, strained Si layers were deposited on relaxed buffers with x ¼ 0.60 and 0.70. The strained Si layers were kept to approximately 4 nm in thickness. The layers were greater than the critical thickness for misfit dislocation introduction. Figure 6.4.5 is a plot of the hole mobility enhancement versus inversion charge. We use inversion charge for the x-axis due to the fact that the exact vertical field experienced by the carriers is not easily determined due to the large band offsets close to the SiO2Si interface. High inversion charge occurs when there is a high vertical field, as in Figure 6.4.3 and Figure 6.4.4, but the exact quantitative relationship requires detailed Poisson–Schrodinger solutions, which incorporate full band structures, band alignments, and three-dimensional effective masses. For both the x ¼ 0.60 and 0.70 single-channel structures, we observe a unique phenomenon in which the hole mobility enhancement factor increases with inversion charge or effective vertical field. Thus, it is possible to have a structure that can host both nMOS and pMOS channels with high carrier mobility enhancements at high vertical fields. We interpret this increase in carrier mobility enhancement as a result of the wave function averaged between the two valence structures. At low fields, the hole resembles the relaxed Si0.4Ge0.6 hole, since the band offset at the strained SiSi0.4Ge0.6 interface forces most of the hole in the buried relaxed Si0.4Ge0.6 material. The enhancement is not large due to alloy scattering; it is well known that the alloy scattering in relaxed SiGe alloys suppresses mobility for most of the alloy compositions, and mobility rises sharply very near the pure Ge and pure Si concentrations [32]. As voltage is applied to the gate and vertical field and inversion charge are increased, more of the hole is

2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 2

4

6

8

10

12

12

14⫻10

N inv (per cm2)

FIGURE 6.4.5 The mobility enhancement versus inversion charge for single-channel strained Si on relaxed Si1xGex alloys with x ¼ 0.60 (circles) and x ¼ 0.70 (squares).

© 2006 by Taylor & Francis Group, LLC

6.4-688

The Silicon Heterostructure Handbook

forced to sample the surface strained Si, thus hybridizing the wave function as described above. The valence band splitting inherited from the strained Si now decreases hole scattering, and mobility is enhanced. At some larger field, the hole should once again occupy mostly the top strained Si layer and exhibit, once again, a decrease in enhancement with vertical field (Figure 6.4.5). Figure 6.4.5 clearly shows that the x ¼ 0.60 structure behaves accordingly. At first, the mobility enhancement rises as the vertical field and inversion charge are increased. At about 1013 cm2, the enhancement starts to level off and decrease slightly with further increases in field. Thus, we suspect that in the leveling-off phase, much of the hole is becoming ‘‘strained-Si-like,’’ and the decrease in mobility enhancement with vertical field is once again observed. A stunning result is that for x ¼ 0.70, the point of leveling-off has been pushed out to very high inversion charge, and therefore, the mobility enhancement nears three times at 1.4 1013 cm2. It is interesting to note that this enhancement is larger than the best dual-channel structure results at these high inversion charge densities. The larger band offset between the strained Si and the Si0.30Ge0.70 dictates that a higher field will be required to pull the majority of the hole into the strained Si, thus creating a higher inflection point for the enhancement versus inversion charge curve. Finally, we must speculate that wave function penetration into the oxide may play an important role in hole scattering in these structures. One can interpret much of the data also with an oxide-penetration perspective. For example, as more of the hole begins to reside in the strained Si layer, recall that the vertical mass is also quite light in the vertical direction. As the hole moves into the strained Si, it becomes larger and more ‘‘unwieldy’’ in the vertical direction, penetrating the gate oxide to a greater extent and decreasing mobility drastically. From this perspective, larger band offsets below the strained Si will keep the hole from penetrating as far into the oxide for a given field or inversion charge. Although the exact reason for the enhancement versus inversion charge curves is unknown, and much future analysis and modeling will be necessary to ascertain the exact mechanisms of enhancement, it is clear that the empirical view regarding a single carrier and its interaction with the layer structure is sufficient to converge on a plethora of very high-mobility pMOS structures, and has shown the ability to engineer the enhancement versus inversion slope in strained Si pMOS. In continuing with the empirical design guidelines discussed so far, a further test of our hypothesis would be to create an environment for the hole such that the band structure ‘‘seen’’ by the hole would be invariant with respect to vertical field. We have constructed, therefore, a MOS structure with a ‘‘digital alloy’’ channel, i.e., one in which the wavelength of the hole is greater than the periodicity of the digital alloy, or superlattice [33]. To apply the appropriate comparison to the other data, the structure consisted of the x ¼ 0.70 substrate, and an approximately 10 nm superlattice was constructed with approximately 1 nm periodicity. The superlattice layers were composed of pure strained Si and x ¼ 0.70 relaxed layers. Thus, the superlattice is nothing more than an ordered intermixing of the x ¼ 0.70 single-channel structure discussed in the last section. However, by distributing the strained Si through the x ¼ 0.70 in the 10 nm superlattice, we have created a thicker layer of material that will provide the hole the same environment, independent of vertical field. The pMOSFETs fabricated from the digital alloy channel described above indeed have a hole enhancement, approximately two times. This is a surprising result, since if we consider the average potential of the digital alloy, it is essentially an ordered version of a tensile, y ¼ 0.35 alloy on relaxed x ¼ 0.70 (the digital alloy is composed of equal thickness x ¼ 0.70 and 0, thus averaging to x ¼ 0.35). Other experiments in our laboratory have shown that such a random alloy structure of y ¼ 0.35 on relaxed x ¼ 0.70 will result in no enhancement as compared to control Si MOS (i.e., tensile alloys on relaxed SiGe for p-channels are generally not useful). Therefore, we conclude that the ordering in the digital alloy is responsible for increasing the scattering time of holes by removing the random alloy scattering of SiGe, in one direction. Figure 6.4.6 is a summary plot of the enhancement factor versus inversion charge for three prototypical structures. The strained Si single-channel structure on relaxed Si0.60Ge0.40 represents the conventional strained Si PMOS structure, in which the hole mobility enhancement is lost with vertical field. The advanced strained Si single channel on Si0.30Ge0.70 shows that the enhancement factor can be

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-689

Mobility enhancement over Cz−Si

3.0 2.8 2.6 2.4 2.2 2.0 ε-Si on Si0.3 Ge0.7 Digital alloy

1.6

ε-Si on Si0.6 Ge0.4

1.5 2

4

6 8 10 N inv (per cm2)

12⫻1012

FIGURE 6.4.6 The mobility in enhancement in pMOSFETs versus inversion charge for the advanced strained Si single-channel structure, the digital alloy structure, and the conventional strained Si channel with a relatively high Ge concentration of x ¼ 0.4.

engineered to increase with increasing inversion charge. Finally, the pMOSFET hole mobility enhancement as a function of inversion charge is also shown. Note that the channel has indeed been engineered such that the mobility enhancement factor is independent of inversion charge, or vertical field. Figure 6.4.6 shows the versatility of the empirical method followed in this work for understanding the band structure effects on a single hole extended over multiple-channel layers.

SiGe Nanostructured Channels on Insulator In the section ‘‘Transfer of Relaxed Lattice Constants via Wafer Bonding of Virtual Substrates,’’ it was mentioned that relaxed buffer bonding opened doors to new engineered substrates, as unattainable bulk lattice constants can be produced on a virtual substrate on Si and then the full-diameter layer of that material can be transferred to a host Si wafer. The first demonstration of this was the creation of SGOI [34–37]. The process is shown in Figure 6.4.7. As described previously, the virtual buffer, in this case SiGe, is bonded to a layer with SiO2 on Si, and the original substrate and graded layer is removed with a standard etch back or exfoliation technique. The result is the ability to transfer SiGe or any strained or unstrained SiGe heterostructure to another wafer. Figure 6.4.8 is a picture showing the transfer of a strained Si–SiGe layer and the resulting heterostructure on insulator. Any of the high-mobility SiGe heterostructures described previously in this chapter can be transferred to ‘‘OI,’’ thus combining the benefits of high mobility with the benefits of SOI. As the relaxed SiGe buffer can be tuned to any lattice constant, Ge on Si can be created and the surface of the virtual Ge wafer can be transferred, creating GOI [15]. There are complications as the planarization of thin virtual Ge layers is more difficult than it is for lower Ge concentrations, but nonetheless it is possible as shown in Figure 6.4.9. Ge-on-insulator can be used for Ge-based electronics or, as is the case for this thicker GOI, for optical devices.

Future Potential of Nanoengineered SiGe MOSFETs Figure 6.4.10 is a summary of all nMOS and pMOS data accumulated to date on the large variety of heterostructures fabricated into MOSFETs in our laboratory. Note that although this paper has concentrated on progress in the hole mobility issue (and therefore, on pMOSFETs), Figure 6.4.10 includes electron mobility enhancements extracted from nMOSFETs fabricated from the same material structure as the pMOSFETs. Thus, at any relaxed buffer Ge concentration, the total enhancements in both nMOS

© 2006 by Taylor & Francis Group, LLC

6.4-690

The Silicon Heterostructure Handbook

Si donor wafer Relaxed Si1−x Gex grade

Relaxed Si1−x Gex Strained Si Relaxed Si1−x Gex grade

Strained Si Relaxed Si1−x Gex SiO2

Si donor wafer (a)

Si handle wafer (b)

Backside grind and Si etch Excess Si1−x Gex Strained Si

SiGe removal Strained Si

Relaxed Si1−x Gex

Relaxed Si1−x Gex

SiO2

SiO2

Si handle wafer (c)

Si handle wafer (d)

FIGURE 6.4.7 Schematic of one method of using relaxed buffer bonding to create SGOI or SSOI.

FIGURE 6.4.8 Cross-sectional TEM of a strained Si–Si0.75Ge0.25 on OI.

© 2006 by Taylor & Francis Group, LLC

6.4-691

Engineered Substrates for Electronic and Optoelectronic Systems

FIGURE 6.4.9 TEM cross section of germanium on insulator, produced from the bonding of a virtual Ge wafer to a SiO2–Si wafer. There is a thin bonding Si layer between the Ge and insulator, and a thin etch stop layer remaining on the top of the Ge layer.

NMOS single-channel PMOS single-channel NMOS dual-channel PMOS dual-channel

Mobility enhancement factor (µ/µ0)

10 9 8 7 6 5 4 3 2

1 0.9 0.8 0

20

40

60

80

100

% Ge in SiGe relaxed buffer

FIGURE 6.4.10 The mobility in enhancements in strained SiGe nMOSFETs and pMOSFETs versus relaxed buffer Ge concentration. Data for both single-channel and dual-channel structures are shown.

and pMOS for the structure can be estimated by looking at the acquired points vertically for the same structure. All of the data were extracted at a vertical field equivalent in the Si controls of about 0.6 MV/cm. The plot reveals some interesting conclusions for the SiGe material system. First, note that the strained Si commercialized today (x 0.20) obtains the highest electron enhancement on the chart, and therefore further improvements via new strained Si substrates require PMOS mobility enhancements, which in turn require relaxed buffers with higher Ge concentrations. Also note that the single channel advanced structures with x ¼ 0.50 to 0.70 also support high electron enhancements, nearly the

© 2006 by Taylor & Francis Group, LLC

6.4-692

The Silicon Heterostructure Handbook

full enhancement observed at lower Ge concentrations, despite the dislocations introduced from the large lattice mismatch between the strained Si and relaxed SiGe buffer. Another observation in Figure 6.4.10 is that the highest PMOS enhancements occur on relaxed buffers with intermediate Ge concentrations (x ¼ 0.40 to 0.70), and not at the end-points (i.e., Si and Ge lattice constants). We believe this indicates the importance of strain in enhancing hole mobility in inversion layers in this materials system. Other issues with lattice constants near the Ge-end of the chart are that nMOS performance is typically very poor when x > 0.70. This degradation of nMOS channels may be related to the use of the strained SiSiO2 gate stack used in all MOSFETs in Figure 6.4.10. Since electrons, like the holes discussed in this chapter, would invariably be mixed over both Si and Ge layers, the poor nMOS performance may be related to the very different band structures of Si and Ge. Having an electron averaging over Si and Ge conduction bands would seemingly create much scattering, as Si has the minimum energy conduction valleys in the h1 0 0i directions, whereas Ge has conduction band minima in the h1 1 1i direction. Finally, note that the highest enhancement observed in our laboratory to date is a dual channel, pure strained Si–pure strained Ge–relaxed Si0.5Ge0.5 structure, demonstrating an electron mobility enhancement of 1.7 for the nMOS, and about a 10 hole mobility enhancement for the PMOS. These data suggest that mobility can be enhanced by approximately 1000% over conventional Si MOS mobility, assuming that short-channel device optimization and low-temperature processing are possible.

6.4.5 Engineered Substrates for III–V–Si Integration Although we have concentrated on describing the impact of relaxed SiGe on channel mobility in MOSFETs, SiGe lattice constants also offer a pathway to integrating III–V materials with Si technology. An engineered substrate composed of both III–V materials and Si could be used to host high-performance optoelectronic circuits with digital processing capability. Early work has shown that virtual Ge on Si can be high enough quality for minority carrier devices, and Ge photodiodes with near-ideal reverse leakage currents were obtained [38]. Since GaAs is nearly the same lattice constant as Ge (see Figure 6.4.1), high-quality Ge virtual substrates can be converted to a GaAsSi substrate by growth of a lattice-matched layer on Ge (Figure 6.4.11). This heterovalent interface can be deleterious if deposition is not initiated properly, as exposure to As at certain temperatures can create antiphase boundaries [39–41]. GaAs grown on Ge–SiGe–Si has high minority carrier lifetime [14], allowing the fabrication of high-efficiency GaAs solar cells on Si [42]. The GaAs–SiGe–Si material is high enough quality that it supports room temperature, continuous wave lasing in GaAs-based lasers on Si. GaAs lasers on Si are considered a test vehicle for the eventual integration of optoelectronics with Si CMOS, since room temperature continuous lasing cannot be achieved with poor quality materials. We have achieved room temperature, continuous wave lasing of AlGaAs/GaAs and AlGaAs/InGaAs quantum well lasers on Si substrates and fabricated primitive optical links [43–45] (Figure 6.4.12). Many materials and processing challenges were overcome to achieve lasing as described in detail in the publications. The laser structures were very primitive, gainguided broad stripe lasers. Such high threshold lasers were constructed for ease and as a demonstration of the material quality. For example, conventional GaAs deposited directly on Si would not have sufficient quality for lasing action. Figure 6.4.13 shows also the improved lifetime of the laser. The first lasers created on Ge–SiGe–Si that lased already lasted more than 20 min (as shown in the figure). This laser lifetime was remarkable for a room temperature, continuous wave laser on Si. And the technology is robust, i.e., unlike earlier reports on GaAs lasers on Si, such lasers could be now created at will. With this advance, we quickly improved the lifetime, as shown in the figure. The improved laser device achieved a lifetime of 4 h. Again, this result is very reproducible, and further improvement is expected as improved laser designs are implemented. Mesa ridge lasers with low threshold currents should improve laser lifetime drastically.

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-693

Al0.6Ga0.4As clad

QW AlGaAs GRINSCH

GaAs Ge

GeSi buffer

200 nm

FIGURE 6.4.11 Cross-sectional TEM image of the first structure to lase, and Figure 6.4.12 shows the improvement of our laser process once lasing was achieved. Shown are the light-voltage curves for the laser diodes on Ge–SiGe–Si and the control GaAs substrate. The y-axis is current in the photodetector, which is detecting the laser light, and that current is linearly related to light from the laser. The L–V curves from the improved GaAs lasers on Si are indistinguishable from the control lasers on GaAs substrates, and the thresholds and quantum efficiency were also nearly identical.

FIGURE 6.4.12 Light intensity (represented on graph by photodetector current) as a function of voltage applied to laser diodes on GaAs and Ge–SiGe–Si substrates (‘‘SiGe substrates’’).

© 2006 by Taylor & Francis Group, LLC

6.4-694

The Silicon Heterostructure Handbook

FIGURE 6.4.13 Laser lifetime at constant optical power out. Initial devices lasted as long as 20 min, whereas new improved devices lasted 4 h.

The window for true monolithic optoelectronic integration on Si has opened. With a properly designed III–V–Si engineered substrate, it will be possible to process the substrate in a Si CMOS fabrication facility and produce Si CMOS digital ICs with optical input and output.

6.4.6 Future Engineered Substrates With the great flexibility to combine thin highly strained materials and materials composed of previously unattainable lattice constants, we can imagine new materials that have not existed before that may have application in microelectronics. As an example, we have recently created a new engineered substrate platform, strained Si on Si (SSOS) [46]. The community has been focusing on combining SOI technology with strained Si, and that motivated the work to demonstrate such combinations early on. However, the potential goes far beyond such linear combinations of existing advanced materials. We have demonstrated that a strained Si layer can be transferred to another silicon wafer, creating a strained Si bulk wafer with no SiGe present. A cross section of the material is shown in Figure 6.4.14. Note that the interface is still bonded with a strength near that of a semiconductor bond, and therefore, the strained Si can be held in place without the need for the original relaxed SiGe and host substrate. There should be an edge-dislocation array at the strained Si–Si interface, since there is a difference in in-plane lattice spacing between strained Si and Si. Figure 6.4.15 is a plan-view TEM image of the strained Si–Si interface, and g*b analysis of the interface shows that the dislocations are edge-type. Also, the spacing of the dislocations is correct for the difference in lattice constant for strained Si–Si. To our knowledge, this is the first material created at this scale that is compositionally the same yet abruptly variant in strain state; i.e., it is a heterojunction that is defined by strain difference only and not by composition difference; it is the first homochemical heterojunction. Although a basic study at this point, it shows that relaxed buffer bonding has great potential for creating new, previously unattainable materials and heterostructures.

6.4.7.

Market Adoption of Engineered Substrates

For the past 30 years, the material of choice for the semiconductor industry has been Si, and Moore’s Law has been pursued by exchanging the manufacturing infrastructure in the supply chain with newer versions of equipment. Each new factory possessed equipment and processes to create higher density circuits on Si, and enough market growth occurred to justify reinvestment into the next factory. Today we are at crossroads. Increased transistor density no longer brings sufficient market growth to reinvest in larger factories. New engineered substrate materials, like strained Si, can be interpreted as aiding the extension of Moore’s Law. Alternatively, strained Si can be considered the beginning of a new

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-695

e-Si Si

Strained Si

Si

2 nm

50 nm

FIGURE 6.4.14 Cross-sectional TEM image of the SSOS structure. Shown at inset is a high-resolution image of the interface.

250 nm

FIGURE 6.4.15 Plan-view TEM image of the strained silicon–silicon interface.

roadmap, in which semiconductor value is delivered through novel circuits on new engineered substrates. In the first case, engineered substrates must be absorbed into the existing large Si CMOS supply chain. This naturally takes time, as the scale of the industry and the lack of knowledge about other parts of the supply chain result in scaling only occurring when critical mass in education of the technology is reached. In the later case, high-performance engineered substrates can be implemented earlier in an integrated supply chain environment for smaller markets. In this case, the market must grow and result in the increasing size of the integrated manufacturer and the supply chain. In either case, bottom– up innovation in semiconductors will take some time, but will allow the semiconductor industry to continue to grow into previously unattainable markets.

© 2006 by Taylor & Francis Group, LLC

6.4-696

The Silicon Heterostructure Handbook

Acknowledgments The author would like to thank Matt Currie, Mike Groenert, Saurabh Gupta, David Isaacson, Andy Kim, Larry Lee, Chris Leitz, Arthur Pitera, Gianni Taraschi, and Vicky Yang. The author is very grateful to the sponsors of the research reviewed in this chapter: The Army Research Office, DARPA Heterogeneous Integration, Singapore-MIT Alliance, MARCO MSD, MARCO IFC, and NSF CMSE central facilities at MIT.

References 1. P.L. Gourley, I.J. Fritz, and L.R. Davidson. Controversy of critical layer thickness for InGaAs/GaAs strained-layer epitaxy. Appl. Phys. Lett. 52(5): 377–379, 1988. 2. A.T. Fiory, J.C. Bean, R. Hull, and S. Nakahara. Thermal relaxation of metastable strained-layer GexS1x/Si epitaxy. Phys. Rev. B 31(6): 4063, 1985. 3. J.M. Woodall, P.D. Kirchner, D.L. Rogers, M. Chisolm, and J.J. Rosenberg. Proceedings of IEEE/ Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987, p. 3. 4. D.L. Harame, J.M.C. Stork, G.L. Patton, S.S. Iyer, B.S. Meyerson, G.J. Scilla, E.F. Crabbe, and E. Ganin. IEDM Tech. Digest, 1988, p. 889. 5. E.A. Fitzgerald. Dislocations in strained-layer epitaxy: theory, experiment, and applications. Mater. Sci. Rep. 7: 87, 1991. 6. R. Hull, J.C. Bean, D.J. Werder, and R.E. Leibenguth. In situ observations of misfit dislocation propagation in GexSi1x/Si (1 0 0). Appl. Phys. Lett. 52(19): 1605–1607, 1988; C.G. Tuppen and C.J. Gibbings. Thin Solid Films 183: 133, 1989. 7. E.A. Fitzgerald. The effect of substrate growth area on misfit and threading dislocation densities in mismatched heterostructures. J. Vac. Sci. Technol. B 7(4): 782–788, 1989. 8. E.A. Fitzgerald , Y.-H. Xie, M.L. Green, D. Brasen, A.R. Kortan, J. Michel, Y.-J. Mii, and B.E. Weir. Totally relaxed GexSi1x layers with low threading dislocation densities grown on Si substrates. Appl. Phys. Lett. 59(7): 811–813, 1991. 9. Y.-J. Mii, Y.-H. Xie, E. A. Fitzgerald , D. Monroe, F.A. Thiel, B.E. Weir, and L.C. Feldman. Extremely high electron-mobility in Si/GexSi1x structures grown by molecular-beam epitaxy. Appl. Phys Lett. 59(13): 1611–1613, 1991. 10. E.A. Fitzgerald , Y.-H. Xie, D. Monroe, P.J. Silverman, J.-M. Kuo, A.R. Kortan, F.A. Thiel, B.E. Weir, and L.C. Feldman. Relaxed GexSi1x structures for III–V integration with Si and high mobility 2-dimensional electron gases in Si. J. Vac. Sci. Technol. B 10(4): 1807–1819, 1992. 11. E.A. Fitzgerald, A.Y. Kim, M.T. Currie, T.A. Langdo, G. Taraschi, and M.T. Bulsara. Dislocation dynamics in relaxed graded composition semiconductors. Mater. Sci. Eng. B 67: 53, 1999. 12. A.Y. Kim, W.S. McCullough, and E.A. Fitzgerald. Evolution of microstructure and dislocation dynamics in InxGa1xP graded buffers Grown on GaP by MOVPE: engineering device-quality substrate materials. J. Vac. Sci. Technol. B 17: 1485, 1999. 13. C.W. Leitz, M.T. Currie, A.Y. Kim, J. Lai, E. Robbins, and E.A. Fitzgerald. Dislocation glide and blocking kinetics in compositionally graded SiGe/Si. J. Appl. Phys. 90: 2730–2736, 2001. 14. R.M. Sieg, J.A. Carlin, S.A. Ringel, M.T. Currie, S.M. Ting, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, and B.M. Keyes. High minority-carrier lifetimes in GaAs grown on low-defect-density Ge/GeSi/Si substrates. Appl. Phys. Lett. 73(21): 3111, 1998. 15. A.J. Pitera, G. Taraschi, M.L. Lee, C.W. Leitz, Z.-Y. Cheng, and E.A. Fitzgerald. Coplanar integration of lattice-mismatched semiconductors with silicon by wafer bonding Ge/Si1xGex/Si virtual substrates. J. Electrochem. Soc. 151: G443, 2004. 16. U.S. Patents: #6,602,613; #6,703,144; #6,680,495; #6,677,655. 17. B.S. Meyerson. UHV/CVD growth of Si and Si:Ge alloys: chemistry, physics, and device applications. Proc. IEEE 80: 1592, 1992.

© 2006 by Taylor & Francis Group, LLC

Engineered Substrates for Electronic and Optoelectronic Systems

6.4-697

18. Y.-H. Xie, G.H. Gilmer, C. Roland, P.J. Silverman, S.K. Buratto, J.Y. Cheng, E.A. Fitzgerald, A.R. Kortan, S. Schuppler, M.A. Marcus, and P.H. Citrin. Semiconductor surface roughness: dependence on sign and magnitude of bulk strain. Phys. Rev. Lett. 72: 3006, 1994. 19. E.A. Fitzgerald, Y.H. Xie, M.L. Green, D. Brasen, A.R. Kortan, J. Michel, Y.J. Mii, and B.E. Weir. Totally relaxed GexSi1x layers with low threading dislocation densities grown on Si substrates. Appl. Phys. Lett. 59(7): 811–813, 1991. 20. Y.J. Mii, Y.H. Xie, E.A. Fitzgerald, D. Monroe, F.A. Thiel, B.E. Weir, and L.C. Feldman. Extremely high electron-mobility in Si/GexSi1x structures grown by molecular-beam epitaxy. Appl. Phys. Lett. 59(13): 1611–1613, 1991. 21. F. Schaffler, D. Tobben, H.J. Herzog, G. Abstreiter, and B. Hollander. High-electron-mobility Si/SiGe heterostructures — influence of the relaxed SiGe buffer layer. Semicond. Sci. Technol. 7(2): 260–266, 1992. 22. J. Welser, J.L. Hoyt, and J.F. Gibbons. IIA-4 Temperature and scaling behavior of strained-Si N-Mosfets. IEEE Trans. Electron Dev. 40(11): 2101, 1993. 23. K. Rim, J.L. Hoyt, and J.F. Gibbons. IEEE Trans. Electron Dev. 47: 1406, 2000. 24. Q. Xiang, J.-S. Goo, H. Wang, Y. Takamura, B. Yu, J. Pan, A. Nayfeh, A. Holbrook, F. Arasnia, E. Paton, P. Besser, M. Sidorov, E. Adem, A. Lochtefeld, G. Braithwaite, M.Currie, R. Hammond, M. Bulsara, and M.-R. Lin. Proceedings of the First International SiGe Technology and Device Meeting, 2003, p. 13. 25. A. Lochtefeld and D.A. Antoniadis. On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? IEEE Electron Dev. Lett. 22(2): 95–97, 2001. 26. M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, and D.A. Antoniadis. Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates. J. Vac. Sci. Technol. B 19: 2268, 2001. 27. C.W. Leitz, M.T. Currie, M.L. Lee, Z.Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 92(7): 3745–3751, 2002. 28. C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Hole mobility enhancements in strained Si/Si1yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1xGex (x < y) virtual substrates. Appl. Phys. Lett. 79(25): 4246–4248, 2001. 29. M.L. Lee, C.W. Leitz, Z.-Y. Cheng, A. Pitera, T.A. Langdo, M.T. Currie, G. Taraschi, E.A. Fitzgerald, and D.A. Antoniadis. Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si1xGex/Si virtual substrates. Appl. Phys. Lett. 79(20): 3344–3346, 2001. 30. M.A. Armstrong. PhD Thesis. Technology for SiGe heterostructure-based CMOS devices MIT, 1999, p. 171. 31. D.K. Nayak and S.K. Chun. Low-field hole mobility of strained Si on (1 0 0) Si1xGex substrate. Appl. Phys. Lett. 64(19): 2514–2516, 1994. 32. M.V. Fischetti and S.E. Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys. 80(4): 2234–2252, 1996. 33. M.L. Lee and E.A. Fitzgerald. Hole mobility enhancements in nanometer-scale strained silicon heterostructures grown on Ge-rich relaxed Si1xGex . J. Appl. Phys. 94(4): 2590–2596, 2003. 34. G. Taraschi, T.A. Langdo, M.T. Currie, E.A. Fitzgerald, and D.A. Antoniadis. Relaxed SiGeon-insulator fabricated via wafer bonding and etch back. J. Vac. Sci. Technol. B 20(2): 725–727, 2002. 35. L.J. Huang, J.O. Chu, D.F. Canaperi, C.P. D’Emic, R.M. Anderson, S.J. Koester, and H.-S.-P. Wong. SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors. Appl. Phys. Lett. 78(9): 1267–1269, 2001. 36. Z. Cheng, G. Taraschi, M.T. Currie, C.W. Leitz, M.L. Lee, A. Pitera, T.A. Langdo, J.L. Hoyt, D.A. Antoniadis, and E.A. Fitzgerald. Relaxed silicon–germanium on insulator substrate by layer transfer. J. Electron. Mater. 30(12): L37, 2001. 37. T. Tezuka, N. Sugiyama, and S. Takagi. Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction. Appl. Phys. Lett. 79(12): 1798–1800, 2001.

© 2006 by Taylor & Francis Group, LLC

6.4-698

The Silicon Heterostructure Handbook

38. S. Samavedam, M. Currie, T. Langdo, and E.A. Fitzgerald. High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers. Appl. Phys. Lett. 73: 2125, 1998. 39. E.A. Fitzgerald , J.-M. Kuo, Y.-H. Xie, and P.J. Silvennan. Necessity of Ga pre-layers in GaAs/Ge growth using gas-source molecular beam epitaxy. Appl. Phys. Lett. 64: 733, 1994. 40. S. Ting, R. Sieg, S. Ringel, and E. A. Fitzgerald. Range of defect morphologies on GaAs grown on Offcut(0 0 1) Ge substrates. J. Electron. Mater. 27: 451, 1998. 41. R. Sieg, S. Ringel, S. Ting, S. Samavedam, M. Currie, T. Langdo, and E.A. Fitzgerald. Toward devicequality GaAs growth by molecular beam epitaxy on offcut Ge/Si1xGex/Si substrates. J. Vac. Sci. Technol. B 16(3):1471, 1998. 42. S. Ringel, J.A. Carlin, C.L. Andre, M.K. Hudait, M. Gonzalez, D.M. Wilt, E.B. Clark, P. Jenkins, D. Scheiman, A. Allerman, E.A. Fitzgerald, and C.W. Leitz. Single junction InGaP/GaAs solar cells grown on Si substrates with SiGe buffer layers. Prog Photovolt.: Res. Appl. 10: 417, 2002. 43. M.E. Groenert, C.W. Leitz, A.J. Pitera, V.K. Yang, H. Lee, R.J. Ram, and E.A. Fitzgerald. Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers. J. Appl. Phys. 93(1): 362–367, 2003. 44. M. Groenert, A. Pitera, R.J. Ram, and E.A. Fitzgerald. Improved room-temperature continuous wave GaAs/AlGaAs and InGaAs/GaAs/AlGaAs lasers fabricated on Si substrates via relaxed graded GexSi1x buffer layers. J. Vac. Sci. Technol. B 21(3): 1064–1069, 2003. 45. V.K. Yang, M.E. Groenert, G. Taraschi, C.W. Leitz, A.J. Pitera, M.T. Currie, Z. Cheng, and E.A. Fitzgerald. Monolithic integration of III–V optical interconnects on Si using SiGe virtual substrates. J. Mater. Sci.: Mater. Electron. 13(7): 377–380, 2002. 46. D.M. Isaacson and E.A. Fitzgerald, patents pending.

© 2006 by Taylor & Francis Group, LLC

6.5 Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7

Robert Hull University of Virginia

6.5.8

Scope of this Chapter................................................ 6.5-699 Introduction............................................................... 6.5-699 Roughening and Islanding as a Strain-Relief Mechanism................................................................. 6.5-700 Equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System ........................ 6.5-702 Non-equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System ........................ 6.5-704 Controlled Growth of Quantum Dot Arrays.................................................................. 6.5-705 Potential Nanoelectronic and Nanophotonic Device Applications................................................... 6.5-708 Summary .................................................................... 6.5-709

6.5.1 Scope of this Chapter In this chapter, strain-driven morphological instabilities and transitions in the Ge(Si)–Si(1 0 0) system are described, and current understanding of the fundamental mechanisms governing these phenomena summarized. The degree to which these processes may be controlled and organized to produce arrays of semiconductor ‘‘quantum dots’’ (QDs) with potential nanoelectronic or nanophotonic applications is also discussed. Due to length limitations these discussions are necessarily limited to key concepts and phenomena; for more detailed discussions of fundamental phenomena, several excellent, longer reviews exist [For example, 1–3]. A note on nomenclature: in the subsequent discussion, the format GexSi1x means that the structures under discussion are comprised explicitly of an alloy of Ge and Si, the format Ge(Si) means they are comprised of either pure Ge or GexSi1x alloy material.

6.5.2 Introduction As described elsewhere in this volume, the lattice parameter mismatch between Ge and Si — about 4.1% at room temperature — produces enormous stored strain energies in epitaxial Ge–Si heterostructures. For the case of GexSi1x–Si heterostructures, the lattice parameter difference scales approximately as the Ge fraction, x . Linear, isotropic elasticity theory shows that the biaxial strain, «; the 6.5-699 © 2006 by Taylor & Francis Group, LLC

6.5-700

The Silicon Heterostructure Handbook

stress, s; and the stored elastic strain energy per unit interface area, E; in a coherent (i.e., dislocationfree), epitaxial film of GexSi1x on a rigid Si substrate is given by « ¼ 0:041x

(6:5:1)

s ¼ 2G «(1 þ y)=(1 y)

(6:5:2)

2

E ¼ 2Gh« (1 þ y)=(1 y)

(6:5:3)

Here G, y, and h are the shear modulus, Poisson’s ratio, and thickness of the epitaxial film, respectively. Note that the quoted elastic strain value is at room temperature — differential thermal expansion coefficients between Ge(Si) and Si can amount to a few percent of the lattice mismatch strain at the growth temperature [4], and are additive to the elastic strain for GexSi1x –Si (i.e., the thermal expansion coefficient for Ge, 5.9 106 K1 is greater than that for Si, 2.2 106 K1). The elastic strain is compressive, i.e., the lattice parameter of Ge(Si) is greater than that of Si. Using tabulated values for G and y, the biaxial stress in the coherent GexSi1x film is of order 10x GPa, and the volumetric stored elastic strain energy is several hundred megajoules per m3 for pure Ge/Si. These enormous strain energies and stresses will seek routes to relax, and the main relaxation mechanisms are summarized in Figure 6.5.1. In the absence of any relaxation mechanisms (Figure 6.5.1(a)) the epitaxial layer grows coherently and in planar fashion. The lattice strain causes a tetragonal distortion of the unit cell, and the epitaxial layer strain, stress and elastic stored energy are given in Equation (6.5.1) to Equation (6.5.3). A general mechanism for epitaxial strain relaxation is roughening or islanding of the surface, and is the main mechanism of interest in this chapter. As shown in Figure 6.5.1(b), this allows the interatomic bonds at the surface to relax toward their equilibrium lengths. Other strain-relaxation mechanisms are interfacial misfit dislocation injection, as described elsewhere in this volume, and interfacial interdiffusion (Figure 6.5.1(d) and (c)) respectively. Of course, all three relaxation mechanisms can and do operate to differing degrees in parallel. The primary goal of this chapter is to describe in some detail the mechanism (Figure 6.5.1(b)), and how it can be used to controllably generate heteroepitaxial clusters of Ge(Si) on Si surfaces that can be viewed as quantum dots, i.e., as individual electronic or optoelectronic device elements that can store, transfer, absorb or emit electrons, holes, or photons.

6.5.3 Roughening and Islanding as a Strain-Relief Mechanism The introduction of surface topography into a compressively strained film allows relaxation of bond length and angles in the surface region, and thereby allows the relaxation of strain energy in the system.

FIGURE 6.5.1 Schematic illustrations of strain-relief mechanisms in lattice-mismatched heteroepitaxy. (a) Tetragonal coherent straining of the epitaxial layer. (b) Strain relaxation through surface topography. (c) Strain relaxation through interdiffusion. (d) Strain relaxation through misfit dislocation injection.

© 2006 by Taylor & Francis Group, LLC

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

6.5-701

Of the mechanisms described in Figure 6.5.1, this particular mechanism tends to be the most dominant at lower epitaxial film thicknesses, where the perturbed surface region is a greater fraction of the total epitaxial film thickness. Surface topography does also persist to greater epitaxial film thicknesses, and generally couples with misfit dislocation injection in this limit. Islanding in the Ge(Si)–Si system is also frequently coupled with interdiffusion with the Si substrate, as will be discussed later in this chapter. As first demonstrated by Eaglesham and Cerullo [5], deformation of the local substrate region also occurs. The formation of coherent islands in strained layer epitaxy — at least in systems with relatively high lattice mismatch strain (greater than a few percent or so) generally occurs in the Stranski–Krastanov mode, as is the case for Ge(Si)–Si [5]. In this growth mode, the heteroepitaxial deposit initially wets the substrate as a planar thin film. In epitaxy of pure Ge on Si(1 0 0), this ‘‘wetting layer’’ is generally a few atomic monolayers thick. Subsequent growth of the heteroepitaxial film then occurs by growth of strained islands on the wetting layer. It is these islands that can be viewed as potential ‘‘quantum dots’’ for nanoelectronic or nanophotonic applications. In epitaxy of pure Ge–Si(1 0 0), the subsequent morphological evolution follows a well-documented series of transitions of island geometries that minimize the combined contributions of surface and strain energies, as will be described in the next section of this chapter. In principle, the same series of transitions occur for GexSi1x –Si(1 0 0) epitaxy, but it is observed that the associated length scales increase substantially with decreasing strain [6–8]. Thus, a key issue becomes whether there is sufficient adatom mobility at the operative growth rates and growth temperatures to realize surface transport over the necessary length scales to attain the equilibrium structures. In the limit of the equilibrium structures attained, the observed surface morphological states relax of order 30 to 50% of the elastic strain [6]. In regimes of more limited adatom mobility, more complex morphological states are observed, as will be discussed in a later section. For lower misfit (ca. 2% lattice mismatch) strain, wetting layer thicknesses are sufficiently large that morphological strain relaxation can be viewed as a roughening, rather than as an islanding transition. In either event, models of strain relief are generally formulated in continuum or atomistic frameworks. Continuum approaches generally balance the relief of elastic strain energy with the increase in surface energy caused by surface roughening [9–14]. Atomistic formulations generally minimize the total system energy, including contributions from step and step interaction energies [15–17]. Strain-driven surface roughening may be understood in terms of diffusive mass transport from regions of high to low strain energy density. Consider a coherent lattice-mismatched film with an undulated surface. The lattice mismatch strain will produce a nonuniform stress distribution, with relaxation (and hence lower strain energy density) at the peaks of the perturbation and stress concentrations (higher strain energy density) in the troughs (Figure 6.5.2). The resulting lateral variation in strain energy density drives atomic transport from troughs to peaks. Opposing this transport is the resulting increase in surface energy. Continuum models show that above a critical wavelength of the surface morphology (i.e., such that the amount of additional surface area created is less than for a topology of the same amplitude but lower wavelength), the relief of strain energy is the dominant process in the system [11, 12]. Thus, both the amplitude of the perturbation and the magnitude of the variation of stress distribution between peak and trough are predicted to grow. In the case of Ge(Si)– Si(1 0 0) epitaxy, this, in turn, leads to preferential bonding of Ge atoms at the peaks, where the local lattice parameter is larger [18]. These continuum approaches predict that any planar strained film is unstable with respect to roughening as a strain-relief mechanism. Atomistic frameworks inherently incorporate energy barriers to roughening or islanding transitions, because of the energy associated with the atomic steps necessary to create surface morphology. They, thus, predict that planar-strained films are metastable with respect to roughening. Of course, atomic steps are always present on a surface, particularly in the case of standard Si(1 0 0) substrates, which are typically only specified to azimuthal directions within a few tenths of a degree of (1 0 0) — thus necessarily containing relatively high-step densities (interspersed by regions of (1 0 0) terrace) to accommodate the substrate misorientation. In fact, interaction energies between these steps produce a likely mechanism for surface roughening or islanding. In the case of compressively strained Si (and, by

© 2006 by Taylor & Francis Group, LLC

6.5-702

The Silicon Heterostructure Handbook

Stress (GPa) 0.33 −0.19 −0.71 Ge0.3 Si0.7

−1.23 −1.75 −2.27

Si substrate

−2.79 −3.31 −3.83 −4.35

FIGURE 6.5.2 Finite element calculation using anisotropic elastic constants of the stress distribution (sxx , perpendicular to the sinusoidal modulations) in a Ge0.3Si0.7 film with a mean thickness of 50 nm and a one-dimensional sinusoidal surface modulation with an amplitude of 40 nm and a period of 250 nm. Stress contours are in GPa, where negative values correspond to compressive stress in the film. Calculations are performed with ANSYS 7.1 Figure courtesy C.C. Wu.

extension, Ge and GexSi1x), step interaction energies encourages bunching of surface steps [19, 20]. This provides a potential mechanism for the initial formation of islands and roughened surfaces in strained epitaxial films [7, 8]. Such atomistic models provide more realistic treatments of the initial formation of rough surfaces, and help explain the specific morphological transitions that occur in the Ge(Si)–Si(1 0 0) system. Continuum approaches, however, have provided key insight into the balance between strain energy and surface energy in roughening transitions. In summary, both sets of models have provided a strong foundation for both qualitative and quantitative understanding of morphological transitions in Ge(Si)–Si(1 0 0), and many other strained layer systems.

6.5.4 Equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System With the background of the previous section, observed morphological transitions in the Ge(Si)–Si(1 0 0) system may be qualitatively (and, to a degree, quantitatively) understood. We first concentrate on the series of equilibrium transitions in Ge–Si(1 0 0), and then extrapolate to GexSi1x –Si(1 0 0). As described previously, the fundamental growth mode in Ge(Si)–Si is the Stranski–Krastanov mode, whereby a thin wetting layer is first formed, followed by island formation. The thickness of the wetting layer for Ge–Si(1 0 0) is of order a few monolayers, depending somewhat upon the growth conditions and the exact surface chemistry. Atomistic details of the evolution of this Ge wetting layer on Si(1 0 0)

© 2006 by Taylor & Francis Group, LLC

6.5-703

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

are described in Ref. [2]. The initial islands that form on the wetting layer surface are of relatively low aspect (height–diameter) ratio, and evolve relatively rapidly into a geometry that is bounded primarily by {5 1 0} facets, the so-called ‘‘hut cluster’’ geometry, as described by Mo et al. [21]. (Note that intermediate stages between the planar wetting layer and the hut cluster geometry also exist, e.g., Ref. [22].) The hut clusters are coherent to the substrate (i.e., free of misfit dislocations). In this first stage of the morphological evolution, minimization of surface energy (that scales with surface area) is more significant than minimization of strain energy (an approximately volumetric term). In strained Ge(Si), the {5 1 0} surface has a particularly low energy [23], discouraging growth to higher aspect ratio facets which, while they would be more efficient in reducing strain energy, have higher surface energy. As the individual clusters grow, volumetric energy terms (i.e., strain energy) become increasingly important with respect to areal energy terms (i.e., surface energy), and the clusters undergo a transition to a higher aspect ratio geometry, termed ‘‘dome clusters’’ bounded predominantly by {3 1 1} facet [24]. This facet represents the next major cusp in the energy-orientation diagram, and thus produces a dome cluster configuration whose decrease in surface energy with respect to a hut cluster of the same volume more than compensates for the increase in strain energy. For pure Ge–Si(1 0 0) the initial dome clusters are still coherent to the substrate. With increasing growth of the dome clusters, they eventually dislocate. Subsequent growth beyond this coherent–incoherent transition has been shown to be cyclical, according to the need to digitally introduce additional dislocations, each of which has an energy barrier associated with its introduction [25]. These morphological transitions are summarized in Figure 6.5.3. The length scales associated with these transitions have been studied by multiple authors. In particular, the transition between the cluster and dome states has received much attention, and generally occurs at lateral island dimensions of order a few tens of nanometers [26, 27]. The transition between coherent and dislocated domes generally occurs at dimensions of order 60 to 70 nm [28, 29]. It should be stressed that these dimensions pertain to growth on clean Si(1 0 0) surfaces, and for Ge growth temperatures and deposition rates where the time at temperature is such that significant diffusion does not occur between Ge clusters or wetting layer and the Si substrate. Relatively rapid stress-enhanced diffusion occurs between these entities, as been documented by multiple authors [30–33]. With increasing Si incorporation into the clusters, the cluster strain is reduced, and the corresponding length scales of transitions (i.e., from hut to dome, and from coherent dome to incoherent dome) increase. The chemical state of the substrate is also key in determining the relevant length scales. The effects of surfactant species, such as P, Ga, and B, have been studied by several authors [34–37], and have shown that cluster facets, aspect ratios, and transition dimensions are affected by the presence of the surfactant

(a)

(b)

(c)

(d) <311>

<510>

Substrate Wetting layer

Hut clusters

Domes

Dislocated domes

FIGURE 6.5.3 Equilibrium series of morphological transitions for Ge(Si)–Si(1 0 0). (a) Ge wetting layer, (b) {5 1 0} facetted hut cluster, (c) coherent dome cluster with dominant {3 1 1} facet, and (d) dislocated dome cluster.

© 2006 by Taylor & Francis Group, LLC

6.5-704

The Silicon Heterostructure Handbook

species. For example, the transition from coherent to dislocated clusters was found to be reduced to 20–30 nm as a function of the presence of Ga from near-surface focused ion beam (FIB) implantation [35], corresponding to a significant increase in the cluster aspect ratios with respect to classic hut and dome geometries on the clean Si(1 0 0) surface. In addition, chemical surfactants can also cause the growth mode to change from the Stranski–Krastanow to Frank van der Merwe (i.e., three-dimensional clusters without a wetting layer). Essentially similar sets of transitions (wetting layer–hut clusters–dome clusters) have been observed for GexSi1x –Si(1 0 0) epitaxy for Ge compositions as low as x ¼ 0.2 (« ¼ 0.01) in the limit where the growth temperature is sufficiently high that adatom mobility is high enough to allow the equilibrium lengths scales to be attained [6]. Evolution of the wetting layer into {5 1 0} facetted hut clusters via growth and increasing contact angle of stepped mounds in GexSi1x –Si(1 0 0) has been observed by real-time LEEM imaging [7, 8]. A number of studies have shown that length scales (wetting layer thickness, cluster transition dimensions, etc.) scale inversely with strain [6–8], so reducing the strain in the system means that adatoms have to migrate further to achieve equilibrium structures — for example achieving the wetting layer–hut cluster–coherent dome cluster sequence at x ¼ 0.2 in GexSi1x –Si(1 0 0) requires growth temperatures 7008C or higher [6]. At lower growth temperatures, with more limited adatom migration lengths, different configurations are observed, as summarized in the next section.

6.5.5 Non-equilibrium Strain-Driven Morphological Transitions in the Ge(Si)–Si System We have established in the previous section that a well-defined series of morphological transitions occurs under conditions of sufficient adatom mobility to allow attainment of equilibrium microstructures in the Ge(Si)–Si(1 0 0) system. However, under conditions of reduced adatom mobility, different microstructures form. At sufficiently reduced growth temperatures (whose magnitudes depend strongly upon lattice mismatch strain, but are typically below about 350 to 4008C), surface migration lengths and islanding or roughening are largely suppressed. Under these conditions the film necessarily grows in a quasi-planar fashion, but with high densities of point defects (and for sufficiently high epitaxial layer thicknesses, interfacial misfit dislocations). Such structures contain extremely high strain energy densities. A more complex regime is the region of intermediate adatom migration lengths, i.e., where adatoms can diffuse over significant distances, but not over sufficient lengths to attain the equilibrium microstructures described in the previous section. In this intermediate regime, periodic surface roughening is frequently observed, as described in Section 6.5.3 [18, 38–40]. However, under specific ranges of kinetically limited growth conditions, well-defined but more complex microstructures may exist. We have recently described a new metastable morphological transition state that occurs during growth of GexSi1x–Si(1 0 0) with 0.2 < x < 0.4 within the specific ranges of epilayer growth temperature and growth rate [41–44], the ‘‘quantum dot molecule.’’ The essential microstructural evolution is shown in Figure 6.5.4. First, shallow pits are observed to form in the growing epitaxial layer. These pits are square (bounded by h0 0 1i directions on the growth surface), are strain relieving, do not penetrate nearly as deep as the original Si–GexSi1x interface, and so far as can be ascertained are not associated with extrinsic effects such as crystalline defects or impurities. With subsequent epilayer growth, small islands of GexSi1x material form at each pit edge, and grow to form a continuous wall. At this point, the facet angles of both pits and bounding island walls have stabilized at {5 1 0}. In subsequent growth, both the ‘‘molecule’’ geometry and size (which depends upon the magnitude of the strain in the epilayer, but is ca. 220 nm for Ge0.3Si0.7) are fixed, i.e., during subsequent epilayer growth, i.e., the structure essentially conformally ‘‘floats’’ on the growth surface [44]. Such microstructures may have significant application to exploratory nanoelectronic architectures such as quantum cellular automata (QCAs), as described in later sections of this chapter. A similar geometry microstructure has been previously reported in the

© 2006 by Taylor & Francis Group, LLC

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

(a)

6.5-705

(b)

(c)

FIGURE 6.5.4 Evolution of the quantum dot molecule surface morphology for growth of Ge0.3Si0.7 –Si(1 0 0) at a growth temperature of 5508C and a growth rate of 0.9 A/sec. AFM scans are 5 mm 5 mm in area. Ge0.3Si0.7 film thicknesses are (a) 0, (b) 15, and (c) 30 nm. Image (a) shows that immediately following growth of the Si buffer layer, the surface is close to atomically flat morphology with no pre-existing pits. Enlarged images of quantum dot molecule structures are shown in the insets to (b) and (c). The RMS surface morphology amplitudes are 0.14, 0.21, and 1.1 nm in (a), (b), and (c), respectively. (Images by J. Gray, J. Floro, and R. Hull. With permission.)

literature, but in that case was linked directly to carbon contamination at the Si substrate–Si buffer layer interface [45]. Neither the geometry, nor the evolution, of the present quantum dot molecules are consistent with that microstructural history.

6.5.6 Controlled Growth of Quantum Dot Arrays For the great majority of electronic or nanoelectronic device architectures that might employ quantum dots, ordering of the quantum dots, either into single spatial frequencies or into more complex patterns, is desirable or necessary. Thus, there has been a great deal of work in the literature focusing upon techniques to control the nucleation sites for quantum dots, or seeking mechanisms by which the quantum dots self-organize into ordered arrays.

© 2006 by Taylor & Francis Group, LLC

6.5-706

The Silicon Heterostructure Handbook

Perhaps the earliest work on the formation of ordered quantum dot arrays was based upon harnessing the strain field interactions between quantum dots. In ‘‘quantum dot superlattices,’’ where successive layers of quantum dots are separated by intervening spacer layers of the same material as the substrate (i.e., in the present case, layers of coherent Ge(Si) quantum dots separated by Si spacer layers), strain field interactions between quantum dots increasingly organize the two-dimensional arrays of dots in successive layers [46, 47]. This is because the strain field associated with a Ge quantum dot in one layer produces a surface strain (dilation) field that encourages localized nucleation of a QD in the successive layer. Thus the QDs form in columns. Further, the three-dimensional minimization of the total crystal strain energy encourages the QDs to organize within the two dimensions of each QD layer [46] (this can be accomplished by tilting, or even by the disappearance of individual columns). These processes are illustrated by three-dimensional tomographic FIB images in Figure 6.5.5. It should be emphasized that one challenge in creating such QD superlattice structures is that on Si capping, individual dots often dramatically decrease their aspect ratio (i.e., flatten), particularly for dots with higher Ge concentrations and at higher growth temperatures [48, 49]. Maintenance of Ge(Si) quantum dot aspect ratios therefore generally requires growth of a lower temperature (ca. 300 to 3508C) layer at the start of the capping sequence, followed by ramping to the standard epitaxial growth temperature to recover crystalline quality [50]. But how can quantum dots be organized into either more complex patterns, or single layers of quantum dots be ordered into a periodic array? One method is to lithographically open windows in, for example, an SiO2 layer on a Si substrate, and to achieve local nucleation of Ge in the windows [51, 52]. A broader set of mechanisms is available through appropriate ‘‘templating’’ of the substrate surface. As illustrated in Figure 6.5.6, there are multiple mechanisms by which local surface modification can be expected to control nucleation sites for quantum dots. One method is to introduce topography into the surface. The additional degree of freedom associated with a free edge creates a logical site for a strained nucleus to form, as the underlying substrate can more readily deform. The use of mesa edges and facets has been demonstrated to be highly effective in localizing nucleation [53–56]. Similarly, at the more atomistic scale, steps or step bunches are preferred attachment sites [57]. Additional methods are local modification of surface crystallinity or chemistry. Both may affect local adatom diffusivity and attachment energies, thereby localizing the probability of forming a critical nucleus. Another method of modifying the local chemistry is desorption using a scanning probe microscope tip of hydrogen from Si(1 0 0) surfaces at temperatures below 5358C (while the hydrogen-terminated

FIGURE 6.5.5 Focused ion beam tomographic image showing evolution of quantum dot columns in a Ge quantum dot superlattice sample. Ge quantum dot layers are grown with an equivalent planar layer thickness of 1.4 nm at 7508C. Intervening Si spacer layers are grown with 20 nm at 3008C, and 80 nm at 7508C. The spatial resolution in the vertical direction was intentionally decreased so that the evolution of the columns could more easily be observed. The column in blue terminates during the growth of the superlattice structure. (Image courtesy of A. Kubis. With permission.)

© 2006 by Taylor & Francis Group, LLC

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

(a)

(c)

6.5-707

(b)

(d)

(e)

FIGURE 6.5.6 Schematic illustration of basic mechanisms for local modification of substrate surface structure for templated heteroepitaxial assembly. Local modification of (a) crystallinity, (b) topography, (c) surface lattice parameter from buried stressors, (d) surface chemistry, and (e) surface reactivity. ‘‘Atoms’’ are shown as solid circles. The lengths of lateral arrows in (a) and (d) indicate variations in local surface adatom mobility. The solid rectangular regions in (a) and (c) indicate regions of disturbed crystallinity (or second phase inclusions in the case of (c)). The solid rectangular regions in (d) and (e) represent regions of locally modified chemistry.

surface remains stable elsewhere), allowing local epitaxy of Ge in the desorbed regions [58]. Buried strain centers can also localize nucleation because of the creation of associated dilation or compression fields at the crystal surface. For example, both buried SiO2 precipitates [59] and buried misfit dislocations [60–62] have been shown to localize Ge quantum dot nucleation on Si(1 0 0) surfaces. Finally, for the case of chemical vapor deposition (or other related thermally activated deposition mechanisms) variations in local surface chemistry can affect the surface reactivity and hence local deposition rates [34, 63]. One method by which all these mechanisms can be explored is through local Gaþ FIB modification of the substrate surface. The FIB can create controlled local surface topography through sputtering, modifies the surface crystallinity (creating surface amorphization for implantation into Si at room temperature, which can be fully recovered by moderate time–temperature annealing cycles), modifies the local surface chemistry (and hence reactivity) through the implanted species, and creates local strain centers due to residual defects. In Figure 6.5.7, we show how such FIB implantation (performed in conjunction with ultrahigh vacuum chemical vapor deposition, and transmission electron microscope

© 2006 by Taylor & Francis Group, LLC

6.5-708

The Silicon Heterostructure Handbook

FIGURE 6.5.7 Local control of Ge–Si(1 0 0) cluster nucleation by focused ion beam prepatterning. Images are from transmission electron microscope imaging in situ to the FIB and deposition capabilities. Left-hand image shows in situ as-patterned Si(1 0 0) surface (25 keV Gaþ, 10 pA, 100 ms per feature). Right-hand image, following annealing and Ge deposition by chemical vapor deposition (digermane source) at 6008C (Ge clusters are the bright dots as indicated by the red arrow). (Images by M. Kammler, F. Ross, and R. Hull. With permission.)

imaging, all within the same integrated instrument), can successfully localize nucleation in Ge–Si(1 0 0) [35, 42, 63]. In fact this method convolutes possible effects from local modification of surface crystallinity, surface reactivity and strain, but extensive experiments suggest that localized nano-topography and strain fields are the primary mechanism for controlling nucleation [35, 63].

6.5.7 Potential Nanoelectronic and Nanophotonic Device Applications Nanoelectronic and nanophotonic device applications of GexSi1x –Si heterostructures are dealt with extensively elsewhere in this volume, but specific opportunities exist for harnessing the properties of Ge(Si) quantum dots. One exploratory application is the use of QD quadruplets as cells for QCAs [64–66]. In this architecture, extra charges (electrons or holes) will occupy opposite corners of the cell, creating bistable states that can form the basis of digital logic. The quantum dot molecule geometry discussed in Section 6.5.5 has the appropriate geometry to form individual quantum dot cells, providing groups of cells can be organized into the correct patterns for QCA circuits. We have demonstrated the ability to organize the quantum dot molecules using topographic forcing functions on the substrate surface, such that the dimensions of interstices between holes in a two-dimensional array match to the dimensions of the quantum dot molecules (Figure 6.5.8). Other potential uses of quantum dot arrays include single electron transistors [67, 68] and memory elements, either in epitaxial structures or embedded in oxides [69–71]. In all cases, the ability to accurately control the spatial distribution of quantum dots is key to successful realization of these nanoelectronic applications. While Ge, Si, and GexSi1x are of course indirect semiconductors, the optical properties of embedded Ge(Si) quantum dots are also a topic of active research, including the ability to tune optical emission wavelength through the dot dimensions, for example in photovoltaic applications [72–75]. Applications to potential quantum computing applications [58], and thermoelectric properties of Ge quantum dot superlattices are also being explored [76].

© 2006 by Taylor & Francis Group, LLC

6.5-709

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

0.5 ∝m

1 ∝m

FIGURE 6.5.8 Controlled formation of quantum dot molecules by topographic forcing functions (surface topography is created ex situ to the deposition chamber with a focused ion beam). Images are recorded in the atomic force microscope. Left-hand image shows the quantum dot molecule structure. Right-hand image shows ordered arrays formed on patterned substrates with original (i.e., prior to deposition) hole spacings of 250 nm. Inset shows the perspective image of patterned region. In the unpatterned region, quantum dot molecules form at apparently random locations. (Images by J. Gray, J. Floro, and R. Hull. With permission.)

6.5.8 Summary The high mismatch strain in the GexSi1x –Si system provides a natural driving force for cluster (quantum dot) assembly during heteroepitaxy. The equilibrium set of morphological transitions that occur during growth in this system are well documented and reasonably well understood, at least for the (1 0 0) surface. Transitions under nonequilibrium (i.e., kinetically limited) growth conditions are less well explored and understood, although it is clear that fascinating metastable structures, such as the quantum dot molecule, can occur. Substantial progress has been made by several groups in localizing cluster nucleation into desired arrays or patterns, although no technique to date has fully demonstrated the necessary combinations of spatial accuracy, field of view, and acceptably low error rates necessary for practical application of most potential nanoelectronic device concepts. Further advances in this area are necessary to accelerate the development of applications.

Acknowledgments The author acknowledges invaluable discussions and collaborations with many individuals, relevant to the material in this chapter: J. Floro (Sandia); F. Ross, M. Reuter, J. Tersoff, and R. Tromp (IBM); I. Berbezier (CNRS, Marseilles); E. Stach (Lawrence Berkeley); and S. Atha, J. Bean, J. Gray, A. Kubis, M. Kammler, A. Portavoce, T. Pernell, T. Vandervelde, and C.-C. Wu (U. Virginia). Work at the University of Virginia described in this chapter was performed under a Materials Research Science and Engineering Center (DMR0080016), and a Focused Research Group (DMR-0075116), funded by the National Science Foundation.

References 1. A.R. Woll, P. Rugheimer, and M.G. Lagally. Self organized quantum dots. Int. J. High Speed Electron. Syst. 12, 45–78 (2002). 2. D.E. Savage, F. Liu, V. Zielask, and M.G. Lagally. Fundamental mechanisms of thin film growth. In Germanium Silicon: Physics and Materials, R. Hull and J.C. Bean, eds. Academic Press, San Diego, CA, 1999, pp. 49–101. 3. R.M. Tromp and J.B. Hannon. Thermodynamics of nucleation and growth. Surf. Rev. Lett. 9, 1565– 1593 (2002). 4. K.L. Wang and X. Zheng. In Properties of Strained and Relaxed GeSi, E. Kasper, ed. IEEE EMIS Datareview Series No. 12, London, England, 1995, pp. 78–80, and references therein.

© 2006 by Taylor & Francis Group, LLC

6.5-710

The Silicon Heterostructure Handbook

5. D.J. Eaglesham and M. Cerullo. Dislocation-free Stranski–Krastanow growth of Ge on Si(1 0 0). Phys. Rev. Lett. 64, 1943–1946 (1990). 6. J.A. Floro, E. Chason, L.B. Freund, R.D. Twesten, R.Q. Hwang, and G.A. Lucadamo. Evolution of coherent islands in Si1xGex/Si(0 0 1). Phys. Rev. B 59, 1990–1998 (1999). 7. P. Sutter and M.G. Lagally. Nucleationless three-dimensional island formation in low-misfit heteroepitaxy. Phys. Rev. Lett. 84, 4637–4640 (2000). 8. R.M. Tromp, F.M. Ross, and M.C. Reuter. Instability-driven SiGe island growth. Phys. Rev. Lett. 84, 4641–4644 (2000). 9. M. Grinfeld. Two-dimensional islanding atop stressed solid helium and epitaxial films. Phys. Rev B 49, 8310–8319 (1994). 10. W.H. Yang and D.J. Srolovitz. Cracklike surface instabilities in stressed solids. Phys. Rev. Lett. 71, 1593–1596 (1993). 11. B.J. Spencer, P.W. Voorhees, and S.H. Davis. Morphological instability in epitaxially strained dislocation-free solid films: linear stability theory. J. Appl. Phys. 73, 4955–4970 (1993). 12. B.J. Spencer, P.W. Voorhees, and S.H. Davis. Morphological instability in epitaxially strained dislocation-free solid films: nonlinear evolution. Phys. Rev. B 47, 9760–9777 (1993). 13. H. Gao. Stress concentration at slightly undulating surfaces. J. Mech. Phys. Solids 39, 443–458 (1991). 14. L.B. Freund and F. Jonsdottir. Instability of a biaxially stressed thin film on a substrate due to material diffusion over its free surface. J. Mech. Phys. Solids 41, 1245–1264 (1993). 15. J. Tersoff and R.M. Tromp. Shape transition in growth of strained islands: spontaneous formation of quantum wires. Phys. Rev. Lett. 70, 2782–2785 (1994). 16. K.M Chen, D.E. Jesson, S.J. Pennycook, T. Thundat, and R.J. Warmack. Critical nuclei shapes in the stress-driven 2D-to-3D transition. Phys. Rev. B Rapid. Commun. 56, R1700–R1703 (1997). 17. J. Tersoff, Y.H. Phang, Z. Zhang, and M.G. Lagally. Step-bunching instability of vicinal surfaces under stress. Phys. Rev. Lett. 75, 2730–2733 (1995). 18. A.G. Cullis, D.J. Robbins, A.J. Pidduck, and P.W. Smith. The characteristics of strain-modulated surface undulations formed upon epitaxial Si1xGex alloy layers on Si. J. Cryst. Growth 123, 333–343 (1992). 19. N.C. Bartelt, R.M. Tromp, and E.D. Williams. Step capillary waves and equilibrium island shapes on Si(0 0 1). Phys. Rev. Lett. 73, 1656–1659 (1994). 20. C. Duport, P. Politi, and J. Villain. Growth instabilities induced by elasticity in a vicinal surface. J. Phys. 5, 1317–1350 (1995). 21. Y.-W. Mo, D.E. Savage, B.S. Swartzentruber, and M.G. Lagally. Kinetic pathway in Stranski– Krastanov growth of Ge on Si(0 0 1). Phys. Rev. Lett. 65, 1020–1023 (1990). 22. A. Vailionis, B. Cho, C. Glass, P. Desjardins, D.G. Cahill, and J.E. Greene. Pathway for the straindriven two-dimensional to three-dimensional transition during growth of Ge on Si(1 0 0). Phys. Rev. Lett. 85, 3672–3675 (2000). 23. V.B. Shenoy, C.V. Ciobanu, and L.B. Freund. Strain induced stabilization of stepped Si and Ge surfaces near (0 0 1). Appl. Phys. Lett. 81, 364–366 (2002), and references therein. 24. M. Tomitori, K. Watanabe, M. Kobayashi, and O. Nishikawa. STM study of the Ge growth mode on Si(0 0 1) substrates. Appl. Surf. Sci. 76/77, 322–328 (1994). 25. F.K. LeGoues, M.C. Reuter, J. Tersoff, M. Hammar, and R.M. Tromp. Cyclic growth of strain-relaxed islands. Phys. Rev. Lett. 73, 300–303 (1994). 26. G. Medeiros-Ribeiro, A.M. Bratkovski, T.I. Kamins, D.A.A. Ohlberg, and R.S. Williams. Shape transition of germanium nanocrystals on a silicon (0 0 1) surface from pyramids to domes. Science 279, 353–355 (1998). 27. F.M. Ross, R.M. Tromp, and M.C. Reuter. Transition states between pyramids and domes during Ge/Si island growth. Science 286, 1931–1934 (1999). 28. F.M. Ross, J. Tersoff, and R.M. Tromp. Coarsening of self-assembled Ge quantum dots on Si(0 0 1). Phys. Rev. Lett. 80, 984–987 (1998).

© 2006 by Taylor & Francis Group, LLC

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

6.5-711

29. T.I. Kamins, E.C. Carr, R.S. Williams, and S.J. Rosner. Deposition of three-dimensional Ge islands on Si(0 0 1) by chemical vapor deposition at atmospheric and reduced pressures. J. Appl. Phys. 81, 211–219 (1997). 30. J. Tersoff. Enhanced nucleation and enrichment of strained-alloy quantum dots. Phys. Rev. Lett. 81, 3183–3186 (1998). 31. S.A. Chapparro, J. Drucker, Y. Zhang, D. Chandrasekhar, M.R. McCartney, and D.J. Smith. Straindriven alloying in Ge/Si(1 0 0) coherent islands. Phys. Rev. Lett. 83, 1199–1202 (1999). 32. T.I. Kamins, G. Medeiros-Ribeiro, D.A.A. Ohlberg, and R.S. Williams. Dome-to-pyramid transition induced by alloying of Ge islands on Si(0 0 1). Appl. Phys A 67, 727–730 (1998). 33. Y. Zhang, M. Floyd, K.P. Driver, J. Drucker, P.A. Crozier, and D.J. Smith. Evolution of Ge/Si(1 0 0) island morphology at high temperature. Appl. Phys. Lett. 80, 3623–3625 (2002). 34. T.I. Kamins, G. Medeiros-Ribeiro, D.A.A. Ohlberg, and R.S. Williams. Influence of phosphine on Ge/Si(0 0 1) island growth by chemical vapor deposition. J. Appl. Phys. 94, 4215–4224 (2003). 35. M. Kammler, R. Hull, M.C. Reuter, and F.M. Ross. Lateral control of self-assembled island nucleation by focused-ion-beam-micropatterning. Appl. Phys. Lett. 82, 1093–1095 (2003). 36. H. Takamiya, N. Miura, N. Usami, T. Hattori, and Y. Shiraki. Drastic modification of the growth mode of Ge quantum dots on Si by using boron adlayer. Thin Solid Films 369, 84–87 (2000). 37. X. Zhou, B. Shi, Z. Jiang, W. Jiang, D. Hu, D. Gong, Y. Fan, X. Zhang, X. Wang, and Y. Li. Boron-mediated growth of Ge quantum dots on Si(1 0 0) substrate. Thin Solid Films 369, 92–95 (2000). 38. N.-E. Lee, D.G. Cahill, and J.E. Greene. Evolution of surface roughness in epitaxial Si0.7Ge0.3/Si(0 0 1) as a function of growth temperature (200–600 degrees C) and Si(0 0 1) substrate miscut. J. Appl. Phys. 80, 2199–2210 (1996). 39. A.J. Pidduck, D.J. Robbins, A.G. Cullis, W.Y. Leong, and A.M. Pitt. Evolution of surface morphology and strain during SiGe epitaxy. Thin Solid Films 222, 78–84 (1992). 40. D.E. Jesson, S.J. Pennycook, J.-M. Baribeau, and D.C. Houghton. Direct imaging of surface cusp evolution during strained-layer epitaxy and implications for strain relaxation. Phys. Rev. Lett. 71, 1744–1747 (1993). 41. J.L. Gray, R. Hull and J.A. Floro. Control of surface morphology through variation of growth rate in SiGe/Si(1 0 0) epitaxial films: nucleation of quantum fortresses. Appl. Phys. Lett. 81, 2445–2447 (2002). 42. R. Hull, J.L. Gray, M. Kammler, S. Atha, P. Kumar, T. Vandervelde, J.C. Bean, J.A. Floro, and F.M. Ross. Precision placement of heteroepitaxial semiconductor quantum dots. Mater. Sci. Eng. B 101, 1–8 (2003). 43. T.E. Vandervelde, P. Kumar, T. Kobayashi, J.L. Gray, T. Pernell, J.A. Floro, R. Hull, and J.C. Bean. Growth of quantum fortress structures in Si1xGex/Si via combinatorial deposition. Appl. Phys. Lett. 83, 5205–5207 (2003). 44. J.L. Gray, N. Singh, D.M. Elzey, R. Hull, and J.A. Floro. Kinetic size selection mechanisms in intrinsic quantum dot molecules. Phys. Rev. Lett. 92, 135504:1–4 (2004). 45. X. Deng and M. Krishnamurthy. Self-assembly of quantum dot molecules: heterogeneous nucleation of SiGe islands on Si(1 0 0). Phys. Rev. Lett. 81, 1473–1476 ((1998). 46. J. Tersoff, C. Teichert, and M.G. Lagally. Self-organization in growth of quantum dot superlattices. Phys. Rev. Lett. 76, 1675–1678 (1996). 47. C. Teichert, M.G. Lagally, L.J. Peticolas, J.C. Bean, and J. Tersoff. Stress-induced self-organization of nanoscale structures in SiGe/Si multilayer films. Phys. Rev. B 53, 16334–16337 (1996). 48. J.L. Bischoff, C. Pirri, D. Dentel, L. Simon, D. Bolmont, and L. Kubler. AFM and RHEED study of Ge/Si(0 0 1) quantum dot modification by Si capping. Mater. Sci. Eng. B 69/70, 374–379 (2000). 49. P. Sutter and M.G. Lagally. Embedding of nanoscale 3D SiGe islands in a Si matrix. Phys. Rev. Lett. 81, 3471–3474 (1998). 50. A. Rastelli, E. Muller, and H. von Kanel. Shape preservation of Ge/Si(0 0 1) islands during Si capping. Appl. Phys. Lett. 80, 1438–1440 (2002).

© 2006 by Taylor & Francis Group, LLC

6.5-712

The Silicon Heterostructure Handbook

51. A.A. Shklyaev, M. Shibata, and M. Ichikawa. High-density ultrasmall epitaxial Ge islands on Si(1 1 1) surfaces with a SiO2 coverage. Phys. Rev. B 62, 1540–1543 (2000). 52. E.S. Kim, N. Usami, and Y. Shiraki. Selective epitaxial growth of dot structures on patterned Si substrates by gas source molecular beam epitaxy. Semicond. Sci. Technol. 14, 257–265 (1999). 53. L. Vescan. Lateral ordering of Ge islands along facets. J. Cryst. Growth 194, 173–177 (1998). 54. T.E. Kamins and S. Williams. Lithographic positioning of self-assembled Ge islands on Si(0 0 1). Appl. Phys. Lett. 71, 1201–1203 (1997). 55. G. Jin, J. Wan, Y.H. Luo, J.L. Liu, and K.L. Wang. Uniform and ordered self-assembled Ge dots on patterned Si substrates with selectively epitaxial growth technique. J. Cryst. Growth 227–228, 1100– 1105 (2001). 56. L. Vescan, T. Stoica, and B. Hollander. Lateral ordering of Ge islands on Si mesas made by selective epitaxial growth. Mater. Sci. Eng. B 89, 49–53 (2002). 57. I. Berbezier, A. Ronda, A. Portavoce, and N. Motta. Ge dots self-assembling: surfactant mediated growth of Ge on SiGe (1 1 8) stress-induced kinetic instabilities. Appl. Phys. Lett. 83, 4833–4835 (2003). 58. J.R. Tucker and T.-C Shen. Can single electronic integrated circuits and quantum computers be fabricated in silicon? Int. J. Circuit Theory Appl. 28, 553–562 (2000). 59. H. Omi, D.J. Bottomley, and T. Ogino. Strain distribution control on the silicon wafer scale for advanced nanostructure fabrication. Appl. Phys. Lett. 80, 1073–1075 (2003). 60. F.M. Ross. Growth processes and phase transformations studied by in situ transmission electron microscopy. IBM J. Res. Develop. 44, 489–501 (2000). 61. C. Teichert, C. Hofer, K. Lyutovich, M. Bauer, and E. Kasper. Interplay of dislocation network and island arrangement in SiGe films grown on Si(1 0 0). Thin Solid Films 380, 25–28 (2000). 62. H.J. Kim, Z.M. Zhao, and Y.H. Xie. Three-stage nucleation and growth of Ge self-assembled quantum dots grown on partially relaxed SiGe buffer layers. Phys. Rev. B 68, 205312:1–7 (2003). 63. A. Portavoce, M. Kammler, R. Hull, M.C. Reuter, M. Copel, and F.M. Ross. Growth kinetics of Ge islands during Ga surfactant-mediated UHV-CVD on Si(0 0 1). Phys. Rev. B 70, 195306: 1–9 (2004). 64. C.S. Lent, P.D. Tougaw, W. Porod, and G.H. Bernstein. Quantum cellular automata. Nanotechnology 4, 49–57 (1993). 65. C.S. Lent and P.D. Tougaw. A device architecture for computing with quantum dots. Proc. IEEE 85, 541–557 (1997). 66. I. Amlani, A.O. Orlov, G. Toth, G.H. Bernstein, C.S. Lent, and G.L. Snider. Digital logic gate using quantum-dot cellular automata. Science 284, 289–291 (1999). 67. S. Kanjanachuchai, J.M. Bonar, and H. Ahmed. Single-charge tunnelling in n- and p-type strained silicon germanium on silicon-on-insulator. Semicond. Sci. Technol. 14, 1065–1068 (1999). 68. L.J. Klein, K.A. Slinker, J.L. Truitt, S. Goswami, K.L.M. Lewis, S.N. Coppersmith, D.W. van der Weide, M. Friesen, R.H. Blick, D.E. Savage, M.G. Lagally, C. Tahan, R. Joynt, M.A. Eriksson, J.O. Chu, J.A. Ott, and P.M. Mooney. Coulomb blockade in a silicon/silicon–germanium twodimensional electron gas quantum dot. Appl. Phys. Lett. 84, 4047–4049 (2004). 69. C.L. Heng, Y.J. Liu, A.T.S Wee, and T.G. Finstad. The formation of Ge nanocrystals in a metal–insulator–semiconductor structure and its memory effect. J. Cryst. Growth 262, 95–1004 (2004). 70. D.-W. Kim, T. Kim, Y. Liu, L. Weltzer, and S. Banerjee. SiGe quantum dots memory devices with HfO2 tunneling oxide. Proceedings of the 61st Device Research Conference. Conference Digest. IEEE, Piscataway, NJ, USA, Cat. No. 03TH8663, 2003, pp. 131–132. 71. N. Deng, L. Pan, L. Zhang, and P. Chen. Ge quantum dot memory realized with vertical Si/SiGe resonant tunneling structure. Proceedings of the Fourth International Workshop on Junction Technology. IEEE, Piscataway, NJ, USA, Cat. No. 04EX762, 2004, pp. 256–258. 72. L. Chu, A. Zrenner, M. Bichler, and G. Abstreiter. Quantum-dot infrared photodetector with lateral carrier transport. Appl. Phys. Lett. 79, 2249–2251 (2001).

© 2006 by Taylor & Francis Group, LLC

Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy

6.5-713

73. S. Tong, J. Liu, J. Wan, R. Faez, V. Pouyet, and K.L. Wang. Normal-incidence near-1.55 mm Ge quantum dot photodetectors on Si substrate. SPIE Proc. 4580, 193–201 (2001). 74. B-C Hsu, S.T. Chang, T-C Chen, P-S Kuo, PS Chen, Z Pei, and C.W. Liu. A high efficient 820 nm MOS Ge quantum dot photodetector. IEEE Electron Dev. Lett. 24, 318–320 (2003). 75. N. Usami, A. Alguno, T. Ujihara, K. Fujiwara, G. Sazaki, K. Nakajima, K. Sawano, and Y. Shiraki. Stacked Ge islands for photovoltaic applications. Sci. Technol. Adv. Mater. 4, 367–370 (2003). 76. B.Yang, J.L. Liu, K.L. Wang, and G. Chen. Simultaneous measurements of Seebeck coefficient and thermal conductivity across superlattice. Appl. Phys. Lett. 80, 1758–1160 (2002).

© 2006 by Taylor & Francis Group, LLC

7 Optoelectronic Components 7.1

Overview: Optoelectronic Components J.D. Cressler............................................ 7.1-717

7.2 Si–SiGe LEDs K.L. Wang, S. Tong, and H.J. Kim..................................................... 7.2-719 Introduction . LED Design . Summary 7.3

Near-Infrared Detectors L. Colace, G. Masini, and G. Assanto ......................................................................... 7.3-731 Introduction . NIR Photodetectors . SiGe: A Material for NIR Detection . SiGe Detectors: Design and Fabrication . Summary

7.4

Si-Based Photonic Transistor Devices for Integrated Optoelectronics W.-X. Ni and A. Elfving .............................................................................................. 7.4-751 Introduction . Light Emitters . Photodetectors

7.5

Si–SiGe Quantum Cascade Emitters D.J. Paul....................................................... 7.5-763 Introduction . Population Inversion and Gain . Subband Lifetimes . Impurity Electroluminescence . Electroluminescence from Quantum Cascade Emitters . Si–SiGe Quantum Cascade Lasers . Summary

7.1-715 © 2006 by Taylor & Francis Group, LLC

7.1 Overview: Optoelectronic Components

John D. Cressler Georgia Institute of Technology

Given the natural ease with which monolithic integration can be realized in silicon, the merger of the photonics world and the electronics world would seem to offer compelling advantages, at least for the long-haul. Clearly, with respect to light emission and detection, Si (or SiGe) with its indirect bandgap is at a significant disadvantage with respect to their III–V counterparts. Nevertheless, significant progress has been made in Si-based light emitting diodes, as disucssed by K.L. Wang of UCLA in Chapter 7.2, ‘‘Si–Si LEDs.’’ For shorter wavelength applications, much has been accomplished in realm of light detectors, as discussed in Chapter 7.3, ‘‘Near-Infrared Detectors,’’ by L. Colace of the University of Rome, and Chapter 7.4, ‘‘Photonic Transistors for Integrated Optoelectronics,’’ by W. Li of Linko¨ping University. The quest for useful levels of light emission in Si is an old one, and while at first glance it might seem a laughable prospect, bandgap engineering facilitates a number of interesting possibilities that is fueling serious interest. In Chapter 7.5, for instance, ‘‘Si–SiGe Quantum Cascade Emitters,’’ by D. Paul of the University of Cambridge, the potential for light emission is the Si–SiGe system is addressed using quantum cascade techniques. In addition to this substantial collection of material, and the numerous references contained in each chapter, a number of review articles and books detailing the operation and modeling of various optoelectronic components exist, including Refs. [1–5].

References 1. R. People. Physics and applications of GexSi1 x/Si strained layer heterostructures. IEEE Journal of Quantum Electronics 22:1696–1710, 1986. 2. JC Bean. Silicon-based semiconductor heterostructures: column IV bandgap engineering. Proceedings of the IEEE 80:571–587, 1992. 3. RA Soref. Silicon-based optoelectronics. Proceedings of the IEEE 81:1687–1706, 1993. 4. CK Maiti and GA Armstrong. Applications of Silicon–Germanium Heterostructure Devices. London: Institute of Physics Publishing, 2001. 5. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. London: The Institution of Electrical Engineers, 2001.

7.1-717 © 2006 by Taylor & Francis Group, LLC

7.2 Si–SiGe LEDs

K.L. Wang, S. Tong, and H.J. Kim University of California at Los Angeles

7.2.1 7.2.2 7.2.3

Introduction............................................................... 7.2-719 LED Design ................................................................ 7.2-719 Summary .................................................................... 7.2-727

7.2.1 Introduction Light emitting diodes (LEDs) are one of the major components in realizing optoelectronic functions. However, it is well known that Si is an indirect bandgap material, and therefore, its luminescence efficiency is quite poor compared to III–V direct bandgap materials. Due to the nature of its indirect bandgap, the radiative recombination in Si at the band edge needs phonon assistance to maintain the momentum conservation. The transverse optical (TO) phonon-assisted peak dominates the emission spectrum. Due to the multiparticle nature of the recombination process, the radiative lifetime of the carriers is much longer compared to direct transition recombinations. Germanium bandgap is also indirect, but the direct valley at G point is only 0.15 eV higher than the indirect valley. Thus, excited electrons can enter both valleys, and recombination occurs via direct and indirect emission channels. Thus, it is possible to observe direct transitions from thin samples [1]. However, the output is weak due to reabsorption by the material, phonon scattering and low carrier density in direct valley. Nevertheless, people were persistently exploring possible solutions for efficient radiation in Si- and Ge-based materials on silicon substrate, such as porous silicon [2], Si or Ge quantum dots embedded in larger bandgap matrix, e.g., SiOx [3, 4] and a-Si:H [5]. The incorporation of rare-earth atoms into silicon has also been studied. Erbium-based emitters take advantage of the intra-4f shell transitions at 1.54 mm [6]. Room temperature electroluminescence (EL) of erbium-doped silicon LEDs has been reported [7]. Ge and SiGe can be epitaxially grown on a Si wafer with higher quality and fewer problems than III–V materials, since Ge and Si all belong to group IV. SiGe structures are fabricated by MBE or LPCVD techniques to maintain their lattice structure integrity, though defects such as misfit dislocations and point defects always appear in a certain degree. These materials include SinGem strained layer superlattices (SLSs), Si1xGex quantum wells, and Si1xGex quantum dots [8–12].

7.2.2 LED Design The idea of Brillouin-zone folding was first proposed by Gnutzmann and Clausecker [13]. A two-material superlattice with a period of several monolayers can fold the X valley back to the G point. For Si, the conduction band minima is at 0.85(p/a). By growing SinGem SLS, the conduction band minima can be folded to the G point due to the artificially increased lattice constant in the growth direction, so that an enhancement of luminance is expected due to the direct transition in the SLS. Zone-folding ideas have been studied theoretically [13, 14] and experimentally [15–19]. Low temperature and room temperature [19] EL and photoluminescence (PL) have been observed from Si–Ge superlattice structures. With the 7.2-719 © 2006 by Taylor & Francis Group, LLC

7.2-720

The Silicon Heterostructure Handbook

study of absorption threshold behavior [20], transition mechanisms of the EL have been explored. It was shown that bandgap-related transitions as well as defect-related transition might contribute to the EL spectra. However, the transition matrix element calculation shows that the oscillator strength of the direct transition is still at least one order of magnitude lower than in direct III–V semiconductors [21]. Other approaches include realizing quantum structures inspired by the quantum confinement effect. Since the bandgap of Si (1.15 eV) is larger than that of Ge (0.67 eV), it is possible to form wells for carriers in SiGe heterostructures. The ideal situation is to have a type-I (as shown in Figure 7.2.1(a)) band alignment between the two materials, i.e., both electrons and holes are confined in Ge wells. However, in reality, the band alignment between Si and Ge is typically type-II (as shown in Figure 7.2.1(b)), that is, holes are confined in Ge and electrons in Si. Nevertheless, researchers were able to achieve light radiation in such structures up to room temperature. In quantum dots, due to strong carrier localization within a space of less than 10 nm, the momentum is a poorly defined physical quantity and does not have to be conserved, resulting in enhanced no-phonon luminescence. In this section, we present the experimental results of PL and EL in this field. The results from SinGem SLSs Si1xGex quantum wells, and Ge QDs will be presented separately. Studies show that if SLS is grown on a Si substrate, due to the strain effect on the band structure, the inplane four-fold conduction band minima, instead of the two zone-folding conduction band minima, are lowest in energy. So the superlattice needs to be grown on a SiGe substrate. Figure 7.2.2 shows the calculation results of Si5Ge5 grown on the Si structure and Si0.5Ge0.5 alloy buffer layer, respectively, using the effective mass approximation. The upper graph shows that the lowest interband transition for the SLS on Si substrate is an indirect transition between the nonfolded conduction band minima to the heavy hole states. And the lower graph shows direct transitions with both the conduction band minimum and valance band maximum in the SLS region. One way to obtain the SiGe substrate is to grow a SiGecompleted relaxed buffer layer with the strain of Si and Ge in the superlattice canceling each other [15, 22]. The major problem of the fully relaxed buffer layers is the large number of misfit dislocations generated during strain relief [17]. One way to minimize the defect density in the buffer layer so as to improve the superlattice film quality is to grow a thick buffer layer aswell as a partially strained buffer layer [23]. It is also known that higher growth temperature is good for defect-free films. One monolayer (ML) of Sb is used to reduce the intermixing of Si and Ge at interface under high growth temperature [24]. Figure 7.2.3 shows the EL and PL spectra for 250 nm Si5Ge5 grown on 1 mm thick Si0.5Ge0.5 buffer layer. The samples were grown as p–i–n structure and processed with standard silicon technology for waveguide LED structures. The EL was measured at an injected electrical power of 25 mW at 5 K. The

FIGURE 7.2.1 (a) Type-I band alignment, where holes and electrons are confined spatially in the same location. (b) Type-II band alignment, where holes and electrons are spatially separated. © 2006 by Taylor & Francis Group, LLC

7.2-721

Si–SiGe LEDs

Si5Ge5 on Si

Energy (eV)

2.0 1.5

∆(2)

15 meV

∆(6)

1.0

∆(4)

Indirect

hh

0.5 0.0

Ih

Ih,hh 430 meV

−0.5 2.0

Si5Ge5 on Si0.5Ge0.5

Energy (eV)

1.5 ∆(4)

∆(6) 1.0

∆(2)

36 meV

Direct

0.5 0.0

Ih

Ih,hh

hh

70 meV

−0.5

(a)

Si5Ge5

Luminescence intensity (arb. units)

PL

Si0.5Ge0.5 (1µm)

EL

n

+

n+

i

n+

Photoluminescence T=5 K

Si5Ge5

Absorbance T =150 K

0.7

0.8

0.9

1.0

1.1

Energy (eV)

0.7

(b)

0.8

0.9

1.0

1.1

Energy (eV)

FIGURE 7.2.2 (a) Bandgap and band aligments for Si5Ge5 superlattices grown pseudomorphically on a silicon substrate and on a fully relaxed Si0.5Ge0.5 alloy buffer layer. (b) Comparison between EL and PL for a Si5Ge5 superlattice grown on a 1-mm thick fully relaxed Si0.5Ge0.5 alloy buffer layer. The inset shows the comparison between absorption and photoluminescence spectra. The absorption spectrum is plotted on a logarithmic scale. (After U Menczigar, G Abstreiter, J Olajos, H Grimmeiss, H Kibbel, H Presting, and E Kasper. Phys Rev B 47:4099– 4102, 1993. With permission.)

© 2006 by Taylor & Francis Group, LLC

7.2-722

The Silicon Heterostructure Handbook

Light

p+ Si Si 4000 Å Oxide

Si 320 Å Si/SiGe MQW 10 periods SiGe 60Å Si 320Å Si 4000Å n+ Si

2 µm

n-type Si substrate

(a)

Luminescence intensity

80 K EL (c) 77 K PL NP

(b) TO

4K PL (a)

800

850

900

950

1000

Photon energy (meV)

(b)

EL intensity (arb. units)

T = 300 K I = 15 mA SiGeNP

SiTO

800

(c)

900

1000

1100

1200

Photon energy (meV)

FIGURE 7.2.3 (a) Device schematic. The active regions consists of ten layers of Si (320 A)/Si0.65Ge0.35(60 A). (b) Photoluminescence spectra at (a) 4.2 K and (b) 77 K, and (c) electroluminescence spectrum with 10 mA drive current and heat sink temperature at 80 K. (c) Electroluminescence spectra with room temperature heat sink with 15 mA drive current. (After Q Mi, X Xiao, JC Sturm, LC Lenchyshyn, and MLW Thewalt. Appl Phys Lett 60:3177–3129, 1992. With permission.)

© 2006 by Taylor & Francis Group, LLC

Si–SiGe LEDs

7.2-723

light emission is attributed to the intrinsic superlattice region because of the same energy peak for the PL and EL. The absorption spectrum measurements show that the resonance energy is in agreement with PL result of 0.76 eV. Thus the PL and EL spectra of the strained Si5Ge5 superlattice are likely due to bandgap-related transitions [21]. Another structure for light emission is SiGe quantum wells. Characteristic features of such luminescence are the phonon replicas found in indirect bandgap semiconductors plus a signal near the bandgap due to direct exciton recombination without any phonons involved [25]. At T < 20 K the PL is dominated by shallow bound excitons (BE), while at T > 20 K it is dominated by free excitons (FE). No-phonon (NP) emission from FE is the result of alloy effects and was first observed in bulk unstrained alloys [26]. PL and EL of pseudomorphic Si/Si1xGex multiple quantum wells (MQW) and single quantum wells (SQW) grown by molecular beam epitaxy (MBE) at 4008C were first reported by Noel et al. PL signal with a line width of about 100 meV was observed after thermal annealing at temperatures above 5508C. The PL peaks, however, were observed about 100 meV below the expected bandgap [27]. Band edge PL due to exciton recombination was first obtained from strained Si0.958Ge0.042 by Terashima et al. [28]. EL at 1.2 mm from a pseudomorphic Si0.8Ge0.2 alloy grown by CVD at 6108C was demonstrated by Robbins et al. at 77 K [29]. EL (1.3 mm) from strained Si0.65Ge0.35 was obtained at room temperature with the internal quantum efficiency having a lower limit of 2 104 [25]. Then EL was observed at temperature up to 608C in p-type strained Si0.65Ge0.35Si MQW grown on Si(1 1 1) substrates by Fukatsu et al. The no-phonon (NP) line and its TO phonon replica were well resolved in the room temperature EL spectrum at growth temperature of 8008C. These experimental results also show that for a structure grown at a temperature lower than 5008C, the defect-related line dominates the luminescence spectra, while for high-temperature grown sample, bandgap-related PL signals can be observed [21]. As shown in Figure 7.2.3(a), the sample consisted of ten layers of Si0.65Ge0.35 quantum wells placed inside the intrinsic region of a p–i–n diode. Figure 7.2.3(b) shows the PL results at 4 K and 77 K. The peaks near 896 and 842 meV in the 4.2 K spectrum were identified as the NP and the TO replica, respectively. The 77 K spectrum has a clear NP peak at 924 meV. The EL spectrum (I ¼ 10 mA, 400 Hz modulation, 50% duty cycle) at a heat sink temperature of 80 K is also shown. Based on the similarity of the EL and PL spectra, we conclude that the physical mechanisms responsible for recombination are transitions of electrons directly from conduction band to valence band, not involving deep levels. It is also important to note that the peak emitted from the NP line is at 1.34 mm. Figure 7.2.3(c) shows room temperature EL, which is insensitive to temperature from 77 K to room temperature. Although some emissions due to the TO replica from recombination in the Si layer are observed, well over 70% of the emitted spectrum is from the Si0.65Ge0.35. Internal quantum efficiency was estimated to have a lower limit of 2 104 at room temperature [25]. We now discuss the fabrication and measured results of LEDs based on Ge quantum dots. Ge QDs can be grown on Si substrates using both solid source and gas source MBE as well as LPCVD. The dots are formed via the Stranski–Krastanov mode, beginning with layer-by-layer growth followed by island formation. The key driving force of the dot formation is the 4.16% lattice mismatch between Si and Ge. At the beginning of the growth of Ge on Si, misfit strain is built up but is fully accommodated. Once the Ge film thickness exceeds its critical thickness of a few (three to four) monolayers, the strain starts to relax by forming three-dimensional pyramidal islands, and the surface of the layer becomes rougher. Those small islands may evolve into large domes upon subsequent Ge deposition. When the Ge thickness exceeds 20 A˚ or so, misfit dislocations form to relax the additional strain arising from the accumulation of the film thickness [30]. The areal dot density is typically on the order of 108 to 1010 cm2. Some groups reported dots density as high as 1011 cm1 by carbon deposition prior to Ge growth [31, 32]. Usually dots have variable shapes, i.e., pyramid, dome, and superdome. The dots’ height ranges from 3 to 10 nm, and the dot base ranges from 25 to 100 nm. With increasing growth temperature, there is significant interdiffusion between the grown Si and Ge. Thus, the dots are not pure Ge and the content inside the dot is not uniform. Investigations indicate that the dots have a Ge-rich core with less Ge content in the outer side [33]. The island formation results in partial relaxation, thus there is some residual strain inside the dot. The bottom of the dot is compressively strained while the top is more

© 2006 by Taylor & Francis Group, LLC

7.2-724

The Silicon Heterostructure Handbook

relaxed. These dot properties can be controlled by modifying the growth conditions, including substrate temperature, growth rate, and doping. After the formation of Ge dots, there are three monolayers of Ge remaining on the Si surface in addition to the dot locations, which is called the wetting layer. Multilayers of Ge dots are often grown to enhance the optical properties, which can be achieved by repeatedly growing a layer of Ge dot covered by a Si spacer layer. It is well known that the subsequent Ge quantum dot is preferentially nucleated on top of the underlying one when the Si space layer is thin [34, 35]. Electroluminescence studies were carried on p–i–n or p–n LED structures; the substrates can be either p-type or n-type. The Ge dots are grown on the intrinsic or lightly doped region. Holes and electrons are injected from the p- and n-type contact Si layers, and recombination occurs in the center region. Since holes can be confined in Ge dots very easily due to their large effective mass and the large valence band offset, at low temperatures, the luminescence from Ge dots is significant. The transition is similar to the PL transition. That is, holes from the dots and electrons from the surrounding Si layers are within the electron de Broglie wavelength. This is also due to the type-II band alignment between the two materials obtained by these growth methods. Electrons cannot stay in Ge dots since within them the energy is higher than in Si. Photoluminescence can be used to determine the transition energy within such Ge dot materials. With a high-energy excitation, the photogenerated carriers relax to their ground states and recombine. Figure 7.2.4 shows the low-temperature PL spectrum at 4.5 K for a typical dot sample, which consists of ten-period Ge dot (1.6 nm)/Si (50 nm) superlattices [36]. The broad PL peak located around 0.83 eV was attributed to the PL from the island and can be decomposed into two Gaussian line-shaped peaks at 824 and 866 meV, respectively. They were attributed to the NP transition and TO replica of the Ge islands. The two peaks located at 1007 and 949 meV are attributed to the NPWL transition and its TOWL phononassisted transitions of upper pseudomorphic wetting layers. The inset shows the possible mechanism for the NP peak arising from the Ge quantum dots. The Ge–Si quantum dot system has been shown to have

PL intensity (a.u.)

40 400 mW 200 mW 120 mW 70 mW 35 mW 10 mW 20

Si

TOQD NPQD

TOWL

NPWL NPWL1 Si

Si

TOWL1

Si

0

0.7

0.8

0.9

1.0

1.1

1.2

Energy (eV) FIGURE 7.2.4 PL spectra of Ge–Si (0 0 1) islands under different excitation power levels measured at 4.5 K. In addition to the PL peaks from Si, there are two separate components, which come from the islands and the wetting layer, respectively. The TO and NP PL lines originating from the first wetting layer and the upper wetting layer are indicated by TOWL1, NPWL1, TOWL, and NPWL, respectively. The PL band from the islands can be deconvoluted into two Gaussian line-shaped peaks that are indicated by TOID and NPID, respectively. (After XZ Liao, J Zou, DJH Cockayne, J Wan, ZM Jiang, G Jin, and KL Wang. Phys Rev B 65:153306–153309, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

Si–SiGe LEDs

7.2-725

a type-II band alignment. The radiative recombination occurs between electrons in the Si layers and holes confined in the Ge dots, giving rise to the Ge quantum dot peak in the PL spectrum. The TO phonon-assisted peak is about 50 meV lower in energy. The enhanced no-phonon transition is mainly a consequence of relaxed momentum conservation due to alloy-induced disorder. In addition to the Ge peaks, peaks at 1.153, 1.095, 1.061, and 1.027 eV originate from Si and correspond to nonphonon (NP) replica, transverse acoustic (TA), TO, 2TAþTO, and TOþOG peaks, respectively. For the Ge dots grown in high density with carbon predeposition, the dot size can be reduced to 10 nm in diameter and approximately 2 nm in height [31]. Due to the much smaller dot height, there is a blueshift of PL spectrum compared to the large Ge islands. It is assumed that for this kind of dot, electrons are confined in the underlying carbon-rich layer, while the heavy holes are in the Ge-rich upper part of the Ge islands. This band alignment is obtained from the well-known situation in neighboring Si1xGex/Si1yCy quantum wells, so the recombination is spatially indirect between the two regions. However, a temperature-dependence study showed that the thermal activation energy is only 30 meV, due to much stronger confinement in the small size dot. The luminescence was quenched at 50 K. This will hinder the application of LEDs with this kind of dot at room temperature. For fully strained Ge on Si, there is a maximum band offset of 700 meV in the valence band. From PL measurement, however, we can only obtain Ge dots with energy 400 meV below the Si bandgap. This is believed to be mainly due to Si alloying into the islands and quantum confinement effect. In addition, the Ge island is not fully strained, so part of the strain is also transferred into the surrounding Si matrix, further reducing the valence band offset. The EL peak corresponds to the energy difference between the Si conduction band edge and the ground state in the Ge dots. At low injection, recombination from those high excited states of holes in the Ge dots is unlikely since the relaxation of holes is very fast. Since heavy holes have a large effective mass, and the dot lateral dimension is usually big, in the order of 50 to 100 nm, the quantized energy-level separations in Ge dots are very small, only several meV. This is much smaller than the optical phonon in Ge, which is 34 meV. Thus, holes can efficiently relax to ground or low excited states via optical and acoustic phonons. EL spectra are usually broader than kT (k is the Boltzmann constant), which is ascribed to the nonuniformity of the dot size as well as their Ge content. Chretien et al. [37] studied the spectrum dependence upon injection current density. It was discovered that with increasing the current density from 60 to 6000 A/cm2, there is significant blueshift of the peak. This shift is due to a band-filling effect. They also grew Ge dots on different sizes Si mesas. At low injection current density (60 A/cm2), the Ge dot peak experiences a blueshift with increasing the mesa size (lateral size from 5 to 500 mm). Generally speaking, in the recombination process, energy and momentum conservation should both be observed. But for Ge dots, the height is usually in the range of 6 to 10 nm, so the holes are strongly confined in the growth direction. This strong confinement will relax the requirement of the momentum conservation. It is also suggested that the alloy effect of Si and Ge will loosen this conservation requirement. These effects improve the luminescence efficiency of Ge dots. The integrated intensity from dots is much higher than that from Si at low temperatures. However, the efficiency is still orders of magnitude lower than that of III–V materials. Chang et al. [12] measured the external quantum efficiency at room temperature, 4.6 106 was obtained at injection current density of 65 A/cm2, and the estimated internal efficiency was 1.5 104. This low efficiency is mainly due to the long radiative lifetime and poor carrier confinement as well as the presence of nonradiative centers such as defects in the active region. EL spectra from Ge dot samples change with measurement temperature. Shown in Figure 7.2.5 are the EL spectra at different temperatures [11]. Typically, at low temperature, the luminescence from Ge is weak while that from Si is strong. With increasing temperature, the Ge peak increases and the Si peak quenches. The EL is relatively constant up to 225 K and then starts to decrease after this temperature. This is because that the confined holes can be thermally excited out of the Ge dot wells at high temperature. Through measured EL quenching characteristics, an activation energy of 230 meV was estimated, which corresponds to the effective barrier height for holes in Ge dots. The decrease of

© 2006 by Taylor & Francis Group, LLC

7.2-726

The Silicon Heterostructure Handbook

11 K

Electroluminescence (a.u.)

20 K 30 K 45 K 80 K 140 K 200 K 225 K 250 K 33 290 K 3 20

0.6

0.8

1

1.2

Energy (eV) FIGURE 7.2.5 Temperature dependence of the electroluminescence of five layers of Ge QDs separated by 35-nm thick Si barrier layers. The sample was prepared by a lamp-heated single wafer chemical vapor deposition reactor. The dot density is around 1.7 1010 cm2. The quantum dots of a single Ge layer grown in the same conditions have a typical base size of 50 nm and a height of 4 nm. (After T Brunhes, P Boucaud, S Sauvage, F Aniel, JM Lourtioz, C Hernandez, Y Campidelli, O Kermarrec, D Bensahel, G Faini, and I Sagnes. Appl Phys Lett 77:1822–1824, 2000. With permission.)

luminescence efficiency at room temperature limits the application of such LEDs. However, there is a report claiming that the integrated intensity of Ge peak remains the same at room temperature [12]. They attributed the enhanced efficiency to the low nonradiative recombination center density that is caused by the surface passivation and thermal treatment in the processing. The current-dependent EL intensity (L J m) reveals the competition of radiative and nonradiative processes in the active region. Figure 7.2.6 shows the dependence of integrated EL intensity (I) on current density (j) [8]. A linear dependence was shown at low temperatures and low injection, indicating that most of the injected carriers are radiatively recombined. At higher injection current density (>20 A/ cm2), m ¼ 0.67, which implies Auger processes (m ¼ 2/3). At room temperature, m ¼ 1.3 and 1 for low (<20 A/cm2) and high (>20 A/cm2) injection, respectively. The superlinear dependence indicates that a Shockley–Read–Hall (SHR) process is important due to the increased capture probability of nonradiative centers. The linear dependence at high injection suggests that the nonradiative traps are saturated. Talalaev et al. [38] studied this L J m dependence and found that m to be 4.8 and 3.1 for 1 and 2 A/cm2 current densities, respectively. The variation of m was interpreted as a band-bending change, the redistribution of the electrons within the near-contact region and progressive filling of the electron miniband with an increase of the forward bias. A comparison of the PL and EL intensities of the QD-related peak demonstrates a higher efficiency for an electrical excitation. One group also tried to confine electrons near the Ge dots by decreasing the thickness of Si spacer layer to 13 nm [10]. This is to produce a combination of self-assembled Ge dots with tensile-strained Si close to the center of dots, which should have provided electron localization and the overlap of electron

© 2006 by Taylor & Francis Group, LLC

7.2-727

Integrated EL intensity (a.u.)

Si–SiGe LEDs

104

T = 80 K

103

Sample 730 (Si0.7Ge0.3 dots)

102

m~1

0.1

m = 1.1

m = 0.66

m = 2.2

1

Current density

Sample 696 (Si0.80Ge0.20 layer)

10

(A/cm2)

FIGURE 7.2.6 Dependence of integrated EL intensity I on current density j for Ge QDs (sample 730) at 80 K. Result of Si0.8Ge0.2 (sample 696) is also shown. (After R Apetz, L Vescan, A Hartmann, C Dieker, and H Luth. Appl Phys Lett 66:445–447, 1995. With permission.)

and hole wave functions. With this modification, a significantly enhanced Ge dot-related PL signal up to room temperature at 1.55 mm wavelength was obtained.

7.2.3 Summary Despite great efforts contributing to the development of SiGe-based LEDs, there are still two major problems remaining. The first one is the low efficiency. As we have seen, the external quantum efficiency is in the order of 104 to 106. This is mainly due to the long lifetime of radiative recombination process in the material. Although it is improved with the aforementioned methods, the low efficiency still remains the biggest obstacle for such LED devices. The other problem is the luminescence quenching at room temperature. For most of the studies to date, the EL intensity drops at higher temperatures (e.g., >250 K). Relatively shallow carrier confinement is insufficient for devices operating at room temperature. In the future, for achieving high-performance LED based on SiGe materials, carrier confinement has to be improved. This may be achieved by a different design of the structure. The formation of very small (1 to 2 nm in size) dots is also a possible approach because the confinement can be drastically enhanced, thus increasing the recombination rate [39]. In device processing, roughing the surface to increase the coupling-out of the emission from inside of the active region to the outer surface may also be important, since Si and Ge have large refractive indexes, so the angle for the light to emit from the device is small (178 for Si). By roughing the surface, photons have more chances to escape from the body. Since the emission spectra are very broad from Ge dots, it may also help to apply a Febry–Perrot resonant cavity to select the wavelength of interest, thus prohibiting those unwanted emissions. This should increase the efficiency at selected wavelengths.

References 1. JI Pankove. Optical Processes in Semiconductors, Chapter 6. Englewood Cliffs, NJ, Prentice-Hall, 1971. 2. LT Canham. Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers. Appl Phys Lett 57:1046–1050, 1990. 3. DJ DiMaria, JR Kirtley, EJ Pakulis, DW Dong, TS Kuan, FL Pesavento, TN Theis, JA Cutro, and SD Brorson. Electroluminescence studies in silicon dioxide films containing tiny silicon islands. J Appl Phys 56:401–416, 1984.

© 2006 by Taylor & Francis Group, LLC

7.2-728

The Silicon Heterostructure Handbook

4. AJ Kenyon, PF Trwoga, CW Pitt, and G Rehm. The origin of photoluminescence from thin films of silicon-rich silica. J Appl Phys 79:9291–9300, 1996. 5. S Tong, XN Liu, and XM Bao. Study of photoluminescence in nanocrystalline silicon/amorphous silicon multilayers. Appl Phys Lett 66:469–471, 1995. 6. H Ennen, J Schneider, G Pomrenke, and A Axmann. 1.54-mm luminescence of erbium-implanted III–V semiconductors and silicon. Appl Phys Lett 43:943–945, 1983. 7. G Franzo, F Priolo, S Coffa, A Polman, and A Carnera. Room-temperature electroluminescence from Er-doped crystalline Si. Appl Phys Lett 64:2235–2237, 1994. 8. R Apetz, L Vescan, A Hartmann, C Dieker, and H Luth. Photoluminescence and electroluminescence of SiGe dots fabricated by island growth. Appl Phys Lett 66:445–447, 1995. 9. L Vescan, T Stoica, O Chretien, M Goryll, E Mateeva, and A Muck. Size distribution and electroluminescence of self-assembled Ge dots. J Phys Lett 87:7275–7282, 2000. 10. K Eberl, OG Schmidt, O Kienzle, and F Ernst. Preparation and optical properties of Ge can C-induced Ge quantum dots on Si. Thin Solid Films 373:164–169, 2000. 11. T Brunhes, P Boucaud, S Sauvage, F Aniel, JM Lourtioz, C Hernandez, Y Campidelli, O Kermarrec, D Bensahel, G Faini, and I Sagnes. Electroluminescence of Ge/Si self-assembled quantum dots grown by chemical vapor deposition. Appl Phys Lett 77:1822–1824, 2000. 12. WH Chang, AT Chou, WY Chen, HS Chang, TM Hsu, Z Pei, PS Chen, SW Lee, LS Lai, SC Lu, and MJ Tsai. Room-temperature electroluminescence at 1.3 and 1.5 mm from Ge/Si self-assembled quantum dots. Appl Phys Lett 83:2958–2960, 2003. 13. U Gnutzmann and K Clausecker. Theory of direct optical transitions in an optical indirect semiconductor with a superlattice structure. Appl Phys 3:9–14, 1974. 14. RJ Turton, M. Jaros, and I Morrison. Electronic band structure and nonparabolicity in strained-layer Si–Si1xGex superlattices. Phys Rev B 38:8397–8405, 1988. 15. SJ Chang, CF Huang, MA Kallel, KL Wang, RC Bowman Jr, and PM Adama. Growth and characterization of Ge/Si strained-layer superlattices. Appl Phys Lett 53:1835–1837, 1988. 16. T Pearsall, JM Vandenberg, R. Hull, and JM Bonar. Structure and optical properties of strained Ge– Si superlattices grown on (0 0 1) Ge. Phys Rev Lett 63:2104–2107, 1987. 17. R Zachai, K Eberl, G Abstreiter, E Kasper, and H Kibbel. Photoluminescence in short-period Si/Ge strained-layer superlattices. Phys Rev Lett 64:1055–1058, 1990. 18. MA Kallel, VA Engels, KL Wang, and RPG Karunasiri. MBE SimGen strained monelayer superlattices. J Cryst Growth 111:897–901, 1991. 19. J Engvall, J Olajos, HG Grimmeiss, H Presting, H Kibbel, and E Kasper. Electroluminescence at room temperature of a SinGem strained-layer superlattice. Appl Phys Lett 63:491–493, 1993. 20. J Olajos, J Engvall, HG Grimmeiss, H Presting, H Kibbel, and E Kasper. Band-to-band transitions in strain-symmetrized, short-period Si/Ge superlattices. Thin Solid Films 222:243–245, 1992. 21. U Menczigar, J Brunner, E Friess, M Gail, G Abstreiter, H Kibbel, H Presting, and E Kasper. Photoluminescence studies of Si/Si1xGex quantum wells and SimGen superlattices. Thin Solid Films 222:227–233, 1992. 22. E Kasper, H Kibbel, H Jorke, H Brugger, E Friess, and F Abstreiter. Symmetrically strained Si/Ge superlattices on Si substrates. Phys Rev B 38:3599–3601, 1988. 23. U Menczigar, G Abstreiter, J Olajos, H Grimmeiss, H Kibbel, H Presting, and E Kasper. Enhanced bandgap luminescence in strain-symmetrized (Si)m/(Ge)n superlattices. Phys Rev B 47:4099–4102, 1993. 24. J Olajos, J Engvalt, HG Grimmeiss, U Menczigar, M Gail, G Abstreiter, H Kibbel, E Kasper, and H Presting. Photo- and electroluminescence in short-period Si/Ge superlattice structures. Semicond Sci Technol 9:2011–2016, 1994. 25. Q Mi, X Xiao, JC Sturm, LC Lenchyshyn, and MLW Thewalt. Room-temperature 1.3 mm electroluminescence from strained Si1xGex/Si quantum wells. Appl Phys Lett 60: 3177–3129, 1992. 26. J Weber and MI Alonso. Near-band-gap photoluminescence of Si–Ge alloys. Phys Rev B 40:5683– 5693, 1989.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe LEDs

7.2-729

27. JP Noel, NL Rowell, DC Houghton, and DD Perovic. Intense photoluminescence between 1.3 and 1.8 mm from strained Si1xGex alloys. Appl Phys Lett 57:1037–1039, 1990. 28. K Terashima, M Tajima, and T Tatsumi. Near-band-gap photoluminescence of Si1xGex alloys grown on Si (1 0 0) by molecular beam epitaxy. Appl Phys Lett 57:1925–1927, 1990. 29. DJ Robbins, P Calcott, and WY Leong. Electroluminescence from a pseudomorphic Si0.8Ge0.2 alloy. Appl Phys Lett 59:1350–1352, 1991. 30. DJ Eaglesham and M Cerullo. Dislocation-free Stranski–Krastanow growth of Ge on Si (1 0 0). Phys Rev Lett 64:1943–1946, 1990. 31. OG Schmidt, C Lange, K Eberl, O Kienzle, and F Ernst. Formation of carbon-induced germanium dots. Appl Phys Lett 71:2340–2342, 1997. 32. AI Yakimov, AV Dvurechenskii, YY Proskuryakov, AI Nikiforov, OP Pchelyakov, SA Teys, and AK Gutakovskii. Normal-incidence infrared photoconductivity in Si p–i–n diode with embedded Ge self-assembled quantum dots. Appl Phys Lett 75:1413–1415, 1999. 33. XZ Liao, J Zou, DJH Cockayne, J Wan, ZM Jiang, G Jin, and KL Wang. Alloying, elemental enrichment, and interdiffusion during the growth of Ge(Si)/Si (0 0 1) quantum dots. Phys Rev B 65:153306–153309, 2002. 34. GS Solomon, JA Trezza, AF Marshall, and JS Harris Jr. Vertically aligned and electronically coupled growth induced InAs islands in GaAs. Phys Rev Lett 76:952–955, 1996. 35. Y Sugiyama, Y Nakata, K Imamura, S Muto, and N Yokoyama. InAs self-assembled quantum dots on (0 0 1) GaAs grown by molecular beam epitaxy. Jpn J Appl Phys 35:1320–1324, 1996. 36. J Wan, GL Jin, ZM Jiang, YH Luo, JL Liu, and KL Wang. Band alignments and photon-induced carrier transfer from wetting layers to Ge islands grown on Si (0 0 1). Appl Phys Lett 78:1763–1765, 2001. 37. O Chretien, T Stoica, D Dentel, E Mateeva, and L Vescan. Influence of the mesa size on Ge island electroluminescence properties. Semicond Sci Technol 15:920–925, 2000. 38. VG Talalaev, GE Cirlin1, AA Tonkikh, ND Zakharov, and P Werner. Room temperature electroluminescence from Ge/Si quantum dots superlattice close to 1.6 mm. Phys Stat Sol (a) 198:R4–R6, 2003. 39. MS Hybertsen. Absorption and emission of light in nanoscale silicon structures. Phys Rev Lett 72:1514–1517, 1994.

© 2006 by Taylor & Francis Group, LLC

7.3 Near-Infrared Detectors

Lorenzo Colace, Gianlorenzo Masini, and Gaetano Assanto University ‘‘Roma Tre’’

7.3.1 7.3.2 7.3.3 7.3.4

Introduction............................................................... 7.3-731 NIR Photodetectors................................................... 7.3-732 SiGe: A Material for NIR Detection ........................ 7.3-733 SiGe Detectors: Design and Fabrication ................. 7.3-738 Waveguide Photodetectors (WPD) . Normal Incidence Photodetectors . Toward Monolithic Integration

7.3.5

Summary .................................................................... 7.3-745

7.3.1 Introduction The term ‘‘near-infrared’’ or NIR is most commonly used with reference to a wavelength spectral range between 0.7 and 2.0 mm. This portion of infrared is of paramount importance in several applications, first among them are the optical communications with transmission windows located at 0.85, 1.3, and 1.55 mm, corresponding to GaAs-based laser emission and to two minima in attenuation for standard silica fibers, respectively. Moreover, wavelength division multiplexing for high-capacity links encourages to using the whole interval between 1.3 and 1.6 mm (S, C, and L bands). Due to the growing demand for wideband internet and massive data transmission, applications have shifted from long-haul pointto-point connections to local networks down to subscribers, softening the specifications and opening entirely new markets [1]. In addition to communications, NIR spectroscopy is employed in remote sensing of the environment, monitoring of industrial processes, biology, and medicine. For example, water has absorption lines that allow to detect its content in the flora for fire prevention [2], various gas species exhibit NIR absorption bands useful for emission or toxicity analysis [3]. In addition, NIR spectroscopy has been exploited for DNA sequencing [4], brain activity mapping [5], and cancer detection [6]. However, since optical fiber communications remain the main field driving research in NIR detectors, this chapter will focus on NIR detectors on silicon from the receiver standpoint. Among semiconductor materials, SiGe alloys have allowed to fabricate novel, high performance electronic devices such as heterojunction bipolar and field-effect transistors [7], opening new perspectives also in NIR optoelectronics by exploiting the bandgap of germanium (0.66 eV), much lower than that of silicon (1.12 eV), which is otherwise useless for detection at these wavelengths. Numerous NIR devices have been proposed, from emitters to waveguides, couplers, modulators, and detectors [8]. The centrosymmetry and the indirect nature of Si, Ge, and SiGe pose important limitations to SiGe devices as compared to III–Vs; nevertheless, exploiting a few structurally related modifications such as quantum confinement, acceptable performances have been foreseen, with the significant advantage of the compatibility with the unsurpassed silicon VLSI technology. The key to the success of SiGe-based optoelectronics is the ability to conveniently compromise between material performance and monolithic integration. The fabrication of embedded optoelectronics and electronics in the same process does 7.3-731 © 2006 by Taylor & Francis Group, LLC

7.3-732

The Silicon Heterostructure Handbook

considerably reduce alignment and interconnection problems, offering improved reliability, yield, compactness, and reduced parasitics. Conversely, monolithic integration with SiGe requires heteroepitaxy, which is known to be critical for lattice-mismatched materials such as Si and Ge, with mismatch of about 4%. In the specific case of photodetectors, material quality requirements are less stringent than in other devices, thus encouraging toward the realization of innovative and competitive devices. This chapter is organized as follows. After a short introduction on photodetector operation and figures of merit in Section 7.3.2, Section 7.3.3 deals with the SiGe technology for photodiodes, focusing on the quality of both strained and relaxed epilayers, their optical and electrical characteristics and their bearing in device performances. Design strategies and fabrication are discussed in Section 7.3.4 along with an overview of the most relevant approaches that were proven successful to date.

7.3.2 NIR Photodetectors Near-infrared light detection in semiconductors is obtained by the creation of electron–hole pairs through the absorption of photons with energy greater than the bandgap. Germanium, with its gap of 0.66 eV, allows to reveal wavelengths as large as 1.88 mm. A photocurrent is generated when a built-in or applied electric field sweeps the carriers toward a couple of contacts (anode and cathode). Photodetectors can be subdivided into three categories: photomultipliers, photoconductors, and photodiodes, the latter being p–n or p–i–n junctions, avalanche and metal–semiconductor–metal (MSM) diodes. The pin photodiode is by far the most commonly used in optical receivers and we will focus on it, keeping in mind that a large portion of the following can be extrapolated to other devices. The pin photodiode consists of an intrinsic semiconductor (active layer) sandwiched between two heavily doped pþ and nþ regions (contacts). One of the most important figures related to the light– current conversion is the responsivity R, defined as the photocurrent flowing per incident watt of radiation and expressed by R¼

l (1 QR )hint (1 eaW ) 1:24

(7:3:1)

where l is the vacuum wavelength in mm, QR the reflectivity, hint (internal quantum efficiency) the number of collected electron–hole pairs per incident photon, a the optical absorption, and W the active layer thickness. The maximum theoretical responsivity of l/1.24 can be approached with suitable antireflection coatings to minimize QR, good electronic quality to grant a drift length large enough to prevent recombination and a large product aW to maximize absorption efficiency. The speed of the photoresponse depends on three main factors: the finite time needed by carriers to reach the contacts, the RC time-constant, and the diffusion time of the photogenerated electron–hole pairs outside the intrinsic layer. The transit time can be approximately written as ttr ¼ W =mE

(7:3:1a)

where m is the carrier mobility and E the electric field. At large enough fields (104 V/cm), velocity saturation occurs and (7.3.1a) becomes ttr ¼ W =vsat

(7:3:1b)

i.e., transit time limitations can be reduced by decreasing W. In the RC time constant above, R is the combination of diode series-resistance and load, while C is the junction capacitance with the addition of parasitics. The junction capacitance can be expressed as Cj ¼

© 2006 by Taylor & Francis Group, LLC

«A W

(7:3:2)

7.3-733

Near-Infrared Detectors

where « is the dielectric constant of the absorbing layer and A the area of the detector. Balancing the opposite effects of W on transit time and capacitance, an optimization can be pursued. However, a conventional high-speed photodiode is commonly designed to be small enough (area) to be transit-time limited, while W is set by a compromise between responsivity and speed, usually leading to W comprised between 1/a and 2/a. More device-oriented speed parameters are the 3 dB bandwidth f3 dB and the full width at half maximum (FWHM) of the pulse photoresponse, with 2f3 dB ¼ 1/FWHM. The two main sources of noise are dark current and quantum noise, both regarded as shot noise. Neglecting the background radiation, the total rms shot noise current is is2 ¼ 2qB(Ip þ Id )

(7:3:3)

where q is the electron charge, B the bandwidth, and Ip and Id photocurrent and dark current, respectively. The pertinent figure of merit is the noise equivalent power (NEP), defined as the minimum detectable rms optical power corresponding to a unity signal-to-noise ratio. The NEP is inversely proportional to the responsivity and scales with the rms shot noise in expression (7.3.3) above. In order to reduce both the transit time and the diffusion capacitance while, sometimes, improving their linearity, photodiodes are often operated at high reverse bias, thereby increasing the dark current and affecting negatively their noise performance.

7.3.3 SiGe: A Material for NIR Detection In this section, we discuss the SiGe material issues drawing specific attention to near-infrared light detection. Although Si and Ge have the same crystal structure, the growth of SiGe epitaxial layers on Si is affected by a large lattice mismatch (up to 4.2% for pure Ge on Si). At the deposition start-off, the initial SiGe layers adjust their lattice through compression (in the growth plane) and tensile strain (along the normal), while the substrate remains substantially undistorted. As the growth proceeds, however, the large strain is abruptly released and Ge recovers its own lattice spacing. This process, referred to as relaxation, takes place once the strain reaches a threshold corresponding to a critical thickness hc, and it is usually associated with the generation of a large amount of defects both in the growth plane (misfit dislocations) and perpendicularly to it (threading dislocations). The critical layer thickness hc as a function of Ge-concentration is graphed in Figure 7.3.1 (solid line) according to Bean’s model [9]. Results obtained with more conservative models and accounting for strain stability over temperature cycles typical of silicon processes are represented by a dashed line. The figure emphasizes the main problem in strained-layer epitaxy: high-quality epilayers of suitable thickness for electronic devices must have a low Ge content; on the other hand, if Ge-rich alloys are needed, one has to deal with a relaxed material. For a long time, relaxed epilayers were not considered suitable for devices, but they were recently reconsidered taking into account the tolerances to defects in different applications [10]. Defects, such as dislocations, affect the electrical properties of semiconductors in two main ways: first, they act as scattering centers thus impairing free carriers mobility; second, they introduce levels in the forbidden gap, which can serve as recombination centers or carrier traps. Majority-carrier devices (such as FET), when working in the active region, are less sensitive to carrier lifetime than minority-carrier devices (e.g., HBT, BJT) and, therefore, tolerate higher defect densities. Photogenerated carriers, in properly designed and biased p–i–n devices, travel at the saturation velocity and are collected by drift: for this reason, short lifetimes and impaired mobilities are still acceptable. The only concern with defects-induced levels in the gap relates to dark current, which becomes governed by Shockley–Read–Hall generation. In Equation (7.3.1) the factor (1 eaW) is the fraction of light absorbed in the intrinsic region of the p–i–n photodiode and approaches unity when W exceeds the absorption length. In Figure 7.3.2 we display the absorption coefficients at 1.3 and 1.55 mm, respectively, versus Ge-content for both unstrained (circles) and strained (lines) Si1xGex alloys. Absorption coefficients of unstrained alloys are after Potter [11] and Braunstein et al. [12] while strained-alloy data were calculated by Naval et al. [13]. The considerably

© 2006 by Taylor & Francis Group, LLC

7.3-734

The Silicon Heterostructure Handbook

Critical layer thickness (nm)

104

103

102

101

100

0

0.2

0.4 0.6 Ge mole fraction

0.8

1

FIGURE 7.3.1 Critical layer thickness versus Ge-concentration for both metastable (solid line) and unconditionally stable (dashed line) cases.

Absorption coefficient (cm−1)

104

103

102

101

100

0

0.2

0.4 0.6 Ge mole fraction

0.8

1

FIGURE 7.3.2 Optical absorption of strained (lines) and relaxed (dots) SiGe alloy as a function of Ge-content. The former are calculated, the latter are measured. Both 1.3 and 1.55 mm data are shown with filled and empty circles, respectively.

larger values of the latter are expected as a consequence of the strain-related bandgap shrinkage, as predicted by People [14] and experimentally demonstrated by Lang et al. [15]. From Figure 7.3.1 and 7.3.2 it is apparent that, for each composition of either strained or unstrained SiGe, the thickness required to obtain adequate absorption efficiencies is much larger than the corresponding critical thickness. For example, for x ¼ 0.2 at 1.3 mm, the absorption is 20 cm1 (strained), requiring more than 1 mm to absorb 90% of the light while the critical thickness is only 200 nm. The limitation described above suggested alternative strategies for fabricating sensitive and fast photodetectors: (i) the use of strained, high-quality SiGe alloys with low Ge-content to compensate

© 2006 by Taylor & Francis Group, LLC

Near-Infrared Detectors

7.3-735

the low responsivity with excellent noise performances, thanks to good transport properties and low dark currents; (ii) the use of relaxed pure-Ge layers to exploit the high absorption of the pure material at the cost of larger noise. In the case (i), materials can be obtained with a crystal quality comparable with the best achievable in conventional III–V heterostructure devices [9]. In strained SiGe layers the formation of dislocations is suppressed by keeping thicknesses below the critical value. The relevant drawback remains the previously mentioned low absorption. The adoption of multiple heterostructures or different geometries (guided-wave detectors) to overcome such limitation will be addressed in Section 7.3.4. Since a significant portion of this handbook is devoted to strained-layer epitaxy, we will not further discuss it, but turn to the less known relaxed material. In this case (ii), large aW products can be obtained through high Ge concentration and thick layers, but at the expense of a poorer crystal quality. The competition between relaxed (ii) and strained (i) approaches rests on the development of either a defect engineering strategy, in order to lower the defect density to an acceptable level, or an advanced design strategy. In general, due to lattice mismatch, the growth of Ge on Si is expected to be two-dimensional for the first few monolayers, after which islands are formed [16]. Islanding during epitaxy (or threedimensional growth), unless induced to exploit the quantum properties of nanostructures, is detrimental because it results in a nonflat, inhomogeneous film. Therefore, large efforts have been devoted to identify growth methods and parameters aiming at the release of strain (rather than island formation) through a controlled insertion of dislocations. The growth of Ge-rich epilayers above critical thickness has been attempted by several groups. Early heteroepitaxial growths by both chemical vapor deposition (CVD) [17] and physical vapor deposition (PVD) were carried out at a pressure of 1010 Torr on heated substrates: they exhibited similar characteristics with dislocation densities around 109 cm2. Pure-Ge single crystals were also obtained by evaporation at 106 Torr from a boron-nitride crucible at low temperatures (3758C to 4258C) [18]. Using an analogous technique Ohmachi et al. reported a remarkably high carrier mobility of 1000 cm2/V sec [19]. One of the first MBE-grown pure-Ge epilayers was reported with a threading dislocation density between 107 and 108 cm2 [20], and a comparable density was obtained by Fujinaga via low-pressure CVD and thermal annealing [21]. In 1991 at IBM, for the first time, Cunningham et al. reported the UHV–CVD epitaxial growth of pure Ge on Si [22]. Despite these initial and promising results, the reported threading dislocation (TD) densities were considered too large for practical purposes, and several techniques were proposed for improving the growth: graded buffer layers, surfactants, carbon incorporation, growth on processed substrates, and low-temperature buffer layers. Strain relaxation can be accomplished by the insertion of dislocations through a completely or partially relaxed buffer layer [23], either stepwise or linearly graded. The effectiveness of linearly graded buffers was first demonstrated by Fitzgerald et al. at AT&T Bell Laboratories [24] investigating both MBE and CVD growth techniques. They adopted a high growth temperature to completely relax the first layer and chose the grading rate in order to maintain a low strain throughout it. Their buffers with a grading rate of 10% Ge/mm up to final Ge-compositions of 23% and 50% exhibited TD densities of 4.4 105 and 3 106 cm2, respectively. They also obtained CVD epitaxial Si0.7Ge0.3 films with TD densities between 105 and 106 cm2 with grading of 10% to 40% Ge/mm [25]; nevertheless, the extension to pureGe turned out much more difficult. Only in the mid-1990s, combining a slowly varying graded buffer (10- to 20-mm thick) and a chemi-mechanical polishing, a pure-Ge epilayer was reported with a threading dislocation density as low as 2 106 cm2 using CVD [26]. The use of surfactants has been proposed to reduce the surface-free energies of both substrate and epilayer and thereby ease two-dimensional growth in the presence of a large mismatch. A remarkable result was obtained by Liu et al. with MBE by introducing a single Sb monolayer before epitaxy [27]. They fabricated a graded buffer with up to 50% Ge, followed by a 0.3-mm thick Si0.5Ge0.5 cap-layer, with a TD density of 1.5 104 cm2, two orders of magnitude lower than without Sb. H2 has also been proposed as a surfactant [28], and its effectiveness demonstrated in the growth of thick Ge films [29]. Despite their beneficial effects, however, surfactants are often prone to the drawback of residual doping [30].

© 2006 by Taylor & Francis Group, LLC

7.3-736

The Silicon Heterostructure Handbook

Another attempt to grow SiGe epilayers above critical thickness consists in the incorporation of carbon atoms to form SiGeC compounds. The strain can be compensated due to the smaller lattice parameter of C with respect to Si. The viability of this technique was first demonstrated by Eberl et al. in the growth of SiGeC epilayers with 25% Ge [31]. A TD density of 105 cm2 was obtained in a 1-mmthick relaxed step-graded buffer (up to 30% Ge) in a combination of Si1xGex and Si1xyGex Cy [32]. Unfortunately, the C dose is limited to about 4% by the low solubility of C in Si and by SiC precipitation, preventing its use in Ge-rich epilayers. Moreover, as C is added to a SiGe alloy keeping constant the Ge concentration, the bandgap is expected to increase, partially thwarting the effect of Ge [33]. Improved crystals can be obtained if misfit dislocations, rather than pinned and swept across the epilayer, are terminated on a free surface without affecting the film. Since this depends on the sample size, a decrease in TD density can be expected when the area is reduced, or the substrate is processed in order to obtain selective epitaxy. The effectiveness of this approach was proved by growing defect-free Si0.9Ge0.1 layers up to 3 mm on silicon oxide patterned Si [34] and high-quality pure-Ge on Si patterned through interferometric lithography [35]. The remarkable results obtained by graded buffers can be ascribed to strain release by means of the insertion of dislocations, which are expected not to propagate in the epilayer. A simpler way to achieve the same is the use of low-temperature Ge-buffer layers. The substrate temperature is crucial in Ge-rich epitaxy on Si: at low temperature (LT) the growth mode can be layer-by-layer, but above a certain temperature it turns into three dimensional (e.g., islands). In addition, if the surface is hydrogenated (as in CVD at low temperatures), the anisotropy of the surface energy is reduced, thus promoting a layer-by-layer growth (anisotropy is the main agent in island formation). This can be accomplished by keeping the substrate at a temperature Tsub below the desorption value Tdes of H from Ge [36]. Initially, only silicon LT-buffers were considered. Chen et al. reported a TD density of about 106 cm2 in a 500 nm thick Si0.7Ge0.3 MBE grown on a 200 nm LT Si buffer [37]. A slightly lower TD density (105 cm2) was reported by Li et al. using a thinner (50 nm) LT Si buffer before the MBE deposition of Si0.7Ge0.3 [38]. Linder et al. obtained TD densities of the order of 104 cm2 in MBE Si0.85Ge0.15 on 100 nm LT Si buffers [39], but Si buffers were effective only for low-concentration SiGe epilayers. A combination of Si LT buffer and step-graded buffer was employed in Si0.1Ge0.9 on Si with a TD density of 3 106 cm2 [40]. A new approach, based on an LT Ge buffer, has been recently proposed for the epitaxy of pure Ge on silicon via UHV-CVD [41]. At the beginning, the substrate is kept at low temperature in order to grow a flat and relaxed epitaxial layer of thickness suitable for total strain relaxation. The temperature is chosen in order to prevent H desorption from the Ge surface, thus avoiding the nucleation of three-dimensional Ge islands due to the H surfactant. Following the LT GE buffer, the deposition can proceed as in the homoepitaxial case, thus allowing a temperature increase for a faster growth rate. The good crystal quality was assessed by RHEED spectra, and the defect distribution in Ge evaluated by TEM. As expected, most defects were confined in the buffer, although a few dislocations penetrated the Ge epilayer up to the free surface. Luan et al. proposed a method to considerably reduce residual threading dislocations based on postgrowth thermal annealing [42]. They used an LT Ge-buffer and cyclic annealing between high and low temperatures, obtaining TD densities of 107 cm2. The TD reduction is due to enhanced dislocation glide and annihilation, as promoted by thermal stress. Following these results, the same group demonstrated a further TD reduction by performing a similar growth on small mesas of dimensions from 10 to 100 mm. The average TD density was about 2 106 cm2 [42]. An entirely novel approach employed the granular structure of polycrystalline Ge as an alternative to solve the problem of the large strain [43]. Thin films of poly-Ge were deposited on silicon by thermal evaporation in a vacuum of 106 Torr at different substrate temperatures. Raman spectroscopy and absorption measurements showed a clear transition between amorphous and polycrystalline around Tsub ¼ 3008C and poly-Ge optical absorption comparable to crystalline germanium [44]. The electronic properties of poly-Ge on Si are affected by a large acceptor-like defect density, leading to short carrier

© 2006 by Taylor & Francis Group, LLC

7.3-737

Near-Infrared Detectors

108

TDD (cm−2)

107

106

105

104

103 0

0.2

0.4

0.6

0.8

1

Ge mole fraction

FIGURE 7.3.3 Threading dislocation density versus Ge content.

lifetime and severely limiting the doping. Nevertheless, the large absorption in the NIR (about 104 cm1 at 1300 nm) makes this material quite interesting for NIR photodetectors [45]. Moreover, the required Tsub ¼ 3008C ensures good compatibility with silicon technology with respect to both CVD and MBE heteroepitaxy, where substrate cleaning, deposition, and annealing require temperatures in the range 6008C to 10008C. Figure 7.3.3 summarizes the reported TD densities versus Ge concentration in films above critical thickness [46]. The graph confirms that, even in the relaxed regime, the larger the mismatch (Ge concentration) the more critical is the epitaxial growth. The visible spread in values for a fixed Ge-concentration depends on the method employed for defect reduction and on the typical sensitivity of heteroepitaxy to apparatus and parameters. While TD density is a commonly accepted figure-of-merit for epitaxial films, from a device viewpoint its impact in terms of transport parameters must be investigated. Early studies on plastically deformed germanium demonstrated a linear relationship between TD and carrier lifetime, suggesting that lifetime is limited by recombination at dislocations [47]. More recently, deep-level transient spectroscopy has pointed out to a linear relationship between TD and deep-trap densities, confirming the role of dislocations in the enhancement of minority carrier recombination and generation [48]. Quantitative correlations between leakage current and TD density have been demonstrated in SiGe p–n and p–i–n diodes [49, 50]. For the latter, dark currents of 1 mA/cm2 were measured for TD of 107 cm2 in 0.5-mm thick Si0.75Ge0.25, with a linear increase with TD density. This behavior is expected in photodiodes with thick intrinsic layers, because the dark current is dominated by thermal generation, inversely proportional to carrier lifetime and directly proportional to the intrinsic layer width. Figure 7.3.3 shows that pure-Ge epilayers can be obtained with TD spanning from 106 to 108 cm2. Using the relationship in Ref. [50], dark currents of 0.2 to 20 mA/cm2 can be expected in this density range for a 1-mm-thick intrinsic layer. Although an extrapolation of the scaling law from Si0.75Ge0.25 to pure-Ge is questionable, a dark current of 20 mA/cm2 was measured on 4 mm p–i–n diodes with TD densities of 2 107 cm2, in close agreement with the predicted value of 16 mA/cm2 [51]. At zero or low reverse bias, the TD-related carrier-lifetime reduction can lead to enhanced recombination in the depleted active layer of a p–i–n photodiode, thus affecting the internal quantum efficiency (hint). A suitable approach to investigate this is to measure photocurrent versus bias on a metal–semiconductor–metal structure, where the semiconductor is the SiGe epilayer under test. Figure 7.3.4 shows the photocurrent versus bias for closely spaced (10 mm) interdigited metal–Ge–metal photodiodes with different TD densities [52]. The TD effect is clear in both the magnitude of hint

© 2006 by Taylor & Francis Group, LLC

7.3-738

The Silicon Heterostructure Handbook

Internal quantum efficiency hi

100 10−1 10−2 10−3 TDD = 9⫻108 cm−2 −4

TDD = 3⫻107 cm−2

10

TDD = 1⫻107 cm−2

10−5 0

0.2

0.4

0.6

0.8

1

1.2

1.4

Bias voltage [V]

FIGURE 7.3.4 Internal quantum efficiency for various TD as a function of applied voltage.

and the higher applied voltage required in lower quality epilayers. Quantitatively, the experimental data can be fit to extract the mt product by hint ¼

i d L(E) h 1 eL(E) d

(7:3:4)

with d the interelectrode spacing and L(E) ¼ mtE the drift length, and m, t, and E the carrier mobility, lifetime, and electric field amplitude, respectively [53]. The possibility (demonstrated in Figure 7.3.4) of reaching total internal quantum efficiency at very low voltage bias for TDD of 107 cm2 is quite remarkable and could help as a reference for the evaluation of the acceptable TDD for photodetector application. As will become clear in the next paragraph, the dark current and the internal quantum efficiency can be regarded as important factors in the evaluation of a certain SiGe technology for NIR applications. In this section, after addressing the material issues of SiGe as a semiconductor for the realization of the active layer of photodetectors, we have presented a wide and updated review of the several growth techniques that demonstrate the large variety of SiGe and the different level of compromise between crystal quality and NIR absorption.

7.3.4 SiGe Detectors: Design and Fabrication According to the epilayer used, SiGe light detectors can be divided in the two main categories: strained and relaxed devices. As already pointed out, small aW values achievable in the former force the adoption of waveguide geometries where the light, confined in the growth plane, is absorbed in propagation rather than across the thickness (as for normal incidence). This approach is usually pursued in conjunction with multiple heterostructures: the growth of a SiGe layer is followed, before critical thickness, by a Si-layer to partially release the strain, repeating the steps up to the desired thickness. Figure 7.3.5 represents the most common structures: (a) mesa photodiode at normal incidence, (b) photodiode embedded in, or (c) above a waveguide.

Waveguide Photodetectors (WPD) Guided-wave geometries can compensate for the low aW products in strained epilayers. While these devices are only suitable as fiber-optic receivers, the latter constitute a vast portion of the detector market.

© 2006 by Taylor & Francis Group, LLC

7.3-739

Near-Infrared Detectors

FIGURE 7.3.5 Schematic of the most commonly used photodetector geometries: (a) normal incidence, (b) waveguide photodiode, and (c) passive waveguide with photodiode.

In WPD the responsivity, at variance with (7.3.1), can be expressed as R¼

l C(1 QR )hint (1 eaGfL ) 1:24

(7:3:5)

where C is the coupling efficiency between the optical fiber and the guide, and depends on the twodimensional overlap integral of the two corresponding modes. C can be optimized and eventually approach unity if tapered waveguide or fibers are employed. Antireflection coating of the input facet is possible but not common, because the process is not planar as the device fabrication. The exponent aGfL can be regarded as an absorption–length product, with L the device length and aGf an effective absorption given by the product of the optical absorption a in the alloy, the guide confinement G and the ratio f between the SiGe and the total semiconductor volume of the waveguide. The bandwidth is limited by both junction capacitance and transit time, as mentioned in Section 7.3.2. To avoid RC speedlimitations due to large capacitances, the WPD length must be kept as short as possible. WPDs are commonly integrated on silicon-on-insulator (SOI) wafers, with dielectric confinement perpendicular to the growth plane. Lateral confinement is obtained by etching ridges of size compatible with the fiber core. The need for nþ and pþ top and bottom contacts, respectively, complicates the guide design due to free-carrier absorption losses, which imposes intrinsic Si-spacers around the SiGe heterostructure. Several design parameters are involved in the optimization of the WPD using (7.3.5) as a guideline while keeping low the capacitance. We will focus mostly on material-related parameters, e.g., the thickness h of the SiGe alloy, the thickness W of the silicon epilayer between two adjacent SiGe layers, the number N of SiGe–Si repetitions, Ge-concentration x, and device length L. Even if the alloy absorption increases with x, quantum size effects eventually arise due to the limits on critical thickness, widening the bandgap and, consequently, lowering a. Once typical alloy concentrations for highest absorption are chosen in the 0.5 to 0.6 mm range with thickness set to the maximum allowable hc, then silicon thickness and number of periods have to be selected. The overall structure thickness, however, is limited by the critical value corresponding to the average Ge composition or by fabrication issues. Figure 7.3.6 is an example of calculated SiGe WPD following such design guidelines. The responsivity is derived for both 1.3 and 1.55 mm for SiGe alloy at 50% using Equation (7.3.5) assuming unity internal quantum efficiency and employing a vectorial modal solver for evaluating the factor aGf. As for the absorption coefficients, strained values are used from Figure 7.3.1, while the critical thicknesses are those metastable (solid line of Figure 7.3.2). The responsivity clearly increases with detector length at the expense of the bandwidth, indicated in the upper side of the plot, but a considerably lower absorption poses severe limitations to the WPD at 1.55 mm. A systematic SiGe design technique for the optimization of 1.3 mm waveguide photodiode has been developed by Naval et al. and the results are reported in Ref. [13]. The following is a review of the most relevant SiGe WPD presented to date. A first SiGe waveguide device was proposed by Temkin et al. [54]: the active layer (which also is the guide core) was a strained GexSi1x/Si quantum well repeated 20

© 2006 by Taylor & Francis Group, LLC

7.3-740

The Silicon Heterostructure Handbook

Bandwidth (GHz) 10

0.8

5

2.5

1

0.7 1300 nm Responsivity (A/W)

0.6 0.5 0.4 0.3 1550 nm

0.2 0.1 0 0

1000

2000 3000 4000 Detector length (µm)

5000

FIGURE 7.3.6 Calculated responsivity and bandwidth versus device length. The investigated structure is made of three QW (10 nm Si0.5Ge0.5 þ 500 nm Si) between two Si spacers (1 mm). Width is taken as 10 mm.

times, and various Ge contents in the 0.4 to 0.6 range were realized adjusting the thickness to the critical value. The maximum external quantum efficiency at 1.3 mm was 10.2% for a 10 V reverse bias. At this bias the dark current was 7.1 mA/cm2, with a bandwidth close to 1 GHz in a 300-mm-long detector. A similar heterostructure (3.3 nm Ge0.6Si0.4 and 29 nm Si) was used in an avalanche diode embedded in waveguides 50-mm wide and 50 to 500 mm long [55] with a maximum responsivity of 1.1 A/W at 1.3 mm. A successive device with inverted doping (nþppþ on an nþ type substrate) exhibited more stable electrical characteristics and an external responsivity as high as 4 A/W at 1.3 mm for 30 V reverse bias, with a remarkably fast (100 ps) response time [56]. As new optical transition of SiGe superlattices was predicted in the NIR [57], short-period (few monolayers) GeSi heterostructures were also attempted in waveguides [58]. The lack of responsivity improvements, probably due to the large quantum size effect, did not encourage further efforts in this direction. A waveguide p–i–n photodiode was fabricated in UCLA/AT&T with a 1-mm thick Ge-rich (x ¼ 0.7) multi-quantum-well absorbing layer, equipped with two 1-mm thick Si spacers. The external quantum efficiency at 1.32 mm reached 7% for 14 V, while the dark current density (at the same bias) was 2.7 mA/cm2 [59]. Open eye-diagrams for 0.5 and 1.5 Gb/s pseudorandom NRZ (nonreturn to zero) optical signals were also reported. Splett et al. [60] introduced a novel WPD SiGe detector: SiGe alloys of different compositions were used for the waveguide (x ¼ 0.02) and for the detector (x ¼ 0.45), the latter grown above the guide as sketched in Figure 7.3.5(c). For a 7 V reverse bias the maximum external efficiency at 1.28 mm was 11%, with a dark current of about 1 mA/cm2 and a GHz bandwidth. The first SiGe detector on a SOI waveguide was reported by Kesan et al. [61]. The absorbing layer was a typical SiGe MQW structure: the device exhibited a good responsivity of 0.4 A/W at 1.1 mm, but poor above 1.2 mm. A SiGeC waveguide detector was proposed by Huang et al. [62]. It consisted of an 80-nm-thick SiGeC absorbing layer with a Ge-content of about 50%. The measured maximum external quantum efficiency at 0.3 V was 0.2 and 8% at 1.55 and 1.3 mm, respectively, with dark current density of 4 mA/cm2. Li et al. reported a large (one of the largest) responsivity of 80 mA/W at 1.55 mm for a SiGe device operated at 10 V. The device (2-mm long) consisted of a 50%SiGe MQW above a low Ge-content SiGe waveguide [63]. Undulating MQWs of Si0.5Ge0.5 5 nm layers, sandwiched in 12.5-nm thick Si barriers, formed the absorption layer of an MSM WPD fabricated on SOI with a 2 mm thickness, a 65 mm width, and 240 mm

© 2006 by Taylor & Francis Group, LLC

7.3-741

Near-Infrared Detectors

length. This device exhibited responsivities as high as 1.6 and 0.1 A/W at 1.3 and 1.55 mm, respectively [64]. In this case the large quantum efficiency at 1.3 mm, the observed sublinear dependence of responsivity on light intensity and the large dark current density pointed to the role of photoconductive gain, expected to affect noise and bandwidth. Comparable responsivities (0.16 A/W at 1.55 mm) were reported in similar guided-wave structures. The increased absorption was explained in terms of high local Ge-concentration, typical of a three-dimensional growth mode [65]. In 1997, the NEC Corporation realized a waveguide detector on SOI employing a 30-period MQW with 3 nm Si0.9Ge0.1 and 32 nm Si. The low Ge-content, imposed for compatibility with the high temperature (9508C) used in Si technology for bipolar and MOS transistors, resulted in an NIR photoresponse only slightly larger than in silicon. For a 5 V reverse bias at 980 nm the detector featured an external quantum efficiency of 25% to 29%, a dark current below 50 mA/cm2 and a frequency response extending up to 10.5 GHz and indicating good material quality [66]. Two specific features of this device were the selective growth of SiGe layers in a previously opened trench in SOI overlayer and the groove receptacle for fiber alignment. In conclusion, while most SiGe WPDs in literature are consistent with the predictions in Figure 7.3.6, lower than expected responsivities can be often associated to coupling and waveguide losses. Figure 7.3.7 shows responsivity versus reverse bias as reported by various authors. The need for a large voltage is associated to the trapping of photogenerated carriers by the SiGe wells, a common feature of most MQW detectors.

Normal Incidence Photodetectors Normal incidence photodetectors (NIP) are the most common, because light from any source can be easily coupled and the fabrication is entirely planar. In this case, light propagation and carrier transport proceed in the same direction (as schematically shown in Figure 7.3.5(a)). The design of NIPs is based on the optimization of the responsivity, as evaluated from (7.3.1), and resembles the design of conventional photodetectors except for the need of dealing with relaxed materials. If the device can be operated at a fixed wavelength, a SiO2 layer of suitable thickness can effectively reduce reflection losses, which would otherwise amount to about 36%. The collection

0.12 L = 9mm

Responsivity (A/W)

0.1

L = 2mm

0.08

0.06 L = 1mm 0.04 Li l=1.55 µm [63] Jalali l=1.3 µm [59] Splett l=1.3 µm [60]

0.02

0 0

5

10 15 Reverse voltage (V)

20

FIGURE 7.3.7 Selection of some relevant results in terms of responsivity versus reverse bias voltage. The device length L is also indicated.

© 2006 by Taylor & Francis Group, LLC

7.3-742

The Silicon Heterostructure Handbook

efficiency, which depends on transport properties (through the mobility–lifetime product mt), can be made close to unity by applying a large enough reverse bias. It has been shown that 100% carrier collection can be achieved at <1 V [52] and that the built-in voltage of a p–i–n diode is high enough to efficiently operate at short circuit if the TD density is around 107 cm2 [51]. When using relaxed layers the material of choice is pure-Ge, therefore the maximum a is available and the absorption efficiency is maximized by employing the largest thickness W. Upper limits to W relate to the longest acceptable deposition time (two-dimensional heteropitaxy in the presence of large strain imposes small growth rates) or are dictated by trade-off with transit-time limitations. The charts in Figure 7.3.8 can be used to design a Ge photodetector based on bandwidth and responsivity (upper horizontal axis). In the figure, the iso-bandwidth curves are traced versus active layer thickness and photodiode diameter, for velocity saturation and absorption as in Figure 7.3.1. In the second plot, the large required thickness is associated with the rather low absorption of Ge at 1.55 mm (460 cm1). It should be noted that the spectral range between 1.45 and 1.54 mm (S and part of C bands) is exploited for WDM optical communications: in this window Ge-absorption spans between 5800 and 1470 cm1. Recently, bandgap narrowing of Ge-layers grown on Si and induced by strain accumulated during growth and due to different thermal expansion of Si and Ge was reported [67]. This opens new perspectives for exploiting Ge-detectors in the L band, as well. Following the design guidelines above, below we review the most relevant results in NIP obtained with relaxed material.

FIGURE 7.3.8 Calculated responsivity and bandwidth versus device area and active layer thickness for illumination at (a) 1.3 mm and (b) 1.55 mm.

© 2006 by Taylor & Francis Group, LLC

Near-Infrared Detectors

7.3-743

The first pure-Ge p–i–n detector was MBE grown on a thick step-graded buffer to separate the intrinsic active layer from the highly dislocated Si–Ge interface. The diode exhibited good quantum efficiency (40% at 1.3 mm) in the photovoltaic mode, indicating satisfactory transport properties of the Ge-intrinsic layer. The large (50 mA/cm2) reverse dark current was attributed to the residual dislocation density. A significant improvement was obtained with a SiGe superlattice embedded in the buffer layer, reducing TD down to 5 107 cm2. Unfortunately, even the quantum efficiency dropped to 3% at 1.3 mm [68]. After a long inactivity due to a largest interest to the second window (1.3 mm) where strained SiGe were competitive, pure-Ge has been revived for use in an extended portion of the NIR. Adopting a twophase growth Sutter et al. tried to bypass the time-consuming growth of a thick buffer graded up to pure-Ge [69]. The growth rate was low during the evaporation of a thin layer, then the temperature was raised for the remaining deposition. The Ge layer was 4-mm-thick, and the first 2 mm highly p-doped the p–i–n junction formed by subsequent diffusion. Material characterization confirmed the good crystalline quality with TD of 5 106 cm2. Performances were very similar to those by Luryi et al. (43% peak external quantum efficiency at 1.55 mm in the photovoltaic mode with dark current of 51 mA/cm2). Among NIP based on strained SiGe, Huang et al. reported p–i–n photodiodes employing a MQW absorbing layer with 10 nm Si0.5Ge0.5 wells and 40 nm Si spacers up to an overall thickness of 500 nm [70]. The device was a pþ–i–nþ structure, antireflection coated with SiO2 to optimize light coupling at 1.3 mm. A 1% external quantum efficiency was reported at 1.3 mm and dark current densities of about 3 mA/cm2 for a reverse bias of 4 V. The same group tested the incorporation of carbon to compensate for SiGe–Si lattice mismatch [71]. This normal incidence p–i–n detector with a SiGeC active layer was grown on pþ Si using 80 nm Si0.4xGe0.6Cx alloy with x ¼ 1.5%. The normal incidence quantum efficiency at 1.3 mm was about 1%, remarkable when compared to the similar efficiency obtained in the previous work with a 500 nm SiGe [70]. Only slight improvements (1.3% to 2.2% at 1.3 mm) were subsequently achieved with thicker active layers [72]. The early experiments in SiGeC for NIR NIPs confirmed the expected limitations: due to the counteracting effects of energy gap increase in the alloy and strain balance associated with C-concentration, only modest absorptions or small enlargements of critical thickness could be obtained. An alternative approach to NIPs consists of strained layer photodetectors embedding SiGe in a resonant cavity. A fourfold responsivity enhancement at 1.3 mm (6.5 mA/W) was demonstrated employing the silicon–oxide interface of a SOI substrate as the bottom mirror and a SiO2–Si Bragg reflector on the top. The SiGe-layer was a MQW of 20 periods of 8 nm Si0.65Ge0.35 and 19 nm Si [73]. A similar approach was used to thin the Ge-layer and achieve good responsivities at 1.55 mm. Around 740-nm-thick Ge was deposited on a double-SOI, which served as the bottom mirror, while the Ge–air interface defined the top reflector, yielding R ¼ 0.19 A/W [74]. To exploit the benefits of a low-temperature buffer along with the surfactant action of hydrogen to reduce TD, pure-Ge was CVD deposited on Si for MSM [75]. The NIP exhibited a 1.3 mm responsivity of 240 mA/W at 1 V bias. More recently, Ge-on-Si MSM detectors with small finger-spacing (1 to 3 mm) [76] based on a 300 nm pure-Ge layer (MBE grown using Sb as surfactant) exhibited responsivities as high as 140 and 90 mA/W at 1.3 and 1.55 mm, respectively, with dark current densities exceeding a few A/cm2. This major drawback of MSM geometries is associated with low Schottky barriers, although MSM are the fastest Ge-on-Si NIPs demonstrated to date, with responses as short as 12 psec. Interdigited Ge p–i–n photodetectors with small spacing (1 mm) and 1 mm pure-Ge on a thick SiGe graded-buffer provided responsivities of about 0.51 A/W at 1.3 mm, dark currents of about 0.7 A/cm2 and a 3 dB-bandwidth of 3.8 GHz [77]. Later on, low-dislocation Ge-on-Si NIPs was realized by a combination of a lowtemperature buffer and postgrowth annealing [78]. The devices consisted of 1 mm unintentionally doped Ge on p-type (1 0 0) Si. Due to the improved material quality, the photodetectors exhibited a highly saturated responsivity of 550 and 250 mA/W at 1.3 and 1.55 mm, respectively, at reverse biases of a few hundred mV. The measured speed of 850 psec was RC limited even in the smallest 200 200 mm2 device, and the dark saturated current was 30 mA/cm2. Remarkable improvements were demonstrated

© 2006 by Taylor & Francis Group, LLC

7.3-744

The Silicon Heterostructure Handbook

by fabricating p–i–n structures with intrinsic layer from 1 to 4 mm in thickness. This, along with antireflection coatings, allowed the highest reported Ge-on-Si responsivities of 0.89 and 0.75 A/W at 1.3 and 1.55 mm, respectively, at <1 V bias, with RC limited pulse response <200 psec at 1.3 mm and dark currents as low as 15 mA/cm2 [79, 80]. The remarkable performances for this devices are reported in Figure 7.3.9, where the spectral responsivity and the 3 dB bandwidth are shown. The lowest dark current in Ge-on-Si pn-junctions was reached with low TD density by an optimized graded-buffer complemented by chemi-mechanical polishing at an intermediate composition of Si0.5Ge0.5. Dark current densities were lower than 0.2 mA/cm2, comparable with what expected for a bulk-Ge diode with the same doping profile. A maximum R ¼ 133 mA/W was obtained at 1.3 mm in short circuit, denoting excellent transport properties in the junction; its absolute value was limited by the small (0.24 mm) thickness of the absorbing layer [81]. A comparison between the two approaches, LT and graded buffers, respectively, was conducted by Jiang et al. [82]. They evaluated the responsivity of two p–i–n devices with active layers of (a) 400-nmthick Si0.15Ge0.85 on LT Si buffer, (b) 300-nmthick Si0.65Ge0.35 on 2 mm SiGe graded buffer. Saturated values of 70 and 150 mA/W were measured at 1.3 mm in samples (a) and (b), respectively. The shortcircuit responsivity of the LT sample was much larger than on the graded buffer, suggesting a better quality or a more efficient collection due to the shorter depletion region. NIR photodetectors have been demonstrated in poly-Ge–Si with R ¼ 16 and 6 mA/W at 1.3 and 1.55 mm, respectively [44]. The limitation was attributed to the short diffusion length of poly-Ge and to the unintentional high p-doping. These NIPs have been operated at >2.5 Gbit/sec with a dark current of 2 mA/cm2 at 1 V [83].

Toward Monolithic Integration The pioneering work by People [9] and Pearsall [84] on electronic and optical characterization of SiGe heterostructures opened new perspectives in the fabrication of silicon-based photonic devices, the key

3.0 2.5

10−1 f 3dB (GHz)

Responsivity (A/W)

100

2.0 1.5 1.0 0.5 0.0

10−2 1100

1200

1.0 1.5 0.5 Reverse voltage (V)

1300

1400

1500

2.0

1600

1700

Wavelength (nm)

FIGURE 7.3.9 Experimental data from Fama` et al. [80] showing the spectral responsivity of a 4-mm thick pure-Ge mesa on Si. Bandwidth as a function of reverse bias is displayed in the inset.

© 2006 by Taylor & Francis Group, LLC

Near-Infrared Detectors

7.3-745

issue is the compatibility with the unsurpassed VLSI technology. Since then, large effort has been devoted to the exploitation of SiGe heterostructures in optoelectronics, as reported in Refs. [8, 85]. Nevertheless, to date only two SiGe photonic devices have been monolithically integrated with Si electronics. A monolithic SiGe–Si p–i–n and front-end transimpedance amplifier circuit was demonstrated in 1998, with SiGe HBTs exhibiting fmax ¼ 34 GHz and DC-gain ¼ 25 [86]. The SiGe p–i–n shared the HBT base and collector and provided R ¼ 0.3 A/W at 850 nm, with a 450 MHz bandwidth. Although the SiGe contribution in the p–i–n was negligible (the absorption layer is the Si collector), this was the first demonstration of monolithic feasibility using a standard process. The first SiGe optoelectronic integrated circuit (IC) operating in the NIR was a linear array of eight NIPs, connected to a transimpedance amplifier through an analog multiplexer. The IC was fabricated in the ALCATEL 2.0 mm CMOS technology and, after the CMOS process, a polycrystalline Ge-layer was evaporated at low temperature in properly windowed n-wells to form the p–n photodiodes. Due to the low thermal budget required for poly-Ge deposition, the silicon electronics preserved both functionality and performance, and the NIP responsivity and dark current density were 16 mA/W and 1 mA/cm2, respectively [87]. Figure 7.3.10 is a photograph of the chip. The poly-Ge film was deposited on a silicon tub (cathode) and extended over a metal pad (anode), as shown in the enlargement on the right. The same authors are currently working at a more advanced chip containing a linear array of poly-Ge photodiodes provided with A/D conversion circuitry and serial digital output.

7.3.5 Summary In this chapter, we have attempted to provide the reader with a comprehensive introduction to NIR detection with SiGe. Since this relatively new material has been investigated at levels typical of actual device engineering, we reviewed its most relevant properties with specific attention to photodiode implementations. Both guided-wave (WPD) and normal incidence (NIP) detectors have been discussed, pointing to basic design guidelines and focusing on limitations and trade-offs typical of the SiGe–Si heterostructures. We have presented a critical overview of the best devices fabricated in the past 20 years.

FIGURE 7.3.10 Photograph of the integrated eight-pixel linear array with amplifier and addressing electronics. The poly-Ge film on a silicon tub is visible in the enlargement on the right.

© 2006 by Taylor & Francis Group, LLC

7.3-746

The Silicon Heterostructure Handbook

Ge NIP

1

Ge NIP Ge NIP

Ge NIP

Ge NIP

0.6

0 10−4

10−3

SiGeC WPD SiGe WPD

polyGe NIP SiGe WPD SiGe NIP SiGeC WPD

SiGe WPD

GeC NIP

Ge NIP

0.2

Ge NIP

0.4

SiGe NIP

Responsivity (A/W)

0.8

10−2

10−1 2

Dark current density (A/cm )

FIGURE 7.3.11 Responsivities and corresponding dark current densities for most reported photodetectors. NIP stands for normal incidence, WPD for waveguide detectors. The top-right (bottom-left) oval collects the relaxed-Ge (strained-alloy) photodiodes.

At the end of this chapter, finally, in Figure 7.3.11, we collect responsivities and dark current densities of a number of SiGe devices reported to date and cited in the bibliography. The picture clearly shows the trade-off between efficiency and material quality. Data for SiGe alloys are grouped in the bottom-left, showing that high-quality strained-epilayers with low Ge-alloys are obtained at the expense of a trade-off with absorption efficiency. To overcome the thickness limitation, they can be employed in waveguide geometries. Thick Ge-rich relaxed layers appear in the top-right corner of the graph, showing the beneficial effect of the Ge-absorption associated to large thicknesses. However, they exhibit lower crystal quality, as witnessed by the large current density, and are commonly used at normal incidence. It is worth noting that attempts in reducing the dark current of pure-Ge devices turned into severe quenching of the responsivity (as seen in Figure 7.3.11). Despite the fact that the ideal region with R >0.5 A/W and dark currents below 1 mA/cm2 have not yet been accessed, we trust that the current quality of both materials and devices is close to meet the requirements of industry developments and commercialization of SiGe-based NIR detectors for a large number of applications. Most pure Ge-based devices exhibit large R at both 1.3 and 1.55 mm, while the corresponding dark currents are often negligible with respect to both thermal and excess noise of the transimpedance amplifiers in most receivers. In critical applications where the shot noise associated to the dark current is unacceptable, the strained-alloy needs be adopted, eventually aiming at higher sensitivities in suitably tailored waveguide geometries.

References 1. AE Willner and Y Xie. Wavelength domain multiplexed (WDM) fiber optic communication network. In M Bass, ed. Handbook of Optics. NewYork: McGraw Hill, 2001, pp. 1–27. 2. P Ceccato, N Gobron, S Flasse, B Pinty, and S Tarantola. Remote Sensing of Environment 82:188–192, 2002. 3. AC Stanton, JA Silver, DS Bomse, DB Oh, DC Hovde, DJ Kane, and ME Paige. Trace gas detection using near-infrared diode lasers. Proc. IEEE-LEOS Ann. Meet. 2:324–325, 1995.

© 2006 by Taylor & Francis Group, LLC

Near-Infrared Detectors

7.3-747

4. SA Soper, JH Flanagan Jr, BL Legendre, DC Williams, and RP Hammer. Near-infrared, laser-induced fluorescence detection for DNA sequencing applications. IEEE J. Sel. Top. Quantum Electron. 2: 1129–1139, 1996. 5. PJ Kirkpatrick, P Smielewski, JMK Lam, and P Al-Rawi. Use of near infrared spectroscopy for the clinical monitoring of adult brain. J. Biomed. Opt. 1:363–374, 1996. 6. TD Tosteson, BW Pogue, E Demidenko, TO McBride, and KD Paulsen. Confidence maps and confidence intervals for near infrared images in breast cancer. IEEE Trans. Medical Imaging 18:1188– 1193, 1999. 7. JD Cressler. SiGe technology. In WK Chen, ed. The VLSI Handbook. Boca Raton: CRC Press, 2000, pp. 1–10. 8. RA Soref. Silicon-based Optoelectronics. Proc. IEEE 81:1687–1706, 1993. 9. R People. Physics and applications of GeSi/Si strained-layer heterostructures. IEEE J. Quantum Electron. 22:1696–1710, 1986. 10. FK LeGoues. The effect of strain on the formation of dislocations at the SiGe/Si interface. MRS Bull. 21:38–44, 1996. 11. RF Potter. Germanium. In ED Palik, ed. Handbook of Optical Constants of Solids. New York: Academic Press, 1985, pp. 465–469. 12. R Braunstein, AR Moore, and F Herman. Intrinsic optical absorption in germanium–silicon alloys. Phys. Rev. 109:695–710, 1958. 13. L Naval, B Jalali, L Gomelsky, and JM Liu. Optimization of SiGe/Si waveguide photodetectors operating at l ¼ 1.3 mm. J. Lightwave Technol. 14:787–797, 1996. 14. R People. Indirect band gap of coherently strained GeSi bulk alloys on h0 0 1i silicon substrates. Phys. Rev. B 32:1405–1408, 1985. 15. DV Lang, R People, JC Bean, and AM Sergent. Measurement of the band gap GeSi/Si strained-layer heterostructures. Appl. Phys. Lett. 47:1333–1335, 1985. 16. I Daruka, J Tersoff, and AL Barabasi. Shape transition in growth of strained islands. Phys. Rev. Lett. 82:2753–2756, 1999. 17. TF Kuech and M Maenpaa. Epitaxial growth of Ge on h1 0 0i Si by a simple chemical vapor deposition technique. Appl. Phys. Lett. 39:245–247, 1981. 18. M Garozzo, G Conte, F Evangelisti, and G Vitali. Heteroepitaxial growth of Ge on h1 1 1i Si by vacuum evaporation. Appl. Phys. Lett. 41:1070–1072, 1982. 19. Y Ohmachi, T Nishioka, and Y Shinoda. The heteroepitaxy of Ge on Si(1 0 0) by vacuum evaporation. J. Appl. Phys. 54:5466–5469, 1983. 20. JM Baribeau, TE Jackman, DC Houghton, P Maigne, and MW Denhoff. Growth and characterization of SiGe and Ge epilayers on (1 0 0) Si. J. Appl. Phys. 63:5738–5746, 1988. 21. K Fujinaga. Low-temperature heteroepitaxy of Ge on Si by GeH4 gas low-pressure chemical vapor deposition. J. Vac. Sci. Technol. B 9:1511–1516, 1991. 22. B Cunningham, JO Chu, and S Akbar. Heteroepitaxial growth of Ge on (1 0 0) Si by ultrahigh vacuum, chemical vapor deposition. Appl. Phys. Lett. 59:3574–3376, 1991. 23. E Kasper. Growth and properties of Si/SiGe superlattices. Surf. Sci. 174:630–639, 1986. 24. EA Fitzgerald, YH Xie, ML Green, D Brasen, AR Kortan, J Michel, YJ Mii, and BE Weir. Totally relaxed GeSi layers with low threading dislocation densities on Si substrates. Appl. Phys. Lett. 59:811–813, 1991. 25. GP Watson, EA Fitzgerald, YH Xie, and D Monroe. Relaxed, low defect density Si0.7Ge0.3 epitaxial layers grown on Si by rapid thermal chemical vapor deposition. J. Appl. Phys. 75:263–269, 1994. 26. MT Currie, SB Samavedam, TA Langdo, CW Leitz, and EA Fitzgerald. Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical–mechanical polishing. Appl. Phys. Lett. 72:1718–1720, 1998. 27. JL Liu, CD Moore, GD U’Ren, YH Luo, Y Lu, G Jin, SG Thomas, MS Goorsky, and KL Wang. A surfactant-mediated relaxed Si0.5Ge0.5 graded layer with a very low threading dislocation density and smooth surface. Appl. Phys. Lett. 75:1586–1588, 1999.

© 2006 by Taylor & Francis Group, LLC

7.3-748

The Silicon Heterostructure Handbook

28. M Copel and RM Tromp. Are bare surfaces detrimental in epitaxial growth? Appl. Phys. Lett. 58:2648–2650, 1991. 29. A Sakai and T Tatsumi. Ge growth on Si using atomic hydrogen as a surfactant. Appl. Phys. Lett. 64:52–54, 1994. 30. D Reinking, M Kammler, M Horn-von-Hoegen, and KR Hofmann. Enhanced Sb segregation in surfactant-mediated-heteroepitaxy: high-mobility, low-doped Ge on Si. Appl. Phys. Lett. 71:924– 926, 1997. 31. K Eberl, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Appl. Phys. Lett. 60:3033–3035, 1992. 32. HJ Osten and E Bugiel. Relaxed Si1xGex/Si1xyGexCy buffer structures with low threading dislocation density. Appl. Phys. Lett. 70:2813–2815, 1997. 33. RA Soref. Silicon-based group IV heterostructures for optoelectronic applications. J. Vac. Sci. Technol. A 14:913–918, 1996. 34. F Banhart and A Gutjahr. Stress relaxation in SiGe layers grown on oxide-patterned Si substrates. J. Appl. Phys. 80:6223–6228, 1996. 35. TA Langdo, CW Leitz, MT Currie, EA Fitzgerald, A Lochtfeld, and DA Antoniadis. High quality Ge on Si by epitaxial necking. Appl. Phys. Lett. 76:3700–3702, 2000. 36. L Di Gaspare, G Capellini, E Palange, F Evangelisti, L Colace, G Masini, F Galluzzi, and G Assanto. Ge on Si(1 0 0) near infrared detectors: material issues and results. Proc. of the 24th Int. Conf. Phys. Semicond. (CD), Jerusalem, 1998. 37. H Chen, LW Guo, Q Cui, Q Hu, Q Huang, and JM Zhou. Low-temperature buffer layer for growth of a low dislocation-density SiGe layer on Si by molecular-beam epitaxy. J. Appl. Phys. 79:1167–1169, 1996. 38. JH Li, CS Peng, Y Wu, DY Dai, JM Zhou, and ZH Mai. Relaxed Si0.7Ge0.3 layers grown on lowtemperature Si buffers with low threading dislocation density. Appl. Phys. Lett. 71:3132–3134, 1997. 39. KK Linder, FC Zhang, JS Rieh, P Bhattacharya, and D Houghton. Reduction of dislocation density in mismatched SiGe/Si using a low-temperature Si buffer layer. Appl. Phys. Lett. 70:3224–3226, 1997. 40. CS Peng, ZY Zhao, H Chen, JH Li, YK Li, DY Dai, Q Huang, JM Zhou, YH Zhang, TT Sheng, and CH Tung. Relaxed Ge0.9Si0.1 alloy layers with low threading dislocation densities grown on lowtemperature Si buffers. Appl. Phys. Lett. 72:3160–3162, 1998. 41. L Colace, G Masini, F Galluzzi, G Assanto, G Capellini, L Di Gaspare, and F Evangelisti. Ge/Si(1 0 0) photodetector for near infrared light. Solid State Phenom. 54:55–57, 1997. 42. HC Luan, DR Lim, KK Lee, KM Chen, JG Sandland, K Wada, and LC Kimerling. High-quality Ge epilayers on Si with low threading-dislocation densities. Appl. Phys. Lett. 75:2909–2911, 1999. 43. L Colace, G Masini, F Galluzzi, and G Assanto. Evaporated polycrystalline germanium for near infrared photodetection. Proc MRS Fall Meeting, Boston, 1998, pp. 469–475. 44. G Masini, L Colace, and G Assanto. Advances in the field of poly-Ge on Si near infrared photodetectors. Mater. Sci. Eng. B 69:257–260, 2000. 45. L Colace, G Masini, and G Assanto. Ge-on-Si approaches to the detection of near infrared light. IEEE J. Quantum Electron. 35:1843–1852, 1999. 46. G Masini, L Colace, and G Assanto. Germanium thin film on silicon for detection of near-infrared light. In HS Nalwa, ed. Handbook of Thin Film Materials. New York: Academic Press, 2002, pp. 327–367. 47. GK Wertheim and GL Pearson. Recombination in plastically deformed germanium. Phys. Rev. 107:694–698, 1957. 48. PN Grillot, SA Ringel, EA Fitzgerald, GP Watson, and YH Xie. Electron trapping kinetics at dislocations in relaxed GeSi/Si heterostructures. J. Appl. Phys. 77:3248–3256, 1995. 49. FM Ross, R Hull, D Bahnck, JC Bean, LJ Perticolas, and CA King. Changes in electrical devices characteristics during the in situ formation of dislocations. Appl. Phys. Lett. 62:1426–1428, 1993. 50. LM Giovane, HC Luan, AM Agarwal, and LC Kimerling. Correlation between leakage current density and threading dislocation density in SiGe pin diodes grown on relaxed graded buffer layers. Appl. Phys. Lett. 78:541–543, 2001.

© 2006 by Taylor & Francis Group, LLC

Near-Infrared Detectors

7.3-749

51. G Masini, L Colace, G Assanto, HC Luan, K Wada, and LC Kimerling. High performance p–i–n Ge on Si photodetectors for the near infrared: from model to demonstration. IEEE Trans. Electron. Dev. 48:1092–1096, 2001. 52. L Colace, G Masini, G Assanto, HC Luan, K Wada, and LC Kimerling. Efficient high-speed nearinfrared Ge photodetectors integrated on Si substrates. Appl. Phys. Lett. 76:1231–1233, 2000. 53. V Chu, JP Conde, S Shen, and S Wagner. Photocurrent collection in a Schottky barrier on an amorphous silicon–germanium alloy structure with 1.23 eV optical gap. Appl. Phys. Lett. 55:262–264, 1989. 54. H Temkin, TP Pearsall, JC Bean, RA Logan, and S Luryi. GexSi1x strained-layer superlattice waveguide photodetectors operating near 1.3 mm. Appl. Phys. Lett. 48:963–965, 1986. 55. S Luryi, TP Pearsall, H Temkin, and JC Bean. Waveguide infrared photodetectors on a silicon chip. IEEE Electron Dev. Lett. 7:104–107, 1986. 56. H Temkin, A Antreasyan, NA Olsson, TP Pearsall, and JC Bean. Ge0.6Si0.4 rib waveguide avalanche photodetector for 1.3 mm operation. Appl. Phys. Lett. 49:809–811, 1986. 57. TP Pearsall, J Bevk, LC Feldman, JM Bonar, and JP Mannaerts. Structurally induced optical transitions in Ge–Si superlattices. Phys. Rev. Lett. 58:729–732, 1987. 58. TP Pearsall, EA Beam, H Temkin, and JC Bean. Ge–Si/Si infrared zone folded superlattice detectors. Electron. Lett. 24:685–686, 1988. 59. B Jalali, L Naval, and AFJ Levi. Si-based receivers for optical data links. J. Lightwave Technol. 12:930– 935, 1994. 60. A Splett, T Zinke, K Petermann, E Kasper, H Kibbel, HJ Herzog, and H Presting. Integration of waveguides and photodetectors in SiGe for 1.3 mm operation. IEEE Photon. Technol. Lett. 6:59–61, 1994. 61. VP Kesan, PG May, E Bassous, and SS Iyer. Integrated waveguide photodetector using Si/SiGe multiple quantum wells for long wavelength applications. IEDM Techn. Dig. 637–639, 1990. 62. FY Huang, K Sakamoto, KL Wang, P Trinh, and B Jalali. Epitaxial SiGeC waveguide photodetector grown on Si substrate with response in the 1.3–1.55 mm wavelength range. IEEE Photon. Technol. Lett. 9:229–231, 1997. 63. B Li, G Li, E Liu, Z Jiang, J Qin, and X Wang. Monolithic integration of a SiGe/Si modulator and multiple quantum well photodetector for 1.55 mm operation. Appl. Phys. Lett. 73:3504–3506, 1998. 64. H Lafontaine, NL Rowell, and S Janz. Growth of undulating Si0.5Ge0.5 layers for photodetectors at lambda ¼ 1.55 mm. Appl. Phys. Lett. 72:2430–2432, 1998. 65. S Janz, JM Baribeau, DJ Lockwood, JP McCaffrey, S Moisa, NL Rowell, DX Xu, H Lafontaine, and MRT Pearson. Si/SiGe photodetectors using three-dimensional growth modes to enhance photoresponse at l ¼ 1550 nm. J. Vac. Sci. Technol. 18:588–592, 2000. 66. T Tashiro, T Tatsumi, M Sujiyama, T Hashimoto, and T Morikawa. IEEE Trans. Electron Dev. 44:545–549, 1997. 67. DD Cannon, J Liu, Y Ishikawa, K Wada, DT Danielson, S Jongthammanurak, J Michel, and LC Kimerling. Tensile strained epitaxial Ge films on Si (1 0 0) substrates with potential application in L-band telecommunications. Appl. Phys. Lett. 84:906–908, 2004. 68. A Kastalsky, S Luryi, JC Bean, and TT Sheng. Single-crystal Ge/Si infraredphotodetector for fiber optics communications. Proc. Electrochem. Soc. PV85-7:406–411, 1985. 69. P Sutter, U Kafader, and H von Ka¨nel. Thin film photodetectors grown epitaxially on silicon. Solar Energy Mater. Solar Cells 31:541–547, 1994. 70. FY Huang, X Zhu, MO Tanner, and KL Wang. Normal-incidence strained-layer superlattice Ge0.5Si0.5/Si photodiodes near 1.3 mm. Appl. Phys. Lett. 67:566–568, 1995. 71. FY Huang and KL Wang. Normal-incidence epitaxial SiGeC photodetector near 1.3 mm wavelength grown on Si substrate. Appl. Phys. Lett. 69:2330–2232, 1996. 72. X Shao, SL Rommel, BA Orner, H Feng, MW Dashiell, RT Troeger, J Kolodzey, PR Berger, and T Laursen. 1.3 mm photoresponsivity in Si-based GeC photodiodes. Appl. Phys. Lett. 72:1860–1862, 1998.

© 2006 by Taylor & Francis Group, LLC

7.3-750

The Silicon Heterostructure Handbook

73. C Li, Q Yang, H Wang, J Zhu, L Luo, J Yu, and Q Wang. SiGe/Si resonant cavity enhanced photodetectors with a silicon on oxide reflector operating near 1.3 mm. Appl. Phys. Lett. 77:157– 159, 2000. 74. O Dosunmu, MK Ernsley, DD Cannon, B Ghyselen, LC Kimerling, and S Unlu. Germanium on double-SOI photodetectors for 1550 nm operation. Proc. of the IEEE-LEOS 16th Ann. Meet., Vol. 2, 2003, pp. 853–854. 75. L Colace, G Masini, F Galluzzi, G Assanto, G Capellini, L Di Gaspare, E Palange, and F Evangelisti. Metal–semiconductor–metal near-infrared light detector based on epitaxial Ge/Si. Appl. Phys. Lett. 72:3175–3177, 1998. 76. D Buca, S Winnerl, S Lenk, S Mantl, and Ch Buchal. Metal–germanium–metal ultrafast infrared detectors. J. Appl. Phys. 92:7599–7605, 2002. 77. J Oh, JC Campbell, SG Thomas, S Bharatan, R Thoma, C Jasper, RE Jones, and TE Zirkle. Interdigitated Ge p–i–n photodetectors fabricated on a Si substrate using graded SiGe buffer layers. IEEE J. Quantum Electron. 38:1238–1241, 2002. 78. G Masini, L Colace, G Assanto, HC Luan, K Wada, and LC Kimerling. High responsivity near infrared Ge photodetectors integrated on Si. Electron. Lett. 35:1467–1468, 1999. 79. G Masini, L Colace, G Assanto, HC Luan, and LC Kimerling. Electron. Lett. 36:2095–2096, 2000. 80. S Fama`, L Colace, G Masini, G Assanto, and HC Luan. Appl. Phys. Lett. 81:586–588, 2002. 81. SB Samavedam, MT Currie, TA Langdo, and EA Fitzgerald. High quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers. Appl. Phys. Lett. 73:2125– 2127, 1998. 82. RL Jiang, ZY Lo, WM Chen, L Zang, SM Zhu, XB Liu, and XM Cheng. Normal-incidence SiGe/Si photodetectors with different buffer layers. J. Vac. Sci. Technol. B 18:1251–1253, 2000. 83. G Masini, L Colace, and G Assanto. 2.5 Gbit/s polycrystalline germanium-on-silicon photodetector operating from 1.3 to 1.55 mm. Appl. Phys. Lett. 82:2524–2526, 2003. 84. TP Pearsall. Silicon–germanium alloys and heterostructures: Optical and electronic properties. CRC Crit. Rev. Solid State Mater. Sci. 15:551–599, 1989. 85. G Masini, L Colace, and G Assanto. Si based optoelectronics for communications. Mater. Sci. Eng. B 89:2–9, 2002. 86. JS Rieh, D Klotzkin, O Qasaimeh, LH Lu, K Yang, LPB Katehi, P Bhattacharya, and ET Croke. Monolithically integrated SiGe/Si PIN-HBT front-end photoreceivers. IEEE Photon. Technol. Lett. 10:415–417, 1998. 87. G Masini, V Cencelli, L Colace, F DeNotaristefani, and G Assanto. Monolithic integration of nearinfrared Ge photodetectors with Si complementary metal–oxide–semiconductor readout electronics. Appl. Phys. Lett. 80:3268–3270, 2002.

© 2006 by Taylor & Francis Group, LLC

7.4 Si-Based Photonic Transistor Devices for Integrated Optoelectronics 7.4.1 7.4.2

Introduction............................................................... 7.4-751 Light Emitters ............................................................ 7.4-751 Si–SiGe–Si:Er Heterojunction Light-Emitting Transistors . Si–SiO2:Er MOS Emitters

Wei-Xin Ni and Anders Elfving Linko¨ping University

7.4.3

Photodetectors ........................................................... 7.4-754 1.3 to 1.5 mm Ge-Dot Phototransistors . 1.3 to 1.5 mm Ge-Dot FET Type Photodetectors . Ge-Dot FET-Type Mid–Far Infrared Photodetectors

7.4.1 Introduction It is known that, due to its indirect bandgap, Si is an optically inefficient material, although many efforts have been made in manipulating the materials in order to improve the efficiency. For example, by incorporating SiGe quantum well layers or self-assembled Ge dots in the Si structure, one can push the absorption edge into the wavelength range of 1.3 to 1.55 mm due to the reduced bandgap [1]. The basic optical properties cannot be improved, however, since the nature of the indirect bandgap remains for these materials. In this chapter, we give a summary of the efforts made using another approach, i.e., although the materials are not very efficient due to physical limitations, one can instead find new types of device solutions. Therefore, one can in a more optimized way use the material potential for fabrication of practically useful Si-based optoelectronics. In this context, three-terminal photonic devices, namely photonic transistors, are considered. In the following sections, we select several examples to demonstrate how three-terminal transistors can be implemented for such a purpose of integrated optoelectronics.

7.4.2 Light Emitters It is of high interest for achieving efficient Si-based light emitters, which are the key components for realizing all Si-based optoelectronics, but presently are still unavailable. Er3þ ions can emit near infrared light at 1.54 mm at room temperature when incorporated together with oxygen in Si. Transistor solutions implemented for the Si:Er emitters are mainly motivated for an efficient pumping mechanism of Er excitation. Hot electron injectors have been studied using both bipolar and MOS transistors.

7.4-751 © 2006 by Taylor & Francis Group, LLC

7.4-752

The Silicon Heterostructure Handbook

Si–SiGe–Si:Er Heterojunction Light-Emitting Transistors As established, Er emission at 1.54 mm is due to an intra-4f transition of Er3þ ions. Different from the optical or electrical pumping mode in Si for emitting light directly via interband recombination, excitation of the Er-doped Si system is a process of energy transfer from carriers to Er ions. There exist two main excitation processes of Er3þ ions: (i) excitation by electron–hole recombination-mediated energy transfer at an Er-related defect level, in cases of a forward biased p–n junction [2] or carrier generation due to laser irradiation; and (ii) hot carrier direct impact excitation in case of a reverse biased p–n junction [3–6]. However, since the spontaneous radiative decay time of Er ions is very long (1 msec) [7], nonradiative de-excitation processes strongly compete with the radiative decay, causing a significant reduction of the luminescence intensity. For the reverse biased devices, although the thermally activated energy back transfer process at elevated temperatures can be suppressed [3, 4], the Auger de-excitation induced by the excess free carriers (because of Er and O dopants) as well as injected carriers may set a limit on high luminescence intensity. The high density of electrons and holes could be generated by hot electron impact ionization of the Si matrix [5]. Therefore, Er excitation would never be efficient if the device is operating in the avalanche breakdown regime. Consequently, there is a necessary tradeoff when controlling the electron kinetic energy for impact excitation while avoiding avalanche breakdown, which is however a difficult task to realize in a conventional diode structure. It has been impossible to de-couple the effects of two correlated variables, i.e., the applied voltage and the injection current. SiGe–Si:Er heterojunction light transistors containing a thin SiGe base layer and an Er-doped active layer in the collector were thus studied [5, 7], aiming at achieving high electrical pumping efficiency for Er excitation. In these devices, one can in a controlled way introduce hot electrons from the transistor emitter with a collector bias voltage below avalanche breakdown for improved impact excitation efficiency. The SiGe–Si:Er light-emitting transistors were fabricated using an emitter-down structure (as schematically shown in Figure 7.4.1). The layer structures were grown through the pre-patterned oxide windows by differential molecular beam epitaxy (MBE) [5] for achieving a freestanding external base contact. Er ions together with oxygen, supplied by sublimation of Er and SiO during the MBE growth, were incorporated in the B–C junction with the area aligned to the emitter, which permits all incorporated Er ions to be electronically pumped by injecting hot electrons from the emitter. SiGe–Si:Er HBTs are typically operated with the common-emitter configuration. Intense electroluminescence (EL) was observed from Er-doped HBTs measured at low injection current (0.17 A/cm2) for two base layer thicknesses (Figure 7.4.2). The determined impact excitation cross section was 5 1015 cm2, which was a 50-fold increase compared to the values reported from conventional diode structures. The external quantum efficiency was 1.5 104, which was increased due to an efficient excitation process with a controlled acceleration condition avoiding impact ionization [7]. The HBT-type Si–SiGe–Si:Er:O light-emitting devices are also a useful tool for studying the excitation and de-excitation mechanisms, since the device is able to separately control the applied bias across the B–C junction (the hot electron acceleration field), and the injection current density (the electron flux) during an impact excitation process. The influence of the Auger effect due to carriers from ionized dopants on the EL intensity was clearly revealed by the EL decay measurements on the SiGe–Si:Er:O-HBT [7]. Under common-emitter configuration, a long 1/e decay time (e.g., 190 msec for Ic ¼ 1.2 mA) was measured, when applying a DC bias (marked as 5-5 V in Figure 7.4.3) across C–E for the electron acceleration. However, the measured decay time decreased to 4 msec, when Vce was only applied in pulses synchronized with the Vbe pulses. A longer decay time constant observed in the former case is due to suppression of the Auger effect because of carrier depletion in the space–charge region under the constant bias. When Vce and Vbe were switchedoff simultaneously, the excited Er ions are quickly embedded in a region where the carriers due to dopant ionization act as de-excitation centers via an Auger transfer process, thus causing a fast decay. The understanding of the Auger carrier effect is crucial for an efficient Si:Er emitter.

© 2006 by Taylor & Francis Group, LLC

Si-Based Photonic Transistor Devices for Integrated Optoelectronics

7.4-753

c b n-Si e Si:Er:O

Al

p-SiGe n-Si

SiO2

n+− Si substrate (a)

(b)

FIGURE 7.4.1 (a) A schematic cross section and (b) an SEM micrograph of the SiGe/Si:Er:O HBT-type lightemitting device prepared by differential MBE.

EL intensity (a.u.)

SiGe:Er-HBTs EL at 298 K Idri = 0.6 mA

HBT−4,VCE = 3.4 V

HBT−1, VCE = 4.5 V

1000

1200 1400 1600 Wavelength (nm)

1800

FIGURE 7.4.2 EL spectra measured at 300 K from SiGe–Si:Er:O-HBTs with the base thickness of 50 nm (HBT-1) and 30 nm (HBT-4), respectively, with a very low driving current.

© 2006 by Taylor & Francis Group, LLC

7.4-754

The Silicon Heterostructure Handbook

Normalized EL intensity

1 Si/SiGe/Si:Er:O HBT RT, 1.2 mA 5-5 V, 190 µs

5-0 V, 5 µs

0.1

0

200

400 Time (µs)

600

800

FIGURE 7.4.3 EL decay curves measured with two different bias conditions across the B–C junction.

Si–SiO2:Er MOS Emitters Er3þ ions can be very efficiently excited when incorporating them in a SiO2 layer using hot-electrons injected from the poly-Si gate contact. Since the material systems used for these types of devices are not single crystalline, it will thus not be discussed in this chapter. Some detailed descriptions can be found in Ref. [8] for those who are interested.

7.4.3 Photodetectors The interesting wavelengths for the Si-based detector devices are mainly in the near-infrared range (e.g., 1.3 to 1.55 mm, for possible applications in optical links and chip optical interconnects, etc.), and the mid/far infrared range (3 to 20 mm, for environment monitoring, thermal imaging and night vision, etc.). SiGe-based heterojunction material systems are widely studied for these purposes.

1.3 to 1.5 mm Ge-Dot Phototransistors The idea of the phototransistor was proposed already by Shockley et al. in 1951 [9], and the working principle was discussed in detail in Ref. [10]. For this type of detector, electron–hole pairs, generated by photoionization due to the illuminating light beam with the energy larger than the semiconductor bandgap, are separated by an applied reverse bias across the B–C junction. The holes move and contribute to the base current, which then facilitate the injection of electrons from the emitter to collector resulting in current gain, i.e., the primary photocurrent is amplified through the transistor. High-performance phototransistors had been made using heterojunction materials. A successful example was the InP-based double heterojunction phototransistor with optical-gain cutoff frequencies of up to 135 GHz [11]. In 2002, Elfving et al. reported growth and characterization of the first phototransistor fabricated using the Si–SiGe material system [12–14], in which multiple Ge dot layers were incorporated in the B–C junction region using MBE. In this case, electron–hole pairs only generated in the base and collector with the SiGe layer and the islands by the infrared radiation below the Si bandgap, but not in the E–B junction. The optically controlled I–V characteristics of such a Ge-dot phototransistor are depicted in Figure 7.4.4. As shown in the figures, the device revealed a very low dark current, 0.01 mA/cm2 at 2 V [14]. A strong light modulation effect was observed, i.e., the collector current Ic was drastically increased when increasing the light power, which is similar to the case when changing the base current Ib. For the

© 2006 by Taylor & Francis Group, LLC

7.4-755

Si-Based Photonic Transistor Devices for Integrated Optoelectronics

6⫻10−4 Normal incidence, 850 nm T = 298 K

4⫻10−4

Current (A)

2⫻10−4 0 mW 0⫻100 0.06 mW

−2⫻10−4

0.13 mW −4⫻10−4 OP = 0.2 mW

−6⫻10−4

−2

−4

(a)

0

2

4

Applied bias (V)

1.5

Normal incidence, 1.31µm T = 298 k

Current density (mA/cm2)

1 0.5 0

0 mW

−0.5

0.3 mW

−1 −1.5

0.6 mW 0.9 mW 1.2 mW

−2 OP = 1.5 mW −5 (b)

−4

−3

−2 −1 0 Applied bias (V)

1

2

FIGURE 7.4.4 Optically controlled I–V characteristics of a Ge-dot HBT with laser illumination at different optical power at (a) 850 nm and (b) 1.31 mm. The light modulation effect was observed only in the reverse bias direction at 1.31 mm.

experiments using a 850 nm wavelength radiation source, such an effect was observed at both bias directions, but at 1.31 mm the light modulation only occurred when the Ge dot containing B–C junction was reverse biased (Figure 7.4.4(b)) while the E–B junction became photoinsensitive. This is a natural effect, because in this case Si is completely transparent for the incident infrared light, such that there is no generation of photocarriers in Si, which may bring an advantage for the low noise performance of light detection. These Ge-dot phototransistors were measured with very high photoresponse [13], which were 2.5 A/W at 850 nm (normal incidence, an apparent external quantum efficiency value of 350 % at this wavelength), 0.5 A/W (waveguide) at 1.31 mm, and 25 mA/W (waveguide) at 1.55 mm, respectively, at a bias condition of 4 V. These values are significantly higher compared to the measured

© 2006 by Taylor & Francis Group, LLC

7.4-756

The Silicon Heterostructure Handbook

2.5

0 Rotative response (dB)

1V 2V 3V

Pulse response (mv)

2.0

550 MHz

−3

1.2 GHz

−4 −9 −12

1.5

10 16 Frequency (GHz)

3V: Rise: 64 ps Fall: 442 ps FWHM: 184 ps

1.0

0.5

2

3 Time (n s)

4

5

FIGURE 7.4.5 Pulse response of SiGe HPT at 850-nm and 50-psec pulse laser illumination with the applied voltages of 1, 2, and 3 V, respectively.

photoresponse obtained from reference p–i–n photodiodes with an identical Ge dot layer structure in the intrinsic region. Pei et al. showed that the cutoff frequency (fT) and maximum oscillation frequency (fmax) of the SiGe– Si-MQWs phototransistor were found to be 25 GHz [15], which is thus suitable for gigabit integrated circuits. In particular, the transient responsivity with the pulsewidth of 184 psec (the rise time of 64 psec and fall time of 442 psec) at a wavelength of 850 nm was observed (Figure 7.4.5), in spite of the fast falling of the ac response at the level of the 6-dB bandwidth at 1.2 GHz. All of the above observed features indicate that Si–SiGe-based phototransistors have excellent electrical and optical performance, which are thus attractive for future Si-based optoelectronic integrated circuit applications.

1.3 to 1.5 mm Ge-Dot FET Type Photodetectors The optically controlled field-effect transistors (FET) can also generate high photoresponse, which has attracted a great deal of attention to be used as sensitive detectors. Furthermore, the FET phototransistors can be easily used, for example, mixing of a microwave signal with an optically coupled local oscillator signal for oscillator tuning, etc. The principle of using the FET as a photodetector is very straightforward. The measured photocurrent depends on the lateral carrier transport, according to the following equation: IDS /

W mns L

where L is the conducting channel length (the source-to-drain distance) and W is the channel width, m is the carrier mobility, and ns is the number of charges in the conduction channel. For an undoped structure, ns is determined by the photoionization cross section and the efficiency of carrier transfer into

© 2006 by Taylor & Francis Group, LLC

7.4-757

Si-Based Photonic Transistor Devices for Integrated Optoelectronics

the conduction channel, which can be controlled by the top gate. The equation thus tells us that the primary photogenerated carries can yield a larger effect of the eventually measured IDS, due to the gain factor determined by the device design. Several types of FET photodetectors (MESFET or HEMT) were studied using III–V materials, and showed excellence performance. At the 0.6 mm wavelength range, Khalid and Rezazadeh reported that the DC photoresponsivity of GaAs MESFETs was about 4.5 A/W [16], and pulse responses with a FWHM value of 22 psec. By using an InP–InGaAs HEMT structure with semitransparent meander shaped gate (ITO), Marso et al. reported a very high DC photoresponse of 15.4/W [17], and pulse response with a FWHM of 90 nsec at 1.3 mm wavelength. RF measurements were also carried out with a frequency limit up to 20 GHz. Studies on SiGe-based FET type detectors have just been initiated, however, but the results are still very promising and may lead to some interesting applications. Elfving et al. recently reported a SiGe-QW–Gedot HEMT photodetector operating at 1.3 to 1.55 mm [18]. For this detector, Ge dots were used as the absorption medium to push the cutoff wavelength into the interesting 1.55 mm regime. However, in-plane current transport, namely IDS, is limited by the discrete distribution of the Ge islands and the very thin wetting layer. To solve the problem, SiGe quantum wells (QWs) were placed next to the dot layers to serve as the high mobility channel when the photogenerated carried can be transferred from the dots to the wells. Ten periods of SiGe(6 nm)/Si(10 nm)/Ge(8 monolayers)/Si(60 nm) multiple stacks were grown at 6008C using MBE, and the detectors were processed using a multi-finger mesa design with Al source and drain contacts connected to the side edge of the mesas, which is shown in Figure 7.4.6. Pt was used as gate material to create a Schottky-contact. Some preliminary experimental results based on normal incidence measurements (200 mm in diameter shinning area) showed that the responsivity was about four times higher than that observed from 0.85 at VDS the reference sample without SiGe QWs. The increase of the photocurrent is proportional to Pop ¼ 5 V (Figure 7.4.7), indicating an efficient photocarrier transfer process from the Ge QDs into the SiGe QWs. The effect of the gate bias has been studied using the broadband light source with a long pass filter ranging >1.1 mm. Figure 7.4.8 shows the dark current and photocurrent measured at VG ¼ 0 and 2 V. With no incident photons, the dark current was small and almost independent of the gate voltage. The photoresponsivity was >200 mA/W at VDS ¼ 2.5 V and VG ¼ 2 V. Even though one can observe some gate leakage, the photocurrent can be modulated with VG when near infrared photons are incident on to the transistors. By switching the direction of VG, the detectors can quickly be switched between onand off-state, with a decay or rise time of 300 nsec (not shown), which was actually limited by the bandwidth of the experimental instruments.

Ge-Dot FET-Type Mid–Far Infrared Photodetectors Similar ideas to that described in Section 3.2 can be used to fabricate photodetectors operating in the mid/far-infrared range. The main difference is that the dots must be doped, so that intersubband photoexcitation is responsible for generating photo-carriers for detection.

QD QW

G

S

D

FIGURE 7.4.6 Schematic drawing of the device cross section.

© 2006 by Taylor & Francis Group, LLC

S

7.4-758

The Silicon Heterostructure Handbook

Photocurrent (a.u.)

Normal incidence at 1.31 µm VG = 0 V V DS = 5 V I DS~Pop0.85 1 0.8 0.6

0.4

0.2 0.01

0.1 P op(mW)

1

FIGURE 7.4.7 The photocurrent as a function of the incident optical power for the SiGe-QW–Ge-dot photoMESFET.

0

Dark, VG = 0 V Dark, VG = 1 V

ID (A)

Light, VG = 0 V

−1⫻10−5 Light, VG = 2 V

−4

−3

−2 −1 V DS (V)

0

1

FIGURE 7.4.8 I–V characteristics of a MEFET photodetector with Pt gate contact. With light incident to the detector, current modulation was observed while the dark current was weakly dependent on VG.

Most mid/far-infrared photodetectors were made in a conventional way that is based on intersubband transitions within the quantum well or self-assembled quantum dots, i.e., carriers within the wells or dots are first excited by incident photons from the ground state to the excited states or the continuous band, and subsequently measured as photoenhanced conductivity when these carriers are moved out from the wells and transported along the direction perpendicular to the potential wells [19]. Several physical limitations are, however, imposed for this type of vertical transport photodetector. First, the detection, which relied on removal of the excited carriers from the potential well for transport in the continuous band, suffers from thermal excitation, therefore conducting a large dark current at elevated temperatures. The smaller the transition energy, which is required for detection at longer

© 2006 by Taylor & Francis Group, LLC

7.4-759

Si-Based Photonic Transistor Devices for Integrated Optoelectronics

wavelengths, the more severe the effect. Therefore, there is a tradeoff between the operation wavelength and temperature. Furthermore, during carrier transport there is a large probability that excited carriers can fall into the successive potential well, i.e., the so-called re-trapping mechanism, which limits the detection quantum efficiency. In 2002, Bougeard et al. [20] demonstrated a novel approach on measuring the photoresponse of structures based on in-plane transport of holes photoexcited from self-assembled Ge dots in Si. As seen in Figure 7.4.9, the devices showed broad spectral response ranging from about 2 to 4:75 mm with a maximum around 3 mm. The addition of SiGe-QWs as conductive channels increased the photoresponse up to about 90 mA/W at 20 K, which was about 50 times better compared to the reference without using SiGe QWs. Adnane et al. at Linko¨ping have further developed this idea to manufacture Ge-dot-based detectors using an FET structure [21]. In these structures, one uses the larger dot size to allow detection at a longer wavelength (small transition energy), while deep trapping of photoexcited holes in the dot well with high thermal barrier may ensure a low dark current. The eventually measured source–drain current is determined by charge transfer via either the tunnelling or thermal excitation process, triggered by an emission field provided from the gate, from the discrete dots to a SiGe two-dimensional QW placed close to each dot layer as conducting channel, and would be amplified due to the geometrical design factor (W/L ratio) and the mobility in the channel. The photoconductivity measurements were performed at 20 K using a glow-bar infrared light source in combination with different beam splitters forming the bandwidth in two ranges, i.e., 1.5 to 6 mm (CaF2) and 3 to 15 mm (KBr). Some experimental results are summarized in Figure 7.4.10. As revealed in Figure 10(a), the FET detectors showed a very low dark current. The photoresponse was evidently observed when shining the device with the various bandwidths of infrared radiation. Much more pronounced photoconductivity was observed from the multifinger sample (Figure 10(b)), and a photoresponsivity value of 100 mA/W was observed with a broadband source at 3 to 15 mm. In summary, although the structures of transistor devices are often more complex than conventional two terminal diodes, with the implementation of the natural transistor function, one can fabricate devices with much improved photonic performance compared to the simple solutions. This has been seen in terms of both photoresponse and frequency–speed properties. The technologies used for

4.5 4 3.5

3

Wavelength (µm) 2.5 2

1.5

1.2 T = 20 K Bias voltage = 1 V

Photocurrent (a.u.)

1.0

Si75Ge25-QW 10 Ge-dot and SiGe-QW layers

0.8 0.6 0.4 0.2

Without SiGe-QW (⫻ 10) 10 Ge-dot-layers

0.0 300

400

500 600 700 Energy (meV)

800

900

FIGURE 7.4.9 Photoconductivity spectra of a Si–Ge–Si–SiGe multilayer structure and a reference sample containing no SiGe QWs.

© 2006 by Taylor & Francis Group, LLC

7.4-760

The Silicon Heterostructure Handbook

1⫻10−9

Photocurrent (A)

8⫻10−10 2 mm

6⫻10−10

1.5-6 µm

4⫻10−10 2⫻10−10

3-15 µm 0 Dark current −1

−0.5

(a)

0 0.5 Bias voltage (V)

1

10−4

Photocurrent (A)

10−5

10−6

10−7

10−8 −4 (b)

−3

−2

−1 0 1 Bias voltage (V)

2

3

4

FIGURE 7.4.10 I–V characteristics with or without infrared radiation at various band widths were measured from two detectors (a) W/L ¼ 2 and (b) W/L ¼ 3000, at T ¼ 20 K.

fabrication of Si-based photonic transistor devices are totally compatible with the mainstream Si technology for integration circuits. Therefore, we anticipate that further studies along this direction may bring more interesting and practically useful results toward Si-based optoelectronics.

References 1. K. Brunner. Rep. Prog. Phys. 65, 27 (2002). 2. B. Zheng, J. Michel, F.Y.G. Ren, L.C. Kimerling, D.C. Jacobson, and J.M. Poate. Appl. Phys. Lett. 64, 2842 (1994). 3. G. Franzo`, F. Priolo, S. Coffa, A. Polman, and A. Carnera. Appl. Phys. Lett. 64, 2235 (1994). 4. J. Stimmer, A. Reittinger, J.F. Nu¨tzel, G. Abstreiter, H. Holzbrecher, and CH. Buchal. Appl. Phys. Lett. 68, 3290 (1996).

© 2006 by Taylor & Francis Group, LLC

Si-Based Photonic Transistor Devices for Integrated Optoelectronics

7.4-761

5. C.-X. Du, F. Duteil, G.V. Hansson, A. Elfving, and W.-X. Ni. Appl. Phys. Lett. 78, 1697 (2001). 6. N.A. Sobolev, A.M. Emel’Yanov, S.V. Gastev, P.E. Khakuashev, Yu.A. Niklaev, and M.A. Trishenkov. In Materials and Devices for Silicon-based Optoelectronics, Mat. Res. Soc. Symp. Proc., Vol. 486. Warrendale, Pennsylvania, 1998, p. 139. 7. W.-X. Ni, C.-X. Du, G.V. Hansson, A. Elfving, A. Vo¨rckel, and Y. Fu. In ‘‘Towards the First Si Laser’’ NATO Advanced Research Series, L. Pavisi et al., eds. Kluwer Academic Publishers, The Netherland, 2003, pp. 429–444. 8. D. Pacifici, A. Irrera, G. Franz, M. Miritell, F. Iacona, and F. Priolo. Phys. E 16, 331 (2003). 9. W. Shockley, M. Sparks, and G.K. Teal. Phys. Rev. 83, 151 (1951). 10. S.M. Sze. In Physics of Semiconductor Devices. John Wiley & Sons, New York, 1981, pp. 783–786. 11. A. Leven, V. Houtsma, R. Kopf, Y. Baeyens, and Y.-K. Chen. In The Proceedings of IEEE International Microwave Symposium, Philadelphia, June 8–13, 2003. 12. A. Elfving, G.V. Hansson, and W.-X. Ni. Phys. E 16, 528 (2003). 13. A. Elfving, M. Larsson, P.O. Holtz, G.V. Hansson, and W.-X. Ni. In The MRS Proc. 770, I2.2 (2003). 14. W.-X. Ni, A. Elfving, M. Larsson, G.V. Hansson and P.-O. Holtz. In The Proceedings of the Third International Conference on SiGe(C) Epitaxy and Heterostructures, Santa Fe, March 9–12, 2003, pp. 251–254. 15. Z.W. Pei, C.S. Liang, L.S. Lai, Y.T. Tseng, Y.M. Hsu, P.S. Chen, S.C. Lu, M.-J. Tsai, and C.W. Liu. IEEE Electron Dev. Lett. 24, 643 (2003). 16. A.H. Khalid and A.A. Rezazadeh. IEE Proc. Optoelectron Vil. 143, 7 (1996). 17. M. Marso, M. Horstmann, H. Hardsdegen, and P. Kordos. Solid-State Electron. 42, 197 (1998). 18. A. Elfving, G.V. Hansson, and W.-X. Ni. Extended abstract accepted by The First IEEE International Conference on Group-IV Photonics. Hong Kong, September 28–October 1, 2004. 19. J. Phillips, K. Kamath, and P. Bhattacharya. Appl. Phys. Lett. 72, 2020 (1998). 20. D. Bougeard, K. Brunner, and G. Abstreiter. Phys. E 16, 609 (2003). 21. B. Adnane, A. Elfving, M. Zhao, M. Larsson, B. Magnuson, and W.-X. Ni. Extended abstract accepted by The First IEEE International Conference on Group-IV Photonics, Hongkong, September 28–October 1, 2004.

© 2006 by Taylor & Francis Group, LLC

7.5 Si–SiGe Quantum Cascade Emitters 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5

Douglas J. Paul University of Cambridge

7.5.6 7.5.7

Introduction............................................................... 7.5-763 Population Inversion and Gain................................ 7.5-763 Subband Lifetimes..................................................... 7.5-766 Impurity Electroluminescence.................................. 7.5-768 Electroluminescence from Quantum Cascade Emitters ....................................................... 7.5-769 Si–SiGe Quantum Cascade Lasers ........................... 7.5-771 Summary .................................................................... 7.5-773

7.5.1 Introduction The major problem in silicon optoelectronics is the lack of a laser or efficient electroluminescent device. There have been many attempts to realize silicon-based lasers including porous silicon, erbium-doped silicon, and SiGe along with silicon nanocrystals [1, 2]. The indirect bandgap of silicon precludes the efficient recombination of electrons and holes, which to date has prevented the realization of an interband laser. The quantum cascade laser (QCL) [3–5] is a unipolar laser utilizing intersubband transitions, and therefore, can be applied both to direct and indirect materials systems such as silicon. QCLs were originally proposed in 1971 [6] but the first experimental realization did not happen until 1994 using GaInAs and AlInAs heterostructures [7]. In particular for far-infrared or terahertz applications where no practical semiconductor materials exist with appropriate bandgaps, the potential for use in applications is high [8]. Potential terahertz applications include medical and dental imaging (for instance skin cancer detection) [8], security imaging [9], molecular spectroscopy, and bioweapons detection [10]. QCLs were first demonstrated at mid-infrared wavelengths [7] and more recently there have been a number of far-infrared demonstrations [11].

7.5.2 Population Inversion and Gain The QCL principle relies on the intersubband emission of a photon (Figure 7.5.1) with the upper laser state designed to have population inversion by engineering the lifetime using bandgap engineering and subband lifetime engineering [3–5]. To date all demonstrated Si–SiGe quantum cascade emitters have been demonstrated using holes in the valence band. This is predominantly related to the heavy electron effective mass (m* 0.918m0 [12] where m0 is the free electron mass) in the tunneling direction of the conduction band of Si or Si1xGex (x < 0.85). The m* in the transport direction of a tensile strained-Si quantum well is the lower 0.197m0 [12], which does not vary significantly with strain but this cannot be used for tunneling through quantum mechanical barriers grown on (0 0 1) substrates. A SiGe electron cascade device would require extremely thin tunnel barriers if miniband or efficient injection is to be attempted. Holes on the other hand have significantly smaller m*, typically all well below 0.5m0, which 7.5-763 © 2006 by Taylor & Francis Group, LLC

7.5-764

The Silicon Heterostructure Handbook

Ec h ν = E2−E1

Miniband e−

E2

Miniband

E1

Injector

e−

E0

Emitter transition region

E2

Miniband

E1

Injector

E

e−

E2

0

Emitter transition region

E1

Injector

E0

FIGURE 7.5.1 A schematic diagram of the conduction band of a quantum cascade laser. This particular design uses the E2 subband state as the upper radiative transition level and the E1 state as the lower. The energy between E1 and the ground state of the quantum well, E0 is set to the optical phonon energy so that the lower laser level has fast, nonradiative depopulation. This particular design uses a miniband injector using six quantum wells and three cascade periods are shown.

can also be engineering with strain. The light-hole m* of pure Ge is only 0.044m0, which is lower than the electron m* of GaAs. The strain also splits the light-hole and heavy-hole band degeneracy at k ¼ 0. This significantly relaxes the growth requirements to achieve minibands or tunneling. To allow large numbers of strained layers to be grown coherently to a substrate well above the total critical thickness [13], quantum wells and tunnel barriers must be strain-symmetrized with alternating (and balanced) compressive and tensile strain, respectively (Figure 7.5.2). This, therefore, requires the layers to be latticed matched to a relaxed Si1yGey virtual substrate. The valence band discontinuities are also typically larger for the valence band compared to the conduction band when amenable virtual substrate germanium contents are considered (Figure 7.5.2). The active heterostructure region of a QCL is where the population inversion and gain takes place. Figure 7.5.3 shows schematically a diagram of the subband energy levels of a three-level laser system, which are used to engineer population inversion. Electrons or holes are injected from an injector into the upper laser state, E3 with an injector efficiency of h3. The radiative transition is from level 3 to level 2 with the photon emission frequency given by v ¼ (E3 E2)/h where h is Planck’s constant. For population inversion assuming 100% injector efficiency into the E3 state and no nonparabolicity the condition is simply t32 > t2 where t321 is the nonradiative scattering rate from level 3 to level 2 and t21 is the total scattering rate out of level 2. In many designs this is achieved by fast depopulation of the lower laser state, E2 to a lower energy subband, E1 but any fast scattering or tunneling out of the lower laser state is beneficial if it reduces t2. In real quantum cascade active designs there are also scattering rates and unwanted injection into different levels, which decrease the gain in the system and require to be minimized. Injection from the injector to the lower laser state, E2 with efficiency h2 is clearly an unwanted process. Putting all these processes together, it can be demonstrated that the gain in the active region for a quantum cascade emitter is given by [14]

© 2006 by Taylor & Francis Group, LLC

7.5-765

Si–SiGe Quantum Cascade Emitters

1.0 00 50

0.8

−1

00

−1

0

0.6

−5

8

74

0 Barrier

2

22

6

29

0

37

0.2

4

44

51

8 2

59

66

Quantum well

6

0.4

14

Relaxed-Si1−y Gey substrate

−2

0.0 0.0

0.2

0.4

0.6

0.8

1.0

Strained-Si1−x Gex active layer

FIGURE 7.5.2 The valence band discontinuity of strained-Si1xGex layers grown on relaxed Si1y Gey virtual substrates in meV. (MM Rieger and P Vogl. Electronic-band parameters in strained Si1xGex alloys on Si1yGey substrates. Phys. Rev. B 48:14276–14287, 1993; Phys. Rev. B 50:8138, 1994. With permission.) Energy h3

Emission

t3

Injector

E3 t32

h2

t2 t21 E1

E2 tesc tesc

FIGURE 7.5.3 A schematic diagram of the energy levels in a quantum cascade laser along with the injection efficiency into different levels (hx) and the lifetimes of states (tx), and transitions (txy).

Gain ¼ sDn ¼ s

J t2 t 3 h3 1 h2 t 2 q t 32

(7:5:1)

where s is the transition cross section, Dn is the population inversion between the E3 and E2 energy levels, J is the current density, and q is the electron charge. This equation demonstrates the importance of high injection efficiency into the upper laser state, h3, the requirement of t32 > t2 and the detrimental effects of injection into the lower laser state with efficiency h2. Figure 7.5.4 shows schematically four different designs for achieving population inversion in the active quantum cascade elements. Figure 7.5.4(a) shows a vertical radiative transition that uses a resonant LO optical phonon depopulation. The two lowest energy-hole subband states (that is higher up the page for the lowest hole energy) are set to be exactly the LO optical phonon energy apart. Therefore, transitions between the two states are fast and nonradiative providing fast depopulation of the lower radiative transition level, and therefore, population inversion can be attended in the upper energy level. If this technique is used for an intrawell cascade then it can only operate for energies above the optical phonon energy, which is 62 meV for silicon. An interwell or diagonal transitions is shown in Figure 7.5.4(b). Such structures are easier to engineering in population inversion but have reduced matrix element compared to vertical or intrawell optical transitions. Figure 7.5.4(c) uses a miniband injector and an optical transition between miniband states. Miniband transitions allow higher currents, which can be important

© 2006 by Taylor & Francis Group, LLC

7.5-766

The Silicon Heterostructure Handbook

(a)

(b)

Collector

Collector

ELO

Injector Injector Ev

hn

hole

Ev

Emitter transition (d)

(c)

Ev

miniband1

Ev miniband injector

miniband2

Energy

Emitter transition

Hole

hn

Hole

Collector

hn Hole

Emitter transition

k

hn

HH1

Injector LH1

FIGURE 7.5.4 Schematic diagrams of four methods of achieving population inversion in a SiGe hole QCL. (a) Resonant LO optical phonon depopulation, (b) interwell or diagonal transition, (c) interminiband transitions, and (d) negative effective mass structure.

for electrical pumping to produce linewidth narrowing followed by lasing. All the above three techniques have been used to produce QCLs in a number of materials in the III–Vs. The design in Figure 7.5.4(d) is radically different to those discussed above [15]. The structure requires only quantum wells with tunnel barriers between the quantum wells. Since holes can only tunnel between quantum wells at k ¼ 0 the structure is engineered to produce a radiative transition at finite k. This is achieved by bending the LH1 band upwards producing a negative effective mass. Since the selection rules forbid the LH1 and HH2 bands to cross, by trying to engineer the LH1 band to be higher in hole energy will result in an anticrossing with the HH2 state so that the LH1 band is forced to have a negative effective mass structure. The structure is engineered so that holes tunneling into the quantum well at k ¼ 0 where they are forbidden for transitions to the HH1 band. They are scattered by alloy or hole–hole scattering to the minima in k where a radiative transition is allowed before scattered by alloy or hole–hole scattering back to k ¼ 0 where they can tunnel to the next quantum well. The radiative transition requires to be engineered to be longer than the alloy or hole–hole scattering times so that population inversion can result. The problem with this structure in the Si–SiGe system is that while a negative effective mass can be produced at zero electric field, it is very weak when combined with strain symmetrization and can easily be removed by applying small electric fields. Unfortunately rather larger electric fields are required to align the suband states between wells to allow the holes to cascade.

7.5.3 Subband Lifetimes The lifetime of subbands is important as they will determine whether a particular heterostructure design can achieve population inversion. These lifetimes can be engineered in a number of different ways including through the control of the quantum mechanical tunneling of an electron or hole to or from other states along with making subband states resonant with LO optical phonon transitions. A long

© 2006 by Taylor & Francis Group, LLC

7.5-767

Si–SiGe Quantum Cascade Emitters

nonradiative lifetime (t32 in Figure 7.5.3) for the upper laser state is required, preferably much longer than the radiative lifetime. Below the optical phonon energy in silicon of 62 meV (14.9 THz), a Si–SiGe QCL has potentially many advantages over a III–V based laser. While mature and cheap silicon process technology suggests a cheaper product and silicon has a higher thermal conductivity than most III–Vs, more importantly for the subband lifetimes there is no polar optical phonon scattering in Group IV semiconductors. Polar optical phonon scattering through interactions with the electrical dipole in the molecular bonds of GaAs results in a substantial decrease in the nonradiative lifetimes (t32) at temperatures above about 40 K [16, 17]. Experiments in strained Si1xGex quantum wells have demonstrated almost constant nonradiative lifetimes (t32) of around 10 psec between 4 and 150 K for 24 meV transitions [18, 19]. Modeling of the results suggests that alloy scattering is the dominant scattering mechanism, which has a very weak temperature dependence unlike polar optical phonon scattering [19]. More recent measurements on electrically biased Si1xGex quantum cascade structures have demonstrated almost constant nonradiative lifetimes as long as 30 psec up to room temperature (Figure 7.5.5) [20, 21]. This demonstrates that group IV cascades have significant advantages over III–V devices below the optical phonon energy and should be able to operate at higher temperatures. For transitions above the optical phonon energy (62 meV for silicon and 37 meV for germanium), the nonradiative lifetime is substantially reduced. Experiments in strained Si1xGex quantum wells have demonstrated 250 fsec lifetimes for transitions of 167 meV [22]. One method of increasing the lifetime is to use an interwell transition and the lifetime can be increased up to about 10 psec by increasing the thickness of the barrier between the wells [23]. The disadvantage of this technique is that the optical matrix element for radiative transitions is reduced (that is the gain is reduced) as the barrier

0.05

4K 30 K

0.04

60 K

Transmission change (au)

100 K 150 K

0.03

200 K 250 K

0.02

300 K

0.01

0.00

−0.01

−0.02

0

100

200

300

Delay (psec)

FIGURE 7.5.5 Pump–probe measurements of the nonradiative lifetime of a LH1 to HH1 transition in a quantum cascade structure at 14 meV (about 3.4 THz or 89 mm) [20, 21].

© 2006 by Taylor & Francis Group, LLC

7.5-768

The Silicon Heterostructure Handbook

thickness is increased. A second technique is to use minibands [24] or coupled quantum wells [25] where the wave function spread over a number of quantum wells results in signficantly longer nonradiative lifetimes.

7.5.4 Impurity Electroluminescence The p-Ge laser uses crossed electric and magnetic fields to produce population inversion between the split hydrogen-like impurity states in the semiconductor [26]. The disadvantage of such a laser is that the large magnetic fields along with the 4 K operating temperature makes such lasers impractical for many applications. Figure 7.5.6 shows the electroluminescence by applying an electric field along ten boron modulation-doped Si0.72Ge0.28 quantum wells grown on top of a Si0.78Ge0.22 virtual substrate with strain-symmetrized Si barriers [19, 20]. Six-band kp theory predicted a broad spontaneous electroluminescent peak due to a large number of states in k-space available for radiative transitions. At 4 K, however, three very sharp features were observed, which correspond to boron impurity transitions at 30.4 meV (1s2p0), 34.5 meV (1s2p+ ), and 39.6 meV (1s3p0) [27, 28]. Only above 20 K is the impurity emission quenched and intersubband radiative transitions are observed. When the intersubband emission dominates, there is strong absorption at the impurity lines. The mechanism for this impurity emission is still not fully understood. For the impurity state lasers, magnetic fields are required to achieve sufficient splitting of the appropriate laser energy levels but no magnetic fields have been applied to the SiGe samples. This suggests that the strain must be involved at some level in splitting the impurity energy levels. Strain, however, will also shift the positions of the impurity lines in energy compared to bulk or relaxed Si or SiGe and yet the positions agree with absorption data on bulk silicon

Frequency (THz) 3.5

0

4

8

16

12

T=4K

Spectral power (a.u.)

3.0

T = 60 K Theory

2.5 2.0 1.5 1.0 0.5 0.0

0

10

20

30

40

50

60

70

80

Energy (meV)

FIGURE 7.5.6 The electroluminescence from modulation-doped Si0.7Ge0.3 quantum wells with the current applied along the quantum wells. (a) At 4 K boron impurity states emit and no intersubband radiative transitions are visible. (b) Heating the substrate to 60 K quenches the impurity transitions and the intersubband electroluminescence dominates with strong absorption at the impurity lines. The width of the transition agrees well with a sixband kp theory and is broad due to the large number of states in k-space over which radiative transitions are allowed [19, 20].

© 2006 by Taylor & Francis Group, LLC

7.5-769

Si–SiGe Quantum Cascade Emitters

wafers suggesting that no strain is involved. This strongly suggests that it is the relaxed p-Si0.78Ge0.22 supply layers, which are emitting and not the quantum wells. It does create a potential problem as while there is no forbidden Reststrahlen band in Group IV materials, for p-type Si or SiGe the impurities may create an energy region in which intersubband emission may be dominated by interactions with boron impurities.

7.5.5 Electroluminescence from Quantum Cascade Emitters All existing III–V QCLs have been n-type, and therefore, limited to only edge-emitting devices unless a grating is used to scatter or couple light out of the surface of the device. The optical matrix element is nonzero only for interactions with the electric field dipole that is oriented perpendicular to the quantum well layers (TM polarization), hence the emitted radiation can only propagate parallel to the quantum well resulting in edge emission. The use of light-hole to heavy-hole transitions results in a finite matrix element in the plane of the quantum wells resulting in a TE mode, thereby allowing surface-normal emission without a grating. The first Si–SiGe quantum cascade emitter was demonstrated at mid-infrared frequencies in 2000 [29] using intrawell HH2 to HH1 transitions. A diagonal or interwell HH2 to HH1 transition has also been demonstrated in the mid-infrared [30]. The major problem with these two demonstrations was that the structures were pseudomorphically grown on bulk silicon substrates, limiting the number of active periods. The first strain-symmetrized cascade was demonstrated at terahertz frequencies [31] using an intrawell LH1 to HH1 transition. As demonstrated in Figure 7.5.7, this was also the first surfacenormal emitting quantum cascade in any materials system since the LH1 to HH1 transition has a TE polarized component. The spontaneous emission peak in Figure 7.5.7 is significantly wider than comparable GaAs electron cascades, which is the result of a large number of allowed transitions for many different k-values. The nonparabolicity of the valence band will also broaden the transition. Strain-symmetrized mid-infrared quantum cascades using a bound-to-continuum transition have also been demonstrated [32]. Figure 7.5.8 shows a TEM image of the bottom periods of a strain-symmetrized interwell quantum cascade structure grown by CVD. This wafer has 600 periods of 6.5 nm Si0.7Ge0.3 quantum wells with 2 nm strained-Si barriers all grown on top of a Si0.8Ge0.2 virtual substrate. A 200 nm boron-doped

Surface-normal spectral power (a.u.)

Frequency (THz) 1.00

0

4

8

16

12

LH1-HH1

40 K 2.0 V 50% dutycycle

20

60

0.75

0.50

0.25

0.00

0

10

30 40 50 Energy (meV)

70

80

FIGURE 7.5.7 The surface-normal emission from an intrawell LH1 to HH1 transition electroluminescence in a 30-period quantum cascade structure [31]. The dashed line is 6 band kp theory.

© 2006 by Taylor & Francis Group, LLC

7.5-770

The Silicon Heterostructure Handbook

FIGURE 7.5.8 A TEM picture of the bottom of a stack of a 600 period strain-symmetrized quantum cascade emitter of total thickness 5 mm. Below the lowest quantum well is a graded SiGe injector (collector) and 200 nm of boron-doped Si0.8Ge0.2 as the bottom contact layer. Frequency (THz) 3.5

0

4

8

12

16

Edge emitted spectral power (a.u.)

impurity 3.0

HH1

2.5

LH1

HH1-LH1

HH1

2.0

LH1

1.5 Ev 1.0 0.5 0.0

0

10

20

30

40

50

60

70

80

Energy (meV)

FIGURE 7.5.9 An interwell HH1 to LH1 transition electroluminescence in a 100 period quantum cascade structure at 700 mA current with 5% duty cycle and 5 K [33]. The inset shows a schematic diagram of the HH1 to LH1 diagonal radiative transition.

Ohmic contact layer is grown below the quantum cascade structure and a thinner 40 nm doped layer on the top. Graded SiGe injectors (collectors) are also designed to inject holes into the correct subband when an electric field is placed across the device. Such structures are pushing the SiGe growth technology to new limits with the thin layers required for tunneling structures. The electroluminescence from a 100-period interwell (diagonal) transition is shown in Figure 7.5.9 [33]. The transition (see inset) is from the HH1 ground state in one quantum well to the LH1 state in the

© 2006 by Taylor & Francis Group, LLC

7.5-771

Si–SiGe Quantum Cascade Emitters

20

Peak energy (meV)

3.8 V 6.4 V

Intensity (a.u.)

15

10

8.0 7.0 6.0 5.0 4.0 5.0 6.0 Applied voltage (V)

5

0 0

2

4

6

8

10

12

14

16

18

20

Energy (meV)

FIGURE 7.5.10 The terahertz edge-emitted electroluminescence from an interwell HH1 to LH1 transition. The inset shows the movement of the peak as a function of the electrical bias [33].

adjacent well. By changing the voltage across the device the transition can be moved in energy (Figure 7.5.10). In addition to the intersubband electrolumninescence, this device also demonstrates emission from the impurity states mentioned above between 30 and 40 meV (Figure 7.5.9). The normal method of proving that the emission is intersubband rather than blackbody is to reverse the voltage demonstrating emission only when the subband levels are aligned. For symmetrical quantum well designs this cannot be achieved and measurement of the polarization along with a demonstration of a linear light output power as a function of current (blackbody is unpolarized with a power dependent on the square of the current) is required. Figure 7.5.11 plots the power outputs of the terahertz quantum cascade emitters as a function of frequency against the main compact devices available at these frequencies. As no calibration standard is available in the terahertz, the power levels have an error of up to an order of magnitude for devices emitting between 1 and 10 THz. All the quantum cascade devices plotted have been measured using liquid He cooled Si bolometers calibrated using blackbody sources. The impurity transitions from p-SiGe have demonstrated the highest output powers in 600-period quantum cascade structures [34]. The multiplication of the gain in the GaAs quantum cascade structures produced a six order of magnitude increase in power from a LED to a laser and so the higher demonstrated output powers from the Si–SiGe quantum cascades bode well for high-power emission when a laser is produced [11]. The higher output powers along with the weaker temperature dependence of the nonradiative transitions bode well for higher temperature operation of silicon QCLs when realized.

7.5.6 Si–SiGe Quantum Cascade Lasers At present no Si–SiGe QCL has been produced. Population inversion has been demonstrated [33] but at present attempts at producing cavities have not demonstrated structures with enough gain to lase. The major problem has been the confinement of the mode in the vertical direction, resulting in poor modal overlap, which is the amount of the mode overlaps with the active gain heterostructure layers of the device. Since the wavelengths used in the mid- and particularly the far-infrared are larger than the thicknesses of the heterolayers of the laser even when divided by the refractive index, the mode leaks into the substrate producing poor modal overlap and high losses. In GaAs, heavily doped layers have been used to create plasmons to confine the mode in the vertical direction. In silicon material the inversion of the real and imaginary parts of the dielectric constant does not occur in the mid- or far-infrared since

© 2006 by Taylor & Francis Group, LLC

7.5-772

The Silicon Heterostructure Handbook

Wavelength (µm) 3000 2000 102

1000

500

300 200

100

50

30

Schottky diodes 100

InP MMICs

Gunn Gunn

GaAs QCL 5K 5K 10 K

tubes

Power (W)

10−2

5K 77 K 10 K

77 K 100 K 10−4

−6

10

10−8

InGaAs RTDs

p-SiGe SiGe QC 5 K 150 K

photomixer

SiGe QC 5 K photoconductive antenna SiGe QC 5 K

10−10 0.1

GaAs QC 5 K

0.2

0.3

0.5

1

2

3

5

10

Frequency (THz)

FIGURE 7.5.11 A comparison of the output power versus frequency of a number of radiation sources between 100 GHz and 10 THz. (DJ Paul. Picturing People: non-intrusive imaging. UK DTI Foresight Exploiting the Electromagnetic Spectrum Report (http://www.dti.gov.uk/). With permission.)

the electrical conductivity of the doped silicon is not high enough to allow plasmon reflectors to be produced [35]. There are two potential methods to provide vertical confinement of the mode. The first is to etch away the substrate of the wafer and deposit a metallic reflector on the bottom side of the active heterolayers. This has been demonstrated on GaAs QCLs operating at about 3.2 THz or 94 mm wavelength [36] and results in improved high-temperature operation of the GaAs devices. The silicon system allows a second more amenable solution. Silicon-on-insulator (SOI) and buried-silicide layers are available, which have already been used as reflectors in mid-infrared quantum-well photodetectors (QWIPs) [37, 38]. In particular, the buried silicide layer has an electrical conductivity within an order of magnitude of the best metals and provides excellent confinement of the mode in the vertical direction [34, 35]. Figure 7.5.12 shows the first attempts at growing a virtual substrate and strain-symmetrized cascade emitter on top of a silicon-on-silicide wafer. In this particular structure, the modal overlap has been increased from 18% to over 44% by the inclusion of the silicide layer if a metal surface plasmon reflector is used on top of the wafers. The major problem is that the top silicon layer of the silicon-on-silicide wafer and the SiGe-relaxed buffer still contribute a large amount of lossy material inside the cavity and these layers need to become a smaller percentage of the total thickness in future wafers if a laser is to be realized. The modal overlap and waveguide losses of this particular structure when fabricated into ridge waveguides are comparable to the values in demonstrated GaAs THz lasers [11, 36]. The cascade emitter has demonstrated electroluminescence with only a TM-polarized component when the HH1 to LH1 interwell electroluminescence is measured. At higher currents, strong heating effects are absorbed due to the poorer thermal conductivity of the substrate compared to bulk silicon. The work does demonstrate that Si–SiGe cascade emitters can benefit from the rich technology basis available in silicon technology.

© 2006 by Taylor & Francis Group, LLC

7.5-773

Si–SiGe Quantum Cascade Emitters

4005 nm Si / Si0.7Ge0.3 600 period diagonal cascade

990 nm Si0.8Ge0.2

2830 nm SiGe graded buffer

1280 nm silicon WSi2 400 nm SiO2

FIGURE 7.5.12 A TEM picture of a 600 periods interwell Si–SiGe strain-symmetrized cascade emitter grown on top of a silicon-on-silicide wafer using CVD. The silicide is 440-nm thick and is fabricated by wafer bonding on top of an oxidized silicon hand wafer [34]. (DJ Paul, SA Lynch P Townsend, Z Ikonic´, RW Kelsall, P Harrison, SL Liew, DJ Norris, AG Cullis, J Zhang, HS Gamble, WR Tribe, and DD Arnone. Si/SiGe terahertz quantum cascade emitters. Int. Semicond. Dev. Research Symp., Washington, USA, December 2003. With permission.)

7.5.7 Summary A number of different Si–SiGe quantum cascade emitters have been demonstrated operating at frequencies from 1.2 THz (250 mm) in the far-infrared or terahertz up to 42 THz (7.1 mm) in the midinfrared. To date no laser has been demonstrated but a number of different approaches are pursued to circumvent the present known problems. If a silicon laser can be realized then it should have significant advantages over III–V lasers for operation below the silicon optical phonon energy of 62 meV. With the present knowledge and effort in the field, it should be only a matter of time before a silicon unipolar laser is produced.

Acknowledgments The work involved in this paper has been supported by DARPA, EPSRC, and through the EC program SHINE (IST-2001-38035). The author acknowledges the contributions of his numerous colleagues especially at the Universities of Cambridge, Leeds, Sheffield, Queens Belfast, and Imperial College along with TeraView Ltd. in the production of many of the results and pictures used in this review article.

References 1. L Pavesi. Will silicon be the photonic material of the third millenium. J. Phys.: Condens. Matter 15:R1169–R1196, 2003. 2. L Pavesi, S Gaponenko, and L Dal Negro, eds. Towards the First Silicon Laser (NATO Series, Vol. 93). New York: Kluwer, 2003.

© 2006 by Taylor & Francis Group, LLC

7.5-774

The Silicon Heterostructure Handbook

3. C Gmachl, F Capasso, DL Sivco, and AY Cho. Recent progress in quantum cascade lasers and applications. Rep. Prog. Phys. 64:1533–1601, 2001. 4. F Capasso, R Paiella, R Martini, R Colombelli, C Gmachl, TL Myers, MS Taubman, RM Williams, CG Bethea, K Unterrainer, HY Hwang, DL Sivco, AY Cho, AM Sergent, HC Liu, and EA Whittaker. Quantum cascade lasers: ultrahigh-speed operation, optical wireless communications, narrow linewidth and far-infrared emission. IEEE J. Quantum Elec. 38:511–532, 2002. 5. C Gmachl, A Straub, R Colombelli, F Capasso, DL Sivco, AM Sergent, and AY Cho. Single-mode, tunable distributed-feedback and multiple-wavelength quantum cascade lasers. IEEE J. Quantum Elec. 38:569–581, 2002. 6. RF Kazarinov and RA Suris. Possibility of the amplification of electromagnetic waves with a semiconductor superlattice. Sov. Phys. Semiconductors 5:707–709, 1971. 7. J Faist, F Capasso, DL Sivco, C Sirtori, AL Hutchinson, and AY Cho. Quantum cascade laser. Science 264:553–556, 1994. 8. DD Arnone, CM Ciesla, and M Pepper. Terahertz imaging comes into view. Phys. World 13(4):35, 2000. 9. MC Kemp, PF Taday, BE Cole, JA Cluff, AJ Fitzgerald, and WR Tribe. Security applications of terahertz technology. Proc. SPIE 5070:44–52, 2003. 10. F Oliveira, R Barat, B Shulkin, J Federici, and D Gary. Neural network analysis of terahertz spectra of explosives and bio-agents. Proc. SPIE 5070:60–70, 2003. 11. R Ko¨hler, A Tredicucci, F Beltram, HE Beere, EH Linfield, AG Davies, DA Ritchie, RC Iotti, and F Rossi. Terahertz semiconductor laser. Nature 417:156–158, 2002. 12. MM Rieger and P Vogl. Electronic-band parameters in strained Si1xGex alloys on Si1yGey substrates. Phys. Rev. B 48:14276–14287, 1993; Phys. Rev. B 50:8138, 1994. 13. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers. J. Cryst. Growth 32:265–271, 1976. 14. J Faist, M Beck, T Aellen, and E Gini. Quantum-cascade lasers based on bound-to-continuum transitions. Appl. Phys. Lett. 78:147–149, 2001. 15. L Friedman, G Sun, and RA Soref. SiGe/Si THz laser based on transitions between inverted mass light-hole and heavy-hole subbands. Appl. Phys. Lett. 78:401–403, 2001. 16. BN Murdin, W Heiss, CJGM Langerak, SC Lee, I Galbraith, G Strasser, E Gornik, M Helm, and CR Pidgeon. Direct observation of the LO phonon bottleneck in wide GaAs/AlxGa1xAs quantum wells. Phys. Rev. B 55:5171–5176, 1997. 17. CD Bezant, MM Chamberlain, PM Pellemans, BN Murdin, W Batty, and M Henini. Intersubband relaxation lifetimes in p-GaAs/AlGaAs quantum wells below the LO-phonon energy measured in a free electron laser experiment. Semicond. Sci. Technol. 14:L25–L28, 1999. 18. P Murzyn, CR Pidgeon, J-PR Wells, IV Bradley, Z Ikonic´, RW Kelsall, P Harrison, SA Lynch, DJ Paul, DD Arnone, DJ Robbins, DJ Norris, and AG Cullis. Picosecond intersubband dynamics in p-Si/SiGe quantum-well emitter structures. Appl. Phys. Lett. 80:1456–1458, 2002. 19. DJ Paul, SA Lynch R Bates, Z Ikonic´, RW Kelsall, P Harrison, DJ Norris, SL Liew, AG Cullis, DD Arnone, CR Pidgeon, P Murzyn, J-PR Wells, and IV Bradley. Si/SiGe quantum cascade emitters. Physica E 16:147, 2003. 20. DJ Paul, SA Lynch R Bates, Z Ikonic´, RW Kelsall, P Harrison, DJ Norris, SL Liew, AG Cullis, CR Pidgeon, DD Arnone, and DJ Robbins. Electroluminescence from Si/SiGe quantum cascade emitters. Physica E 16:309, 2003. 21. CR Pidgeon, P Murzyn, SA Lynch, and DJ Paul. Measurement of the non-radiative lifetime in a biased Si/SiGe quantum cascade emitter. Unpublished. 22. RA Kaindl, M Woerner, M Wurm, K Reimann, T Elsaesser, C Miesner, K Brunner, and G Abstreiter. Femtosecond intersubband scattering of holes in Si1xGex quantum wells. Physica B 314:255, 2002. 23. I Bormann, K Brunner, S Hackenbuchner, G Abstreiter, S Schmult, and W Wegscheider. Nonradiative relaxation times in diagonal transition Si/SiGe quantum cascade structures. Appl. Phys. Lett. 83:5371–5373, 2003.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe Quantum Cascade Emitters

7.5-775

24. F Capasso, A Tredicucci, C Gmachl, Dl Sivco, AL Hutchinson, AY Chu, and G Scamarcio. Highperformance superlattice quantum cascade lasers. IEEE J. Sel. Topics Quant. Elec. 5:792–807, 1999. 25. L Diehl, A Borak, S Mentese, D Gru¨tzmacher, H Sigg, U Gennser, I Sagnes, Y Campidelli, O Kermarrec, D Bensahel, and J Faist. Anticrossing between heavy-hole states in Si0.2Ge0.8/Si-coupled quantum wells grown on Si0.5Ge0.5 pseudosubstrates. Appl. Phys. Lett. 84:2497–2499, 2004. 26. S Komiyama, S Kuroda, I Hosako, Y Akasaka, and N Iizuka. Germanium lasers in the range from farinfrared to millimetre waves. Optical Quant. Elec. 23:S133–S162, 1991. 27. HJ Hrostowski. Infrared absorption of semiconductors. In Semiconductors, NB Hannay, ed. Reinhold: New York, 1959, pp. 437–481. 28. C Jagannath, ZW Grabowski, and AK Ramdas. Linewidths of the electronic excitation spectra of donors in silicon. Phys. Rev. B 23:2082–2098, 1981. 29. G Dehlinger, L Diehl, U Gennser, H Sigg, J Faist, K Ensslin, D Gru¨tzmacher, and E Mu¨ller. Intersubband electroluminescence from SiGe quantum cascade structure. Science 290:2277–2279, 2000. 30. I Bormann, K Brunner, S Hackenbuchner, G Zandler, G Abstreiter, S Schmult, and W Wegscheider. Midinfrared intersubband electroluminescence of Si/SiGe quantum cascade strucrtures. Appl. Phys. Lett. 80:2260–2262, 2002. 31. SA Lynch, R Bates, DJ Paul, DJ Norris, AG Cullis, Z Ikonic´, RW Kelsall, P Harrison, DD Arnone, and CR Pidgeon. Intersubband electroluminescence from Si/SiGe cascade emitters at terahertz frequencies. Appl. Phys. Lett. 81:1543–1545, 2002. 32. L Diehl, S Mentese, E Mu¨ller, D Gru¨tzmacher, H Sigg, U Gennser, I Sagnes, Y Campidelli, O Kermarrec, D Bensahe, and J Faist. Electroluminescence from strain-compensated Si0.2Ge0.8 quantum-cascade structures based on a bound-to-continuum transition. Appl. Phys. Lett. 81:4700–4702, 2002. 33. R Bates, SA Lynch, DJ Paul, Z Ikonic´, RW Kelsall, P Harrison, SL Liew, DJ Norris, AG Cullis, WR Tribe, and DD Arnone. Interwell intersubband electroluminescence from Si/SiGe quantum cascade emitters. Appl. Phys. Lett. 83:4092–4095, 2003. 34. DJ Paul, SA Lynch P Townsend, Z Ikonic´, RW Kelsall, P Harrison, SL Liew, DJ Norris, AG Cullis, J Zhang, HS Gamble, WR Tribe, and DD Arnone. Si/SiGe terahertz quantum cascade emitters. Int. Semicond. Dev. Research Symp., Washington, USA, December 2003. 35. Z Ikonic´, P Harrison, and RW Kelsall. Waveguide design for mid- and far-infrared p-Si/SiGe quantum cascade lasers. Semicond. Sci. Technol. 19:76–81, 2004. 36. S Kumar, BS Williams, S Kohen, Q Hu, and LJ Reno. Continuous wave operation of terahertz quantum-cascade lasers above liquid nitrogen temperature. Appl. Phys. Lett. 84:2494–2496, 2004. 37. RT Carline, DJ Robbins, MB Stanaway, and WY Leong. Long-wavelength SiGe/Si resonant cavity infrared detector using a bonded silicon-on-oxide reflector. Appl. Phys. Lett. 68:544–546, 1996. 38. RT Carline, V Nayar, DJ Robbins, and MB Stanaway. Resonant cavity longwave SiGe-Si photodetector using a buried silicide mirror. IEEE Photon. Tech. Lett. 10:1775–1777, 1998. 39. DJ Paul. Picturing People: non-intrusive imaging. UK DTI Foresight Exploiting the Electromagnetic Spectrum Report (http://www.dti.gov.uk/).

© 2006 by Taylor & Francis Group, LLC

8 Measurement and Modeling 8.1

Overview: Measurement and Modeling J.D. Cressler ............................................ 8.1-779

8.2 Best-Practice AC Measurement Techniques R.A. Groves...................................... 8.2-781 AC Device Measurement Techniques: Overview . AC Measurement Techniques . Summary 8.3

Industrial Application of TCAD for SiGe Development D.C. Sheridan, J.B. Johnson, and R. Krishnasamy ..................................................... 8.3-793 Introduction . SiGe Process Simulation . SiGe Device Simulation . Application Examples . Predictive Model Extraction . Summary

¨ ...................................... 8.4-807 8.4 Compact Modeling of SiGe HBTs: HICUM M. Schroter Introduction . HICUM Basics . Geometry Effects and Scaling . Parameter Determination Methodology . Model Hierarchy . Trends . Summary 8.5 Compact Modeling of SiGe HBTs: Mextram S. Mijalkovic´ .................................. 8.5-825 Introduction . Transfer Current . Recombination Currents . Substrate Current . Charges and Capacitances . Thermal Phenomena . Parameter Extraction 8.6

CAD Tools and Design Kits S.E. Strang.................................................................. 8.6-847 Introduction . Schematic Capture . Design Simulation . Physical Design . Physical Verification . Chip Assembly . Chip Finishing

8.7

Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs R. Singh ............................................................................ 8.7-859 Introduction . Substrate Noise Isolation and Coupling . Interconnect Modeling and Loss . Mitigating Circuit Parasitic Noise Effects . Summary

8.8

Transmission Lines on Si Y.V. Tretiakov ................................................................. 8.8-871 Introduction . Transmission Line Technology . Modeling Aspects . Transmission Line Measurements . Transmission Line Examples and Applications . Summary

8.9

Improved De-Embedding Techniques Q. Liang .................................................... 8.9-883 On-Wafer Parasitics and De-Embedding Techniques . Improved De-Embedding Technique . Comparison . Noise De-Embedding Technique

8.1-777 © 2006 by Taylor & Francis Group, LLC

8.1 Overview: Measurement and Modeling

John D. Cressler Georgia Institute of Technology

Measurement and modeling of high-speed semiconductor devices is something that, unfortunately, is rarely discussed in a meaningful manner in the technical literature. This is a shame. In my experience, robust measurement and modeling, particularly at the extreme levels of performance found in modern SiGe devices, is a fine art, requires extreme dexterity in the laboratory, and getting reliable data, and importantly, a model to fit the data, is often two thirds of the battle for success (that may be an understatement)! One inevitably sees a nicely presented set of data, and the natural response is ‘‘How did they do that? What tricks did they use? How can I do that for myself ?’’ Alas, often times, one must simply keep on wondering, since such ‘‘tricks-of-the-trade’’ are held close to the vest and rarely divulged. One of the unique features of this handbook is that I have attempted to buck this trend and get some experts to talk about the subtle nuances of the measurement and modeling trade. It is something I am quite proud of, and I suspect will prove to be very useful to practioners. Chapter 8.2, ‘‘Best-Practice ac Measurement Techniques,’’ by R. Groves of IBM Microelectronics shows how one accurately obtains ac data off of advanced SiGe HBTs. In Chapter 8.3, ‘‘Industrial Application of TCAD for SiGe Development,’’ by D. Sheridan of IBM Microelectronics, the use of TCAD in device design is addressed. In Chapter 8.4, ‘‘Compact Modeling of SiGe HBTs: HICUM,’’ by M. Schro¨ter of the University of Dresden, and Chapter 8.5, ‘‘Compact Modeling of SiGe HBTs: MEXTRAM,’’ by S. Mijalkovic of Delft University of Technology, two of the most sophisticated SiGe HBT compact models are described in detail, and importantly, also address how one should intelligently use them! Integrated circuit design kits are amazingly sophisticated these days, and S. Strang of IBM Microelectronics covers ‘‘CAD Tools and Design Kits,’’ in Chapter 8.6. Noise coupling and the modeling of such complex effects is often key to success at the circuit level in conductive-substrate silicon-based technologies, and is discussed at length in Chapter 8.7, ‘‘Parasitic Noise Modeling and Mitigation Approaches,’’ by R. Singh of IBM Microelectronics. Given that the frequency response of state-of-theart SiGe HBTs has reached unprecedented levels, designers are now beginning to seriously attack microwave and even mm-wave applications in SiGe. Key to success in this endeavor is the realization of robust transmission lines in Si, as discussed in Chapter 8.8, ‘‘Transmission Lines on Silicon,’’ by Y. Tretiakov of RF Micro Devices. Finally, accurate on-wafer de-embedding of parasitics to mm-wave frequencies is covered in Chapter 8.9, ‘‘Improved De-embedding Techniques,’’ by Q. Liang of Georgia Tech. 8.1-779 © 2006 by Taylor & Francis Group, LLC

8.2 Best-Practice AC Measurement Techniques 8.2.1 8.2.2

AC Device Measurement Techniques: Overview .................................................................... 8.2-781 AC Measurement Techniques................................... 8.2–782

8.2.3

Summary .................................................................... 8.2-791

Robert A. Groves IBM Microelectronics

S-Parameter Measurement . C–V

8.2.1 AC Device Measurement Techniques: Overview Development of high-quality device models is an essential ingredient in the design of successful analog and mixed-signal applications. Accurate device characterization plays a critical role in model development and circuit benchmarking. Model behavior must be verified against device measurements in order to validate the model and to define regions outside which the model may be inaccurate. The characterization of high-performance silicon heterostructures, and associated passives, requires care due to the demanding requirements associated with these devices: high frequencies, low leakage currents, low resistances, wide temperature ranges, etc. An area of particular concern and interest to device modelers and circuit designers is the improvement of the S-parameter measurement methodology as the measurement frequency extends to 100 GHz and beyond. Traditional calibration and de-embedding techniques need to be re-examined to determine if the underlying assumptions remain valid [1, 2]. In addition to characterization in support of model development, circuits must be measured and compared to design predictions and requirements. Circuit measurement is particularly demanding for applications utilizing SiGe devices due to the high-frequency and low-noise characteristics of these designs [3, 4]. Frequently, off-the-shelf measurement solutions do not exist to satisfy the characterization requirements for these cutting-edge circuits, requiring circuit designers to assume the role of test system developer. Preceding all these requirements is the necessity to create carefully controlled device measurement test structures that allow for accurate extraction of the desired device and circuit parametrics. Careful thought must be given to the limitations inherent in creating low parasitic test structures in a wafer-probing environment. This includes the creation of additional test structures that allow for the accurate characterization of the test structure parasitics, so that the device characteristics can be accurately de-embedded from the measured data [5, 6].

8.2-781 © 2006 by Taylor & Francis Group, LLC

8.2-782

The Silicon Heterostructure Handbook

8.2.2 AC Measurement Techniques S-Parameter Measurement Why S-Parameters The demands of high-frequency device modeling and characterization of device under test (DUT) behavior require a test system that is able to provide detailed information about DUT performance characteristics over a broad range of frequencies (DC to 100 GHzþ). Often the linear behavior of the DUT to a test signal is needed in order to characterize or model its behavior. A test system that is able to accurately report the network parameters of an unknown linear network to an applied signal is required for these high-frequency measurements. Some network parameters appropriate to characterization and modeling of silicon heterostructures, passives, and circuits are H-parameters (hybrid parameters), Y-parameters (admittance parameters), Z-parameters (impedance parameters), S-parameters (scattering parameters), and T-parameters (transmission parameters). Each of these network parameter sets describes the response of the DUT to a defined set of input conditions. H-parameters, for instance, are widely used to determine HBT device characteristics. They are useful for this purpose because the equations describing the H-parameters can naturally be used to determine short-circuit current gain or b (in addition to other useful device parametrics). Network parameters are applicable generally to N-port networks. Most applications of network parameters are limited to between two- and four-port networks. Since many circuits and devices have two well-defined ports, two-port networks are quite often the most useful in determining DUT characteristics. The two-port network shown in Figure 8.2.1 is labeled as is customary, with the upper terminals at positive potential with respect to the lower terminals and the currents defined as flowing into the two upper terminals and out of the two lower terminals. Under conditions of applied stimulus to one of the ports and defined termination of the other port, the response of the network can be characterized in terms of the voltage and current relationships observed at the ports. For a two-port network, two equations completely define the network characteristics as a function of the applied stimuli and measured voltages and currents and some constants of proportionality (simply the network parameters themselves). For H-parameters, the following relationships define the interaction between the voltages, currents, and H-parameters [7]: V 1 ¼ h11 I 1 þ h12 V 2 I 2 ¼ h21 I 1 þ h22 V 2 V 1 V1 h11 ¼ h12 ¼ I 1 v2 ¼0 V2 I1 ¼0 I2 I2 h21 ¼ h22 ¼ I 1 v2 ¼0 V 2 I1 ¼0 I1

(8:2:1)

I2

+

+

V1 −

Linear network

V2 −

FIGURE 8.2.1 Two-port network representation of a linear-time-invariant (LTI) system with conventional representation of applied voltages and measured currents.

© 2006 by Taylor & Francis Group, LLC

8.2-783

Best-Practice AC Measurement Techniques

These H-parameters can be derived directly through measurement of the two-port network, by applying the appropriate terminal conditions and monitoring the voltages and currents. H11, for instance, can be directly measured by applying a voltage (V1) to port 1, shorting port 2 to ground (V2 ¼ 0) and measuring the current flowing into port 1 (I1). Similarly, the other three H-parameters can be derived from physical measurements by simply applying the appropriate voltages and currents and setting one of the ports to either an open- or short-circuit condition as required by the definitions in Equation (8.2.1). A problem arises in applying this direct measurement technique at high frequencies. It is difficult to achieve perfect short or open circuits at the device terminals due to the parasitics associated with the connections between the measurement instruments and the device. These parasitic capacitances, resistances, and inductances combine to make the characteristics of open- and short-circuit connections strong functions of frequency. Therefore, a short circuit at one frequency may appear to be an open circuit at another, etc. This makes the broadband, direct measurement of many of the network parameters difficult. Another difficulty comes into play with active devices. Even if perfect broadband open and short circuits were achievable, silicon heterostructures may not be stable under conditions of open- and short-circuit termination of their terminals due to high gain and low parasitic resistances. The solution to this dilemma is to make device measurements using a set of network parameters that make use of applied bias and termination conditions that are easily achievable at high frequencies and that lend themselves to stable device operation. S-parameters satisfy these requirements. S-parameters are defined similarly to the previously described network parameters except that the applied bias conditions are defined in terms of traveling voltage waves, rather than total voltages and currents, and the termination conditions are defined in terms of the characteristic impedance of the transmission lines supplying these traveling waves, rather than open and short circuits. Figure 8.2.2 shows a two-port network with loss-less transmission lines supplying a traveling wave from a generator to port 1 and connecting a terminating impedance to port 2. The traveling voltage wave incident on port 1 will generate a reflected wave traveling back toward the source due to impedance mismatch between port 1 of the DUT and the transmission line. In addition, some of the energy will be transmitted through the network to port 2 and travel down the transmission line toward the load impedance. A voltage wave will then be reflected from the load toward port 2 (assuming that the load impedance is not equal to the characteristic impedance of the line), some of which will be transmitted back through the network and travel down the port 1 transmission line toward the generator where it will be either reflected or absorbed. Further reflections occur as each of these reflected voltage waves encounter an impedance mismatch or discontinuity. This complex combination of forward and reflected waves on the transmission lines connected to ports one and two will generate standing voltage waves.

a1 =

E1i

a2 =

√Z0 E1i

Z0

Z0

b1 =

E1i

Z0

Linear network s

E1r √Z0 E1i

E2i √Z0

ZL

b2 =

E2r √Z0 E1i

FIGURE 8.2.2 Two-port network representation used to describe S-parameters of a DUT. Loss-less transmission lines connect the DUT to the applied signal and load termination.

© 2006 by Taylor & Francis Group, LLC

8.2-784

The Silicon Heterostructure Handbook

The relationships equating these voltage waves at the two DUT pﬃﬃﬃﬃ ports and the S-parameters are indicated here [7] (the voltage waves are normalized by dividing by Z 0 for computational convenience): b1 ¼ s11 a1 þ s12 a2 b2 ¼ s21 a1 þ s22 a2 E1i E1r a1 ¼ pﬃﬃﬃﬃﬃ b1 ¼ pﬃﬃﬃﬃﬃ Z0 Z0 E2i E2r a2 ¼ pﬃﬃﬃﬃﬃ b2 ¼ pﬃﬃﬃﬃﬃ Z Z0 0 b1 b1 s11 ¼ s12 ¼ a1 a2 ¼0 a2 a1 ¼0 b2 b2 s21 ¼ s22 ¼ a1 a2 ¼0 a2 a1 ¼0

(8:2:2)

The constraining conditions that describe each individual S-parameter (i.e. a2 ¼ 0 for S11 and S21) are achieved by setting the appropriate reflection coefficient (G ¼ Ereflected / Eincident) to zero. This implies that the voltage wave is totally absorbed by a load impedance that is equal to the characteristic impedance of the transmission line. Thus, the two load conditions that must be achieved in order to directly measure the four S-parameters are as follows: 1. A load has been put in place of the generator of Figure 8.2.2 and a generator is applying a signal to port 2 through the transmission line. The condition a1 ¼ 0 implies that the load impedance on the port 1 transmission line is equal to the Z0 of that line, fully absorbing the voltage wave traveling toward the port 1 load. 2. The circuit of Figure 8.2.2 is achieved, with the load impedance on port 2 equal to the Z0 of the transmission line connected to port 2, absorbing the voltage wave incident on the load and setting the reflected wave to zero (a2 ¼ 0). These load conditions in a typical S-parameter measurement system are equal to 50 V, since the transmission lines connecting the measurement instrument and the DUT are generally 50 V transmission lines. This condition is much easier to achieve over a broad range of very high frequencies and contributes to a more stable measurement environment for high gain devices. Measuring the S-parameters of a DUT, then, consists of measuring the complex voltage waves present at the DUT ports under the conditions of an applied voltage wave transmitted through a loss-less transmission line toward one port and the termination of the other ports with a 50 V load (for a 50 V measurement system). While this is simpler than achieving the requirements for directly measuring a set of network parameters defined in terms of total voltages and currents (implying that perfect open- and short-termination conditions must be realized), there are still difficulties in achieving accurate measurements representative of the conditions at the DUT ports due to nonideal measurement conditions. For example, the transmission line connecting the measurement instrument and DUT has losses and may not have a Z0 of exactly 50 V, making it nonideal; reflections occur where cables, waveguides, or wafer probes connect to the measurement system and the DUT due to impedance mismatches; the 50 V load termination has frequency-dependent behavior and is not exactly 50 V; the generator does not have a perfect 50 V impedance; the equipment required to sample and measure the incident and reflected voltage waves causes additional losses and distortions; when making on-wafer measurements, the probe pads and transmission line launches introduce further errors. The procedures used to extract the DUT port characteristics from the raw measured S-parameters are called calibration and de-embedding. Instrumentation The measurement of S-parameters is most commonly performed using a test instrument called a vector network analyzer (VNA). These are typically configured to measure one-, two-, or four-port

© 2006 by Taylor & Francis Group, LLC

Best-Practice AC Measurement Techniques

8.2-785

S-parameters. Fully automated VNAs, able to measure more than one-port S-parameters, typically contain switching elements that allow for either a signal or load to be applied to each port in turn enabling the measurement of the multiport S-parameters with no manual intervention. In addition, a means of calibrating out the parasitics associated with connecting the VNA to a DUT is generally provided as an internal procedure that can be implemented from the instrument front panel or through a network connection by a host computer. Figure 8.2.3 shows an on-wafer, semi-automated S-parameter measurement system capable of measuring S-parameters up to 110 GHz. Calibration Since all voltage-wave measurements must, of necessity, be made in the VNA itself, a means of accounting for the effects of the nonideal transmission lines and other parasitics, present between the VNA measurement transducers and the DUT ports is required. In the simplest sense, VNA calibration makes use of the concept of a shifted reference plane to enable the direct measurement of the DUT port characteristics. Figure 8.2.4 shows the measurement setup of Figure 8.2.2 with the addition of a fourport S-parameter matrix (S 0 ) representing the actual transmission lines, and their associated loss and coupling parasitics, connecting the VNA to the DUT measurement ports. The measurement reference plane defines the actual ports of the uncalibrated, measured S-parameters and exists somewhere in the interior of the VNA itself. The DUT reference plane represents the desired location of the DUT ports such that the measured S-parameters, shifted to the DUT reference plane, represent the desired terminal characteristics of the DUT. This implies that 16 error terms (the S-parameters of the four-port matrix S 0 ) must be determined during calibration in order to fully describe the four-port error network. Once the 16 error terms are known, the DUT S-parameters can be extracted from the measured S-parameters using matrix manipulation. This removal of the effects of the S 0 network is known as ‘‘shifting the reference plane to the DUT ports.’’ In practice, the error network is passive implying that it is reciprocal and that S 0 ¼ S 0 T. This means that the eight S-parameters representing signal transmission through the network are equal in both the forward and reverse directions (i.e., S13 ¼ S31, etc.). A reciprocal fourport network, then, can be fully qualified with 12 error terms, since four of them will be redundant. This is, in essence, how the standard VNA 12-term error model is derived [8]. Calibration consists of measuring known standards located at the DUT reference plane and then applying algorithms to determine the 12 error terms. For wafer-level calibration, there are two main techniques:

FIGURE 8.2.3 Agilent N5250A 110 GHz VNA measurement system connected to a Cascade Microtech Summit semi-automated wafer probing system for characterizing on-wafer devices to 110 GHz. (Copyright 2004, Agilent Technologies, Inc. Reproduced with permission of Agilent Technologies.)

© 2006 by Taylor & Francis Group, LLC

8.2-786

The Silicon Heterostructure Handbook

S9 (4-port)

Measurement reference plane

Linear network S

DUT reference plane

DUT reference plane

Measurement reference plane

Z0

ZL

S meas

FIGURE 8.2.4 Representation of desired DUT network (S) embedded in a four-port error network (S 0 ) representing the nonideal measurement environment present between the VNA and the DUT.

1. Let the four-port error network represent the environment between the VNA and the probe tips.

a. Shift the reference plane to the probe tips followed by an additional step called deembedding that is designed to characterize and remove any additional parasitics that might exist between the probe pads and the DUT. 2. Let the four-port error network represent the environment between the VNA and the actual DUT ports. a. Shift the reference plane directly to the DUT ports by measuring standards at the end of the signal launches that exist between the probe pads and the DUT. Each approach requires that the 12 unknown error terms be determined to a great degree of accuracy. The first approach requires the additional determination of the parasitic behavior of the probe pads and transmission line launches connecting the probes to the DUT. Determination of the error terms is done in a similar manner regardless of the desired location of the corrected reference plane. If the reference plane is desired to be at the probe tips (method 1), then the calibration standards may be realized either on-wafer or on a separate calibration substrate. In order to shift the reference plane directly to the DUT ports (method 2), the calibration standards must be realized on-wafer, in close proximity to the DUT. There are several different techniques that can be used to achieve the desired reference plane shift, generally named according to the calibration standards required to achieve the calibrations [9, 10]: .

.

SOLT (Short-Open-Load-Thru) a. Requires accurate knowledge of actual characteristics (parasitic inductance and capacitance) of cal standards up to the highest frequency of operation.

b. Used successfully to 50 GHz and beyond, but sensitive to probe placement at higher frequencies, making measurement repeatability a problem. SOLR (Short-Open-Load-Reciprocal) a. Same requirements as SOLT, but only constraint on Reciprocal standard is that S12 ¼ S21. Typically used in applications where probes cannot be placed such that they are 1808 opposed

© 2006 by Taylor & Francis Group, LLC

Best-Practice AC Measurement Techniques

.

.

8.2-787

(i.e., both probes in the same plane, or one port rotated 908 with respect to the other), requiring that the Thru standard have a bend. b. Accuracy suffers in relation to SOLT cals [11]. TRL (Thru-Reflect-Line) a. Multiple different line lengths (probe spacing variable) required to provide broadband calibration (i.e., three line lengths required to cover 2 to 18 GHz range). b. Characteristic impedance of lines defines reference impedance of resulting S-parameters. c. Extending frequency range below 5 GHz requires excessively long transmission lines as cal standards and may sacrifice accuracy. d. Dispersion effects on the transmission line Z0 can limit effectiveness [12]. e. NIST-TRL technique provides high accuracy over valid frequency range. LRM/LRRM (Line-Reflect-Match, Line-Reflect-Reflect-Match) a. Thru delay and Match resistance must be known. b. Match reactance adjusted to achieve best-calibrated open response. c. Match resistance defines reference impedance of resulting S-parameters. d. Less sensitive to probe placement.

While shifting the measurement reference plane directly to the DUT terminals in one step is desirable, in practice this technique is difficult to implement due to problems associated with achieving acceptable calibration standards on-wafer. Match standards (typically 50 V resistors) are difficult to achieve with sufficient tolerance and low parasitics. Off-wafer match standards are laser trimmed to within 0.5% of 50 V, while on-wafer resistors with tolerances better than 10% are very difficult to realize and usually have significant capacitive parasitics. Transmission lines realized on Si wafers display excessive dispersion and loss effects for characteristic impedances near 50 V and for lines long enough to allow for reasonably low-frequency measurements. Additionally, transmission line standards, with sufficient length to allow measurement as low as 5 GHz, require large chip areas due to their excessive length. For these reasons, the first approach mentioned above (calibration to probe tips followed by on-wafer de-embedding) is the de facto standard for calibrating on-wafer S-parameter measurements. Utilizing this ‘‘probe-tip’’ cal approach has a drawback to achieving high accuracy in the final calibrated DUT S-parameters. The parasitic capacitance to ground and probe-to-probe coupling (primarily through the substrate) experienced by the probe when measuring the cal standards of the off-wafer cal substrate (typically an insulating alumina substrate) will be different than those seen when probing the DUT on-wafer (typically lossy Si substrate). This difference will result in systematic errors that will not be accounted for in the probe-tip cal. This systematic error can be minimized through careful measurement structure design. The most common two approaches used for probe-tip calibrations are LRRM and SOLT. TRL and SOLR calibrations have drawbacks in bandwidth and accuracy that generally preclude their use except in special circumstances. Proper choice of calibration and de-embedding techniques, then, is a major factor in achieving accurate S-parameter measurements to 100 GHz and beyond. De-Embedding The procedure used most frequently for on-wafer de-embedding of DUT characteristics from probe-tip calibrated measurements makes use of on-wafer standards designed to represent the parasitic environment around the DUT [13–18]. Figure 8.2.5(a) shows a typical on-wafer S-parameter probe-pad environment used to measure silicon heterostructures. This layout is optimized for two-port probing with ground-signal-ground (GSG) microwave probes. The GSG probes provide a means of launching a coplanar voltage wave onto the probe pads from the primarily coaxial transmission environment that exists between the VNA and the probes [19]. The S-parameter padset is designed to minimize the parasitic capacitance, resistance, and inductance that will need to be de-embedded from the measured S-parameters. The signal pad is made as small as possible while still providing enough metal landing area to completely land the microwave probe tip without overhanging the sides of the pad, as an overhanging probe provides additional parasitic capacitance that must be de-embedded. A conductive groundplane

© 2006 by Taylor & Francis Group, LLC

8.2-788

The Silicon Heterostructure Handbook

(running from the top ground strap to the bottom ground strap at each port) is often provided underneath the signal pad, providing a well defined, low impedance return path for the parasitic electric field of the pad. This ground return path can be constructed of any material with reasonable conductivity, such as silicided polysilicon or a metal layer, such as M1. The various parasitic elements associated with the padset are added to the padset of Figure 8.2.5(a) and represented in Figure 8.2.5(b). The schematic representation of the padset parasitics alone can be seen in Figure 8.2.5(c). As can be seen from Figure 8.2.5(c), the parasitic network represented by the elements labeled G1 and G2 (pad to groundplane capacitive and resistive parasitics), and G3 (port 1-to-port 2 capacitive and resistive parasitics) is connected in parallel with the DUT. On the other hand, the network consisting of Z1 and Z2 (port-to-DUT series resistive and inductive parasitics), and the network represented by Z3 (DUT third terminal-to-ground resistive and inductive parasitics) are in a series connection with the DUT terminals. This grouping of the padset parasitics into two networks, Z representing the combined series connected parasitics and G representing those parasitics that show up in parallel with the DUT, allows us to effectively remove (or minimize) the effects of the parasitics through the procedure called de-embedding. The standards used to facilitate the de-embedding process are designed to represent either the parallel (G) parasitics, called the ‘‘Open Standard’’, or the series (Z) parasitics, called the ‘‘Short Standard.’’ The basic procedure is called Open-Short de-embedding. The Open standard is created by simply removing the DUT from the complete padset of Figure 8.2.5(a), while the Short standard is created by replacing the DUT with a metal shorting piece that shorts the port 1 and port 2 connections to each other and to ground. Proper design of these standards is crucial to achieving accurate de-embedding of the padset parasitics up to very high frequencies. In order for Open-Short de-embedding to provide valid results, the padset must be designed to have an electrical behavior that closely mimics the schematic of Figure 8.2.5(c). Any series or parallel paths not accounted for in the schematic should be minimized as much as possible (i.e., the impedance of the ground straps separating ports one and two should be made as small as possible, since this is represented as a zero impedance node in the schematic). If the padset is made to mimic the schematic as closely as possible and the parasitics are reduced to as low a value as possible, Open-Short de-embedding can provide valid results to 100 GHz. Above 100 GHz and for padsets that, due to their larger than normal size (as in spiral inductors) do not adhere to the schematic, further de-embedding methods may be required [1, 2]. The de-embedding procedure consists of the following steps: 1. Measure the S-parameters of the DUT embedded in the padset (Smeas). 2. Measure the S-parameters of the Open and Short de-embedding standards (Sopen and Sshort, respectively). 3. Convert Sopen and Sshort to Y-parameters (Yopen and Yshort, respectively). Subtract Yopen from 0 (the Y-parameters of the short standard with the parallel capacitive and Yshort to yield Yshort resistive contribution from the pads and substrate removed). 0 0 0 to Zshort . Zshort now represents the combined network consisting of the three 4. Convert Yshort series impedances (Z1, Z2, and Z3). 0 (the Y-parameters of the DUT 5. Convert Smeas to Ymeas and subtract Yopen from it. This yields Ymeas with the parallel capacitive and resistive contribution from the pads and substrate removed). 0 0 to Zmeas which still contains the series impedances associated with Z1, Z2, and Z3 Convert Ymeas in addition to the desired DUT terminal characteristics. 0 0 00 from Zmeas to yield Zmeas (the Z-parameters of the DUT in the absence of all 6. Subtract Zshort 00 00 back into fully padset corrected S-parameters (Smeas ) padset parasitics) and finally, convert Zmeas for analysis of the DUT terminal characteristics. In addition to creating an ideal padset structure, another condition must be satisfied in order to be able to achieve valid results from Open-Short de-embedding. The network parameters representing the Open, Short, and DUT measurements must be linear and time invariant (LTI) in nature. This is not a problem for the Open and Short standards, as they are passive networks and, therefore, satisfy the LTI requirements. The DUT network parameters are LTI only under certain conditions, the most important

© 2006 by Taylor & Francis Group, LLC

8.2-789

Best-Practice AC Measurement Techniques

nd ou Gr lane p

nd ou Gr lane p

M3 M2 M1

(a)

nd ou Gr ane pl

M3 M2 M1

nd ou Gr ane pl

(b)

G3 Z1

Z2 DUT

G1

Z3

G2

(c)

FIGURE 8.2.5 (a) S-parameter measurement padset showing probe landing pads and connections between the probe pads and the DUT. (b) S-parameter measurement padset of (a) with schematic symbols representing padset parasitics and their general physical location. (c) Schematic representation of S-parameter padset parasitics with the physical structure removed for clarity.

© 2006 by Taylor & Francis Group, LLC

8.2-790

The Silicon Heterostructure Handbook

of which is that the DUT is behaving linearly with applied input power (i.e., the network parameters are not dependent on input power level). This condition holds true when the input power level is low enough to ensure that the device gain remains linear with input power. Above this threshold input power level, the device no longer behaves as an LTI system, and the de-embedding procedures are no longer valid. Power-Level Selection Recall that the network parameters for a DUT are defined with the condition that the DUT behaves as a linear system. For example, if the device cannot linearly translate the input to the output (i.e., experiences gain compression), then the resulting S-parameters will no longer be valid. This concept applies to all four S-parameters, not just S21. If a particular S-parameter changes significantly with varying power level, the device can be said to be operating nonlinearly, negating the validity of the Sparameters. A simple test for this is to display the S-parameter of interest while the device is biased in its operational region. Divide the display data, using the VNA display math functions, by itself to yield a flat curve with a value of 0 dB across the frequency range of interest. Next change the power level in stages and observe the resulting curve. At some point the curve will begin to deviate from a flat 0 dB line. The magnitude of this deviation in dB is a measure of the nonlinearity of the device at that power level. For a range of power levels, there will exist a power level below which the S-parameters will no longer change. This is the highest power level that should be applied to the device while still assuring linear behavior. Power levels significantly below this level should be avoided for a different reason. The VNA has a noise floor that is a function of various settings and the internal instrumentation itself, the dynamic range of the VNA measurement is the difference between the measured power level and the noise floor. A high dynamic range is desired as it implies less noise present in the measured results. One further caution should be observed with regard to power levels. DUTs with high gain (many silicon heterostructures) may raise the output power level enough to overload the receiver on the input of the VNA. Judicious choice of input power levels, and possibly attenuation on the output, should be used to avoid this overload condition, which will affect the accuracy of the measured results. Therefore, appropriate choice of measurement power level is critical to achieving accurate S-parameters for silicon heterostructures. Some incorrect power conditions will be obvious (i.e., VNA receiver overload), while others will not (i.e., nonlinear behavior of the DUT or excessive noise in the data due to reduced dynamic range).

C–V For certain measurement situations, determination of device capacitance or inductance through S-parameter measurements is not required. Capacitance and inductance characteristics versus voltage or current bias can be achieved through the use of an impedance measurement system. This method is only suitable for measuring device characteristics that can be well described by a simple model consisting of resistors, capacitors, and inductors in various series and parallel configurations. The instrument essentially measures the magnitude and phase response of the DUT to an applied AC and DC bias (frequencies typically less than 10 MHz) and then applies a model (i.e., a capacitor in parallel with a conductance) to the data to report element values for the model (capacitance and conductance in this example). Different models will be appropriate for different device characteristics. For example a large capacitor with a nonnegligible series resistance might benefit from extracting the capacitance and resistance from a series R-C model. The model is typically chosen such that the reactive component characteristics can be extracted from the imaginary part of the measured impedance without having a strong variation in value over a certain range of frequencies. Different models may be appropriate for the same device at different measurement frequencies. Proper selection of the measurement model and frequency of measurement is crucial to getting meaningful data from an impedance measurement system [20].

© 2006 by Taylor & Francis Group, LLC

Best-Practice AC Measurement Techniques

8.2-791

8.2.3 Summary Accurate high-frequency measurement capabilities and practices are crucial to the development and modeling of silicon heterostructures and their associated circuits. A basic understanding of S-parameters and the role they play in determining device and circuit characteristics is important for the laboratory technician, device development engineer, device modeler, and circuit designer. Proper interpretation of S-parameter and low-frequency C–V measurement data provides the engineer with the information needed to make informed decisions in the technology development and product design processes. An understanding of the assumptions used in the calibration, de-embedding and reporting of high-frequency data allows the engineer to use the information wisely, discarding information that may be based on invalid assumptions. This chapter has attempted to lay the groundwork for interpreting high-frequency data acquired in the RF laboratory. In addition some effort has been made to describe the requirements for creating effective on-wafer measurement pad structures that minimize the parasitics that must be de-embedded from measured data. Properly designed pad structures allow for more accurate de-embedding of measured device characteristics, resulting in data that accurately represent the DUT terminal characteristics.

References 1. Q. Liang, J.D. Cressler, G. Niu, Y. Lu, G. Freeman, D. Ahlgren, R.M. Malladi, K. Newton, and D.L.Harame. A simple 4-port parasitic de-embedding methodology for high-frequency characterization of SiGe HBTs. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2003, pp. 357–360. 2. L.F. Tiemeijer, J. Ramon, and Havens. A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors. IEEE Transactions on Electron Devices 50(3), 2003, 822–829. 3. J. Kim, J.-O. Plouchart, N. Zamdmer, N. Fong, M. Sheronv, Y. Tan, M. Talbi, R. Trzcinski, J. Safran, K. Wu, S. Womack, J. Sleight, C. Sheraw, A. Ray, and L. Wagner. Highly manufacturable 40–50 GHz VCOs in a 120 nm system-on-chip SOI technology. IEEE International Electron Devices Meeting, December, 2003, pp. 15.3.1–15.3.4. 4. G. Freeman, M. Meghelli, Y. Kwark, S. Zier, A. Rvlyakov, M.A. Sorna, T. Tanji, O.M. Schreiber, K. Walter, J.-S. Rieh, B. Jagannathan, A. Joseph, and S. Subbanna. 40-Gb/s circuits built from 120 GHz f.sub T/SiGe technology. IEEE Journal of Solid State Circuits 37(9), 2002, 1106–1114. 5. T.E. Kolding. Shield-based microwave on-wafer device measurements. IEEE Transactions on Microwave Theory and Techniques 49(6), 2001, 1039–1044. 6. T.E. Kolding, O.K. Jensen, and T. Larsen. Ground-shielded measuring technique for accurate onwafer characterization of RF CMOS devices. Proceedings of the International Conference on Microelectronic Test Structures, Monterey, CA, 2000, pp. 246–251. 7. Agilent Technologies, Inc. Agilent AN 154 S-Parameter Design. Agilent Technologies, Inc. Application Note, 2000. 8. Agilent Technologies, Inc. Agilent AN 1364-1 De-Embedding and Embedding S-Parameter Networks Using a Vector Network Analyzer. Agilent Technologies, Inc. Application Note, 2001. 9. Cascade Microtech, Inc. On-Wafer Vector Network Analyzer Calibration and Measurements. Cascade Microtech, Inc. Application Note, 1997. 10. A.M.E. Safwat and L. Hayden. Sensitivity analysis of calibration standards for fixed probe spacing on-wafer calibration techniques. IEEE Microwave Theory and Techniques Symposium Digest, 2002, pp. 2257–2260. 11. S. Basu and L. Hayden. An SOLR calibration for accurate measurement of orthogonal on-wafer DUTs. IEEE Microwave Theory and Techniques Symposium Digest, Denver, CO, January 1997. 12. P.C. Walters, R.D. Pollard, J.R. Richardson, and B.M. Byzery. The effects of process variations on microstrip wafer calibration. Proceedings of IEEE Instrument and Measurement Technology Conference, May 1993, pp. 118–122.

© 2006 by Taylor & Francis Group, LLC

8.2-792

The Silicon Heterostructure Handbook

13. M.C.A.M. Koolen, J.A.M. Geelen, and M.P.J.G. Versleijen. An improved de-embedding technique for on-wafer high-frequency characterization. Proceedings of the Bipolar Circuits and Technology Meeting, Minneapolis, MN, September 1991, pp. 188–191. 14. H. Cho and D.E. Burk. A three-step method for the de-embedding of high-frequency S-parameter Measurements. IEEE Transactions on Electron Devices 38(6), 1991, 1371–1375. 15. S. Bousnina, C. Falt, P. Mandeville, A.B. Kouki, and F.M. Ghannouchi. An accurate on-wafer deembedding technique with application to HBT devices characterization. IEEE Transactions on Microwave Theory and Techniques 50(2), 2002, 420–424. 16. T.E. Kolding. General accuracy considerations of microwave on-wafer silicon device measurements. IEEE Microwave Theory and Techniques Symposium Digest, 2000, pp. 1839–1842. 17. T.E. Kolding. On-wafer calibration techniques for giga-Hertz CMOS measurements. IEEE International Conference on Microelectronic Test Structures 12, 1999, 105–110. 18. T.E. Kolding. A four-step method for de-embedding gigahertz on-wafer CMOS measurements. IEEE Transactions on Electronic Devices 47(4), 2000, pp. 734–740. 19. S.A. Wartenberg. Selected topics in RF coplanar probing. IEEE Transactions on Microwave Theory and Techniques 51(4), 2003, 1413–1421. 20. Agilent Technologies, Inc. Agilent Technologies, The Impedance Measurement Handbook. Agilent Technologies, Inc. Application Note, 2003.

© 2006 by Taylor & Francis Group, LLC

8.3 Industrial Application of TCAD for SiGe Development 8.3.1 8.3.2

Introduction............................................................... 8.3-793 SiGe Process Simulation ........................................... 8.3-794 Emitter Out-Diffusion . Boron Diffusion in SiGe Epitaxial Layer Base

8.3.3

David C. Sheridan, Jeffrey B. Johnson, and Rajendran Krishnasamy IBM Microelectronics

SiGe Device Simulation ............................................ 8.3-798 DC Calibration . AC Extraction and Calibration . Advanced RF Simulations

8.3.4 8.3.5 8.3.6

Application Examples ............................................... 8.3-800 Predictive Model Extraction..................................... 8.3-802 Summary .................................................................... 8.3-804

8.3.1 Introduction Due to rapid evolution of semiconductor technologies, the use of technology computer-aided design (TCAD) has become a critical enablement path in the industrial development cycle. The capability to perform numerical process and device simulation that is able to accurately predict device performance under various process conditions can significantly reduce the time and cost of technology development. With experimental wafer processing costs increasing dramatically for advanced generation technologies, the economic necessity for accurate predictive TCAD is apparent. But it is not only the wafer cost and device complexity that is continuing to drive the need for accurate predictive SiGe TCAD. Unlike the high-performance CMOS logic that can have years between products, the analog and mixed-signal market that encompasses the majority of SiGe applications demands significantly reduced product cycle time. This aggressive development schedule is generating a new paradigm for the relationship between TCAD, process development, and circuit designers. The traditional relationship of TCAD with technology development (Figure 8.3.1) consisted of having SIMS profiles, TEMs, and various other physical and electrical measurements provided to the TCAD engineer to calibrate the process and device models in parallel to the process development effort. The flow is then iterated until target device characteristics are achieved and representative hardware can be furnished to the compact modeling team. The compact modeling team must then fully characterize the devices to generate a physically based model parameter set, which is then combined with the complete technology design kit. Even if the process of record is known, circuit designers cannot begin to design for a significant period of time before the processing, characterization, and design kit cycle is complete. It is in this regard that TCAD can be used to impact the product design cycle time independent of the benefits contributed by increased process development time (Figure 8.3.1). With accurate process and device simulation early in the development cycle the TCAD engineer can create the electrical device 8.3-793 © 2006 by Taylor & Francis Group, LLC

8.3-794

TCAD flow

Technology definition

Calibration

Process experiments

Process simulations

Evaluate experiments

Device simulations

TARGETS?

TARGETS?

Qualification hardware

Model creation

Model creation

Designer lead time

}

3−8 months

Design kit to designers

Models to designers

Traditional TCAD role

1 month

3−6 months

Technology flow

1 WEEK

1− 4 months

The Silicon Heterostructure Handbook

FIGURE 8.3.1 Flow diagram showing the traditional TCAD relationship with technology development and the new extended paradigm.

characteristics to derive a initial predictive compact model. A compact model can then be provided to circuit designers in substantially earlier timeframe than traditionally available, based on calibrated physical simulations. As the technology development progresses, updates to the compact models can be provided to ensure the designers will have minimal design impact from the initial models to the final hardware-based models. The following sections demonstrate this new methodology with an overview of the TCAD process, device, and compact modeling strategy successfully employed in developing state-ofthe-art SiGe technologies.

8.3.2 SiGe Process Simulation Bipolar technologies dominated the early years of the microelectronics industry, and significant industrial and academic effort was focused on impurity diffusion characteristics that affected the vertical emitter–base–collector profiles of the bipolar transistor structures [1]. The incorporation of models that account for the co-diffusion of point defects (interstitials and vacancies) with dopant impurities addressed the important physical effects of oxidation-enhanced diffusion and transient-enhanced diffusion, forming the basis for the impurity diffusion models used in modern silicon process simulation programs. Such programs combine many different physical modeling capabilities including oxidation, diffusion of various dopants and their interactions, etching, deposition, and various approaches to simulating ion implantation.

© 2006 by Taylor & Francis Group, LLC

Industrial Application of TCAD for SiGe Development

8.3-795

The emergence of SiGe BiCMOS technologies has again made bipolar transistor simulation an important part of the demand for state-of-the-art process simulation capability. SiGe BiCMOS technologies utilize many of the same process operations as CMOS devices, and therefore, benefit directly from the accrual of simulation expertise gained from years of detailed submicron CMOS process modeling research. In the following discussion, it is assumed that the goal is not merely to generate an idealized SiGe HBT structure, for which task-detailed process simulation is not required, but rather to address the issue that dominates practical industrial applications of process and device simulation for SiGe BiCMOS technologies. Issues related to lateral diffusion of impurities generally dominate CMOS process simulation development, and the resultant physical models are equally applicable to issues related to vertical impurity diffusion profiles critical to SiGe HBT simulation. However, process simulation for SiGe HBTs is distinguished from CMOS process simulation by its critical dependence on Si–Si1x GexSi epitaxy and the interaction of polysilicon on silicon in the formation of the emitter and base structures. The challenge for SiGe HBT process simulation is to accurately simulate SiGe epitaxy and heavily doped polysilicon–silicon systems and combine this capability with the CMOS-specific process operations that dominate a modern SiGe BiCMOS technology.

Emitter Out-Diffusion Polysilicon is generally used to form the emitter region of modern high-speed SiGe HBTs as the polysilicon has a significantly lower surface recombination velocity to maintain high current gain with the continually scaled emitter diffusion depths. The emitter polysilicon is generally formed by a lowtemperature epitaxial process to reduce thermal effects on existing CMOS components, with impurities added either in situ during epitaxy or by ion implantation. The subsequent annealing and out-diffusion of the emitter dopants into the SiGe epitaxy creates the HBT emitter–base region. This positioning of the intersection of the emitter diffusion with germanium profile and both intrinsic and extrinsic base regions is fundamental in determining the transistors DC and AC characteristics. This annealing and out-diffusion of the emitter dopants, and their impact on the other dopant profiles under the emitter, is a complex combination of physical phenomena. Process-dependent physical effects such as arsenic (As) or phosphorus (P) deactivation mechanisms between As or P and vacancies, diffusion of dopants through interfacial oxide layers between the polyemitter and silicon, As or P clustering mechanisms, and diffusion differences of As or P in Si and strained or relaxed SiGe must be considered in the process simulation modeling to predictively fit the As or P emitter out-diffused profiles. Because of this complexity, TCAD cannot expect to be predictive over wide variations in process conditions by assuming diffusion models characteristic of CMOS technology development. Figure 8.3.2 illustrates this by plotting the profile generated by SIMS analysis of the emitter–base region in a modern SiGe BiCMOS technology. The arsenic distribution in the emitter can be divided into four distinct regions. In the first region a relatively uniform distribution of arsenic in deposited polycrystalline emitter, which can be calibrated based on process knowledge or testing of emitter sheet resistance structures. Second, the region where there is an As dopant segregation at the polysilicon–Si interface is calibrated using SIMS information and tuning the segregation and transport coefficients between polycrystalline emitter and single crystalline silicon. The third and fourth regions consist of the As diffusion regions in the pure Si cap and the strained SiGe epitaxial layers, respectively. The As (or P) deactivation mechanism with vacancy is modeled as [2]: nAs þ Si , AsnV þ I

(8:3:1)

where AsnV is an arsenic–vacancy cluster. The diffusion coefficients for As and P in strained SiGe epitaxial layer are modeled as [3]:

© 2006 by Taylor & Francis Group, LLC

8.3-796

The Silicon Heterostructure Handbook

Arsenic concentrations (cm−3)

10 22 10 21 10 20 1019 SIMS Simple Model Full Model

1018 1017 −0.05

0

0.05 Depth (µm)

0.1

0.15

FIGURE 8.3.2 Simple model is simulated As out-diffused profile from polysilicon emitter not considering all the physical effects. Full model is the simulated As out-diffused profile from polysilicon emitter considering As diffusion difference in Si and strained SiGe epitaxial layers and clustering between and As and B atoms.

DAs (SiGe) ¼ DoAs fi Di0 þ Di

n ni (SiGe)

" P

D (SiGe) ¼

DoP Di0

þ

Di

þ fv Dv0 þ Dv

n ni (SiGe)

2 # n n þ Di ni (SiGe) ni (SiGe)

(8:3:2)

(8:3:3)

where DoAs and DoP are the prefactor, fi and fv are the fraction of interstitial and vacancy mediated diffusion, Di0, Di, Dv0, Dv, Di ¼ represent the contributions from neutral, single-negatively charged interstitials, vacancies, and double-negative charged interstitials defects, n is the electron concentration, and ni(SiGe) is the intrinsic carrier concentration for SiGe. The individual contributions may require significant tuning of the large number of various parameters during process simulations in order to be predictive over a wide range of processing conditions. Figure 8.3.2 also shows a better prediction of the simulated profile with SIMS by carefully calibrating all the necessary physical models in each region (Equation (8.3.1) to Equation (8.3.3)).

Boron Diffusion in SiGe Epitaxial Layer Base Recently, the diffusion of the epitaxially deposited boron in modern SiGe HBTs has rivaled that of CMOS short-channel effects as a subject for research in silicon impurity diffusion. The epitaxial base in SiGe HBTs is a complex region in which B, Ge, and recently carbon (C) atoms are deposited. Point defects flow through the base as a result of P and As out-diffused from the subcollector, emitter diffusions, extrinsic base implants, and selectively implanted collector (SIC) implants, all of which influence the boron diffusion in the intrinsic base. Although point defect interaction with boron is typically considered in CMOS process simulation, in the SiGe or SiGeC base both the Ge and C concentrations have a strong influence in the base diffusion mechanics, and must be considered if a useful range of predictive simulation is expected. Two approaches to simulating the HBT vertical profile are typically used. The first approach illustrated in Figure 8.3.3 is to calibrate the B diffusion using only two physical factors that influence the diffusion of B in strained SiGe epitaxial layers. These two effects include the B diffusion coefficient that is modified by strain introduced by Ge mole fractions and GeB clustering reactions using [4], DB ¼ D0 exp ( EA =kT ) exp ( fS=kT )

© 2006 by Taylor & Francis Group, LLC

(8:3:4)

8.3-797

Industrial Application of TCAD for SiGe Development

14.0

------- Model O O SIMS

12.0

1019 1000⬚C & 20 sec

10.0

1050⬚C & 20 sec

1018

8.0

SIMS initial profile

Ge (%)

B concentrations (cm−3)

1020

6.0 1017 4.0 1016 0

0.03

0.06 0.09 Depth (µm)

0.12

2.0 0.15

FIGURE 8.3.3 Simulated B profiles compared with SIMS for B doping in strained SiGe base by taking into considerations strain from Ge and GeB clustering mechanisms on B diffusions. (From K Rajendran, D Villaneuva, P Moens, and W Schoenmaker. Modeling of clustering reaction and diffusion of boron in strained siixGex epitaxial layers. Solid State Electron. 47: 835–839, 2003. [7] With permission.)

and the effect of B atoms that are trapped by Ge atoms by forming a clustering or chemical reaction G þ B , GeB [5] with DBeff ¼ DB

1 1 þ (CGe =Cch )

(8:3:5)

where EA is the activation energy of the boron in silicon, S is the local strain due to the presence of Ge, f is the activation energy per unit strain, CGe and Cch are the Ge and characteristic concentrations, respectively. Coefficients f and Cch are the fitting parameters used to fit the SIMS profiles for the B diffusion in strained SiGe epitaxial layers. For SiGe:C profiles, the more complex, yet potentially more predictive approach, is to individually treat both the Ge and C influence on the B diffusivity. It is well known that C controls the B diffusivity in SiGe:C base by trapping the interstitials [6], while the Ge concentration affects the B diffusion by both strain and Ge:B clustering mechanisms [5]. For modeling purposes, difficulties arise in separating the individual contributions from the Ge and C on the B diffusion, especially since the effects contain the forward and reverse GeB clustering reactions and the forward and reverse C trapping of interstitials. Apart from these two major competitive physical effects, still more complex problems relating to calibration and predictability arise from clustering reactions of B þ As and B þ P, as well as nonuniform point-defect distributions from various adjacent regions of the SiGe base. The interstitial concentrations trapped by substitutional carbon (Cs) (to control the B diffusion) are modeled by both kick-out (KO) mechanism and Frank–Turnbull reactions (FT) [8]: Cs þ I , Ci

(8:3:6)

Ci þ V , Cs

(8:3:7)

where I and V are interstitial and vacancy concentrations and CCi is the interstitial carbon concentration. Careful tuning of both forward and reverse reaction coefficients with the previous B diffusivity variables is required for predictive models. Figure 8.3.4 shows the simulated B profile by taking into consideration all the physical models compared to experimental B SIMS profiles. These final process variables consist of a careful balance between the Ge and C impact on the base B diffusion.

© 2006 by Taylor & Francis Group, LLC

8.3-798

The Silicon Heterostructure Handbook

Boron concentrations (cm−3)

10 20

SIMS Model

1019

1018

1017

1016 0.15

0.2 0.25 Depth (µm)

0.3

FIGURE 8.3.4 Simulated B profile compared with SIMS in a strained SiGeC base with calibration of the percentage C and Ge contributions on B diffusion.

8.3.3 SiGe Device Simulation A final two-dimensional SiGe HBT process simulation structure is shown in Figure 8.3.5 showing considerable parallel to the experimental SEM. This simulated device structure can either be directly used as input for device simulation, or translated through a regridding procedure, resulting in a more robust device simulation grid. The SiGe HBT grid generation benefits from the central role played by epitaxy in the process simulation. Since epitaxy models typically consist of repeated depositions of thin layers of material, the mesh arising from the process simulation will contain a smooth, finely graded grid point distribution in the device active areas. Experience has shown that such grids can serve as excellent device simulation platforms with minimal adjustment. For HBT device simulation, the fundamental electrical and material properties of the SiGe layers must also be accurately captured through the physical device models in the device simulator. For SiGe devices, the most fundamental changes to the default Si models pertain to the rigid bandgap narrowing and the mobility models for the minority and majority carriers. In the device simulator the Ge content at each node is known from the process simulation and the relative valence and conduction bands for can then be modified by DEc , Si1x Gex ¼ ( 0:04X)

(8:3:8)

DEv , Si1x Gex ¼ (0:740X)

(8:3:9)

to determine the total bandgap change due to Ge (DEg,Ge). Distortion of the band structure due to the Ge-induced stress causes a change in the effective mass and consequently carrier mobilities. Low-field mobilities for both electrons and holes are equally important in bipolar device operation and must be accurately modeled in the device simulator. Experimental measurements, analytical models, and Monte Carlo simulations given in Refs. [9, 10] confirm an increase in hole mobility of up to 2.4 in strained Si1xGex layers compared to the unstrained Si values, while electron mobilities are generally reduced. The mobility model given in Ref. [11] shows excellent agreement with both published experimental data and Monte Carlo simulation data across Ge content and impurity concentration. Inclusion of the permittivity changes with Ge content is important for internal electric field and capacitance calculations. Since the fractional Ge percentage is known at each node, the effective permittivity can be calculated using linear interpolation between the pure Si and Ge values as

© 2006 by Taylor & Francis Group, LLC

Industrial Application of TCAD for SiGe Development

8.3-799

FIGURE 8.3.5 Experimental SEM and simulated cross section of a SiGe HBT demonstrating full two-dimensional process simulation capabilities.

«Si1x Gex ¼ 11:9(1 x) þ 16x

(8:3:10)

Similarly, the critical electric field dependence on Ge fraction can be approximated by EcritSi1x Gex 3 105 (1 x) þ 1 105 x

(8:3:11)

DC Calibration DC calibration logically starts with comparison of the HBT forward Gummel curves. The collector current calibration is predominantly dependent on the accuracy of the process emitter diffusion into the Ge and base profiles in combination with the bandgap narrowing models. Since the carrier properties at the emitter–base interface are strongly dependent on the interface processing conditions, polysilicon grain size, and impurity concentration, liberal adjustment to the emitter minority carrier polysilicon lifetimes are used to accurately match the experimental base currents. Extrinsic resistances that account for contact resistances and technology-dependent polysilicon resistances must be added only as needed depending on the comprehensiveness of the process simulation. Optimizations of layout variables such as collector contact configuration and isolation trench design require full two-dimensional process and device simulation of both the intrinsic and extrinsic device regions. For full predictive capability, all HBT breakdown modes must be able to be simulated accurately including BVcbo, BVceo, and BVcer . Reliable numerical simulation of such events is challenging, especially for modern high-performance HBTs, which rely on very nonuniform and relatively heavily doped collector and base regions to achieve performance targets. For HBT breakdown simulations, local-field models can perform adequately for high-power transistors with wide, low-doped collector regions. For more complex devices, experience has shown that hydrodynamic models [12] can reliably simulate HBT breakdown modes. The simulation user should expect to be prepared to tune critical parameters for such models, such as energy relaxation times and impact ionization thresholds, in the calibration phase of such modeling.

© 2006 by Taylor & Francis Group, LLC

8.3-800

The Silicon Heterostructure Handbook

AC Extraction and Calibration Small-signal Y- or S-parameters can be determined from device simulations performed using a wellknown 50 V terminated simulation method [13]. For high-speed devices, it is usually required to perform only a single small-signal solution at a predetermined ‘‘corner’’ frequency to extract the maximum operating frequency and maximum unilateral gain curves versus Ic. From this frequency point (usually between 5 and 30 GHz depending on the technology), 20 log10jH21j is calculated and straight line with a slope of 20 db/dec and extrapolated from this value to 0 db to give the ft value at each dc bias point. The unilateral gain fmax can be determined in a similar way by calculating U U¼

jy21 y12 j 4Re[y11 ]Re[Y22 ] 4Re[y21 ]Re[Y12 ]

(8:3:12)

at the simulation frequency and again extrapolating at a constant 20 dB/dec slope. Example simulation versus hardware plots of both ft and fmax are shown in Figure 8.3.7. The simulated S-parameters can not only be used to extract ac performance metrics such as ft and fmax, but also used to extract important information on the accuracy of individual calibration parameters such as rb, Ccb, Cbe, etc. Practical ac experimental characterization methods, such as extraction of base and emitter resistance using the impedance circle method and extraction of total junction capacitances using cold S-parameter simulations, can be applied to simulated data for a direct calibration of intrinsic components. Figure 8.3.6 shows the simulated and experimental S-parameter curves showing an excellent fit over a wide frequency range.

Advanced RF Simulations For RF applications, advanced simulations of high-frequency noise as well as intermodulation characteristics may be useful in the intrinsic device design phase but are often not considered necessary for predictive modeling. RF noise simulations are possible using impedance field methods [14] or hierarchal DD and HD methods from Monte Carlo simulations [15], but with results that are generally useful for only qualitative investigation of gross noise source phenomenon. Similarly, simulation of distortion through harmonic balance based methods [16] can prove to be informative for device design in determining the major components of nonlinearities that can affect important RF power metrics such as IIP3. However, these performance metrics can also be much more easily obtained through circuit simulation of the extracted compact model parameters from the simulated device characteristics.

8.3.4 Application Examples In self-aligned emitter–base SiGe HBT structures, the extrinsic emitter spacer determines the position of the extrinsic base implant in relation to the intrinsic emitter diffusion. The thickness of this spacer is critical in determining the inherent tradeoff between the fT and fmax of the device. If the spacer is too thin, extrinsic base implants will diffuse far into the intrinsic base region resulting in an increased base transit time, and lowering fT, but also favorably decreasing base resistance and increasing fmax. On the other hand, increasing the spacer has a positive effect on fT, but ultimately increases the base link resistance and lowers the peak fmax. Through full two-dimensional calibrated process simulation experiments and device simulations, an optimal spacer thickness was determined and resulted in a fT increase of 10 GHz through the extrinsic base process redesign. The simulations were used not only to maximize fT, but also to establish the sensitivity of fT to potential process variances. Figure 8.3.8 shows the excellent agreement of the device simulations with the subsequent process experiments. In order to increase the 90 GHz device to 120 GHz, an extensive device redesign that targeted the entire intrinsic device including the trapezoidal germanium profile as well as the as-deposited intrinsic

© 2006 by Taylor & Francis Group, LLC

8.3-801

Industrial Application of TCAD for SiGe Development

0.2

1 Re(S11) experiment Im(S11) experiment

Re(S11) simulation Im(S11) simulation

Re(S12) experiment Im(S12) experiment

Re(S12) simulation Im(S12) simulation

0.15

S12

S11

0.5 0.1

0 0.05

−0.5

0 0

20

40

60

80

100

120

0

20

Frequency (GHz)

40

60

80

100

120

Frequency (GHz)

2

1

1 0.5

Re(S22) experiment Im(S22) experiment

S22

S21

0

Re(S22) simulation Im(S22) simulation

−1 0 −2

Re(S21) experiment Im(S21) experiment

Re(S21) simulation Im(S21) simulation

−3

−0.5 0

20

40

60

80

100

120

0

20

Frequency (GHz)

40

60

80

100

120

Frequency (GHz)

FIGURE 8.3.6 Comparison of experimental and simulated S-parameter characteristics of a high-performance SiGe HBT.

140

fT, fmax (GHz)

120 100

Exp. fT Exp. fmax TCAD fT TCAD fmax

80

120 GHz

60

40 20 0.0001

90 GHz

0.001

0.01

0.1

Ic (A)

FIGURE 8.3.7 Comparison of experimental and simulated fT and fmax characteristics for 90 and 120 GHz SiGe HBT design points.

© 2006 by Taylor & Francis Group, LLC

8.3-802

The Silicon Heterostructure Handbook

95 90

Experiment TCAD

fT (GHz)

85 80 75

Emitter Pedestal

Spacer

70 65 −30

−20

−100

0

10

20

30

% Change in EB spacer

FIGURE 8.3.8 modifications.

Simulated prediction and experimental results for fT changes due to emitter–base spacer process

base was needed. These modifications in turn drove changes to the collector design to maximize the transit-time reduction offered by the redesign of the intrinsic base, since without modifications to the collector, reduced the reduced base transit-time benefits may be negated by corresponding increases in collector transit times with an earlier onset of Kirk effect. Experimental fT and fmax results, shown in Figure 8.3.7, validated the process changes ultimately recommended by the concurrent process and device simulation study. The new fT ¼ 120 GHz device design was compatible with the existing 0.18 mm CMOS technology in which it was embedded, as the process simulations used to define it contained all the CMOS etch, depositions, and thermal budget characteristic of the base CMOS technology [17]. This calibrated TCAD capability was then used to define the first fT ¼ 200 GHz and 300 GHz SiGe HBTs [18, 19]. These optimizations of peak device performance have always been the main object of TCAD, but for manufacturing purposes, sensitivity of the design point to process changes can be of equal priority. If the targeted design point is too sensitive to process variation, product yield and profitability can suffer, but it is often expensive and time consuming to produce large amounts of process window hardware during the development process. These tasks can be efficiently handled by well-calibrated two-dimensional device simulations. Figure 8.3.9 shows a simulated ‘‘sweet spot’’ plot of the targeted fT, fmax, and BVceo for a given technology. The central contour of the plot exhibits all possible processing conditions that still meet the device targets, emphasizing that design point ‘‘B’’ is considerably less sensitive to implant dose and energy than design point ‘‘A.’’ Such simulations can also be used to produce predictive process statistics for TCAD based compact models.

8.3.5 Predictive Model Extraction Traditionally, the information provided by the TCAD process and device experiments had only direct impact on the process and device development cycle time, but did not have an immediate benefit to the design cycle time. But since the previously described approach to TCAD simulation encompasses the complete process and device simulation, it is elementary to produce the entire suite of ac and dc device characteristics that are needed to extract a suitable model for circuit design. Generating the compact model can be difficult and time consuming due to the amount of required data and number of modeling parameters. A genetic algorithm (GA) model generation methodology has been developed [20] that uses only a minimal set of extracted parameters together with the use of a physically bounded genetic algorithm

© 2006 by Taylor & Francis Group, LLC

8.3-803

Industrial Application of TCAD for SiGe Development

8⫻1013 7⫻1013 6⫻1013 Dose

Design Point B

SweetSpot Criterias met 2 Criterias met 1 Nothing

5⫻1013 4⫻1013

Design Point A

3⫻1013 2⫻1013 1⫻1013 160

180

200

220

240

260

280

300

Energy

FIGURE 8.3.9 Results of a simulated design of experiments showing process sensitivity of two optimized design points.

0.005 T = 25⬚C forced Ib experiment VBIC95 fit to experiment VBIC95 fit to simulation

0.004

Ic (A)

0.003 0.002 0.001 0.000 0

1

2 Vcb (V) SiGe npn modeling

3

4

FIGURE 8.3.10 Comparison of simulated forced-Ib output characteristics, VBIC model extracted from the simulated data, and a VBIC model extracted from experimental hardware demonstrating excellent predictive modeling capability.

to efficiently optimize a model parameter set. Genetic algorithms have many advantages over more familiar optimization approaches, in particular robustness to getting caught in local minima, no requirements on calculation of functional derivatives or solution of large sets of linear equations, and easy specification of variable constraints. The simulated electrical characteristics are compiled and used as part of the genetic fitness function, allowing the algorithm to mutate the model variables until a predetermined number of generations or ‘‘fitness’’ is achieved. This significantly reduces the extraction and optimization effort as well as eliminating inaccuracies resulting from commonly used fitting methods to approximate model equations, allowing designers early access to technology models. Figure 8.3.10 shows the genetically fit output curves derived from the TCAD-simulated results, and the experimentally derived VBIC model, demonstrating excellent predictive TCAD and model extraction process.

© 2006 by Taylor & Francis Group, LLC

8.3-804

The Silicon Heterostructure Handbook

8.3.6 Summary This chapter intended to demonstrate the impact that TCAD can have in industrial SiGe technology development, with emphasis on the ability to simulate the full development cycle from the most sensitive process variation to the development of predictive compact models. As developmental wafer costs and process cycle are driven to more aggressive schedules, industry will continue to leverage TCAD as a core component of SiGe technology development.

References 1. RB Fair. Explanation of anomalous base regions in transistors. Appl. Phys. Lett. 22:186, 1973. 2. PM Rousseau, SW Crowder, PB Griffin, and JD Plummer. Arsenic deactivation enhanced diffusion: a time, temperature, and concentration study. J. Appl. Phys. 84:3593–3601,1998. 3. S Eguchi, JL Hoyt, CW Leitz, and EA Fitzgerald. Comparison of arsenic and phosphorus diffusion behavior in silicon–germanium alloys. Appl. Phys. Lett. 80:1743–1745, 2002. 4. NEB Cowern, PC Zalm, P Vander Swis, DJ Gravesteijm, and WB de Boer. Diffusion in strained Si(Ge). Phys. Rev. Lett. 72: 2585–2588, 1994. 5. K Rajendran and W Schoenmaker. Studies of boron diffusivity in strained Si1xGex epitaxial layers. J. Appl. Phys. 89:980–987, 2001. 6. H Rucker, B Heinemann, W Ropke, R Kurps, D Kruger, G Lippert, and HJ Osten. Suppressed diffusion of boron and carbon in carbon-rich silicon. Appl. Phys. Lett. 44:1682–1684, 2000. 7. K Rajendran, D Villaneuva, P Moens, and W Schoenmaker. Modeling of clustering reaction and diffusion of boron in strained Si1xGex epitaxial layers. Solid State Electron. 47:835–839, 2003. 8. JL Ngau, PB Griffin, and JD Plummer. Modeling the suppression of boron transient enhanced diffusion in silicon by subtitutional carbon incorportation. J. Appl. Phys. 90:1768–1778, 2001. 9. T Manku, JM McGregor, A Nathan, DJ Roulston, JP Noel, and DC Houghton. Drift hole mobility in strained and unstrained doped Si1xGex alloys. IEEE Trans. Electron Dev. 40:1990–1996, 1993. 10. LE Kay and TW Tang. Monte Carlo calculation of strained and unstrained electron mobilities in Si1xGex using an improved ionized-impurity model. J. Appl. Phys. 70:1483–1488, 1991. 11. V Palankovski and S. Selberherr. Critical modeling issues of SiGe semiconductor devices. Proceedings of the 6th Symposium Diagnostics and Yield: Advanced Silicon Devices and Technologies for ULSI Era, Warsaw, 2003, pp. 1–11. 12. M Bartels, S Decker, B Neinhus, KH Bach, A Schuppen, and B Meinerzhagen. Comprehensive hydrodynamic simulation of an industrial SiGe heterobipolar transistor. Proceedings Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 105–108. 13. S. Laux. Techniques for small-signal analysis of semiconductor devices. IEEE Trans. Electron Dev. 32:2028–2037, 1985. 14. W Shockley, JA Copeland, and RP James. The impedance field method of noise calculation in active semiconductor devices. Quantum Theory of Atoms, Molecules, and the Solid-State. New York: Academic Press, 1966. 15. C Jungermann, B Neinhus, and B Meinerzhagen. Hierarchical 2-D DD and HD noise simulations of Si and SiGe devices — Part I: Theory. IEEE Trans. Electron Dev. 49:1250–1257, 2002. 16. B Troyanovsky, Z Yu, L So, and RW Dutton. Relaxation-based harmonic balance technique for semiconductor device simulation. Technical Digest ICCAD, San Jose, 1995, pp. 700–703. 17. A Joseph, D Coolbaugh, M Zierak, R Wurthrich, P Giess, Z He, X Liu, B Orner, J Johnson, G Freeman, D Alghren, B Jagannathan, L Lanzerotte, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/ fmax) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146.

© 2006 by Taylor & Francis Group, LLC

Industrial Application of TCAD for SiGe Development

8.3-805

18. JB Johnson, A Stricker, AJ Joseph, and JA Slinkman. A technology simulation methodology for ACperformance optimization of SiGe HBTs. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp 21.4.1–21.4.4. 19. JS Rieh, B Jagannahan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D. Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D. Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2002, pp. 771–774. 20. DC Sheridan, JB Johnson, and J Watts. Use of genetic algorithm optimization techniques for bipolar compact modeling. Presented at the Workshop on Compact Modeling for RF/Microwave Applications, Toulouse, France, 2003.

© 2006 by Taylor & Francis Group, LLC

8.4 Compact Modeling of SiGe HBTs: HICUM 8.4.1 8.4.2

Introduction............................................................... 8.4-807 HICUM Basics........................................................... 8.4-808 Internal Transistor . External Base–Emitter Region . External Base–Collector Region . Collector–Substrate Region . Other Effects

M. Schro¨ter University of California at San Diego

8.4.3 8.4.4 8.4.5 8.4.6 8.4.7

Geometry Effects and Scaling................................... 8.4-814 Parameter Determination Methodology ................. 8.4-816 Model Hierarchy........................................................ 8.4-819 Trends ......................................................................... 8.4-819 Summary .................................................................... 8.4-821

8.4.1 Introduction The demand for high-speed wireless and fiber-optic communications has pushed the development of SiGe and SiGeC epitaxial base processes into the flow of CMOS mainstream technologies. This combination of narrow base width, due to epitaxial growth techniques, and lateral footprint reduction, due to the utilization of advanced CMOS lithography, has resulted in a tremendous performance boost of Si-based bipolar transistors (e.g., Chapter 3 and Ref. [1]). In order to capture the resulting new electrical and physical effects occurring in such technologies, improved compact models have been developed such as the HIgh-CUrrent Model (HICUM) [2–4], that provide the capability of accurately predicting circuit performance. This capability has become extremely important due to the soaring mask cost, which can run as high as US$ 1 million for a 0.1 mm-BiCMOS process. Thus, saving just one design cycle and its associated mask cost quickly pays off any model development and support cost. The development of sophisticated compact models takes 10 to 20 years before they actually become suitable for production circuit design. HICUM development started in the early 1980s [5, 6], originally targeting the design of high-speed fiber-optic circuits using geometry scaling for circuit optimization [7, 8]. Later on, the model was extended to accurately simulate high-frequency small-signal operation [9]. Over time, many effects occurring in advanced Si–SiGe heterojunction bipolar transistors (HBTs) have been added [10–13], and further developments still ongoing following the advancements in bipolar transistor technology and design [36, 37]. A detailed documentation of HICUM model equations can be found in Ref. [3]. It should be emphasized that a successful production compact model and its development have to satisfy many requirements from different directions (as visualized in Figure 8.4.1). Since such a model embraces a major portion of the respective transistor theory, completely presenting its physical background and the derivation of its equations cannot be accomplished with the limited available space here. 8.4-807 © 2006 by Taylor & Francis Group, LLC

8.4-808

The Silicon Heterostructure Handbook

Process development Include all physical effects Model parameters without wafers Rapid et al. of process variations "Debugging" of process issues

Simulator

Param. extraction Well-defined, fast, reliable Using standard equipment Min. parameter interaction

Compact model

EC topology, equations to fit in different interfaces I, Q contin. differentiable Modular, easily extendable

Circuit design Accurate, valid over wide range Smooth geometry scaling (for optim.) Computationally fast and reliable Easy to understand

FIGURE 8.4.1 Requirements for compact model development.

Therefore, the goal of this chapter is to provide an overview on HICUM and its associated infrastructure that needs to be in place to deploy the model for production design purposes. This includes: (i) the basic operating principle of HICUM, (ii) how the physical effects in advanced transistors are covered, (iii) the geometry scaling methods used, (iv) the parameter determination methodology, (v) how a hierarchy of models can be generated in an efficient way, and (vi) new research directions. For all the above topics, the reader is guided through the related literature that contains more detailed explanations and background material.

8.4.2 HICUM Basics This section contains a concise overview on the operating principle of HICUM, with the focus on its equivalent circuit (EC) and the most important bias-dependent equations. Geometry scaling, although required for a model, will be discussed in Section 8.4.3. Usually, model construction is described in a ‘‘bottom–up’’ approach, starting with a one-dimensional (intrinsic) formulation and then extending step by step to the external transistor [2, 3]. In contrast, this section provides a complementary view at HICUM, following a ‘‘top–down’’ approach, in which the overall structure of the transistor is considered first and then broken down into separate physical regions and their associated ECs. If not otherwise specified, an npn transistor and forward operation is assumed. (Note that proper modeling of inverse biasing is still necessary from a simulator point of view.) Figure 8.4.2 shows a schematic cross section of a Si–SiGe bipolar transistor fabricated in a nonselective epitaxial growth process. (Please refer to the Chapter 3 of this book and further literature therein for a more detailed description of SiGe-HBT technologies.) The cross section is partitioned into various regions, indicated by the different line styles. Each of the subdivision is represented by a respective EC, resulting in a physics-based EC. In order to enhance the correspondence between EC and cross section, the internal nodes are inserted into the cross section. The portion determining the fundamental transistor characteristics is the internal transistor under the emitter with the corresponding EC elements following nonlinear bias dependences. In contrast, most elements of the external (parasitic) EC portions — except for the junction capacitances — have simple linear bias-dependent equations.

Internal Transistor Bipolar transistors are mostly employed due to their speed advantage. Speed is closely related though to the charges stored in the transistor. Hence, HICUM is based on an accurate large- and small-signal description of the charge-storage elements, which are discussed below first.

© 2006 by Taylor & Francis Group, LLC

8.4-809

Compact Modeling of SiGe HBTs: HICUM

Base

Emitter

Base

Collector

External BE region

l b

BE spacer

n+

w, x Silicide p+ poly

E' SiGe

P+

B*

External BC region

External BC region

SiO2

n+ sinker

n-epi p+

n-SIC C' Internal transistor n+ buried layer

Collector−substrate region

p− substrate

External BC region S'

rSu

Collector-substrate region

S

Q jS CSu

iTS ijSC Q'BCx

Q"BCx

ijBCx

rBx

Q jEp

B

Q dS

CrBi

ijBCi

B*

ijBEp C'Eox

rCx

C' QjCi

iAVL

Qr

B' QjEi

r*bi iBEt

C

iT Qf

ijBEi E

C"Eox External BE region

rE

∆Tj

Internal transistor

P

R th

C th

E

FIGURE 8.4.2 Upper figure: schematic deep trench-isolated SiGe-HBT cross section with main regions identified by surrounding lines. Lower figure: large-signal HICUM/Level2 equivalent circuit with parasitic substrate transistor and self-heating network; network portions related to the main regions in the cross section are identified by the same line style.

A large-signal model for the charge elements starts with a bias-dependent description of the smallsignal quantities. The depletion capacitances CjEi and CjCi, which dominate the charge storage at low current densities, are nonlinear functions of the voltages across the respective internal junctions. Their integration yields the large-signal bias-dependent internal BE and BC depletion charges:

© 2006 by Taylor & Francis Group, LLC

8.4-810

The Silicon Heterostructure Handbook

QjEi ¼

Z

VB0 E0

CjEi (v)dv

and

QjCi ¼

0

Z

VB0 C0

CjCi (v)dv

(8:4:1)

0

The respective analytical expressions for CjEi(VB0 E0 ) and CjCi(VB0 C0 ) have been extended beyond the classical equation found in textbooks in order to not only avoid numerical instabilities but also to increase the model accuracy. For instance, CjCi includes the punch-through of the BC space–charge layer to the buried layer which, beyond a certain reverse voltage, can lead to a significantly larger (feedback) capacitance than the classical equation predicts; also, both capacitances contain a smooth limitation to their maximum value at high forward bias. Toward high current densities, the minority charge becomes important, which starts to significantly exceed the depletion charge around the peak transit frequency. The minority charge is spatially distributed over the whole internal transistor and is partitioned into a forward and reverse component, Qf ¼

Z

iTf

t f (i)di

and

Qr ¼ t r iTr

(8:4:2)

0

with tf and tr as forward and reverse transit time, which include contributions from the base, emitter, and collector region. The bias dependent tf can be partitioned into a low-current component tf0 that depends on VB0 C0 (or VC0 E0 ) only, and a high-current component Dtf that depends on both the voltage VC0 E0 and forward component ITf of the (quasi-static) transfer current IT [13]. Variation in both base width (Early effect) and BC space–charge region width is included in the description of tf0, allowing to model transistors with a wide range of collector-doping profiles. The increase of tf at high current densities (via Dtf ) is determined by the mobile (electron) charge in the collector, which compensates the fixed space–charge. As a result, the electric field in the collector becomes bias dependent as shown in Figure 8.4.3, and its value Ejc starts decreasing with IT. Once Ejc approaches the critical field, the carrier velocity in the BC SCR starts to drop, leading to an increase in minority charge storage both in the base and — for a BC homojunction — also in the collector and to a decrease of fT. The current, at which the critical field occurs, is designated as ICK and can be calculated analytically as a function of VB0 C0 as well as doping and width of the collector region [14, 29]. This has been one of the central equations in the minority charge storage formulation of HICUM due to its physics-based nature. Note that ICK is also related to circuit design since it can often be used during optimization for sizing transistors of certain

20

Eϕ Eψ

10 0

ICK

E (kV/cm)

−10 −20 −30 −40 −50 −60 −70 −80 −90

IC Ejc VBC = 0 V

xjc

IC/(mA)=0.074,0.155,0.225,0.3,0.37,0.45,0.51

0.05

0.1

0.15 x (µm)

0.2

0.25

FIGURE 8.4.3 Spatial dependence of the electric field in the collector of a SiGe HBT with the collector current density ( ¼ IT) as parameter [36]. xjc is the BC junction depth, Ew and Ec, respectively, is the field derived from electron quasi-Fermi potential and electrostatic potential, respectively.

© 2006 by Taylor & Francis Group, LLC

8.4-811

Compact Modeling of SiGe HBTs: HICUM

circuit types, such as differential pair switches in CML and mixers. The bias dependence of the transit time is composed by the components in the various transistor regions, which are described in a physicsbased approach [13, 36]. The transfer current of Si BJTs and SiGe HBTs can be expressed in a compact form by the GICCR (cf. Appendix A.3 and [10]) exp iT ¼ iTf iTr ¼ Is

VB0 E0 VT

exp VVB0TC0

Qp,T =Qp0

(8:4:3)

All nonideal effects and their bias dependence are taken into account in the weighted hole charge Qp,T ¼ Qp0 þ hjEi QjEi þ hjCi QjCi þ Qf ,T þ Qr

(8:4:4)

with transfer current ‘‘related’’ minority charge Qf,T ¼ QnB þ QpE, low þ hfE DQpE þ hfCQpC. The ‘‘D’’ indicates the difference (increase) of charge in addition to the low-current density component. With respect to the original one-dimensional GICCR given in the appendix, a few modifications are required to make it work for actual (three-dimensional) transistor structures: (i) only the high-current portion of the emitter minority charge is multiplied with the weighting factor, because the lowcurrent portion is calculated as QnB þ QpE,low ¼ tf0iTf via the low-current transit time tf0, which is very difficult to partition into its components by measurements. (ii) Qp0 assumes a modified value compared to the one-dimensional zero-bias charge due to the actual three-dimensional structure. In addition, the names of the weighting factors, which are HICUM parameters, are slightly different to better indicate their application: e.g., the index ‘‘i’’ in hjEi and hjCi indicates that the factors are applied only to the charges of the internal transistor. The weighting factors, their dependence on the Ge profile shape, and their impact on the transfer current are discussed in Appendix A.3. Since the charges are based on a continuous formulation of the respective small-signal quantities, iT is continuously differentiable. The current gain in a bipolar transistor is a derived quantity defined by the physically independent mechanisms governing base and collector current; hence, the base currents in HICUM are modeled independently of the transfer (collector) current. This allows to approximate realistic shapes of the measured forward current gain as a function of collector current using two components for ijBEi in Figure 8.4.2, representing back injection into the emitter, iBEi, and recombination within the BE space– charge region, iREi, vB0 E0 vB0 E0 DQfB 1 þ IREiS exp 1 þ ijBEi ¼ IBEiS exp mBEi VT mREi VT tBrec

(8:4:5)

The last term in the above equation takes into account excess recombination (with the lifetime tBrec) at the BC barrier that forms at high collector current densities due to the Ge concentration drop [15]. The current flowing across the (forward biased) internal BC junction, ijBCi(vB0 C0 ), can be described analogously to Equation (8.4.5), but with the last term omitted. One of the most difficult elements to describe in a compact analytical form is the internal base resistance rBi, which depends on geometry, temperature, and transistor operating mode. It represents the (time- or frequency-dependent) distributed voltage drop caused by the internal base current flowing in perpendicular direction of the transfer current. This leads to a current crowding at the perimeter edge for sufficiently high current densities. Note though that in advanced transistors with narrow emitter stripes and fairly low internal base sheet resistance, the effect of dc emitter current crowding is negligible while dynamic (ac or transient) current crowding can be very significant. Only for power transistors, the effect of dc current crowding sometimes may become relevant. HICUM contains an accurate compact analytical formulation for the bias dependence of rBi that includes emitter current crowding and is valid up to very high current densities [17, 18]. The

© 2006 by Taylor & Francis Group, LLC

8.4-812

The Silicon Heterostructure Handbook

frequency-dependent current crowding for small-signal operation is also explicitly accounted for (to first order) through the shunt capacitance CrBi in Figure 8.4.2 [9]. Unfortunately, a similar calculation as for the small-signal case is not possible for the general case of (high-speed) large-signal switching. Therefore, using CrBi in the latter case can lead to incorrect results and is not recommended. The only known accurate solution here is a multi- or (at least) two-transistor model as suggested in Ref. [19]. Investigations have shown though that at least for the class of high-speed current-mode circuits the different values of rBi during switching-off and switching-on tend to compensate each other [11], giving fairly accurate results using the dc value. The avalanche current iAVL can become a quite complicated function of bias toward high current densities. However, investigations have shown [16] that for circuits that are sensitive to breakdown, the three-dimensional pinch-in effect (caused by the voltage drop across the internal base resistance) is the dominant failure mechanism compared to one-dimensional breakdown at high current densities. Thus, rather than offering a computationally expensive one-dimensional breakdown model, HICUM contains only a weak avalanche model with the main purpose of indicating the onset of avalanche in order to avoid biasing or operation in this region. In addition though the formulation can still be used to construct a distributed three-dimensional model to properly capture the onset of the three-dimensional pinch-in effect.

External Base–Emitter Region The lateral extension of the emitter doping underneath the spacer region (cf. cross section in Figure 8.4.2) creates the emitter perimeter junction. Together with the BC junction under the spacer, this forms a periphery transistor with an associated transfer current iTp and corresponding charge elements [9]. For practical applications, i.e., circuit design and model parameter extraction, such a complicated two-transistor model is not attractive and needs to be simplified. This can be done by combining the transfer current components of the perimeter and internal transistor into a single transfer current source with iT ¼ iTi þ iTp as shown in the EC of Figure 8.4.2. Since so far Equation (8.4.3) is only applied to iTi, the GICCR needs to be extended to the two- and three-dimensional case as described in the appendix to retain a consistent description of the impact of nonideal effects on the total transfer current. This results in enlarged values for also the saturation current and hole charge components. The consequence of this transformation is a one-transistor model with an effective internal transistor, which includes portions of the currents and charges of the physical perimeter transistor in a consistent way. The leftover portions of the perimeter transistor elements in Figure 8.4.2, ijBEp, QjEp and part of 00 00 QjCx (included in QBCx ) are then kept at the respective (perimeter) nodes and, together with the emitter 00 resistance rE and part of the parasitic spacer capacitance, QEox , form the EC of the external BE region.

External Base–Collector Region This region consists of a resistive layer on top of the external BC junction and (shallow trench) oxide. Fundamentally, this structure corresponds to a transmission line, which is quite lossy though and can be treated as a distributed RC network. Up to not too high frequencies typical for high-speed circuit applications, the electrical behavior can be represented by a simple p equivalent circuit consisting of 0 00 0 QBCx rBx QBCx as shown in Figure 8.4.2. Note that QBCx also contains the bias-independent parasitic capacitance of the oxide underneath the base polysilicon layer and contact. Furthermore, the diode current ijBCx of the (effective) external BC junction is included in the EC; notice that this current is only relevant under hard-saturation condition.

Collector–Substrate Region Figure 8.4.4 shows a magnified view of this region. Fundamentally, at high frequencies the electrical behavior of the CS junction also needs to be represented by a distributed RC network.

© 2006 by Taylor & Francis Group, LLC

8.4-813

Compact Modeling of SiGe HBTs: HICUM

C

S

SiGe SiO2 n+ sinker

n-epi

p+ CSp

n+ buried layer C jSb

DTI

p− substrate Bottom

Periphery

FIGURE 8.4.4 Enlarged schematic cross section of the collector substrate region with corresponding physics-based equivalent circuit (DTI ¼ deep trench isolation).

The latter consists of the CS depletion and isolation capacitance as well as the resistive regions of the external collector (i.e., buried layer, collector sinker) and the substrate. A simplified lumped EC that is still physics-based and sufficiently accurate for circuit applications [1, 3, 20] is shown in Figure 8.4.4. The signal path consists mainly of a bottom portion, indicated by the respective depletion capacitance CjSb, and a perimeter portion, indicated by the DTI capacitance CSp. If the DTI is replaced by pn-junction isolation — like in more cost-conscious process technologies — CSp has to be replaced by the respective perimeter depletion capacitance. Depending on the process and layout, the EC for the collector–substrate region can be even more complicated than that in Figure 8.4.4 [3, 20]. For SOI technologies, there is still a bottom capacitance, which is to first-order bias independent though. Since in general, the substrate contact can be anywhere and be of any layout shape, calculating the substrate resistance components is a three-dimensional geometry-dependent problem, for which no general analytical solution exists that is suitable for compact models. Therefore, for modeling it is recommended to have a fixed substrate contact layout (i.e., a transistor p-cell), which is also used in circuit applications. This allows at least a direct characterization of the substrate impedance and resistance for given (critical) transistor layouts. In the built-in version of HICUM in simulators (cf. Figure 8.4.2), the nonlinear CS depletion charge QjS and the external collector resistance rCx are represented by lumped elements in order to keep the model as simple as possible. The substrate-coupling network also consists of a lumped substrate resistance, rSu, and the associated dielectric capacitance CSu. If a more sophisticated substrate-coupling network is required, the built-in network can be interpreted as the bottom path, and any desired network can be easily added via a subcircuit. Note again that the determination of the substrate coupling resistance remains the responsibility of backend parasitics extraction, unless the transistor layouts employed in circuits are identical to those used for parameter extraction regarding the location and shape of the substrate contact. The EC in Figure 8.4.2 also contains a simple substrate transistor model, consisting of the transfer current iTS, the base current elements ijSC and ijBCx, the charge storage elements QdS and QjS, and the series resistances rBx, rCx, rSu, which are partially shared with the regular transistor EC. Because operation in the substrate current regime is generally not preferred and can usually be avoided with a proper layout, the purpose of the substrate transistor element in HICUM is mostly to indicate the turn-on of its operation in a circuit with a minimum of modeling effort.

© 2006 by Taylor & Francis Group, LLC

8.4-814

The Silicon Heterostructure Handbook

Other Effects The temperature-dependent description in HICUM is physics-based, with smooth extensions toward very low and very high temperatures for those expressions that otherwise would become numerically unstable [3]. The respective equations are based on TCs of material parameters such as mobility, intrinsic carrier density, and saturation velocity, allowing even reasonably accurate predictions of the transistor temperature behavior without extracting the parameters [4, 8, 14]. To achieve maximum speed, modern bipolar transistors have to be operated at fairly high current densities. This leads to significant self-heating, which is most pronounced for larger transistors used in driver applications and is taken into account by the separate network consisting of Rth and Cth in Figure 8.4.2. Although heat transfer is a distributed process, with usually at least a fast (nanosecond scale) and a slow (microsecond scale) characteristic time constant [21], only a simple single-pole network has been implemented to maintain a reasonable model complexity for most applications. If modeling of distributed effects is required, such as for power amplifier design, the thermal node DTj in Figure 8.4.2 is accessible in circuit simulators and allows adding a sophisticated thermal (coupling) network [22]. Since the temperature increase at node DTj requires the re-calculation of all temperaturedependent model parameters and bias-dependent equations, simulations with self-heating tend to be much more time-consuming than if the effect is neglected. Also, convergence problems in circuit simulators can occur if the transistor is operated such that it becomes thermally unstable (thermal runaway). For communication circuit design, the prediction of noise and distortion behavior as a function of bias, geometry, and frequency is important. Noise simulation is accomplished in HICUM by adding the physical description of noise sources to the dissipative equivalent circuit elements [3, 23, 24]. For lf (flicker) noise, a simple 1/f behavior is included in the model the corner frequency of which as a function of bias can be adjusted with two parameters. For describing hf noise and distortion behavior, which are both given by the EC and bias-dependent description of its elements [23–27], no separate model parameters are required.

8.4.3 Geometry Effects and Scaling It cannot be emphasized enough that compact model development has to keep the application, i.e., mainly circuit design, in mind. Therefore, priority should be assigned to modeling those effects that matter most for circuit design. One important requirement in this regard is transistor sizing, which for a circuit designer is usually more important than detailed modeling of second-order physical effects. From a design point of view, it is desirable to be able to vary the transistor configuration, defined by the emitter width and length together with the number of contacts (or stripes) for base, emitter, and collector as well as their spatial arrangement. For example, when designing a low-noise amplifier, usually specifications for bandwidth and noise have to be met simultaneously. Unfortunately, maximum speed and minimum noise in a transistor do generally not occur at the same bias point. Thus, a compromise needs to be found by properly selecting the transistor size that gives the best overall circuit performance. There are many other examples [7], where transistor sizing is essential to achieving the circuit specifications for a given process technology. To speed up the design job, numerical optimizers have become available which, however, require continuously differentiable geometry scaling for (compact) models. A geometry scalable compact model requires that all of its EC elements are described as a function of layout dimensions. While this is fairly simple for some elements it can become very complicated for other elements in a given process as will be shown later. Note that geometry effects can not only depend on the device dimensions but also, for given dimensions, on bias and frequency (cf. tf and rBi). Also, sometimes certain vertical dimensions are allowed to be changed if requested by a foundry customer. Below, the presently most important geometry scaling effects from a hf point of view and their modeling in HICUM are briefly reviewed.

© 2006 by Taylor & Francis Group, LLC

8.4-815

Compact Modeling of SiGe HBTs: HICUM

All elements of the internal transistor, except rBi, are scaled proportional to the effective emitter area AE which — according to section ‘‘Internal Transistor’’ — is given by lumping together the bottom and perimeter components of the transfer current: LE0 iT ¼ iTi þ iTp ¼ jTi AE0 þ jTp LE0 ¼ jTi AE0 1 þ gC ¼ jTi AE , AE0

(8:4:6)

LE0 is the emitter perimeter length and gC ( ¼ jTp/jTi) is a process constant [28, 29]. Hence, the effective electrical emitter area AE can be used to scale the transfer current iT correctly for arbitrary emitter sizes. This also applies to the associated (total) minority charge. With smaller emitter size, the peak of fT not only broadens but also shifts toward higher current densities. This three-dimensional effect is caused by collector current spreading and is taken into account analytically in the expressions for the critical current ICK and the minority charge Qf [29], that influence the transfer current via the GICCR. Since for the BE depletion charge and the base current flowing across the BE junction the ratio of perimeter to internal portion is usually different from iTp/iTi, the ‘‘leftover’’ portions are included as effective periphery elements QjEp and iBEp in Figure 8.4.2, preserving their total values. Also, the impact of the perimeter minority charge, which is included now in the effective internal transistor, on the input impedance of the internal transistor is taken into account by an effective internal base resistance rBi* [9]. HICUM contains an accurate compact formulation for the geometry dependence of the base resistance components rBi* and rBx [18, 19]. The equation takes into account different contact configurations, such transistors with single-base contacts, which have become quite common due to the use of low-ohmic silicides and in which part of the current has to flow around the emitter as shown in Figure 8.4.5.

B

E

p+ SiO2 (a)

bo

bp

bl

b

bl

bp

6

5

4 contact

l/2 3

2 bl

1 lp (b)

0 0

1

2

3

4

5

6

FIGURE 8.4.5 Base resistance considerations for a single-base transistor: (a) schematic cross section with conducting plane through base and (b) current flow and equipotential lines in the base plane.

© 2006 by Taylor & Francis Group, LLC

8.4-816

The Silicon Heterostructure Handbook

The two-dimensional current distribution, including dc current crowding effects, is captured by explicit analytical equations that are based on simple physics-based considerations. The elements of the external transistor portions are scaled with the respective dimensions as described in Refs. [3, 8, 18]. For instance, the total external BC depletion capacitance scales with an expression similar to Equation (8.4.6), but with the external BC junction area, ABCx ¼ ABC AE, and perimeter length LBCx, where ABC is the total BC junction area. With increasing frequency and reduced device dimensions various parasitics become important. This includes the isolation capacitances, especially the portion CEox resulting from the BE spacer region, the spatial topology of which can be quite complicated. Further, parasitics that may need to be included are the capacitances between the metal studs as well as the self-inductances of the fingers, which are not covered by backend extraction. All these parasitics belong to the transistor itself and have to be dealt with already during parameter extraction. Scaling becomes even more complicated for the elements of the substrate and the thermal network due to the large variety of layouts and device designs (e.g., junction isolation, deep trench, SOI, metallization). Basically, different sets of scaling equations or even (fast) numerical methods have to be used for those cases. All these scaling equations further extend the physics-based formulation of HICUM toward addressing challenging circuit design and simulation tasks, including statistical modeling. Since a complete description of the scaling equations for bipolar transistors is beyond the scope of this paper, the reader is referred to, e.g., Refs. [3, 8] and the references therein. It has been mentioned several times that the large variety of bipolar transistor fabrication processes and device designs require quite a sophisticated set of suitable scaling equations. Therefore, implementing those equations into circuit simulators along with the bias and temperature-dependent equations makes the model code messy, difficult to understand, and to maintain. The latter holds especially because geometry equations usually need to be improved or adapted to a particular process often at different times than the other equations. The result would be a large burden for the model developer to coordinate the respective code changes, tests, and releases in the many-circuit simulators the model is available in. As a consequence, accurate geometry scaling equations for (so far) five different BJT and HBT process technologies have been implemented in a separate tool. The program, TRADICA [8], enables a flexible model and parameter generation for practically relevant configurations, spanning from minimum size single-base over large multifinger transistors to coupled transistor cells, and including all important physical effects. Figure 8.4.6 provides an overview on the operating principle of the program. The input data consist of process-related parameters such as sheet resistances and per area capacitances, which are obtained from parameter extraction, and of device-relevant dimensions, that are obtained from design rules and SEMs of actually fabricated transistors (cf. Section 8.4.4). The initial program development started out in the early 1980s as sizing aid for circuit designers, a feature that has been expanded in the recent past. This origin underlines the close relationship of HICUM development with circuit design. Note though, that HICUM and TRADICA are independent tools, i.e., using HICUM does not depend on the availability of TRADICA. More recently, a set of analytical equations for calculating the transistor parameters and electrical performance as a function of process variations (in both vertical and lateral direction) have been added, enabling the generation of ‘‘skewed’’ model parameters. This capability can be used together with a design-of-experiment-based response-surface method, for statistical modeling and predicting the impact of process changes on electrical device behavior in a computationally efficient way. In fact, since physicsbased models for passive devices are also available in TRADICA, the parameter correlation between devices on the same chip can even be taken into account. Thus, the modular integration into a design system enables the simulation of parametric yield and device matching.

8.4.4 Parameter Determination Methodology The typical methodology for model parameter determination relies on adjusting the parameters to fit a set of measured electrical characteristics of a transistor with given geometry. Unfortunately, this

© 2006 by Taylor & Francis Group, LLC

8.4-817

Compact Modeling of SiGe HBTs: HICUM

Design rules

Process specific parameters Process control monitor (PCM) data

sheet resistances, capacitances per area, sat, current per area, ...

Transistor configurations E width and length, number of E, B, C stripes, location

Critical bias points TRADICA

⇒

transistor sizing

Model characteristics Model parameters device libraries

(fT, fmax, NFmin ... as function of geometry and bias)

for specified bias points

FIGURE 8.4.6 Overview on the TRADICA program operation principle.

generally does not lead to physics-based model parameters and, thus, prohibits any predictive or statistical modeling. Most importantly though, every transistor configuration that is required for circuit design, has to be available on a test chip and to be fitted. Since test chip space and measurement time and, hence, transistor configurations are quite limited, such a methodology severely limits circuit design. In contrast, HICUM parameter extraction is based on a well-defined and small set of test structures, which then enables parameter generation also for any other configuration that is not available on a test chip. The parameter determination methodology is described in more detail in Refs. [3, 30–32]. Also, a GUI-based extraction tool is available in Ref. [33]. ‘‘Production’’ HICUM parameters have been delivered for a variety of process technologies from foundries such as Atmel, IBM, Jazz, ST, TSMC; for publicly available results see Refs. [1, 3, 4, 12, 13, 24–27, 31]. Due to the lack of space, only a few selected examples can be presented here, which are key results related to the high-frequency transistor behavior and are typical for the accuracy achievable with HICUM in an industrial environment. The transit frequency fT shown in Figure 8.4.7 is an important figure-of-merit characterizing the performance of a technology. It also includes the information on how accurately the charge storage (connected to the base terminal) of a transistor is described by a compact model. As Figure 8.4.7 demonstrates, the experimental results for a SiGe(C) process are quite well described by HICUM. Noise figure NFmin and equivalent noise resistance Rn versus frequency are shown in Figure 8.4.8 for a 150 GHz production process. The bias point is typical for low-noise applications. HICUM gives good agreement for Rn over the whole frequency range and for NFmin at high frequencies. The observable deviation at lower frequencies is caused by the missing correlation between collector and base noise, which has not yet been implemented in circuit simulators. This is confirmed by the thin line that results from a HICUM-generated small-signal model (SSM) with added correlation. Figure 8.4.9 contains for a two-tone distortion measurement the output power both at the fundamental frequencies (f01 ¼ 5 GHz, f02 ¼ 5.01 GHz) and the third-order intermodulation frequencies (2f1 f2 ¼ 4.99 GHz, 2f2 f1 ¼ 5.02 GHz). Despite a bias point at a fairly high current density and the

© 2006 by Taylor & Francis Group, LLC

8.4-818

The Silicon Heterostructure Handbook

0.1

140

1

JC (mA/µm2)

10

120

fT (GHz)

100 80 60 40 20 0 0.1

1

10

IC (mA)

100

FIGURE 8.4.7 Transit frequency fT versus collector current (density) for STs 120 GHz SiGeC BiCMOS process: comparison between measurement (symbols) and HICUM (lines). VBC/V ¼ 0.6, 0.4, 0.2, 0, 0.25, 0.5; AE0 ¼ 0.25 12.65 mm2.

NFmin(dB), Rn /50Ω

3 NFmin 2

HICUM Rn/50Ω SSM & corr

1

HICUM SSM & corr

0 1

5

9

13 17 Frequency (GHz)

21

25

28

FIGURE 8.4.8 Minimum noise figure and equivalent noise resistance versus frequency for JazzSemi’s 150 GHz SiGeC-BiCMOS process: comparison between measurements (symbols) and HICUM (lines); IC ¼ 0.52 mA, VCE ¼ 1 V, AE0 ¼ 0.2 10.16 mm2. 20 0

Pout (dBn)

−20

Pout(f1,1)

f1,1 = 5.00 GHz f1,2 = 5.00 GHz

−40 IMD3

−60 −80

−100 −120 −140 −160 −50

−40

−30

−20 Pin (dBm)

−10

0

5

FIGURE 8.4.9 Output power versus input power for a high-voltage transistor of Atmel’s SIGE1 process: comparison between measurement (symbols) and HICUM (lines) for two-tone intermodulation distortion (IMD). IC ¼ 25 mA ( fT,peak), VCE ¼ 2.5 V; AE0 ¼ 2 1.3 49.7 mm2.

© 2006 by Taylor & Francis Group, LLC

Compact Modeling of SiGe HBTs: HICUM

8.4-819

relatively high frequencies for the considered power transistor with 22 GHz peak fT, the model shows excellent agreement. At lower input power, even better results were obtained [27].

8.4.5 Model Hierarchy For design tasks often (at least initially), a fairly simple model is sufficient. However, driven by the increasing number of physical effects to be accounted for, most of the present developments seem to be moving toward more complicated models, less and less understood by circuit designers. Model complexity is defined by number of nodes and elements in the EC along with the element equations and number of parameters. For final verification and some other cases though, more complicated models (even more than in Figure 8.4.2) are required. Thus, providing a model hierarchy is very attractive for meeting the very different design needs. As discussed in Ref. [34], it is most suitable to choose a medium complexity model as reference, from which both simple and more sophisticated models can be generated without any additional parameter extraction effort. Using TRADICA, such an approach has been realized with reasonable coding and maintenance effort, resulting in the (presently existing) hierarchy shown in Figure 8.4.10. The standard HICUM form (Level2) serves as reference model, from which — by adequately simplifying both EC and equations — HICUM/Level0 [35] and the standard SPICE Gummel–Poon model (SGPM/Level0) can be generated. Since all model parameters are calculated from process-specific parameters and layout dimensions, distributed models (HICUM/Level4, SGPM/Level4) can be generated at the same time. Notice that parameter extraction is performed only once for HICUM/Level2, ensuring a consistent set of models. Within each of the complexity levels, the model user can still create intermediate levels by turning off certain effects independently (without the necessity of reformulating equations).

8.4.6 Trends Considering recent SiGe(C) technology development with HBTs exceeding even 300 GHz transit frequency, applications are increasingly becoming limited by ‘‘parasitic’’ effects rather than by the intrinsic transistor. Examples for important parasitic effects to be modeled more accurately include BC breakdown, intra- and inter-device substrate and electrothermal coupling as well as the metal contact studs and the connections between, e.g., amplifier cells. Reliable modeling of extreme cases such as power amplifiers is still a challenge, also for circuit simulators when dealing with self-heating and interdevice coupling. Fast, preferably compact, solutions are developed to account for the abovementioned effects during model generation. Providing an efficient statistical design capability is a demand from circuit designers that has been existing for a long time. There has also been an increasing interest by both foundries and designers to have this feature available already at the early stage of process development. To address these needs, physics-based statistical models for the complete device portfolio are developed and implemented in TRADICA [38, 39]. This allows to include the correlations between parameters of different devices and to offer an integrated modular solution within a design system. For predictive modeling, TRADICA is coupled to a device simulator and an automated parameter extractor, enabling fast investigations of the impact of intentional process changes in electrical characteristics of devices and circuits. Improving the equations of the internal transistor toward a more compact HICUM formulation with more features is presently pursued. One of the goals is to model the bias dependence of the electric field in the BC region, which controls the transistor behavior at higher current densities, namely the voltage and current-dependent transit time, base–collector capacitance, avalanche breakdown and even nonlocal effects in the collector region. First versions of such an approach were presented in Refs. [36, 37]. Coding in circuit simulators has been a major bottleneck to deploy improved compact models and keep pace with process development. Most recently, model compilers have been developed and become

© 2006 by Taylor & Francis Group, LLC

8.4-820

The Silicon Heterostructure Handbook

HICUM/Level0 ijSC

C CCox

CjCx

IjBC

CjCi

Cdc

CjE

CdE

SGPM/Level0

S CjS

rCx

S CjS

C

iAVL

CCox

ijBC

CjCx

B B

rB

CEox

ijBE

rD

CEox

Cth

SGPM/Level2

rsu S ijSC ijSC B

Q

dS

CrBi

B* Q

rBx Q

Eox

Q

rCx Q

jCi

dC

iBEt

Q

Q

jEi

C

iBCx

Q

B

iT

ijBEi

Q

E

E

Q

iBEt

ijBEp

Eox

rCx

su

Q

jCi

Q

Q

jEi

C

dC

B rBi

jEP

iT dE

ijBEi E

∆Tj P

C ijBCi

dS

B* Q

rBx

rE

Q

iTS

ijSC

dE

S

jS

iAVL

B rBi

jEp

ijBEp

Q

su

C ijBCi

TSU

S

S Q

CdE

E

E

HICUM/Level2

iTS

CjE

C

rE

Rth

P

jS

CdC

ijBE

∆Tj

rE

Q

CjCi

B B

E

E

g jSC r Cx

C

rE

Rth

Cth E

HICUM/Level4, SGPM/Level4

C

C T2n

Tkn

T1n

E

E

rsu S Tk3

T23

B*

C n C Tk2

T22

Tn E

E

cl

∆rCx

C cK ∆rCx

S

Cw

S

Tcl

TcK

rCxI

C

S Tw

E

C

C Tk1

C

S

B

T12

∆rCx

Csu

T31

T21

T11 z

E

E

E

E y

Symmetry lines

FIGURE 8.4.10 Model hierarchy generated by TRADICA. HICUM/Level2 is the reference model, while ‘‘Level0’’ indicates simplified and ‘‘Level4’’ indicates distributed models with various types of partitioning.

available [40, 41], that can transfer a Verilog-A model description into C code suitable for the compiled interfaces of various mainstream simulators. This capability will not only tremendously speed-up model deployment, but will also allow users to adapt existing models much quicker to their needs, such as special process features and design applications, than in the past.

© 2006 by Taylor & Francis Group, LLC

Compact Modeling of SiGe HBTs: HICUM TABLE 8.4.1

8.4-821

Summary of HICUM Features

High accuracy . Over wide bias range including the high-current region . For high-speed nonlinear large-signal (switching) operation . Up to very high frequencies in small-signal operation . Over wide geometry (transistor configuration) and temperature range Physical effects . Two-dimensional and three-dimensional effects such as emitter periphery injection, emitter current crowding, collector current spreading, distributed external base–collector region . (Weak) avalanche breakdown and BE tunneling . Temperature dependence (including parasitics and self-heating effects) . Parasitic substrate transistor and simple substrate coupling network . Non-quasi-static effects for both charge and current . Impact of bandgap variation in (SiGe) HBTs . All standard noise mechanisms Parameter determination . Well-defined set of test structures . Well-defined methodology and procedures . Commercial tools Simulator availability: ADS, SPECTRE, ELDO, HSPICE, MWO (cf. website in Ref. [3])

8.4.7 Summary The basic operation principle of the advanced physics-based compact bipolar transistor model HICUM has been reviewed. The accurate description of small-signal quantities, such as depletion capacitance and transit time, as a (nonlinear) function of bias, temperature, and geometry results ‘‘by construction’’ not only in continuously differentiable relations for charges and transfer current but also in accurate modeling of the large-signal switching behavior, including harmonic distortion at high frequencies. Moreover, the small-signal quantities can be measured via the terminals using standard methods and equipment. The main features of the model are summarized in Table 8.4.1. HICUM development follows an integrated approach that is oriented toward circuit design and process development. Necessary infrastructure and CAD tools for flexible geometry scaling, parameter determination, and generating a model hierarchy, have been discussed in Sections 8.4.3 to 8.4.5. ‘‘Production’’ HICUM parameters have been delivered for a variety of foundry technologies; additional experimental results can be found in many publications, such as those listed below.

Acknowledgments Many individuals have contributed to the development of HICUM and related tools. In addition to those individuals mentioned already in Ref. [2], the author would like to thank Dr. B. Ardouin (XMOD), Dr. H. Jiang (JazzSemi), Dr. P. Zampardi (Skyworks Inc.), and Dr. P. Sakalas, S. Lehmann, H. Tran, Y. Zimmermann, H. Wittkopf, K. Moebus (all with the Chair for Electron Devices and Integrated Circuits, Dresden University of Technology), for their feedback and help with model and tool development. Financial and in-kind support are gratefully acknowledged from Atmel, JazzSemi, ST, IBM, Agilent, AWR, Cadence, Mentor, XMOD, and IHP.

References 1. M. Schroter. Compact device modeling for RF circuit design. Invited Tutorial at the IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 2002. 2. M. Schroter. Staying current with HICUM. IEEE Circuits and Devices Magazine 18(3), 16–25, 2002. 3. M. Schroter. ‘‘HICUM — a scalable physics-based compact bipolar transistor model. Documentation at www.iee.tu-dresden.de/iee/eb/ or www.xmodtech.com.

© 2006 by Taylor & Francis Group, LLC

8.4-822

The Silicon Heterostructure Handbook

4. H.-M. Rein and M. Schroter. A compact physical large-signal model for high-speed bipolar transistors at high current densities — Part II: Two-dimensional model and experimental results. IEEE Trans. Electron Dev. 34, 1752–1761, 1987. 5. H.-M. Rein, H. Stu¨bing, and M. Schroter. Verification of the integral charge-control relation for highspeed bipolar transistors at high current densities. IEEE Trans. Electron Dev. 32, 1070–1076, 1985. 6. M. Schroter and H.-M. Rein. A compact physical large-signal model for high-speed bipolar transistors including the high-current region. NTG meeting, Wu¨rzburg, May 1986. 7. H.-M. Rein. Very-high-speed Si and SiGe bipolar ICs. Proc. ESSDERC, 1995, pp. 45–56. 8. M. Schroter, H.-M. Rein, W. Rabe, R. Reimann, H.-J. Wassener, and A. Koldehoff. Physics and process-based bipolar transistor modeling for integrated circuit design. IEEE J. Solid-State Circuits 34, 1136–1149, 1999. See also: TRADICA User’s Guide and www.xmodtech.com. 9. A. Koldehoff, M. Schroter, and H.-M. Rein. A compact bipolar transistor model for very highfrequency applications with special regard to narrow stripes and high current densities. Solid-State Electron. 36, 1035–1048, 1993. 10. M. Schroter, M. Friedrich, and H.-M. Rein. A generalized integral charge-control relation and its application to compact models for silicon based HBTs. IEEE Trans. Electron Dev. 40, 2036–2046,1993. 11. M. Schroter and H.-M. Rein. Investigation of very fast and high-current transients in digital bipolar circuits by using a new compact model and a device simulator. IEEE J. Solid-State Circuits 30, 551–562, 1995. 12. M. Schroter, Z. Yan, T.-Y Lee, and W. Shi. A compact tunneling current and collector breakdown model. Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis, 1998, pp. 203–206. 13. M. Schroter and T.-Y. Lee. A physics-based minority charge and transit time model for bipolar transistors. IEEE Trans. Electron Dev. 46, 288–300, 1999. 14. M. Schroter and H.-M. Rein. Transit time of high-speed bipolar transistors in dependence on operating point, technological parameters, and temperature. Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis, 1989, pp. 85–88. 15. S. Tiwari. A new effect at high currents in heterostructure bipolar transistors. IEEE Electron Dev. Lett. 9, 142–144, 1988. 16. M. Rickelt and H.-M. Rein. A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits. IEEE J. Solid-State Circuits 37, 1184–1197, 2002. 17. H.-M. Rein and M. Schroter. Experimental determination of the internal base sheet resistance of bipolar transistors under forward-bias conditions. Solid-State Electron. 34, 301–308, 1991. 18. M. Schroter. Simulation and modeling of the low-frequency base resistance of bipolar transistors in dependence on current and geometry. IEEE Trans. Electron Dev. 38, 538–544, 1991. Also, M. Schroter. Modeling of the low-frequency base resistance of single base contact bipolar transistors. IEEE Trans. Electron Dev. 39, 1966–1968, 1992. 19. H.-M. Rein. Improving the large-signal models of bipolar transistors by dividing the intrinsic base into two lateral sections. Electron. Lett. 13, 1977, S.40–S.41. 20. M. Pfost, H.-M. Rein, and T. Holzwarth. Modelling substrate effects in the design of high-speed Sibipolar ICs. IEEE J. Solid-State Circuits 31, 1493–1497, 1996. 21. D.J. Walkey, T.J. Smy, D. Marchesan, H. Tran, C. Reimer, T.C. Kleckner, M.K. Jackson, M. Schroter, and J.R. Long. Extraction and modeling of thermal behavior in trench isolated bipolar structures. IEEE Bipolar and BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 97–100. 22. D.J. Walkey et al. Equivalent circuit modeling of static substrate thermal coupling using VCVS representation. IEEE J. Solid-State Circuits 37, 1198–1206, 2002. 23. S. Voinigescu et al. A scalable high-frequency noise model for bipolar transistors and its application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid-State Circuits 32, 1430–1439, 1997. 24. P. Sakalas et al. Analysis of microwave noise sources in 150 GHz SiGe HBTs. RFIC Symp., Tech. Dig., 2004.

© 2006 by Taylor & Francis Group, LLC

Compact Modeling of SiGe HBTs: HICUM

8.4-823

25. P. Sakalas, M. Schroter, P. Zampardi, and M. Racanelli. Microwave noise in III–V and SiGe-based HBTs: Comparison, trends, numbers (Invited paper). 18th Int. Conf. on Noise and Fluctuations, Canary Islands (Spain), 2004. 26. M. Schroter, D.R. Pehlke, and T.-Y. Lee. Compact modeling of high-frequency distortion in Si integrated bipolar transistors. IEEE Trans. Electron Dev. 47, 1529–1539, 2000. 27. P. Sakalas, M. Schroter, W. Kraus, and L. Kornau. Modeling of SiGe power HBT intermodulation distortion using HICUM. Proc. ESSDERC, Lisboa, 2003, pp. 311–314. 28. H.-M. Rein. A simple method for separation of the internal and external (peripheral) currents of bipolar transistors. Solid-State Electron. 27, 1984, S.625–S.632. 29. M. Schroter and D.J. Walkey. Physical modeling of lateral scaling in bipolar transistors. IEEE J. SolidState Circuits 31, 1484–1491, 1996; 33, 171, 1998. 30. T.-Y. Lee and M. Schroter. Methodology for bipolar compact model parameter extraction. At www.iee.tu-dresden.de/iee/eb/ or www.eigroup.org/cmc. 31. T.-Y. Lee, M. Schroter, and M. Racanelli. A scalable model generation methodology for bipolar transistors for RF IC design. IEEE Bipolar and BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 171–174. 32. D. Berger, D. Celi, M. Schroter, M. Malorny, T. Zimmer, and B. Ardouin. HICUM parameter extraction flow for a single transistor geometry. IEEE BCTM, Monterey, CA, 2002, pp. 116–119. 33. XMOD Technologies. The HICUM Aperitif Toolkit. User Manual, 2002. www.xmod-tech.com. 34. M. Schroter. Compact bipolar transistor modeling — issues and possible solutions. Invited paper at WCM, Proc. International NanoTech Meeting, San Francisco, CA, 2003, pp. 282–285. 35. M. Schroter, H. Jiang, S. Lehmann, and S. Komarow. HICUM/Level0 — a simplified compact bipolar transistor model. IEEE BCTM, Monterey, CA, 2002, pp. 112–115. 36. M. Schroter and H. Tran. Modeling of base–collector junction related effects in heterojunction bipolar transistors. Proc. Compact Modeling Workshop at the International NanoTech Meeting, Boston, MA, Vol. II, March 2004, pp. 102–107. 37. S. Wilms and H.-M. Rein. Analytical high-current model for the transit time of SiGe HBTs. Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 199–202. 38. M. Schroter, H. Tran, and W. Kraus. Germanium profile design options for LEC-SiGe HBTs. SolidState Electron. 48, 1133–1146, 2004. 39. M. Schroter. Modeling of high-speed bipolar transistors for predictive circuit design and optimization. Natural Sciences and Engineering Research Council of Canada, Project Report 1996. 40. See www.tiburon-da.com. 41. L. Lemaitre, C. McAndrew, and S. Hamm. ADMS — automatic device model synthesizer. Proc. Custom Integrated Circuits Conf., 2002, pp. 27–30.

© 2006 by Taylor & Francis Group, LLC

8.5 Compact Modeling of SiGe HBTs: Mextram 8.5.1 8.5.2

Introduction............................................................... 8.5-825 Transfer Current ........................................................ 8.5-827 Quasi-Neutral Base . Epilayer

8.5.3

Recombination Currents........................................... 8.5-831 Intrinsic Transistor Region . Extrinsic Quasi-Neutral Regions . Weak Avalanche Current

8.5.4 8.5.5

Substrate Current ...................................................... 8.5-834 Charges and Capacitances ........................................ 8.5-835 Depletion Capacitances . Diffusion Charges . Distributed and Non-Quasi-Static Charges

Slobodan Mijalkovic´ Delft University of Technology

8.5.6 8.5.7

Thermal Phenomena................................................. 8.5-838 Parameter Extraction ................................................ 8.5-840

8.5.1 Introduction The worldwide interest in SiGe heterojunction bipolar transistors (HBTs) as a commercial IC technology is growing rapidly [1]. The corresponding circuit design activities essentially depend on accurate compact models of SiGe HBTs in all relevant modes of the transistor operation. This chapter gives an overview of the vertical bipolar transistor compact model Mextram (the acronym of the ‘‘most exquisite transistor model’’) and its capabilities to meet SiGe HBT circuit design challenges. The Mextram has been introduced by De Graaff and Kloosterman at Royal Philips Electronics in 1985 [2]. Appearing to be the fifth existing bipolar transistor model (after the previous four described in Ref. [3]), the first Mextram release was introduced as Level 501. Following the requirements of the continuous technology development, Mextram has appeared later in several update releases: Level 502 in 1987 [4], Level 503 in 1994, and Level 504 in 2000 [5]. Figure 8.5.1 shows the equivalent circuit of the Mextram model as it is specified in its latest release (Level 504). The branches representing model currents and charges are schematically associated with different physical regions of a bipolar transistor separated by the base–emitter (BE), base–collector (BC), and substrate–collector (SC) junctions. All current and charge branches in Mextram are given as explicit functions of external and internal nodal potentials and there are no implicit modeling variables that require internal iterations. The governing Mextram equations are formulated having in mind NPN transistors, but the model can be equally well used for PNP transistors by simple change of the current and charge polarity. The main transfer current IN in Mextram, as in the Gummel–Poon model [6], is evaluated in the quasi-neutral base (QNB). However, the mathematical appearance of the equations governing the transfer current is quite different in comparison to the Gummel–Poon model. The principle novelty was to abandon the classical Gummel–Poon charge control relationship between the transfer current and charges [7]. The integral base charge (at high injection) is evaluated in Mextram directly from the 8.5-825 © 2006 by Taylor & Francis Group, LLC

8.5-826

The Silicon Heterostructure Handbook

C

C 0BE

p-type base

Q StE

RCC B1

RE E1

QtE

Qtex Iex + IB3

Isub

B2 Iavl

Qex

Qepi n-type epilayer n+ buried layer

ISF QtS

IN

IB2

QBC QtC

XIsub XIex

n + emitter QE

IB1 QBE

IB1B2 XQtex

S I B1

QB1B2

RBC

XQex

E

C0 BC

B

C2 Iepi C1

p-type substrate

S

FIGURE 8.5.1 Mextram equivalent circuit.

junction low at QNB boundaries. Moreover, the effects of a graded Ge profile in QNB [8] are physically addressed in the transfer current description. A distinguishing feature of the Mextram model is the description of the epilayer transfer current Iepi. It is employed for intensive physical modeling of the quasi-saturation phenomena including the base widening, Kirk effect [9], hot-carrier behavior in the epilayer, and advance modeling of the distortion effects [10]. S , IB2, IB3, Iex, and XIex in the Mextram equivalent circuit The diode-like injection currents IB1, IB1 describe various recombination currents in the quasi-neutral and depletion transistor regions. The recombination in the modulated QNB, which is particularly important for SiGe HBT applications [11], is also included. The effect of a distributed hole injection across BE junction is described by an additional current branch IB1B2. Mextram provides also a sophisticated model for the weak avalanche current in the branch Iavl. The contribution of the parasitic PNP transistor transfer current to the substrate current, represented by the current sources Isub and XIsub, is implemented using a simplified Gummel–Poon integral charge control relationship. S , QtC, Qtex, The dynamic currents are accounted for by the depletion capacitances (charges) QtE, QtE XQtex, and QtS as well as diffusion charges (capacitances) QBE, QBC, QE, Qepi, Qex, and XQex in the intrinsic and extrinsic transistor regions as shown in Figure 8.5.1. The BC depletion capacitance is particularly equipped to account for the full depletion of the epilayer and the charge current modulation. An additional charge branch QB1B2 accounts for the distributed high-frequency effects in the intrinsic transistor base. Thermal phenomena are addressed in Mextram by a simple thermal impedance (thermal resistance and capacitance in parallel) and a power dissipation source. Moreover, the model is equipped with the physical temperature-scaling rules. A set of temperature-scaling parameters is extracted along with the corresponding electrical model parameters in the straightforward procedure. The physical background of the Mextram parameters also provides an excellent framework for the geometrical [12] and configurational scaling [13]. Mextram has been already used intensively in various SiGe HBTs applications including highperformance SiGe HBT integration [14], low-noise amplifiers [15, 16], and SiGe HBTs phototransistors [17]. As an additional illustration of Mextram capabilities, some results of the Mextram parameter extraction for an IBM SiGe HBT test sample device are given at the end of this chapter.

© 2006 by Taylor & Francis Group, LLC

8.5-827

Compact Modeling of SiGe HBTs: Mextram

8.5.2 Transfer Current The transfer current is maintained by the electron flow in vertical direction from the emitter contact to the collector buried layer and further up to the collector contact. The pure ohmic regions on that way are represented by the constant emitter resistance RE ¼ RE and collector resistance RCC ¼ RCC. The electron current density Jn in QNB and epilayer is assumed to obey the one-dimensional drift-diffusion equation Jn ¼ qmn n(x)

dfn (x) dx

(8:5:1)

where n is the electron concentration, fn is the electron quasi-Fermi potential, mn is the electron mobility, q is the elementary charge, and the x-axis is directed from the emitter toward the epilayer region. Moreover, in the model derivation the electron and hole concentrations are related by the pn product p(x)n(x) ¼

n2ie (x) exp

fpB fn (x) VT

(8:5:2)

where p is the hole concentration, nie is the position-dependent effective intrinsic carrier concentration, fpB is the constant hole quasi-Fermi level in the QNB, and VT is the thermal voltage.

Quasi-Neutral Base The electron current density (8.5.1), and transfer current IN, can be expressed in QNB with the help of the pn product (8.5.2) as Jn ¼

fpB fn (x) IN n2 (x) d exp ¼ qVT mn (x) ie p(x) dx AE VT

(8:5:3)

where AE is the effective emitter area. Integrating (8.5.3) for constant Jn in the interval (xBE, xBC), where xBE and xBC denote the edges of the QNB, we have [7] IN ¼

fpB fn (xBE ) fpB fn (xBC ) qn2i AE exp exp G(p;xBE ,xBC ) VT VT

(8:5:4)

where ni is the intrinsic carrier concentration and the functional G(p;x1 ,x2 ) ¼

ð x2 x1

2 p(x) ni dx mn VT nie (x)

(8:5:5)

is well known as the Gummel number. The transfer current (8.5.4) is implemented in Mextram as IN ¼

IS VB2 VE1 VB2 VC2 exp exp gB VT VT

(8:5:6)

G(p; xBE , xBC ) 0 , x0 ) G(NA ; xBE BC

(8:5:7)

where gB ¼

© 2006 by Taylor & Francis Group, LLC

8.5-828

The Silicon Heterostructure Handbook

0 0 is the relative change of the Gummel number in QNB with BE and BC junction biases, xBE and xBC denote the edges of the QNB at zero bias, NA is the acceptor-doping concentration in the base and 0 0 ,xBC ) is transfer saturation current. The quasi-Fermi potentials in Equation (8.5.4) IS ¼ qn 2i AE /G(NA;xBE are replaced in Equation (8.5.6) by the corresponding Mextram nodal biases. Notice that the value of the electron quasi-Fermi potential fn(xBC) in Equation (8.5.4) is not directly associated with the nodal bias VC2. Instead an effective value V*C2 is used in Mextram (Level 504) as provided by the epilayer model description. The relative Gummel number gB in Equation (8.5.7) is further expressed in Mextram as product gB ¼ gBWgBH where

gBW ¼ 1 þ

0 0 G(NA ; xBE ,xBE ) G(NA ; xBC ,xBC ) þ 0 0 0 0 G(NA ; xBE ,xBC ) G(NA ; xBE ,xBC )

(8:5:8)

G(n; xBE ,xBC ) : G(NA ; xBE ,xBC )

(8:5:9)

and gBH ¼ 1 þ

The role of gBW is to describe the relative change of the Gummel number in QNB with the modulation of BE and BC depletion widths (Early effect). On the other hand, the term gBH accounts for the relative change of the Gummel number in QNB due to the minority electron concentration at high injection currents. Assuming a linear graded Ge profile (and bandgap Eg) in QNB, as shown in Figure 8.5.2, for the spatial dependence of (ni/nie)2 in Equation (8.5.5) holds:

ni nie

2

DEG / exp x qVT wB0

(8:5:10)

0 0 0 0 where wB0 ¼ xBC xBE is the width of QNB and DEG ¼ Eg(xBE ) Eg(xBC ) is the bandgap difference over the base (in eV), both evaluated at zero bias. Integrating Gummel numbers in Equation (8.5.8) for constant NA and mn using Equation (8.5.10), the term gBW becomes [18]

gBW

DEG wBE DEG wBC 1 exp 1 exp VT wB0 VT wB0 þ ¼1þ DEG DEG 1 exp 1 exp VT VT

(8:5:11)

0 0 xBE and wBC ¼ xBC xBC define the modulation of BE and BC depletion regions. Notice where wBE ¼ xBE that in the limiting case DEG ¼ 0, the term gBW is reduced to

NA = const QtC DEG

Eg

QtE xBE

0 xBE

FIGURE 8.5.2 Doping and bandgap distribution in the QNB.

© 2006 by Taylor & Francis Group, LLC

0 xBC

xBC

8.5-829

Compact Modeling of SiGe HBTs: Mextram

0 gBW ¼1þ

wBE wBC þ wB0 wB0

(8:5:12)

representing the relative change of QNB width or Early factor [3]. The relative variation of the depletion widths in Equation (8.5.12) is implemented in Mextram in terms of the BE and BC depletion charges QtE and QtC as wBE(C) QtE(C) ¼ wB0 VER(F) CJE(C)

(8:5:13)

where CJE and CJC are zero-bias BE and BC depletion capacitances while VER and VEF are reverse and 0 becomes identical to the Early factor proposed in Ref. [19] for forward Early voltages. In that way, gBW silicon bipolar transistors. The model parameters VER and VEF may be interpreted for SiGe HBTs as the effective Early voltages that define the modulation rate of QNB width instead of the Gummel number. For an alternative way to account for the Early effect in SiGe HBTs, see Ref. [20]. The high-injection therm gBH is implemented in Mextram in terms of minority electron concentration as gBH ¼ 1 þ

1 n(xBE ) n(xBC ) þ 2 NA NA

(8:5:14)

which for simplicity assumes uniform nie and linear distribution of n in QNB. The required normalized electron concentrations in Equation (8.5.14) are evaluated solving the system of electroneutrality equation p ¼ n þ NA and pn product (8.5.2) at xBE and xBC as 2 n(x) nie VB2 fn (x) ¼F exp NA VT NA2 2z pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ F(z) ¼ 1 þ 1 þ 4z

(8:5:15)

* where fn(xBE) ¼ VE1 and fn(xBC) ¼ VC2 . This is also the place where the forward knee current IK is introduced in Mextram using

n2ie IS ¼ NA2 IK

(8:5:16)

but in principle it has the same physical role in the description of the high-current effects as the corresponding knee current parameter of the Gummel–Poon model [21].

Epilayer The drop of the electron quasi-Fermi potential over epilayer is essential for the correct evaluation of fn(xBC) and the transfer current IN if the transistor is operating in quasi-saturation [22]. In that case, the epilayer region, between 0 and wepi having uniform donor doping concentration ND, can be split into quasi-neutral injection region 0 < x < xi and drift region xi < x < wepi as shown in Figure 8.5.3. From the pn product (8.5.2) we have n(x)

© 2006 by Taylor & Francis Group, LLC

dfn (x) VT d(p(x)n(x)) ¼ dx dx p(x)

(8:5:17)

8.5-830

Concentration

The Silicon Heterostructure Handbook

n (x) p (x) ND

0

wepi

Electric field

xi

x

E (xi)

FIGURE 8.5.3 Distribution of the carrier concentrations and electric field in the epilayer.

which together with the quasi-neutrality condition n ¼ ND þ p allows to express the electron current density (8.5.1) in the injection epilayer region as [23] Iepi 2 1 dp : ¼ qmn ND VT þ Jn ¼ ND p dx AE

(8:5:18)

Integrating Equation (8.5.18) in the injection region for constant Jn and introducing the epilayer resistance RCV ¼ wepi/(qmnNDAE), we have xi p(0) p(xi ) p(0) RCV Iepi ¼ VT 2 þ ln ND p(xi ) wepi

(8:5:19)

as an integral control relationship for the electron transport through the injection epilayer region. The normalized minority hole concentrations p(0)/ND and p(xi)/ND in Equation (8.5.19) are obtained similar to the electron normalized concentrations in Equation (8.5.15) as 2 p(x) nie VB2 fn (x) ¼F exp , ND VT ND2

(8:5:20)

but this time the doping related term nie2/ND2 is implemented as n2ie VDC ¼ exp VT ND2

(8:5:21)

where VDC is the BC built-in voltage. The drift epilayer region is neutral and has ohmic behavior as long as Iepi is significantly smaller than the critical current for velocity saturation IHC ¼ qAENDvsat, where vsat is the electron saturation velocity. Otherwise, the electron concentration becomes current dependent as n ¼ NDIepi/IHC and the electric field E(x) has slope defined by the Poisson equation Iepi dE(x) qND ¼ 1 dx « IHC

© 2006 by Taylor & Francis Group, LLC

(8:5:22)

8.5-831

Compact Modeling of SiGe HBTs: Mextram

where « is the permittivity of the epilayer. It should be emphasized that for the drift electron transport holds E(x) ¼ dfn(x)/dx, which allows to directly evaluate the drop of fn over the drift epilayer region integrating the Poisson equation (8.5.22) twice in the interval (xi, wepi). The result is VC1 fn (xi ) ¼ E(xi )wepi dR þ

2 qND wepi

2«

Iepi 1 dR2 IHC

(8:5:23)

where dR ¼ 1 xi/wepi is the relative depth of the drift epilayer region. Using the interface condition E(xi ) ¼

vs IHC RCV ¼ wepi mn

(8:5:24)

2 and introducing the epilayer space charge resistance SCRCV ¼ qNDwepi /(2« IHC), Equation (8.5.23) becomes

VC1 fn (xi ) ¼ IHC RCV dR þ Iepi IHC SCRCV dR2

(8:5:25)

and represents the governing equation for the electron transport through the drift epilayer region if Iepi > IHC. The validity of Equation (8.5.25) could be extended to the ohmic case after transformation IHC IV IHC þ IV

(8:5:26)

VC1 fn (xi ) RCV dR

(8:5:27)

IHC ! where IV ¼

is the ohmic current in the drift epilayer region. The integral relationships (8.5.19) and (8.5.25) for the injection and drift epilayer regions still require an additional condition to close the system of equations for unknown Iepi, xi/wepi and fn(xi). It may be the continuation of the electric field as proposed in Ref. [22]. In order to avoid implicit model variables and to improve smoothness of the modeling equations, the present Mextram release (Level 504) implements the above epilayer physics in a qualitatively different way. Namely, the epilayer current Iepi, as seen from the circuit simulator, is evaluated only from Equation (8.5.19) applied to the whole epilayer. The governing equations (8.5.19) and (8.5.25) are then employed in the * ¼ fn(xBC) that substitutes the evaluation of the effective electron quasi-Fermi potential VC2 nodal bias VC2 in all subsequent calculations. The detailed implementation procedure is given in Refs. [21, 24].

8.5.3 Recombination Currents The recombination currents in the intrinsic transistor region, due to the hole injection into quasineutral emitter (QNE) and BE space–charge region as well as recombination in QNB, actually serve to model the transistor forward base current. The ohmic part of the base region is represented by the constant base resistance RBC ¼ RBC. The electron and hole injection across BC junction, in the reverse transistor operation, is addressed in Mextram in the extrinsic transistor area. The carrier generation due to the weak avalanche effects is introduced separately as a controlled current source.

© 2006 by Taylor & Francis Group, LLC

8.5-832

The Silicon Heterostructure Handbook

Intrinsic Transistor Region The carrier recombination in the intrinsic transistor region is indirectly evaluated in terms of the currents injected into quasi-neutral or space–charge regions. These currents are typically given in the form of a diode-like characteristics Vj ID (Vj ,I0 ,m) ¼ I0 exp 1 mVT

(8:5:28)

where Vj is the junction voltage, I0 is the diode saturation current, and m is the nonideality factor. The most important contribution to the static base current is the recombination (injection) in QNE. It is expressed in terms of the diode current (8.5.28) as IBE ¼ ID

IS ,1 VB2E1 , BF

(8:5:29)

where BF is the ideal forward current gain. The recombination in the QNB may produce significant impact on the performance of SiGe HBTs [11]. It could be physically evaluated as an additional current component IBB ¼ qAE

ð xBC xBE

Dn dx tn

(8:5:30)

where Dn is the excess minority carrier concentration and tn is the minority carrier lifetime in the QNB. Assuming that the excess minority concentrations at the QNB boundaries are proportional to the injection currents as [25] IS ,1 and Dn(xBE ) / ID VB2E1 , BF

IS Dn(xBC ) / ID VB2C2 ,1 , BF

(8:5:31)

the QNB recombination current (8.5.30) is implemented in Mextram as [18] IS IS wBC IBB ¼ XREC ID VB2E1 , , 1 þ ID VB2C2 ,1 1þ , BF BF w0

(8:5:32)

where XREC is the EB recombination current prefactor. Notice that the width modulation of QNB, especially that due to the BC depletion capacitance, produces an Early-like effect in the forward base current. The hole injection into QNE is essentially a two-dimensional phenomenon. Namely, part of the holes are injected along the sidewalls of the BE junction. Moreover, the hole injection is laterally nonuniform along the intrinsic base below the emitter due to the variations of the internal BE junction bias. The sidewall base current component is introduced by splitting the injection current into the vertical IB1 ¼ (1 XIBI)½(1 XREC)IBE þ IBB

(8:5:33)

and sidewall S IB1

© 2006 by Taylor & Francis Group, LLC

IS ,1 ¼ XIBI ID VB1E1 , BF

(8:5:34)

8.5-833

Compact Modeling of SiGe HBTs: Mextram

components using diode partition factor XIBI. The distributed injection along the pinched transistor base below the emitter is emulated using a nonlinear current branch IB1B2 ¼

0 gBW VB1B2 VB1B2 þ 2VT exp 1 3 RBV VT

(8:5:35)

where RBV is the resistance of pinched base under the emitter at low injection and it may be approximately evaluated as RBV ¼

rWE 3LE

(8:5:36)

for the given pinched base sheet resistance r as well as emitter width and length WE and LE, respectively. The Shockley–Read–Hall (SRH) recombination in the BE space–charge region is implemented in Mextram as a nonideal diode current IB2 ¼ ID ðVB2E1 , IBF, MLFÞ þ Gmin VB2E1

(8:5:37)

where IBF is the saturation current and MLF is the emission coefficient of the BE leakage diode. Small conductance Gmin ¼ 1013 V1 in Equation (8.5.37) is introduced for numerical stability.

Extrinsic Quasi-Neutral Regions The current Iex describes the recombination of carriers injected into a quasi-neutral region of the extrinsic BC junction. It is evaluated by

Iex ¼

exp VVB1C1 1 T

IS ext BRI 1 þ 12 (n(xBC )=(NA ))

(8:5:38)

where BRI is the ideal reverse current gain, ext n(xBC ) IS VB1C1 ¼F exp NA IK VT

(8:5:39)

is the normalized electron concentration at the edge of extrinsic QNB, which is obtained in the same way as n(xBE) but for the bias VB1C1. In principle, Iex represents the ideal component of the reverse base current taking also high-injection effects into account. An additional extrinsic current component XIex, similar to Equation (8.5.38) but evaluated for internal bias VBC1, is introduced if the model flag EXMOD is set to 1. It is also assumed that SRH recombination in the BC space region contributes dominantly to the extrinsic base current component. This current component is derived from maximum value of the net SRH recombination in the space charge region as [4] IB3 ¼ IBR

expðVB1C1 =VT Þ 1 þ Gmin VB1C1 expðVB1C1 =VT Þ þ expðVLR=2VT Þ

where IBR is saturation current and VLR is the crossover voltage of the BC leakage diode.

© 2006 by Taylor & Francis Group, LLC

(8:5:40)

8.5-834

The Silicon Heterostructure Handbook

Weak Avalanche Current The avalanche current Iavl is evaluated in Mextram as [26, 27] Iavl ¼ Iepi

ð WAVL

an ðE(x)Þdx

(8:5:41)

0

where WAVL the effective width of the epilayer, the ionization rate an is given by [28] Bn an (E(x) ) ¼ An exp E(x)

(8:5:42)

and An and Bn are predefined model constants. Assuming the linear electric field distribution x EM E(x) ¼ EM 1 lD 1 þ x=lD

(8:5:43)

with the slope 1/lD around the maximum electric field value EM, Equation (8.5.41) may be integrated to express the weak avalanche current as Iavl

An Bn Bn WAVL exp : ¼ Iepi lD EM exp 1þ lD Bn EM EM

(8:5:44)

The maximum electric field value EM and lD are obtained from the Poisson equation (8.5.22) in the epilayer. To this end, it is rewritten as Iepi dE(x) VAVL ¼2 1 dx WAVL2 IHC

(8:5:45)

where VAVL ¼ qND WAVL2/(2«) is the avalanche curvature voltage. If the model flag EXAVL is set to 1, the weak avalanche model handles also the electric field distribution in quasi-saturation due to the Kirk effect [21].

8.5.4 Substrate Current Substrate current is implemented in Mextram using a simplified Gummel–Poon integral charge control relationship for parasitic PNP transistor:

Isub

VB1C1 1 2 ISS exp VT sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ¼ ﬃ IS VB1C1 exp 1þ 1þ4 IKS VT

(8:5:46)

where ISS is PNP transistor saturation current and IKS is the substrate knee current. Notice that the effects of the base width modulation by depletion capacitances are neglected and VSC1 ¼ 0 is assumed. Moreover, the high-injection effects are expressed in terms of IS/IKS instead of ISS/IKS to simplify parameter extraction. An additional extrinsic substrate current component XIsub, similar to Equation (8.5.46), but evaluated for internal bias VBC1, is introduced if the model flag EXMOD is set to 1. A diodelike current ISF is added between the substrate and collector nodes, S and C1, to serve as an indicator of wrongly polarized SC junction.

© 2006 by Taylor & Francis Group, LLC

8.5-835

Compact Modeling of SiGe HBTs: Mextram

It should be emphasized that Mextram equivalent circuit is deliberately left without any circuit elements connecting intrinsic substrate node S and the substrate contact. In that way, external substrate network of arbitrary complexity could be easily attached to the intrinsic substrate node [29].

8.5.5 Charges and Capacitances The temporal variation of the electric field results in the displacement current components across the space–charge regions. These dynamic current components are represented by the depletion capacitances (charges). On the other hand, the temporal variation of the compensated (diffusion) charges, produces an effective dynamic recombination current along the transistor transfer current flow, which is implemented by the diffusion charges (capacitances). Mextram (Level 504) also takes account of the BE and BC parasitic overlap capacitances C0BE ¼ CBEO and C0BC ¼ CBCO as shown in Figure 8.5.1.

Depletion Capacitances The bias dependence of the depletion capacitances is in Mextram generally considered as Ct (Vj ) ¼ (1 Xp )

C0 fI 1

Vjeff (Vj )=Vbi

P þ Xp C0

(8:5:47)

where C0 is the zero bias depletion capacitance, Vj is the internal p–n junction bias, Vbi is the junction built-in voltage, and P is the grading coefficient. The expression (8.5.47) is inspired by the simple empirical description for depletion capacitance of abrupt (or linear) p–n junctions but also enhanced, with quantities Xp and fI as well as function Vjeff(Vj), to increase the physical and computational range of the model validity. In order to avoid singular capacitance behavior at the forward bias, an effective junction bias Vjeff(Vj) is employed in the denominator of Equation (8.5.47). It is related to the real junction bias Vj as Vjeff (Vj )

Vj VF ¼ Vj Vch ln 1 þ exp Vch

(8:5:48)

where the control voltage

1=P VF ¼ Vbi 1 aj

(8:5:49)

forces the capacitance to asymptotically approach the constant value ajC0 for Vj > VF (see Figure 8.5.4). The smoothness of this transition is defined by Vch. The quantity Xp in Equation (8.5.47) limits the

C t (Vj)

a jC0

VF

Vbi

FIGURE 8.5.4 Implementation of the Mextram depletion capacitances.

© 2006 by Taylor & Francis Group, LLC

Vj

8.5-836

The Silicon Heterostructure Handbook

decrease of the capacitance under the reverse bias. It is of particular importance for BC depletion capacitance having a fully depleted epilayer region. Finally, the term fI accounts for the modulation of the BC depletion capacitance by the transfer epilayer current. It is defined as fI ¼

Iepi 1 Iepi þ IHC

MC (8:5:50)

where MC is the current-modulation coefficient. Table 8.5.1 provides the corresponding model parameters in Mextram for the BE, BC, and SC junctions. For compact modeling purpose, it is more convenient to consider corresponding depletion charges Qt (Vj ) ¼

ð Vj 0

Ct Vjeff (Vj ) dV

(8:5:51)

instead of the depletion capacitances. The Mextram depletion charges (see Figure 8.5.1) are implemented as QtE (VB2E1 ) ¼ ð1 XCJEÞQt ðVB2E1 Þ

(8:5:52)

S QtE (VB1E1 ) ¼ XCJE Qt ðVB1E1 Þ QtC (VB2C2 ) ¼ XCJC Qt VjC (VB2C2 )

(8:5:53)

Qtex (VB1C1 ) ¼ ð1 XCJCÞð1 XEXTÞQt ðVB1C1 Þ

(8:5:55)

XQtex (VBC1 ) ¼ ð1 XCJCÞXEXT Qt ðVBC1 Þ

(8:5:56)

QtS (VSC1 ) ¼ Qt ðVSC1 Þ

(8:5:57)

(8:5:54)

where XCJE, XCJC, and XEXT are geometry partitioning factors splitting the depletion capacitances into vertical and sidewall components as well as between intrinsic and extrinsic parts of the transistor. Notice that the internal BC junction bias VjC in Equation (8.5.54) has to be evaluated implicitly as a function of bias VB2C2 in order to correctly take into account the effects of quasi-saturation in the epilayer [21].

Diffusion Charges The diffusion charges are evaluated in Mextram independently for the QNB, QNE, and epilayer as well as for the extrinsic transistor region. For the linear distribution of electrons in QNB, the total base diffusion charge is 0 QB ¼ QB0 gBW

1 n(xBE ) n(xBC ) þ 2 NA NA

(8:5:58)

where QB0 ¼ qAEwB0NA. In the quasi-static approximation, the base diffusion charge (8.5.58) is split into BE and BC components QBE and QBC as TABLE 8.5.1

BE BC SC

© 2006 by Taylor & Francis Group, LLC

Parameters for the Depletion Capacitances Vbi

C0

P

Xp

fI

VDE VDC VDS

CJE CJC CJS

PE PC PS

— XP —

— MC —

8.5-837

Compact Modeling of SiGe HBTs: Mextram

1 0 n(xBE(C) ) QBE(C) ¼ TAUB IK gW 2 NA

(8:5:59)

and associated with Mextram nodes E1 and C2. The model parameter TAUB ¼ QB0/IK is introduced as base transit time. The diffusion charge in the QNE (including the compensated charge in the BE space–charge region) is expressed as VB2E1 1 QE ¼ QE0 exp MTAU VT

(8:5:60)

where MTAU is the emitter diffusion charge coefficient. The emitter transit time can be approximately expressed from Equation (8.5.60) as t E (IN )

QE0 IN 1=MTAU : IN IS

(8:5:61)

Introducing a emitter transit time as TAUE ¼ tE(IK), the prefactor QE0 in Equation (8.5.60) becomes 1=MTAU IS QE0 ¼ TAUE IK IK

(8:5:62)

as it is implemented in Mextram. The epilayer diffusion charge Qepi ¼ qAE

ð xi p(x)dx

(8:5:63)

0

actually represents the hole (minority carrier) charge in the injection epilayer region. This charge can be related to the epilayer current by the Gummel integral charge relationship Iepi ¼

q2 n2i A2E Dn V VB2 fn (xi ) : exp B2C2 exp VT Qepi VT

(8:5:64)

2 Introducing the epilayer transit time TEPI ¼ Wepi /(4Dn) and with the help of pn product (8.5.2), the epilayer diffusion charge can be expressed also as

Qepi ¼

2 Qepi0

4 TEPI Iepi

p(0) p(0) p(xi ) p(xi ) þ1 þ1 ND ND ND ND

(8:5:65)

4 TEPI VT : RCV

(8:5:66)

where Qepi0 ¼ qAE Wepi ND ¼

For practical implementation in Mextram, expression for Qepi is combined with the expression for the epilayer current Iepi and further simplified [21, 30]. The extrinsic diffusion charge is evaluated combining expression for the injection in QNB and epilayer in extrinsic part of the transistor:

© 2006 by Taylor & Francis Group, LLC

8.5-838

The Silicon Heterostructure Handbook

Qex ¼

ext ext TAUR 1 n(xBC ) p(xW ) QB0 þ Qepi TAUB þ TEPI 2 NA ND

(8:5:67)

where TAUR is the reverse base transit time, ext p(xW ) VB1C1 VDC ¼ F exp ND VT

(8:5:68)

ext while n(xBC )/NA is given in Equation (8.5.39). Further partition of the extrinsic diffusion charge, similar to that of the extrinsic injection currents, is possible if the model flag EXMOD is set to 1. In that case, the similar expression to Equation (8.5.67) is used to evaluate the extrinsic charge XQext in terms of junction bias VBC1 and the BC diode partition factor XEXT is used to split their contributions.

Distributed and Non-Quasi-Static Charges In high-frequency and high-speed applications, the quasi-static assumption is no longer valid. Moreover, the effects of the distributed capacitances along the BE junction should be taken into account. The high-frequency current-crowding effects are modeled introducing an effective charge branch QB1B2 ¼

1 dQB2E1 VB1B2 5 dVB2E1

(8:5:69)

where QB2E1 ¼ QtE þ QBE þ QE. The non-quasi-static effects in QNB base are accounted for in Mextram introducing charge partitioning: QBC ! 1=3QBE þ QBC

and

QBE ! 2=3QBE :

(8:5:70)

Both modeling options require the flag EXPHI to be set to 1.

8.5.6 Thermal Phenomena The electrical characteristics of bipolar transistors are particularly susceptible to temperature variations due to the self-heating or thermal interaction with other devices. The electrothermal effects are implemented in Mextram as a combination of the electrical model (current and charge branches), with temperature-dependent parameters, and thermal model, that links the device average temperature to the dissipated electrical power. The temperature-scaling parameters are based on strong physical background of the electrical parameters. The default Mextram thermal model is one-pole linear thermal impedance (parallel thermal resistance RTH and thermal capacitance CTH of the device surrounding) connected between the external thermal node dT and zero bias (ambient) device temperature. If it is necessary, the default thermal impedance may be suspended and bypassed by a more advanced thermal network via external thermal node. In order to correctly take into account the time delays of the internal biases, the total dissipated power in the device is evaluated as a sum of the power dissipated in all nonreactive circuit elements separately. Most of the Mextram current and charge-modeling expressions have explicit temperature dependence. The actual device temperature is expressed as T ¼ TA þ DTA þ VdT þ 273:15

ðKÞ

(8:5:71)

where TA is the ambient (simulation) temperature in 8C, parameter DTA specifies constant temperature shift to ambient temperature and VdT is the temperature at the thermal node dT. The electrical potential

© 2006 by Taylor & Francis Group, LLC

8.5-839

Compact Modeling of SiGe HBTs: Mextram

at the thermal node dT actually represents the excess device temperature. The temperature at which the electrical parameters are extracted is the reference temperature TREF in 8C or Tref ¼ TREF þ 273.15 in kelvin. The model parameters depend implicitly on temperature via intrinsic carrier concentration and carrier mobility temperature dependence. The temperature dependence of the intrinsic carrier concentration is VG n2i / tN3 exp VDT

(8:5:72)

where tN ¼

T Tref

1 q 1 1 ¼ VDT k T Tref

(8:5:73) (8:5:74)

k is the Boltzmann constant and * may be B, C, S, and J for the bandgap in base, collector, substrate, and BE depletion region, respectively. This approach is particularly suitable for HBTs with varying bandgap across the device. The carrier mobility is scaled with temperature as m / tNA

(8:5:75)

where * may be E, B, EX EPI, C, and S for the emitter, base, extrinsic base, epilayer, collector, and substrate region, respectively. A few temperature-scaling parameters, that could be particularly important for SiGe HBT applications, are introduced separately for certain electrical parameters. The forward and reverse current gain parameters BF and BRI depend on the difference of bandgaps at BE and BC junctions. Their temperature dependence is additionally expanded by DVGBF(R) BF(RI) / exp VDT

(8:5:76)

where DVGBF and DVGBR are the bandgap voltage differences. It is well known that the compensated charge in the BE space–charge region could have significant effect on the dynamic performance of SiGe HBTs [25]. This charge also has different temperature dependence then the base diffusion charge. In Mextram, it may be easily taken into account by the temperature dependence DVGTE TAUE / exp VDT

(8:5:77)

where DVGTE is the emitter transit time bandgap voltage difference. Finally, the base zero-bias charge QB0 has a separate temperature-scaling coefficient AQBO. Since it accounts also for the temperature dependence of wB0, it is crucial for the temperature scaling of Early voltages VER and VEF but also Gerelated parameter DEG as DEG / tNAQBO :

(8:5:78)

Figure 8.5.5 shows the complete set of Mextram temperature-scaling parameters associated with the different bandgap or doping areas along the transistor structure.

© 2006 by Taylor & Francis Group, LLC

8.5-840

The Silicon Heterostructure Handbook

VGB

DVGBR

DVGBF

VGC

VGJ DVGTE

VGS

AEX

AE

AC AB

AQBO

AEPI

AS

FIGURE 8.5.5 Temperature-scaling parameters.

8.5.7 Parameter Extraction The accuracy of compact models in circuit simulation depends not only on the correct physical description of various physical phenomena in the device but also on a reliable, robust, and unambiguous parameter extraction methodology. It should be emphasized that a general and fully automatic parameter extraction procedure is not currently available. The unambiguous determination of individual parameter values in the parameter extraction procedure could be seriously hampered by the correlation among the parameters. In order to minimize the correlation among electrical and temperature-scaling Mextram parameters, the electrical parameters may be split into parameters extracted at low-injection- (not affected by the self-heating) and high-injection-related parameters. Moreover, in order to further reduce the parameter correlation, the electrical and temperature-scaling parameters could be further split into small groups that are extracted subsequently, in the direction of their dominant dependence, from the measured data sensitive to the selected parameters. An example of such slitting for Mextram parameter extraction is given in Table 8.5.2 for low and Table 8.5.3 for high-injection extraction step, respectively. The more detailed discussion on Mextram parameter extraction is given in Ref. [31]. As a practical example of the full Mextram (Level 504) parameter extraction, we present here the results for the IBM self-aligned high-breakdown 0.32 mm BiCMOS SiGe graded-base test technology. It has been offered by IBM as a nonproduction test vehicle for free data exchange in compact model evaluation and standardization effort [32]. The measurement data have been provided for five different temperatures. The comparisons between measured data and Mextram characteristics for a single device, having emitter length of 16.7 mm, are shown in Figure 8.5.6 to Figure 8.5.11. The characteristics of the static current gain, reverse Gummel plot, output characteristics, and cutoff frequency at reference temperature of Tref ¼ 258C are shown in Figure 8.5.6 to Figure 8.5.9, respectively. Figure 8.5.10 and Figure 8.5.11 show the result of the collector current and cutoff frequency temperature scaling.

© 2006 by Taylor & Francis Group, LLC

8.5-841

Compact Modeling of SiGe HBTs: Mextram

TABLE 8.5.2

Extraction of the Low-Injection Parameters

Characteristics

Electrical Parameters

Scaling Parameters

BE depletion capacitance BC depletion capacitance SC depletion capacitance Forward–Early Reverse-Early Forward-Early Forward-Gummel (Ic) Forward-Gummel (Ib) Re-flyback Rc-active Reverse-Gummel (Is) Reverse-Gummel (Ib)

CJE, PE, VDE CJC, PC, XP CJS, PS, VDS WAVL, VAVL, XREC VER VEF IS BF, IBF, MLF RE RCC ISS, IKS BRI, IBR, VLR

VGB VGC VGS

TABLE 8.5.3

AQBO AQBO VGB, AB DVGBF, VGJ AE AC VGS, AS DVGBR, VGC

Extraction of the High-Injection Parameters

Characteristics

Electrical Parameters

Output-characteristic Forward-Gummel Cutoff frequency Reverse-Gummel

RTH, IK RCV, VDC SCRCV, IHC, TAUE, TEPI TAUB XEXT

Scaling Parameters

DVGTE, AEPI

70 60

Ic /Ib

50 40 30 20 10 0 10−11 10−10 10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 Ic (A)

FIGURE 8.5.6 The static current gain versus collector current.

© 2006 by Taylor & Francis Group, LLC

8.5-842

The Silicon Heterostructure Handbook

10−2 10−3 10−4

Ie,Ib (A)

10−5 10−6 10−7 10−8 10−9 10−10 10−11 0.4

0.5

0.6

0.7 0.8 Vbc (V)

0.9

1

1.1

FIGURE 8.5.7 The reverse Gummel plot. 10 Ib = 0.12 µA Ib = 1.2 µA Ib = 6 µA Ib = 15 µA Ib = 30 µA Ib = 45 µA Ib = 60 µA

I c (mA)

8

6

4

2

0 0

1

2

3 Vce (V)

4

5

FIGURE 8.5.8 Output characteristics. 30 25

Ft (GHz)

20 15 10 0 0 10−4

Vcb = −0.3 V Vcb = 0 V Vcb = 1V Vcb = 2 V Vcb = 3 V 10−3

10−2 Ic (A)

FIGURE 8.5.9 Cutoff frequency versus collector current.

© 2006 by Taylor & Francis Group, LLC

6

8.5-843

Compact Modeling of SiGe HBTs: Mextram

10−1 10−2 10−3 10−4

Ic (A)

10−5 10−6

T = 25⬚C T = 125⬚C T = 85⬚C T = 55⬚C T = −15⬚C

10−7 10−8 10−9 10−10 10−11

0.4

FIGURE 8.5.10

0.5

0.6

0.7

0.8 0.9 Vbe (V)

1

1.1

1.2

Gummel plot of the collector current at different temperatures.

30 25

Ft (GHz)

20 15 10 5 0 10−4

T = 25⬚C T = 125⬚C T = 85⬚C T = 55⬚C T = −15⬚C 10−3

10−2 I c (A)

FIGURE 8.5.11

Cutoff frequency versus collector current at different temperatures.

Acknowledgments The author would like to thank IBM for providing the measurement data for Mextram parameter extraction and Philips Research Laboratories for continuous support of the compact modeling activities at Laboratory of High-frequency Technology and Components, Delft University of Technology, The Netherlands.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston: Artech House, 2003. 2. HC Graaff and WJ Kloosterman. New formulation of the current and charge relations in bipolar transistor modeling for CACD purposes. Trans Electron Dev 32:2415–2419, 1985. 3. IE Getreu. Modeling the Bipolar Transistor. Amsterdam: Elsevier, 1978.

© 2006 by Taylor & Francis Group, LLC

8.5-844

The Silicon Heterostructure Handbook

4. HC de Graaff and FM Klaassen. Compact Transistor Modeling for Circuit Design. New York: SpringerVerlag, 1990. 5. JCJ Paasschens and WJ Kloosterman. The Mextram Bipolar Transistor Model — Level 504. Nat Lab Unclassified Report, NL-UR 2000/811, Koninklijke Philips Electronics, 2001. 6. HK Gummel and HC Poon. An integral charge control model of bipolar transistors. Bell Syst Tech J 49:827–852, 1970. 7. HK Gummel. An charge control relation for bipolar transistors. Bell Syst Tech J 49:115–120, 1970. 8. SL Salmon, D Cressler, RC Jaeger, and DL Harame. The influence of Ge grading on the bias and temperature characteristics of SiGe HBTs for precision analog circuits. IEEE Trans Electron Dev 47:292–298, 2000. 9. CT Kirk. A theory of transistor cutoff frequency (fT) falloff at high current densities. IRE Trans Electron Dev 9:164–174, 1962. 10. LCN de Vreede, HC de Graaff, K Mouthaan, M de Kok, JL Tauritz, and RGF Baets. Advanced modeling of distorsion effects in bipolar transistors using the Mextram model. IEEE J Solid-State Circuits 31:114–121, 1996. 11. G Niu, JD Cressler, and AJ Joseph. Quantifying neutral base recombination and the effects of collector–base junction traps in UHV/CVD HBTs. IEEE Trans Electron Dev 45:2499–2504, 1998. 12. HC Wu, S Mijalkovic´, and JN Burghartz. Parameter extraction of scalable Mextram model for highspeed SiGe HBTs. Proc 2004 Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 140–143. 13. E So¨nmez, A Trasser, P Abele, KB Schad, and H Schumacher. Integrated receiver components for low-cost 26 GHz LMDS applications using an 0.8 mm SiGe HBT technology. 33rd European Microwave Conference, 2003, pp. 399–402. 14. P Deixler, HGA Huizing, JJTM Donkers, JH Klootwijk, D Hartskeerl, WB de Boer, RJ Havens, R van der Torn, JCJ Paasschens, WJ Kloosterman, JGM van Berkum, D Terpstra, and JW Slotboom. Exploration for high perfomance SiGe-heterojunction bipolar transistor integration. Proc 2001 Bipolar/BiCMOS Circuit and Technology Meeting, 2001, pp. 30–33. 15. U Erben and E So¨nmez. Fully differential 5 to 6 GHz low noise amplifier using SiGe HBT technnology. Electron Lett 40:39–40, 2004. 16. WC Hua, TY yang, and CW Liu. The comparison of isolation technologies and device models on SiGe bipolar low noise amplifier. Appl Surf Sci 224:425–428, 2004. 17. F Yuan, Z Pei, JW Shi, ST Chang, and CW Liu. Mextram modeling of Si/SiGe heterojunction phototransistors. Proc 2003 International Semiconductor Device Research Symposium, 2003, pp. 92–93. 18. JCJ Paasschens, WJ Kloosterman, and RJ Havens. Modeling two SiGe HBT specific features for circuit simulation. Proc 2001 Bipolar/BiCMOS Circuit and Technology Meeting (BCTM), Minneapolis, 2001, pp. 38–41. 19. CC McAndrew and LW Nagel. Early effect modeling in SPICE. IEEE J Solid-State Circuits 31:136– 138, 1996. 20. S Mijalkovic´. Generalized Early factor for compact modeling of bipolar transistors with nonuniform base. Electron Lett 39:1757–1758, 2003. 21. JCJ Paasschens, WJ Kloosterman, and R vd Toon. Model Derivation of Mextram 504. Nat Lab Unclassified Report, NL-UR 2002/806, Koninklijke Philips Electronics, 2002. 22. HC de Graaff and WJ Kloosterman, Modeling of the collector epilayer of a bipolar transistor in the Mextram model. IEEE Trans Electron Dev 42:274–282, 1995. 23. GM Kull, LW Nagel, S Lee, P Lloyd, EJ Prendergast, and H Dirks. A unified circuit model for bipolar transistors including quasi-saturation effects. IEEE Trans Electron Dev 32:1103–1113, 1985. 24. JCJ Paasschens, WJ Kloosterman, RJ Havens, and HC de Graaff. Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. IEEE J Solid-State Circuits 36:1390– 1398, 2001. 25. M Reisch. High-Frequency Bipolar Transistors. Berlin: Springer-Verlag, 2003.

© 2006 by Taylor & Francis Group, LLC

Compact Modeling of SiGe HBTs: Mextram

8.5-845

26. WJ Kloosterman and HC de Graaff. Avalanche multiplication in compact bipolar transistor model for circuit simulation. IEEE Trans Electron Dev 36:1376–1380, 1989. 27. WJ Kloosterman, JCJ Paasschens, and RJ Havens. A comprehensive bipolar avalanche multiplication compact model for circuit simulation. Proc 2000 Bipolar/BiCMOS Circuit and Technology Meeting, 2000, pp. 172–175. 28. AG Chynoweth. Ionization rates for electron and holes in silicon. Phys Rev 109:1537–1540, 1958. 29. M Kleeme and E Barke. An extended transistor model for substrate crosstalk analysis. Proc IEEE 1999 Custom Integrated Circuit Conference, 1999, pp. 579–582. 30. LCN de Vreede, HC de Graaff, JL Tauritz, and RGF Baets. Extension of the collector charge description for compact bipolar epilayer models. IEEE Trans Electron Dev 45:277–285, 1998. 31. JCJ Paasschens and WJ Kloosterman. Parameter Extraction for the Bipolar Transistor Model Mextram — Level 504. Nat Lab Unclassified Report, NL-UR 2001/801, Koninklijke Philips Electronics, 2001. 32. D Sheridan, MR Murty, W Ansley, and D Harame. IBM Bipolar Model Standardization: VBICMEXTRAM-HICUM. Compact Model Counsil (CMC), Puerto Rico, April 2002.

© 2006 by Taylor & Francis Group, LLC

8.6 CAD Tools and Design Kits 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5

Introduction............................................................... 8.6-847 Schematic Capture .................................................... 8.6-848 Design Simulation ..................................................... 8.6-850 Physical Design .......................................................... 8.6-851 Physical Verification .................................................. 8.6-852 Layout versus Schematic . Parasitic Extraction (PEX)

Sue E. Strang IBM Microelectronics

8.6.6 8.6.7

Chip Assembly ........................................................... 8.6-856 Chip Finishing ........................................................... 8.6-857

8.6.1 Introduction Design projects are comprised of several phases, specification definition, design, and manufacture. The design phase spans the flow inputting information from the specification phase and outputting information to the manufacturing phase (Figure 8.6.1). To facilitate a design, computer-aided design (CAD) tools are integrated into the flow and customized to aid the designer. A process design kit (PDK) is a complete set of building blocks that are critical for any custom-integrated circuit design. The fundamental elements of a PDK consist of documentation, models for device and macros, schematic symbols, simulation support, physical design elements for device and routing options, technology files and physical verification rule decks for manufacturability and signal integrity. PDK development and support integrated into pure play foundry have proven an essential edge for foundries and customer-owned tooling (COT) vendors. A proven design methodology flow can take years to develop and is continuously improving to address the rapid transitions of technologies to tighter lithography and broader frequencies. Silicon germanium allows for integration of large digital content with high-frequency analog components (Figure 8.6.2) requiring a mixture of tools for system-level verification [1]. System and circuitlevel design methodologies are integrated within a CAD framework of tools. This framework links the various design stages, design entry, simulation, physical layout, and verification with multiple point tools. The design framework provides a high-level extension language, which can access the design database and provide a means for data translation between different tools as well as a mechanism for developing custom software. The design cycle is a highly iterative process, successive simulations are performed to optimize a circuit, layouts are optimized for matching, form factor and parasitic reduction, recursive verifications are run and layouts altered to match design rules, connectivity checks and simulations from layout data may cause updates to the original schematic placing the designer back to the electrical design stage. A framework of tools enables easy flow between tools allowing for a more efficient design process, especially when a single design database is shared. A discussion of the tools used in design phase of a custom and semi-custom design follows. The supporting PDK is developed to optimize the available CAD tools within each stage to reduce design cycles and to reduce or eliminate hardware fabrication errors. 8.6-847 © 2006 by Taylor & Francis Group, LLC

8.6-848

The Silicon Heterostructure Handbook

Manufacture

Design

Specification

Phases of IC Design Phase Techology definition Testsite design Device characterization Circuitry design Simulation Physical design Design verification

Schematic capture Design simulation RF − Analog − Mixed Mode − Digital Physical design Polygon-cell block layout, Place and Route Design verification DRC, ERC, LVS, PEX, Resimulation

Foundry verification Fill and level Generation Mask generation

Chip assembly and verification Pads, block placement, Routing, DRC Chip finishing GDS2, Tape out for manufacture

FIGURE 8.6.1 Design framework flow.

FIGURE 8.6.2 Integrated analog and digital PRML design with 1200 SiGe HBT and >1,000,000 gates.

8.6.2 Schematic Capture Design entry begins with the placement of devices or circuits from a library. A library is a collection of devices and circuits with symbolic and physical representations. Devices developed for RF custom libraries include DC MOSFETs, RF MOSFETs, BJTs, polysilicon, diffusion and metal resistors, MOS, metal–insulator–metal and vertically stacked capacitors, hyper-abrupt, MOS and collector–base varactors, Schottky Barrier and forward-biased diodes, ESD devices, symmetric spiral inductors, stacked inductors, programmable fuses, bondpads, transmission lines, and transformers. These devices are modeled primitives characterized in a technology and optimized for design use. Artwork for these

© 2006 by Taylor & Francis Group, LLC

8.6-849

CAD Tools and Design Kits

devices is provided in the library for placement in schematics to form an electrical representation of a circuit. While many devices have industry standard artwork associated with them, custom changes such as color or text may be used to describe layout characteristics or design usage. These devices are used as building blocks to create an electrical representation of a circuit. Figure 8.6.3 shows a schematic representation of a differential amplifier. For each primitive a set of parameters are defined for use within circuit simulation and physical representation of the device as well as informational applications such as device current ratings. These parameters are used within the model to adjust the intrinsic model parameters per design dimensions and usage. Parameters such as self-heating and impact ionization and simulation frequencies describe design usage. The physical parameters describe the geometry and characteristics of the device. For MOSFETs parameters such as the length, width, number of channels, gate extensions, contact location, and bulk guard ring inclusion are defined. For passive devices like an inductor, parameters such as outer dimension, number of turns, line width, spiral spacing, underpass characteristics, metal stacking, groundshield pattern, and inductance are defined. For BJTs reliability parameters may be defined to determine the rated current for the device and the base wiring. Each parameter describes a physical characteristic of the device, which is used to build the layout (Figure 8.6.4). For optimization, device parameters may be defined as variables or expressions for variation within circuit simulation. A series of simulations is launched based on these parameters, initiating an iterative loop within the simulation. A family plot from the simulation results may be analyzed to select the optimal value of the parameter.

vdd

W=4.5U l=180n nf=2 m=1

vdd

pfet

pfet W=4.5U l=180n nf=2 m=1

out

enl=3U performance=Low fT nstripe=1

inp

enl=3U performance=Low fT nstripe=1 npn reff-169.83 W-8U l=5.06U

npn

inn

Polyres

nfet

nref

W=7.2U l=180n nf=1 m=1 gnda

FIGURE 8.6.3 Device library symbols used in a differential amplifier circuit.

© 2006 by Taylor & Francis Group, LLC

nfet W=7.2U l=180n nf=1 m=1 gnda

8.6-850

The Silicon Heterostructure Handbook

drain

gate

bulk

source

Model subcircuit

Device symbol

Device layout

FIGURE 8.6.4 RF MOSFET model subcircuit, symbol, and layout representations.

For nonphysical, calculated parameters such as resistance, capacitance, and inductance, these values must be calculated within the model or preprocessor when a variable is defined. Linking CAD tools that require electrical or schematic input, such as circuit simulators and layout versus schematic (LVS) tools, requires a netlist of the circuit. The netlist is a text file defining the component name, device ports, connectivity, and the device parameters. Each device is prefixed by a character describing its type and may be defined as hierarchical. This information is unique for each simulator, and custom procedures can be written to adjust the information based on technology or application. For example, to pass a nonphysical parameter to LVS such as multiplicity, the component name may be altered or an additional parameter may be listed to group-like devices and verify multiplicity.

8.6.3 Design Simulation A large-scale complex IC design may comprise of RF, analog, and digital elements requiring different simulation methods for each section. RF analysis is required for predicting RF and microwave behavior, transient and frequency analysis for analog circuitry, and high-level behavioral for logic applications. Several circuit simulations are available for these specific design types. Two types of algorithms are available for simulating RF characters in circuits such as power amplifiers, low-noise amplifiers, mixers, and voltage-controlled oscillators (VCOs) [2]. These are periodic steadystate (PSS) and harmonic balance (HB). The PSS algorithm is an RF simulation extension to a transient simulation engine, which assumes that a periodic signal exists in the system [3]. The HB engine is a pure frequency-domain approach. If the input signal is small enough that nonlinear elements in the circuit do not significantly distort the signal output, then the small-signal simulation gives valid results. However, as the input signal becomes increasingly large, new frequencies appear at the output. Harmonic balance solves for each of these new frequencies. Analog circuit simulation provides transistor-level analysis and net connectivity using compact models in multiple domains including time and frequency. Manufacturing and yield analysis can be done through statistical Monte Carlo simulations and corner analysis to emulate process variations. Nonuniformity in semiconductor processing produces differences in like devices due to lithography and etch processes, conductivity gradients, thickness differences due to polish differences, and thermal distribution across the chip. These differences cause mismatches in device behavior, which can be analyzed in statistical simulation runs. Digital macros can be modeled as top-level behavioral models at the system level. A mixed-mode simulation system analyzes both analog and digital.

© 2006 by Taylor & Francis Group, LLC

CAD Tools and Design Kits

8.6-851

Safe operating areas (SOA) are set by a technology and determined based on simulation results. A simulation can be augmented by additional analysis to show instantaneous voltage and currents and dynamically warn about any violations in the transistors if the SOA is exceeded ensuring reliability. Other simulation enhancement tools are defined to input manufacturing process bias and variability to specific model parameters to target device performance after fabrication. A post-circuit-simulation analysis determines critical operating range for the specifications and indicates the need to adjust device dimensions to tolerate circuit conditions based on current, voltage, or temperature. Circuit performance is affected by the physical layout of the circuit, therefore specific layout techniques such as device matching or bulk connection proximity must be passed to the physical stage.

8.6.4 Physical Design Physical layout and interconnect in RF designs requires customization in order to control parasitic effects and match circuits for optimal performance. Physical representations of devices may be drawn custom by manually placing each layer to construct a unique device or interconnect. While this allows for highly specialized devices, this is tedious and prone to design rule errors. Another method is to use predrawn devices that are highly characterized. These, however, may not suit the design needs by limiting the possible configurations and form factors. To this end, programmable devices are developed within a library. These devices may be varied in shape by geometry inputs and optionally add in wiring, contacts, extensions, or repetition of shapes specified by designer input. These programs take the device parameters and create design rule correct device layouts to produce designs ready for manufacture. Figure 8.6.5 shows a graphical representation of a symmetric inductor and the same device after processing. Stretching of geometric shapes and conditional inclusions of device options allows for flexibility in layout. This methodology can be extended hierarchically to create programmable circuits in which design points are entered and a layout is generated. In reality, all described methods custom, fixed, and programmable are used for a design to meet the design criteria. In addition to device design, programmable cells may be created to assist in sound layout practices for silicon germanium technologies. These include the formation and properties of noise-isolating moat structures, guard rings, substrate contact techniques to achieve optimum device matching, and prevention of electromigration failure and voltage drops through proper metallization. Isolation moats place a

FIGURE 8.6.5 Inductor layout in CAD tool and manufactured inductor.

© 2006 by Taylor & Francis Group, LLC

8.6-852

The Silicon Heterostructure Handbook

region of high resistance between two circuits, or separate areas of the chip, to reduce noise or signal coupling through the substrate. Guard rings form a barrier to the input of ionic contaminants, which are highly mobile in silicon dioxide, by surrounding the device or the die with a wall of metal. The contacts of the isolation guard ring may be switched off or sections may be removed for chaining of devices. Substrate contacts maintain the substrate potential to the desired voltage levels and assure that local potential variations are minimized to prevent latch-up, especially in highly resistive substrates. In the layout, good matching can be attained by keeping like devices close together or adjacent, placing groups of devices around a common center, orienting devices in the same direction, or using identical layouts. Abutment of MOSFET devices allows for devices to be merged into a single diffusion. The use of schematic-driven-layout streamlines the physical design process. The schematic is used to drive the placement within the physical design and assist in routing. Placement aids allow for predefinition of topology and routing aids guide interconnect for design constructs using recommended wiring layers and widths according to electromigration guidelines. Devices should be constructed with terminals with a predefined permutation rule for autorouting.

8.6.5 Physical Verification Design rule requirements are imposed to ensure a variety of quality metrics, including area, timing, power, and yield. Each process step requires mask-layer design for fabrication. Analysis is required on the physical shapes generated by the physical design phase to verify the process steps for manufacturing and tool requirements. Design rule checking (DRC) is a requirement for fabrication and assures manufacturability. Process layers are checked for interaction between layers, metallization vias, overlay tolerances, width and separation limits, shape integrity (Figure 8.6.6). CAD tools are available to measure physical shapes hierarchically or for flat shapes for specified design rules and report design rule violations to the designer. Some process and design techniques checked in the DRC are discussed in the following sections. Antenna rules are introduced to identify process-induced gate oxide damage caused when exposed polysilicon and metal structures, connected to a thin oxide transistor, collect charge from the processing environment such as reactive ion etch. When a sufficiently large potential is developed, a current may propagate through the thin oxide. Unchecked occurrences may result in reduced performance or nonfunctional devices when exposed to process-induced damage. Gate oxide damage due to charging may be avoided by providing an alternate discharge path from the gate node to the substrate. A diode to substrate is an effective means to prevent charge build up across the gate dielectric. At wafer processing temperatures, the diode is sufficiently conductive to prevent any charge build up, and the potential is at maximum the junction breakdown voltage. At normal circuit operation temperatures, the diode is in a low-leakage reverse biased state. The manufacturing process utilizes chemical–mechanical polishing (CMP) to achieve planarity on a wafer. This process feature requires that the variations in density on a layer be restricted and must be

Spacing error FIGURE 8.6.6 Example of design rule checks.

© 2006 by Taylor & Francis Group, LLC

Width violation

Overlap error

CAD Tools and Design Kits

8.6-853

verified on a global and local area of the wafer. When densities are not sufficient, automatic placement of fill shapes may be added to a design in sparse regions to increase density or densities may be decreased by slotting or cutting holes in a layer. Copper lines are desirable for low resistance in the line, however, due to the soft structure of the material dishing may occur [4]. To achieve planarity slots may be required to be drawn in the conductor layers. Lines may be auto-filled or auto-slotted using CAD tools or devices may contain the fill techniques within the cell design. For sensitive circuitry such as transmission lines, fill shapes may be introduced in the library device to channel the signal current in the line for better modeling (Figure 8.6.7). Motion of electrons of a metal conductor, such as aluminum, in response to the passage of high current through it, may lead to the formation of voids within the conductor. These voids can grow to a size where the conductor is unable to pass current. Electromigration is aggravated at high temperature and high current density, and therefore, is a reliability concern. Electromigration is minimized by limiting current densities and by adding metal impurities such as copper or titanium to the aluminum. These conditions can be highlighted through CAD tools by overlaying the simulation results of current flow through the physical dimensions as designed in the layout and determining the current density of the conducting material. This electrical rule check (ERC) will highlight these conditions to the designer that may result in malfunctioning designs. The design for manufacturing (DFM) approach identifies trouble spots in a design and provides the important data that allow the designer to determine a cost–yield analysis. DFM checks are sets of recommended rules in which the tolerance is set to a statistically altered value to increase the chip yield. Separate DRC checks for DFM rules are used and results may be analyzed to determine concentrations of shapes, which exceed the DFM limits.

Layout versus Schematic When physical design is completed, a verification check is necessary to compare the generated physical design to the simulated electrical design. This is the LVS process. Physical shapes are analyzed and matched to predetermined devices. Correctly formed devices as determined by the manufacturer are extracted. The device design and the extraction code must be developed such that the device can be

FIGURE 8.6.7

Manual fill lines channel the current for better modeling, auto-generated fill inhibits current flow.

© 2006 by Taylor & Francis Group, LLC

8.6-854

The Silicon Heterostructure Handbook

recognized by the extraction code as the device is built. These devices are checked for net connectivity and compared to that simulated in the schematic representation. Physical dimensions for these devices, which are used in the device model are compared with those which were simulated in the schematic. Standard comparison routines may be used for simple well-known devices and design styles, but many devices include unique parameterization, especially RF-type circuitry. These elements require custom comparison procedures. Inconsistencies are reported to the designer. Design practices involving connectivity are also checked during the LVS process. A common design practice for MOSFET layout is to interdigitate the devices in a common centroid layout for matching purposes. Such a practice takes the multiple schematic devices and merges them through abutment to form a single multichanneled device in the layout (Figure 8.6.8). For multichanneled devices in a single diffusion, each channel is extracted as a separate device then combined to ensure proper connection and matching to the schematic. Butted junctions, where a well contact and the source of a MOSFET are

FIGURE 8.6.8 Cell representations for interdigitated MOSFETs.

© 2006 by Taylor & Francis Group, LLC

CAD Tools and Design Kits

8.6-855

formed in the same diffusion active shape, are permitted in most silicide technologies and are a common layout practice. Contacts are required on the source side of the junction, and are optional on the well side of the diffusion. The source side must be contacted because of electrical and reliability concerns with the current-carrying capability of the silicide when it bridges both n- and p-type diffusions. Digital circuits generate high-frequency switching noise that is coupled into the substrate through the source–drain junction capacitances, bulk connections, and wiring. This noise signal can travel through the substrate where it may be introduced to sensitive analog circuits through wiring paths or substrate to bottom plate capacitance of MIM capacitors. The substrate network can be complex and specific regions must be designated. Substrate regions within a design for identifying different bulk areas within a chip must be extracted separately. These regions are necessary to isolate circuitry for noise and usually have physical barriers such as trenches or resistive moats. Separate regions allow the designer to study the effects of isolation versus coupled regions. CAD tools specific to substrate analysis are available to simulate the substrate effects due to integrating devices in local proximity with a common bulk material. These tools produce large simulation netlists, which are difficult to analyze for large chip areas. Firstorder effects, however, may be identified within LVS and simulated in a post-layout methodology. Process characteristics are checked during the LVS verification. Shallow-trench isolation (STI) induced stress and well proximity effects are two issues requiring explicit device parameter extraction to identify MOSFET model parameters to characterize device alterations within the process. The basic STI process sequence involves several sources of process strain, which can significantly increase the stress levels in the enclosed silicon area. This stress influences junction leakage and MOS electrical characteristics and must be extracted then passed to the device model. Proximity effects are caused by the erosion of the gate area caused by the scattering of ions during deposition that causes a change in Vth (threshold voltage) a device simulation parameter. The effects apply to both n-well and p-well devices. The effect is measured as a function of the distance between the gate and the well, weighted by the area of the gate affected. The erosion of the gate increases with decreasing distance.

Parasitic Extraction (PEX) Device interconnect introduces coupling effects to the device circuitry. These effects must be modeled for inclusion in design simulation. Estimation of the parasitic effects is critical for IC design and may alter the design point significantly. A typical IC design may contain thousands of devices with a broad frequency range and significantly more interconnect lines. During the PEX phase, each interconnect line is extracted based on the dimensions of the line, the vertical profiles of the process stack distance to adjacent conductors and the frequency of the signals traveling through the line. Parasitics include area and fringe capacitance of parallel plates of different conductors, parasitic diodes from diffusion, substrate or well, coupled capacitance for non-polarized capacitors, distributed resistance of conductors, and fringe capacitance of separation (non-overlapping) of like conductors (Figure 8.6.9). Skin resistance causes significant change in impedance for changing frequencies making inductance significant for gigabit frequencies. To this end, various extraction techniques must be employed in a given design. For designs below the 20 GHz range, parasitic RLC tools for estimation of parasitic effects may be used. Integrated mixed-signal designs often contain considerable metal density variation requiring a specific technology profile to define the stack heights and dielectric constants. Many parasitic extraction tools, however, produce large errors for sparsely packed wide metal geometries as in RF designs and in dense digital designs, large parasitic netlists remain a problem for resimulation. For critical interconnect estimation, a transmission line may be specifically modeled for accuracy. Transmission lines distribute the frequency and time-domain effects. For high-frequency designs, a three-dimensional field solver may be required for accurate investigation of key circuitry. It is necessary to identify the parasitics associated with the device model and that of the interconnect such that the coupling is not double counted. Identification shapes are useful for device boundaries so that the parasitic tool can couple internal parasitics to the shape and discard them in analysis as they are part of the modeled device.

© 2006 by Taylor & Francis Group, LLC

8.6-856

The Silicon Heterostructure Handbook

Wi+1 Li+1 = 20 µm

Mi+1

C2

C1

C3

Si,1-2

Li,# = 18 µm

Si,2-3

Mi,1

Mi,2

Wi,1

C5

C4

Mi,3

Wi,2 C9

Li-1 = 20 µm

C10

C7 C6

Wi,3 C8

Mi-1 Wi-1 Wi+1 = Wi-1 = Wi,1 + Wi,2 + Wi,3 + Si,1-2 + Si,2-3 + 6 µm

FIGURE 8.6.9 Parasitic capacitance for a metal stack.

Postlayout simulation stitching all parasitic analysis may be produced including all parasitic components and extracted devices with measured parameters. Nonphysical model parameters, such as substrate resistance and temperature variability, must be overlayed onto the extracted data for accurate simulations.

8.6.6 Chip Assembly Simulated and verified design blocks for both analog and logic circuitry are combined at the chip level. Combining the cell blocks and assembling the chip require unique tools and design practices. Full chip simulation for large designs is difficult and most times not possible due to too many devices, simulator performance, nonconvergence, and debugging concerns. Behavioral modeling becomes useful to characterize blocks of the design. Parameterized models promote cell reuse and are much faster than device-level simulation. System-level models promote top–down design techniques. Behavioral models are written in a high-level design language (HDL) to describe the functionality of the circuit in a mathematical equation. Mixed-signal languages require interaction between analog and digital sections, transferring the signal through some interface connect modules. Electrostatic discharge (ESD) protection is an important consideration in chip design and should be architected from the start of the design process [5]. All pins need a protection strategy, and ESD circuitry for a specific application must be designed according to the manufacturing design rules for chip protection. The three most common ESD test specifications are the human body model, the charged device model, and the machine model. The human body model (HBT) is intended to represent a discharge from a person touching one of the package leads. The human body has a large resistance, and the pulse is characterized by a decaying exponential function. The charged device model (CDM) represents a discharge that would be caused by chip or packaging handling equipment. The CDM is a brief discharge, with higher peak current and lower overall energy than that of the HBT and is distributed throughout the chip. The machine model (MM) represents a discharge to a pin by a charged piece of equipment. Current is more localized as in HBM, but peak current is high as in CDM.

© 2006 by Taylor & Francis Group, LLC

8.6-857

CAD Tools and Design Kits

Each of these events requires circuitry to dissipate the charge and protect the design circuitry. ESD protection circuitry can be built from common elements in the design kits to build a hierarchical circuit based on protection strategy. This circuitry consists of strings of diodes, RC-triggered power clamps, and Darlington clamps using varactors, HBTs, MOSFETs, and diodes. No new device characterization or modeling is required.

8.6.7 Chip Finishing Designs are delivered to the foundry by translating the layout data from the physical design database to an industry standard binary format such as GDS2 or CIF. It is a common practice to verify the data to be released to the foundry and the physical layout database by performing an exclusive or (XOR) check which will overlay the input GDS2 and the native database and run a shape check to determine any dropped or shifted shapes. A complete DRC verification and density check is required prior to manufacture. Many foundries run postlayout checks and alterations to input design data for yield and reliability improvements. Automated fill and slotting techniques for designs, which do not meet the density requirements, may be run at the foundry. These will introduce shapes to increase or decrease the density. These algorithms are programmed to include the design rules and look for design features such as RF sensitive circuitry and via farms. Layers used in manufacturing such as implant halos are auto-generated from design build shapes. Automatic generation of fill and design layers simplifies the layout for the end designer. To print manufacturable features on silicon, the physical design data must be modified post-tapeout (Figure 8.6.10). Optical proximity correction (OPC), phase shift mask (PSM) design, and scattering bar (SB) may be required. These techniques are grouped as reticle enhancement technology (RET). OPC introduces design rules on physical layout provide allowances for the effects of sub-wavelength lithography and process distortions not present in the design data. These rules produce better yield and reliability by introducing shapes or cut-outs such as hammerheads, inner–outer serifs, assist bars, biasing, and line-end serifs to produce the actual shapes designed by using the process tolerances and biases [6]. Many CAD tools are readily available in the industry to solve many of the design challenges, which highly integrated RF–mixed-signal chips face. It is essential, however, to customize the tools for optimal performance for a given technology given the requirements from the foundry and the design specifications established.

Conventional (no OPC)

Silicon image w/o OPC

Original layout 0.18 µm OPC layout

Silicon image with OPC

FIGURE 8.6.10 OPC rules force alterations to a conductor in order to manufacture corners.

© 2006 by Taylor & Francis Group, LLC

8.6-858

The Silicon Heterostructure Handbook

Acknowledgment The author would like to thank Don Jordan for contributions, editing, and general knowledge.

References 1. DL Harame, KM Newton, R Singh, S Sweeney, S Strang, J Johnson, SM Parker, CE Dickey, M Erturk, G Shulberg, D Jordan, D Sheridan, MP Keene, J Boquet, R Groves, M Kumar, DA Herman, and BS Meyerson. Design automation methodology and RF/analog modeling for RF CMOS and SiGe BiCMOS technologies. IBM Journal of Research and Development 47(2/3), 2003. 2. R Singh, C Dickey, and M Keene. RF-simulation algorithms: Which one is better for IC design? EDN, 8/22/2004 3. Kundert. The Designer’s Guide to SPICE & SPECTRE. Kluwer Academic Publishers, New York, 1995. 4. D Jordan and S Strang. Custom verification using DIVA and DFII. Transactions of the International Cadence Usergoup Conference, September 2001. 5. S Voldman et al. Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors. International Reliability Physics Symposium, March 2000. 6. L Thenie. Implementing OPC correction in a mask data preparation flow. Transactions of the International Cadence Usergroup Conference, September 2000.

© 2006 by Taylor & Francis Group, LLC

8.7 Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs 8.7.1 8.7.2

Introduction............................................................... 8.7-859 Substrate Noise Isolation and Coupling ................. 8.7-860 Substrate Noise Coupling . Modeling Substrate Noise . Substrate Isolation: Predicting Isolation through TCAD and Test-Site Structures

8.7.3

Interconnect Modeling and Loss ............................. 8.7-864 Modeling versus Extracting the Interconnect Parasitics . Parasitic Interconnect Inductance

8.7.4

General Noise Mitigation Guidelines . Substrate Noise Mitigation Guidelines

Raminderpal Singh IBM Systems and Technology Group

Mitigating Circuit Parasitic Noise Effects ............... 8.7-867

8.7.5

Summary .................................................................... 8.7-868

8.7.1 Introduction As SiGe processes migrate and lower in cost, opportunities for higher levels of circuit integration and faster signal frequencies arise. In addition, as signal voltage headroom has dropped (due to technology scaling) and circuit ‘‘noise activity’’ has risen (due to higher digital and oscillator frequencies and higher levels of integration), an urgent need has arisen for accurate understanding and modeling of the coupling paths to and from each sensitive part of the circuitry. A key challenge has become the modeling and design of the parasitic effects of the passive devices, IC package, interconnect, and substrate. Figure 8.7.1 abstractly shows the resistive, capacitive, and inductive parasitics that affect the circuit performance. These effects cover most (probably not all) coupling and leakage paths possible, and are very significant and complex, often gating first pass design and product success. In this chapter, we focus on the topics of interconnect and substrate parasitic modeling and noise mitigation. Not all noise concerns are covered in this chapter, as SiGe offers design potential of integrated on-chip circuits with frequencies up to 100 GHz today [1]. Effects such as electromagnetic (EM) coupling also need thought, at millimeter-wave frequencies (40 GHzþ). There needs to be an integrated design methodology to allow the designer to probe and measure how the design performance is affected by the parasitics. Additionally, no single modeling methodology is 8.7-859 © 2006 by Taylor & Francis Group, LLC

8.7-860

The Silicon Heterostructure Handbook

Package, RLC

Interconnect coupling, C (RL)

Bond pad and bond wire, RLC

Interconnect, RCL and transmission line models

Substrate model, R (C)

Guard ring, with very low R

FIGURE 8.7.1 SiGe integrated circuits today involve a combination of circuits, with different characteristics, building for a complex parasitic modeling problem.

sufficient to model and design with all these complex effects, throughout the RF IC design flow. Figure 8.7.2 shows a high-level view of an RF–analog custom IC design flow typically used by designers. Transmission line models are included here, as a needed but not yet prolific part of the design community. Additionally, it is very important that the SiGe designer includes the effects of the IC package, as shown in the figure. Ideally, co-design of the package with the silicon circuit is needed. But, this is not always possible, especially when the package and IC are coming from different design groups or companies. In these cases, careful hand-off and early specifications are critical. Finally, there is a need for guidelines to mitigate these parasitic effects in the circuit design. This discussion is qualitative and directional, but helps guide designers on some of the key nuances in trying to balance the parasitic effects against the design specifications and schedule.

8.7.2 Substrate Noise Isolation and Coupling Substrate noise has emerged as a real parasitic effect since the mid-1990s. The noise itself has existed in the silicon substrate for far longer, due to digital circuit switching and on-chip oscillators. The difference is that the coupling effects are now significant and more acute, and designers are observing performance degradation due to them. Figure 8.7.3 shows the effect of oscillator signal self-mixing to create an effect called DC Offset, in direct conversion receivers. This effect is caused by the oscillator signal coupling through the substrate, and has caused complex design techniques to be used to avoid the self-mixing to the DC frequency range. Notably, design techniques [2] are very commonly used to avoid the problem. However, finding a solution requires more than design experience — i.e., modeling and estimation tools have a critical role to play in aiding the designer’s decisions.

Substrate Noise Coupling Figure 8.7.4 describes the mechanisms for substrate noise injection into the silicon substrate. Simply, electrons in the circuit follow lower AC impedance paths to the circuit ground. The chip substrate often

© 2006 by Taylor & Francis Group, LLC

8.7-861

Parasitic Modeling and Noise Mitigation

RF-AMS IC

Package Schematic Capture

Device-level Transient Simulation

Transmission Lines Substrate Isolation estimation

Mixed-Signal Simulation

Simulation Environment

Electrical package design & modeling

Frequency Domain Simulation

Layout Transmission Line PCells

Resimulation Physical Verification

Parasitic Extraction Interconnect RLC Substrate Modeling

Package design

GDS II Tape-out

FIGURE 8.7.2 The RF-AMS IC design flow is complex, including several different point tools. There is also a need to carefully co-design the package, as illustrated here.

Self-mixing of interferer

LNA

Mixer

LO signal selfmixing through substrate VCO

FIGURE 8.7.3 Substrate coupling leading to LO feedthrough, in a Direct Conversion Receiver.

offers impedance paths to other points of the circuit and current noise in the substrate results. The mechanisms can be summarized as: .

.

Substrate noise current injections from active devices, such as rail-to-rail and high-frequency switching HBTs (e.g., in local oscillators) and switching FETs (i.e., digital switching circuitry). Capacitive coupling effects from lower level interconnects (e.g., M1) and passive devices. This mechanism has had little focus on by modeling, tool, and design teams. But, it is a

© 2006 by Taylor & Francis Group, LLC

8.7-862

The Silicon Heterostructure Handbook

p+

Digital FET/ switching HBT n+ n+

Interconnect/ passives analog/rf n+ n+

p+

Current noise flow, based on substrate voltage bounce

FIGURE 8.7.4 There are several mechanisms for substrate noise injection into the substrate.

TABLE 8.7.1 Comparison between Substrate-Doping Levels (p-Type Substrate) and the Effective Cutoff Frequency, When the Capacitive Effects of the Substrate Become Significant Doping Level (cm3) 1014 1015 1016 1018

.

Resistivity (V cm)

fc (GHz)

125.6 12.7 1.4 0.035

1.2 12.0 >100 >1000

contributing factor, even with capacitive shielding (i.e., oxide) between the interconnects and the substrate. Native resistive connection to the substrate of substrate contacts and connected ground rails. This effect is often the dominant mechanism — i.e., large ground planes in digital circuitry virtually control the substrate voltage bounce in the region and sometimes the whole chip — depending on the chip floor plan and nature of the other on-chip circuitry.

As the frequency of the signal rises, the nature of the substrate impedance moves from ‘‘real’’ (i.e., resistance) to complex (i.e., resistive and capacitive) [3]. This ‘‘cutoff ’’ or transition frequency for the substrate depends on the doping level. Table 8.7.1 lists out a few data points mapping the doping level, to the cutoff frequency. These data are used by substrate modeling tools, but can also be used by designers when thinking about substrate effects due to different circuit blocks (with different frequencies).

Modeling Substrate Noise In recent years, there have been numerous papers published [4] attempting to offer practical and usable approaches to model substrate coupling. This realization has arisen from the adoption of single IC solutions, where smaller gate lengths have led to higher frequencies of circuit operations and to high levels of integration. Given these trends, it is somewhat surprising that substrate-modeling methodologies are not yet common in commercial verification design flows. This is partly because substrate modeling requires complex breakdown of the three-dimensional silicon body and methodology inefficiencies often lead to impractical extraction and simulation times as well as large memory requirements. Several algorithms [4] attempt to model the full nature of the silicon and interface to the circuitry, to a high level of detail. This may include three-dimensional numerical modeling techniques and close linkage to the device modeling methodology used. Some of the key difficulties with this approach include: 1. The size of the netlists extracted are large — approximately n2/2 for n substrate ports connecting to the design — and need reduction for any practical circuit analysis. This leads to heuristic assumptions in the reduction, which dilutes the value of the original algorithm.

© 2006 by Taylor & Francis Group, LLC

Parasitic Modeling and Noise Mitigation

8.7-863

2. The methodology implementation is dependent on a close tie to the silicon process technology used, which requires much work in integrating the device models and device layout extraction code. This is a risky process, given the margin for error in the complexity of the device models and device layout extraction code. 3. This methodology does not handshake well with the interconnect extraction–modeling methodologies used. So, the effect of the interconnects and even the substrate contacts can be easily missed or inaccurately modeled. 4. For most designers, there is a need for estimation of the substrate effects early in the design flow, for floor planning–layout design purposes. The silicon extraction approach assumes layout is complete or near to complete, and are hence used in a circuit sign-off mode not a circuit design mode — where it is needed. Another set of algorithms exists [4] with estimation of the substrate effects as a starting point. These approaches typically try to capture the dominant activity in the noise injection circuitry (e.g., switching activity of digital circuit blocks) and map them to sensitivity analyses of the sensitive (e.g., RF) circuit blocks. Macromodeling of the different circuit blocks is often tried, to try and reduce the size of the problem. Some comments on this general approach include: 1. The approaches have the general benefit of looking to at the design trade-offs based on limited available data — e.g., block-level floor plan. The effectiveness of this methodology has not yet been proven, but the impact is earlier in the design flow. 2. Because limited data are used, these algorithms sometimes follow the ‘‘junk in, junk out’’ approach. This problem is hard to avoid, with designers and CAD engineers often conflicting about the ultimate value of the results. 3. There is no leading commercial implementation of this approach, available today — although there have been many ideas and several prototypes in universities. Without proliferation and broad usage, it is difficult to prove the value for the common design space — especially as the effects vary depending on the application design.

Substrate Isolation: Predicting Isolation through TCAD and Test-Site Structures From the designer’s perspective, the most commonly understood and apparent need for substrate modeling is in the prediction of block-to-block isolation or impedance. Given this, there are a couple of focused and useful methodologies that could be used to aid the designer, which avoid the need for complex substrate modeling tools and methodologies. 1. TCAD predictive modeling — TCAD tools have been used for several years to understand the effects of coupling between active and passive devices. TCAD can also be effectively used to verify substrate isolation in chip floor plans (SiGe book), providing for value and impact early in the design flow. The capabilities also improve as the algorithms move from two-dimensional to three-dimensional modeling, with some results shown in Figure 8.7.5 and Table 8.7.2. This work has been done in IBM’s 0.25 mm SiGe 6HP process technology, where digital circuits are often integrated. The results compare the three-dimensional TCAD simulation data with measured data for a range of test structures. As can be seen, the results are very close, demonstrating the value of the TCAD tools. One still has to be careful with these data, as real circuit designs have numerous devices and have complex ground and parasitic paths that TCAD simulations cannot adequately capture — due to memory and CPU limitations. Nevertheless, this methodology is useful for high-level first-order analysis. 2. Substrate isolation test site structures — the use of test-sites to verify accuracies of substrate modeling tools is common. However, there has been a stream of papers that have brought forward useful methodologies for developing fitted equations to predict the impedance between points and even circuit blocks [3]. In many senses, this is a ‘‘home run’’ for the designer, as the

© 2006 by Taylor & Francis Group, LLC

8.7-864

The Silicon Heterostructure Handbook

FIGURE 8.7.5 IBM 0.25 mm 6HP SiGe test site structures used to verify accuracy of IBM’s three-dimensional TCAD modeling methodology and tool. Each structure has a noise transmitter point and a receiver point.

TABLE 8.7.2 Measured and TCAD Simulated Results from Test Structures Shown in Figure 8.7.5 Device

W W W W W

¼ ¼ ¼ ¼ ¼

10u; D ¼ 50u 10u; D ¼ 100u 10u; D ¼ 100u 50u; D ¼ 50u 100u; D ¼ 50u

0.6 23 27 32 16 13

Measurement

Simulation Data

jS21j (db) at

jS21j (db) at F

23 27 32.7 16.1 13.5

2 23 27 32.8 16.6 13.8

0.6 23.25 26.10 31.44 16.5 12.96

2 23.25 26.27 31.43 16.5 12.95

10 23.10 25.84 31.29 17.06 12.82

30 22.06 23.62 30.25 14.88 11.86

results are specific to a process technology and hardware derived. In addition, through the use of TCAD simulations, the test-site fitted equations can be broadened to include different isolation structures and dimensions.

8.7.3 Interconnect Modeling and Loss Interconnect extraction is a very common, and almost an assumed part of the SiGe IC design flow today (see Figure 8.7.2). However, as signal frequencies and levels of integration have risen, there is a need for a deeper understanding of key challenges faced by the designer.

Modeling versus Extracting the Interconnect Parasitics There are two ways to predict the effect of the interconnect parasitic impedances — modeling and shape-based extraction. Which approach to use depends on the types of signals on the interconnect and the level of accuracy required. Modeling: This involves the development of fitted equivalent circuit models, from experimental (using hardware and software methods) data. These models are typically distributed in nature (e.g., RLC ladder

© 2006 by Taylor & Francis Group, LLC

Parasitic Modeling and Noise Mitigation

8.7-865

networks) parameterized. For interconnects with RF signals — i.e., analog signals at 1 GHzþ frequencies — there is a need for S-parameter characterization and modeling, as well as modeling of any impedance mismatches and losses. Full-wave EM tools are needed to model the effects, as well as test-sites allowing RF measurements (S-parameters) to be taken. This methodology has been described in detail in Chapter 8.8 on transmission line modeling. This methodology enables a growing field of interconnect-aware design, where the transmission line parasitics are designed as part of the circuit performance from the early stages of the design [5]. Extraction: This involves commercial software integrated into the design flow. The software breaks down the interconnect structures into small polygons, and uses precalculated look-up tables and coefficients to extract the RLC for each polygon. For interconnects carrying time-domain signals — i.e., digital — the accuracy is best modeled by comparing the extracted parasitic resistances (R), capacitances (C), and inductances (L) from the chosen interconnect extraction tool to a golden standard extractor. For hardware verification, the methodology required is to look at the measured delay from ring oscillators and other circuits. Extraction algorithms are typically shape-based — i.e., they calculate the parasitic R, L, and Cs from the physical dimensions of the interconnect. The advantage of this is that any shape can be analyzed. Conversely, analyzing complex structures with shape-based extractors leads to stray parasitics being netlisted, especially where discontinuities in the metal occur. Each of these methods has certain advantages and disadvantages. For example, if S-parameters are used in the accuracy verification (using full-wave EM modeling tools or RF measured data) for interconnects carrying digital signals, then there is room for error in the setup of the measurement– modeling structures. Conversely, if the models are aimed to be broadband and are applied to narrowband high-frequency signals, then the accuracy at a particular frequency may not be sufficient. Hence, there needs to be sufficient knowledge and expertise of the application and signal type. In SiGe designs, there is sufficient mix of both analog–RF and digital signals that both types of modeling and extraction are needed in the design flow. This leads to a more complex design environment.

Parasitic Interconnect Inductance Parasitic inductance effects are regularly discussed in literature [4, 6, 7], both for RF and digital designs. .

.

For RF designs, the effect of inductance is more prominent as the frequencies are higher. RF designers have for many years needed to predict and back-of-the-envelope estimate the transmission line effects in their designs, in order to meet circuit performance. As SiGe technologies have advanced, the situation has become more acute and a need has arisen for more integrated and proven transmission line structures (see Figure 8.7.6) to accurately model the frequency-dependent parasitic inductance, as well as resistance and capacitance. – Another concern for modeling RF signals is the effect of the substrate leakage path [3]. The silicon substrate is effectively a resistive and capacitive load on the interconnect. As the signal frequency rises to the cutoff point of the substrate (see Table 8.7.1), the substrate becomes more capacitive in nature and can provide a lower AC impedance path to ground for the signal. Hence, signal loss from the interconnect to the substrate may occur. The simplest method to avoid this effect is to use microstrip structures, which control the loss (see Figure 8.7.6) using physical ground shields. In designs where the RF interconnect routing is dense — e.g., highspeed integrated data converters — space is not always available for ground shields. In such cases, the interconnect to substrate effects needs to be modeled using novel hardware-correlated techniques as part of the RF IC design flow [3]. For digital designers, the impact of the parasitic inductance is dependent on several issues — such as switching activity and the net resistance. Previous publications have discussed the key guidelines for when digital designers should take inductance seriously in their design flow [4]. Determination of when to take inductance into account is complex, but simple guidelines can

© 2006 by Taylor & Francis Group, LLC

8.7-866

The Silicon Heterostructure Handbook

FIGURE 8.7.6 Parasitic extraction tools are not always sufficient for SiGe communication designs, and microstrip line models are needed in integrated design flow.

Partial equivalent inductance

Loop inductance

V V

FIGURE 8.7.7 Inductance extraction of metal interconnects is often done using either PEEC or loop inductance. Each approach has its benefits and drawbacks, for the analog–RF designer.

be used to the first order — based on the net impedance, switching activity, return path. Some algorithms have already started to use this. Inductance extraction algorithms have (and continue to) advanced over the years, but are fundamentally tied to one of two methodologies [7] (see Figure 8.7.7): 1. Loop-based inductance — this methodology assumes a known dominant return path, and provides a reduced netlist comparable in size of the transmission line models. Inherently, this approach is useful for simpler routing patterns. 2. Partial equivalent electrical circuit (PEEC) — this methodology is very commonly used today for interconnect modeling, as it allows for complex interconnect structures and return paths. The netlist generated is, however, significantly larger than that of the transmission line model or extraction using loop-based algorithms. Another consideration to be aware of, is the assumption that the substrate makes a good return path [6]. The validity of this assumption is tied to the conductive nature of the substrate, which is proportional to the doping concentration level. The doping varies from foundry to foundry (typically, between 1 and 15 V cm), and even between processes, and sometimes low doping is used to raise the substrate impedance — for device design benefits and for higher inherent substrate isolation. The designer should always make some back-of-the-envelope calculations to check whether the substrate is a valid return path.

© 2006 by Taylor & Francis Group, LLC

Parasitic Modeling and Noise Mitigation

8.7-867

8.7.4 Mitigating Circuit Parasitic Noise Effects General Noise Mitigation Guidelines SiGe RF–mixed-signal designers are often faced with a complex set of trade-offs and noise paths that cannot be precisely modeled or quantitively reduced. To help provide some insight and direction, some general mitigation techniques that circuits designers often use to preserve the quiet of mixed-signal ICs, include [8]: .

.

.

.

.

. .

Use smallest possible output driver to reduce switching noise. Output drivers are high contributors to overall substrate and power grid noise. Shut down switching functions of the rarely used logic circuits to reduce loading capacitance, and hence switching noise. Avoid long traces, long parallel runs near known noise sources, changing layers when possible. This will lead to less net-to-net coupling. Not to let Spice simulations that indicate no problems lull designers into a false sense of security. Many times, inaccurate modeling or incomplete simulation strategies lead to speculative results, which may not capture key noise-coupling issues. Pick the quietest portion of the clock cycle for sampling. In this way, less noise is picked up during sampling. Distribute the bias signal as a current to improve the resistance to noise. Use parallel supply connection instead of a series daisy chain of power connections. This leads to lower impedance paths, improving the tie down to AC ground.

Substrate Noise Mitigation Guidelines Substrate noise components can be broken down to RF and DC for the most. RF substrate noise is typically based on the clock or the VCO frequency and is typically higher for the rest of the circuit. This noise can be easily identified and partially protected against, from sensitive circuitry, using frequency planning and substrate-isolation techniques. DC substrate noise is typically generated from lowfrequency ground bounce effects, and as such is much harder to protect against — as the ground routing can cover a large portion of the design layout area. A handful of cost-effective structures and techniques [3] specific to reducing substrate noise coupling, include: .

.

. .

.

.

Guard ring structures around the noisy and sensitive circuitry, usually tied to dedicated package pins for closer AC grounding. Note that, in RF designs, a dedicated pin is not always available. NWELL trenches and deep trenches (DT) between the noisy and sensitive circuitry to block the substrate current flowing near the surface of the substrate. Differential circuitry — a favorite for RF designers. Lower package parasitic inductance (for the pins), causing stronger AC grounding of the substrate. This is a very effective but sometimes expensive approach due to the extra package costs. Lower inductance is also accomplished through multiple or shorter bond wire connections, or flip-chip area I/O packages. Note that corner pins have higher parasitic values than center pins. Careful floor planning can also be used. The idea is that the farther the sensitive and noisy circuits are, the less the substrate coupling will affect the circuit’s performance. Figure 8.7.8 shows an abstract view of the common approach to sensible floor planning. Use of an exposed paddle structure, to which the IC bondpads are downbonded, connected effectively to the PCB ground. This is another common technique, and is very effective. One has to be careful to realize that the analog and digital grounds are now common in the system.

© 2006 by Taylor & Francis Group, LLC

8.7-868

The Silicon Heterostructure Handbook

Low amplitude analog circuits

Medium amplitude analog circuits

High amplitude analog circuits

P+ Guard Rings Low speed digital circuits

High speed digital circuits

Digital output buffers

FIGURE 8.7.8 Careful floor planning should be used to reduce the effect of substrate coupling between different circuit blocks. In this example, the primary noise sources are the digital output buffers.

8.7.5 Summary In this chapter, we have covered numerous relevant and significant topics to aid SiGe RF–mixed-signal IC designers. There are no absolute solutions to accurate modeling and noise mitigation, but — with a combination of experienced designers, good modeling algorithms and methodologies, and useful and practical guidelines for noise mitigation — there is ‘‘light at the end of the tunnel.’’

Acknowledgments The author would like to thank Wayne Woods, Youri Tretiakov, Nick Lam, Bob Barry, Mukesh Kumar, and Rajendran Krishnaswamy for their help in pulling together the needed data and content for this chapter. Special thanks also goes to Ramana Malladi, for his help in reviewing this chapter.

References 1. J. Robert Lineback. IBM Claims Proof of SiGe Beating InP and GaAs Chips in Future. http:// www.siliconstrategies.com/story/OEG20020225S0010, 2002. 2. W. Namgoong and T. Meng. Direct-conversion RF receiver design. IEEE Trans. Commun. 49:518–529, 2001. 3. R. Singh, D.L. Harame, and M. Oprysko. Silicon Germanium — Technology, Modeling, and Design. New York, NY: John Wiley & Sons, 2003. 4. R. Singh. Signal Integrity Effects in Custom IC and ASIC Designs. New York, NY: John Wiley & Sons, 2001. 5. D. Goren, M. Zelikson, T.C. Galambos, R. Gordin, B. Livshitz, A. Amir, A. Sherman, and I.A. Wagner. An interconnect-aware methodology for analog and mixed-signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach. Design Automation and Test in Europe Conference and Exhibition, Paris, 2002, pp. 804–811.

© 2006 by Taylor & Francis Group, LLC

Parasitic Modeling and Noise Mitigation

8.7-869

6. C.K. Cheng, J. Lillis, S. Lin, and N. Chang. Interconnect Analysis and Synthesis, Chapter 5. New York, NY: John Wiley & Sons, 2000. 7. K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao. Inductance 101: analysis and design issues. Design Automation Conference, Las Vegas, 2001, pp. 329–334. 8. C. Falcon. Preserve the Quiet in your Mixed-Signal ASIC. Electronic Design Magazine, March 18, 2004, pp. 81–86.

© 2006 by Taylor & Francis Group, LLC

8.8 Transmission Lines on Si 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5

Youri V. Tretiakov RF Micro Devices

8.8.6

Introduction............................................................... 8.8-871 Transmission Line Technology ................................. 8.8-871 Modeling Aspects ...................................................... 8.8-872 Transmission Line Measurements............................ 8.8-875 Transmission Line Examples and Applications ............................................................... 8.8-876 Summary .................................................................... 8.8-878

8.8.1 Introduction Microstrip, strip transmission lines, and coplanar waveguides are often utilized in high-speed radiofrequency (RF) integrated circuits (IC), digital and mixed-signal applications [1–6] to avoid signal integrity problems for critical transmission line interconnects. These transmission lines can range from narrow digital clock nets over a wide common ground plane to wide analog interconnects in power amplifiers. Traditionally, transmission line interconnects are employed to control high-frequency distributed impedance effects that become important as the wavelength approaches a fraction of the interconnect line length. Increasingly, transmission line structures are also employed to isolate critical interconnects from the lossy substrate either through reference ground plane shielding signal lines from below or field containment in coplanar-like structures. They can also serve as the open and short stubs [4] or as the input, output, and interstage interconnects [5] for matching purposes. Essential to transmission line capability is both the technology in which it is implemented, and also an accurate and flexible design system. The transmission line technology establishes structural constraints. The design system enables the designer to understand these trade-offs and establish the design first-pass success.

8.8.2 Transmission Line Technology From a technology point of view, the design of the metal interconnect stack takes into account many issues that are not obvious at first glance. Compatibility with high-performance CMOS, integration with low-cost metal–insulator–metal capacitors as well as low-cost wire-bond need to be taken into account. The most simple transmission line structures to design and manufacture are microstrip lines [1] and coplanar waveguides [7, 8] shown in Figure 8.8.1. The microstrip line interconnects with possible side shielding are effectively shielded from the substrate below to eliminate the silicon substrate losses and minimize coupling to other circuit elements. Optional side shielding is usually made of stacked vias. They work well as the side electromagnetic shield walls. Usually, top thick metal layers are used as signal 8.8-871 © 2006 by Taylor & Francis Group, LLC

8.8-872

The Silicon Heterostructure Handbook

Signal ground

Single wire with bottom shield

Single wire with bottom and side shields

Coupled wires with bottom shield

Vias

Coupled wires with bottom and side shields

Signal ground

Silicon substrate

Silicon substrate

Single wire coplanar waveguide

Coupled wires coplanar waveguide

FIGURE 8.8.1 Transmission line interconnects: microstrip lines and coplanar waveguides.

wires with a thinner ground shield on the lower copper layers. This enables the use of microstrip lines for the most critical interconnects including power lines in RF power amplifiers. At the same time, the coplanar waveguide interconnects (see Figure 8.8.1) do not have bottom metal shield. The possible losses in the silicon substrate below are minimized by introducing the side shield lines at the same metal layer as signal ones. To enable the high-performance CMOS on the same chip, the tight-pitch thin-wire metal system nearest to the silicon must be established in the same way as the digital technology. On top of these thin metal layers, thick metal layers with thick interlevel dielectrics create low resistance films and low unit area capacitance. This combination is favorable for the low loss and high impedance required by designers. An alternative way to the low interconnect resistance, inductance, and losses is to use the stacked interconnect structures. The example of such a vertically stacked interconnect can be found in Ref. [8]. The major technology requirement for stacked interconnects to exist on a chip is the good manufacturability of long (a few hundreds of mm) via bars. If they can be manufactured, vertical coplanar waveguide devices have more flexibility in terms of impedance matching and loss control rather than single layer coplanar waveguides [8].

8.8.3 Modeling Aspects A key element to design of transmission lines is the ability to rapidly optimize transmission line geometry during the IC design stage. Device component equations are calculated in the component description form (CDF) as well as the model files, including compatible interconnect libraries for a broad range of industry-leading Spice-compatible tools.

© 2006 by Taylor & Francis Group, LLC

8.8-873

Transmission Lines on Si

A suitable interconnect modeling methodology is through the development of Spice-compatible lumped element models [9], preferably passive by construction. The models are usually parameterized (with respect to IC technology process metal stack and geometrical dimensions) frequency-dependent RLC lumped circuits that have been correlated using hardware, RLC extraction, and full-wave electromagnetic (EM) solver software. If the constructed model uses only frequency-independent RLCelements, then it can be used easily for both time and frequency-domain simulations. Therefore, the transmission line interconnect modeling sometimes is challenging due to the presence of frequencydependent skin and proximity effects. The frequency-dependent losses in the silicon substrate also have their significant impact on major interconnect electrical parameters (especially in coplanar waveguide structures). The general transmission line network representation is shown in Figure 8.8.2. The rule here is to have at least a few (usually 10) basic ZY-segments per minimum signal wavelength in a particular IC design. We should mention here that the simple lumped element network representation shown in Figure 8.8.2 is valid only when the explicit current return path is a part of a transmission line interconnect at all frequencies (from DC and up to RF). In real-life designs, this condition is difficult to satisfy since at low frequencies return current flows where the resistance is the lowest and at high frequencies current flows in a way that it minimizes the total loop inductance (and hence total loop impedance). Therefore, in general case the current return paths at DC and high frequencies can be different, especially if there is an alternative current return path (such as power grid) in the vicinity of a transmission line interconnect. In that case, the network shown in Figure 8.8.2 is not valid anymore. This results in the fact that each piece of metal (signal lines, ground return paths) should be treated in the same way. Each metal shape has selfresistance, capacitance, and inductance. In addition to that, all pieces of metal also have mutual coupling (inductive and capacitive). As a result, the developed interconnect model can be very complicated so it models properly the DC interconnect behavior (low-frequency IR drop for instance) as well as its highfrequency characteristics (impedance, loop inductance, S-parameters, and time delay). In the case of a well-defined transmission line interconnect (where the current return path is known), the Z-elements in Figure 8.8.2 describe longitudinal currents in metal and silicon substrate. At the same time, the Y-elements are responsible for modeling of transverse currents in metal and a substrate. Therefore, all lumped RLCG-elements in Figure 8.8.2 can be frequency dependent. Figure 8.8.3 shows their most common frequency behavior. The transition frequency for the L-element in Figure 8.8.3 is

Several segment per wavelength

Z

Z Y

Z Y

Z Y

Y

T-line segment Z-element: longitudinal current in metal and substrate

R(f )

L(f )

G(f ) T-line segment FIGURE 8.8.2 Transmission line network representation.

© 2006 by Taylor & Francis Group, LLC

C(f )

Y-element: transverse current in metal and substrate

8.8-874

The Silicon Heterostructure Handbook

L0

R(f )~f 0.5 L(f )

R(f )

L⬁

R0

ftr

f

f

0

0

G⬁

C0 G(f ) frel

C(f )

C⬁ frel

f

0

f

0

FIGURE 8.8.3 Frequency behavior of the RLCG elements.

L(f )

R(f )

L⬁

∆L

∆G

∆L

∆G

∆L

∆G

One basic element for each freq. decade ∆L1 L⬁

∆Ln

R0 ∆R1

∆Rn

FIGURE 8.8.4 Modeling of the Z-elements.

when the skin depth is comparable with the relevant interconnect cross-section dimension (thickness or width). For the GC-elements, the relaxation frequency depends on silicon substrate properties [10]. As we mentioned before, it is desirable that transmission line equivalent models use only series of lumped and frequency-independent RLC-segments. To model frequency-dependent effects (skin and proximity effects, silicon substrate losses) from DC till the given chip technology transistor cutoff frequency, so-called ladder networks have been developed and used extensively in the past [1, 10, 11]. Most popular examples of such ladder networks are shown in Figure 8.8.4 for LR-elements and in Figure 8.8.5 for GC-parameters. More details on the proper ladder network design can be found in Refs. [1, 10, 11]. We just mention here that in the case of a microstrip transmission line the capacitance is usually constant over the whole range of interest. The G-element can also be neglected. Therefore, microstrip line models usually have in their network only ladder networks shown in Figure 8.8.4. At the same time, for coplanar waveguide all RLCG-elements are frequency dependent. That makes models to be more complicated since now they have ladder networks to describe the frequency behavior of RL and CG elements. We should also stress here that all elements in Figure 8.8.4 and Figure 8.8.5 are frequency independent. They are passive by construction and easy to netlist in commercial Spice-like simulators. All ladder network-building elements depend only on an interconnect geometry, IC technology backend-of-the-line (BEOL) stack and derived based on low- and high-frequency interconnect behavior.

© 2006 by Taylor & Francis Group, LLC

8.8-875

Transmission Lines on Si

Cox

Cside G(f )

C(f ) Gs

Cs

Signal to metal ground

∆Cox1

Coxo ∆Gs1

∆Cs1

∆Coxn ∆Gs1

∆Csn

FIGURE 8.8.5 Modeling of the Y-elements.

As far as basic RLC blocks are concerned, C and L parameters must be calculated carefully to take into account mutual electromagnetic coupling. As it can be seen from Figure 8.8.3 and Figure 8.8.4, it is required to know only their low- and high-frequency limits to finish building an interconnect lumped element network. That can be accomplished using quasi-static transverse electromagnetic (TEM) approximation to calculate low-frequency capacitance and inductance [12] of an interconnect. The quasi-static approach has a good accuracy because the cross section dimensions of on-chip interconnects are usually very small in comparison with the shortest on-chip wavelength even for high frequencies of operation. After low-frequency capacitance is estimated, it is used to calculate high-frequency inductance limit. The next step combines low- and high-frequency inductance values to construct ladder networks. The final transmission line models have strong frequency dependencies of resistance and inductance for microstrip line.

8.8.4 Transmission Line Measurements The accurate simulation and modeling of on-chip passive devices such as transmission line interconnects are critical for the design to be successful. The increasing operating frequency of integrated circuits has enhanced the need to accurately model standard transmission line components over a wide frequency range (DC to 100 GHz). To develop accurate models, measured test site S-parameter data (with subtracted pad parasitics) need to be available. Major interconnect electrical parameters such as inductance (L), resistance (R), capacitance (C), and characteristic impedance (Z) can then be extracted and compared versus device model prediction. Before designing an interconnect test site, there is the need for proper measuring padset. The main advantage of a well-defined transmission line interconnect is its explicit current return path, which is a part of an interconnect device. As a result, there is no need to create the on-wafer ground ring around an interconnect under study. The ground contacts of probe tips at both interconnect ends will have a good on-wafer electric connection through the interconnect current return path. Therefore, the designer has only to shield effectively measuring padset from the silicon substrate below to create the padset device, which have well-defined (preferably frequency independent) parasitics. This allows the accurate deembedding of padset parasitics during the analysis of measurement data. We mention here the design described in Ref. [13] as a good example of the properly shielded measuring padset.

© 2006 by Taylor & Francis Group, LLC

8.8-876

The Silicon Heterostructure Handbook

A number of simple and accurate de-embedding techniques have been developed in the past for onwafer active and passive device characterization. Although these methods have been already employed to study on-chip transmission line interconnects [14, 15], we will briefly review them here. Here, the focus will be on methods that model the measuring padset structure to be de-embedded by the series impedance and shunt admittance [13, 15–19]. Among on-wafer de-embedding techniques is the well-known ‘‘open-short’’ method [16], which is given by Ydut ¼

Ymeas Yopen

1

Yshort Yopen

1 1

,

(8:8:1)

where Yopen, Yshort denote the two-port admittance parameters measured on the ‘‘open’’ and ‘‘short’’ devices, Ymeas is the measured two-port admittance of the device, and Ydut is the de-embedded Y-parameters of the device under study. A second de-embedding technique based on the same ‘‘open’’ and ‘‘short’’ dummy structures has been proposed in Ref. [17], which switches the order of the series impedance and parallel admittance compared to the ‘‘open-short’’ method in Ref. [16]: Ydut ¼ ðZmeas Zshort Þ1 Zopen Zshort

1

:

(8:8:2)

Based on the assumption that the structures to be de-embedded on both ends are identical, another very powerful method (especially for on-wafer transmission lines) is the simplified ‘‘thru’’ de-embedding algorithm [15], which uses only two devices: the device under question with attached measurement pads and a simple dummy ‘‘thru’’ structure. This facilitates the whole de-embedding procedure and saves test site chip space. A detailed description of the ‘‘thru’’ method can be found in Ref. [15]. For most practical cases though it is difficult to adequately design a good ‘‘thru’’ structure where left and right pads are effectively uncoupled. Increasing distance between pads and measurement frequency cause the interconnect line connecting left and right pads of the ‘‘thru’’ device to behave as true transmission lines, which would have to be described by a distributed topology. Therefore, the easiest way would be to treat that connecting line to be also a true transmission line. Based on this, the use of only two devices has been proposed in Ref. [19]. The new de-embedding method uses only L1 ¼ L and L2 ¼ NL (N, the discrete number) long interconnects with attached pads. As a result of measuring only these two devices, they can be both de-embedded. The immediate advantage of the proposed in Ref. [19] technique is that left and right pads can be separated far enough to minimize mutual coupling between them. In that case, the new method treats the interconnect connecting pads as a true transmission line device, which improves the overall deembedding accuracy. The proposed method also eliminates the need for dummy ‘‘open,’’ ‘‘short,’’ and ‘‘thru’’ devices, which sometimes impose an additional challenge to the designer.

8.8.5 Transmission Line Examples and Applications As the first example, we simulated a single wire transmission line without side shielding (see Figure 8.8.1) using the same lumped element model as the one adopted in Ref. [1]. The industry standard Spectre tool has been employed as the simulation engine. Figure 8.8.6 represents S-parameter correlation results (model versus EM solver) over a wide frequency range of 0.1 to 40 GHz. We also compared the above test case with on-wafer measurement results. They can be found in Figure 8.8.6, and are accurate to within acceptable levels with S21 magnitude differing by less than 1 dB across the whole frequency range of interest. The transmission line characteristics, shown in Figure 8.8.6, are quite accurate, and tools, at the center of which is an interconnect-aware design methodology [1], enable the designers to design critical nets in complex metal systems of silicon technologies with great accuracy and the design first-pass success.

© 2006 by Taylor & Francis Group, LLC

Transmission Lines on Si

FIGURE 8.8.6

8.8-877

Test site versus lumped element model and EM solver: S-parameters, microstrip line interconnect.

As the second example, we simulated (using developed Spectre model) and compared two 50 V single-wire microstrip lines (see Figure 8.8.1) made of 4-mm thick aluminum (width of 12.5 mm and 9.25 mm distance from a finite width metal ground plane below) and a 1.25-mm thick aluminum (width of 5.9 mm and distance 4 mm from a finite width metal ground plane below). Both lines have the same length of 1000 mm. It can be clearly seen from Figure 8.8.7 that the thicker interconnect has the lowest losses (parameter S21). Figure 8.8.8 also shows extracted RLCZ parameters for the above lines. The simple equations from Ref. [20] have been used to perform RLCZ extraction procedure from the twoport S-parameter data. Again, thicker line has lower resistance and inductance. Its characteristic impedance is more close to the 50 V value across the whole frequency range of interest. Figure 8.8.9 and Figure 8.8.10 show the 77 GHz SiGe power amplifier (PA), which is described in Ref. [5]. That kind of amplifier has its potential use in the modern automotive radar systems. In this design single-wire microstrip lines are employed as matching interconnects. The implemented interconnect devices were carefully designed and accurately modeled to allow their successful application in such a high-speed design. The 60 GHz low-noise amplifier (LNA) from Ref. [4] is another example of the extensive use of microstrip transmission line interconnects. At 60 GHz in the SiO2 dielectric a quarter wave length is about 617 mm. Therefore, the shunt-stub microstrip transmission line interconnects were used successfully as the input, interstage, and output matching devices. Figure 8.8.11 and Figure 8.8.12 show the 60 GHz LNA schematic view and the LNA chip microphotograph. Finally, we mention here the work described in Ref. [21]. It presents an interesting application of a single-wire on-chip microstrip line. The developed parameterized microstrip line device was employed

© 2006 by Taylor & Francis Group, LLC

8.8-878

The Silicon Heterostructure Handbook

FIGURE 8.8.7 S-parameter comparison between two modeled microstrip lines.

to design the monolithic four-port 30 GHz branch line coupler. The availability of the accurate model and the well-defined transmission line structure enables for the designer to properly choose width and length of each arm so the branch line coupler device operates properly at the particular frequency of interest.

8.8.6 Summary Due to increasing signal frequencies, the transmission line effects of interconnects are more prominent in modern digital, RF, and mixed-signal ICs. Therefore, there is a strong need for transmission line device support in modern IC (both analog and digital) design flows. Transmission lines, if properly designed, are well-defined waveguide structures with an explicit current return path. This allows for their successful design, accurate predictive modeling, design, manufacturing, and measurements. In multi-GHz design regimes, on-chip interconnects have a substantial impact on the IC performance. The main issues are impedance matching, loss control, time delay, coupling to other circuit elements and to silicon substrate. Even around 1 GHz inductance starts to impact longer lines. Therefore, simple RC interconnect models are not accurate anymore and frequency-dependent inductance has to be included in the model. In order to account for transmission line effects during the design process, critical interconnects should be properly designed and accurately modeled over a wide frequency range. The designed interconnect structures and developed models should be able to account for frequency-dependent

© 2006 by Taylor & Francis Group, LLC

8.8-879

Transmission Lines on Si

Resistance - R(f ) 15

⫻ 10−10 4.4

w = 12.5 µm, th = 4 µm w = 5.9 µm, th = 1.25 µm

4.2

Inductance - L(f ) w = 12.5 µm, th = 4 µm w = 5.9 µm, th = 1.25 µm

4 10

3.8 3.6 3.4

5

3.2 3 0 0 10 ⫻ 10−13

101 Frequency (GHz)

100

Capacitance - C(f )

101 Frequency (GHz)

Characteristic Impedance - abs(Z(f )) 110

1.4

w = 12.5 µm, th = 4 µm w = 5.9 µm, th = 1.25 µm

100

1.3 1.2

90

1.1

80

1 70

0.9 w = 12.5 µm, th = 4 µm w = 5.9 µm, th = 1.25 µm

0.8 0.7 100

60 50 0 10

101 Frequency (GHz)

101 Frequency (GHz)

FIGURE 8.8.8 RLCZ parameter comparison between two modeled microstrip lines.

VCC = 2.5V

Quarter-wave RF-Choke

Out T2

In

T1

Bias2 Bias1

Input match

Inter-stage match

Microstrip transmission lines

Output match

FIGURE 8.8.9 The balanced 77 GHz power amplifier schematic diagram (half-circuit). (From UR Pfeiffer, SK Reynolds, and BA Floyd. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

8.8-880

The Silicon Heterostructure Handbook

Output matching

Balanced circuit

Bank of bypass caps

out− Supply-/Regulated-Voltages

out+

T2 T2 T1 T1

in−

in+ Inter-stage matching

Quarter-wave RF-choke T1 bias circuit Differential 100 Ohm

FIGURE 8.8.10 Chip microphotograph of the balanced 77 GHz power amplifier. (From UR Pfeiffer, SK Reynolds, and BA Floyd. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. With permission.)

Vcc R1

Cbyp

T7

T6

CUR

T4

R6

Q3 Cbyp T2

Q1

C3 OUT

Microstrip transmission lines (T1-T7)

T3

Q5

C2 Q2

IN

Q4

R2

T1

VB1 C1

R3

R4 T5

R5 Cbyp

FIGURE 8.8.11 The 60 GHz low-noise amplifier. (From SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004. With permission.)

skin and proximity effects and be passive by construction. As a result, simple lumped RLC interconnect models (which might include dependent current or voltage sources) are easily netlisted and used in Spice-like simulators for time- and frequency-domain simulations (including harmonic balance and periodic steady-state analysis). Interaction between an interconnect and the lossy silicon substrate below has to be also well understood and accounted for in the interconnect model (especially for coplanar waveguides). The typical transmission line examples are microstrip interconnects over a finite width ground plane below and coplanar waveguide devices over a silicon substrate. The microstrip line interconnects are effectively shielded from the silicon substrate. At the same time, coplanar waveguides are opened to the silicon substrate below. The substrate losses in coplanar waveguides are minimized by using the side shield lines at the same level as signal ones.

© 2006 by Taylor & Francis Group, LLC

8.8-881

Transmission Lines on Si

LNA OUT

IN

Microstrip transmission lines FIGURE 8.8.12 Chip microphotograph of the 60 GHz low-noise amplifier. (From SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004. With permission.)

For nondense IC designs (usually SiGe BiCMOS) microstrip lines are a good choice. At the same time, in CMOSRFCMOS designs these structures may have to be different due to higher design density. This is where most of coplanar waveguides find their applications. To summarize this chapter, we just mention here that we attempted to provide a short review of most popular transmission line topologies, which are employed in modern IC designs. We also covered their modeling issues and challenges. In addition to that, we presented a few interconnect application examples.

Acknowledgments The author would like to thank R. Gordin, D. Goren of IBM Haifa (Israel); S. Venkatadri, W. Woods, R. Singh of IBM Burlington (USA); U. Pfeiffer, B. Floyd, T. Zwick, S. Reynolds of IBM Yorktown (USA); R. Groves, K. Vaed of IBM Fishkill (USA); M. Toupikov of Amgen Inc. (USA), and G. Pan of Arizona State University (USA), for their contributions and valuable discussions. In addition, I thank my wife, Marie Sackett, my mother, Valentina Tretiakova, my mother-in-law, Hedy Sackett, my brother-in-law, Nick Sackett, and my grandparents-in-law, Esther and Bob Solla, for their devotion and support in all my endeavors.

References 1. D Goren, M Zelikson, R Gordin, IA Wagner, A Amir, B Livshitz, A Sherman, R Groves, K Park, YV Tretiakov, D Jordan, S Strang, R Singh, C Dickey, and D Harame. On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices. Technical Digest Design Automation Conference, Anaheim, 2003, pp. 724–727. 2. GG Freeman, B Jagannathan, N Zamder, R Singh, YV Tretiakov, JP Plouchart, DR Greenberg, S Koester, and JD Shaub. Integrated SiGe and Si device capabilities and trends for >10 GHz applications. International Journal of High Speed Electronics and Systems 13:175–219, 2003. 3. R Singh, YV Tretiakov, J Johnson, S Sweeney, RL Barry, M Kumar, M Erturk, J Katzenstein, C Dickey, and D Harame. Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes. IEEE Transactions on Electron Devices 50:700–717, 2003. 4. SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. 60 GHz transceiver circuits in SiGe bipolar technology. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004.

© 2006 by Taylor & Francis Group, LLC

8.8-882

The Silicon Heterostructure Handbook

5. UR Pfeiffer, SK Reynolds, and BA Floyd. A 77 GHz SiGe power amplifier for potential applications in automotive radar systems. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. 6. A Deutsch, PW Coteus, GV Kopcsay, HH Smith, CW Surovic, BL Krauter, DC Edelstein, and PJ Restle. On-chip wiring design challenges for gigahertz operation. Proceedings of the IEEE, 89:529– 555, 2001. 7. B Kleveland. CMOS Interconnects beyond 10 GHz. Ph.D. thesis, Stanford University, Stanford, CA, 2000. 8. W Woods, YV Tretiakov, K Vaed, D Ahlgren, J Rascoe, and R Singh. Vertically-stacked on-chip SiGe/ BiCMOS/RFCMOS coplanar waveguides. Technical Digest IEEE International Interconnect Technology Conference, San Francisco, 2004. 9. T Dhaene and D De Zutter. Selection of lumped element models for coupled lossy transmission line. IEEE Transactions on Computer-Aided Design 11:805–815, 1992. 10. D Goren, R Gordin, and M Zelikson. Modeling methodology for on-chip coplanar transmission lines over the lossy silicon substrate. Technical Digest IEEE Workshop on Signal Propagation in Interconnects, Hanover, 2003. 11. BK Sen and RL Wheeler. Skin effects models for transmission line structures using generic SPICE circuit simulators. Technical Digest IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 1998, pp. 128–131. 12. R Gordin, D Goren, and M Zelikson. Modeling of on-chip transmission lines in high-speed A&MS design — the low frequency inductance calculation. Technical Digest IEEE Workshop on Signal Propagation in Interconnects, Pisa, 2002. 13. TE Kolding, OK Jensen, and T Larsen. Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices. Technical Digest International Conference on Microelectronic Test Structures, Monterey, 2000, pp. 246–251. 14. T Zwick, YT Tretiakov, and D Goren. On-chip SiGe transmission line measurements and model verification up to 110 GHz. IEEE Microwave and Wireless Components Letters, 15: 65–67, 2005. 15. DC Laney. Modulation, Coding and RF Components for Ultra-Wideband Impulse Radio. Ph.D. thesis, University of California, San Diego, CA, 2003. 16. M Koolen, J Geelen, and M Versleijen. An improved de-embedding technique for on-wafer high frequency characterization. Technical Digest BCTM Symposium, 1991, pp. 188–191. 17. LF Tiemeijer and RJ Havens. A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors. IEEE Transactions on Electron Devices 50:823–829, 2003. 18. J Song, F Ling, G Flynn, W Blood, and E Demircan. A de-embedding technique for interconnects. Technical Digest Electrical Performance of Electronic Packaging Conference, 2001, pp. 129–132. 19. YV Tretiakov, J Rascoe, K Vaed, W Woods, S Venkatadri, and T Zwick. A new on-wafer deembedding technique for on-chip RF transmission line interconnect characterization. Technical Digest IEEE Automatic RF Techniques Group Conference, Fort Worth, 2004. 20. WR Eisenstadt and Y Eo. S-parameter-based IC interconnect transmission line characterization. IEEE Transactions on Components, Hybrids and Manufacturing Technology 15:483–490, 1992. 21. J Lee, YV Tretiakov, JD Cressler, and AJ Joseph. Monolithic 30 GHz branch line coupler design on Si/ SiGe with 3D simulations. Technical Digest Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 2004.

© 2006 by Taylor & Francis Group, LLC

8.9 Improved De-Embedding Techniques 8.9.1 8.9.2

On-Wafer Parasitics and De-Embedding Techniques.................................................................. 8.9-883 Improved De-Embedding Technique ...................... 8.9-885 Four-Port Parasitics Model and Theory . De-Embedding Process . Validity and Layout Concerns

Qingqing Liang Georgia Institute of Technology

8.9.3 8.9.4

Comparison ............................................................... 8.9-890 Noise De-Embedding Technique ............................. 8.9-893

8.9.1 On-Wafer Parasitics and De-Embedding Techniques Precise measurement is a prerequisite to accurate device modeling and characterization. For accurate evaluation of high-frequency characteristics and models, S-parameter measurements are a widely used approach. As the operating frequency in measurement increases into the microwave range, the on-wafer parasitics, including the pad-substrate capacitance and wire impedance, become significant. Figure 8.9.1 shows the three-dimensional cross-section view of the on-wafer parasitics and the intrinsic device. As the pad-substrate admittances or wire impedances are comparable to the admittance or impedance of the intrinsic device, respectively, the measured S-parameters on the pads (p1 and p2 in Figure 8.9.1) misrepresent the device ac characteristics. In addition, the layout device size is normally several hundred micrometers, then the distributive nature of parasitics (coupling between wires and substrate) becomes apparent at the millimeter-wave band.

Intrinsic device Wire impedance

Wire impedance

p2

p1

Pad-sub capacitance

Pad-sub capacitance Substrate network

FIGURE 8.9.1

Three-dimensional cross-section view of the on-wafer parasitics and the intrinsic device.

8.9-883 © 2006 by Taylor & Francis Group, LLC

8.9-884

The Silicon Heterostructure Handbook

G

G

INT

C2

P1 P1

P2

G

G

OPEN test structure

P2 C1

C3

OPEN

The parasitics model used in the "open" technique

FIGURE 8.9.2 The OPEN test structure and the equivalent circuit of parasitics model used in ‘‘open’’ technique.

The on-wafer parasitic effects increase as the operating frequency increases. Moreover, the parasitics correlate with the layout and device process (e.g., the properties of the substrate and insulator) and is hard to predict. Therefore, accurate microwave ac characterization requires de-embedding techniques that exclude the parasitic effects and retrieve the intrinsic device characteristics from the measured data. The standard ‘‘open’’ de-embedding method was first proposed in 1987 [1]. It employs a technique in which the pad-substrate and wire-substrate capacitance are accounted for and calibrated by using an OPEN test structure. The layout of OPEN test structure is same as the layout of deviceunder-test (DUT) except the transistor is removed. Figure 8.9.2 shows the OPEN test structure and the equivalent circuit of parasitics model. Note that in this model, the equivalent circuit of DUT can be viewed as the intrinsic device in parallel with the OPEN. Then the intrinsic device y-parameters YINT are derived as [1] Y INT ¼ Y DUT Y OPEN ,

(8:9:1)

where the YDUT and YOPEN are the measured y-parameters of the DUT and OPEN test structure, respectively. This approach assumes that the pad-substrate capacitances dominate the parasitics. The validity of this assumption depends on the process technology and layout. Usually, the approach is only accurate at a lower frequency range (i.e. f < 20 GHz). At high frequencies (i.e., f > 20 GHz), the wire impedance, especially the wire inductance, cannot be neglected. The industry standard ‘‘open-short’’ de-embedding method was then proposed to exclude the effects of the wires [2]. Beside the OPEN and DUT, a SHORT test structure is used to extract the parasitics in this method. The layout of SHORT test structure is similar as the layout of the OPEN except that the intrinsic ports are both connected to the intrinsic ground. Figure 8.9.3 shows the SHORT test structure and the equivalent circuit of parasitics model. Note that the distributive parasitics are modeled as lumped components in this method. The intrinsic y-parameters can be derived using the measured y-parameters of OPEN (Y OPEN), SHORT (Y SHORT), and DUT (Y DUT) [2] Y INT ¼

h 1 1 i1 Y DUT Y OPEN Y SHORT Y OPEN :

(8:9:2)

In millimeter-wave measurement, the parasitics becomes more distributive and the ‘‘open-short’’ method starts to lose accuracy. Some high-frequency de-embedding techniques, which use different lumped equivalent circuit to model the parasitics and different test structures for extraction, have been proposed [3, 4]. The frequency range of valid ac measurement is extended using these methods, but the accuracy of the parasitics model depends on the process technology.

© 2006 by Taylor & Francis Group, LLC

8.9-885

Improved De-Embedding Techniques

G

G

C2 L1

INT

L2

P1

C1

P2

P1

P2

OPEN

C3

SHORT

L3 G

G

SHORT test structure FIGURE 8.9.3 technique.

The parasitics model usedin the "open" technique

The SHORT test structure and the equivalent circuit of parasitics model used in ‘‘open-short’’

INT

OPEN

THRU1

THRU2

P2

P1

The parasitics model using cascade two-port networks FIGURE 8.9.4 An illustration of the parasitics model using cascade two-port networks.

Moreover, some methods that use cascade two-port networks instead of lumped equivalent circuit to model the parasitics are presented [5, 6]. Figure 8.9.4 shows the parasitics model used in these techniques. The two-port networks capture the distributive effects. However, the model neglects the crosstalk between the two ports, and hence is not fit for devices with lossy substrate. All the de-embedding techniques introduced above use simplified versions of parasitics model. These approaches become problematic when the neglected terms in parasitics models are not negligible. To generalize the problem and avoid the potential inaccuracy, a four-port system calibration methodology is developed [7–9]. In this chapter, we will focus on the improved four-port de-embedding technique and its application.

8.9.2 Improved De-Embedding Technique Four-Port Parasitics Model and Theory Figure 8.9.5 shows a DUT using a four-port network as parasitics model and a two-port network as the intrinsic device. The four ports include two extrinsic ports (1 and 2), which are the measured referenceplane, and two intrinsic ports (3 and 4), which represent the intrinsic device characteristics. Since only the I–V characteristics at the extrinsic ports and intrinsic ports are concerned, the four-port network is sufficient to model the parasitics effects. Furthermore, at small-signal level, the parasitics can be modeled as a linear four-port network, which is characterized by a 4 4 matrix. Then, the I–V relationships of the extrinsic and intrinsic ports can be written as a 4 4 y-matrix according to

© 2006 by Taylor & Francis Group, LLC

8.9-886

The Silicon Heterostructure Handbook

DUT Parasitics I1

I2 I3

I4 V3

V1

V4

INT

V2

Parasitics

FIGURE 8.9.5

An illustration of the parasitics model using four-port networks.

0

1 2 Y11 I1 ) B I2 ) C 6 Y21 B C¼6 @ I3 ) A 4 Y31 Y41 I4

Y12 Y22 Y32 Y42

Y13 Y23 Y33 Y43

30 1 V1 Y14 B V2 C Y24 7 7B C: Y34 5@ V3 A Y44 V4

(8:9:3)

In some circumstances, Yij can be 1 (i.e., there is a short between various ports). In this case, let Yij be very large to avoid any singularities. Let Ve and Ie be the extrinsic voltage and current vectors, and Vi and Ii be the intrinsic voltage and current vectors [7]

Ve Vi

0

1 V1 B V2 C C ¼B @ V3 A and V4

Ie Ii

0

1 I1 B I2 C C ¼B @ I3 A: I4

(8:9:4)

Then we have [10]

Ie Ii

¼

Yee Yie

Yei Yii

Ve , Vi

(8:9:5)

where [Yee], [Yei], [Yie], and [Yii] are four 2 2 matrices. The extrinsic y-parameters and the intrinsic device y-parameters can then be related as Y DUT Ve ¼ Yee Ve þ Yei Vi ,

(8:9:6)

Y INT Vi ¼ Yie Ve þ Yii Vi ,

(8:9:7)

where YINT are the intrinsic device y-parameters, and YDUT are the 2-port y-parameters of the DUT. Note that the current directions of the intrinsic device are opposite to the current directions of the parasitics. It follows from Equation (8.9.6) and Equation (8.9.7) that Y DUT ¼ Yee Yei (Y INT þ Yii )1 Yie

(8:9:8)

Y INT ¼ Yie (Y DUT Yee )1 Yei Yii :

(8:9:9)

or

© 2006 by Taylor & Francis Group, LLC

8.9-887

Improved De-Embedding Techniques

Once the 16 variables of the 4 4 matrix are known, one can build the appropriate one-to-one relationship between the extrinsic and intrinsic y-parameters. For each test structure, a 2 2 y-parameters can be obtained using the measured raw S-parameters. Given the intrinsic y-parameters of the test structure as well as the measured raw y-parameters, four equations are derived from one test structure. To solve for all 16 variables, one needs to measure at least four different test structures, unless approximations are made. For example, the ‘‘open-short’’ de-embedding method only uses two test structures. Apply this method in the four-port system, one gets Vi ¼ 0 for the short structure and Ii ¼ 0 for the open structure. Applying these two boundary conditions to Equation (8.9.5) yields Y SHORT ¼ Yee ,

(8:9:10)

Y OPEN ¼ Yee Yei (Yii )1 Yie :

(8:9:11)

Putting the above equations to Equation (8.9.8), after simplification, yields YX þ YB ¼ YX YB1 Yie YX1 Yei þ YX YB1 Yie YB1 Yei ,

(8:9:12)

YX ¼ Y DUT Y SHORT ,

(8:9:13)

YB ¼ Y SHORT Y OPEN :

(8:9:14)

Without loss of generality, YX can be any matrix, and thus the equalities above hold when Yie ¼ Yei ¼ Yii ¼ Y SHORT Y OPEN :

(8:9:15)

Equation (8.9.15) gives the condition (assumption) under which the ‘‘open-short’’ approach is valid. At high frequencies (e.g., f > 30 GHz), however, this assumption is clearly no longer valid because the distributed nature of the parasitics must be considered.

De-Embedding Process As discussed above, at least four test structures are required to solve all 16 elements. Therefore, besides the OPEN and SHORT, more test structures are designed to obtain more boundary conditions. The question is then to decide which test structures should be used. Observe in Equation (8.9.10) that Yee equals to the measured SHORT y-parameters: Y SHORT. To decouple the product term Yei(Y INT þ Yii)1 Yie in Equation (8.9.8) is the key to solve Yei, Yie, and Yii. Then, different test structures are chosen to obtain matrices in the form of 0 Y , a ie b 0 Y RO ¼ Yei Y , 0 0 ie c c Y TS ¼ Yei Y : c c ie Y LO ¼ Yei

0 0

(8:9:16) (8:9:17) (8:9:18)

where a, b, and c are constants. From Equation (8.9.16) to Equation (8.9.18), Yei, Yie can be calculated Yie ¼ k1 Yei0 ¼ k1

© 2006 by Taylor & Francis Group, LLC

1 m1

RO RO y12 =y11 LO LO , m1 y12 =y11

(8:9:19)

8.9-888

The Silicon Heterostructure Handbook

Yei ¼ kr Yie0 ¼ kr

1 RO RO y21 =y11

m2 LO LO : m2 y21 =y11

(8:9:20)

And Yii is Yii ¼ k1 kr Yie0 (Y SHORT Y OPEN )1 Yei0 ,

(8:9:21)

where m1 ¼

TS TS RO RO y12 =y11 y12 =y11 , LO LO TS TS y12 =y11 y12 =y11

(8:9:22)

m2 ¼

TS TS RO RO y21 =y11 y21 =y11 , LO LO TS TS y21 =y11 y21 =y11

(8:9:23)

and kl and kr are scale-factors and will be determined below. To obtain the matrices discussed above, five test structures are used. Figure 8.9.6 shows the layout of the DUT and the required test structures. The Ytest,int þ Yii for OPEN, LEFT, RIGHT, THROUGH test structures are

Yii, 11 Yii, 12 , Yopen,int þ Yii ¼ Yii, 21 Yii, 22 Yii,11 þ g l Yii,12 Yleft,int þ Yii ¼ , Yii,21 Yii,22

(8:9:24) (8:9:25)

G

G

G

G

G

G

P1

P2

P1

P2

P1

P2

G

G

G

G

G

G

OPEN

DUT

SHORT

G

G

G

G

G

G

P1

P2

P1

P2

P1

P2

G

G

G

G

G

G

THROUGH FIGURE 8.9.6

LEFT

RIGHT

The layout of the DUT and the required test structures used in the four-port technique.

© 2006 by Taylor & Francis Group, LLC

8.9-889

Improved De-Embedding Techniques

Yright,int þ Yii ¼ Ythrough,int þ Yii ¼

Yii,11 Yii,21

Yii,11 þ A Yii,21 A

Yii,12 , Yii,22 þ gr Yii,12 A , A ! 1, Yii,22 þ A

(8:9:26) (8:9:27)

where g1 ¼ 1/R1 and gr ¼ 1/Rr are conductances of the resistors in the LEFT and RIGHT structures, respectively. Using simple mathematics, one can prove that [9]

0 Y , a ie 0 Y , 0 ie c Y , c ie

0 xY (1 x)Y ¼ Yei Y 0 b Y RIGHT yY OPEN (1 y)Y SHORT ¼ Yei 0 c Y THRU zY OPEN (1 z)Y SHORT ¼ Yei c LEFT

OPEN

SHORT

(8:9:28) (8:9:29) (8:9:30)

where x, y, and z are the solutions of LEFT Y xY OPEN (1 x)Y SHORT ¼ 0,

(8:9:31)

RIGHT Y yY OPEN (1 y)Y SHORT ¼ 0,

(8:9:32)

THRU Y zY OPEN (1 z)Y SHORT ¼ 0,

(8:9:33)

and x 6¼ 1, y 6¼ 1, and z 6¼ 1. 0 0 0 Therefore, the normalized Yei , Yie , and Yii are derived. Take them into Equation (8.9.9), one gets 0

0

0

Y INT ¼ kr kl Yie (Y DUT Yee )1 Yei Yii :

(8:9:34)

The next step is to solve the scale factors kr and kl. Substituting Y DUT using Y LEFT yields Y

left,int

0

¼ kr kl (Yie (Y

0

DUT

0

1

0

0

Yee ) Yei Yii ) ¼ kr kl Y

LINT

g ¼ l 0

0 , 0

(8:9:35)

0

DUT where Y LINT ¼ Yie (Yp Yee)1 Yei Yii . Thus kr kl ¼ gl/Y11LINT. Furthermore, if the parasitics are ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ LINT . passive, then kr ¼ kl ¼ gl =Y11 As a summary, the improved four-port de-embedding process includes:

1. Measure the S-parameters of the DUT, OPEN, SHORT, THROUGH, LEFT, and RIGHT, and convert the S-parameters into y-parameters. 2. Solve for x, y, and z in Equation (8.9.28) to Equation (8.9.30), and choose the solution that x 6¼ 1, y 6¼ 1, and z 6¼ 1. 3. Calculate Y LO, Y RC, and Y TS using Equation (8.9.16) to Equation (8.9.18). 0 0 0 4. Obtain normalized [Yei ], [Yie ], and [Yii ] by using Equation (8.9.19) to Equation (8.9.21). 5. Calculate the scale factor k ¼ krkl using Equation (8.9.35). 6. Calculate the intrinsic y-parameters using Equation (8.9.9).

© 2006 by Taylor & Francis Group, LLC

8.9-890

The Silicon Heterostructure Handbook

Validity and Layout Concerns In this method, it has been assumed that Equation (8.9.24) to Equation (8.9.27) and Yee þ Yei (Yshort,int þ Yii)1 Yie Yee hold, indicating that the intrinsic ac characteristics of test-structures should be ideal. It is necessary to check the validity of the de-embedding methodology using nonideal test structures. In ideality, one solution of x, y, and z should be 1, and the intrinsic RIGHT should be open at port 1 and a resistor at port 2. These equations are used for validity verification. In the current technology for RFIC applications, the intrinsic device layout size is smaller than a few tens of microns although the DUT size (including pads, etc.) is several hundreds of microns, and thus the assumptions made in this method are valid in the millimeter-wave band with optimized layout design. In higher frequency measurements (i.e., f > 300 GHz), if one can accurately model the nonideal intrinsic S-parameters of the test structures, the four-port methodology is feasible with a few modifications in the extraction equations.

8.9.3 Comparison Both HP-ADS simulation and ac measurement in SiGe HBTs are performed here to fully verify and compare the accuracy of the improved four-port de-embedding methodology with other techniques (e.g., ‘‘open-short’’). In simulation, several equivalent circuits were chosen to determine how a given parasitic model impacts the four-port technique and ‘‘open-short’’ technique. Figure 8.9.7 shows three equivalent circuits of the parasitics. The parasitics model (from 1 to 3) becomes more distributive using more capacitors and inductors. The component values in each circuit were extracted and optimized from the

Model 1

Port 1

Port 3

Model 2

Port 4

Port 2 Port 1

Port 3

Model 3

1

FIGURE 8.9.7

3

4

2

Three equivalent circuits of the parasitics used in the simulation.

© 2006 by Taylor & Francis Group, LLC

Port 4

Port 2

5

10

5

0 0.0

20.0

40.0 60.0 80.0 Frequency(GHz)

0 100.0

0.0

0.0

–0.5

–0.5

–1.0

HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

–1.5 0.0

–10 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

0.0

20.0

40.0 60.0 80.0 Frequency (GHz)

–20

–30 100.0

Real(Y22) (mS)

30

Imag(Y21) (mS)

Real(Y21) (mS)

0

10

40.0 60.0 80.0 Frequency (GHz)

8

40

20

20.0

6 4

–1.0

–1.5 100.0

5 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

4 3 2

2 0 0.0

Imag(Y22) (mS)

10

Real(Y12) (mS)

15 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

Imag(Y11) (mS)

Real(Y11) (mS)

15

Imag(Y12) (mS)

8.9-891

Improved De-Embedding Techniques

1

20.0

40.0 60.0 80.0 Frequency (GHz)

0 100.0

FIGURE 8.9.8 The extracted de-embedded y-parameters using both the ‘‘open-short’’ and the new four-port method on each parasitic model.

measured S-parameters of parasitics. A device model carefully calibrated to measured data was used to simulate the S-parameters of the SiGe HBTs, both with and without the parasitics. The simulated frequency range was 1 to 100 GHz. Figure 8.9.8 shows the de-embedded y-parameters after applying both the ‘‘open-short’’ and the four-port method on each parasitic model. For equivalent circuit model 1, the intrinsic y-parameters are accurately de-embedded using both the four-port and ‘‘open-short’’ method. For equivalent circuit models 2 and 3, however, observe that the ‘‘open-short’’ method produces large deviations from the intrinsic y-parameters at frequencies above about 30 GHz. This clearly demonstrates the potential inaccuracy of the traditional ‘‘open-short’’ method at high frequencies. Observe as well that the accuracy of the new four-port method is not dependent on the choice of the equivalent circuit or the frequency. Both de-embedding techniques applied on actual 2 to 110 GHz S-parameter measurement data of state-of-the-art SiGe HBTs are also compared. The measured device is a 0.2 2.5 mm2 highperformance npn SiGe HBT with a peak fT of 110 GHz at JC ¼ 7.0 mA/mm2. Figure 8.9.9 shows the extracted fT and fmax as a function of current density. Figure 8.9.10 shows the raw DUT S-parameters and extracted S-parameters using the ‘‘open-short’’ and the four-port method. For a better comparison, we have plotted S21/6 and S11 0.75 instead of S21 and S11. Observe that there are large deviations between the un-deembedded and de-embedded data, indicating that the on-wafer parasitics are significant in this SiGe technology. Note that the deembedded S-parameters using the two methods are in close agreement, except in the high-frequency range, implying the validity of both two methods at low frequencies. To more closely examine the differences between the two methods, we plot the de-embedded Y21 as a function of frequency (as shown in Figure 8.9.11). The deviation of the results is negligible at frequencies lower than about 30 GHz. At frequency higher than 30 GHz, the ‘‘open-short’’ method overestimates the

© 2006 by Taylor & Francis Group, LLC

8.9-892

The Silicon Heterostructure Handbook

120

f T, fMAX (GHz)

100 80 60

SiGe HBT 0.2×2.5µm2 VCB = 1 V fT fMAX

40 20 0 0.1

1.0 JC (mA/µm2)

10.0

30.0

FIGURE 8.9.9 The extracted fT and fmax as a function of current density JC of the measured SiGe HBT. VBE = 0.9 V, VCB = 1 V DUT open–short four–port S21/6

S12

S11–0.75

FIGURE 8.9.10 method.

S22

The raw DUT S-parameters and extracted S-parameters using the ‘‘open-short’’ and the four-port

0⬚

200

–45⬚ 100

–135⬚

Angle (Y21)

Abs(Y21) (mS)

–90⬚

–180⬚

VBE = 0.9 V, VCB = 1 V open–short four–port

–225⬚ –270⬚

10 10.0

100.0

Frequency (GHz)

FIGURE 8.9.11

The extracted y21 as a function of frequency using the ‘‘open-short’’ and the four-port method.

© 2006 by Taylor & Francis Group, LLC

8.9-893

Improved De-Embedding Techniques

magnitude and underestimates the phase of Y21. This is caused by the distributive nature of the wire lines between the pads and the intrinsic device. As expected, the error increases as the frequency increases. These errors can severely distort the measured characteristics of the device (e.g., the gain) at high frequencies. Figure 8.9.12 shows the current gain H21 as a function of frequency at different bias points. Although the current gain extracted using the two methods nearly overlap at lower frequencies (the ‘‘open-short’’ de-embedded gain is slightly less than the ‘‘four-port’’ gain), at frequencies above 70 GHz, the current gain extracted with the ‘‘open-short’’ method ceases to decrease, which is clearly not the physical (real) behavior of the intrinsic device. Observe, however, that the current gain with the fourport method continues decreasing with a constant slope of about 20 dB per decade, indicating the accuracy of this technique.

8.9.4 Noise De-Embedding Technique The four-port technique can also be applied to noise de-deembedding. A generalized noise system can be characterized by a noise current correlation matrix SY or noise voltage correlation matrix SV. Figure 8.9.13 shows the equivalent circuit of the noise current model for an n-port system [11, 12]. The correlation matrix can be written as 2 6 SY ¼ 4

in,1 in*,1

in,1 in*,n

.. .

in,n in*,1

.. .

in,n in*,n

3 7 5,

(8:9:36)

40 VBE = 0.9 V 30 H21 (dB)

20dB/decade 20

VBE = 0.8 V

10 0

VCB = 1 V VBE = 0.8, 0.82, 0.84, 0.9 V open–short four–port

–10 1.0

10.0 Frequency (GHz)

100.0

FIGURE 8.9.12 The current gain H21 as a function of frequency at different bias points.

1

2

1

2 iN,2

iN,1 Noisy N-port System N-1

Noiseless N-port System N

N-1

N

iN,N-1 N+1

iN,N N+1

FIGURE 8.9.13 The equivalent circuit of the noise current model for an n-port system. (F Bonani, G Ghione, MR Pinto, and RK Smith. An efficient approach to noise analysis through multidimensional physics-based models. IEEE Trans. Electron Dev. 45:261–269, 1998.)

© 2006 by Taylor & Francis Group, LLC

8.9-894

The Silicon Heterostructure Handbook

DUT Noiseless parasitics

INT iN,e1

iN,i1

iN,i2

iN,int1

FIGURE 8.9.14 device.

iN,e2

iN,int2

The equivalent circuit of noise model of the four-port parasitics network and two-port intrinsic

where in,j , j ¼ 1,2,3, . . . is the noise current source at port j. In a two-port system, the minimum noise figure Fmin, noise impedance Rn, and the optimum noise admittance Yopt can be directly converted into the noise current correlation matrix SY2 [11]. Once the 4 4 Y-matrix is obtained, the noise de-embedding method is thus straightforward [13]. Figure 8.9.14 shows the equivalent circuit of noise model of the four-port parasitics network and two-port intrinsic device. The noise current correlation matrix SY4 of the parasitics can be written as 2

SYn,11 6 SYn,21 6 SY4 ¼ 4 SYn,31 SYn,41

SYn,12 SYn,22 SYn,32 SYn,42

3

SYn,13 SYn,23 SYn,33 SYn,43

2

in,1 in*,1

SYn,14 6 * 6 SYn,24 7 7 ¼ 6 in,2 in,1 SYn,34 5 6 4 in,3 in*,1 SYn,44 in,4 in*,1

in,1 in*,2

in,1 in*,3

in,2 in*,2

in,2 in*,3

in,3 in*,2

in,3 in*,3

in,4 in*,2

in,4 in*,3

in,1 in*,4

3

7 in,2 in*,4 7 7¼~ in ~ in* , in,3 in*,4 7 5 in,4 in*,4

where SYn,ij, i, j ¼ 1,2,3,4 are the noise current correlation between port i and port j. For brevity, in and SY4 are also written as 0

1 in,1 B in,2 C ~ C ¼ in,e in ¼ B @ in,3 A in,i in,4

(8:9:37)

and SY4 ¼

SYn,ee SYn,ie

SYn,ei SYn,ii

Yee ¼ 4kT Real Yie

Yei Yii

,

(8:9:38)

where in,e and in,i are extrinsic and intrinsic noise current sources, respectively. The four-port I–V relation of the DUT, considering noise currents, can then be written as

Ie þ in,e Ii þ in,i þ in,int

¼

Yee Yie

Yei Yii

Ve : Vi

One can thus calculate the intrinsic noise correlation matrix as [9]

© 2006 by Taylor & Francis Group, LLC

(8:9:39)

Improved De-Embedding Techniques

SYn,int ¼ (YT )1 (SYn,total SYn,ee )(YT* )1 SYn,ii þ (YT )1 SYn,ei þ SYn,ie (YT* )1 ,

8.9-895

(8:9:40)

where YT ¼ Yei (Y INT þ Yii)1.

Acknowledgments We would like to thank D. Greenberg, J.-S. Rieh, A. Joseph, D. Herman, B. Meyerson, and the IBM SiGe team for their support and contributions. This work was supported by IBM, the Semiconductor Research Corporation, and the Georgia Electronic Design Center at Georgia Tech.

References 1. PJ van Wijnen, HR Claessen, and EA Wolsheimer. A new straightforward calibration and correction procedure for ‘‘on wafer’’ high-frequency s-parameter measurements (45 MHz–18 GHz). Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 1987, pp. 70–73. 2. MCAM Koolen, JAM Geelen, and MPJG Versleijen. An improved de-embedding technique for on-wafer high-frequency characterization. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 1991, pp. 188–191. 3. H Cho and DE Burk. A three-step method for the de-embedding of high-frequency s-parameter measurements. IEEE Trans. Electron Dev. 38:1371–1375, 1991. 4. EP Vandamme, DMMP Schreurs, and CV Dinther. Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures. IEEE Trans. Electron Dev. 48:737–742, 2001. 5. J Grzyb, D Cottet, and G Tro¨ster. Systematic deembeding of the transmission line parameters on high-density substrates with probe-tip calibrations. Technical Digest of the IEEE Electronic Components and Technology Conference, 2002, pp. 1051–1057. 6. CH Chen and MJ Deen. A general noise and s-parameter deembedding procedure for on-wafer high-frequency noise measurements of MOSFETs. IEEE Trans. Micro. Theory Tech. 49:1004–1005, 2001. 7. RA Pucel, W Struble, R Hallgren, and UL Rohde. A general noise de-embedding procedure for packaged two-port linear active devices. IEEE Trans. Micro. Theory Tech. 40:2013–2024, 1992. 8. S Bousnina, C Falt, P Mandeville, AB Kouki, and FM Ghannouchi. An accurate on-wafer deembedding technique with application to HBT devices characterization. IEEE Trans. Micro. Theory Tech. 50:420–424, 2002. 9. Q Liang, JD Cressler, G Niu, Y Lu, G Freeman, DC Ahlgren, RM Malladi, K Newton, and DL Harame. A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs. IEEE Trans. Micro. Theory Tech. 51:2165– 2174, 2003. 10. V Rizzoli, F Mastri, and C Cecchetti. Computer-aided noise analysis of MESFET and HEMT mixers. IEEE Trans. Micro. Theory Tech. 37:1401–1410, 1989. 11. H Hillbrand and PH Russer. An efficient method for computer-aided noise analysis of linear amplifier networks. IEEE Trans. Circ. Syst. CAS-23:235–238, 1976. 12. F Bonani, G Ghione, MR Pinto, and RK Smith. An efficient approach to noise analysis through multidimensional physics-based models. IEEE Trans. Electron Dev. 45:261–269, 1998. 13. S Lee, V Tilak, KJ Webb, and LF Eastman. Intrinsic noise characteristics of AlGaN/GaN HEMTs. Technical Digest of the IEEE MTT-S International Microwave Symposium, 2002, pp. 1415–1418.

© 2006 by Taylor & Francis Group, LLC

9 Circuits and Applications 9.1

Overview: Circuits and Applications J.D. Cressler ................................................ 9.1-899

9.2

SiGe as an Enabler for Wireless Communications Systems L.E. Larson and D.Y.C. Lie .......................................................................................... 9.2-901 Introduction . Architectural Design Considerations for Wireless Receivers and Transmitters . SiGe HBT Transistor Performance for Wireless Transceivers . SiGe HBT-Based RF Circuit Considerations . Examples of SiGe HBT-Based RF Wireless Transceivers . Summary

9.3

LNA Optimization Strategies Q. Liang ................................................................... 9.3-923 Introduction . RF LNA Design Concerns . SiGe Cascode LNA Design Example . Summary

9.4

Linearization Techniques L.C.N. de Vreede and M.P. van der Heijden............................................................... 9.4-937 Introduction . Nonlinear Distortion Concepts . Circuit Interaction of Device Nonlinearities . RF Design Techniques for Linearity

9.5

SiGe MMICs H. Schumacher..................................................................................... 9.5-979 Introduction . The Substrate Issue . SiGe MMICS Using Heterojunction Bipolar Transistors . SiGe MMICS Using Heterostructure Field-Effect Transistors . Summary

9.6

SiGe Millimeter-Wave ICs J.F. Luy .......................................................................... 9.6-997 Introduction . Silicon as a Substrate . Millimeter-Wave Generation . Amplifier . Mixer . MMICS with SiGe Diodes . Summary

9.7

Wireless Building Blocks Using SiGe HBTs J.R. Long ........................................ 9.7-1007 Introduction . Monolithic Components for RFIC Design . RF Amplifiers . RF Mixers . Voltage-Controlled Oscillators

9.8

Direct Conversion Architectures for SiGe Radios S. Chakraborty and J. Laskar..................................................................................... 9.8-1049 Overview of Direct Conversion Architectures . Direct Conversion System Aspects and IC Abstraction . Choice of Differential Architecture . Transmitter and Receiver Considerations . Impacts of System Performance . SiGe Direct Conversion Radio: A Practical Example .

9.1-897 © 2006 by Taylor & Francis Group, LLC

9.1-898

The Silicon Heterostructure Handbook

The Integration: Interfaces and Layout . Characterization of Receiver Front End . Fabricated Hardware and Results . Compensation and Corrections . Future of Direct Conversion Radios 9.9

RF MEMS Techniques in Si/SiGe J. Papapolymerou .......................................... 9.9-1075 Introduction . RF MEMS Switches . Application circuits

9.10

Wideband Antennas on Silicon M.M. Tentzeris and R.L. Li........................... 9.10-1099 Microstrip Antennas on Cavity-etched Silicon Substrate . Microstrip Antennas on Hole-perforated Silicon Substrate . Tapered Slot Antennas on Micromachined Silicon Substrates . Surface Micromachined Monopoles for W-Band Applications

9.11

Packaging Issues for SiGe Circuits K. Lim, S. Pinel, and J. Laskar .............................................................................. 9.11-1119 Background . IC Package Evolutions . Recent Package Technology Trend . Future Direction . Package Design Consideration . Summary

9.12

Industry Examples of State-of-the-Art: IBM — High-Speed Circuits for Data Communications Applications D.J. Friedman and M. Meghelli ............................................................................ 9.12-1127 Introduction . Transmitter and Receiver Chip Set at 43 Gb/sec . Summary

9.13

Industry Examples at the State-of-the-Art: Hitachi K. Washio................................................................................................................ 9.13-1145 Introduction . IC and LSI for Optical Transmission Systems . IC for Wireless Communication Systems . Summary

9.14

Industry Examples at the State-of-the-Art: ST D. Belot ................................................................................................................... 9.14-1155 Introduction . Process Definition . Switched Gain LNA Implementation . Down Mixers and PMA Implementation . Variable Gain Amplifier (VGA) and Low-Pass Filter (LPF) . LNA-Mixer Isolation Strategy . Receiver Implementation . Validation Strategy . RF and Analog Blocks Validation . RF and Analog Receiver Validation . WCDMA Receiver Global Test . Summary

© 2006 by Taylor & Francis Group, LLC

9.1 Overview: Circuits and Applications

John D. Cressler Georgia Institute of Technology

One of the unique merits of this book lies in its extreme breadth. What begins with materials, must not end with devices, but rather must also span the circuit and system application space. This is particularly so in our field because its success is intimately tied to the uncanny ability of Si-based devices to be integrated, enabling the construction of large systems from many diverse components in a very small space at low cost. This final section provides coverage of this application space; the real world, if you will. In Chapter 9.2, ‘‘SiGe as an Enabler of Wireless Communications Systems,’’ L. Larson of the University of California at San Diego gives a broad view of the merits of SiGe for emerging wireless communications systems. In Chapter 9.3, ‘‘LNA Optimization Strategies,’’ by Q. Liang of Georgia Tech, new techniques for improved LNA design are addressed, and Chapter 9.4, ‘‘Linearization Techniques,’’ by L. de Vreede of the Delft University of Technology, presents a comprehensive view of linearization techniques in devices and circuits. The next three chapters span the RF to millimeter-wave IC space, beginning with Chapter 9.5, ‘‘SiGe MMICs,’’ by H. Schumacher of the University of Ulm, and then moving up in frequency in Chapter 9.6, ‘‘SiGe Millimeter-Wave ICs,’’ by J. Luy of DaimlerChrysler, and then down in frequency in Chapter 9.7, ‘‘Wireless Building Blocks Using SiGe HBTs,’’ by J. Long of the Delft University of Technology. New wireless radio architectures are covered in Chapter 9.8, ‘‘Direct Conversion Architectures for SiGe Radios,’’ by S. Chakraborty of Georgia Tech. MEMS processing represents an important emerging area in silicon fabrication and applications, and is addressed in Chapter 9.9, ‘‘RF MEMS Techniques in Si–SiGe,’’ by J. Papapolymerou of Georgia Tech. Future system integration approaches necessarily require robust packaging techniques and even on-board antennae for signal transmission, as addressed in Chapter 9.10, ‘‘Wideband Antennas on Si,’’ by M. Tentzeris of Georgia Tech and Chapter 9.11, ‘‘Packaging Issues for SiGe Circuits,’’ by K. Lim of Georgia Tech. Finally, in the last three chapters, we take a snapshot of the state-of-the-art in the IC application space. While by definition this view holds only for 2005, a blink of the eye in this dynamic field, it nonetheless provides a nice glimpse of the future, as envisioned by several industry leaders: Chapter 9.12, ‘‘Industry Examples at the State-of-the-Art: IBM,’’ by D. Friedman of IBM Research; Chapter 9.13, ‘‘Industry Examples at the State-of-the-Art: Hitachi,’’ by K. Washio of Hitachi, and Chapter 9.14, ‘‘Industry Examples at the Stateof-the-Art: ST Microelectronics,’’ by D. Belot of ST Microlectronics.

9.1-899 © 2006 by Taylor & Francis Group, LLC

9.2 SiGe as an Enabler for Wireless Communications Systems* 9.2.1 9.2.2 9.2.3 9.2.4

Introduction............................................................... 9.2-901 Architectural Design Considerations for Wireless Receivers and Transmitters........................ 9.2-903 SiGe HBT Transistor Performance for Wireless Transceivers................................................. 9.2-908 SiGe HBT-Based RF Circuit Considerations .......... 9.2-912 Si–SiGe HBT Low-Noise Amplifier Fundamentals . Si–SiGe HBT Voltage-Controlled Oscillators and Frequency Synthesizers

Lawrence E. Larson University of California at San Diego

Donald Y.C. Lie

9.2.5

Dynamic Research Corporation and University of California at San Diego

9.2.6

Examples of SiGe HBT-Based RF Wireless Transceivers ................................................................ 9.2-915 Summary .................................................................... 9.2-919

9.2.1 Introduction The desire to communicate quickly and reliably with our family, friends, and colleagues is one of the most widespread of human needs, and wireless telephony has exploded in the last decade as a ubiquitous tool to fulfill that desire. Over 400 million cellular handsets were sold in the years 2002 and 2003, and the market is expected to grow to nearly a billion phones per year within the next decade. At the same time, the market for the now-ubiquitous wireless local area network 802.11a/b/g is expected to exceed 100 million per year. The cellular telephone and wireless LAN card have become so common and widespread, such an integral part of modern existence, that it is easy to forget that they were considered to be expensive novelties just 15 years ago. This revolution in communications has resulted from the confluence of a variety of technological factors: advances in communications theory, networking architectures, semiconductor technology, and transceiver design. The wireless ‘‘revolution’’ would not have happened without the advances in each of these areas, and no one technology can plausibly lay claim to be the dominant technology driving us forward. However, the combination of stunning advances in semiconductor technology, e.g., Moore’s law, combined with improved approaches to transceiver design, has enabled the size, cost, and battery life of the wireless transceiver to be shrunk to that of a typical consumer item, within plausible reach of *Portions of this chapter first appeared in the IEEE Transactions on Electron Devices and International Journal on Wireless and Optical Communications.

9.2-901 © 2006 by Taylor & Francis Group, LLC

9.2-902

The Silicon Heterostructure Handbook

half the population on the planet. It is our contention that SiGe BiCMOS technology is an ideal candidate for implementation of these advanced wireless devices of the future. The communications medium that a wireless transceiver typically finds itself in is often referred to as ‘‘hostile,’’ since the path — or channel — from the transmitter to the receiver is subject to time-varying obstructions and multipath fading, as well as Doppler effects. This is in contrast to ‘‘point-to-point’’ communications links — either wireless, fiber-optic or free-space optical — where the channel is essentially nontime-varying or ‘‘stationary.’’ This hostile channel affects both the design of the transmitter and receiver in profound ways, and the next section will summarize some of the key challenges associated with the wireless transceiver, as well as some of the new approaches that are developed to produce fully monolithic versions of wireless transceivers. A related challenge for next generation wireless devices is the necessity to deliver multiband as well as multistandard functionality in the future. A typical functional block diagram of the electronics of a cellular telephone that might accomplish this is shown in Figure 9.2.1, where a next generation European handset might support GSM (at 900 MHz) for voice applications, as well as W-CDMA (at 2000 MHz) for data applications, Bluetooth (at 2.4 GHz) for piconet applications, GPS (at 1.5 GHz) for position location, and 802.11 (at 2.4 GHz) for wireless local area network functionality. Of course this seems impractical today, but it is expected to be well within the reach of semiconductor and system technology within the next few years. In a manner similar to what Moore’s law has achieved for digital integrated circuits, we expect that RF microwave circuits will benefit from the same lithographic scaling advances, and the entire industry can significantly reduce the costs and the form factors of communication products by achieving a higher level of RF system integration on a single integrated circuit. However, the RF portion of a typical highperformance wireless communication system remains a mixture of devices made with different technologies. For example, III–V compound (GaAs or InP-based) low-noise amplifiers (LNAs), switches, or power amplifiers (PAs) are often used in cellular telephones or wireless LAN products today, along with

Radio transceiver

Baseband processor

UMTS/ W-CDMA

UMTS/ W-CDMA

GSM 900/ 1800

GSM 900/ 1800

To man−machine interface Bluetooth/ 802/11

Bluetooth/ 802/11

GPS

GPS

Single-chip

Single-chip

FIGURE 9.2.1 Multimode and multiband cellular handset architecture. These features will be common in future handset designs.

© 2006 by Taylor & Francis Group, LLC

9.2-903

SiGe as an Enabler for Wireless Communications Systems

lower-cost silicon components for other functions, preventing the high integration levels and ultralow cost of a ‘‘single-chip radio.’’ This is due in large part to the differing performance between III–V-based and Si-based transistors, where the superior electron transport and breakdown characteristics provide the III–V-based devices with superior performance. While GaAs FETs, PHEMTs, and heterojunction bipolar transistors (HBTs) can be inexpensive and highly efficient at gigahertz frequencies and cellular handset power levels, they offer a limited ability to integrate with CMOS baseband chips. Although CMOS technology has achieved impressive levels of RF integration lately — especially for cost-sensitive applications like Bluetooth — its performance lags behind that of III–V-based devices and circuits. As a result, Si–SiGe heterostructures — and specifically Si–SiGe HBTs — are under extensive investigation, since they can provide nearly III–V levels of performance with the low cost of a Sibased technology [1]. HBTs that utilize Si–SiGe heterolayers extended the high-frequency limit of Si-based bipolar technology to cutoff frequencies f T well above 200 GHz, a frequency range that has been historically dominated by GaAs-based devices [2, 3]. In addition, fabrication processes for Si–SiGe devices are compatible with those routinely used for CMOS ICs, enabling the manufacture of Si–SiGe BiCMOS technology. When combined with the state-of-the-art digital CMOS devices, the SiGe BiCMOS technology offers a unique suite of devices to enable dramatic improvements in RF–analog–mixed-signal IC integration. This technology truly has become an ‘‘enabler’’ for single-chip implementation of highperformance wireless communications systems.

9.2.2 Architectural Design Considerations for Wireless Receivers and Transmitters The standard receiver architecture for wireless systems — the venerable heterodyne — is shown in Figure 9.2.2. Since its initial development by Edwin Armstrong in the 1910s, the heterodyne architecture has remained the preferred approach for the implementation of the vast majority of radio-frequency applications in the world. Its perennial popularity is due to its ability to reproducibly pick out

Dynamic range? VGA

LNA

Duplexer

BPF

BPF

SAW filter

SAW filter

cos w LO2t

I LPF

From power amplifier

Channel select sin w LOt

To A/D demodulator

cos w LOt LPF Channel select

FIGURE 9.2.2

Typical heterodyne receiver used in cellular handsets.

© 2006 by Taylor & Francis Group, LLC

Q To A/D demodulator

9.2-904

The Silicon Heterostructure Handbook

narrow-bandwidth high-frequency signals from the surrounding background clutter of signals outside the frequency range of interest. One way to view these constraints of background clutter is through the ‘‘football field’’ metaphor, first proposed by Paul C. Davis of Bell Laboratories [4]. The popular European GSM system has a minimum received signal sensitivity level (the smallest level of the desired received signal) at the output of the antenna of 102 dB m (1013.2 W), but the largest interferer also received by the antenna has a level of 0 dB m (103 W). If you imagine the desired signal power to be normalized to the head of a pin, roughly 1 mm in diameter, then the largest interferer is roughly the size of two football fields 100 m 100 m. Receiving a GSM signal is analogous to the problem finding the head of a pin in a football field without being able to actually going onto the field to look for it. In addition, this has to be accomplished in less than 100 msec, which is typically the time it takes for the cellular handset to receive a call. Viewed through this lens, the modern cellular handset is truly a technological marvel. The heterodyne receiver accomplishes this through a combination of filtering and careful frequency planning. In the heterodyne receiver, the radio signal is sent from the receiving antenna to an LNA, whose purpose is to boost the signal level without reducing the signal-to-noise ratio significantly. The signal level at the antenna can range between 1 mV rms and nearly 100 mV rms — over a 100-dB variation. At the low end of the signal range, the LNA performance is fundamentally limited by thermodynamic issues, while at the high end of the signal range, the challenge is to minimize the effects of nonlinearities on receiver performance. These diverse requirements are often referred to as the ‘‘LNA Bottleneck’’ [5]. As a result, the high-frequency LNA must exhibit excellent performance over both small-signal and large-signal conditions. Following the LNA, the signal is typically passed through a mixer, which essentially multiplies the input signal by a local oscillator signal of constant frequency, producing an output signal whose frequency is the difference between the two inputs — the so-called intermediate frequency (IF) — and whose amplitude is proportional to the original input signal. Preceding the mixer, an analog filter eliminates the response to an undesired input signal at (2flo – frf ) that would also downconvert to the intermediate frequency. This image-reject filter is typically implemented with a physically large surface acoustic wave (SAW) filter. In addition to their size, these filters have extremely unforgiving sensitivities to variations in source impedance, ground loops, etc. The dilemma of image rejection and its elimination in heterodyne receivers is one of the fundamental limitations on performance and power reduction in radio-frequency systems. A highly integrated transceiver will allow for these filters to be dispensed with, significantly reducing power dissipation and physical size in the transceiver. A second limitation of traditional frequency translating mixers and the heterodyne architecture is their sensitivity to a menagerie of spurious responses that result from nonlinearities in the amplifiers preceding the mixer, as well as the mixer itself. These nonlinearities produce harmonics of the input and local oscillator frequencies that can themselves mix down to the intermediate frequency. The potential range of frequencies where this unfortunate set of circumstances can occur is nearly limitless, so very high linearity in the mixer is required. The architecture of the heterodyne also has a number of problems, which make it very poorly suited for completely monolithic integration — the key to lower power operation. The major problems are the ubiquitous image and spurious responses, which must be carefully controlled through bulky and expensive off-chip filters. These filters represent the major impediment to raising the level of integration of wireless radios, since they cannot be easily implemented monolithically. Therefore, alternative architectures that do not suffer from these limitations are actively explored. Substantial progress has been made recently in the area of direct downconversion — or homodyne — approaches for wireless receivers, which also eliminate the need for image rejection filters, and are better suited to monolithic integration. A schematic diagram of a typical direct conversion receiver is shown in Figure 9.2.3. An excellent review of recent research in this field is presented in Refs. [6, 7]. In this case, the IF is at dc, and the in-phase and quadrature (I and Q) paths of the mixer contain the positive and negative frequency components of the desired signal. The advantages of this particular architecture are

© 2006 by Taylor & Francis Group, LLC

9.2-905

SiGe as an Enabler for Wireless Communications Systems

I LPF sin w LOt

Channel select

To demodulator

LNA

cos w LOt Q LPF Channel select

To demodulator

FIGURE 9.2.3 The direct downconversion — or homodyne — receiver. The absence of the image response makes this approach particularly attractive for monolithic integration.

that it is uniquely well suited to monolithic integration, due to its lack of complex filtering, and its intrinsically simple architecture. However, although it is actively researched, the direct conversion receiver has not gained completely widespread acceptance to date, especially in high-performance wireless receivers, due to its intrinsic sensitivity to dc offset problems, even-order harmonics of the input signal that interfere with the desired signal, and local-oscillator leakage problems back to the antenna. These issues are all actively pursued by a variety of worldwide research groups, and it is anticipated that they will gradually become solved with further design maturity. The LO feedthrough problem has been addressed through the use of subharmonic mixer approaches — a technique borrowed from millimeter-wave radio astronomy — where the mixer is driven at half the desired frequency [8]. This reduces the problem of LO feedthrough and frequency ‘‘pulling’’ of the local oscillator at the expense of a higher local oscillator drive power. The limitations of the direct conversion approach can once again be seen by examining a specific example — in this case in the GSM environment. In this case, the signal level at the antenna at the minimum sensitivity level is roughly 1 mV rms. The maximum gain from the antenna to the lowfrequency output of the mixer is at most 20 dB, due to dynamic range considerations. So, the remaining low-frequency gain in the system, from the output of the mixer to the input of the A–D converters, must be in the order of 80 dB (10,000). This presents two problems. First, any small offset voltage in the subsequent amplifiers will saturate the remaining stages; an input offset voltage of 1 mV will be amplified to 10 V. Second, the input referred noise voltage of the amplifier itself must be in the order of 5 nV/Hz1/2 or less. This is a challenging goal for a low-current baseband amplifier. The residual dc offset problem is the largest concern in most practical systems, and it is typically addressed through a variety of background calibration algorithms. Despite these inherent problems, the homodyne architecture has become very common in GSM handsets recently. For example, recent GSM phones — such as the Ericsson A1018 and T28 — have employed the direct conversion approach very successfully, and the Ericsson R520m triband GSM/GPRS phone employs the homodyne approach in a multimode multiband architecture [9]. Transmitter architectures are also the focus of intense international development. The main role of the transmitter section is to convert the digitally generated baseband signals — typically in-phase (I) and quadrature (Q) — to amplitude and phase modulated RF signals superimposed on a fixed carrier frequency. The classic approach for this process is known as the indirect upconversion approach, which is shown in Figure 9.2.4. A fixed intermediate frequency (or IF) is modulated with the I/Q baseband signal. The resulting signal is filtered and then further upconverted with a second mixer to the desired frequency. In CDMA-oriented systems — such as IS95 or W-CDMA — the power level coming out of

© 2006 by Taylor & Francis Group, LLC

9.2-906

The Silicon Heterostructure Handbook

LNA

Duplexer

LPF

PA Σ

BPF VGA

VGA RF local oscillator

sin w LOt IF cos w LOt

I-channel

Reconstruction filter

LPF

Q-channel

Reconstruction filter

FIGURE 9.2.4 Indirect upconversion transmitter architecture. This is the most common approach for transmitters requiring both amplitude and phase modulation of the carrier.

the antenna must be strictly controlled over a very wide range (roughly 80 dB) to prevent the ‘‘near–far’’ problem common to direct sequence spread spectrum multiuser systems. The indirect approach has several advantages, which have made it popular for a practical system. The variation in gain can be at both the IF and final RF, so the gain can be distributed throughout the upconversion chain without concern for isolation issues. The IF is at a relatively low frequency, so the first I/Q modulator can be made very accurate, which improves the performance of the modulator and reduces the dc current consumption. Also, since the first IF is at a fixed frequency, a filter with a sharp rolloff frequency can be used to eliminate any spurious noise resulting from the DAC output driving the I/Q modulator. Despite its intrinsic advantages, there are several disadvantages with the indirect upconversion approach. These include the need for two frequency synthesizers to generate the necessary frequencies, and the fact that the final upconversion mixer generates an output at two frequencies (LO þ IF and LO IF). Since only one of these two frequencies is desired, the mixer has to dissipate extra dc power to accommodate the extra (unwanted) signal. Finally, harmonics of the LO and IF frequencies (nLO + mIF) can multiply (or intermodulate) together to create a spurious in-band signal. This problem can be minimized through a careful choice of the IF and LO frequencies. The direct upconversion approach is an alternative to the indirect approach and is shown in Figure 9.2.5. Its simplicity is reminiscent of the homodyne receiver approach — the I/Q baseband signal is directly upconverted to the RF. The main advantage here is the elimination of the second synthesizer, and the attendant spurious responses this and the first upconversion mixer create. However, now there are two high-power mixers operating at the high upconversion frequency (instead of one) and the accuracy of the I/Q modulator at the higher frequency is greatly diminished. Furthermore, the local oscillator frequency and the transmit frequency are now one and the same, so the output of the PA can alter — or ‘‘pull’’ — the local oscillator with the same I/Q modulation as the transmitted signal. This problem can be eliminated by utilizing a subharmonic mixer, as discussed previously, or using a local oscillator at twice the desired frequency, and then dividing the resulting LO frequency by two on-chip. This eliminates the frequency pulling problem, although several other problems remain with the approach. One remaining problem with the direct upconversion approach is that the 80-dB output power variation must now be achieved by varying the gain either at the high RF frequency or at low frequencies in the separate I/Q paths. At microwave frequencies, on-chip isolation is typically 40 to 60 dB at best, so achieving a full 80-dB change in gain entirely at high frequency becomes very difficult. At the same time, it is difficult to vary the gain of the circuit at baseband, since any I/Q gain mismatch at lower frequencies

© 2006 by Taylor & Francis Group, LLC

9.2-907

SiGe as an Enabler for Wireless Communications Systems

LNA

Duplexer

LPF

PA

sin w LOt Σ VGA

I-channel

Reconstruction filter

IF cos w LOt LPF

Q-channel

Reconstruction filter

FIGURE 9.2.5 Direct upconversion architecture. In this case, the baseband signal is directly converted to RF.

translates directly into errors in the transmitted signal, and the effects of local oscillator feedthrough on output power become more pronounced at the low gain levels. The problems of direct upconversion systems remain a challenge, and they are the subject of much active worldwide research. This discussion of transmitter and receiver architectures naturally leads us to considerations of the interactions between the transmitter and receiver of a typical wireless handset. These issues will become increasingly important in the future, as multimode and multiband handsets become more prevalent. As an example, a multimode 2G/3G GSM/W-CDMA handset will have to contend with differing frequencies, bandwidths, modulation formats, and access methods. Note that there are several possibilities for compromised performance with this proposed system and frequency plan. As an example, consider the case where the GSM portion of the receiver is ‘‘on,’’ listening to a signal at 959.9 MHz, the W-CDMA receiver is ‘‘off,’’ and the GSM receiver uses the direct conversion approach discussed previously. Furthermore, there is a nearby W-CDMA handset transmitting at 1922.5 MHz. In this case, the unlucky GSM receiver would ‘‘receive’’ the nearby transmitted W-CDMA signal, the mixer would mix it with the second harmonic of the GSM local oscillator (at 1919.8 MHz), and downconvert the resulting spurious signal to 3 MHz, partially corrupting the desired signal that is also in the same frequency range. Although this chain of events seems implausible at first glance, the very small level of the desired signal (less than 100 dB m) and the large value of the potential interferer (up to 0 dB m) make this scenario an unfortunate reality. Considerations of co-interference of different frequency plans must be carefully considered as we move into a more complex environment in the future. The reference frequencies required for upconversion and downconversion of the transmitted and received signals are generated by a frequency synthesizer, which uses a precise reference (usually produced by crystal oscillator) to synthesize the necessary local oscillator frequencies. In this case, the phase noise of the synthesized signal must be as low as possible to accurately modulate and demodulate the signal. Furthermore, the synthesizer itself is a complex RF–analog–digital circuit, which generates copious amounts of digital switching noise and harmonics. Historically, the synthesizer circuit was contained on a separate integrated circuit but, with system-on-chip implementations, this noise must be isolated from the sensitive receiver circuits despite the fact that they share a common substrate and package environment. This presents a fundamental challenge to the integration level of these complex circuits. The digital portion of the communication system performs the key functions of modulation and demodulation (the so-called ‘‘modem’’), carrier recovery, timing recovery, symbol recovery, equalization, channel coding, power detection, and calibration, among others. Separate digital controllers also perform media access control (MAC) functions as well as a variety of other control functions.

© 2006 by Taylor & Francis Group, LLC

9.2-908

The Silicon Heterostructure Handbook

The eventual goal is to include all these digital functions on the same integrated circuit substrate as the RF and analog circuits in order to realize a true ‘‘single-chip’’ communications system implementation.

9.2.3 SiGe HBT Transistor Performance for Wireless Transceivers The key active device parameters for enhanced circuit performance of noise and linearity for most RF applications are the short-circuit unity current gain frequency (f T) and the maximum unity power gain frequency (fMAX). These two parameters have made astonishing progress in recent years in SiGe HBT technology, with recently reported values in excess of 200 GHz [10]. The next most important issue is breakdown voltage which, together with noise considerations, sets the dynamic range limitation of most circuits. If we examine the Si–SiGe HBT first, using the physical cross section and equivalent circuit model of the device shown in Figure 9.2.6, the f T is given by 1 kT ¼ tB þ tC þ (Cje þ Ccb ) þ (Rex þ Rc )Ccb 2pfT q

(9:2:1)

where Rex and Rc are the parasitic emitter and collector resistances, Ccb is the collector–base junction capacitance, Cje is the emitter–base junction capacitance, tB is the base transit time, and tC is the collector transit time.

FIGURE 9.2.6 Si–SiGe HBT. (a) Cross section of device. (b) Equivalent circuit model of transistor.

© 2006 by Taylor & Francis Group, LLC

SiGe as an Enabler for Wireless Communications Systems

9.2-909

In most high-frequency applications, the base and collector transit times dominate the f T, and the other parasitic-related terms have a secondary effect. For this same physical structure and equivalent circuit model, the fMAX of the transistor is given by [11]

f MAX

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ fT 8pt cb

(9:2:2)

where tCB is approximately RbCcb but can be more accurately described as a weighted average of the distributed base resistance and base-collector capacitance. These expressions highlight the critical role of vertical scaling to improve the f T and fMAX for bipolar device performance. At the same time lateral scaling of the devices is equally critical, to further reduce extrinsic base resistance and collector–base capacitance. Most scaling efforts with HBT structures aim to keep the fMAX equal to or slightly larger than the f T. The dependence of transistor f T and fMAX on base width can be seen clearly from the plots of measured devices in Figure 9.2.7, where the clear dependence of transit time on base width has a significant effect on f T [12]. The effect of base width on fMAX is less pronounced, due to the additional necessity to keep base resistance equally low. The other absolutely key issue for RF applications of scaled transistors is the breakdown voltage of the device, which influences the dynamic range of operation. The breakdown voltage of a transistor is mostly an issue for the implementation of PAs in the transmitter section, although other circuit areas can benefit from a high breakdown voltage as well. The breakdown voltage issue is detemined by the physics of the device at high electric fields, the varied physical mechanisms that lead to device failure, and the interaction of the breakdown mechanisms with the external circuit. The bipolar device is fundamentally limited by avalanche multiplication in the collector–base region. This breakdown effect is traded-off against the increasing f T of the transistor, and the BVf T product is the key consideration for most high-frequency applications and is a material-related constant known as the Johnson limit [14]. In the bipolar device, the collector–base junction typically experiences avalanche breakdown first, and the device can be characterized by the collector–emitter breakdown voltage when the emitter is open-circuited (BVCBO) or when the base is open-circuited (BVCEO). The former is usually larger than the latter, due to current gain in the emitter–base region, and can be approximated by BVCEO

BVCBO b1=n

(9:2:3)

where b is the dc current gain of the transistor and n is a constant that varies from 2 to 5, depending on a variety of physical factors. When the devices have very shallow doping (as in the high f T case), the transistors exhibit nonlocal avalanche, and the BV f T of the device can exceed its value seen for lower frequency devices [15]. Figure 9.2.8 plots the BVCEO and BVCBO for modern bipolar devices, and the effects of nonlocal avalanching on breakdown voltage can clearly be seen at the higher f T values, where the breakdown voltage does not change significantly as the f T increases. In the operation of a PA circuit, the device can typically operate at peak voltages in excess of BVCEO, but less than BVCBO, due to the time-dependent nature of the carrier multiplication process [16] and the impedances presented at each terminal. This last issue of terminal impedances is crucial in the operation bipolar devices for PAs, since the current gain at the emitter–base junction influences the breakdown characteristics. The collector–base avalanche current can be modeled by m 0 iC iAV ¼ Cav vCB

where Cav is a technology-dependent avalanche breakdown constant.

© 2006 by Taylor & Francis Group, LLC

(9:2:4)

9.2-910

The Silicon Heterostructure Handbook

Transit frequency f T (GHz)

300

100

50

10

5

10

50

100

Base thickness w B (nm)

(a)

Power gain frequency f MAX (GHz)

300

100

NA

=1

⫻1

0 20

cm −3

50 NA

10

5

10

(b)

=5

⫻1

0 19

50

cm −3

100

Base thickness w B (nm)

FIGURE 9.2.7 Si–SiGe HBT speed as a function of base width. (From U. Konig, A. Gruhle, and A. Schuppen. SiGe devices and circuits: where are the advantages over III–V. Proc. 1995 IEEE GaAs IC Symposium, pp. 14–18. With Permission). (a) The fT demonstrates a clear base width dependence, and (b) the device fMAX is also affected by the base resistance but the improvement with decreasing base thickness is much less pronounced. (From L. Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip’’. IEEE Trans. Electron Dev. 50(3), 2003, 683–699. With Permission.)

The transistor exhibits breakdown when @iC0 =@vCE ! 1 which can be rewritten as

© 2006 by Taylor & Francis Group, LLC

(9:2:5)

9.2-911

SiGe as an Enabler for Wireless Communications Systems

25

Breakdown voltage (V)

20

15 BVCBO 10

BVCEO

5 VDS(Rel) 0

20

30

40

50

60 f T (GHz)

70

80

90

100

FIGURE 9.2.8 Comparison of voltage limitations of MOSFETS and HBTs as a function of fT . (From L. Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip’’. IEEE Trans. Electron Dev. 50(3), 2003, 683–699. With Permission.) The VDS(Rel) of the MOSFET is the recommended operating voltage to minimize long-term degradation of the transistor. The Si–SiGe HBT BVCEO and BVCBO maintain a roughly 1:3 relationship from 20 to 90 GHz.

@iC0 @iC0 @vB @iAV ¼ @vCE @vB @iAV @vCE b(1 þ gm re ) @iAV gm ¼ rb gm 1 þ gm re @vCE gm0 rin

@iAV @vCB

(9:2:6a) (9:2:6b) (9:2:6c)

where gm0 is the effective transconductance of the device (including the feedback effects of any extrinsic emitter impedance) and rin is the input impedance consisting of the parallel combination of the extrinsic source impedance (including the base resistance Rb) and the input impedance. In the limiting case of a low-source impedance, rin is simply the transistor base resistance Rb. Then Equation (9.2.6a) to Equation (9.2.6c) result in BVCBO ¼

1 Cav gm0 r b

1=m (9:2:7)

which illustrates the dependence of breakdown voltage on base resistance; as the base resistance increases, the internal feedback shunts more and more of the avalanche current to the emitter, increasing the positive feedback that leads to breakdown. In the limit of a high source impedance (BVCEO), rin increases to approximately b/gm and BVCEO BVCBO

gm0 r b b

1=m (9:2:8)

which illustrates the well-known relationship between BVCBO and BVCEO in the bipolar transistor. The dependence of bipolar breakdown voltage on source impedance can be exploited in PA design to significantly increase the safe operating voltage range.

© 2006 by Taylor & Francis Group, LLC

9.2-912

The Silicon Heterostructure Handbook

9.2.4 SiGe HBT-Based RF Circuit Considerations Si–SiGe HBT Low-Noise Amplifier Fundamentals The front-end LNA is one of the key determiners of the performance of a complete receiver, since the overall signal-to-noise ratio of the final received signal is set by the noise performance of this particular amplifier. Typical wireless application frequencies today are in the 1 to 5 GHz range. Fortunately, the microwave noise performance of SiGe HBTs bipolar has improved dramatically in recent years, thanks to aggressive technology scaling that was largely designed to improve digital circuit performance. The input referred noise performance of a radio receiver determines the minimum signal level that can be reliably demodulated. As a result, it is a key factor in determining the range and power dissipation of the entire communications system. The noise factor (F), defined as the degradation of the signal-tonoise ratio of an input signal as it passes through the amplifier, is the standard metric for determining the noise performance of a radio-frequency receiver and is given by F¼

total noise power delivered to the load impedance total noise power delivered to the load impedance due only to the source

(9:2:9)

and the noise figure (NF) is defined as F in decibels [i.e., NF ¼ 10 log 10(F)]. Given this noise model of the bipolar transistor, the transistor will exhibit the following minimum noise factor as a function of source impedance [17] Fmin

Rb gm f 2 (Rb þ Rs )2 gm f 2 (Rb þ Rs )2 þ Xs2 ¼1þ þ þ Rs 2 fT2 Rs 2b fT2 Rs

(9:2:10)

So, the keys to lowering the noise figure of the bipolar device are the reduction in Rb or an increase in the f T. In this respect, the bipolar device has achieved ‘‘near-ideal’’ performance at sub-5 GHz frequencies recently, as state of the art the f T of the devices exceeds 100 GHz. Circuit linearity affects the performance of the receiver as well. An RF receiver is typically operated well below its 1-dB compression point, and therefore small-signal linearity is the key performance metric. As an example, in the GSM receiver case, the circuit must be able to amplify a signal of roughly 1013 W while simultaneously receiving an undesired signal many orders of magnitude larger. The key figures-of-merit here are the input intercept point and cross-modulation sensitivity. Transmitters are typically operated at high levels of output power, and so their large-signal linearity is the key consideration. From the perspective of receiver design, which encompasses the low-noise amplification stages as well as the downconversion mixer, circuit nonlinearity arises from weak nonlinearities both in the dependent sources (principally the transconductance) and charge storage elements (capacitors) within the transistor; at low frequencies, the former consideration dominates. The standard small-signal linearity figure-of-merit for a receiver amplifier is the third-order inputreferred intercept point (IIP3). This is defined as the input power level of two input signals (at frequencies f1 and f2), where the extrapolated undesired third-order output nonlinear response intersects the desired first-order linear response. Although this figure-of-merit has many limitations in practical situations, its ease of measurement and calculation make it a perennial favorite among microwave engineers. The second-order input-referred intercept point (IIP2) — the input power level where the extrapolated second-order response intersects the desired first-order response — is also sometimes specified, although it is usually less important than the IIP3. The nonlinearities introduce frequency dependence to the nonlinearity, which considerably complicates the analysis. The situation can be simplified if we consider resistive terminations only at each terminal of the transistor. In this case, the work of Vaidyanathan et al. [18] employing a Volterraseries analysis clarifies the relationship between the high-frequency linearity of the bipolar transistor

© 2006 by Taylor & Francis Group, LLC

SiGe as an Enabler for Wireless Communications Systems

9.2-913

and its physical design, particularly the relationship between the high-frequency linearity and the behavior of its ‘‘loaded’’ unity current-gain frequency f T, where the loaded unity current-gain frequency is defined as the frequency where the current-gain drops to unity with the appropriate terminating impedances. As an example, at sufficiently high frequencies, and without avalanche breakdown occurring, the OIP2 of a bipolar transistor is given by the relatively simple relationship [18] 4f T OIP2(2f ) 0 fT

(9:2:11)

where f T0 is the derivative of the loaded f T with respect to collector current. To minimize the secondorder intermodulation distortion, the transistor should be designed to have as constant an f T as possible, and the device will have the highest OIP2 near the peak of the f T versus iC curve. The important OIP3 behavior is more complicated than in the OIP2 case, but some important generalizations can be derived from the analysis of device operation. At sufficiently high frequencies, and when the device is operated at the peak of the iCf T curve, the OIP3 of the bipolar transistor can be approximated by [18] 1=2 8f T OIP3(2f2 f1 )f 0 ¼0 00 T fT

(9:2:12)

where f 00T is the second derivative of the loaded f T with respect to collector current. These results imply that, when the device is operated at the peak of its f T versus collector current curve, the best distortion performance is obtained when the device has a high f T and when the f T curve is as ‘‘flat’’ as possible. Both the OIP2 and OIP3 results mentioned above demonstrate that the ‘‘ideal’’ bipolar transistor is defined as one with very low junction capacitances; and hence, nearly constant f T will have outstanding highfrequency linearity, and that this intrinsic linearity can improve with future device scaling.

Si–SiGe HBT Voltage-Controlled Oscillators and Frequency Synthesizers The voltage-controlled oscillator (VCO) provides the frequency reference for the upconversion of the transmitted signal or downconversion of the received signal. The VCO frequency is usually not accurate enough by itself to provide the correct downconversion or upconversion frequency, and so it is usually phase-locked to a more precise reference frequency. The key performance issues with this circuit are phase noise, power dissipation, and frequency tuning range. Unlike many other circuits, the performance of the passive devices can have a significant impact on the performance of this circuit. The phase noise of the oscillator is the ratio of the power in the desired output (the carrier) to the output power in a 1 Hz bandwidth at a given frequency offset from the carrier, when the amplitude variation on the carrier has been removed through a limiting process. So, the phase noise is expressed in units of dB c/Hz at a specified offset frequency. Ideally, the spectrum of the VCO output is a deltafunction in the frequency domain, so the ideal VCO phase noise would be infinite dBc/Hz at all offset frequencies. Phase noise contributes to a variety of deleterious effects in radio systems, including a rise in the receiver noise floor and reciprocal mixing. A simplified schematic of a bipolar transistor monolithic differential LC-tuned VCO, along with its most significant noise sources is shown in Figure 9.2.9. The cross-coupled differential transistor pair presents a negative impedance to the resonator, canceling the resistive losses in the resonator and enabling sustained oscillation. Frequency variation is achieved with a reverse-biased pn-junction diode or accumulation-mode MOS varactor, which changes the resonant frequency of the circuit. The close-in phase noise behavior at an offset fm from the carrier frequency f0 in the differential LC-tuned VCO is determined from the well-known Leeson’s [19] model to be

© 2006 by Taylor & Francis Group, LLC

9.2-914

The Silicon Heterostructure Handbook

VCC

C1

L1

Req

C1

L1 Req

4kT/Req

4kT/Req 4kTRB

qIEE

Q1

Q2

qIEE

qIEE/B

SI T

IEE

FIGURE 9.2.9 Simplified schematic of a monolithic SiGe HBT transistor LC-tuned VCO with noise sources.

L(fm ) ¼

2 2kTReq F f0 A20 2Qfm

(9:2:13)

where k is Boltzman’s constant, T is the absolute temperature, A0 is the amplitude of oscillation, Q is the resonator-loaded quality factor, and F is the excess noise factor. Leeson’s model shows that phase noise is reduced as the amplitude of oscillation is increased. However, once the amplitude of oscillation drives the transistors in the cross-coupled differential pair into saturation, the loaded quality factor of the resonator is lowered and phase noise degrades significantly. It also illustrates the tradeoff between the power dissipation and phase noise, since a large amplitude will lead to both lowered phase noise and higher power dissipation. Leeson’s equation clearly shows the importance of maximizing the quality factor of the resonating circuit. The excess noise factor F is determined by the wideband noise from the cross-coupled differential transistor pair and the dc current noise source, taking the nonlinear operation of the oscillator into account. In the case of a bipolar VCO, the excess noise factor F can be approximated to be [20] F 1þ

Rbb 2Req

qIT Req DV 2 SI Req fT DV þ þ T 1 þ sinc2 2A0 f0 2kT pA0 8kT

(9:2:14)

where DV is the signal level required to make the cross-coupled differential transistor pair switch completely to one side, Req is the parallel equivalent impedance of the resonator, IT is the dc current, and SIT is the mean square current noise power spectral density. This illustrates the importance of minimizing base resistance for low-phase noise operation as well as the slight penalty incurred through the use of a high f T device. Low-frequency noise from the dc current source results in amplitude modulation of the carrier, and therefore little phase noise contribution from this source. However, dc current source noise at frequencies near the even harmonics of the oscillator creates both amplitude and phase noise.

© 2006 by Taylor & Francis Group, LLC

9.2-915

SiGe as an Enabler for Wireless Communications Systems

Due to the absence of a high-quality on-chip varactor diode, the fully integrated VCOs that employ on-chip LC tanks typically suffer from limited tuning range, which need to cover the practical (approximately +10%) lot-to-lot variation in capacitance values. If the tuning range of integrated VCOs can be made significantly larger than 20%, it would be ideal to have one single VCO covering the multiple frequency bands required by several different wireless standards (e.g., W-CDMA/GSM/PCS) and for both the transmit and receive modes. Such a large bandwidth requirement makes the fully integrated VCO design more challenging to meet the low-phase noise and low variation on VCO gain (i.e., KVCO) requirements for wireless applications. For example, a 3.4 to 4.6 GHz fully monolithic SiGe VCO designed for the GSM/DCS/PCS applications was recently reported [21]. The VCO provides a tuning range of 33% and with a very good phase noise of 138 dBc/Hz at 3 MHz offset at 3.4 GHz. After a divide-by-4, the VCO phase noise performance at 900 MHz is approximately 147 dBc/Hz at 3 MHz offset, which meets the challenging GSM TX VCO spec of 143 dBc/Hz at 3 MHz offset with a margin. The large tuning range and low-phase noise are achieved by using a combination of coarse tuning via digital selection of MOS capacitors and analog fine-tuning using P–N junction varactors. The chip is fabricated in a 50/65-GHz f T/fmax SiGe 0.25 mm BiCMOS production process [22]. Figure 9.2.10 and Figure 9.2.11 show the schematic and the die photograph of this fully monolithic VCO, respectively.

9.2.5 Examples of SiGe HBT-Based RF Wireless Transceivers SiGe HBT technology has become so ubiquitous recently, that a complete listing of all the wireless transceivers implemented in the technology would complete an entire book. Here, we will just focus on some of the 2.5G/3G cellular implementations of SiGe transceivers. In the 3G UMTS/W-CDMA system, the signal bandwidth is adjustable, so the direct-conversion receiver architecture is particularly suitable for W-CDMA implementation where the bandwidth of the receiver is determined by the cutoff

Vcc L1

L2 Out2

Out1

C1 C2 Q1 Bias

Q2 LB1

LB2

R_bias

R1

Bit 1

R2

Bit 2

R3

Bit 3

R4

Bit 4

R5

Vtune

C5

C3

FIGURE 9.2.10 Schematic for a fully monolithic multiband VCO with 33% tuning range. (From D.Y.C. Lie, X. Yuan, L.E. Larson, T. Robinson, A. Senior, X. Wang, J. Mecke, and M. Case. Phase noise analysis of fully-integrated digitally-tuned wideband Si/SiGe BiCMOS VCOs. Proc. IEEE Bipolar/BICMOS Circuits and Technology Meeting (BCTM), 2002, Monterey, CA, pp. 65–68. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.2-916

The Silicon Heterostructure Handbook

FIGURE 9.2.11 Die photograph of the fully monolithic VCO shown in Figure 9.2.10. (From D.Y.C. Lie, X. Yuan, L.E. Larson, T. Robinson, A. Senior, X. Wang, J. Mecke, and M. Case. Phase noise analysis of fully-integrated digitally-tuned wideband Si/SiGe BiCMOS VCOs. Proc. IEEE Bipolar/BICMOS Circuits and Technology Meeting (BCTM), 2002, Monterey, CA, pp. 65–68. With permission.)

frequency of the low-pass filters in the baseband. There have been several recent reports that demonstrated the feasibility of W-CDMA direct-conversion receivers in SiGe [23–26]. Besides the issue of dc offsets and AM-detection, it is challenging to meet the overall receiver sensitivity, selectivity, and dynamic range, as the overall NF needs to be 9 dB (including the 3.5 to 4 dB loss from the RF system switch and the diplexer) and the IIP3 needs to be high enough to pass the intermodulation/blocker tests while consuming the lowest dc power possible. The strong signal leakage from the transmitter through the duplexer can also interact with the LO signals leaked from the mixers to generate dc offsets. Lie et al. [27] have recently reported a W-CDMA direct-conversion front-end receiver chip consisting of an LNA, a dual-gain RF variable-gain amplifier (RF-VGA), two direct-down-conversion mixers, an I/Q quadrature generator, and a base-band five-gain-stage VGA that was designed and manufactured in a 0.25-mm SiGe BiCMOS production process. A very low LO-induced dc offset value of less than 300 mV (uncalibrated) was measured at the output of the mixers, as the LO signal was fed into the chip at twice the RF frequency. The measured cascaded noise figure for the chip (including the SAW filter) was 4.3 dB at the maximum gain mode, and the IIP2 and IIP3 were þ37 and 16.5 dBm, respectively. The reported

© 2006 by Taylor & Francis Group, LLC

9.2-917

SiGe as an Enabler for Wireless Communications Systems

SAW filter

I

RF in

LPF

LNA

BB-VGA

RF-VGA

2⫻LO

% by 2/ quadrature generator

Q LPF

BB-VGA

FIGURE 9.2.12 Block diagram of W-CDMA SiGe direct-conversion front-end receiver chip. (From D.Y.C. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, T. Beukema, L.E. Larson, A. Senior, C. Saint, J. Blonski, N. Swanberg, P. Pawlowski, D. Gonya, X. Yuan, and H. Zamat. A direct-conversion W-CDMA front-end SiGe receiver chip. Proc. IEEE Radio Frequency Integrated Circuits Conference (RFIC), 2002, pp. 31–35. With permission.)

LO leakage and the dc offset values are among the best in the literature for W-CDMA direct-conversion receiver chips, with an uncalibrated I/Q amplitude/phase mismatch of less than 0.1 dB and 1.58, respectively. The overall chip performance meets all the essential parameters and BER requirements of W-CDMA front-end receiver specs. Figure 9.2.12 shows the block diagram of the W-CDMA SiGe directconversion front-end receiver chip as an example of direct-receiver architecture [27]. A BER ¼ 0.1% is reached at a signal level of approximately 122.9 dBm at the LNA input, which meets the 3GPP receiver sensitivity spec of 117 dBm at antenna or approximately 121 dBm at LNA input at the worst-case (assuming a 4-dB loss from the system switch and TX SAW filter loss). A transmitter creates a modulated carrier at the desired output frequency by upconversion and power amplification. Many of today’s CDMA and TDMA mobile phones use the two-step transmitter approach because this architecture has proven to be less problematic, but it requires the addition of high-quality filters at both the RF and IF stages. The IF filter is required to attenuate the wideband noise floor and the higher harmonics of the IF generated by the quadrature (I/Q) modulator. The RF filter is required to attenuate the unwanted sidebands and spurs generated from the upconverting mixing process. Another issue with a two-step transmitter is that two LO signals must be generated, which may require a second phase-locked loop (PLL). The primary advantage of a two-step transmitter is that narrowband filtering and gain control can be implemented efficiently at the IF stage, which improves the dynamic range of the transmitter. This architecture also benefits from the local oscillators operating at different frequencies from the transmit frequency, which avoids the injection pulling caused by the PA. Figure 9.2.13 shows an example of a highly linear W-CDMA SiGe W-CDMA two-step transmitter IC with high dynamic range and on-chip transformers [28]. It meets or exceeds all necessary specifications for 3GPP compliance transmitter IC for UE Output Power Class-3. This TX IC consists of a wideband I/Q modulator, a narrowband IFVGA, a variable-gain mixer, an RFVGA, a differential class A/B driver, a LO driver, and on-chip low-pass and band-pass filters. The transmitter achieves carrier suppression >35 dBc; side-band suppression >40 dB; and RMS error-vector-magnitude (EVM) <3% at 3 dBm output power. The measured adjacent-channel-leakage ratio (ACLR) is less than 49 dBc (i.e., at +5 MHz offset: 49 dBc/3.84 MHz; at +10 MHz offset: 59 dBc/3.84 MHz). The TX IC maximum output power is 7 dBm and with overall 100 dB dynamic range (i.e., +13 dB margin compared with

© 2006 by Taylor & Francis Group, LLC

9.2-918

The Silicon Heterostructure Handbook

HPA SAW

RF driver

LC-filter

LC-filter

Matching

Matching

RFVGA

External and internal LC Network Elements provide sufficient out of band rejection

IQ modulator

UP mixer

2

IFVGA 2

DIV 4

X2 2

RX RFLO PS

RFVCNTL

IFLO PS

IFVCNTL PS

Low-side injection 1540-1600 MHz

High-side injection

760 MHz

FIGURE 9.2.13 Block diagram of W-CDMA SiGe heterodyne transmitter chip. (From D. Malhi, L. Larson, D. Wang, C. Demirdag, and V. Pereira. SiGe W-CDMA transmitter for mobile terminal application. IEEE J. Solid-State Circ. 38(9), 2003, 1570–1574. With permission.)

FIGURE 9.2.14

Die photograph of the W-CDMA SiGe heterodyne transmitter chip shown in Figure 9.2.13.

3GPP spec to allow for process–temperature–environment variations). The out-of-band noise and spurs for the DCS band (1805 to 1880 MHz) is 121 dBm/Hz, for the TDD band (1893.5 to 1991.6 MHz) is 95.8 dBm/Hz, and for the Rx band (2110 to 2170 MHz) is 120 dBm/3.84 MHz. Figure 9.2.14 shows a die picture of this TX IC.

© 2006 by Taylor & Francis Group, LLC

9.2-919

SiGe as an Enabler for Wireless Communications Systems

Recently, Molnar et al. [29] have reported a single-chip BiCMOS quad-band direct-conversion GSM/ GPRS RF transceiver with fully integrated VCOs and fractional-N synthesizer. Subharmonic mixers are used in the direct-conversion receiver to ensure the LO to RF isolation, where the receive frequency is 2/3 and 4/3 of the UHF frequency for GSM versus DCS/PCS mode, respectively. The LO leakage at the receive band is measured approximately 110 dB m, which, together with a high receiver IIP2, reduces the dc offsets induced by large interferers coupling to the LO signal. A proprietary on-chip calibration helps the receiver IIP2 to be above 65 dB m for all modes. An on-chip transformer is used to do the single-ended to differential-signal conversion from LNA to drive a two-stage polyphase filter. The receiver AGC provides programmable gain from 9 to 125 dB in 2-dB steps, with eight poles of baseband filtering and a three-stage dc offset calibration correction. The NF is roughly below 4 dB for all modes under nominal operating condition. The fractional-N synthesizer includes a fully integrated wideband UHF VCO (1.2 to 1.7 GHz), where a band-switching VCO coarse-tuning technique is used (same as the one shown in Figure 9.2.10). The transmitter uses a translational loop with in-loop vector modulation. The transmit VCOs cover all four bands and meet the GSM out-of-band noise spec. We show in Figure 9.2.15 a single-chip transceiver in Si BiCMOS technology that successfully meets the DECT specifications [30]. With an advanced SiGe BiCMOS technology, the performance of the RF products can be significantly improved, enabling IC designers to build multistandard multiband singlechip RF systems for cellular applications. Similar to what has been recently reported by Molnar et al. in 0.35-mm BiCMOS technology, Figure 9.2.16 shows a die picture of a multiband single-chip direct-conversion SiGe BiCMOS transceiver that supports GSM/PCS/DCS multistandards as a highly integrated RF-SoC product [31]. Note that the IC in Figure 9.2.16 contains a 3.6-GHz VCO, transceiver, and synthesizer. However, the PA is still not integrated on-chip.

9.2.6 Summary To achieve the highest level of RFIC integration for single-chip, multiband, multistandard wireless devices of the future, we expect SiGe-based HBT technology to play a significant role. This is due to its

DeModulator

LNA

ADC O.C. ADC

Rx Data Rx CLK

VGA RSSI

AGC /2

VCO

Fref

PD Filter Cal.

/N /2

RSSI

O.C. Bandgap

PA

PPA

DAC

Modulator

DAC

Tx Data Tx CLK

FIGURE 9.2.15 Block diagram of a single-chip direct-conversion BiCMOS DECT transceiver. (From F.O. Eynde, J. Craninckx, and P. Goetschalckx. A fully-integrated zero-IF DECT transceiver. IEEE Int. Solid-State Circuits Conf., Dig., 2000, p. 138. With Permission.) Note only the PA, antenna switch, and filter are external to the chip.

© 2006 by Taylor & Francis Group, LLC

9.2-920

The Silicon Heterostructure Handbook

FIGURE 9.2.16 Die photograph of a multiband single-chip direct-conversion SiGe BiCMOS transceiver that supports GSM/PCS/DCS multistandards as a RF-SoC product. (From J. Sevenhas, F. Op’t Eynde, and P. Reusens. The silicon radio decade. IEEE Trans. Microwave Theory Tech. 50, 2002, 235–244. With permission.)

superior performance, ease of integration with CMOS, and low overall cost structure. This chapter has illustrated many of the key device, circuit, and system issues that will make this technology an important part of the wireless future.

References 1. D. Harame. Si/SiGe epitaxial-base transistors — Part I: Materials, physics, and circuits. IEEE Trans. Electron Dev., 1995, 455–468. 2. D.Y.C. Lie and K.L. Wang. Si/SiGe heterostructures for Si-based nanoelectronics. Handbook of Advanced Electronic and Photonic Devices and Materials, Chapter 1, H.S. Nalwa, ed., Academic Press, San Diego, 2000, pp. 1–69. 3. D. Nguyen-Ngoc, D.L. Harame, J.C. Malinowski, S.J. Jeng, K.T. Schonenberg, M.M. Gilbert, G.D. Berg, S. Wu, M. Soyuer, K.A. Tallman, K.J. Stein, R.A. Groves, S. Subbanna, D.B. Colavito, D.A. Sunderland, and B.S. Meyerson. A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications. IEEE Proc. BCTM, 1995, 89–92. 4. P.C. Davis. Merits and requirements of a few RF architectures. Proc. 1999 Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, September 1999, pp. 62–66. 5. B. Gilbert. The Design of Si/SiGe LNAs from the Ground Up. IEEE BCTM Short Course Notes, 1996.

© 2006 by Taylor & Francis Group, LLC

SiGe as an Enabler for Wireless Communications Systems

9.2-921

6. A. Abidi. Direct-conversion radio transceivers for digital communications. IEEE JSSSC 30(12), 1995, 1399–1410. 7. F. Aschwanden. Direct conversion — how to make it work in TV tuners. IEEE Trans. Consumer Electron. 42(3), 1996, 729–751. 8. L. Sheng, J.C. Jensen, and L. Larson. A wide-bandwidth Si/SiGe HBT direct conversion subharmonic mixer/downconverter. IEEE J. Solid-State Circ. 35(9), 2000, 1329–1337. 9. S. Mattison. Architecture and technology for Multistandard transceivers. Proceedings of Bipolar/ BiCMOS Circuits and Technology Meeting, 2001, pp. 82–85. 10. B. Jagannathan, M. Khater, F. Pagette, J. Rieh, D. Angell, H. Chen, H.J. Florkey, F. Golan, D. Greenberg, R. Groves, R.S. Jeng, J. Johnson, E. Mengistu, K. Schonenberg, C. Schnabel, P. Smith, A. Stricker, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna. Self-aligned site NPN transistors with 285 GHz fMAX and 207 GHz f T in a manufacturable technology. IEEE Electron Dev. Lett. 23(5), 2002, 258–260. 11. M. Vaidyanathan and D. Pulfrey. Extrapolated fMAX of heterojunction bipolar transistors. IEEE Trans. Electron Dev. 46(2), 1999, 301–309. 12. U. Konig, A. Gruhle, and A. Schuppen. SiGe devices and circuits: where are the advantages over III–V. Proc. 1995 IEEE GaAs IC Symposium, pp. 14–18. 13. L. Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip’’. IEEE Trans. Electron Dev. 50(3), 2003, 683–699. 14. E.O. Johnson. Physical limitation on frequency and power parameters of transistors. IEEE Intern. Conv. Record 5, 1965, 27. 15. R. Jos. Future developments and technology options in cellular phone power amplifiers: From power amplifier to integrated RF front-end module. Proceedings of the 2000 Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, pp. 118–125. 16. A. Inoue, S. Nakatsuka, R. Hattori, and Y. Matsuda. The maximum operating region in SiGe HBTs for RF power amplifiers. Proceedings of 2002 IEEE MTT-S International Microwave Symposium, Seattle, WA, USA, June 2002, pp. 1023–1026. 17. G. Niu, J. Cressler, Z. Shiming, W. Ansley, C. Webster, and D. Harame. A unified approach to RF and microwave noise parameter modeling in bipolar transistors. IEEE Trans. Electron Dev. 48(11), 2001, 2568–2574. 18. M. Vaidyanathan, L. Larson, M. Iwamoto, P. Asbeck, and P. Gudem. A basic theory of high frequency distortion in bipolar transistors. IEEE Trans. Microwave Theory Tech. 51(2), 2003, 448– 461. 19. D. Leeson. Simple model of a feedback oscillator noise spectrum. Proc. IEEE 54, 1956. 20. T.K. Johansen and L.E. Larson. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2003, pp. 273–276. 21. D.Y.C. Lie, X. Yuan, L.E. Larson, T. Robinson, A. Senior, X. Wang, J. Mecke, and M. Case. Phase noise analysis of fully-integrated digitally-tuned wideband Si/SiGe BiCMOS VCOs. Proc. IEEE Bipolar/BICMOS Circuits and Technology Meeting (BCTM), 2002, Monterey, CA, pp. 65–68. 22. D. Nguyen-Ngoc, D.L. Harame, J.C. Malinowski, S.J. Jeng, K.T. Schonenberg, M.M. Gilbert, G.D. Berg, S. Wu, M. Soyuer, K.A. Tallman, K.J. Stein, R.A. Groves, S. Subbanna, D.B. Colavito, D.A. Sunderland, and B.S. Meyerson. A 200 mm SiGe-HBT technology for wireless and mixed-signal applications. IEEE Proc. BCTM, 1995, 89–92. 23. A. Pa¨rssinen, J. Jussila, J. Ryyna¨nen, L. Sumanen, and K.A.I. Halonen. A 2-GHz wide-band direct conversion receiver for WCDMA applications. IEEE J. Solid-State Circ. 34(12), 1999, 1893. 24. J. Ryyna¨nen, K. Kiveka¨s, J. Jussila, A. Pa¨rssinen, and K. Halonen. A dual-band RF front-end for WCDMA and GSM applications. Proc. IEEE Custom Integrated Circuits Conference (CICC), 2000, p. 175. 25. K. Itoh, T. Katsura, H. Nagano, T. Yamaguchi, Y. Hamade, M. Shimozawa, N. Suematsu, R. Hayashi, W. Palmer, and M. Goldfarb. 2 GHz band even harmonic type direct conversion receiver with ABBIC for W-CDMA mobile terminal. IEEE MTT-S Digest, 2000, p. 1957.

© 2006 by Taylor & Francis Group, LLC

9.2-922

The Silicon Heterostructure Handbook

26. H. Pretl, W. Schelmbauer, L. Maurer, H. Westermayr, R. Weigel, B.-U. Klepser, B. Adler, and J. Fenk. A W-CDMA zero-IF front-end for UMTS in a 75 GHz SiGe BiCMOS technology. IEEE RFIC Symp. Dig., 2001, pp. 9–12. 27. D.Y.C. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, T. Beukema, L.E. Larson, A. Senior, C. Saint, J. Blonski, N. Swanberg, P. Pawlowski, D. Gonya, X. Yuan, and H. Zamat. A direct-conversion W-CDMA front-end SiGe receiver chip. Proc. IEEE Radio Frequency Integrated Circuits Conference (RFIC), 2002, pp. 31–35. 28. D. Malhi, L. Larson, D. Wang, C. Demirdag, and V. Pereira. SiGe W-CDMA transmitter for mobile terminal application. IEEE J. Solid-State Circ. 38(9), 2003, 1570–1574. 29. A. Molnar, R. Magoon, G. Hatcher, J. Zachan, W. Rhee, M. Damgaard, W. Domino, and N. Vakilian. A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer. IEEE Int. Solid-State Circuits Conf., Dig., 2002, pp. 232–233. 30. F.O. Eynde, J. Craninckx, and P. Goetschalckx. A fully-integrated zero-IF DECT transceiver. IEEE Int. Solid-State Circuits Conf., Dig., 2000, p. 138. 31. J. Sevenhas, F. Op’t Eynde, and P. Reusens. The silicon radio decade. IEEE Trans. Microwave Theory Tech. 50, 2002, 235–244.

© 2006 by Taylor & Francis Group, LLC

9.3 LNA Optimization Strategies 9.3.1 9.3.2

Introduction............................................................... 9.3-923 RF LNA Design Concerns ........................................ 9.3-924 Noise Factor/Figure . Gain and Matching . Linearity . Power Consumption and Stability

9.3.3

Optimization Strategies . Device Models . Simulation and Optimization . Analytical Expressions and Design Rules of Thumb

Qingqing Liang Georgia Institute of Technology

SiGe Cascode LNA Design Example........................ 9.3-927

9.3.4

Summary .................................................................... 9.3-935

9.3.1 Introduction In an RF receiver, one of the most important features is its noise characteristics; that is, the attribute of collecting the desired input signal while producing less noise. The noise factor F and noise figure NF are the parameters that measure the noise characteristics of RF receivers, F¼

SNin , SNout

NF ¼ 10 log10 (F),

(9:3:1) (9:3:2)

where SNin and SNout are the signal-to-noise ratios at the input and output of the amplifier, respectively. Using the definitions above, one can calculate the minimum detectable input power level Pin,min of a receiver: Pin,min ¼ F SNreq Pnf ,

(9:3:3)

where the SNreq is the required signal-to-noise power ratio at the output of the receiver, Pnf is the input noise floor. Pin,min is a fundamental parameter of a receiver: the smaller Pin,min, the higher sensitivity, and the wider space over which the receiver is functional. Note that both SNreq and Pnf are not determined by the receiver. Therefore, to improve the sensitivity of the receiver (i.e., a smaller Pin,min), F should be minimized. In a linear cascaded system (Figure 9.3.1), the overall noise factor Ftotal can be written as [1] Ftotal ¼ F1 þ

F2 1 F3 1 . . . , þ þ G1 G1 G2

(9:3:4)

9.3-923 © 2006 by Taylor & Francis Group, LLC

9.3-924

The Silicon Heterostructure Handbook

G1G2Pin

G1G2Nin+G2N1+N2

G1Pin Pin

G1Nin+N1 Nin

G1, N1

G2, N2

G3, N3

Gx: gain, Nx: noise power, x=1, 2, 3, ...

FIGURE 9.3.1 Signal and noise gain in cascade amplifiers.

where F1, F2, and F3 are noise factors of stages 1, 2, and 3, G1, G2, and G3 are gains1 of stages 1, 2, and 3, and so forth. Observe that if the gain of the first stage (G1) is high enough, the overall noise factor is dominated by the noise factor of the first stage (F1). Therefore, a low-noise amplifier (LNA), which provides a decent gain with a smaller F, is required and attached at the front of a receiver to obtain low Ftotal. Compared with other RF building blocks (e.g., mixers, oscillators), the circuit structure of LNA is kept simple, since more devices produce more noise. There are three main circuit topologies of LNA: singletransistor, cascade, and cascode [2–4]. Figure 9.3.2 shows the three different LNA equivalent circuit structures. Compared with single-transistor LNAs, the cascade and cascode LNAs provide higher gain and isolation. However, the single-transistor LNAs require less dc power consumption and can achieve lower noise factor. Different topology is then used depending on the application requirement. From a device perspective, the SiGe HBT is a better contender for Si-based RF LNAs because of its high speed, high gain, low noise, and good linearity characteristics [5]. The improvement of the device technology broadens the design space for LNAs. On the other hand, it raises the demand of general and elaborated optimization on LNAs to achieve better performances, indicating that the design and optimization is not only on a circuit-level (e.g., different circuit structures, biasing current) but also on a device-level (e.g., device geometry, device characteristics). In this chapter, we will focus on general design concerns and optimization strategies of LNAs. An example of a inductively degenerated cascode SiGe LNA optimization is then demonstrated.

9.3.2 RF LNA Design Concerns Noise Factor/Figure According to linear two-port noise theory [6], the noise factor (F ) or noise figure (NF) is a function of the source impedance (YS) and the noise parameters of the two-port system (Fmin, Rn, and Yopt): F ¼ Fmin þ

2 Rn YS Yopt , GS

(9:3:5)

where GS is the real part of YS, Fmin is the minimum noise factor, Rn is the noise impedance, and Yopt is the optimum admittance of the system. The noise parameters are functions of the biasing current and 1

The available gain is used in this situation, therefore Equation (9.3.4) assumes that the input and output of stages 1, 2, and 3 are matched.

© 2006 by Taylor & Francis Group, LLC

9.3-925

LNA Optimization Strategies

VCC Rc

VCC

RFIN

Cb

Q2 RFOUT

Ib

Cc RFOUT

Ic

Rc

Ic

RFIN

Cc

Cb

Ib Q1

VBIAS2

Rbb

Rbb

Ie

Ie VBIAS1

VBIAS Single-transistor LNA

Cascode LNA

VCC

VCC Rc2

Ic1 Cb RFIN

Ic2

Ib

Q2

Q1

Rbb1

Rbb2 Ie1

VBIAS1

Cc2 RFOUT

Cc1

Ie2 VBIAS2

Cascade LNA

FIGURE 9.3.2 The three different LNA equivalent circuit structures.

device properties (both active and passive). Figure 9.3.3 shows the noise factor and minimum noise factor as a function of the collector current (IC) of a single-transistor SiGe HBT LNA. In RF LNA, the source impedance is fixed (usually 50 V). Then the optimization goal is to engineer the noise parameters of the system for a lower F. One method is to find out the minimum Fmin in design space and then tune the Yopt (without changing Fmin) close to YS. This approach produces the lowest F of the amplifier. As shown in Figure 9.3.3, for example, the minimum Fmin is at IC ¼ 3.0 mA. Therefore, to obtain the lowest NF (i.e., 0.93 dB), IC should equal 3 mA and Yopt ¼ YS. In reality, however, other specifications (e.g., gain, linearity) of the LNA need to be considered, and trade-offs between the noise factor and these specifications are unavoidable. In this case, the noise figure F does not need to be tuned to Fmin because Fmin also depends on design variables (e.g., device geometry and biasing current [7]). As shown in Figure 9.3.3, the actual NF at IC ¼ 6 mA is lower than NFmin at IC ¼ 10 mA. It implies that losing the noise factor requirement can either trade for a larger biasing current range while Yopt ¼ YS holds, or a smaller IC range but more flexible noise matching requirement (i.e., Yopt 6¼ YS, hence there is a larger device geometry range to choose). Due to these concerns, general optimization strategies will be developed in the next section.

Gain and Matching The gain of LNA also affects the overall noise factor of the system. Among various gain definitions, the transducer gain (GT) and available gain (GA) are used as the figure-of-merit since the source impedance of LNA is fixed.

© 2006 by Taylor & Francis Group, LLC

9.3-926

The Silicon Heterostructure Handbook

1.2 Cadence simulation NF of the LNA NFMIN of the LNA NF (dB)

1.1

1

0.9 0.0

2.0

4.0 6.0 8.0 Collector current (Ic) (mA)

10.0

FIGURE 9.3.3 The actual noise factor and minimum noise factor as a function of the collector current (IC) of a single-transistor SiGe HBT LNA.

The transducer gain is the ratio of the actual power delivered by the amplifier to an arbitrary load to the power available from the source. It is a function of the s-parameters of the amplifier (s11, s12, s21, and s22) and the source and load reflection coefficients (GS and GL): 2

GT ¼ js21 j

1 jG S j2 1 jG L j2

j1 G Ss 11 j2 j1 G L G 2 j2

,

(9:3:6)

where G 2 ¼ s22 þ

s12 s21 G S : 1 s11 G S

(9:3:7)

The available gain is the ratio of the power available at the output of the amplifier to the power available from the source. It is actually the maximum transducer gain (by sweeping the load impedance) and is a function of the s-parameters and the source reflection coefficients: GA ¼ js21 j2

1 jG S j2 : j1 G Ss 11 j2 1 jG 2 j2

(9:3:8)

The source impedance is usually 50 V. Therefore GA ¼ js21j2=(1 js22j2). When an LNA is designed exclusively as an RF building block, low voltage-standing-wave-ratio (VSWR) at the input and output of the LNA is also required. This requirement offers good matching between the LNA and other blocks (e.g., antenna, mixer, filter). Therefore, the js11j and js22j of the LNA should be minimized. In ideal conditions, s11 ¼ s22 ¼ 0 and GA ¼ js21j2. Then the optimization goals concerning the gain and matching are to maximize js21j and minimize js11j and js22j.

Linearity Another concern in LNA is linearity. It confines the maximum input power of the LNA. For circuits such as LNA operating at small-signal range, the figure-of-merit of linearity is the input third-order intercept point (IIP3).

© 2006 by Taylor & Francis Group, LLC

9.3-927

LNA Optimization Strategies

Pout

Pout,1st

Pout,3rd Pout,3rd

noise floor

Pin,max1

Pin,max2 IIP31

Pin IIP32

FIGURE 9.3.4 The first- and third-order output powers as a function of input power of the LNAs with different IIP3s.

Figure 9.3.4 shows the first- and third-order output powers as a function of input power of the LNAs with different IIP3s. In the RF receiver, the third-order distortion of the output power is an unexpected signal, and should be lower than a required level (e.g., the noise floor) to maintain the output signal quality. Correspondingly, the input power should be lower than Pin, max Pin,max ¼ IIP3 (IIP3 þ gain-Pnf )=3

(9:3:9)

Where Pnf is Power level of the noise floor. Observe that the LNA with higher IIP3 exhibits a higher Pin,max , indicating a wider range for acceptable input power. Therefore, maximizing IIP3 is another goal of LNA optimization.

Power Consumption and Stability The total dc power is approximately equal to the product of the biasing current and supply voltage: PDC ¼

X

Ibias,i Vbias,i ,

(9:3:10)

i

where Ibias,i and Vbias,i are the dc current and voltage supply at pad i, respectively. The voltage supply is typically fixed, therefore smaller biasing current is desired for low-power LNA design. Additionally, a robust LNA should be unconditionally stable at any frequency range. These requirements are considered as design constraints rather than optimization goals.

9.3.3 SiGe Cascode LNA Design Example Optimization Strategies Without loss of generality, the optimization goals for RF LNAs are low noise (NF), high gain (js21j2), low VSWR (js11j and js22j), and high linearity (IIP3) with the low power consumption and stability

© 2006 by Taylor & Francis Group, LLC

9.3-928

The Silicon Heterostructure Handbook

constraints; and the design variables are the values of inductors (Lx), capacitors (Cy), resistors (Rz), the device geometry (LE)2, and biasing current (IC)3. The optimization goals can be written as functions of design variables [e.g., NF(Lx, Cy, Rz, LE, IC), IIP3(Lx, Cy, Rz, LE, IC)]. Therefore, the problem can be generalized as optimizing a group of goal-functions in an N-dimensional space, where N is the number of the design variables. For a better evaluation of the overall performance, we first choose the goal-functions that are not considered in the trade-off (e.g., js11j and js22j). The dimension of the design space decreases as these goal-functions are optimized. In inductively degenerated cascode LNAs (Figure 9.3.2), for example, the values of inductors and capacitors are determined when js11j and js22j are minimized, and consequently the design space is reduced to two-dimensional (LE and IC). Second, the values of those goal-functions, which are of interest to us (e.g., NF, gain, IIP3), are calculated in the design subspace, and contours of these functions are drawn. In this example, the contour-lines of NF, gain, and IIP3 are plotted in the two-dimensional (LE IC) space. Moreover, the design subspace shrinks when the additional design constraints are considered. For instance, the power consumption constraint requires that IC should be smaller than a required level (IC,max). Therefore, the design LE IC subspace diminishes from (0, 1) (0, 1) to (0, 1) (0, IC,max). The optimum design point, as shown later, can be easily found in this contour plot on the design subspace.

Device Models In this chapter, a simplified device model is used in analysis to derive analytical expressions and design rules of thumb. In actual design experience, delicate compact models, such as VBIC, HICUM, or MEXTRAM, are used so that the parasitics and second-order effects are considered. IBM 5HP SiGe HBTs are used in the design. Table 9.3.1 summarizes the measured transistor parameters of a unit SiGe HBT. Figure 9.3.5 shows the large-signal nonlinear model of the SiGe HBT. Here ICE represents the collector current transported from the emitter, IBE represents the hole injection into the emitter, and ICB represents the avalanche multiplication current: ICB ¼ ICE (M 1) ¼ IC0 (VBE )FEarly (M 1),

(9:3:11)

where IC0 (VBE) is IC measured at zero VCB, M is the avalanche multiplication factor, and FEarly is the Early effect factor. M 1 and FEarly were experimentally extracted using a technique proposed in Ref. [8]. M 1 is often modeled only as a function of VCB. In the SiGe HBTs used in this work, however, M 1 is also a strong function of JC [9]. The following equation was used to describe the VCB and JC dependence of M 1: TABLE 9.3.1 Measured Parameters of a SiGe HBT, the Device Size is 0.5 20 2 mm2 Peak b Peak fT tec tbb at IC ¼ 10 mA BVceo

2

110 51 GHz 2.7 psec 8.9 V 3.3 V

For brevity, the effect of device geometry is viewed as the effect of laying out multiple unit devices in parallel. Here the emitter length LE is used and is equivalent to a device scaling factor. 3 IC denotes the collector biasing current. For MOSFETs, IDS is used to denote the drain-source biasing current.

© 2006 by Taylor & Francis Group, LLC

9.3-929

LNA Optimization Strategies

XcjcC bc

(1−Xcjc)Cbc

I CB(V be,V bc) B

C rb

rc C be

I BE(V be) I CE(V be,V bc)

re

Nonlinear source:

C cs

Substrate

E

C be−EB capacitance C bc−CB capacitance C cs−CS capacitance

I CB−avalanche multiplications I CE−transport current I BE−hole injection into emitter

FIGURE 9.3.5 The large-signal nonlinear model of the SiGe HBT.

VCB Vmb M 1¼ exp 1b b , aVCB0 a VCB

(9:3:12)

where a is an empirical coefficient that accounts for Kirk effect a ¼ 1 tanh

IC VCB exp , IC0 VR

(9:3:13)

where VCB0, Vm, VR, IC0, and b are model parameters, and b is typically 0.33 to 0.5. These parameters were determined by fitting the measured M 1 data. In addition, Ccb is the collector base junction depletion capacitance, Ccs is the collector substrate depletion capacitance, and Cbe consists of diffusion capacitance Cde and depletion capacitance Cte according to Cbe ¼ Cde þ Cte ,

(9:3:14)

Cde ¼ gm t f :

(9:3:15)

In this model, six nonlinear sources are considered: nonlinear transconductance (gm), nonlinear EB conductance (gbe), nonlinear capacitances (Cbe, Cbc, and Ccs), and avalanche multiplication (ICB). In the RF LNA noise simulation, only broadband noise is considered.4 Figure 9.3.6 shows the noise model of the SiGe HBT, where ib2 and ic2 are the base and collector current shot noise sources

4

Since the devices in LNA are operating at small signal range, the device-induced low-frequency noise is negligible at radio frequencies.

© 2006 by Taylor & Francis Group, LLC

9.3-930

The Silicon Heterostructure Handbook

vb

vc

B rc

rb ib

C

ic

g be

re

Substrate

ve E

FIGURE 9.3.6 The noise model of the SiGe HBT.

ib2 ¼ 2qIb Df ,

(9:3:16)

ic2 ¼ 2qIc Df :

(9:3:17)

and n2rb , n2re , and n2rc are the thermal noise sources produced by the base, emitter, and collector resistances, respectively: n2rx ¼ 4kTRx Df ,

(9:3:18)

where ‘‘x’’ refers to ‘‘b,’’ ‘‘e,’’ or ‘‘c’’ for the base, emitter, or collector resistances.

Simulation and Optimization The general, Volterra-series method [10] is used to derive analytical expression of IIP3. As mentioned, the optimization process is adopted in the presented design methodology: first, for any given LE and IC, LB, LE, L1, R1, and C1 are calculated to obtain 50 V input and output impedance; second, the circuit netlist is updated with the calculated values and then gain (js21j2), NF, and IIP3 are simulated. The twodimensional gain, NF, and IIP3 contours are thus calculated by sweeping the two design variables. Note that the matching requirements are satisfied at each LE IC point in the contour plot. A determination of the optimum LE and IC that balances NF, gain (js21j2), and IIP3 can be obtained. Figure 9.3.7 shows the NF ¼ 1.2 dB, gain ¼ 15 dB, and IIP3 contours as a function of LE and IC. The design space for NF 1.2 dB is within the dashed line, and the design space for gain >15 dB is above the dash-dotted line. Within the design space that meets both NF 1.2 dB and gain >15 dB, observe that IIP3 changes dramatically, from approximately 5 to 15 dB m. The optimum design point for a maximum IIP3 is thus LE ¼ 80 mm and IC ¼ 7.5 mA. The maximum IIP3 is then above 15 dBm, with a resultant noise figure of 1.15 dB. In contrast, IIP3 at the design point optimum for noise figure (LE ¼ 60 mm, IC ¼ 4 mA) is only 0 dBm, with NF ¼ 1.04 dB. The LNA design point optimum for IIP3 is a better overall choice because noise figure is only degraded about 0.11 dB, while IIP3 is significantly higher (by 15 dB). The disadvantage of this design point, however, is that the required bias current is 3.5 mA higher.

© 2006 by Taylor & Francis Group, LLC

9.3-931

LNA Optimization Strategies

IIP3 contours (in dB m) 10

5

20

7

15

10

6

15

5

10 5

10 NF < 1.2 dB

0

4

5

3

−5

2

20

0

−5

−10 1

15

Gain > 15 dB

8 Collector current (mA)

10

5

9

40

60

80

100

120

140

160

180

200

Emitter length (µm)

FIGURE 9.3.7 The NF ¼ 1.2 dB, gain ¼ 15 dB, and IIP3 contours as a function of LE and IC.

Therefore, for an optimized design (80 mm and 7.5 mA), IIP3 ¼ 15.8 dB m, gain is 18 dB, NF ¼ 1.15 dB, and js11j,js22j < 30 dB. Furthermore, if the power consumption constraint shrinks to IC 5.5 mA, an IIP3 of 5 dB m can be obtained at LE ¼ 50 mm and IC ¼ 5.5 mA, with a near-minimum noise figure of 1.08 dB.

Analytical Expressions and Design Rules of Thumb The procedure introduced above is a numerical methodology that produces accurate simulation results. Furthermore, analytical expressions of the required inductors value, gain, NF, and IIP3 can also be derived by simplifying the device model [11]. These analytical expressions provide the design rules of thumb. To derive the analytical expressions, we neglect the emitter and collector resistance, base–collector and collector–substrate capacitance, and avalanche multiplication current. The analytical expressions of LE and LB can be written as: Rs 2pfT (1=g be Rs ) , 2pfT v2 b2

(9:3:19)

2pfT (1=g be Rs ) 2pfT (1=g be Rs ) Rs , le ’ v2 b v2 b 2pfT

(9:3:20)

le ’ lb ’

where v ¼ 2pf is the circuit operating frequency, Rs ¼ 50 V is the source impedance, and fT is the cutoff frequency at the chosen LE IC point. Note that gbe was neglected in the traditional input impedance matching equations, assuming 1 vb/2pfT and Rs 1/gbe [12]. However, the assumption of 2pfT vb is no longer valid when fT is much higher than the operational frequencies for SiGe HBT LNAs. In RFIC fabrication, smaller lb is preferred5 because that the Q-factor of typical onwafer inductors is small and hence will degrade noise performance. From the equations above, 5

The value le is usually much smaller than lb, then the effect of the parasitics of le on noise is negligible.

© 2006 by Taylor & Francis Group, LLC

9.3-932

The Silicon Heterostructure Handbook

when IC is fixed, the required lb becomes smaller as fT decreases. At low injection, fT decreases as the current density (JC ¼ IC/WE/LE, where WE is the emitter width) decreases, then larger LE requires smaller lb. Assuming that v 2pfT, then the current gain of the common-base stage is close to unity. Moreover, since the input impedance is matched to the source resistance Rs , the current injected into the EB junction is constant. Thus, the current gain equals to bg be b ¼ , gbe þ jvCbe 1 þ jvb=2pfT

(9:3:21)

and the gain of power can be written as G¼

b2 Rload : [1 þ (vb=2pfT )]2 Rs

(9:3:22)

At low injection, as JC increases, fT increases, and thus the gain increases. Hence, gain increases with increasing IC and fixed LE, and decreases with increasing LE and fixed IC, as expected. The noise figure can be written as: NF ¼ 10 log10 (1 þ nib þ nic þ nvb ),

(9:3:23)

(g be Rs )2 þ [B(1 g be Rs )]2 , 2gbe Rs

(9:3:24)

4(g be Rs )2 þ [g be Rs =B þ B(1 g be Rs )]2 , 2gm Rs

(9:3:25)

rb , Rs

(9:3:26)

nib ¼ nic ¼

nvb ¼

where B ¼ 2 pfT/vb. Under an overall power consumption constraint, IC normally is less than 10 mA, meaning g beRs 1. Rewriting the above equations, one obtains (g be Rs )2 þ B 2 , 2g be Rs

(9:3:27)

4(g be Rs )2 þ [g be Rs =B þ B]2 , 2gm Rs

(9:3:28)

rb : Rs

(9:3:29)

nib ¼ nic ¼

nvb ¼

According to these equations, when LE is fixed, at lower IC, the collector current shot noise (nic) is dominant. The NF increases as IC decreases. At higher IC, the base current shot noise (nib), which is proportional to IC, dominates NF. Thus, there is an optimum value of IC that minimizes NF. When IC is fixed, at a small LE, the thermal noise caused by the base resistance (nrb) is dominant. At a large LE, however, the collector current shot noise (nic) contribution dominates NF. Therefore, there is an optimum LE that balances the noise caused by rb and IC. Applying Volterra series, one can derive 3 IM3 ’ C(v1 ,v2 )L(v)(1 G(2v1 ) 2G(v1 v2 )), 4

© 2006 by Taylor & Francis Group, LLC

(9:3:30)

9.3-933

LNA Optimization Strategies

where C(v1 ,v2 ) ¼

1 1 nin,1 (v1 )nin,1 (v2 ) ’ jn2 (v1 )j, 6Vt2 6Vt2 in,1

(9:3:31)

and nin,1 is the first-order ac voltage on the EB junction. In addition, Vt K (v)G(v) , IC

(9:3:32)

A(v)IC , B(v) þ A(v)IC

(9:3:33)

B(v) , A(v)Vt

(9:3:34)

1 (Zb (v) þ Ze (v)) þ Ze (v), jvt f þ b

(9:3:35)

L(v) ¼ where G(v) ¼

K (v) ¼ A(v) ¼

B(v) ¼ Vt [1 þ jvCte (Zb (v) þ Ze (v))],

(9:3:36)

Zb (v) ¼ jvlb þ Rs ,

(9:3:37)

Ze (v) ¼ jvle ,

(9:3:38)

where le and lb are determined by Equation (9.3.19) and Equation (9.3.20). C(v1, v2) is the square of the magnitude of the first-order ac voltage across the EB junction. As IC increases, the voltage drop across the EB junction decreases, and thus this term decreases. L(v) is proportional to the current gain divided by IC at the operating frequency, and also decreases as IC increases. The third term of IM3, j(1G(2v1)2G(v1v2))j, determines the nonlinearity cancellation and is called cancellation term. Figure 9.3.8 shows the j1G(2v)j, j2G(Dv)j, and j1G(2v) 2G(Dv)j as a function of IC. At IC ¼ 7 mA, j1 G(2v)j is equal to j2G(Dv)j, and they are both in phase. Thus, j1G(2v)2G(Dv)j is minimized at this point.

Cancellation terms

100

10−1 |1– G (2s)–2G (∆w)| |1– G (2w)| |2 G (∆w)| 10−2

0.0

5.0

10.0 15.0 20.0 Collector current (mA)

25.0

30.0

FIGURE 9.3.8 Cancellation term and its two components as a function of IC. Note that the minimum value of this term responds to the maximum cancellation.

© 2006 by Taylor & Francis Group, LLC

9.3-934

The Silicon Heterostructure Handbook

Fixing LE, the cancellation term can be maximized at a specific IC. An IM3 valley or an IIP3 peak is observed when the effect of cancellation dominates. Figure 9.3.9 shows the three terms, the total IM3, and the IIP3 for the input-impedance matched amplifier. The minimum value of the cancellation term, IM3, and the maximum IIP3 occur at the same value of IC, proving that the cancellation term dominates IM3. The IM3 is a similar function of LE. However, at some ICs, the other two terms dominate IM3. Thus, when IC is fixed at these values, no IIP3 peak can be observed. Figure 9.3.10 and Figure 9.3.11 show the three terms, the IM3, and the IIP3 as a function of LE at IC ¼ 6 mA and IC ¼ 7.5 mA. An IIP3 peak can be observed at IC ¼ 6 mA, but no IIP3 peak is observed at IC ¼ 7.5 mA. The cancellation is pushed to higher current and weakened as IC increases, then the other two terms dominate the IM3 trend. The derived behavior of gain, NF, and IIP3 as varying LE and IC is identical to the simulations, although they offer better intuitive insight into the optimum LNA design space. Therefore, one can at the first-order locate the optimum design range using the equations above.

50 Total IM3 |1–G(2s) – 2G(∆s)|

IM3 (dB), IIP3 (dBm)

40 30

| L(2w1 – w 2) | C (w1,w 2) IIP3

20 10 0 –10 –20 –30 0.0

5.0

10.0 15.0 20.0 Collector current (mA)

25.0

30.0

FIGURE 9.3.9 The three terms, the total IM3, and the IIP3 for the input-impedance matched amplifier.

50

Total IM3 |1 – G(2w) – 2G(∆w)|

IM3 (dB), IIP3 (dBm)

40 30

|L(2w1 – w2) |C(w1,w2) IIP3

20 10 0 –10 –20 –30 0

20

40 60 Emitter length (µm)

FIGURE 9.3.10 IM3 terms and the IIP3 as a function of LE at IC ¼ 6 mA.

© 2006 by Taylor & Francis Group, LLC

80

100

9.3-935

LNA Optimization Strategies 50 Total IM3 |1 – G(2s) – 2G(∆s)|

IM3 (dB), IIP3 (dBm)

40 30

|L(2s1 – w2) |C(s1,w2) IIP3

20 10 0 –10 –20 –30

0

20

40 60 Emitter length (µm)

80

100

FIGURE 9.3.11 IM3 terms and the IIP3 as a function of LE at IC ¼ 7.5 mA.

9.3.4 Summary In this chapter, we proposed a generalized LNA design problem: how to trade-off various requirements of LNA in an extended design space, including all design variables. Then we presented optimization strategies and demonstrated a design example of an inductively degenerated cascade LNA using IBM 5HP technology. As shown in the example, close to the valley of NF, the noise figure changes slightly in a decently wide design-space, while IIP3 drops dramatically from 15 to 5 dB m. The results indicate that the optimization methodology, which considers not only NF but also IIP3 and gain, is necessary. The presented optimization strategies provide a convenient approach for an LNA design that balances all specifications. Furthermore, we derived the analytical expressions and design rules of thumb, which facilitate the determination of the optimum design range.

Acknowledgments We would like to thank D. Herman, A. Joseph, G. Freeman, D. Ahlgren, J. Dunn, B. Meyerson, and the IBM SiGe team for their support and contributions. This work was supported by IBM, the Semiconductor Research Corporation, and the Georgia Electronic Design Center at Georgia Tech.

References 1. B Razavi. RF Microelectronics. Indianapolis, IN: Prentice-Hall, 1997. 2. P Crippa, S Orcioni, F Ricciardi, and C Turchetti. Design of a 4.4 to 5 GHz LNA in 0.25-mm SiGe BiCMOS technology. Proceedings of the International Symposium on Circuits and Systems, 2003, pp. 333–336. 3. Q Liang, G Niu, JD Cressler, S Taylor, and DL Harame. Geometry and bias current optimization for SiGe HBT cascode low-noise amplifiers. Technical Digest of the IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 407–410. 4. M Soyuer, J-O Plouchart, H Ainspan, and J Burghartz. A 5.8-GHz 1-V low-noise amplifier in SiGe bipolar technology. Technical Digest of the IEEE Radio Frequency Integrated Circuits Symposium, 1997, pp. 19–22. 5. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Trans. Micro. Theory Tech. 46:572–589, 1998. 6. HA Haus, WR Atkinson, WH Fonger, WW Mcleod, GM Branch, WA harris, EK Stodola, WB Davenport Jr, SW Harrison, and TE Talpey. Representation of noise in linear twoports. Proc. IRE 48:67–74, 1960.

© 2006 by Taylor & Francis Group, LLC

9.3-936

The Silicon Heterostructure Handbook

7. S Zhang, G Niu, JD Cressler, AJ Joseph, G Freeman, and DL Harame. The effects of geometrical scaling on the frequency response and noise performance of SiGe HBTs. IEEE Trans. Electron Dev. 49:429–435, 2002. 8. G Niu, JD Cressler, S Zhang, U Gogineni, and DC Ahlgren. Measurement of collector–base junction avalanche multiplication effects in advanced UHV/CVD SiGe HBTs. IEEE Trans. Electron Dev. 46:1007–1015, 1999. 9. G Niu, Q Liang, JD Cressler, CS Webster, and DL Harame. IEEE Trans. Micro. Theory Tech. 49:1558– 1565, 2002. 10. P Wambacq and W Sansen. Distortion Analysis of Analog Integrated Circuits. New York, NY: Kluwer Academic, 1998. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 12. H Schumacher, U Erben, W Du¨rr, and K-B Schad. Low-noise, low-power wireless front-end MMICs using SiGe HBTs. IEICE Trans. Electron E 82-C:1943–1950, 1999.

© 2006 by Taylor & Francis Group, LLC

9.4 Linearization Techniques 9.4.1 9.4.2

Introduction............................................................... 9.4-937 Nonlinear Distortion Concepts................................ 9.4-938 Power Series Approach . Single-Tone Excitation . Two-Tone Excitation . Cascaded Systems . Feedback Configurations . Hard Nonlinearities and Clipping

9.4.3

Circuit Interaction of Device Nonlinearities .......... 9.4-945 Dominant Device Nonlinearities . Low Current/Power Operation . High Current/Power Operation

L.C.N. de Vreede and Mark P. van der Heijden Delft University of Technology

9.4.4

RF Design Techniques for Linearity ........................ 9.4-949 Current-Mode Operation . Negative Feedback Techniques . Shaping the Transfer Function . Harmonic Matching Techniques

9.4.1 Introduction Currently Si–SiGe BiCMOS process technology is the workhorse for the implementation of wireless building blocks. Depending on the application, circuit function, and communication standard, a wide variety of requirements and specifications have to be fulfilled. A general trend in wireless communication systems is the use of increased data rates within confined frequency bands. For this purpose, frequency bandwidth-efficient schemes for the digitally modulated signals (e.g. EDGE-GSM, WCDMA) have been introduced. One of the common characteristics of these communication standards is the large amplitude modulation component, which puts high linearity demands on the circuit blocks involved. For this reason linearity is currently a key requirement in modern RF front-end design, since the transceiver linearity mainly determines the proper reception or transmission of RF signals. This increased linearity requirement is in conflict with the general demand to lower the DC power consumption of new product generations. Consequently, the designer is confronted with the challenge to develop low DC power consuming, highly linear circuit solutions for the basic RF circuit functions like the low-noise amplifier (LNA), the up/down converting mixer, and the transmitter power amplifier (PA). This chapter is intended to provide the reader with basic understanding of nonlinear distortion in bipolar circuits and provide solutions towards the design of more power efficient and linear circuit implementations. In order to address this complicated task in a unified manner, we start in Section 9.4.2 with the review of basic distortion concepts relevant to RF design. Then, in Section 9.4.3 we study the linearity of a bipolar transistor for a simple but practical test circuit and identify the dominant distortion phenomena for a particular bias condition. Based on the knowledge of the dominant nonlinearities, we can distinguish various design techniques for improved circuit linearity. Finally, Section 9.4.4 introduces the basics of these design methods and gives various design considerations and constraints by comparing the different circuit implementations for their performance based on a 70 GHz SiGe reference device. All linearity considerations and conclusions are supported analytically as well as by harmonic balance 9.4-937 © 2006 by Taylor & Francis Group, LLC

9.4-938

The Silicon Heterostructure Handbook

simulations using the Mextram 504 model [1]. Especially, emphasis is placed on clarifying the dominant distortion phenomena and distortion cancellation conditions in today’s most popular and promising circuit topologies.

9.4.2 Nonlinear Distortion Concepts All practical active devices have nonlinear electrical characteristics; this is especially true for bipolar transistors, which have an exponential relationship between output current and input voltage. For this reason, circuits based on active devices will exhibit nonlinear distortion. Although there are some circuits that only exist by the grace of nonlinear device operation, like oscillators or frequency multipliers. In most cases, however, nonlinear circuit behavior is undesired, since it causes signal corruption and channel-to-channel interference.

Power Series Approach Depending on the circuit specification under consideration, linearity is expressed in terms like gain compression, intermodulation distortion, cross-modulation, blocking, and desensitization [2]. In order to gain more insight in nonlinear distortion phenomena, we consider for the moment the basic nonlinear properties of two widely used bipolar building blocks, namely the common-emitter (CE) stage in Figure 9.4.1 and the differential pair in Figure 9.4.2. These building blocks are often favored in LNA or mixer designs, due to their inherent high gain and low noise behavior. In our analytical considerations we assume for now a memoryless system. This basically means that we neglect all charge-storage elements and their associate nonlinearities in the active device, which is of course a strong simplification. Later in Section 9.4.4, we deal with these cases by using the more rigorous Volterra series approach for the analysis of weak nonlinear circuits [3, 4]. For now, we model the transfer functions of the CE-stage and the differential pair with a power series representation, as given by y(t) ¼ a1 x(t) þ a2 x 2 (t) þ a3 x 3 (t) þ . . .

(9:4:1)

in which the an are the Taylor coefficients of the transfer function at the desired operating point X0, defined as an ¼

1 dn y(X0 ) n! dx n

(9:4:2)

VCC RC

VCC

RC −

VBB RC RFC

vout

+

+ vout

vin −

vin IEE

FIGURE 9.4.1

The common-emitter configuration.

© 2006 by Taylor & Francis Group, LLC

FIGURE 9.4.2

The differential pair.

9.4-939

Linearization Techniques

The voltage transfer function of the CE-stage with ideal DC- voltage biasing and voltage drive at the base can now be expressed as VIN 1 VOUT ¼ VCC RC IC ¼ VCC RC IS exp VT

(9:4:3)

So, the nonlinear Taylor coefficients of VOUT are given by a1 ¼

RC IC RC I C , a2 ¼ , VT 2VT2

a3 ¼

RC IC 6VT3

(9:4:4)

Similarly, we can write the well-known voltage transfer function of the differential pair as [5]: VOUT ¼ RC IEE tan h

VIN 2VT

(9:4:5)

and the nonlinear coefficients of VOUT are a1 ¼

IEE RC , 2VT

a2 ¼ 0,

a3 ¼

IEE RC 24VT3

(9:4:6)

Note that the differential pair has an odd-transfer function, consequently all an are zero if n is even. We will now use the previously introduced power series models to explain some distortion phenomena under single and two-tone excitation.

Single-Tone Excitation If we excite the nonlinear system in (9.4.1) with a sinusoidal signal x(t) ¼ Acos(vt), harmonic signals will be generated at various frequencies: Fundamental DC 2ndHarmonic 3rd-Harmonic zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ ﬄ{ zﬄﬄﬄﬄﬄﬄﬄﬄﬄ ﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄﬄ}|ﬄﬄ{ 1 3 1 1 y(t) ¼ a2 A2 þ a1 A þ a3 A3 cos vt þ a2 A2 cos 2vt þ a3 A3 cos 3vt þ . . . 2 4 2 4

(9:4:7)

This type of distortion is called harmonic distortion and is especially harmful in broadband amplifiers such as in cable television (CATV) or audio amplifiers. In order to quantify harmonic distortion, usually the ratio is taken of the amplitude at the specific harmonic frequencies with the amplitude of the fundamental frequency, which is a1A. In this way the second-harmonic distortion (HD2) is expressed as 1 a2 HD2 ¼ A, 2 a1

(9:4:8)

and the third-harmonic distortion (HD3) is expressed as 1 a3 2 HD3 ¼ A 4 a1

(9:4:9)

In RF circuit design, these harmonics are almost always automatically filtered out, due to the narrowband nature of the circuits involved.

© 2006 by Taylor & Francis Group, LLC

9.4-940

The Silicon Heterostructure Handbook

Two other nonlinear phenomena that we can quantify using a single-tone excitation is the DC-shift due to self-biasing and gain compression or expansion. As we can see from (9.4.7), the self-biasing (12 a2 A2 ) is a second-order nonlinear effect and yields an increase in the DC-bias current. Gain compression or expansion can be explained by inspecting the fundamental amplitude in (9.4.7). We see that as the input signal amplitude A rises, the factor 34 a3 A3 (depending on the sign of the cubic term a3) may cause an increase or decrease of the fundamental signal (i.e. gain expansion or compression, respectively). For example, the cubic term of the CE configuration in (9.4.4) has the same sign as the linear term, leading to some gain expansion. On the other hand, the cubic term of the differential pair in (9.4.6) has an opposite sign with respect to the linear term, leading to gain compression at high drive levels. In fact, also the CE configuration will suffer from gain compression at some point. However, this will be due to other, strong nonlinear effects such as signal clipping to the supply voltage or saturation of the collector current (see ‘‘Hard Nonlinearities and Clipping’’ section), which are generally not described properly by a power series expansion. In general, gain compression is quantified by the 1 dB gain compression point (P1dB) and is defined as the input or output power level where the gain has dropped 1 dB with respect to the small-signal gain.

Two-Tone Excitation Two-tone testing is quite common for wireless systems, since it yields information about various undesired distortion phenomena, such as intermodulation distortion (IMD), crossmodulation distortion, blocking, and desensitization [2]. Here we only quantify intermodulation distortion, since in general it gives sufficient information about the other distortion types. In general, a two-tone test is performed by exciting a system with two sinusoidal signals with equal amplitude, namely: x(t) ¼ Acos(v1t) þ Acos(v2t). By substituting this two-tone input signal into (9.4.1), we obtain the following expression for the output signal, containing the distortion products up the third harmonic and intermodulation frequencies: Fundamental 2nd-Harmonic 3rd-Harmonic DC zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ}|ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{ zﬄ}|ﬄ{ 9 1 1 y(t) ¼ a2 A2 þ a1 A þ a3 A3 cos v1,2 t þ a2 A2 cos 2v1,2 t þ a3 A3 cos 3v1,2 t 4 2 4 3 þ a2 A2 cos (v2 v1 ) þ a3 A3 cos (2v1,2 v2,1 ) þ |ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ} 4 |ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ} 2nd-orderIMD 3rd-orderIMD

(9:4:10)

In which v1,2 refers to the two tones at v1 and v2, respectively. Besides the DC-shift and the harmonics, second-order intermodulation products (second-order IMD) are generated at the envelope (or baseband) frequency v2 v1 and sum frequency v2 þ v1. Furthermore, third-order intermodulation products (third-order IMD) are generated at 2v1,2 v2,1 adjacent to the fundamentals and at 2v1,2 þ v2,1 adjacent to the third harmonic. In general, the third-order IMD products at 2v1 v2 and 2v2 v1 are the most troublesome in RF circuit design, since these products are close to the desired channels and therefore cannot be filtered out, yielding signal corruption. The second-order IMD product at v2 v1 is equally important, when considering homodyne or zero-IF receivers. This is because, unwanted signals in the receive band (e.g., caused by channels that are unwanted but yet close in frequency to the wanted signal) can down convert through second-order nonlinearities, corrupting the desired baseband signal [2]. To illustrate some of the distortion figure of merits, we plot in Figure 9.4.3 the amplitude of the fundamental, the second- and third-order IMD as function of input signal amplitude as expressed in (9.4.10). Like HD2 and HD3, we now introduce IM2 and IM3, which are defined as the ratio of the intermodulation distortion amplitude with respect to the fundamental signal amplitude: a2 IM2 ¼ A a1

© 2006 by Taylor & Francis Group, LLC

(9:4:11)

9.4-941

Linearization Techniques

Output amplitude (log)

OIP3 OIP2

IM2

fundamental

IM3

2nd-harm.

3rd-harm.

Noise floor spurious-free dynamic range

IIP3 IIP2 Input amplitude (log)

FIGURE 9.4.3 The fundamental, the second-order, and third-order intermodulation amplitude as function of input amplitude.

3 a3 IM3 ¼ A2 4 a1

(9:4:12)

˙ D2 and IM3 ¼ Since we only consider a memoryless system (power series), we find that IM2 ¼ 2H ˙ 3HD3, which in general does not hold for systems with memory. Another figure-of-merit, which is commonly used in low-power or weakly nonlinear circuits, is the input second-order intercept point (IIP2) and the input third-order intercept point (IIP3). Both quantities are defined as the input amplitude A, where the extrapolated fundamental amplitude intersects with the extrapolated amplitude of second and third-order intermodulation products as depicted in Figure 9.4.3 a1 IIP2 ¼ a2 sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ 4 a1 IIP3 ¼ 3 a

(9:4:13)

(9:4:14)

3

If we calculate all these distortion figures for the voltage-driven differential pair and the CE stage using the coefficients in (9.4.4) and (9.4.6), the IM2 and IM3 become IM2CE ¼ IM3CE ¼

1 A , 2 VT

1 A2 , 8 VT2

IM2DP ¼ 0 IM3DP ¼

1 A2 16 VT2

(9:4:15) (9:4:16)

and the IIP2 and IIP3 become IIP2CE ¼ 2VT , IIP2DP ¼ 1 pﬃﬃﬃ IIP3CE ¼ 8 VT , IIP3DP ¼ 4VT

© 2006 by Taylor & Francis Group, LLC

(9:4:17) (9:4:18)

9.4-942

The Silicon Heterostructure Handbook

Discussion The previous analysis showed that the input intercept point of a bipolar transistor is independent of the DC bias current. This can be better understood by looking at the output current of a bipolar transistor as function of input voltage. This can be evaluated with the following analysis, where we use the power series of the exponential collector-current nonlinearity: ic (t) ¼ gm y be (t) þ gm,2 y 2be (t) þ gm,3 y 3be (t)

(9:4:19)

in which gm ¼

IC , VT

gm,2 ¼

IC , 2VT2

gm,3 ¼

IC 6VT3

(9:4:20)

If we now write ybe(t) in terms of the desired linear output current ic1(t) and transconductance gm as ybe(t) ¼ ic1(t)/gm, we find 2 3 (t) þ B3 ic1 (t), ic (t) ¼ ic1 (t) þ B2 ic1

(9:4:21)

in which Bn ¼ gm,n/ gmn. Normalizing the above for IC yields m(t) ¼

ic (t) ¼ m1 (t) þ IC B2 m21 (t) þ IC2 B3 m31 (t) IC

(9:4:22)

with m1(t) ¼ ic1(t)/IC, being the relative linear current swing. Substituting the nonlinear coefficients of (9.4.20) in (9.4.22), we obtain [6] 1 1 m(t) ¼ m1 (t) þ m21 (t) þ m31 (t) 2 6

(9:4:23)

Consequently, the IM3 for a CE stage can be written as 3 1 ic1 2 IM3 ¼ IC2 B3 jm1 j2 ¼ 4 8 IC

(9:4:24)

Note that m1(t) ¼ ic1(t)/IC ¼ ybe(t)/VT, which for ybe(t) ¼ A cos(v1t) þ A cos(v2t) leads to the same IM3-expression for the CE stage as found in (9.4.16). From (9.4.24) we observe that IM3 is a function of the relative output current swing. Therefore, linearity can be improved for a required output current swing by increasing the DC bias current. In the same way we can argue that the linearity improves by decreasing the relative voltage swing at the input with respect to the thermal voltage VT for a given DC bias current.* This is why in practice it is always possible to improve the output linearity of a transistor stage at the expense of DC power consumption. This becomes more evident when we consider the output third-order intercept point (OIP3) of a bipolar transistor. The OIP3 is defined as the amplitude of the fundamental at the output at which the extrapolated IM3 amplitude intercepts the extrapolated linear part of the fundamental amplitude (see Figure 9.4.3). Alternatively, the OIP3 can also directly be calculated by multiplying IIP3 with the linear gain factor (i.e., gm ¼ IC/VT in case of a voltage driven CE-stage, where we monitor the output current), consequently OIP3 ¼

pﬃﬃﬃ 8IC ¼ gm IIP3

*Decreasing the input voltage swing is commonly referred to as back-off.

© 2006 by Taylor & Francis Group, LLC

(9:4:25)

9.4-943

Linearization Techniques

From this we can conclude that for a purely voltage driven bipolar transistor, the OIP3 is proportional to the collector current IC, as long as the nonlinear distortion of the bipolar transistor is dominated by its exponential nonlinearity.

Cascaded Systems In RF transceiver design, we are normally dealing with a cascade of nonlinear circuits blocks (e.g., the cascade of the LNA and the downconverting mixer). In order to calculate the (spurious-free) dynamic range of the receiver (see Figure 9.4.3), we need to know how the nonlinearities of the individual blocks are referred back to the input. The easiest way to do this, is by calculating an overall input third-order intercept point in terms of the individual intercept points of all stages. Therefore, we consider the two cascaded nonlinear stages in Figure 9.4.4 of which the nonlinearity of stage A is given by (1) and the nonlinearity of stage B by z(t) ¼ b1 y(t) þ b2 y 2 (t) þ b3 y 3 (t)

(9:4:26)

We can calculate the overall IIP3 of the cascaded system by calculating the intersect of the fundamental response with the resulting overall third-order nonlinear response. We can do this by substituting (1) into (26) and regroup the first- and third-order terms of the overall response, yielding [2]:

IIP3cas

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ 4 a1 b1 ¼ 3 3 a1 b3 þ 2a1 a2 b2 þ a3 b1

(9:4:27)

In a worst-case scenario, the terms of the denominator under the square-root of (9.4.27) will add linearly, yielding the following approximation: IIP32cas ¼

1 a2 3a2 b2 þ 12 þ 2 IIP3A IIP3B 2b1

1 (9:4:28)

where IIP3A and IIP3B represent the input IP3 of the first and second nonlinear circuit blocks in Figure 9.4.4. The last term in (9.4.28) represents the secondary mixing in stage B of the second-harmonic and the fundamental provided by stage A. Although, in general, people tend to ignore this term, in practical situations it can influence the overall linearity significantly. For the moment, however, we can conclude from (9.4.28) that by increasing the gain (a1) of stage A, the linearity of stage B becomes relatively more important and tends to form a natural limit for the overall linearity of the system.

Feedback Configurations Negative feedback plays an important role in RF circuit design in both a beneficial and harmful way. Undesired linear (or nonlinear) feedback through the base–collector capacitance and emitter resistance are examples of the harmful aspects of feedback, since it basically limits the high-frequency gain of the device. A positive aspect is the possibility to create an accurate overall linear transfer function with ‘‘linear’’ passive components. This is why it is interesting to study the effect of negative feedback on the overall linearity of a system in more detail. For this purpose we consider a nonlinear amplifier with a

y

x A

FIGURE 9.4.4 A cascade of two nonlinear amplifiers.

© 2006 by Taylor & Francis Group, LLC

z B

9.4-944

The Silicon Heterostructure Handbook

+

x

s -

y

A

f

FIGURE 9.4.5 A nonlinear amplifying element with linear feedback.

linear negative feedback loop as given in Figure 9.4.5 for which the transfer of the nonlinear amplifier core is given by y(t) ¼ a1 s(t) þ a2 s 2 (t) þ a3 s 3 (t)

(9:4:29)

We can develop the expression for the IM2 and IM3 of the overall feedback amplifier in terms of the Taylor coefficients of the nonlinear core and the negative feedback element f, given the fact that for Figure 9.4.5 we can write s(t) ¼ x(t) fy(t)

(9:4:30)

y(t) ¼ a1 [x(t) fy(t)] þ a2 [x(t) fy(t)]2 þ a3 [x(t) fy(t)]3

(9:4:31)

y(t) ¼ n1 x(t) þ n2 x 2 (t) þ n3 x 3 (t)

(9:4:32)

Substitution of (9.4.30) in (9.4.29) yields

By now substituting

in both left and right-hand side of (9.4.31), we can solve for n1, n2, and n3 by isolating the terms with the corresponding power of x(t), yielding: n1 ¼

a1 , 1 þ a1 f

n2 ¼

a2 , (1 þ a1 f )3

n3 ¼

a3 (1 þ a1 f ) 2a22 f (1 þ a1 f )5

(9:4:33)

With these nonlinear Taylor coefficients of the overall negative feedback amplifier, we can compare the second- and third-order IMD of the feedback amplifier IM2FB and IM3FB to the second- and third-order IMD of the nonlinear amplifier core alone (IM2Amp and IM3Amp), which are expressed as IM2Amp n2 a2 A¼ 2A¼ n1 a1 (1 þ a1 f ) (1 þ a1 f )2

(9:4:34)

IM3Amp 3 n3 2 3 a3 A ¼ A2 ¼ , 4 n1 4 a1 (1 þ a1 f )3 (1 þ a1 f )3

(9:4:35)

IM2FB ¼ IM3FB ¼

where we assumed for simplicity that a2 ¼ 0 in the calculation of IM3. In that case, we see from (9.4.34) that the feedback action reduces the second-order intermodulation distortion of the original amplifier (IM2Amp) by a factor of (1 þ a1f )2 and the third-order intermodulation distortion of the original amplifier (IM3Amp) is reduced by a factor (1 þ a1f )3. Note that there is another contribution to IM3FB, when (a2 6¼ 0). In that case, secondary mixing of even harmonics with the fundamental occurs

© 2006 by Taylor & Francis Group, LLC

Linearization Techniques

9.4-945

due to the feedback action, yielding an additional contribution to IM3FB, as can can be observed from (9.4.33).

Hard Nonlinearities and Clipping When the amplitude of the input signal is increased, at some point the output signal that can be generated by the active device(s) will be limited by the bias circuit and are no longer able to follow the input signal over its complete cycle. This is called clipping, yielding a dramatic loss in linearity performance. For this reason clipping conditions should be avoided at all times. An effective way to identify potential clipping problems in a design is to plot the load lines of all active devices in the circuit for a time domain signal with increasing amplitude. In this way voltage or current clipping conditions for each device can be easily recognized and encountered for.

9.4.3 Circuit Interaction of Device Nonlinearities Until now we have addressed the basics of nonlinear distortion using ideal bipolar devices with no memory effects, driven by an ideal voltage source. As a consequence, the interaction of the nonlinearities with the surrounding circuitry was more or less omitted. However when considering RF circuit design with real devices, we have to extend our scope in order to identify the dominant sources of distortion at a given bias and frequency point of operation. One of the most commonly used configurations to test the device behavior for single-tone excitation is the common-emitter stage configuration with 50 Ohm loading conditions at input and output [7–10]. The motivation of this choice is mainly based on the wide availability of 50-Ohm ‘‘small-signal’’ device characterization equipment and consequently, the ease of measurement. One should be aware, however, that device linearity is the result of a strong interaction between active device and external (harmonic) loading conditions provided by the surrounding circuitry. For this reason one must be very careful to qualify device linearity for modulated signals under these simple, far from ideal loading conditions. Note for example that even the presents of simple bias Tees in combination with the DC bias sources in the test setup, can yield ill-defined impedances at the base-band or envelope frequency (v2 v1) for a twotone excitation. As will be discussed in Section 9.4.4, this influences the device linearity measurements to a great extent. Based on these considerations, semiconductor manufactures prefer to use practical but rather simple and therefore well-defined test configurations to quantify the linearity performance of their devices. These test configurations are often simplified situations of a meaningful application of their devices, and are adapted to some degree to the desired impedance level and biasing condition of the active device under test (DUT). Although not providing the ultimate linearity performance of the DUT, these benchmark circuits are very useful to identify the influence regions of the various distortion sources [12].

Dominant Device Nonlinearities A typical benchmark circuit is shown in Figure 9.4.6, which represents a two-tone test for a dual-loop feedback single-stage transistor network. Note that this configuration can provide simultaneous matched impedance conditions at input- and output by setting the resistors R1 and R2 to their proper values [11]. In this section we use such benchmark circuit to investigate the linearity of a typical highspeed SiGe transistor, like the 0.5 mm 20.3 mm Philips QUBiC4G BNA style transistor with a peak-fT of 70 GHz @ 10 mA. In the remainder of this chapter, we will use this device as a reference transistor to analyze its nonlinear behavior for various circuit conditions. To introduce this device, Figure 9.4.7 and Figure 9.4.8 show the IC(VCE), fT(IC), and Fmin (IC) characteristics. As can be observed from this figure, the device exhibits a peak-fT of approximately 70 GHz, an Fmin of 0.8 dB, while its BVCE0 is 2.5 V. To identify the dominant distortion characteristics of this device under different bias conditions, we consider the circuit topology of Figure 9.4.6. A two-tone test with small amplitude was performed on

© 2006 by Taylor & Francis Group, LLC

9.4-946

The Silicon Heterostructure Handbook

R1 Vout Vin Zout= Z0 R2

Zin= Z0

FIGURE 9.4.6 AC-schematic of a typical benchmark circuit for two-tone testing of an active device for linearity. 30.0m

IC (A)

20.0m

10.0m

BVCEO~2.5 V 0.0 0.0

FIGURE 9.4.7 SiGe BJT.

0.5

1.0

1.5

2.0 VCE (V)

2.5

3.0

3.5

4.0

The IC–VCE characteristic for constant IB in 10 mA steps of the 0.5 mm 20.3 mm Philips QUBIC4G

6

80G 70G

5

60G

fT (Hz)

3

40G 30G

Fmin (dB)

4

50G

2

20G 1

10G 0

1⫻10−3

0.01

0

IC (A)

FIGURE 9.4.8 The fT and Fmin versus IC characteristics derived at 5 GHz for VCE ¼ 0.5, 1, 1.5, 2, and 2.5 V of the 0.5 mm 20.3 mm Philips QUBIC4G SiGe BJT.

© 2006 by Taylor & Francis Group, LLC

9.4-947

Linearization Techniques

this circuit in order to compute the OIP3 in each bias point of the IC–VCE plane, as shown in Figure 9.4.9. By plotting the lines of constant OIP3 in the IC–VCE plane of the bipolar device, we can identify three regions where different nonlinearities dominate. In support of this identification, Figure 9.4.9 also indicates the bias conditions where ‘‘weak’’-avalanche sets in (VCE 2.5 V), the peak-fT occurs, as well as the points where the fT of the device has been reduced to half of its peak value due to high current effects. The ‘‘Low’’ Current Region In the region where IC < IC @ fTpeak the distortion is dominated by the exponential dependency of IB, IC, and the diffusion term of Cbe (CDE ¼ tf gm) on the input voltage VBE. This can be easily verified by observing there is almost no variation of OIP3 with VCE but only with IC. Consequently, the DC bias current sets the output linearity, what is in line with the conclusions found for the ‘‘bare’’ CE-stage in Section 9.2.2. The Base–Collector/Nonlinear Transit Time Dominated Region At higher DC-current levels the influence of the exponential distortion on the OIP3 is reduced, therefore other nonlinearities become visible. One of the most important effects is the nonlinear feedback through the base–collector capacitance Cbc and the variation of tf [13]. Both effects result from the base-charge modulation by the collector voltage and current swing, and become more dominant at a lower VCE or at higher current levels close to quasisaturation. This is due to the strong increase of Cbc and tf at these bias conditions. Since in general, feedback defines the transfer of a network [11], nonlinear feedback through Cbc and tf will lead to a nonlinear transfer function and consequently to a nonlinear circuit operation. The Avalanche Region At ‘‘very’’ high collector voltages ‘‘weak’’ avalanche effects occur [14], resulting in an avalanche current between the base and the collector. Consequently, again a nonlinear feedback appears which interacts with the other device non-linearities. At higher voltages, this interaction can degrade or improve the device linearity depending on the phase relations of the individual distortion components. Note, for example, that at low current levels the IIP3 should be constant as function of VCE. However, we observe in Figure 9.4.9 that there is some improvement of the IIP3 for very high VCE due to the influence of

12

14

12

pe

0.01 16 14

0

12

0

0.5

18

16

20

20

f T p e18 ak

16

12 14

18

fT

12 4

τf 1 d n n a tio C bc stor di

20

18

Exponential 14 distortion

16

12

12

1

24

ak

/2

22

IC [A]

0.02

0.005

20 22

0.025

0.015

18

16

12

14

Avalanche distortion

16

12

0.03

1.5

2

2.5

3

VCE [V] FIGURE 9.4.9 Constant OIP3-contours in dBm on the IC – VCE plane for the SiGe reference device, simulated in the circuit of Figure 9.4.6. Indicated are the dominant distortion phenomena and the bias conditions for the peak-fT and the points where the fT has dropped to halve its peak value due to high current effects.

© 2006 by Taylor & Francis Group, LLC

9.4-948

The Silicon Heterostructure Handbook

‘‘weak’’ avalanche effects. In practical circuit implementations we avoid device operation under these bias conditions in order to guarantee a reliable operation. Based on the previous observations, we define a simplified equivalent schematic in Figure 9.4.10 of a bipolar transistor, including the most dominant distortion sources. For the functional description of these sources and charges we refer to Ref. [14]. In the remainder of this chapter we will use simplifications of this model in order to evaluate BJT device linearity for practical circuit conditions. Having the previous linearity considerations of the benchmark circuit in mind combined with this simple model; we are now able to make classifications for design strategies commonly found in ‘‘classical’’ RF circuit design. For this purpose we will distinguish between low and high current/ power operation.

Low Current/Power Operation From the above it is obvious that the exponential relationship between input voltage and currents and charges dictates low-current applications. For this reason, one is in practice focused on the exploration of the ‘‘linear’’ input-to-output current relation or the so-called current-mode type of design [15]. A simple practical way to achieve this is the use of high-Ohmic source and low-Ohmic load conditions of the transistor stages as will be discussed in Section 9.4.4. Although simple to use and very effective, this technique is not directly compatible with the universal desire of RF engineers to design for characteristic ‘‘50-Ohm’’ input- or output impedances. For these typically low-characteristic source impedances we find a significant deviation from the ideal current-driven situation, which is based on the use of infinite source impedance. Therefore, the device will be driven by input power rather than input current. Consequently, the device will also be voltage driven. This results again in the situation that one suffers from the exponential relation between input-voltage, current, and diffusion charge. This simple fact has triggered various design techniques for improving linearity, ranging from local feedback (e.g. inductive emitter degeneration [16]), overall feedback [11, 17], to multi-tanh [18] or ultra-multi-tanh stages [19] in order to mask the exponential transfer function. Although effective for many applications, the general trend in RF circuitry is to increase operating frequency and reduce the DC power consumption and supply voltage, yielding significant limitations when implementing the desired linear RF circuit functions without compromising other specifications. In respect of this, recently new circuit design techniques became available for the design of LNAs, mixers, and PAs that eliminate the classical trade-offs between DC-power consumption, gain, noise, and linearity [16, 20–22], facilitating a high linearity performance at low current levels and high frequencies. These designs are based on the use of out-of-band matching techniques in order to fully exploit IM3 cancellation effects. In general, these circuit designs can operate at much lower DC powers for a given linearity requirement. Besides that, the amount of trade-offs can be reduced, which are required between

QBC RB

RC

b

c IAVL QBE

IB

IC

RE e

FIGURE 9.4.10 Simplified large signal equivalent circuit of a bipolar transistor with all dominant nonlinearities in forward active operation, RB, IB, IC, IAVL, QBE, and QBC.

© 2006 by Taylor & Francis Group, LLC

Linearization Techniques

9.4-949

the various specifications. Although very promising, the latter design technique is in general more difficult to implement, since the proper impedances must be provided not only at the fundamental, but also at the second-harmonic as well as the IF or base-band frequencies. We will describe these techniques in Section 9.4.4.

High Current/Power Operation At higher DC current levels, for a properly scaled device in class-A operation, the influence of the exponential distortion can be neglected (see also (9.4.25) for the OIP3). Consequently, the nonlinear feedback capacitance Cbc and the dependency of the delay time tf on the output voltage are most troublesome for linearity, since both cause a nonlinear feedback action over the device. Due to the fact that the transfer function of a network is predominantly determined by its feedback elements, the transfer-function will also become nonlinear. Design techniques should therefore target the reduction of this undesired non-linear feedback by harmonic loading [23], unilateralization, or by modifying the transistor technology for the lightly doped epilayer [24]. Note that for hard driven devices quasisaturation effects come into play [8, 14], which yield a strong increase of the total base charge and consequently also Cbc and tf. Besides the undesired nonlinear feedback through the base charge modulation, also weak avalanche effects play a role since they cause a nonlinear feedback action to the internal base node as well. Normally this operation region will be avoided in most designs. However, if one wants to push a PA stage to its maximum performance for a given technology this effect might be important. In these special cases, attention should be given to bias circuitry in order to handle the negative going base current. At the same time, one can use harmonic terminations at the output in order to shape the waveform in such a way that the peak excursion remains limited [23, 25, 26]. The use of out-of-band terminations at the input can be used to further boost the linearity and enhance self-biasing effects to improve the power compression behavior of the amplifier [27].

9.4.4 RF Design Techniques for Linearity In the previous section various linearization techniques were mentioned, which will be discussed and studied here in more detail. In order to link our discussion to practical design examples, we will use the previously introduced 70 GHz SiGe BJT as reference device. This 0.5 mm 20.3 mm BJT, which has its peak fT of 70 GHz @ 10 mA, will be modeled by a simplified analytical Volterra series model to highlight the basic distortion mechanisms of a particular circuit design, as well as, by the full Mextram model to illustrate the validity of the analysis and its related assumptions. In sequence, we will discuss the current-mode or translinear design approach, the use of feedback design techniques with a focus on inductive emitter degeneration, the applicability of multi-tanh-based circuits for RF design and conclude with an inventory of linearization techniques based on the utilization of out-of-band terminations.

Current-Mode Operation One of the most effective ways to design highly linear circuitry at lower power levels is the use of currentmode design techniques [15], which are based on the ‘‘linear’’ current relationship between the collector and the base current. The basic assumption in current-mode design is that the input signal is delivered by a current source with an infinitely high drive impedance. In that case we operate the transistor in current-mode in contrast to our previous analysis in Section 9.4.2, where we considered ideal bipolar devices without memory effects under voltage-driven conditions. In order to investigate the applicability of this design technique with respect to linearity at RF frequencies, this section studies the influence of the source impedance on the linearity of a bipolar device with memory (capacitances) and evaluates the results towards different design approaches. For the moment we will assume constant (resistive) terminations at the input- and output of the stage under

© 2006 by Taylor & Francis Group, LLC

9.4-950

The Silicon Heterostructure Handbook

consideration and study the influence of the source resistance RS on the common-emitter stage and the common-base stage. Analysis of a CE Stage in Current-Mode To investigate the influence of the source resistance on linearity, we analyze the circuit of Figure 9.4.11 using a Volterra series analysis. The full analysis for the CE-stage is given in detail in the Appendix, however, in this analysis we have used the Miller approximation for the base–collector capacitance, since it is assumed that the collector is terminated with a low impedance. Besides that, taking the feedback of the base–collector capacitance into account, does not significantly improve the accuracy of our analysis, while the equation complexity would increase dramatically. Furthermore, the series feedback through the emitter resistance rE is neglected for simplicity. First of all, the overall linear transfer function relating the source voltage Vs to the output current Ic is given by H1c (s) ¼

Ic ¼ gm H1b (s) Vs

(9:4:36)

in which the linear transfer function H1b (s), relating the source voltage Vs to base–emitter voltage Vbe is given by H1b (s) ¼

Vbe 1 RP 1 ¼ ¼ 1 þ gm RS =bf þ sCp Rs RS 1 þ sRP Cp Vs

(9:4:37)

where RP ¼ rp / / RS, rp ¼ bf /gm, Cp ¼ CjE þ tf gm, and s ¼ jv. In order to make a fair comparison, we must use the output-current referred third-order intercept point OIP3 rather than the IIP3, when driving the transistor with a very low impedance (voltage-mode) or a very high impedance (current-mode). This can be understood by considering the extreme case (RS ! 1) in Figure 9.4.11, where the high source impedance prevents any signal power going into the device, yielding a very high IIP3. Therefore, we focus on the OIP3, which is in this case the only viable means of comparison. Then, for the simplified circuit in Figure 9.4.11 we obtain

OIP3CE

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ H13c (s2 ) 4 4 gm3 (s) ¼ 3 H3c (s2 , s2 , s1 ) 3 j«(Ds, 2s)j jA(s)j

(9:4:38)

in which A(s) ¼

RP (1 þ sRS CjE ) RS (1 þ sRP Cp )

(9:4:39)

RS

Vs

iB

Vbe CjE

FIGURE 9.4.11 current-mode.

iC

CDE

The simplified large-signal model of a CE-stage for studying the intermodulation distortion in

© 2006 by Taylor & Francis Group, LLC

9.4-951

Linearization Techniques

and «(Ds, 2s) ¼

gm RP (1 þ 2sRS CjE ) RP (1 þ DsRS CjE ) þ 1 3VT2 2RS (1 þ 2sRP Cp ) RS (1 þ DsRP Cp )

(9:4:40)

When substituting gm ¼ IC/VT and assuming Ds ¼ + j(v2 v1) 0, we obtain 2IC OIP3CE ¼ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ RP (1 þ sRS CjE ) RP (1 þ 2sRS CjE ) RP 1 þ R (1 þ sR C ) 2R (1 þ 2sR C ) R S P p S P p S

(9:4:41)

As we will see, the ratio of RS and rp plays a primary role, since RP/RS ¼ (1 þ RS/rp) 1. This is most evident when we consider the low frequency limit or ‘‘DC-behavior’’ of (9.4.38) by setting s ¼ 0, yielding

OIP3CE,DC

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ (1 þ RS =rp )2 ¼ 2IC 2 1 2R =r S

(9:4:42)

p

The denominator of (9.4.42) indicates that an IM3-cancellation effect exists for a specific base-current level, namely IB ¼ VT/2RS. This ‘‘low’’-frequency IM3-cancellation phenomena was already reported by Reynolds [28] and results from the interaction of the source resistance with the nonlinear base–emitter junction. We will address IM3-cancellation in more detail in ‘‘Harmonic Matching Techniques’’ and here only focus on the current-mode design approach. For this reason we will now compare as a function of frequency the current-mode situation where RS >> rp and the voltage-mode situation where RS rp. In current-mode, setting RS >> rp in (9.4.41) yields approximately OIP3CE,cm

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ RS 1 þ srp Cp 2IC r 1 þ sR C p

(9:4:43)

S jE

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ which for low frequencies (OIP3CE 2IC RS =rp ) is a strong function of the ratio RS/rp. When plotting starts ﬃdecreasing at 1/2pRSCjE and levels (9.4.43) as a function of frequency (Figure 9.4.12), the OIP3p CEﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ off just beyond the frequency v ¼ vT / bf to OIP3CE 2IC Cp =CjE . When considering voltage-mode, setting RS rp in (9.4.41) yields

OIP3CE,vm

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ (1 þ sRS Cp )(1 þ 2sRS Cp ) 2IC 2 (1 þ sRS CjE )(1 þ 2sRS CjE )

(9:4:44)

pﬃﬃﬃ which shows that OIP3CE 8IC over a wide frequency range and slightly increases at high frequencies, since Cp > CjE. To illustrate the previous equations, Figure 9.4.12 plots the calculated and simulated OIP3CE versus frequency in current-mode (RS ¼ 50k) and in voltage mode (RS 0). This leads to the conclusion that a current-mode design with a CE-stage is beneficial when the driving impedance RS is much higher compared to rp and when we operate the circuit below vT/bf. In practice this puts relatively high demands on the driving circuit. Also note that the gain versus frequency performance of this stage is strongly frequency dependent. To improve for these points, when aiming design for current-mode operation, people quite often prefer the use of a common-base (CB) configuration. For this reason, we will now also study the linearity of the CB-stage.

© 2006 by Taylor & Francis Group, LLC

9.4-952

The Silicon Heterostructure Handbook

1/2πRSCjE f T/b f

−42

OIP3CE (dBI)

−44

−46

fT

OIP3 (mextram) OIP3 (calculated)

Current-mode RS = 50 k

−48

voltage-mode RS = 0

−50

−52 6 10

FIGURE 9.4.12

107

108 109 Frequency (Hz)

1010

1011

The OIP3 in dBI versus frequency of a CE-stage in current-mode and voltage mode.

Analysis of a CB-Stage in Current-Mode The circuit of the CB-stage is given in Figure 9.4.13. Since b >> 1 for typical SiGe devices we can neglect the base current nonlinearity with respect to the collector current nonlinearity. In this case, the expression for OIP3 is similar to the one in the previous example with the only difference that RP ¼ re//RS with re ¼ 1/gm, yielding 2IC OIP3CB ¼ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ RP (1 þ sRS CjE ) RP (1 þ 2sRS CjE ) RP R (1 þ sR C ) 2R (1 þ 2sR C ) þ R 1 S P p S P p S

(9:4:45)

This means that now the ratio of RS and re plays a primary role. Again we compare the current-mode (RS >> re) to the voltage-mode situation (RS re), which for the current-mode (RS >> re) in (9.4.45), yields

OIP3CB,cm

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ RS 1 þ sre Cp 2IC r 1 þ sR C e

(9:4:46)

S jE

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ In the low-frequency limit (9.4.46) becomes OIP3DC 2IC RS =re , which is a strong function of the ratio RS/re. Moreover, the linearity improvement of a current-mode CB-stage extends up to vT, making current-mode design attractive also at high frequencies (Figure 9.4.14). In voltage-mode, setting RS re in (9.4.45) yields

OIP3CB,vm

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ (1 þ sRS Cp )(1 þ 2sRS Cp ) 2IC 2 (1 þ sRS CjE )(1 þ 2sRS CjE )

(9:4:47)

which is equal to that of the CE-stage in voltage mode. Most importantly, these equations show again that the lowest distortion is obtained in current-mode when RS >> re. Figure 9.4.14 plots the OIP3CB as function of frequency for a CB-stage in current-mode (RS ¼ 5k) and voltage-mode (RS 0). This figure clearly shows that in current-mode operation the linearity improvement of a CB-stage extends to almost the cutoff frequency and is a strong function of RS and re, of which the latter is set by IC.

© 2006 by Taylor & Francis Group, LLC

9.4-953

Linearization Techniques

RS Vs

iC Vbe

CjE

CDE

FIGURE 9.4.13 The simplified large-signal model of a CB-stage for studying the intermodulation distortion in current-mode.

−28

1/2πRSCjE

fT

current-mode

−32 R = 5 k S

OIP3CB (dBI)

−36

OIP3 (mextram) OIP3 (calculated)

−40 −46 −48 −52

Voltage-mode RS = 0

−56 106

107

108 109 Frequency (Hz)

1010

1011

FIGURE 9.4.14 The OIP3 in dBI versus frequency of a CB-stage in current-mode and voltage mode.

From the previous analyses we can conclude that once again, when the source impedance is high compared to the input impedance of the transistor stage (current-mode) we can obtain a significant reduction of the IM3 compared to the voltage-driven situation. However, since the input impedance of a CB-stage at lower frequencies is approximately a factor bf lower than for a CE-stage, current-mode operation is enforced for much lower values of the source resistance. This freedom can be utilized to obtain linear transfer functions, which are less frequency-dependent compared to the CE stage, yielding improved current-mode operation up to very high frequencies (Figure 9.4.14). A practical situation where we use the current mode for the CB-stage is for example in the Gilbert mixer where the switching core is driven by the high ohmic output of the driving stage (see Figure 9.4.15). Note that, although a mixer in general is considered as a nonlinear component due to the up- or down-conversion of the RF signal by the switching/mixing action with the LO signal, the RF signal transfer of the lower stage to the switching core must be linear in order to obtain a proper ‘‘distortionfree’’ up- or down-frequency conversion. In practice, current-mode signal transfer of the driving stage to the switching core almost automatically arranges this property. Consequently, most difficulties with mixer nonlinearities are found in converting the input signal power to a current-mode signal by the driving stage. To deal with this problem, we will consider various approaches in ‘‘Negative Feedback Techniques’’ and ‘‘Shaping the Transfer Function.’’ Translinear Design Techniques The translinear loop (TL) principle is also a form of current-mode, which can be applied in order to obtain the desired overall linear current-to-current relation [15]. It is based on intermediate transitions from current-mode to voltage-mode, and vice versa. In practice, when a closed loop of base–emitter junctions is formed, a TL is created, which can be configured to yield linear current-to-current transfer

© 2006 by Taylor & Francis Group, LLC

9.4-954

The Silicon Heterostructure Handbook

VCC ZIF

VIF

ZIF

+ Switching core

VLO −

+ VRF

−

Driver stage IEE

FIGURE 9.4.15

Gilbert cell mixer with switching core and differential driver stage.

functions. Figure 9.4.16 shows the current-mirror, which is one of the most simple examples of this principle. The input current Ii is converted to a nonlinear base–emitter voltage Vbe ¼ VT ln (Ii/IS) and translated again to a current Io ¼ IS exp (Vbe/VT), which is linearly proportional to the original input current and scaled by the ratio of the active device area Ae2/Ae1. In this context, however, we will treat these techniques as an extension of the current-mode design approach. An extensive discussion of various translinear circuit design techniques that also addresses distortion generated by device mismatch and b-nonlinearity can be found in Ref. [15]. A practical example of a PA driver based on the TL principle can be found in Ref. [29], where the input drive signal is a current, which is converted to an output signal power. Another nice example that makes use of the TL principle is the Micromixer [30]. It uses a TL driver stage as shown in Figure 9.4.17, which can handle very large input current signals without introducing significant distortion. Although elegant, this design approach does not provide a solution for the transfer of the input signal power to a current representation. This is caused by the voltage-dependent input impedance of the micromixer. As a result, the overall linearity of the micromixer is dominated by this aspect. Discussion When applicable, current-mode design provides you with a direct and straightforward implementation of the desired linear circuit functions. Although efficient for many applications, one should be aware of the limitations of this technique. This becomes apparent when considering higher frequencies of operation, where the relative high base–emitter capacitance of a bipolar transistor limits the proper use of current-mode design for CE-stages (v vT / bf ). CB-stages are more tolerable at this point due to their much lower input impedance (re), which lowers the impact of the base–emitter capacitance at higher frequencies. Another advantage of current-mode design techniques is the ease of combining output signals of various circuit blocks by summing the output currents. An illustrative example of this technique is given by Aggarwal et al. [29] where the outputs are current-summed at all times. As closing remarks on the current-mode design approach, we mention that although translinear design techniques are available [15], which relax the influence of b-nonlinearity; one should verify that when designing at very low currents or high currents levels, the collector-to-base current ratio is not significantly degraded by the nonideal base-current or high-current effects [14]. In addition, for very

© 2006 by Taylor & Francis Group, LLC

9.4-955

Linearization Techniques

Ii

Io

Ae1

Ae2 Vbe

FIGURE 9.4.16 The current mirror as an example of a simple translinear circuit.

VPOS

IF loads

LO Driver

VLO QM1

QM2

QM3

I1

QM4 IB

I3 Q1

ZS

CC

QZ1 Q3

VGEN

CD

Q2

VRF I2

QZ2

COM

FIGURE 9.4.17 The micromixer uses a translinear circuit to implement a linear current-to-current transfer between the RF-input and the switching core. (From B. Gilbert. The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric class-AB input stage. IEEE J. Solid-State Circ. 32(9), 1412–1423, 1997. With permission.) Copyright 1997 IEEE.

highly linear applications, attention should be paid to the b-nonlinearity caused by the reverse Early effect [14, 31]. Although this is in general a weak nonlinearity that depends on the semiconductor technology, it may limit the linearity of current-mode designs to some extent. Finally, it must be mentioned that current-mode design techniques often lack noise optimization and do not provide a real solution for the nonlinear transfer of the input signal voltage (or power) to a current representation. This makes this design technique less favorable for a front-end LNA design operating at several GHzs. For this reason, the next section considers other design techniques, which overcome these problems.

Negative Feedback Techniques Feedback design techniques are commonly used in electronic circuits to improve the circuit performance in terms of well-defined (wideband) transfer characteristics and optimum impedance matching conditions for both low return loss and low noise. In addition, the use of negative feedback makes the

© 2006 by Taylor & Francis Group, LLC

9.4-956

The Silicon Heterostructure Handbook

circuit less sensitive to process, temperature variations and here most importantly, it reduces the error in the transfer characteristics, making the overall circuit more linear. Overall Feedback For these reasons and as became apparent from the analysis of ‘‘Feedback Configurations,’’ the use of negative feedback is at first sight an effective and attractive technique to improve the linearity of a system. Therefore it is not surprising that overall feedback based on multiple transistor stages is one of the favored design techniques at lower frequencies [11, 32]. At high frequencies, however, overall feedback design is somewhat less common. Here conventional microwave techniques or the use of only local feedback stages are mostly favored. The reasons for this are the following: firstly, at higher frequencies the gain of the active devices drops and therefore the use of negative feedback is less attractive, since it lowers the gain even more. Secondly, RF applications require device operation closer to the fT of the device, yielding a relative large phase shift per stage. Consequently, combining more stages within a feedback loop can easily yield an instable situation. Finally, wireless communication circuits are quite often more bandpass oriented than lowpass, which is traditionally the case for most feedback designs. Note that a bandpass characteristic makes the circuit less sensitive for jamming or blocking by an interfering signal outside the band of interest, while a lowpass characteristic would not suppress interfering signals at lower frequencies. Although these considerations put some restrictions to the blind application of feedback design techniques, the recent improvements in high-frequency performance of SiGe devices facilitate the use of these feedback techniques also at higher frequencies. In view of this, we provide here some design guidelines for linear negative feedback amplifiers. .

.

.

.

.

A large loop-gain reduces the distortion (see ‘‘Feedback Configurations’’) therefore the loop-gain must be maximized, preferably by adding more active stages, while assuming the overall gain to be fixed by the feedback network. In practice this approach will be limited by stability considerations that pose a maximum on the number of transistor stages that can be used (e.g., for practical circuits in the order of two to three stages [11, 33]. When using a cascaded chain of gain stages, the conclusion of ‘‘Cascaded Systems’’ apply and consequently, the stage with the highest nonlinearity must be placed at the beginning of the amplifying chain, while the stage with the highest gain and linearity should be placed at the end of the amplifying chain. Note that the requirements on the signal handling of the stages increases with their position in the cascaded chain. Increasing the DC-bias current of the stages will increase their transconductance and consequently their gain, yielding a higher overall loop gain. Furthermore, the relative current swing (see Equation (9.4.22)) for the stages will be reduced. Both effects will yield an improved linearity at the cost of DC power consumption. The use of local feedback within the active loop should in general be avoided, since the linearity improvement of the local stage will vanish compared to the drop in linearity as a result of the lower overall loop gain [32]. Since the resulting linearity is not only depending on the loop-gain itself (consider e.g., the loop-gain term a1f in (9.4.33)–(9.4.35)), but also on the magnitude of the nonlinearity to be reduced (e.g., a2 and a3 in (9.4.33)–(9.4.35)), it is also important that these ‘‘loop errors’’ are reduced as well [34]. This can be accomplished by applying current-mode coupling of the gain stages within the loop, or when considering a voltage-current transfer (due to a nonideal current-driven stage at the beginning of the chain of cascade stages) the inclusion of a stage with a shaped (linearized) transconductance function like the multi-tanh doublet [18], which we discuss later in ‘‘Shaping the Transfer Function’’.

A practical example of the application of overall feedback in a RF mixer is shown in Figure 9.4.18, where overall feedback is applied in order to implement the LNA driver block of the switching core [17]. In this way the inherently nonlinear transfer of the ‘‘power’’ input signal to the output drive current for the switching core is linearized.

© 2006 by Taylor & Francis Group, LLC

9.4-957

Linearization Techniques

VCC Rbias1

Rload1

Cbp1

IF_out+

Rbias3

LO+ Q3

R1

R5

VRF_in+

R3

Q4

1

Rbias5

Rbias7

Dual-Loop FBLNA Q2

R2

R4

Iref

2

Rbias2

Cbp2

LO−

VCC Q7

Q5

R7

Rload2 Rbias4

Switching mixer

LO− Q1

IF_out−

Q8

R6

VRF_in− Q6

Rref

Rbias8

Rbias6

R8

FIGURE 9.4.18 Dual-loop wide-band active-feedback LNA and switching mixer. (From Adiseno, M Ismail, and H Olsson. A wide-band RF front-end for multiband multistandard high linearity low-IF wireless receivers. IEEE J. Solid-State Circ. 37(9), 1162–1168, 2002. Copyright 2002 IEEE.)

Local Feedback As mentioned before, traditionally only local feedback is applied at ‘‘very’’ high frequencies to improve the linearity of a transistor stage. For this purpose, the most frequently used configuration is the emitter degenerated CE-stage. Depending on the type of emitter degeneration, resistive, capacitive, or inductive, the linearity of the stage can be improved to a great extent. This has been analyzed by Keng and Meyer [16], who discuss the results for various emitter degenerated CE and differential stages. In order to follow the discussion of Keng and Meyer, we consider the schematic of Figure 9.4.19. In the following discussion we assume again low-current operation, and consequently that the dominant source of nonlinearity is formed by the exponential distortion of the base–emitter junction, which is reflected in ib, ic, and the diffusion capacitance CDE. The complete analysis is given in the Appendix, but in this study we neglect the influence of Cbc. This assumption simplifies the equations, without losing generality of the main aspects of series feedback. The source impedance ZS and base resistance rB are both absorbed in Zb and the emitter resistance rE and any externally applied emitter impedance ZE are absorbed in Ze. Consequently, when applying a two-tone excitation, assuming s s1 s2 and Ds ¼ (s1 s2) s, we can write the input-referred IM3 product as 3 ^s2 IM3 ¼ j«(Ds, 2s)j jH1b (s)j3 jD(s)j V 4 ^s2 1 1V 3 ¼ jH1b (s)j jT (s)j H1b (2s) þ T(2s) þ H1b (Ds)T (Ds) 1 4 VT2 2

(9:4:48)

in which the transfer from the source voltage to the internal base–emitter voltage is defined as H1b (s) ¼ and

© 2006 by Taylor & Francis Group, LLC

Vbe 1 ¼ 1 þ Z(s)(gp þ sCp ) þ gm Ze (s) Vs

(9:4:49)

9.4-958

The Silicon Heterostructure Handbook

rB

Vb

ZS Vs

Zb CjE

iB

CDE Ve

iC

rE ZE

Ze

FIGURE 9.4.19 Large-signal model of a CE-stage for studying the effects of series feedback.

T (s) ¼ 1 þ sCjE Z(s)

(9:4:50)

where Z(s) ¼ Zb(s) þ Ze(s) is the sum of the series impedances in the base and emitter, the device parasitics, and the characteristic impedance of the driving source. From (9.4.49) we observe that the use of a high emitter impedance Ze as emitter degradation effectively lowers the voltage transfer of the source to the internal base–emitter junction by H1b, yielding directly to a reduced IM3 level as can be seen in (9.4.48). In addition to this basic feedback phenomenon, the IM3 level is also influenced by a factor T(s) in (9.4.48). Here T(s) represents the interaction of Z(s) with CjE at the fundamental frequency, while T(Ds) and T(2s) address these effects at the baseband and double frequencies. Note that these later frequencies are sometimes also referred to as out-of-band frequencies. The influence of the factors, T(s), T(Ds), and T(2s) on the IM3 level have been the subject of various studies in literature. In Ref. [16] focus was placed on partial IM3-cancellation effects through T(s), while the influence of T(Ds) and T(2s) was recognized but considered as a secondary effect. In the study of [16] three choices for Ze(s) where considered, namely: .

.

.

Capacitive. Choosing Ze capacitive, yields a real positive value for sCjEZe(s), which adds up to the ‘1’-term of T(s) in (9.4.50), consequently, the IM3 level increases by this factor. Resistive. Choosing Ze ¼ Re will result in a positive imaginary value of sCjEZe(s), which again yields an increase of T(s), however less dramatically as in choosing Ze capacitive. Inductive. Choosing Ze inductive proves to be the most beneficial, since it results in a negative real value for sCjEZe(s), lowering the factor T(s), and consequently the IM3 level.

Note that perfect IM3-cancellation through T(s) requires that Z(s) is purely inductive. In practical situations this will never be the case since Z(s) is composed out of: Ze, Zb the device series resistances rB, rE, and the characteristic impedance of the driving source (RS ¼ R0). As a result, only partial IM3cancellation will occur based on the influence of the factor T(s) alone. Inspection of (9.4.48) also reveals that the IM3 level is influenced by T(Ds) and T(2s) in the most righthand factor of (9.4.48), which relate to the device-circuit interactions at the baseband and double frequency. Consequently, a specific choice of Z(s)-like inductive emitter degradation in combination with a proper choice of other circuit elements can also yield ‘‘partial’’ IM3-cancellation effects through these terms. The relevance of the cancellation effects via T(Ds) and T(2s) becomes much more apparent when considering the noise and power matching conditions for an inductively degenerated emitter stage (Figure 9.4.20). For this configuration it can be shown, that by proper selection of LE, gm, and the active device area Ae the optimum noise match at the base can be manipulated close to the conjugate value of the input impedance of the stage [35]. As a result, simultaneous noise and impedance matching for an inductively degenerated emitter stage can be easily implemented. By adding the remaining impedance matching network to the base (in its most simple form an inductor), an easy to implement, highperformance LNA stage is created, which for most applications offers a very acceptable noise, impedance

© 2006 by Taylor & Francis Group, LLC

9.4-959

Linearization Techniques

Ae

Z*in= Zopt,N

LE

FIGURE 9.4.20 CE-stage with inductive emitter degeneration.

match, and linearity performance. Therefore, this configuration is currently one of the most popular input stages in RF circuit design. It must be mentioned, however, that for this configuration the requirements for simultaneous noise and power match prove to be incompatible with the requirements for IM3-cancellation through the factor T(s), since this would simply require a too high value of LE, LB, and/or Ae compared to the component values required for optimum noise and impedance match (ZS ¼ Z*in ¼ Zopt, N). In addition, Z(s) always contains a real part associated with device parasitics and source resistance obstructing full IM3-cancellation. Therefore, the sometimes-remarkable high linearity results reported for this topology, must be explained by the ‘‘partial’’ IM3-cancellation effects through the terms T(Ds) and T(2s) [16, 36]. A practical example of these phenomena can be found in Ref. [7], which gives a simulation based experiment of an inductively degenerated CE-stage, to study the best compromise of various design parameters with respect to: noise, impedance matching, gain, and linearity for a given SiGe technology. In Refs. [7, 16], the distortion reduction through the baseband frequency and second harmonics is considered as a positive side effect, and not fully explored. Consequently, high linearity and low noise can be obtained, but at a relative high current level for a limited modulation bandwidth. Cascode LNA Design To illustrate the above we will now consider the linearity performance of an inductively degenerated cascode-LNA design in Figure 9.4.21 operating at 5 GHz using our reference transistor. The cascodeLNA has been optimized for simultaneous noise and impedance matching conditions by proper selection of LE, gm, and the active emitter area Ae. The base inductor LB takes care for the remaining imaginary part of the input matching. In our design the input bias-decoupling capacitance (CD ¼ 20 pF) behaves like a short for the fundamental, while blocking the low-frequency component at the baseband (or envelope) frequency. This allows us to tweak the linearity using the elements in the base biasing circuitry, which basically defines Z(Ds) seen by the bipolar device at its internal base–emitter junction. Note that the inductor in the bias path (LCH ¼ 20 nH) will represent a large impedance value at the fundamental frequency, eliminating any influence of the biasing circuitry on the noise level of the LNA. The simulation results of this circuit are given in Figure 9.4.22, which shows the minimum noise figure (Fmin), the noise factor (F), power gain, and return loss in dB as function of collector current IC. Evidently, simultaneous noise and impedance matching conditions have been achieved at a gain level of 15 dB and a bias current of IC ¼ 5 mA. When considering the linearity in terms of low- and high-band IIP3, for a small tone spacing (Df ¼ 0.1 MHz) we find a ‘‘partial’’ IM3-cancellation conditions around 6 mA as shown in Figure 9.4.23. Note that this distortion optimum slightly differs from the current for minimum noise level. When repeating this simulation using a larger tone spacing (Df ¼ 100 MHz), we observe that asymmetry in the IM3 distortion products causes a difference in the low- and high-band IIP3, while the peaking becomes less pronounced in the higher band. Note that the lowest IIP3 level indicates the usable linearity performance of the stage. Finally, when considering the IIP3 for the LNA using a different value of the resistor in the bias path (RB ¼ 3k), the distortion cancellation mechanism disappears resulting in a much lower linearity, while the noise performance and matching conditions remain unchanged. The latter experiment clearly indicates that indeed Z(Ds) through the factor T(Ds) has a significant impact on the linearity performance of this LNA configuration, which is in agreement with the results in Ref. [36].

© 2006 by Taylor & Francis Group, LLC

9.4-960

The Silicon Heterostructure Handbook

V B1 = 0.823 V V B2 = 2 V V CC = 3 V A e1 = 5 A e2 = 3

RB

V B1

CH

V CC

LH

RC CL

L CH A e2

RS CS

VS

LB

LC

A e1

LE

V B2

R S = R L = 50 R B = 30 R C = 250 C S = C L = 20 pF L E = 0.28 nH L B = 1 nH L CH = 20 nH L H = 6.75 nH C H = 0.15 pF

RL

FIGURE 9.4.21 A 5-GHz cascode LNA with inductive emitter degeneration. 2.0

10

Power gain Return loss Fmin

0

1.5

F 1.0

−10 −20

Noise figure (dB)

Gain (dB), Return loss (dB)

20

0.5

−30 0.0

2.0 m

4.0 m 6.0 m 8.0 m Collector current (A)

10.0 m

0.0

FIGURE 9.4.22 Simulated small-signal power gain, return-loss, and noise figure as function of collector current for the 5 GHz cascode LNA with inductive emitter degeneration.

When considering the differential pair transconductance stage [16] for their linearity, similar conclusions can be found as for the single-ended stage when comparing the linearity performance of capacitive, resistive, or inductive emitter degeneration, with again finding the best performances for the inductive case. However, it must be noted that the IM3 of a degenerated differential pair is at least twice as large as that of a degenerated CE-stage with the same bias current and degenerated transconductance** [16]. A nice example of a class-AB mixer with inductive degeneration is given in Figure 9.4.24. Discussion The ease of integration, the high linearity, combined with the inherent simultaneous noise and impedance matching properties, provided by the inductively (differential or single-ended) degenerated CE-stage, has led to its great popularity in wireless applications. In spite of this, there are also some **Without degeneration the IM3 of the differential pair is twice as small as that of a CE-stage (see ‘‘Two-Tone Excitation’’).

© 2006 by Taylor & Francis Group, LLC

9.4-961

Linearization Techniques 25 IIP3Io = IIP3hi(RB = 30, f = 0.1 MHz) IIP3Io = IIP3hi(RB = 3 k, f = 0.1 MHz) IIP3Io(RB = 30, f = 100 MHz) IIP3Io(RB = 30, f = 100 MHz)

20

IIP3 (dBm)

15 10 5 0 -5 -10 -15 0.0

2.0 m

4.0 m

6.0 m

8.0 m

10.0 m

Collector current (A)

FIGURE 9.4.23 Simulated input referred intercept point (IIP3) as function of collector current for the 5 GHz cascode LNA with inductive emitter degeneration.

IREF C5

L5

R3 R4

L6

C6 IF−

IF+ R2 LO−

Q5

Q6

LO+

Bias circuit R1 Qa C2

L1

Le

L2 L3 C3

C1 RF Bond wires: L1,L2,Le Off-chip inductors: L3,L5,L6

FIGURE 9.4.24 A class-AB mixer, which uses inductive emitter degeneration to achieve low noise and high linearity performance. (From Keng Leong Fong and RG Meyer. High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages. IEEE J. Solid-State Circ. 33(4), 548–555, 1998.) Copyright 1998 IEEE.

‘‘minor’’ drawbacks. Namely, inductive degeneration means negative feedback, consequently the gain of the stage is reduced. As a result, sufficiently high gain (and linearity) is paid with a relative high DC current that can be disadvantageous for battery-operated applications. Finally, since noise matching, impedance matching, gain, and linearity, all have to be addressed through the same, limited number of design parameters (LE, the emitter area Ae and gm or IC), suboptimum solutions are sometimes unavoidable. In order to overcome these limitations, we will develop in ‘‘Harmonic Matching Techniques’’ ‘‘out-of-band’’ IM3-cancellation techniques to their full extent. This new design technique offers more design freedom to the designer, which can be utilized to realize circuits operating at a very low DC

© 2006 by Taylor & Francis Group, LLC

9.4-962

The Silicon Heterostructure Handbook

power, while providing high gain and linearity over a large bandwidth, at the expense of a somewhat more difficult design procedure/implementation.

Shaping the Transfer Function In the previous section negative feedback was promoted as design technique to improve the linearity of a signal transfer function. This worked out to be particularly useful when considering the strongly nonlinear voltage-to-current transfer of a bipolar device. While the basic principle of negative feedback is based on the reduction of the transfer error by increasing the return difference and loopgain (Equation (9.4.35) in ‘‘Feedback Configurations’’), the multi-tanh design technique [18], which we describe in this paragraph, is focused on the linearization of the nonlinear voltage–current transfer itself. To introduce these topologies let us first consider the input-voltage to outputcurrent relation of an ideal differential pair stage (see Figure 9.4.2) without any memory effects, which can be written as [5]: IOUT ¼ IEE tan h

VIN 2VT

(9:4:51)

When considering the small-signal transconductance of the differential pair we find gmDP (VIN ) ¼

dIOUT IEE VIN ¼ sec h2 dVIN 2VT 2VT

(9:4:52)

which is strongly dependent on the input voltage, as is visualized in Figure 9.4.25. It is not surprising that without any additional measures this voltage dependency of the transconductance significantly limits the input voltage signal handling capability, as is expressed by the input referred voltage IP3 we found earlier in Equation (9.4.18) of ‘‘Two-Tone Excitation.’’ To improve for the voltage handling capability and make the transconductance more linear, multiple differential pairs with DC voltage offsets at their inputs can be combined [18] as shown in Figure 9.4.26. With all voltage offset and tail currents basically free, we obtain the following generalized expression: N X VIN þ Vj (9:4:53) Ij tan h IOUT ¼ 2VT j¼1

Transconductance (AV)

1.0

gm (diff. pair) gm (doublet)

0.8

0.6

0.4

0.2

0.0

−0.2

−0.1

0.0

0.1

0.2

Input voltage (V)

FIGURE 9.4.25 The normalized transconductance of a differential pair and a multi-tanh doublet.

© 2006 by Taylor & Francis Group, LLC

9.4-963

Linearization Techniques

IOUT Q1A

QNA

QjA

VIN Q1B

V1

QjB

Vj

Ij

I1 Stage 1

Stage j

QNB

VN

IN Stage N

FIGURE 9.4.26 A generalized multi-tanh system composed out of several differential pair stages. (From B Gilbert. The multi-tanh principle: a tutorial overview. IEEE J. Solid-State Circ. 33(1), 2–17, 1998. Copyright 1998 IEEE.)

with its related transconductance as gmMT

N X Ij 2 VIN þ Vj ¼ sec h 2VT 2VT j¼1

(9:4:54)

Note that the voltage offsets can be introduced in various ways [18, 19], however, in this chapter we will restrict ourselves to the most well-known implementation; the multi-tanh doublet (N ¼ 2). The doublet uses equal tail currents and introduces the required voltage offsets by combining different active emitter areas of the transistors in a differential pair. The transconductance of the doublet is plotted as function of the input voltage in Figure 9.4.25 for an emitter area ratio of 3.75. This figure shows that the maximum transconductance of the doublet is reduced compared to the differential pair with the same total tail current. However, the transconductance as a whole has become much more constant over a larger input voltage range. The optimum active emitter area ratio for a multi-tanh doublet can be analyzed for a maximum flat behavior of gm and is found to be close to 3.75 [18]. Although elegant in their basic operation, most multi-tanh implementations are based on lowfrequency considerations, which ignore device parasitics like the base and emitter series resistances and junction capacitances. Consequently, when applying the multi-tanh concept at higher frequencies one should carefully verify if for a given application and operating frequency, the multi-tanh concept indeed offers advantages over other design techniques as the resistively or inductively degenerated differential pair. For this reason, we will compare now the performance of the multi-tanh doublet with a resistively and inductively degenerated differential pair at low and high frequencies. We perform this simulation experiment with our SiGe reference device for a voltage driven situation and monitor the fundamental and third-order IMD differential output currents as function of the input voltage amplitude. Figure 9.4.27 shows the circuits used for our comparison, which all operate with the same current budget (ICtot ¼ 1 mA). The area ratio of the multi-tanh doublet is set to 3.75, while the current density of the transistors is kept well below the current of maximum fT (IC ¼ 10 mA for Ae ¼ 10 mm2). The emitter resistance or inductance for the differential pair is chosen in such a way that the resulting small-signal transconductance of the stage at the operating frequency of 5 GHz is equal to that of the multi-tanh doublet. In addition, the active emitter area of the inductively degenerated stage is scaled to the point where v2 CjE LE 1

(9:4:55)

which yields a distortion cancellation condition for the inductively degenerated differential pair due to the factor T(s), which acts on the fundamental frequency (See Equation (9.4.50) for the single-ended case).

© 2006 by Taylor & Francis Group, LLC

9.4-964

The Silicon Heterostructure Handbook

(a)

Iout

Ae Vin

Ae ZE

ZE

IEE

(b)

Iout

Ae1

Ae2

Ae1

Ae2

Vin

IEE /2

FIGURE 9.4.27

IEE /2

(a) The emitter degenerated differential pair stage and (b) the multi-tanh doublet.

The results of this simulation experiment are given in Figure 9.4.28, where the third-order IMD current is plotted as a function of the input voltage amplitude at 5 GHz; and in Figure 9.4.29, where the gain and the voltage IIP3 are plotted as function of frequency. As can be observed from these plots, by far the best results can be obtained at 5 GHz using the inductively degenerated differential pair. The best wide-band performance for the linearity is given by the multi-tanh doublet, while the resistively degenerated differential pair proves to be inferior. Clearly visible in Figure 9.4.29 is the partial distortion cancellation at 5 GHz for the inductively degenerated differential pair, illustrating the relevance of a careful dimensioning of the circuit components involved. Note that the series resistance of the device, rB and rE in combination with the source resistance and ohmic losses of the inductor, will determine how effective the IM3 cancellation is.

Harmonic Matching Techniques Previously, we have examined several techniques based on the linearization of the overall transfercharacteristic, like feedback and the multi-tanh approach. Although effective, these techniques require in general a higher DC power consumption in order to compensate for the loss in gain. In RF circuit design for mobile applications, however, it is quite often desirable to keep the DC power consumption as low as possible to save the battery lifetime, while maintaining useful gain, noise, and linearity specifications. This section presents circuit design techniques that do not compromise the gain and power consumption requirements for increased linearity. These techniques make explicit use of the fact that third-order distortion products are generated in two ways: first, the third-order distortion terms generated directly

© 2006 by Taylor & Francis Group, LLC

9.4-965

Linearization Techniques

−40 −60

Output current (dBI)

−80

Fundamental

−100 −120 −140

3rd-order IMD

IFund (resistive)

−160

IFund (inductive)

−180

IFund (doublet) IIM3 (resistive)

−200

IIM3 (inductive) IIM3 (doublet)

−220 1m

10 m Input voltage (V)

100 m

FIGURE 9.4.28 The fundamental and third-order intermodulation current in dBI as a function of input voltage for the emitter degenerated differential pair and multi-tanh doublet of Figure 9.4.27. f = 5 GHz

−32

20

−34

16

−36

12

−38

IIP3 (dBV)

8 4

gm (inductive)

0

gm (doublet)

−4

gm (resistive)

−40

IIP3 (inductive) IIP3 (doublet) IIP3 (resistive)

−42 −44

−8

−46

−12

−48

−16

−50

−20 108

Transconductance (dB)

24

109 Frequency (Hz)

1010

−52

FIGURE 9.4.29 The transconductance gm in dB and IIP3 in dBV as a function of frequency for the emitter degenerated differential pair and multi-tanh doublet in Figure 9.4.27.

via the third-order nonlinearities; and second, through the indirect mixing of the fundamental and second-order distortion products over the second-order nonlinearities. Third-order Distortion Cancellation Figure 9.4.37 shows the large-signal model of a common-emitter stage, which is used for this analysis. As in the previous discussions, we assume again the exponential current-nonlinearity to be the single dominant source of third-order distortion. However, in contrast to the previous analyses, the base– collector capacitance is taken into account as well, since the condition for distortion cancellation is sensitive to all circuit elements, especially at higher frequencies. The complete analysis for the CE-stage is given in the Appendix, and we will discuss here the most important results.

© 2006 by Taylor & Francis Group, LLC

9.4-966

The Silicon Heterostructure Handbook

Again we assume s s1 s2 and Ds ¼ s1 s2 s, for which the IM3 is expressed as 3 ^s2 IM3 ¼ jH1b (s)j3 jD(s)j j«(Ds,2s)j V 4

(9:4:56)

and consequently, the input referred voltage IP3 is given by sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 4 4 1 jH1c (s2 )j IIP3v ¼ 3 jH3c (s2 , s2 , s1 )j 3 j«(Ds, 2s)j jH1b (s)j3 jD(s)j

(9:4:57)

in which H1b is the linear transfer function relating the source voltage Vs to the internal base–emitter voltage Vbe, which for b >> 1 is given by H1b (s) ¼

1 þ sCbc Zc 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cp Cbc Z

(9:4:58)

where Z ¼ Zb Ze þ Zb Zc þ Ze Zc. The term D(s) linearly relates the third-order nonlinear terms at the base–emitter junction to the collector node and is expressed as D(s) ¼

A(s) 1 1 þ s[CjE (Zb þ Ze ) þ Cbc Zb ] þ s 2 Cbc tZb ¼ H1c (s) gm 1 sCbc (re þ Ze ) s 2 Cp Cbc re Ze

(9:4:59)

Finally, the term «(Ds, 2s) indicates how the second-order interaction influences the total IM3 distortion. This important factor is most conveniently expressed by Equation (9.4.93) in the Appendix and repeated here for convenience: «(Ds,2s) ¼

gm,3 [2F(Ds) þ F(2s)] 3

(9:4:60)

where F(s) ¼

1 2gm (Zb =b þ Ze ) þ s[(CjE 2tgm )(Zb þ Ze ) þ Cbc (Zb þ Zc 2gm Z )] 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cbc Cp Z s 2 Cbc (CjE 2tgm )Z þ 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cbc Cp Z

(9:4:61)

Inspection of Equation (9.4.61) shows that when Zb, Ze, and Zc approach zero, F(s) becomes 1 and the IM3 is completely determined by the direct third-order nonlinearity gm,3 and the fundamental response. In practice this is never the case, due to the finite series resistances in the device and the rather unpractical circuit conditions. Therefore, if we exclude for the moment the influence of «(Ds, 2s), the only practical way to improve IM3 is through inductive emitter degeneration to increase the denominators of H1b(s) and F(s) as we already discussed in ‘‘Negative Feedback Techniques.’’ However, this results in lower gain of the amplifying stage. Therefore, the most effective way to reduce the IM3 is by careful selection of the terminal impedances of the device to enforce cancellation of the direct thirdorder distortion by nullifying F(Ds) and F(2s). Since (9.4.60) is a function of both Ds and 2s, it is rather difficult to find a general solution for these out-of-band impedances. However, several practical implementations have been reported [20–22, 27, 36, 37], which we discuss here in more detail. When using the out-of-band third-order distortion cancellation technique, it is evident from (9.4.56) and (9.4.57) that the term «(Ds, 2s) and consequently F(Ds) and F(2s) are our design equations. We will use a first-order approximation of (9.4.61) to introduce the most practical IM3-cancellation

© 2006 by Taylor & Francis Group, LLC

9.4-967

Linearization Techniques

conditions for a CE-stage. In addition, we will assume for simplicity that Zc(Ds) ¼ Zc(2s) 0 and Ds 0, yielding F(Ds)

1 2gm (Zb =b þ Ze ) 1 þ gm (Zb =b þ Ze )

(9:4:62)

and F(2s)

1 2gm (Zb =b þ Ze ) þ 2s[(Cje 2tgm )(Zb þ Ze ) þ Cbc Zb (1 2gm Ze )] 1 þ gm (Zb =b þ Ze ) þ 2s[(Cje þ tgm )(Zb þ Ze ) þ Cbc Zb (1 þ gm Ze )]

(9:4:63)

Obviously, F(s) is a strong function of the out-of-band impedances Zb and Ze, the transconductance gm ¼ Ic/Vt and the emitter area Ae. We can make F zero by solving the numerator. This gives a continuous set of solutions for the out-of-band impedances. Here we highlight the most relevant solutions with their reference to actual circuit implementations. We perform this exercise by substitution of specific out-of-band terminations at the base and emitter terminal, yielding a simplified expression for «(Ds, 2s). This expression can be used to find the optimum circuit conditions for IM3-cancellation. Doing so, we obtain the following general set of solutions: 1. Setting Ze(Ds) ¼ Ze(2s) 0 (fully grounded emitter) and Zb(Ds) ¼ Zb(2s) ¼ b/2gm [21], yields «(Ds,2s)

2s(CjE þ Cbc 2tgm )rp =3 1 þ 2s(CjE þ Cbc þ tgm )rp =3

(9:4:64)

2. Setting Zb(Ds) ¼ Zb(2s) 0 and Ze (Ds) ¼ Ze(2s) ¼ 1/2gm [22], yields «(Ds,2s)

2s(CjE 2tgm )re =3 1 þ 2s(CjE þ tgm )re =3

(9:4:65)

3. Any combination of Ze(Ds) ¼ Ze(2s) ¼ Re and Zb (Ds) ¼ Zb(2s) ¼ Rb, which fulfills Rb =b þ Re ¼ 1=2gm

(9:4:66)

4. Setting Ze(Ds) ¼ Zb(Ds) 0 [37, 38], yields «(Ds,2s)

1 þ 2s[Cje (Zb þ Ze ) þ Cm Zb ] 1 þ gm (Zb =b þ Ze ) þ 2s[(Cje þ tgm )(Zb þ Ze ) þ Cm Zb (1 þ gm Ze )]

(9:4:67)

which needs a second-harmonic inductive termination at the base and/or emitter to make the numerator zero, similarly to the discussion of 9.4.4 5. Setting Ze (2s) ¼ Zb(2s) 0 [21], yields «(Ds,2s)

1 gm (Zb =b þ Ze ) 1 þ gm (Zb =b þ Ze )

(9:4:68)

which needs a resistive baseband termination at the base and/or emitter node to make the numerator zero. One could argue that choosing any complex impedance at the base and/or emitter node basically yields the same result, however, a purely resistive termination at the baseband and double frequency results in a

© 2006 by Taylor & Francis Group, LLC

9.4-968

The Silicon Heterostructure Handbook

more broadband IM3-cancellation [21]. Furthermore, if the terminations, especially at the baseband, are not resistive; asymmetry can arise in the IM3 sidebands for large envelope frequencies [20]. Therefore, these cases will not be considered in this text. To compare the two main circuit solutions (1 and 2), which are shown in Figure 9.4.30, we will consider the IIP3 as available source power in dBm for Zs(f0) ¼ ZL(f0) ¼ 50. We can calculate this quantity from the voltage referred IIP3 as IIP3P ¼

IIP32V 1 ¼ 3 8R0 6R0 jH1b (s)j jD(s)j j«(Ds,2s)j

(9:4:69)

Low-Frequency IM3-Cancellation To study the IM3-cancellation of our reference transistor, we first plot the low-frequency IIP3 as a function of collector current in Figure 9.4.31 to illustrate the bias dependency of the cancellation condition. The IIP3 is calculated using the simplified model of Figure 9.4.37 (optimized at IC ¼ 1 mA) and simulated with the full Mextram model. As a reference, the IIP3 is plotted for the case where we only have harmonic shorts at the input and the output of the device. For the reference case, cancellation effects occur around 5 mA, which are due to the intrinsic series resistances of the device (rE and rB). The other curve shows a cancellation at 1 mA, for a properly dimensioned emitter resistance (RE ¼ 1/2gm rE). Note that the results are quite accurate around 1 mA, but slightly differ at higher currents approaching the peak-fT value.

RS = RL = 50 RB = 1/(2gm)

ZS(0) = RB ZS(2f0) = RB Ae

ZS(f0) = RS VS

ZE(0) = 0 ZE(f0) = 0 ZE(2f0) = 0

ZL(0) = 0 ZL(f0) = RL ZL(2f0) = 0

(a)

RS = RL = 50 RE = 1/(2gm)

ZS(0) = 0 ZS(2f0) = 0 Ae

ZS(f0) = RS VS

ZE(0) = RE ZE(f0) = 0 ZE(2f0) = RE

ZL(0) = 0 ZL(f0) = RL ZL(2f0) = 0

(b)

FIGURE 9.4.30 The AC equivalent circuit of a CE-stage with out-of-band IM3-cancellation terminations at the (a) base and (b) emitter.

© 2006 by Taylor & Francis Group, LLC

9.4-969

Linearization Techniques

20 15

IIP3 (dBm)

10 5

IIP3 (mextram) IIP3 (mextram) IIP3 (calculated) IIP3 (calculated) f T (mextram)

RE =10.4 W

70G 60G 50G

f T (calculated)

Effects of rE and rB

0

40G

fT (Hz)

25

30G

−5 −10

20G

−15

10G

−20 100 µ

1m Collectr or current (A)

10 m

0

FIGURE 9.4.31 The cut-off frequency fT and low-frequency IIP3 as a function of collector current with proper resistive out-of-band terminations in the base or emitter of a CE-stage and with these terminations set to zero.

To understand the differences between out-of-band tuning at the emitter and the base terminal, Figure 9.4.32 plots the IIP3 as a function of fundamental frequency for both cases. Apparently, applying the harmonic tuning in the emitter gives a linearity improvement over a much broader bandwidth even when no high-frequency IM3-cancellation is applied. This is because «(Ds, 2s) has a pole around 3 2 vT =bf according to (9.4.64), when the device is properly terminated for IM3-cancellation at its base terminal. While according to (9.4.65) a pole around 32 vT exists, when the device is properly terminated for IM3-cancellation at its emitter terminal. Note that this latter pole is negligible, since it lies far beyond the frequency of operation of the device. Since the IIP3 is proportional to «(Ds, 2s)1, these poles translate to zeros in the IIP3 versus frequency plot. The fact that proper IM3termination at the emitter gives a more broadband improvement, can also be explained by considering the transistor as a common-base stage for the even-harmonic frequencies like we have discussed previously in section ‘‘Analysis of a CB-Stage in Current-Mode.’’ High-Frequency IM3-Cancellation In the previous situations we observed that IM3-cancellation becomes less effective at higher frequencies. This linearity degradation can be explained by the increased influence of the total base charge (Cbe þ Cbc). We can compensate for this in various ways. Assuming that Zc is truly zero, we can improve for the high-frequency linearity by choosing the optimum transconductance or by optimum scaling of the emitter area in (9.4.64) or (9.4.65) to satisfy gm,opt ¼

CjE þ Cbc 2tf

(9:4:70)

Note that Rb or Re need adjustment if we choose to modify gm to satisfy (9.4.70), rather than to change the active emitter area. Figure 9.4.33 shows that in case we terminate the emitter correctly for the lowfrequency IM3-cancellation condition, fulfilling (9.4.70) also yields an effective IM3-cancellation at very high frequencies. As became clear from our previous exercise, IM3-cancellation techniques at higher frequencies rely on the small details of the design, which at first sight, seem to be irrelevant for the basic circuit performance in terms of gain and noise. However, as shown above, it works out that these details can trigger major

© 2006 by Taylor & Francis Group, LLC

9.4-970

The Silicon Heterostructure Handbook

1.5 f T/bf

20 15

RE = 10.4 Ω RB = 0 Ω

10 IIP3 (dBm)

5 0

RE = 0 Ω

−5

IIP3 (mextram) IIP3 (calculated)

−10 −15 −20

RB = 2740 Ω

RE = RB = 0 Ω

106

107

108 109 Frequency (Hz)

1010

1011

FIGURE 9.4.32 The IIP3 as a function of frequency for the CE-stages in Figure 9.4.30 with proper out-of-band terminations in the base and the emitter and with both these terminations set to zero. 25 Ae = 0.7 (RE = 8.3 Ω)

IIP3 (dBm)

20

Ae = 1.0 (RE = 10.4 Ω)

15

HF IM3cancellation

10

5

0 106

107

108 109 Frequnecy (Hz)

1010

1011

FIGURE 9.4.33 High-frequency IM3-cancellation for the CE-stage in Figure 9.4.30b with proper out-of-band terminations in the emitter.

improvements of the circuit linearity, even at high frequencies and low DC powers. For this reason, basic understanding of nonlinear distortion phenomena in bipolar circuits is mandatory for the reliable implementation of highly linear power-efficient circuit blocks. This understanding goes hand in hand with accurate models for the active, as well as the passive devices models. To illustrate the potential of the proposed design techniques we will now briefly discuss two practical implementations. Practical Examples From the previous analysis, it is obvious that terminating the base or emitter impedance correctly at the baseband and second-order frequency gives the best trade-off in gain, linearity, and DC power consumption. Two practical circuit examples, in which these techniques were used are given in Ref. [22]

© 2006 by Taylor & Francis Group, LLC

9.4-971

Linearization Techniques

for a down-conversion double-balanced active mixer and in Ref. [38] for an LNA where we simultaneously match for noise, impedance, and IIP3 at low DC-power consumption. Figure 9.4.34 shows the double-balanced active mixer design which is operated from a 2.7 V DC supply and consumes approximately 2.2 mA current at 2.1 GHz. The mixer is designed with proper out-of-band impedance at the common-mode node of the emitter terminal according to case 2 in the previous subsection. In Ref. [22], the linearity of the mixer with third-order cancellation is compared to a multi-tanh input stage that is not terminated with proper second-harmonic terminations. The IIP3 of the mixer is approximately 10 dB better than the linearity of the multi-tanh stage. This is in agreement with the results in ‘‘Shaping the Transfer Function’’ where we have seen similar linearity improvements, when comparing the transconductance linearity of the doublet to a inductively degenerated differential pair fulfilling the IM3-cancellation condition. Figure 9.4.35 shows an example of a current-feedback LNA operating from a 1.5 V DC supply consuming 2.5 mA current at 900 MHz [38]. In this design the IM3-cancellation is implemented according to case 4, presented earlier. By applying a proper inductive second-harmonic source termination, an improvement of approximately 15 dB in terms of IIP3 has been obtained compared to the case without this second-harmonic termination, while gain, noise, impedance match, and bias were not compromised by the use of out-of-band matching techniques. Vcc

LO bias

+ IF −

+ LO − + RF − Short Cc @2ω Lc

Short@dc Mixer bias Re

FIGURE 9.4.34 Down-conversion double-balanced active mixer with third-order cancellation impedance in the emitter and second-harmonic shorts in the base. (From Liwei Sheng and L.E. Larson. An Si–SiGe BiCMOS directconversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications. IEEE Trans. Microwave Theory Techn. 51(11), 2211–2220, 2003.) Copyright 2003 IEEE. VCC

VBB ML1 ZX

RFin

C2

ZS(ω) ZS(2ω)

w1

L1

C3

w2

C1 ML3

RFout

l < λ/10 CPML1

ML2 BFG425W

C4

R1

Le CN Via inductance

CF-transformer

FIGURE 9.4.35 Low-noise amplifier with simultaneous noise, impedance, and IIP3 match. (From M.P. van der Heijden, L.C.N. de Vreede, F. van Straten, and J.N. Burghartz. A high performance unilateral 900 MHz LNA with simultaneous noise, impedance, and IP3 Match. Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 45–48, September 2003.) Copyright 2003 IEEE.

© 2006 by Taylor & Francis Group, LLC

9.4-972

The Silicon Heterostructure Handbook

Figure 9.4.36 shows an example of a InGaP HBT differential driver stage operating from a 3 V DC supply and consumes 30 mA current at 2.0 GHz [39]. In this design the IM3-cancellation is implemented according to case 1 in the previous subsection. By applying a proper resistive second-harmonic common-mode source termination, an improvement of approximately 20 dB in terms of IM3 has been obtained up to the 1 dB output power compression point, compared to the case without this second-harmonic termination. Discussion It is clear that the proper use of out-of-band terminations for improved linearity is more demanding for the designer than the previously discussed techniques. This is mainly caused by the fact that the device matching conditions not only have to be fulfilled for the fundamental, but also for the out-of-band frequencies. Although perfect IM3-cancellation conditions for the active device are sometimes difficult to implement, suboptimum solutions already provide sufficient linearity advantages (e.g., the cascode LNA in ‘‘Cascode LNA Design’’). When considering differential topologies, the orthogonal behavior of the even- and odd-distortion components, facilitate a straightforward implementation of ‘‘even’’ out-ofband terminations through the use of the center tap [21, 22], which acts as a virtual ground for the ‘‘odd’’ fundamental. Note that the larger number of design variables translates itself to more design freedom and therefore facilitates superior amplifier stages that make no compromise whatsoever in gain, noise, impedance matching, and linearity performance, while operating at lowest DC power consumption possible [37, 38]. Consequently, the best values currently reported for the dynamic

VBB

VCC Q1 Q3

CS,CM

+

+

CL,CM

PIN C T1

CT2

−

RS,CM

POUT −

Q4 Q2

0

24 23 GP RS,CM = b F/4gm)

20

−20 −30

20 dB

19 18

−40

RS,CM = 0

17

IM3Lo

16

IM3Hi

14

IM3Lo

RS,CM = b F/4gm

15 0

2

4

6

8 10 12 14 output power (dBm)

IM3 (dBc)

21 Power gain (dB)

−10

GP (RS,CM = 0)

22

−50 −60

IM3Hi 16

18

20

−70 22

FIGURE 9.4.36 Measured power gain and IM3 versus output power of a 2 GHz InGaP HBT unilateral differential driver stage operating from VCC ¼ 3 V and IC ¼ 30 mA. (From MP van der Heijden, M Spirito, LCN de Vreede, F van Straten, and JN Burghartz. A 2 GHz high-gain differential InGaP HBT driver amplifier matched for high IP3. IEEE MTT-S Digest 1, 235–238, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.4-973

Linearization Techniques

range figure-of-merit [38] are designs using out-of-band terminations. Based on this observation, we expect that future bipolar RF front-end designs will be implemented with some form of third-order distortion cancellation technique in the first stages of the receiving chain, followed by current-mode based designs for the subsequent stages.

Appendix To investigate the influence of the externally applied impedances on the linearity of a common-emitter stage, we performed a Volterra series analysis as described in Refs. [3, 4] using the large-signal equivalent circuit of Figure 9.4.37. All relevant parameters for our circuit analysis are obtained from the Mextram model of our reference transistor with a peak fT of 70 GHz at 10 mA. The parameters below have been extracted at IC ¼ 1 mA ( fT 35 GHz) and are given by: . . . . . . . .

The The The The The The The The

base–emitter depletion capacitance CjE ¼ 11 fF collector–base depletion capacitance Cbc ¼ 20 fF collector–substrate depletion capacitance CCS ¼ 5.8 fF forward base–emitter transit timey tf ¼ 0.8 psec forward current-gain bf ¼ 350 base resistance rB ¼ 15 V emitter resistance rE ¼ 2.35 V collector resistance rC ¼ 15 V

For the low-current operation of the device, we assume the exponential input-voltage-to-current relation to be the dominant nonlinearity. Consequently, we write for the collector current iC ¼ IS exp (y BE =VT )

(9:4:71)

and approximate this function with a third-order power series ic ¼ gm y be þ gm2 y 2be þ gm3 y 3be

(9:4:72)

in which the Taylor coefficients at the DC-collector current IC are given by gm ¼

IC , VT

rB

IC IC , gm,3 ¼ 2VT2 6VT3

Cbc

Vb

ZS Vs

gm,2 ¼

Zb CjE

iB

CDE Ve

rC

Vc

iC

rE

ZL CCS

Zc ZE

FIGURE 9.4.37

(9:4:73)

Ze

Large-signal model of a CE-stage with only exponential nonlinearities.

y

For our distortion calculations we need the ‘‘pure’’ base–emitter transit time for the base–emitter diffusion capacitance and not the more common total delay time, which includes all delays.

© 2006 by Taylor & Francis Group, LLC

9.4-974

The Silicon Heterostructure Handbook

The base current ib and the base–emitter diffusion current are both linearly related to ic via the current gain bf and the transit time tf, which are both assumed to be constant. ib ¼

ic bf

iCDE ¼ tf

d ic dt

(9:4:74) (9:4:75)

Furthermore, the base–emitter depletion capacitance is considered to be constant as well, since its nonlinearity is small in comparison with the nonlinearity of the base–emitter diffusion capacitance CDE. The linear transfer function, which relates the source voltage Vs to the internal base–emitter voltage Vbe, is given by H1b (s) ¼

Vbe 1 þ sCbc Zc ¼ Vs 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cp Cbc Z

(9:4:76)

in which Z ¼ Zb Ze þ Zb Zc þ Ze Zc and Cp ¼ CjE þ CDE with CDE ¼ tf gm. The overall linear transfer function relating the source voltage Vs to the internal collector voltage Vc is given by H1c (s) ¼

Vc ¼ Hbc (s)H1b (s) Vs

(9:4:77)

in which Hbc is the linear transfer function relating the base–emitter voltage to the collector voltage: Hbc (s) ¼

Vc Zc gm ¼ [1 sCbc (re þ Ze ) s 2 Cp Cbc re Ze ] Vbe 1 þ sCbc Zc

(9:4:78)

Following Ref. [3], the second-order nonlinear transfer function can be expressed as H2c (s1 , s2 ) ¼ gm,2 H1b (s1 )H1b (s2 )A(s1 þ s2 )

(9:4:79)

in which A(s) relates the nonlinear terms at the base–emitter junction to the collector node and is given by A(s) ¼

Zc (1 þ s[CjE (Zb þ Ze ) þ Cbc Zb ] þ s 2 Cbc tZb ) 1 þ gm (Zb =bf þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cp Cbc Z

(9:4:80)

and the third-order nonlinear transfer function can be expressed as H3c (s1 , s2 , s3 ) ¼ «(s1 , s2 , s3 )H1b (s1 )H1b (s2 )H1b (s3 )A(s1 þ s2 þ s3 )

(9:4:81)

2 «(s1 , s2 , s3 ) ¼ gm,3 gm2 ,2 [B(s1 þ s2 ) þ B(s1 þ s3 ) þ B(s2 þ s3 )] 3

(9:4:82)

Zb =bf þ Ze þ s[t(Zb þ Ze ) þ Cbc Z ] þ s 2 Cbc t Z 1 þ gm (Zb =bf þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cp Cbc Z

(9:4:83)

where

in which B(s) ¼

© 2006 by Taylor & Francis Group, LLC

9.4-975

Linearization Techniques

For a two-tone excitation s1 ¼ s3 ¼ jv1 and s2 ¼ jv2. We calculate IM3 assuming a small tone-spacing to keep our equations compact, s1 s2 s and Ds ¼ s1 s2 << s : 3 H3 (s1 ,s1 , s2 ) ^ 2 3 ^s2 V j«(Ds, 2s)j jH1b (s)j3 jD(s)j V IM3LO ¼ c 4 H1c (2s1 s2 ) s 4 3 H3c (s2 , s2 , s1 ) ^ 2 3 ^s2 V j«(Ds, 2s)j jH1b (s)j3 jD(s)j V IM3HI ¼ 4 H1c (2s2 s1 ) s 4

(9:4:84) (9:4:85)

where D(s) ¼

A(s) 1 1 þ s[CjE (Zb þ Ze ) þ Cbc Zb ] þ s 2 Cbc tZb ¼ H1c (s) gm 1 sCbc (re þ Ze ) s 2 Cp Cbc re Ze

(9:4:86)

and 2 «(Ds, 2s) ¼ gm,3 gm2 ,2 [2B(Ds) þ B(2s)] 3

(9:4:87)

ˆ s at which IM3 Having the expression for IM3, we can calculate the amplitude of the input signal tones V ¼ 1, which is the input referred third-order intercept point (IIP3): sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 4 jH1c (s2 )j 4 1 IIP3 ¼ 3 jH3c (s2 , s2 , s1 )j 3 j«(Ds, 2s)j jH1b (s)j3 jD(s)j

(9:4:88)

The output referred third-order intercept point OIP3 can be calculated by multiplying the IIP3 by the overall linear transfer function H1c(s) at the fundamental frequency: sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 4 jH1c (s2 )j3 4 jHbc (s)j3 OIP3 ¼ 3 jH3c (s2 , s2 , s1 )j 3 j«(Ds, 2s)j jA(s)j

(9:4:89)

The factor «(Ds, 2s) determines how the out-of-band impedances at the baseband and double frequencies influence the total third-order intermodulation distortion. This factor can be expressed in various ways in order to give more insight in how certain circuit parameters influence its behavior. Therefore, we first substitute the nonlinear Taylor coefficients of (9.4.73) in (9.4.87), yielding: «(Ds, 2s) ¼

gm [1 2gm B(Ds) gm B(2s)] 6VT2

(9:4:90)

which we can can rewrite in the following form: «(Ds, 2s) ¼

gm 1 E(2s) 1 E(Ds) þ 2 3VT2

(9:4:91)

where E(s) ¼

1 þ s[CjE (Zb þ Ze ) þ Cbc (Zb þ Zc )] þ s 2 CjE Cbc Z 1 þ gm (Zb =bf þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cp Cbc Z

(9:4:92)

Equation (9.4.92) clearly shows the interaction of the total series impedance connected to the device with the depletion capacitances. This form will be extensively used in ‘‘Negative Feedback Techniques.’’ Another way of writing «(Ds, 2s) is given by

© 2006 by Taylor & Francis Group, LLC

9.4-976

The Silicon Heterostructure Handbook

«(Ds, 2s) ¼

gm [2F(Ds) þ F(2s)] 18VT2

(9:4:93)

where F(s) ¼

1 2gm (Zb =b þ Ze ) þ s[(CjE 2tgm )(Zb þ Ze ) þ Cbc (Zb þ Zc 2gm Z )] 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cbc Cp Z s 2 Cbc (CjE 2tgm )Z þ 1 þ gm (Zb =b þ Ze ) þ s[Cp (Zb þ Ze ) þ Cbc (Zb þ Zc þ gm Z )] þ s 2 Cbc Cp Z

(9:4:94)

This form will be used to describe the IM3 cancellation conditions in ‘‘Harmonic Matching Techniques’’ since it clearly shows the low- and high-frequency circuit conditions for having broadband IM3cancellation.

Acknowledgments We would like to thank the TU Delft for giving the opportunity to conduct research in this field for many years and Philips Research and Philips Semiconductors for their steady encouraging support over many years. In addition we would like to acknowledge Agilent Technologies for software support in terms of MDS, ADS, and ICCAP, as well as BSW and Maury Microwave for their cooperation on large signal measurements. We would like to personally thank Rik Jos and Peter Deixler for their support. Finally, out special thanks to H. C. de Graaff for his very solid and encouraging mentorship over the past few years.

References 1. JCJ Paasschens and WJ Kloosterman. The Mextram bipolar transistor model, level 504. Unclassified Report NL-UR 2000/811, Philips National Laboratory, available at http://www.semiconductors. philips.com/Philips_Models/bipolar/mextram/ 2. B Razavi. RF Microelectronics. Upper Saddle River, NJ: Prentice-Hall, 1998. 3. P Wamback and W Sansen. Distortion Analysis of Analog Integrated Circuits. Dordrecht: Kluwer Academic Publishers, 1998. 4. SA Maas. Nonlinear Microwave and RF Circuits. 2nd edition. Norwood, MA: Artech House, 2003. 5. PR Gray and RG Meyer. Analysis and Design of Analog Integrated Circuits. 3rd edition. New York: Wiley, 1993. 6. ML Lantz. Systematic Design of Linear Feedback Amplifiers. PhD dissertation, Lund University, Lund, Sweden, 2002. 7. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston: Artech House, 2003. 8. LCN de Vreede, HC de Graaff, K Mouthaan, M de Kok, JL Tauritz, and RGF Baets. Advanced modelling of distortion effects in bipolar transistors using the Mextram model. Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 48–51, October 1994. 9. LCN de Vreede, HC de Graaff, JL Tauritz, and RGF Baets. Extension of the collector charge description for compact bipolar epilayer models. IEEE Trans. Elect. Dev. 45, 277–285, 1998. 10. M Schroter, DR Pehlke, and T-Y Lee. Compact modeling of high-frequency distortion in silicon integrated bipolar transistors. IEEE Trans. Elect. Dev. 47(7), 1529–1535, 2000. 11. EH Nordholt. Design of High-Performance Negative Feedback Amplifiers. Elsevier, 1983. 12. LCN de Vreede, HC de Graaff, JA Willemen, W van Noort, HFF Jos, LE Larson, JW Slotboom, and JL Tauritz. Bipolar transistor epilayer design using the MAIDS mixed-level simulator. IEEE J. SolidState Circ. 34(9), 1331–1338, 1999.

© 2006 by Taylor & Francis Group, LLC

Linearization Techniques

9.4-977

13. LCN de Vreede, HC de Graaff, and B Rejeai. The effect of non-saturated electron drift velocity on bipolar device linearity. In: Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 88–91, September 2002. 14. HC de Graaff and FM Klaasen. Compact Transistor Modeling for Circuit Design. New York: SpringerVerlag, 1990. 15. C Toumazou, FJ Lidgey, and DG Haigh (Eds). Analogue IC Design: the Current-Mode Approach. IEE Circuits and Systems Series 2. London: Perigrinus, 1990. 16. Keng Leong Fong and RG Meyer. High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages. IEEE J. Solid-State Circ. 33(4), 548–555, 1998. 17. Adiseno, M Ismail, and H Olsson. A wide-band RF front-end for multiband multistandard highlinearity low-IF wireless receivers. IEEE J. Solid-State Circ. 37(9), 1162–1168, 2002. 18. B Gilbert. The multi-tanh principle: a tutorial overview. IEEE J. Solid-State Circ. 33(1), 2–17, 1998. 19. K Kimura. The ultra-multi-tanh technique for bipolar linear transconductance amplifiers. IEEE Trans. Circ. Systems I. 44(4), 288–302, 1997. 20. V Aparin and C Persico. Effect of out-of-band terminations on intermodulation distortion in common-emitter circuits. IEEE MTT-S Digest 3, 977–980, 1999. 21. MP van der Heijden, HC de Graaff, and LCN de Vreede. A novel frequency-independent third-order intermodulation distortion cancellation technique for BJT amplifiers. IEEE J. Solid-State Circ. 37(9), 1176–1183, 2002. 22. Liwei Sheng and LE Larson. An Si–SiGe BiCMOS direct-conversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications. IEEE Trans. Microwave Theory Techn. 51(11), 2211–2220, 2003. 23. SC Cripps. RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 1999. 24. WD van Noort, LCN de Vreede, HFF Jos, LK Nanver, and JW Slotboom. Reduction of UHF power transistor distortion with a nonuniform collector doping profile. IEEE J. Solid-State Circ. 36(9), 1399–1406, 2001. 25. F van Rijs, R Dekker, HA Visser, HGA Huizing, D Hartskeerl, PHC Magnee, and R Dondero. Influence of output impedance on power added efficiency of Si-bipolar power transistors. IEEE MTT-S Digest, 1945–1948, 2000. 26. M Spirito, LCN de Vreede, LK Nanver, S Weber, and JN Burghartz. Power amplifier PAE and ruggedness optimization by second-harmonic control. IEEE J. Solid-State Circ. 38(9), 1575–1583, 2003. 27. MP van der Heijden, M Spirito, M Pelk, LCN de Vreede, and JN Burghartz. On the optimum biasing and input out-of-band terminations of linear and power efficient class-AB bipolar RF amplifiers. Proceedings of the 2004 Bipolar/BiCMOS Circuits and Technology Meeting, September 2004. 28. J Reynolds. Nonlinear distortions and their cancellation in transistors. IEEE Trans. Elect. Dev. 12, 595–599, 1965. 29. S Aggarwal, A Daanen, M Locher, AL Landesman, M Judson, F Garrigues, M Bracey, H Xu, O Charlon, and M Gao. A highly integrated dual-band triple-mode transmit IC for cellular CDMA2000 applications. IEEE J. Solid-State Circ. 38, 1561–1569, 2003. 30. B Gilbert. The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric class-AB input stage. IEEE J. Solid-State Circ. 32(9), 1412–1423, 1997. 31. P Antognetti and G Massobrio. Semiconductor Device Modeling with SPICE. New York: McGrawHill, 1987. 32. CJM Verhoeven, A van Staveren, GLE Monna, MHL Kouwenhoven, and E Yildiz. Structured Electronic Design. Dordrecht: Kluwer Academic Publishers, 2003. 33. R van den Brink. Low-Noise Wideband Feedback Amplifiers. PhD dissertation, Delft University of Technology, Delft, The Netherlands, 1994. 34. EM Cherry and DE Hooper. Amplifying Devices and Low-Pass Amplifier Design. New York: John Wiley and Sons, 1968.

© 2006 by Taylor & Francis Group, LLC

9.4-978

The Silicon Heterostructure Handbook

35. SP Voinigescu, MC Maliepaard, JL Showell, GE Babock, D Marchesan, M Schroter, P Schvan, and DL Harame. A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid-State Circ. 32, 1430–1439, 1997. 36. Keng Leong Fong. High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network. IEEE J. Solid-State Circ. 35(8), 1249– 1252, 2000. 37. V Aparin, E Zeisel, and P Gazzerro. Highly Linear SiGe BiCMOS LNA and Mixer for Cellular CDMA/AMPS Applications. Proceedings of 2002 IEEE RFIC, pp. 129–132, June 2002. 38. MP van der Heijden, LCN de Vreede, F van Straten, and JN Burghartz. A high performance unilateral 900 MHz LNA with simultaneous noise, impedance, and IP3 Match. Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 45–48, September 2003. 39. MP van der Heijden, M Spirito, LCN de Vreede, F van Straten, and JN Burghartz. A 2 GHz high-gain differential InGaP HBT driver amplifier matched for high IP3. IEEE MTT-S Digest 1, 235–238, 2003.

© 2006 by Taylor & Francis Group, LLC

9.5 SiGe MMICs 9.5.1

Introduction............................................................... 9.5-979 Motivation: SiGe versus III–V MMICs . SiGe MMICs: What They Can and Cannot Do

9.5.2 9.5.3

The Substrate Issue.................................................... 9.5-981 SiGe MMICS Using Heterojunction Bipolar Transistors .................................................................. 9.5-983

9.5.4

SiGe MMICS Using Heterostructure Field-Effect Transistors .................................................................. 9.5-994 Summary .................................................................... 9.5-995

Narrow-Band Circuits . Wide-Band Circuits

Hermann Schumacher University of Ulm

9.5.5

9.5.1 Introduction Often overlooked amid the spectacular advances in digital VLSI, monolithic microwave integrated circuits (MMICs) are crucial building blocks of modern wireless communications systems. Combining passive and active components of microwave circuits onto a single semiconductor substrate not only dramatically reduces size and weight, and eliminates the harmful effects of wire interconnects, but also reduces the cost and effort associated with assembly and most notably the manual pruning still very common in microwave subsystem assembly. In the context of this chapter, the definition of MMICs will be extended to include very wideband components commonly used in the analog portion of fiber-optic communications systems, e.g., the wide-band low-noise amplifier following the photodetector. These circuits use circuit design techniques very similar to microwave circuits in the narrower sense, and may find use also in microwave applications requiring multi-octave performance, such as in instrumentation and surveillance applications. The discussion of MMICs using Si–SiGe heterostructure transistors will start with a brief comparison with its counterparts fabricated on III–V semiconductor substrates. It is important to understand that SiGe MMICs, while a very interesting option in many cases, are not a ‘‘cure-all’’ technology. They perform best and are most convincing when designed with its inherent limitations in mind. Probably, the first issue that comes to mind when comparing Si and GaAs as materials for microwave circuits is the significantly higher loss encountered in Si substrates. The substrate issue hence deserves special treatment, and we will see that it is addressed not so much through substrate modifications, but through appropriate circuit design which has the added advantage of significantly reducing the chip size required for certain functions. While SiGe heterojunction bipolar transistors (HBTs) are at the time of this writing the only commercially available device technology and deserve most of the attention, SiGe heterostructure field-effect transistors (HFETs) are a topic of intense research whose suitability for MMICs has already been demonstrated experimentally. Therefore, a brief section will treat SiGe HFET circuits as well.

9.5-979 © 2006 by Taylor & Francis Group, LLC

9.5-980

The Silicon Heterostructure Handbook

Motivation: SiGe versus III–V MMICs Monolithic microwave integrated circuits have been realized in the past primarily using III–V semiconductor technologies, predominantly GaAs. GaAs-based MMICs still have performance advantages, which are mostly derived from the significantly higher low-field electron mobilities of GaAs and InGaAs, the higher saturation velocity of electrons at medium electric fields, and the higher breakdown fields. The issue of the semiinsulating GaAs substrate, versus mostly conducting substrates for Si, will be dealt with in Section 9.5.2. The main motivation for trying to replace III–V MMICs with Si-based circuits is cost. If the expected market volume for a given microwave application is large, Si–SiGe MMICs can be significantly cheaper than their III–V competitors, predominantly due to the much larger wafer sizes and the industrially very mature manufacturing technology. For small quantities, the advantage is not so clear — especially for large wafer sizes (>6 in.) and BiCMOS technologies, mask costs can be an order of magnitude higher than for typical III–V MMIC processes. An often overlooked point is that testing and packaging tend to render the cost ratios between Si and GaAs ICs considerably less impressive for the packaged products.

SiGe MMICs: What They Can and Cannot Do Comparing SiGe and GaAs MMICs, one realizes that another difference is in the circuit complexity, in the number of individual functions integrated on a single chip, and in the total chip size. GaAs MMICs cannot deny their descent from hybrid microwave integrated circuits (MICs), which combine a few active devices with planar transmission line structures, which also implement the necessary reactances (e.g., open-ended stubs as shunt capacitors). In doing so, the designer can rely on a vast body of microstrip and coplanar models. Due to the high substrate resistivity available in GaAs (about 107 V cm), designs can be easily transferred from nonsemiconducting substrates (e.g., alumina) to the monolithically integrated circuit. The resulting ICs are rather large in size (5 to 15 mm2) and sparsely populated by active devices. The designer of silicon MMICs, including Si–SiGe, will often have to live with substrate resistivities ranging from 20 V cm to may be 1000 V cm. Long transmission line segments would result in intolerable loss in the substrate. The Si MMIC designer will hence resort to realizing reactances using lumped passive elements, wherever possible, predominantly metal–insulator–metal (MIM) capacitors and spiral inductors. The latter still receive considerable research attention (see e.g., Ref. [1]). Longer transmission line segments are avoided, leading to very compact designs with a smaller chip area (sometimes <1 mm2) and a considerably higher density of active devices (capacitors and inductors will still dominate the area consumed, though). Integration density and the high yield of mature silicon processes make MMICs with a high number of integrated functions possible. This is also true for Si–SiGe HBT technologies that differ from all-Si processes only in the base design. Figure 9.5.1, which shows a chip photograph of an eight-channel receiver array for 24 GHz monolithically integrated in a Si–SiGe BiCMOS technology [2], shall serve as an example. In SiGe HFETs, the deviation from standard Si processing is larger, and this explains the lag in commercialization there. Integration density is assisted by another often overlooked difference between GaAs and Si substrates: the thermal conductivity of Si is about three times higher than for GaAs (1.45 W K1 cm1 versus 0.46 W K1 cm1), which makes the thermal management of densely placed active devices considerably easier and prevents the formation of ‘‘hot spots’’ on the IC. As pointed out in Ref. [3] for InP–InGaAs–InP DHBTs, the power dissipated in the collector region of high-speed bipolar transistors increases with the square of the transistor operational bandwidth. For the investigated InP-based HBTs, significant temperature increases were observed in simulation if an InGaAs etch-stop layer of only 50 nm thickness was present. SiGe HBTs should fare much better in this respect. Raw device speed is no longer an issue in Si-based MMIC design. Si–SiGe HBT technologies with transit frequencies up to 350 GHz have been demonstrated [4], rivaling state-of-the-art results reported in III–V technologies. The focus of attention shifts toward compact ICs combining many analog and

© 2006 by Taylor & Francis Group, LLC

9.5-981

SiGe MMICs

3.5 mm

1-Channel phase selector

LO phase distribution 16-phase oscillator Frequency synthesizer

Biasing circuitry

3.3 mm

1 RF channel (LNA + mixer)

IF mixers and BB Amps

FIGURE 9.5.1 Chip photo of an eight-channel phased array receiver for 24 GHz in a SiGe BiCMOS technology, demonstrating the level of complexity possible in Si-based MMICs. (After H. Hashemi, X. Guan, and A. Hajimiri. ISSCC 2004, San Francisco, CA, February 15–18, 2004, with permission.)

some digital (e.g., frequency dividers) onto a single chip. It shall not be overlooked though that III–V MMICs continue to have an edge in performance: the high low-field electron velocity translates into lower noise figures, while the higher average electron velocity at medium electric fields coupled with the higher breakdown fields lead to significantly higher breakdown voltages in III–V semiconductor devices, if we compare devices with the same fT. Excellent application opportunities for Si–SiGe MMICs are hence given if . . .

There is a significant market potential in terms of volume or Multi-functionality on a single chip provides clear benefits and Ultimate performance is not required

9.5.2 The Substrate Issue In much of the early work on Si-based microwave and millimeter-wave integrated circuits, substrates with very high resistivity (e.g., 105 V cm) have been used [5]. These substrates have dielectric properties comparable to semi-insulating GaAs substrates (which have resistivities >106 V cm), allowing the direct transfer of established MMIC design techniques from GaAs to Si substrates. These designs make heavy use of transmission line segments in the realization of reactances, phase adjustment, and impedance transformation and hence depend on low-loss substrates. However, these high-resistivity substrates suffer a decrease in resistivity after high-temperature processing steps. They became only very recently commonly available in commercial bipolar and CMOS processes. Additionally, the SiO2–Si interface on top of the substrate deserves very careful attention — frequently, parasitic surface inversion channels form in high-resistivity Si substrates, leading to strong fluctuations in the loss observed in transmission lines and spiral inductors. The common use of channel stopper implants defeats the purpose of having a high-resistivity substrate and has to be avoided here. Hence, most Si MMICs reported today employ either low- or medium-resistivity Si substrates (1 to 50 V cm). The use of transmission lines is reduced in favor of concentrated reactances — predominantly spiral inductors and metal–insulator–metal (MIM) capacitors. As an added benefit, the resulting layout is necessarily very compact, leading to a further cost benefit over typical GaAs-based MMICs using transmission-line segments. On the other hand, extension of the concept to the upper microwave and

© 2006 by Taylor & Francis Group, LLC

9.5-982

The Silicon Heterostructure Handbook

the millimeter-wave range needs substantial effort in the characterization of passive structures and layout effects. Where distributed structures have to be used on low- and medium-resistivity substrates, they can be modeled as either quasi-thin-film microstrip or lossy-conductor-backed coplanar waveguides [6]. Thinfilm microstrip lines require vias to the substrate, while coplanar waveguides require additional space on chip for the ground metallization. In either case, the Si substrate serves as a lossy backplane. Strong dispersion (slow-wave effects) may exist at low frequencies, while at higher frequencies dispersion is tolerable (see Figure 9.5.2). Observed loss would be prohibitive, for example, quarter-wave impedance transformers, but are adequate for interconnects in typical dense MMICs. A common feature of Si-based MMICs is the significant part of the chip real estate consumed by spiral inductors. An often-used small-signal equivalent circuit for spiral inductors on lossy Si substrates is shown in Figure 9.5.3(a). The shunt elements at input and output model the capacitive coupling to the lossy substrate, while the frequency-dependent series resistance models the increase in metal resistance with increasing frequency due to the skin effect. More rigorous models may also include the effect of Eddy currents in the substrate (see e.g., Ref. [1]). An interesting observation is that when moving into the millimeter-wave domain, practical spiral inductors can be modeled using simpler equivalent circuits (see Figure 9.5.3(b)). This is due to two separate effects: . .

With increasing frequency, series resistance losses dominate due to the skin effect. As the frequency of operation increases, the necessary inductance in tuned circuits decreases proportionately. As a useful rule-of-thumb, the necessary impedance of a spiral inductor is in the same order of magnitude as the characteristic impedance of MMIC transmission lines, typically less than 90 V, which leads to a practical value of approximately 15 nH GHz for the product of inductance and frequency of operation. As an example, required inductor values at 24 GHz are a few tenths of a nano-Henry. With decreasing electrical value, the inductor geometry also shrinks, leading to a markedly decreased interaction with the lossy substrate.

Attenuation (dB mm−1),(√e r,eff)

Metal–insulator–metal capacitors are less critical in the frequency dependence of their impedance than spiral inductors, but may exhibit a parasitic series resistance LS in their equivalent circuit, depending on the geometric shape (see Figure 9.5.4). The series resistance RS can be substantial if the bottom electrode is not an Al interconnect level, but a silicide contact. In any case, the bottom electrode will have a nonnegligible capacitance to the lossy substrate.

4 3 √er,eff

MSL

2 CPW

1 0

Attenuation 0

2

4

6

8

10

12

14

16

18

20

Frequency (GHz)

FIGURE 9.5.2 Measured attenuation and slowing factor for 4.2-mm wide microstrip (MSL — dashed curves) and coplanar transmission lines (CPW — solid curves) on 20 V cm silicon substrate. (After W. Du¨rr, U. Erben, A. Schu¨ppen, H. Dietrich, and H. Schumacher. IEEE Trans. Microwave Theory Tech. 46, 712–715, 1998. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.5-983

SiGe MMICs

(a)

CP Rs(f )

L

Cox,1

Cox,2

Csub,1

Rsub,1

(b)

Csub,2

Rsub,2

CP Rs(f )

L

FIGURE 9.5.3 Typical equivalent circuit of a practical spiral inductor (a) at low-to-medium frequencies and (b) in the upper micro- and millimeter-wave range. (Top electrode)

C (Bottom electrode)

Ls

Cox

Rs Rsub

Csub

FIGURE 9.5.4 Equivalent circuit of a metal–insulator–metal (MIM) capacitor.

The substrate spreading resistance, which appears as Rsub in the equivalent circuits above, generates thermal noise, which is coupled into the circuit, and can substantially degrade performance, e.g., in the input circuitry of a low-noise amplifier. As Figure 9.5.5 shows, not only the input bond-pad, but also a DC blocking MIM capacitor is prone to ground-coupled noise. Ground-coupled noise can be reduced or eliminated using a low-resistance ground shield, which can be the lowest-level interconnect metal or even the buried layer in a bipolar process. It provides a low-resistance path to ground for substrate noise. Figure 9.5.6 illustrates the concept for the case of a typical coplanar bond-pad arrangement, but it can be used also for the MIM capacitor in the above example. In spiral inductors, patterned ground shields are often used which not only reduce substrate loss and ground-coupled noise, but where the shield pattern can strongly reduce Eddy currents in the substrate which otherwise would lower both the inductance and the quality factor [7].

9.5.3 SiGe MMICS Using Heterojunction Bipolar Transistors As SiGe building blocks for wireless communications systems are covered elsewhere in this handbook, this chapter will cover some not-so-common circuits — for applications in the 10 to 30 GHz frequency range, and extremely wideband circuits for fiber-optic communications systems.

© 2006 by Taylor & Francis Group, LLC

9.5-984

The Silicon Heterostructure Handbook

(Bottom electrode)

i 2sub (Bond pad)

2

i sub

FIGURE 9.5.5 Input circuit of a typical low-noise amplifier, showing nodes prone to ground-coupled noise. Ground

Signal

Ground

Ground

Signal

Rgnd

2

i sub

Ground

Rgnd

i 2sub

FIGURE 9.5.6 Reduction of ground-coupled noise in a bond pad using a ground shield: (left) the standard arrangement without a ground shield: substrate-generated noise is fed into the signal pad; (right) addition of a ground shield layer provides a low-impedance path to ground for the substrate noise via Rgnd.

Narrow-Band Circuits In communication and sensor applications in the microwave range, e.g., for satellite communications systems in the Ku and Ka band, or sensors in the increasingly popular 24 GHz ISM band, local oscillator phase noise is often a critical parameter. It is sometimes advantageous to operate the oscillator at a lower frequency, where a higher resonator quality factor can be achieved, and then apply a frequency multiplier to reach the local oscillator frequency required. Frequency multiplication can be achieved in any nonlinear transfer characteristics, in FETs or bipolar transistors. However, unwanted spectral components need to be suppressed, which can be done more efficiently in dedicated frequency multiplier topologies than through filtering. Other critical parameters are required oscillator power, the conversion efficiency, and the necessary supply voltage. The circuit shown in Figure 9.5.7(a) has been realized in an 80 GHz fT SiGe HBT technology. Its key advantages are the low complexity, inherent suppression of fundamental frequency, and the ability to operate from a 1.2 V supply, provided that reactive loads are used. The circuit exploits the fact that the common emitter potential of a differential transistor pair fluctuates with twice the frequency of the driving waveform: the voltage is at its maximum if either Vin,1 or Vin,2 peak, and reaches its minimum when the two input voltages (which are 1808 out of phase) balance. The potential fluctuation is then fed to a common-base transistor stage through a coupling capacitor, which transfers charge between the two

© 2006 by Taylor & Francis Group, LLC

9.5-985

SiGe MMICs

(a)

Vcc

Vout,1

Vout,2

Vin,1

Vin,2 I1

Cc

I2

FIGURE 9.5.7 (a) Principle schematic of the frequency doubler cell; (b) chip photo of the realized Ku band subharmonically pumped downconverter. (After F. Gruson, H. Schumacher, and G. Bergmann. IEEE International Microwave Symposium 2004, Ft. Worth, TX, June 6–11, 2004, Paper TU2C-3. With permission.)

current sources I1 and I2, leading to the output signal at twice the input frequency. Resistors have been used as current sources in the practical implementation. The doubler cell has been used in the design of a subharmonically pumped mixer cell [8], which is wideband, but has its optimum performance at 14 GHz (7 GHz LO input signal). The single-ended LO input signal is converted into a balanced signal in an active balun circuit, then applied to the frequency doubler cell, which drives a single-balanced Gilbert mixer. In the realization of the doubler stage, the collectors of the differential pair have been connected to a low-impedance node created by a second common-base transistor. The collector loads are inductive, realized as a single symmetrically tapped spiral inductor. The chip photo is shown in Figure 9.5.7(b). The doubler has a conversion gain of 17 dB when converting from 7 to 14 GHz, while the mixer overall has a conversion gain of 8 dB for

© 2006 by Taylor & Francis Group, LLC

9.5-986

The Silicon Heterostructure Handbook

fRF ¼ 14 GHz and fIF ¼ 100 MHz. The circuit consumes 48 mA from a 2.7 V supply. The suppression of the fundamental frequency has been determined at 5 GHz, where it was 43 dB. Impressive results have been achieved also with frequency dividers using SiGe HBTs. Using a SiGe HBT technology with 200 GHz, a static frequency divider (divide by 32) with a maximum input frequency of 86.2 GHz, drawing 180 mA from a 5 V supply has been reported [9]. Even higher input frequencies are possible using dynamic frequency dividers. The concept is shown in Figure 9.5.8. Any spectral component at 12 f1 at port 1 of the mixer is sufficient to produce f1 12 f1 at port 3. The active mixer has a low-pass characteristic, which suppresses the higher frequency component and passes the 12 f1 spectral component, which is amplified and fed back to the mixer in a regenerative fashion. The dynamic frequency divider reported in Ref. [9] operated beyond 110 GHz, the highest characterization frequency. Power consumption was 310 mW from a 5 V supply. The input sensitivity versus frequency is also shown in Figure 9.5.8. Multifunctional ICs that combine most or all function, e.g., of a radio receiver on a single chip can be realized even in the upper microwave or millimeter-wave range. A fully integrated receiver IC using Si– SiGe HBTs on medium-resistivity silicon was already published in 2002 [10]. It contained all necessary circuits (preamplifier, VCO, mixer, and IF amplifier) of a 24-to-0.1 GHz downconverter, reducing the number of necessary external connections considerably. The IC used a 50 GHz fT and fmax HBT process, which can be considered to be at the limits of its useful performance at 24 GHz. Using a HBT technology with 75 GHz fT and fmax, a downconverter IC for applications, e.g., in the 26 GHz LMDS band has been realized [11]. The layout is shown in Figure 9.5.9. Within a compact area of 700 mm 170 mm, the IC consists of three preamplifier stages using LC interstage matching (the three left spiral inductors), a Gilbert-cell active mixer stage with the groundside current source replaced by spiral inductor, and an intermediate-frequency output buffer stage. The local oscillator is here not part f1 ⫾ ½ f1 f1

½ f1 ½ f1

3 2 ½ f1

Input power (dBm)

10

0

−10

−20

−30

0

10

20

30

40

50

60

70

80

90

100 110

Input frequency (GHz)

FIGURE 9.5.8 Concept of a dynamic frequency divider, and the result obtained with a SiGe HBT implementation. (From H. Knapp, M. Wurzer, T.F. Meister, K. Aufinger, J. Bo¨ck, S. Boguth, and H. Scha¨fer. 86 GHz static and 110 GHz dynamic frequency dividers in SiGe HBT technology. International Microwave Symposium, Philadelphia, PA, June 8–13, 2003, Paper WE6C-5. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.5-987

170 µm

SiGe MMICs

700 µm FIGURE 9.5.9 Layout of a 26 GHz SiGe HBT downconverter for LMDS applications. (After E. So¨nmez, A. Trasser, P. Abele, K.-B. Schad, and H. Schumacher. Proc. European Microwave Conference (EUMC/EMW), Munich, Germany, October 6–10, 2003, pp. 399–402. With permission.)

of the chip, but is fed through the top coplanar port. The IF output buffer contains an RC low-pass filter with a 3-dB cutoff frequency of 1.5 GHz. The preamplifier stages are identical and consist of a cascode gain cell biased through a current mirror. The circuit has a conversion gain of 24 dB with a differential IF load, and draws 120 mW from a 3 V supply. Sensors operating in the 24 GHz ISM band and potentially at higher frequencies benefit from the low cost of SiGe HBT technologies as well. Doppler RADAR sensors can be realized quite simply and find use in many applications such as contactless speed measurement or motion detection. In SiGe, Doppler sensors can be realized using inexpensive HBT technologies. In the following example, a commercial SiGe HBT technology with 50 GHz fT and fmax has been used. The circuit uses only lumped elements, resulting in a chip area of 780 690 mm2. It can be flip-chip mounted on a substrate carrying the base-band processing and the antennas. In hybrid implementations of Doppler RADAR sensors, a single oscillator is used for receiver and transmitter. The RF power is split by means of a Wilkinson divider, which consumes considerable area and results in power loss. Here, a different concept has been pursued: two separate oscillators synchronized by a magnetic coupling loop (see Figure 9.5.10(a)). As an added benefit, the magnetic coupling allows a clear separation between the receive and transmit paths in the layout, which is shown in Figure 9.5.10(b). The pitch of the flip-chip bond bumps is 200 mm2. The key component, the magnetically coupled inductors, is laid out in perfect symmetry. A two-turn coupling loop is formed in a metalization layer underneath. A lumped-element equivalent circuit has been used to simulate the coupled inductor four-port over the 0 to 50 GHz range with good accuracy. The transmit amplifier feeds a differentially side-fed patch antenna; a single-ended side-fed receive antenna directly works into a Gilbert cell mixer. The IC has been incorporated in a very compact module including the antennas and simple base-band processing [12].

Wide-Band Circuits Multi-octave bandwidth is commonly achieved through two different fundamental approaches: .

Through negative feedback. Single-stage wide-band amplifiers commonly use a parallel (output voltage to input current) feedback technique, often referred to as a transimpedance amplifier.

© 2006 by Taylor & Francis Group, LLC

9.5-988

The Silicon Heterostructure Handbook (a) Osc 1 Differentially driven Patch antenna Sync Single-ended Patch antenna Osc 2

To baseband processing

Solder balls

(b)

Coupled oscillators

Cascode amplifier

Differential output

Mixer input

Mixer

Low pass filter

Doppler output

FIGURE 9.5.10 Block diagram (a) and chip photo (b) of a 24 GHz Doppler RADAR sensor using magnetically coupled synchronized oscillators.

.

Multistage wide-band amplifiers will use alternating parallel and series (output current to input voltage) feedback techniques — the Cherry–Hooper design principle. Through distributed amplifier concepts. Here, the input and output capacitances which form RC low-pass poles with the stage’s source and load impedances are embedded into artificial transmission line structures formed either by lumped-element inductors or, more commonly, by highcharacteristic-impedance transmission line segments. Figure 9.5.11 shows the concept for the case of field-effect transistors. Using this technique, the device input (CGS) and output (CDS) capacitances are completely absorbed over a wide frequency range in an artificial transmission line with characteristic impedance ZL (up to the low-pass cutoff frequency of the cascaded transmission line segments), resulting simultaneously in a flat gain and excellent input and output matching conditions.

© 2006 by Taylor & Francis Group, LLC

9.5-989

SiGe MMICs

L 1/2

C GS

R = ZL

L1

L1

L1

C DS

C DS

C DS

C GS

L2

C GS

L2

L 1/2

R = ZL

C DS C GS

L2

L2

L 2/2

FIGURE 9.5.11 Generic concept of a distributed (or traveling-wave) amplifier.

Transimpedance amplifier

Transadmittance amplifier

Transimpedance amplifier

Reduced input admittance

Increased input and output admittances

FIGURE 9.5.12 Generic concept of a Cherry–Hooper wideband amplifier.

Cherry–Hooper wideband amplifiers are commonly used in SiGe HBT amplifiers intended for highbitrate fiber-optic communications systems. As indicated, they deliberately apply large interstage impedance mismatches and hence deviate significantly from common MMIC design techniques. The generic concept is shown in Figure 9.5.12. A wideband amplifier directly behind a photodiode will have a transimpedance stage as the first stage. A transimpedance stage employs parallel (output voltage to input current) feedback around an inverting amplifier stage, providing a low input impedance for the photodiode (which is essentially a current source). The parallel feedback reduces both the input and the output impedance. The next stage is then a transadmittance stage, using series (output current to input voltage) feedback, which decreases both the input and the output admittance. Most importantly, the input capacitance of the transadmittance stage is reduced by the series feedback, leading to a small characteristic time constant of the pole between the first and second stages. The pole between the second and third stages is reduced by the low input impedance of the third stage, which has a transimpedance topology again. An excellent example of a Cherry–Hooper type amplifier is shown in Figure 9.5.13 [13]. The circuit has a fully differential topology to reduce problems with common-mode impedance in the ground and supply lines. The first stage is a transimpedance stage with feedback RF. The photodiode is connected to one input, while the other is shorted to ground capacitively, but receives an offset-compensating control current. As a slight modification of the classic Cherry–Hooper design, the next block is a three-stage emitter follower, which provides the high input impedance of a transadmittance stage, but a low output impedance. The third stage is then a transadmittance stage with series-feedback resistors RE and a cascode configuration. Using a SiGe HBT technology with 72 GHz fT, the circuit proved capable of 40 Gbit/sec operation.

© 2006 by Taylor & Francis Group, LLC

9.5-990

The Silicon Heterostructure Handbook

VD<0 Output

PD

RF

VB

RF RE

RE

V CC DC amplifier

FIGURE 9.5.13 SiGe HBT limiting transimpedance amplifier for 40 Gbit/sec. (After J. Mu¨llrich, T.F. Meister, M. Rest, W. Bogner, A. Scho¨pflin, and H.-M. Rein. Electron. Lett. 34, 452–453, 1998. With permission.)

Here, the amplifier combines a linear first stage (the transimpedance stage) with voltage-limiting action in the following stages, but this does not affect the general principle. Distributed amplifiers are the circuit topology of choice in HFETs where the input admittance of a common-source stage is predominantly capacitive. An example using experimental SiGe HFETs will be shown in Section 9.5.4. Compared to negative-feedback amplifiers, distributed amplifiers have the advantage that it is considerably easier to achieve a constant group velocity (a linearly varying phase) versus frequency. In digital communications systems, constant group velocity is a very critical parameter, at par with the more commonly considered power gain and input and output match. This inherent property makes distributed amplifiers interesting for implementation also in SiGe HBT technologies. For bipolar transistors in common-emitter configuration, a real conductance gbe ¼ gm/b appears at the input node in parallel (see Figure 9.5.14), and hence the input admittance is no longer purely imaginary, even at low frequencies: y 1, e ¼

gm gm þ jvCTe or, as fT : b 2pCTe gm f 1 þ jb y1,e ¼ fT b

where gm is the transconductance, b the small-signal current gain, Cte the total base–emitter capacitance, and Cbc the base–collector space–charge capacitance. The real part would then seriously attenuate the wave propagating on the input transmission line. The input impedance of the individual gain cell can be increased by using a common-collector (emitter follower) stage ahead of the common-emitter stage. In Figure 9.5.15, the combination of an emitter followed by a cascode stage is shown — the reason for the cascode cell will be discussed later. Using the common-emitter input admittances gm1 f 1 þ jb1 y1 ¼ for the common-emitter transistor T1 and fT1 b1

© 2006 by Taylor & Francis Group, LLC

9.5-991

SiGe MMICs

(Out)

gm Vbe

gbe

gce

Cce

CTe

Vbe

(In)

FIGURE 9.5.14 Simplified equivalent circuit of a common-emitter bipolar gain cell in a distributed amplifier. (Out)

T3 T1 T2

(In)

FIGURE 9.5.15 Simplified schematic of a bipolar gain cell in a distributed amplifier, using an emitter follower/ cascode topology (biasing elements not shown).

y2 ¼

gm2 f 1 þ jb2 for the collector transistor T2 fT2 b2

the input admittance of cascaded common collector and common-emitter stages follows: yin ¼

y2 y1 if b2 1, 1 þ yy21 (1 þ b2 ) b2

y2 (1 þ b2 ) 1 y1

or yin ¼

gm1 f 1 þ b1 fT1 b1 b2

The cascode cell formed by transistors T2 and T3 provides a larger gain, reduces feedback between output and input, and reduces the attenuation on the output line. The latter point deserves some attention. Figure 9.5.16(a) shows the small-signal equivalent circuit for the cascode cell for the case vbe2 ¼ 0, i.e., for the base of T2 at a constant potential. The capacitances Cce2, Cce3 in a bipolar transistor

© 2006 by Taylor & Francis Group, LLC

9.5-992

The Silicon Heterostructure Handbook

(Out) Vbe3

(Out) i2

Cbc3 Cbc3

CTe3

gbe3

gbe3

gm Vbe3

Cce3

gce3

Cce3

gm3 Vbe3 V2 Cbc2 gce2

Cce2

Vbe3

gbe

(a)

CTe

(b)

FIGURE 9.5.16 (a) Equivalent circuit of the cascode cell (T2 and T3 in Figure 9.5.15) for vbe2 ¼ 0. (b) Simplified equivalent circuit, assuming identical transistors and recognizing IC2 ¼ IC3, gm2 ¼ gm3 ¼ gm, Cte2 ¼ CTe3 ¼ CTe, gbe2 ¼ gbe3 ¼ gbe.

are parasitic. We can assume Cte >>Cbc, Cce for both transistors, further gbe ¼ gm/b ¼ gm, gbe >> gce ¼ IC/VA, where VA is the Early voltage. Using these assumptions, we arrive at the much simpler equivalent circuit in Figure 9.5.16(b). The output admittance is

Y2 ¼

(gce þ jvCce3 )(gbe þ jvCTe ) þ jvCcb3 gce þ gbe þ gm þ jv(CTe þ Cce3 )

IC Further simplification: CTe Cce3 ;gbe ¼ bV gce ¼ VICA : T

Y2

gbe gce v2 CTe Cce3 þ jv(gbe Cce3 þ gce CTe ) þ jvCcb3 2 gm þ jvCTe

We are particularly interested in the real part, which will attenuate the wave on the output line: gce v2 gce Cce3 b vT vT R {Y2 } ¼ 2 v 1þ vT using gm gm ¼ vT ¼ 2pfT , the transit frequency. gbe ¼ ; b CTe We note that the resistive loading of the output line is reduced by the common-emitter current gain b (to gce/b). Provided that Cce3 > gcev the output conductance may actually become negative at elevated frequencies. This can be used to further compensate loss on the output line, but may also lead to instability at high frequencies. Losses on the input line can be compensated by introducing a series capacitor into the emitter of the common-collector transistor stage, which will result in a negative resistance at the base node [15].

© 2006 by Taylor & Francis Group, LLC

9.5-993

SiGe MMICs

Using gain cells consisting of a common-collector input stage, a differential amplifier gain cell and a cascode output cell, Wohlgemuth and coworkers realized a distributed amplifier capable of 80 Gbit/sec operation [15]. Figure 9.5.17 shows the block diagram. The design is fully differential, eliminating problems with common-node impedances when packaged. The transmission lines have been realized as ground-backed coplanar waveguides, using the top and bottom metallizations of the standard metallization stack in the SiGe HBT technology used, which has fT and fmax in excess of 200 GHz. The structure has been realized on a chip area of 1.3 0.9 mm2; it consumes 90 mA from a 5.5 V power supply. Characterization has been reported for single-ended performance only; the scattering parameters s11, s22, and s21 are shown in Figure 9.5.18.

50 Ω terminations Input

Output 50 Ω terminations

FIGURE 9.5.17 Block diagram of a fully differential distributed amplifier using SiGe HBTs. (After O. Wohlgemut, P. Paschke, and Y. Baeyens. 33rd European Microwave Conference, Munich, Germany, October 7–10, 2003. With permission.)

20 S21

S-parameter (dB)

10 0 −10

S11

−20 S22

−30 −40 0

20

40 60 Frequency (GHz)

80

100

FIGURE 9.5.18 Experimental scattering parameters of the differential distributed amplifier shown in Figure 9.5.17. The measurement is single-ended. (After O. Wohlgemut, P. Paschke, and Y. Baeyens. 33rd European Microwave Conference, Munich, Germany, October 7–10, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.5-994

The Silicon Heterostructure Handbook

Calibration above 70 GHz was reported to be difficult with the GSSG wafer probes used, which may contribute to the artifacts observed above 80 GHz. The measurements demonstrate a 3-dB-bandwidth of 81 GHz. In differential mode, the gain-bandwidth product would be 350 GHz and be at par with the best values reported for III–V-based distributed amplifiers. The input and output match is good at least up to 60 GHz, above which it may be affected by the noted calibration problems.

9.5.4 SiGe MMICS Using Heterostructure Field-Effect Transistors SiGe HFETs are an emerging technology, which uses strained Si–SiGe heterostructure channels to enhance low-field mobilities of electrons and holes. Both MOSFET-like structures (charge control through an MOS gate diode) and MODFET-like structures (charge control through a Schottky-gate diode) have been used. A first ultrawide-band MMIC amplifier structure has been realized using an n-channel MODFET technology fully described in Ref. [16]. The FET layers reside on a fully relaxed Si1xGex buffer with x ¼ 40%. The Si substrate underneath has a resistivity of 1000 V cm. The n-channel forms in a 9-nm thick undoped Si channel layer, which sits between two Sb-doped SiGe supply layers and spacers. The Schottky gate sits on top of a 3.5 nm Si cap. The gate electrode is a Pt–Au T-gate with LG ¼ 100 nm defined by electron beam lithography. The transistors are characterized by a transconductance gm ¼ 175 mS/mm, a transit frequency fT of 52 GHz, and a maximum frequency of oscillation fmax ¼ 148 GHz extracted from Mason’s unilateral gain U. The transistors used in the circuit design had a total gate width of 100 mm. The MODFETs were modeled using a large-signal equivalent circuit approach with globally continuous equations [17]. Models for the coplanar transmission lines on the virtual SiGe substrate were developed using test structures on similar wafers and fitting the parameter set for coplanar transmission lines in Agilent ADS, which was also used for the complete circuit design. The distributed amplifier realized in this technology has six identical stages [18]. The gate transmission line has segments of 450 mm length with a center conductor width of 20 mm and signal-to-ground gaps of 60 mm, while the drain transmission line has segments of 530 mm length, with a center conductor width of 20 mm and gaps of 40 mm. Figure 9.5.19 shows a chip photograph. The circuit draws 45.7 mA from a 2.3 V supply, the gate bias is held at VGS ¼ 0.16 V. At this bias point, the amplifier exhibits 5.5 + 0.8 dB up to 32 GHz (see Figure 9.5.20). The comparison between modeled and experimental performance shows excellent agreement. The relatively low gain of the amplifier can be explained by the rather high source resistance of the FETs used (RS ¼ 9 V).

FIGURE 9.5.19 Chip photograph of a distributed amplifier using Si–SiGe n-channel MODFETs. (After P. Abele, M. Zeuner, I. Kallfass, J. Mu¨ller, H.L. Hiwilepo, D. Chrastina, H. Von Ka¨nel, U. Ko¨nig, and H. Schumacher. Electron. Lett. 39, 1448–1449, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.5-995

SiGe MMICs

10 5 0 dB

−5 −10 −15 −20 −25 −30

0

5 S21,meas S21,model S11,meas

10

15 20 25 30 Frequency (GHz) S11,model S22,meas S22,model

35

40

FIGURE 9.5.20 Measured and modeled scattering parameters for the Si/SiGe MODFET traveling-wave amplifier. (After I. Kallfass, T. J. Brazil, B. OhAnnaidh, P. Abele, Th. Hackbarth, M. Zeuner, U. Ko¨nig, and H. Schumacher. Solid-State Electron., 48, 2004, 1433–1441. With permission.)

9.5.5 Summary Monolithic microwave ICs using Si–SiGe HBTs and HFETs offer interesting design options for microwave, millimeter-wave, and wideband fiber-optic applications. The disadvantage of the lossy substrate, compared to GaAs, can be compensated by proper circuit design techniques. These silicon-based heterostructure ICs have their best application potential if . . .

A large market volume can be expected or High on-chip circuit complexities are needed and Low-noise and power specifications are moderate

Acknowledgments The author gratefully acknowledges the contributions by and many fruitful discussions with his staff at the University of Ulm, particularly Peter Abele, Nabil Alomari, Frank Gruson, Martin Ha¨fele, Christoph Schick, Ingmar Kallfass, Kai-Boris Schad, Ertugrul So¨nmez, Andreas Trasser, and Shen Yan. The original work presented here would not have been possible without the continuous cooperation of Atmel Germany GmbH, Heilbronn, Germany for the HBT work, and the Daimler Chrysler Research Center, Ulm, Germany for the HFET work. Some of this research has been supported by the European Commission and the German Ministry of Education and Research.

References 1. A.C. Wilson, D. Melendy, P. Francis, K.Hwang, and A. Weisshaar. Comprehensive compactmodeling methodology for spiral inductors in silicon-based RFICs. IEEE Trans. Microwave Theory Tech. 52, 849–857, 2004. 2. H. Hashemi, X. Guan, and A. Hajimiri. A fully integrated 24-GHz 8-Path phased-array receiver in silicon. ISSCC 2004, San Francisco, CA, February 15–18, 2004. 3. I. Harrison, M. Dahlstro¨m, S. Krishnan, Z. Griffith, Y.M. Kim, and M.J.W. Rodwell. Thermal limitations of InP HBTs in 80- and 160 Gb Ics. IEEE Trans. Electron Dev. 51, 529–534, 2004. 4. J.-S. Rieh, B. Jagannathan, H. Chen, K.T. Schoenenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S.-J. Jeng, M. Khater, F. Pagette, C. Schnabel, P. Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna. SiGe HBTs with cut-off frequency of

© 2006 by Taylor & Francis Group, LLC

9.5-996

5. 6.

7.

8.

9.

10.

11.

12.

13.

14. 15.

16. 17.

18.

19.

The Silicon Heterostructure Handbook

350 GHz. International Electron Device Meeting, San Francisco, CA, December 8–11, 2002, pp. 771–774. P. Russer. Si and SiGe millimeterwave integrated circuits. IEEE Trans. Microwave Theory Tech. 46, 590–603, 1998. W. Du¨rr, U. Erben, A. Schu¨ppen, H. Dietrich, and H. Schumacher. Investigation of microstrip and coplanar transmission lines on lossy silicon substrates without backside metalization. IEEE Trans. Microwave Theory Tech. 46, 712–715, 1998. S.-M. Yim, T. Chen, and K.K. O. The effects of a ground shield on spiral inductors fabricated in a silicon bipolar technology. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, September 24–26, 2000, pp. 157–160. F. Gruson, H. Schumacher, and G. Bergmann. A frequency doubler with high conversion gain and good fundamental suppression. IEEE International Microwave Symposium 2004, Ft. Worth, TX, June 6–11, 2004, Paper TU2C-3. H. Knapp, M. Wurzer, T.F. Meister, K. Aufinger, J. Bo¨ck, S. Boguth, and H. Scha¨fer. 86 GHz static and 110 GHz dynamic frequency dividers in SiGe HBT technology. International Microwave Symposium, Philadelphia, PA, June 8–13, 2003, Paper WE6C-5. E. So¨nmez, A. Trasser, K.-B. Schad, P. Abele, and H. Schumacher. A single-chip 24 GHz receiver front-end using a commercially available SiGe HBT foundry process. RFIC Conference, Seattle, USA, June 2–4, 2002, pp. 159–162. E. So¨nmez, A. Trasser, P. Abele, K.-B. Schad, and H. Schumacher. Integrated receiver components for low-cost 26 GHz LMDS applications using an 0.8 mm SiGe HBT technology. Proc. European Microwave Conference (EUMC/EMW), Munich, Germany, October 6–10, 2003, pp. 399–402. P. Abele, A. Trasser, E. So¨nmez, K.-B. Schad, A. Munding, and H. Schumacher. A compact low-cost doppler sensor using SiGe HBT technology and patch antennas for the ISM Band at 24 GHz. 34th European Microwave Conference, Amsterdam, The Netherlands. October 12–14, 2004. J. Mu¨llrich, T.F. Meister, M. Rest, W. Bogner, A. Scho¨pflin, and H.-M. Rein. 40 Gbit/s transimpedance amplifier in SiGe bipolar technology for the receiver in optical-fibre TDM links. Electron. Lett. 34, 452–453, 1998. S. Deibele and J.B. Beyer. Attenuation compensation in distributed amplifier design. IEEE Trans. Microwave Theory Tech. 37, 1425–1433, 1989. O. Wohlgemut, P. Paschke, and Y. Baeyens. SiGe broadband amplifiers with up to 80 GHz bandwidth for optical applications at 43 Gbit/s and beyond. 33rd European Microwave Conference, Munich, Germany, October 7–10, 2003. T. Mack, T. Hackbarth, H.-J. Herzog, H. Von Ka¨nel, M. Kummer, J. Ramm, and R. Sauer. Si/SiGe FETs grown by MBE on LEPECVD grown virtual substrate. Mater. Sci. Eng. B 39, 368–372, 2002. I. Kallfass, M. Zeuner, U. Ko¨nig, H. Schumacher, and T.J. Brazil. A DC to 40 GHz large signal model for n-channel SiGe HFET transistors including low-frequency dispersion. 32nd Europ. Microwave Conf. (EuMC), Milano, Italy, 2002. P. Abele, M. Zeuner, I. Kallfass, J. Mu¨ller, H.L. Hiwilepo, D. Chrastina, H. Von Ka¨nel, U. Ko¨nig, and H. Schumacher. A 32 GHz MMIC distributed amplifier based n-channel SiGe MODFETs. Electron. Lett. 39, 1448–1449, 2003. I. Kallfass, T. J. Brazil, B. OhAnnaidh, P. Abele, Th. Hackbarth, M. Zeuner, U. Ko¨nig, and H. Schumacher. Large-signal modelling including low-frequency dispersion of N-channel SiGe MODFETs and MMIC applications. Solid-State Electronics. 48, 1433–1441, 2004.

© 2006 by Taylor & Francis Group, LLC

9.6 SiGe MillimeterWave ICs 9.6.1 9.6.2 9.6.3

Introduction............................................................... 9.6-997 Silicon as a Substrate ................................................ 9.6-997 Millimeter-Wave Generation .................................... 9.6-998 Oscillators . Coplanar Oscillators . Microstrip Oscillators . Multiplier

9.6.4 9.6.5 9.6.6

Amplifier .................................................................. 9.6-1002 Mixer ........................................................................ 9.6-1002 MMICS with SiGe Diodes ...................................... 9.6-1003

9.6.7

Summary .................................................................. 9.6-1003

Johann-Friedrich Luy DaimlerChrysler Research

Switches . Mott Diodes . IMPATT Diodes

9.6.1 Introduction The millimeter-wave range usually starts at 30 GHz and ends at 300 GHz entering the sub-millimeterwave range. Below 100 GHz there are many possible applications of wireless communication systems, radars, and navigation systems, which are handicapped by the high costs of the front-end electronics. Beyond 100 GHz the applications are still explorative. A major breakthrough is expected for all these applications, if low-cost silicon technologies can serve the markets. Currently, the silicon–germanium HBT technology is the most promising approach to fulfill the requirements. The design, the state-of-theart performance, and some technological aspects of analog silicon-based millimeter-wave integrated circuits using mostly HBT technologies are discussed in this chapter.

9.6.2 Silicon as a Substrate Almost 20 years after the report of microstrip attenuation values below 1 dB/cm at 90 GHz on highresistivity silicon (HRS) substrate [1], the question of the most suited transmission line on silicon substrates is still discussed. If HRS material is considered, microstrip or coplanar transmission lines may be the choice (Figure 9.6.1). There is a high technological effort for the fabrication of microstrip circuits with a thickness of 100 mm including via holes in silicon. Large area coplanar lines with similar attenuation values on HRS may be an alternative. Heat removal and packaging difficulties are the most relevant drawbacks of coplanar circuits. Using low-resistivity substrates (LRS), thin film microstrip lines might be attractive due to their attenuation independent on the substrate resistivity. The question of the most suited transmission line cannot be answered without consideration of the circuit function. If extremely low attenuation values are required (application: high-Q circuits for lownoise MMICs), then microstrip circuits on 100-mm thick HRS substrate are superior with respect to the other transmission line concepts. Additionally, microstrip resonators can be easily coupled to a DR to further increase the Q-value [2]. Figure 9.6.2 shows the Q-value of different transmission lines calculated with field theoretical models [3]. The properties of coplanar lines depend on the line geometry. 9.6-997 © 2006 by Taylor & Francis Group, LLC

9.6-998

The Silicon Heterostructure Handbook

Dielectric

HRS

Arbitrary substrate

HRS

FIGURE 9.6.1 Planar transmission lines: thin film microstrip, microstrip, and coplanar.

240

115/150

220

78/100

MS

200 180 160

Q

140 120 100

150/300

80

CPW

60

50/300

40 20 0

60/25 0

10

20

30

40

50

60

70

80

90

TFM

100

110

[GHz] FIGURE 9.6.2 Quality factor of transmission lines as a function of the frequency. Numbers indicate width of line (mm)/substrate height (mm). CPW: ground-to-ground spacing.

The quality factor of coplanar transmission lines is usually below that of microstrip lines. Thin-film microstrip lines are suited for interconnects and frequencies below 10 GHz. Silicon as a substrate material is advantageous due to a thermal conductivity three times higher than that of GaAs [4]. This is of great importance when active devices are to be integrated. The low thermal expansion coefficient of silicon may be a further advantage for a practical application of silicon-based millimeter-wave integrated circuits.

9.6.3 Millimeter-Wave Generation Oscillators Negative resistance circuits are widely used to realize low-phase noise oscillators. An active device is used to compensate for the attenuation in a resonator and to generate oscillations.

Coplanar Oscillators Coplanar MMICs with SiGe HBTs may be realized on HRS substrates. The coplanar concept is advantageous with regard to the microstrip technology as it avoids backside processing and provides easy measurement access by on-wafer probing. One of the first publications on coplanar millimeterwave oscillator SiGe MMICs reports on a 29 GHz oscillator [5]. A double mesa HBT process is used

© 2006 by Taylor & Francis Group, LLC

SiGe Millimeter-Wave ICs

9.6-999

with an fmax ¼ 80 GHz. Coplanar waveguides with miniaturized dimensions (50 mm ground-to-ground spacing) are used. The transistor is operated in common-base configuration, one emitter finger is connected to an open stub, which realizes the capacitive feedback of the reflection type oscillator. Bias is fed to the second emitter finger. A short stub is connected to the base to generate maximum negative resistance at the collector. At the collector side an output circuit is designed that matches the oscillator impedance to the 50 V load. A maximum output power of 1 dBm at 29.3 GHz is measured with a collector current of IC ¼ 10 mA. Modeling of the passive elements plays an important role for an accurate chip design. Missing the center frequency by more than 10% is an indication of larger differences between models and experiments. Improved modeling as well as improved technology properties lead to an optimized oscillator circuit at 47 GHz. The layout of this oscillator is shown in Figure 9.6.3. The chip size is 1.9 1.1 mm2. The HBT is operated in a common-base configuration. DC bias is fed in symmetric lines to the six-finger HBT without air bridges. The inductive feedback from the base is caused by a coplanar line element. An output network matches the collector to 50 V. MIM capacitances in the emitter and collector DC bias lines block the RF signals. The ground-to-ground spacing of the coplanar lines is 50 mm. In order to optimize the oscillator circuit, 1. The Rollett factor is minimized. 2. The phase slope of the output matching network is maximized.

FIGURE 9.6.3 Layout of a coplanar 47 GHz oscillator.

© 2006 by Taylor & Francis Group, LLC

9.6-1000

The Silicon Heterostructure Handbook

From this SiGe MMIC oscillator an output power of 13 dBm at 47 GHz is measured at a collector current of IC ¼ 32 mA [6]. The corresponding conversion efficiency is 13.6%. The phase noise is below 91 dBc/Hz at 100 kHz (Figure 9.6.4). Similar performance data are obtained at 24 GHz. An output power of 8.7 dBm with a collector current of 27 mA, the SSB phase noise is 99 dBc/Hz at 100 kHz [7]. The coplanar LC resonator–oscillator design concept on HRS is suited to provide high Q-factors for excellent phase noise behavior. Varactor diodes may be integrated in the SiGe HBT process using the base–collector junction as active layers of a varactor diode. A varactor capacitance can change effective lengths of lines, and therefore, tune oscillators. A tuning range of 5% is achieved at Ka band frequencies [7]. So far, coplanar oscillator designs on HRS using distributed elements are discussed. With lumped elements on LRS (20 V cm) miniaturized oscillators may be realized with good performance based on a commercial foundry process. The output power from a chip sized 0.75 1.1 mm2 reaches 1.2 dBm at 25 GHz with an SSB-phase noise of 90 dBc/Hz at 100 kHz [8]. In a fully differential circuit configuration, designed for 47 GHz operation, an output power of 5.6 dBm is obtained from the differential output employing five HBTs on a commercial process with fT fmax 75 GHz. The phase noise is between 103 and 108 dBc/Hz at 100 kHz [9]. This design concept is further improved and applied to a process with fT 150 GHz and fmax 180 GHz [10]. An output buffer comprising an emitter follower and an emittercoupled stage as well a differential grounded-base stage followed by a network to match external 50 V output loads is added to the oscillator core (Figure 9.6.5). A total signal power of 14 dBm is obtained from the output ports at a center frequency for 77 GHz. The phase noise is 95 dBc/Hz at 1 MHz and 75 dBc/Hz at 100 kHz [11]. A 117 GHz LC oscillator is fabricated in a 200 GHz SiGe:C BiCMOS technology with 0.25 mm minimum feature size [12]. An output power of 12 dBm is achieved.

Microstrip Oscillators In spite of the increased technological efforts (wafer thinning down to 100 mm, backside processing, viahole technology) microstrip transmission (MST) line technology is investigated as well. MST enables high-Q resonators, lower attenuation, better RF packaging characteristics, and well-known design and simulation software. An MST technology uses 100 mm substrate thickness and circular via-holes with vertical sidewalls and a diameter of 80 mm, passive elements like resistors, MIM capacitors, and spiral inductors are realized, tested, and modeled [13]. This MST technology is combined with a Si–SiGe HBT technology, which uses for the microstrip technology differentially grown Si MBE layers with 30% Ge in the base layer, a double mesa fabrication

0 (fm): SSB N/C (dBc)

−20 −40 −60 −80 −100 −120

< −91 dBc/Hz @ 100 kHz (b4758b)

−140 −160

103

104

105

106

fm: offset from carrier (Hz)

FIGURE 9.6.4 Single sideband phase noise of the 47 GHz oscillator.

© 2006 by Taylor & Francis Group, LLC

107

9.6-1001

SiGe Millimeter-Wave ICs

λ/4lines

LC1

LCQ

LC2

LQ

VR2 VB

T

T

EF

50 Ω (ext.)

CP

Q

Q

Output

GBS

VR1 Cvar

VR3 ECS

∆CE

V0 = −5.5 V Oscillator core

Output buffer

FIGURE 9.6.5 Circuit diagram of the 77 GHz VCO with output buffer.

FIGURE 9.6.6 Chip photo of 27 GHz microstrip VCO. Chip size is 2.7 mm 1.9 mm.

process with self-stopping emitter etching, self-aligned base contacts, trench-isolation etching, and low temperature-chemical vapor deposition (LT-CVD) deposited silicon nitride isolation. The fT and fmax values of the differential grown and processed SiGe HBT are 40 and 60 GHz. The fmax value is quite low due to the not optimized differential processing. The base and collector layers are used for the varactor. A reflection-type oscillator design in common-base configuration is used [7]. The emitter is connected to a resonator line, which can be tuned by a varactor. The circuit design and chip photo are shown in Figure 9.6.6. From the output spectrum an SSB-phase noise value of better than 90 dBc/Hz at 100 kHz offset is found, which represents an extremely good value for a voltagecontrolled oscillator. For a varactor tuning voltage from 1 to 7 V the output power remains constant. The total output power is 5 dBm at 27 GHz in this 400 MHz tuning range. The total frequency change is 800 MHz.

© 2006 by Taylor & Francis Group, LLC

9.6-1002

The Silicon Heterostructure Handbook

Input matching

Second harmonic reflection

Output matching

FIGURE 9.6.7 Scheme of a doubler in differential technology.

Multiplier There are two important reasons to deal with multipliers: First, it is easier to generate oscillations with transistors at microwave frequencies and then to multiply the signal. Second, in most system applications frequency dividers are needed for stabilization purposes, which are rarely available at millimeter waves. High harmonics can be generated with nonlinear electronic devices as diodes or transistors. Active frequency multipliers with transistors have increasing importance mainly due to their small conversion loss or even conversion gain. The majority of designs of active millimeter multipliers are based on FET devices as the nonlinear component. A first frequency multiplier based on a SiGe HBT technology with fmax 67 GHz is designed for an output frequency of 55 GHz. The conversion efficiency of this circuit is better than 12 dB, operating at an output frequency near fmax of the device [14]. In the frequency range between 15 and 18 GHz an active doubler with conversion gain is demonstrated. In a differential circuit configuration the input signals are fed into the base of the transistors, which are biased near the class B region in order to generate the second harmonic components efficiently (Figure 9.6.7). Due to the feedback of the 2f0 components through the base–collector capacitor, a resonator is needed at the base of transistors T1 and T2 to reflect the second harmonic signals back into the doubler circuit for higher conversion gain. At the fundamental frequency the two input signals are out of phase, and the reflector presents two shunt capacitors, which are treated as part of the input matching network. At the second harmonic frequency, the 2f0 components are in phase and the reflector is equivalent to two series resonators. An output power of 5 to 6 dBm is obtained from 15 to 18 GHz, and the corresponding input power is 1.5 dBm [15].

9.6.4 Amplifier A first HBT-based amplifier MMIC is demonstrated at Ka-band frequencies on high-resistivity substrate [16]. The design is based on the coplanar concept. Air bridges are used to suppress undesired slot-line modes. Spiral inductors serve as RF blocks. The passivation of the metal-free regions between the line conductors must be removed in order to prevent surface charges inducing parasitic conducting layers. Recent results using IBM’s BiCMOS 7HP process prove that SiGe distributed amplifier MMICs for the frequency range from 0.1 to 50 GHz are competitive with III–V solutions [17]. The passband gain from 100 MHz to 50 GHz for this amplifier varies between 9 and 5 dB.

9.6.5 Mixer One specific application area that has received much attention in recent years is the automotive area, especially as the FCC granted regulatory approval in the United States for ultra-wideband (UWB) emissions in 2002. For the use in direct-down conversion I/Q receivers in short-pulse radar systems a

© 2006 by Taylor & Francis Group, LLC

SiGe Millimeter-Wave ICs

9.6-1003

high instantaneous bandwidth is required. Over the 3 to 35 GHz frequency range for an IF frequency of 500 MHz and an LO drive of 0 dBm, a SiGe mixer MMIC displays a conversion gain of over 20 dB, including the contribution of the baseband output stage [18]. The design comprises an LO input stage, a double-balanced Gilbert cell for mixing and multiplication, and an IF output stage. The double sideband (DSB) noise figure of this mixer, which is designed and realized on an Atmel process using 1000 V cm substrate, is less than 8 dB at 24 GHz. The chip size is 250 mm 280 mm. In the Gilbert cell, the use of current sources should be avoided due to their deteriorating effect on the noise performance [19]. In an optimized design, the usual transistor current source is replaced by a spiral inductance of two turns. With a three-stage preamplifier in cascode configuration and a singleended input, a Gilbert cell mixer with a single-ended LO-drive input and a differential-output IF buffer amplifier circuit using lumped elements (MIM capacitors and spiral inductors), a conversion gain of 40 dB for an IF frequency of 100 MHz can be achieved [20].

9.6.6 MMICS with SiGe Diodes Switches Pin diodes are used in switches as they can provide a very low on-resistance and low switching times. SPDT switches with lateral pin diodes for 77 GHz operation are demonstrated on HRS providing the I-region and pþ and nþ layers formed by implantation [21]. These circuits may be fabricated on a wafer before the silicon–germanium process sequence is started. Vertical pin diodes may be created using the collector layer of a HBT as ‘‘intrinsic’’ layer. Shunt diodes based on the IBM SiGe foundry process are demonstrated, which achieve an insertion loss of <0.5 dB and an isolation of >20 dB across the 1 to 20 GHz band [22]. A full transfer switch containing a five-port design with 10 pin diodes is demonstrated with a path loss of 1.4 to 2.1 dB across 7 to 11 GHz; the isolation over the same band is 41 to 75 dB. Utilizing this diode, several control circuits including a broadband (1 to 20 GHz) monolithic single-pole double throw switch, a five-port transfer switch, a six-bit phase shifter, and a five-bit attenuator are realized [23].

Mott Diodes Schottky diodes with fully depleted active layer at zero bias are known as Mott diodes and especially useful in zero bias mixers. In order to adjust the barrier height of the Schottky contact delta-doped layers or SiGe layers may be inserted between the Schottky metal and the active layer [24]. A thin (8 nm) SiGe layer on a n-doped silicon layer increases the barrier height, whereas a SiGe layer on p-layers reduces the barrier height [25].

IMPATT Diodes Impatt diodes are prone to be noisy. This is only partly true, as IMPATT diode design regarding the injection angle and the transit angle can improve the noise behavior significantly [26]. A much more severe drawback is the limited tunability and stability of the IMPATT diodes, which is simply a consequence of the two terminal device. Injection locking is one possible approach to stabilize an IMPATT oscillator [27]. A 73 GHz monolithic IMPATT oscillator can be subharmonically injection locked by a 24 GHz SiGe HBT oscillator [28]. Synchronization is achieved on the third harmonic. Changing the collector current of the HBT-MMIC results in a frequency modulation of the 73 GHz signal.

9.6.7 Summary This chapter tries to give a necessarily selective overview on state-of-the-art SiGe MMIC results. The performance of SiGe MMICs has to be viewed under the consideration of competing approaches — especially CMOS. Recently, K-band low-noise amplifiers using a 0.18 mm CMOS technology with

© 2006 by Taylor & Francis Group, LLC

9.6-1004

The Silicon Heterostructure Handbook

operating frequencies up to 24 GHz, a gain of more than 12 dB, and a noise figure of 5.6 dB have been reported [29]. At 26 GHz still 8.9 dB of gain and a noise figure of 6.9 dB are obtained. The current consumption is 30 mA from a 1.8 V power supply. This result represents the highest operation frequencies reported for LNAs in a standard CMOS process. These results have to be compared with the latest SiGe device and circuit results. Cutoff frequencies are now approaching 400 GHz [30] and the circuit performance at W-band frequencies approaches or even exceeds [11] that of III–V MMICs. The most important advantage of SiGe MMIC concepts is probably the possible co-integration of low-noise, high-current building blocks (e.g., oscillators) with CMOS circuits in order to realize complete single-chip solutions — e.g., a phased array transceiver [31].

References 1. K.M. Strohm, J. Bu¨chler, P. Russer, and E. Kasper. Silicon high resistivity substrate millimeter wave technology. IEEE-MTT-S, 1986, pp. 93–97. 2. U. Guettich. Low cost voltage controlled oscillators for X-band mobile communication purposes realised with Si BTs and SiGe HBTs. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, September 17–18, 1998, Michigan. 3. W. Heinrich. Coplanar waveguide silicon MMICs. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, September 17–18, 1998, Michigan. 4. J.-F. Luy, K.M. Strohm, J. Buechler, and P. Russer. Silicon monolithic millimeter-wave integrated circuits. IEE Proceedings-H 139(3), 1992, 209–216. 5. C. Rheinfelder, K. Strohm, F. Beißwanger, J. Gerdes, F.J. Schmu¨ckle, J.-F. Luy, and W. Heinrich. 26 GHz coplanar SiGeMMICs. IEEE-MTT-S, 1996, pp. 273–276. 6. C. Rheinfelder, K. Strohm, L. Metzger, H. Kibbel, J.-F. Luy, and W. Heinrich. 47 GHz SiGe MMIC oscillator. IEEE-MTT-S, 1999, pp. 5–8. 7. K.M. Strohm, C.N. Rheinfelder, J.-F. Luy, P. Nu¨chter, T. Hess, W. Heinrich, H. Kuhnert, M. Nadarassin, C. Warns, and W. Menzel. Coplanar and microstrip oscillators in SiGeSIMMWIC technology. IEEE-MTT-S, 2001, pp. 1563–1566. 8. H. Kuhnert, W. Heinrich, W. Schwerzel, and A. Schu¨ppen. 25 GHz MMIC oscillator fabricated using commercial SiGe HBT process. Electron. Lett. 36, 2000, 218–220. 9. H. Li, H.-M. Rein, R. Kreienkamp, and W. Klein. 47 GHz VCO with low phase noise fabricated in a SiGe bipolar production technology. IEEE-MWCL 12(3), 2002, 79–81. 10. H. Li, H.-M. Rein, R.-E. Makon, and M. Schwerd. Wide-band VCOs in SiGe production technology operating up to about 70 GHz. IEEE-MWCL 13(10), 2003, 425–427. 11. H. Li, H.-M. Rein, and T. Suttorp. Design of W-band VCOs with high output power for potential application in 77 GHz automotive radar systems. GaAs IC Symposium, 2003, pp. 263–266. 12. W. Winkler, J. Borngra¨ber, and B. Heinemann. A 117 GHz LC oscillator in SiGeC BiCMOS technology. International SiGe Technology and Device Meeting, 2004, pp. 71–72. 13. K.M. Strohm, P. Nuechter, C.N. Rheinfelder, and R. Guehl. Via hole technology for microstrip transmission lines and passive elements on high resistivity silicon. IEEE-MTT-S, 1999, pp. 581–584. 14. S.P.O. Bruce, A. Rydberg, M. Kim, F.J. Beißwanger, J.-F. Luy, H. Schumacher, U. Erben, M. Willander, and M. Karlsteen. Design and realization of a millimeter-wave Si/SiGe HBT frequency multiplier. IEEE-MTT 46(5), 1998, 695–700. 15. J.-J. Hung, T.M. Hancock, and G. Rebeiz. A high-efficiency miniaturized SiGe Ku-band balanced frequency doubler. IEEE-MTT-S, 2004. 16. K.M. Strohm, J.-F. Luy, F. Scha¨ffler, H. Jorke, H. Kibbel, C. Rheinfelder, R. Doerner, J. Gerdes, F.J. Schmu¨ckle, and W. Heinrich. Coplanar Ka-band SiGe-MMIC amplifier. Electron. Lett. 31(16), 1995, 1353–1354. 17. J. Aguirre and C. Plett. 50 GHz SiGe HBT distributed amplifiers employing constant-k and m-derived filter section. IEEE-MTT 52(5), 2004, 1573–1578.

© 2006 by Taylor & Francis Group, LLC

SiGe Millimeter-Wave ICs

9.6-1005

18. I. Gresham and A. Jenkins. A low-noise broadband SiGe mixer for 24 GHz ultra-wideband automotive applications. RAWCON 2003, pp. 361–364. 19. H. Schumacher, P. Abele, E. Soenmez, K. Schad, and T. Teppo. Low-cost Ku to Ka band MMICs using a commercially available Si/SiGe HBT process. Asia Pacific Microwave Conference, 2000. 20. E. So¨nmez, A. Trasser, P. Abele, F. Gruson, K.-B. Schad, and H. Schumacher. 24 GHz high sensitivity downconverter using a commercial SiGe HBT MMIC foundry technology. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 68–71. 21. J.-F. Luy, K.M. Strohm, H.-E. Sasse, A. Schu¨ppen, J. Bu¨chler, M. Wollitzer, A. Gruhle, F. Scha¨ffler, U. Gu¨ttich, and A. Klaaßen. Si/SiGe MMICs. IEEE-MTT 43(4), 1995, 705–714. 22. R. Tayrani, G. Sakamoto, P. Chan, R.v. Leeuwen, and T. Nguyen. X-band SiGe monolithic control circuits. IEEE-MTT-S 1998, 126–134. 23. R. Tayrani, M.A. Teshiba, G.M. Sakamoto, Q. Chaudry, R. Alidio, Y. Kang, I.S. Ahmad, T.C. Cisco, and M. Hauhe. Broad-band SiGe MMICs for phased-array radar applications. IEEE J. Solid State Circuits 38(9), 2003, 1462–1469. 24. K.M. Strohm, J.-F. Luy, T. Hackbarth, and S. Kosslowski. MOTT SiGe SIMMWICs. IEEE-MTT-S 1998, 1691–1694. 25. S. Chattopadyay, L.K. Bera, K. Maharatna, S. Chakrabarti, S. Dhar, S.K. Ray, and C.K. Maiti. Schottky diode characteristics of Ti on strained-Si. Solid-State Electron. 41, 1997, 1891–1893. 26. J.F. Luy and P. Russer, eds. Silicon-Based Millimeter-Wave Devices. Springer-Verlag, Berlin, 1994. 27. J.-F. Luy and P. Russer. SiGe SIMMWICs. IEEE-RFIC Symposium, 1997, pp. 105–108. 28. K.M. Strohm, F. Beisswanger, and J.-F. Luy. A 73 GHz SiGe SIMMWIC module. ESSDERC 97. Proceedings of the 27th European Solid State Conference, Stuttgart, September 1997, pp. 728–731. 29. K.-W. Yu, Y.-L. Lu, D.-C. Chang, V. Liang, and M.F. Chang. K-band low-noise amplifiers using 0.18 mm CMOS technology. IEEE-MWCL 14(3), 106–108. 30. A.D. Stricker, G. Freeman, M. Khater, and J.S. Rieh. Evaluating and designing the optimal 2D collector profile for a 300 GHz SiGe HBT. International SiGe Technology and Device Meeting, ISTDM 2004, pp. 97–98. 31. H. Hashemi, X. Guan, and A. Hajimiri. A fully integrated 24-GHz 8-path phased-array receiver in silicon. IEEE International Solid-State Circuits Conference, San Francisco, February 2004.

© 2006 by Taylor & Francis Group, LLC

9.7 Wireless Building Blocks Using SiGe HBTs 9.7.1

Introduction............................................................. 9.7-1007

9.7.2

Monolithic Components for RFIC Design ........... 9.7-1011

9.7.3

RF Amplifiers ........................................................... 9.7-1020

9.7.4

RF Mixers................................................................. 9.7-1028

What is Different About Designing Circuits at RF? Passives . Bipolar versus CMOS Transistors Low-Noise Amplifiers Transformer Balun-Coupled Mixer . Mixer Comparison and Summary

John R. Long Delft University of Technology

9.7.5

Voltage-Controlled Oscillators ............................... 9.7-1033 Resonant Tanks . Integrated Circuit Oscillators VCO Comparison and Summary

.

9.7.1 Introduction Radio-frequency (RF) circuit design using silicon technologies has progressed over the past decade from small-scale building blocks to complete systems-on-a-chip enabling applications such as 3G wireless telephony [1]. The hundreds of active and passive components used in a handset in the mid-1990s were reduced to a single silicon chip and a handful of passives (filters, capacitors, etc.) by 2000 [2,3]. This was achieved through improvements in the technology, smaller passive components (small and lighter filter packages), and innovations in circuit design and radio architecture. It can be argued that the current success of wireless technology as a consumer product with mass-market appeal has been made possible by the cost, size, and performance advantages of integration on silicon. The performance improvements offered by silicon–germanium heterostructure bipolar transistors (SiGe HBTs) in BiCMOS technologies are enabling even further advances in wireless transceiver performance and integration. The first section of this chapter reviews the aspects of RF circuit design relevant to the design of wireless building blocks. Low-noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO) circuits are then examined in detail. Radio-frequency integrated circuits (RFICs) are constructed using both active and passive devices fabricated directly on a semiconducting substrate. Chip-level integration is possible within the monolithic context, where low complexity circuit blocks (e.g., oscillator, mixer, amplifier) may be combined into a more complex functional block (e.g., transceiver front-end, as shown in Figure 9.7.1). A singlechip transceiver for GSM (global system for mobile communications) capable of operating in both 900 MHz and 1800/1900 MHz bands is a current example of this type of functional integration. The gain-bandwidth product (i.e., fT) of active devices fabricated in both silicon and III–V technologies and representing the current state-of-the-art in production are compared in Figure 9.7.2. It is 9.7-1007 © 2006 by Taylor & Francis Group, LLC

9.7-1008

The Silicon Heterostructure Handbook

Image-reject filter

From T/R Switch (or Diplexer)

To Rx demod. Rx mixer

LNA LO Buffer VCO

Tune input

LO Switch ÷N To synth. Tx Amp

Tx mixer

To power Amp

SSB filter

From Tx mod.

FIGURE 9.7.1 RFIC wireless front-end building blocks.

Transit frequency, f T (GHz)

250 InP DHBT 1.2⫻9µm2

200 SiGe HBT 0.12⫻2.5µm2 150

SiGe HBT 2 0.18⫻5µm

100

Si NMOS 0.13⫻75µm2

50

0 0.01

0.1

1.0 Bias current (mA)

10.0

100.0

FIGURE 9.7.2 Gain-bandwidth product (fT) versus bias current for transistors fabricated using various semiconductor technologies (year 2003).

evident that SiGe HBTs are now competitive with the latest devices fabricated in more exotic materials such as InP. Silicon NMOS devices with 0.13 mm length gates have peak f Ts of approximately 70 GHz while the SiGe bipolar devices have an f T of 200 GHz at the same lithography level (0.12 2.5 mm2). The fT for a 0.12 2.5 mm2 SiGe transistor peaks at about 2 mA, while typical Si-NMOS or InP devices require almost ten times more current to reach their fT peak. Consequently, circuits can be constructed in silicon–germanium technology that consume less current (and therefore less power) than in other technologies. SiGe BiCMOS technology offers the added advantage that many more transistors — meaning more memory and more system functions — can be integrated onto a single chip. In many

© 2006 by Taylor & Francis Group, LLC

Wireless Building Blocks Using SiGe HBTs

9.7-1009

wireless circuits the use of SiGe devices lowers the number of parts needed to build a mobile phone handset which also lowers the cost, and improves the talk-time from a single charge of the batteries. The impressive improvements in active device bandwidth that result from scaling are likely to continue. However, the performance of on-chip passive components and interconnections as well as the packaging technology for off-chip interconnections have not kept pace with the improvements in active device performance. This presents a bottleneck to the development of silicon as a true RF/MMIC platform, where both high-performance passive and active components are integrated together using the same technology.

What is Different About Designing Circuits at RF? There are a number of aspects of circuit design at radio frequencies that make it different from circuit design for lower frequency applications. Some are related to frequency, that is, attempting to operate a transistor or circuit close to its frequency limit, and the difficulties of testing and measuring such a circuit or component in the GHz frequency range. Other differences arise from the way the circuit is used in a system, and the specifications and terminology used to describe RF and high-speed circuitry. In addition, there are many simulators designed specifically to solve RF design problems, so designers must be familiar with the various simulation techniques and design methodologies. Analog RF circuit requirements demand much more than fast switching speeds between binary states and the capability to pack an enormous number of devices onto a single chip. For example, the analog interface between the RF communications channel and the baseband digital signal processor in a cellular telephone demands the ability to detect microvolt signal levels, while keeping the harmonic and intermodulation distortion produced by much stronger interferers within acceptable limits. Also, tetherless communications devices such as cellular telephones and wireless LAN interfaces must be light and portable, which makes factors such as size and battery lifetime important to the RF circuit designer. High Frequency and High Speed Defined Many linear circuits might not appear to involve ‘‘high frequencies’’ or ‘‘high speed,’’ but these terms are related to the bandwidth limitations of the active devices used in the design. The frequency range over which bandwidth-limited instability occurs in most circuits lies between the 3 dB bandwidth, fbw, and the unity gain frequency, funity-gain. Thus, we will define the ‘‘high-frequency’’ region to be between fbw and funity-gain. For a bipolar transistor, this region lies between fb and fT. For a SiGe HBT with a current gain b of 100 at kHz frequencies and an fT of 100 GHz, this implies that the high-frequency range lies above 1 GHz. ‘‘High-speed’’ implies a device or circuit with a frequency range extending into the highfrequency regime, where the maximum frequency of operation lies in the range from 0.1fT to 0.5fT. Transmission Line Effects One of the benefits of the small physical dimensions inherent in integrated circuit technology is that propagation delays along interconnections are usually dominated by component parasitics, which makes them relatively easy to analyze. For example, a 1 GHz signal sees a phase shift of less than 38 across a 1 mm connection corresponding to a traveling time or ‘‘time-of-flight’’ of 8 psec. This is tiny compared to the delays caused by resistances and capacitances present in CMOS circuits. Because these conditions have prevailed since the early years of IC development, popular circuit analysis programs such as SPICE and Spectre1 implicitly assume that all circuit components behave as lumped elements. The ‘‘time-of-flight’’ over interconnect wiring is normally neglected but becomes significant at multiGHz frequencies. This is partly due to the fact that the average wiring length in circuits is not shrinking as quickly as the transistor dimensions. The physical space required by resistors, capacitors and inductors, power supply wiring, and interconnect bondpads, as well as the need to physically separate circuits as a way of reducing electrical interference between blocks, keeps wiring lengths between 10 and 100 mm within circuit blocks and approaching 0.5 to 1 mm between blocks of circuitry.

© 2006 by Taylor & Francis Group, LLC

9.7-1010

The Silicon Heterostructure Handbook

The millimeter-wave frequency range (wavelengths of 10 mm or less in air) corresponds to a frequency of 12 GHz or more for signals traveling on a conventional silicon IC (effective permittivity of 6). Above these frequencies, the wavelength encountered on-chip approaches the length of a typical interconnect wire and time-of-flight delays become important. Wires no longer behave as a simple lumped resistor–capacitor filter, but begin to look like transmission lines. This indicates that a change in the computer-aided design (CAD) tools used to analyze circuits is needed, and also that a shift toward the methods used by microwave circuit designers to synthesize higher frequency circuits will follow. For off-chip interconnections, however, these transmission line effects occur at much lower frequencies. Any interconnection that has a physical length greater than one-tenth the wavelength of the highest frequency component in the signal must be treated as a transmission line, because the effects of time delay over the interconnection affect the circuit behavior. Aside from an RF transmitter and antenna, common examples of transmission lines are: the data bus between a microprocessor and RAM module in a personal computer, a hydroelectric generating plant and an electrical substation several hundred miles away, or the video connection between a DVD player and video monitor. To the circuit designer, transmission line effects imply that impedance must also be closely controlled so that signal reflections and the ringing of pulse waveforms (or ‘‘signal integrity’’) do not impair performance. For example, an ideal voltage amplifier (infinite input impedance, zero output impedance) would not be suitable as an interface to an RF antenna as power could not be efficiently transferred to or received from the antenna. Also, since interconnect cable lengths in a typical measurement setup for an RF circuit are approximately 1 m or more (about 0.2l in electrical length at 1 GHz), transmission lines and their behavior must be understood in order to test and characterize RF and high-speed circuits. While transistor transit frequencies in production technologies move beyond 100 GHz, interconnect bandwidth and passive component parasitics are not scaling with the minimum transistor feature size (e.g., MOSFET gate length). As a result, improvements in RF circuit performance that could capitalize on advances from scaling continue to be constrained by the environment surrounding nanometer-sized active devices. This includes on-chip interconnects, imperfections in passive components that process the voltages and currents in an analog circuit, packaging parasitics (e.g., bondwires), as well as the printed circuit or other sub-assemblies. Despite these problems, there are components available at RF that are not realizable at lower frequencies as illustrated by the chip micrograph of Figure 9.7.3 [4]. In this circuit, a symmetric inductor (synthesized from on-chip transmission lines) improves input power matching and also minimizes the noise figure of a differential low-noise preamplifier (LNA). The transmission line interconnection between the bondpad and LNA form part of the matching network. Interstage signal coupling and bias isolation between the LNA and two balanced mixers are implemented using an on-chip three-filament transformer. Magnetic components enable sub-1 V operation with reduced current consumption and wider dynamic range (i.e., lower noise and distortion) at the cost of additional circuit area. Superior device matching and potential for large-scale integration on silicon

Double-balanced Mixer 1 Multi-filar transformer

Low-noise amplifier (LNA) Symmetric inductor

Double-balanced Mixer 2 Microstrip line MIM capacitor

FIGURE 9.7.3 Passives on a 5 to 6 GHz band single-sideband receiver IC.

© 2006 by Taylor & Francis Group, LLC

Wireless Building Blocks Using SiGe HBTs

9.7-1011

chips enable system architectures such as single-sideband converters (e.g., Figure 9.7.3) with baseband signal process and self-calibration schemes. Consequently, this saves on component costs and size while at the same time improving system reliability and manufacturability.

9.7.2 Monolithic Components for RFIC Design Building blocks for wireless applications perform a variety of specialized tasks that have stringent requirements on sensitivity, distortion, bandwidth, spectral purity, and power output. Circuit performance can be optimized for a given task when a wide variety of on-chip components are available for designers to choose from. Many SiGe BiCMOS technologies offer processing options (e.g., thicker interconnect metal, linear capacitor, polysilicon resistor, etc.) that improve analog–RF performance beyond what is available from a high-volume technology designed for digital applications. The following sections review the attributes of passive and active components typically found in a SiGe BiCMOS technology from an RF circuit design perspective.

Passives Monolithic circuit technologies for RF and microwave circuit fabrication usually consist of a mixture of passive lumped elements (i.e., R or C components with electrical dimensions less than approximately 0.1 times the wavelength) and passive distributed elements (e.g., components constructed from transmission line sections that are a electrically large, such as spiral inductors). However, it is difficult to realize a pure ‘‘lumped’’ element within the monolithic context, because the parasitics to ground or to the substrate affect the performance of any on-chip component. Lumped elements are relatively simple to model for circuit simulation, and these models are suitable for design up to approximately 20 GHz. At frequencies beyond 20 GHz, distributed element circuit models are the most useful for a manufacturable design. Transmission Line Interconnections Transmission lines interconnect circuit components, subsystems, and systems. At millimeter-wave frequencies (i.e., above 12 GHz on a silicon chip), all on-chip interconnections are considered transmission lines and impedance matching between any two-circuit nodes is necessary to preserve signal integrity and maximize efficiency. There are three basic conductor configurations for IC transmission lines: microstrip, coplanar waveguide, and coplanar stripline, where microstrip is the simplest and most popular configuration. The unique properties of transmission lines enable the implementation of monolithic inductors, balanced-to-unbalanced transformers (baluns), and other components that often outperform active circuit equivalents at microwave frequencies. However, existing microwave circuit designs cannot be ported directly to a silicon RF IC without initially considering the limitations and properties of interconnections, which are described in this section. In modern silicon technologies, up to eight layers of metal are now used to reduce the ‘‘interconnect bottleneck’’ in digital VLSI circuits. Minimum dimensions are on the order of the metal thickness, which is currently about 0.5 mm for most metal layers, and 1 to 2 mm for top metal supply and ground busses. The shift to multilevel metallization schemes has also led to an increase in the thickness of the intermetal dielectric that separates the top metal layer and the semiconducting substrate (typically 5 to 8 mm). An additional benefit of thicker oxide is lower attenuation for microstrip transmission lines fabricated in production silicon processes, at least in the 1 to 5 GHz range of frequencies. However, the limitations imposed by the interconnecting metals and the conductive substrate continue to constrain the performance of circuits. The semiconducting substrate degrades the performance of any transmission line fabricated on a silicon chip. ‘‘Skin-effect’’ and ‘‘slow-wave’’ modes of propagation may exist in addition to the quasitransverse electromagnetic (quasi-TEM) mode seen in microstrip lines on insulating substrates [5]. SiGe-BiCMOS technologies developed for mixed-signal and RF applications employ medium resistivity

© 2006 by Taylor & Francis Group, LLC

9.7-1012

The Silicon Heterostructure Handbook

substrates (usually between 10 and 20 V-cm) where the skin-effect mode is not present. Therefore, the slow-wave and quasi-TEM modes are of more interest for RF IC design. The quality (or Q) factor is often used to compare passive components such as inductors and capacitors. The transmission line Q-factor is derived from a resonant tank built using a one-quarter of a wavelength long line at the resonant frequency, v0. The Q is then given by the ratio of bandwidth to v0, or Q ¼ v3 dB/v0. Energy dissipated in the conductor metals, the substrate, or radiated to the surrounding environment reduces the Q, as illustrated in Figure 9.7.4(a) for three widths of microstrip transmission line (5, 10, and 20 mm). The relationship between Q-factor, strip width, and frequency follows from the attenuation of the microstrip line, with the wider lines having a larger Q at very low frequencies and the narrower lines having higher Qs above 3 to 4 GHz. It is interesting to note that the Q initially rises, dips, and then rises again as the frequency increases. This follows from the plateau in attenuation — as the attenuation per wavelength decreases at higher frequencies, Q-factor improves [6]. Since radiation is negligible for electrically short transmission lines (i.e., they are not antennas), the total Q-factor can be expressed as QTotal QConductor k QSubstrate

(9:7:1)

where QConductor is the Q-factor associated with the current loop (e.g., conductor metal and losses due to current induced in the substrate) and QSubstrate is the quality factor of the shunt parasitics (e.g., dissipation of the electric field in the silicon). As seen from Figure 9.7.4(b), the total Q is dominated by

Quality factor Q

8.0

w = 5µm w = 10µm

6.0

w = 20µm 4.0 2.0 0 0

5

10

15 20 25 Frequency (GHz)

30

35

40

(a) Measured Q-Factor for 3 different widths of microstrip on silicon 40 Quality factor Q

Q Total Q Conductor

30 Q Conductor 20

Q Substrate w = 10mm

Q Substrate Q Total

10 0 0

5

10

15 20 25 30 35 40 Frequency (GHz) (b) Constituent components of the Q-Factor for w = 10µm (microstrip on silicon)

FIGURE 9.7.4 Measured Q-factor for microstrip lines on a 15 V-cm substrate (toxide ¼ 5.8 mm, tsilicon ¼ 200 mm, tmetal ¼ 2.1 mm aluminum).

© 2006 by Taylor & Francis Group, LLC

9.7-1013

Wireless Building Blocks Using SiGe HBTs

shunt parasitics. These results are typical of current silicon technologies. The greatest improvement in Q comes from reduction of losses to the substrate, and there is less to be gained from increasing metal thickness. A relatively simple RLC model for microstrip lines on silicon is shown in Figure 9.7.5. It consists of a constant inductance in series with a frequency-dependent resistor that models skin effect in the conductors. Coupling to the substrate is via capacitors Cox, with dissipation modeled by resistor rSi. Capacitor CSi models the transition between slow-wave and quasi-TEM modes. An L–R ladder network (lower part of Figure 9.7.5) models the skin effect for time-domain simulations [7]. At low frequencies, the total dissipation is the combined effect of the parallel network of resistors r1rm. As the frequency increases, series inductors Lsk1Lskm block current flow through the resistors and cause the desired frequency-dependent dissipation. The measured attenuation constant for a 1 mm long microstrip line is compared to one- and twosection lumped element models extracted from measurements in Figure 9.7.6 [8]. The lumped element equivalent circuit is valid over the frequency range where the component length (in this case 1 mm) is less than approximately one-tenth of the signal wavelength. This corresponds to a maximum frequency of 13 to 14 GHz assuming quasi-TEM propagation with an effective permittivity of 5. As seen in Figure

Cox

Cox

Cox CSi

Ls

rs(f )

Ls

RSi

CSi

RSi

Ls

rs(f )

Cox

CSi

RSi

(a) 1-section model

Ls

rs(f )

CSi

Cox RSi

CSi

(b) 2-section model

rs(f )

Lskm

rm

Lsk2

r2

Lsk1

r1

L1

(c) LR skin effect model

FIGURE 9.7.5 Microstrip-on-silicon transmission line models.

Attenuation constant (Np/mm)

0.3 0.25

measured

0.2

1-section model 2-section model

0.15 0.1 0.05 0 0

10

20 Frequency (GHz)

30

FIGURE 9.7.6 Experimental verification of transmission line models.

© 2006 by Taylor & Francis Group, LLC

40

RSi

9.7-1014

The Silicon Heterostructure Handbook

9.7.6, the one-section model begins to deviate significantly from the measured data around 15 GHz, while the two-section model remains reasonably accurate to almost 40 GHz. This validates both the lumped-element model and its accuracy for CAD purposes in both slow-wave and quasi-TEM modes for RF design up to mm-wave frequencies on silicon. Capacitors and Resistors Capacitors are used for ac coupling and decoupling as well as tuning of narrowband or resonant circuits. Larger capacitance values are realized using the metal–insulator–metal (MIM) structure or a combination of interdigitated metal fingers and multiple metal interconnect layers. In a multi-metal layer technology, all but one of the metal layers can be used for the capacitor plates with the bottom layer as a substrate shield, which gives a specific capacitance of approximately 1 to 2 fF/ mm2 of chip area when five to six metal layers are used. A vertical plate configuration gives a high-density MIM capacitor where the plate separation is primarily defined photolithographically [9]. As a result it has less tolerance in processing than a horizontally stacked capacitor, where the insulator thickness can vary by 10% to 20%. A bottom metal shield blocks electric field leakage and associated losses to the underlying semiconductor. A similar layout scheme is used for bondpads (i.e., topmetal and shield layers only) connected to sensitive nodes, such as the input to a low-noise preamplifier. The physical dimensions of MIM capacitors are normally small compared with a wavelength in the dielectric, and so the equivalent circuit of Figure 9.7.7 models the electrical behavior up to about 30 GHz. Resistance Rplate is typically two thirds of the total electrode resistance (note that the skin effect increases R over the dc value) and Lplate is the electrode inductance, CMIM is plate-to-plate capacitance, and conductance Roxide represents the losses in the dielectric film (often negligible). Parasitics of the shield are represented by a series RC circuit. Resistors are required as loads and terminations and for the biasing of RF and microwave circuits. Polysilicon resistors are common in silicon IC technologies (see Figure 9.7.8). Often, only a single-sheet resistivity in the 10 to 30 V/sq. range (i.e., unsilicided gate polysilicon) is available, which limits applications to load resistances on the order of tens to a few hundred ohms. Polysilicon films in mixed-signal technologies are doped separately, allowing multiple sheet resistivities. Power handling is of the order of 100 mW/mm2. The temperature dependence of doped polysilicon depends upon whether

R plate

L plate

T1 R oxide

R Shield

C MIM

C Shield

L plate

R plate

Shield

T2

FIGURE 9.7.7 Lumped-element MIM capacitor model.

Field Oxide

SiO2 Si

R dc/n

R dc

Rpoly Cox 2

Cox 2 IC-CAD Model

FIGURE 9.7.8 Polysilicon resistor structure and models.

© 2006 by Taylor & Francis Group, LLC

Cox 2n

Cox n

R dc/n Cox n

Cox 2n

n-Section distributed model

Wireless Building Blocks Using SiGe HBTs

9.7-1015

p- or n-type dopant is used, with tolerances typically in the +15% to 20% range. A metal film resistor, by contrast, has a typical sheet resistivity of 50 V/sq. with a tolerance of +5%. The frequency limitation of resistors is normally not captured in analog IC design tools, and it is the designer’s responsibility to adjust the resistor model by adding (RC) sections as required. The ICCAD model for the resistor is a simple p-topology (Figure 9.7.8), which is valid to a frequency of approximately fmax ¼ 0:145=Rdc Cox

(9:7:2)

Rdc is the dc resistance between the resistor’s terminals and Cox is the total parasitic capacitance to the substrate. Above this frequency, a larger number of p-sections are needed to model the distributed RC network formed by the polysilicon, oxide, and substrate. For example, at 2 GHz this implies 73 fF (maximum) parasitic capacitance for a single-section IC-CAD model of a 2 kV resistor. Above 2 GHz a lumped equivalent circuit can still be used, however multiple R–C sections in cascade (as shown in Figure 9.7.8) are required to accurately model the electrical behavior. Inductors and Transformers Planar inductors for monolithic circuits are useful for interstage matching and coupling, as resonant loads, and for biasing and bias circuit isolation in RF IC applications [10, 11]. They can be realized in a number of configurations, all implemented (at minimum) using a single-layer metallization scheme and as on-chip transmission lines (i.e., a microstrip line). The total line length must be kept at a small fraction of a wavelength; otherwise the conductor cannot be treated as a lumped element. These components only approximate lumped inductors and in this sense they do not have a low-frequency equivalent for monolithic design compared to on-chip capacitors, which are also used in monolithic circuits for signal processing from audio to radio frequencies. They can also be used to implement components that are unique to RF circuits, such as transformers [7,12–14]. Resonant-tuned (LC) circuits offer many benefits to the designer of high-frequency circuits. Operation at a low supply voltage, simplified impedance matching between stages, and low dissipation for reduced circuit noise are just a few of the properties of LC circuits that can be exploited to achieve a higher level of performance. However, an on-chip inductance is required for the realization of LC networks for these purposes. At radio and microwave frequencies, a purely passive inductor is often preferable to synthesis of an inductive reactance with an active circuit. Passive components introduce less noise, consume less power, and have a wider bandwidth and linear operating range than their electronic equivalents, such as the gyrator. Prior to the mid-1990s, silicon integrated circuit (IC) technology was rarely used for analog applications in the radio and microwave range of frequencies, in part because transmission line structures performed poorly on a semi-conducting substrate. However, suitable performance can be realized when the limitations imposed by the technology are understood by designers and the components are accurately modeled and characterized. For dimensions typically encountered in a commercial IC fabrication process (metal line-widths between 2.5 and 50 mm on a 350-mm thick substrate), the characteristic impedance of a microstrip line ranges from approximately 100 to 200 V. The substrate behavior depends upon both the resistivity and the frequency of the propagating wave. However, the substrate tends to behave as a lossy dielectric in modern silicon VLSI processes, where resistivities are typically in the 10 to 20 V-cm range (i.e., for ‘‘analog’’ or mixed-signal technologies) and operation is in the GHz range of frequencies. Low-ohmic substrates (i.e., resistivities below 0.1 V-cm) are often used for VLSI digital circuit fabrication to suppress latch-up when the highest packing density is required. Substrate current is easily induced immediately beneath a coil on a highly conductive substrate by the alternating magnetic field, which reduces the inductance and causes additional losses. The operation of a passive transformer is based upon the mutual inductance between two or more conductors, or windings. The transformer is designed to couple alternating current from one winding to the other without a significant loss of power, and impedance levels between the windings are

© 2006 by Taylor & Francis Group, LLC

9.7-1016

The Silicon Heterostructure Handbook

transformed in the process (i.e., the ratio of terminal voltage to current flow changes between windings). In addition, direct current flow is blocked by the transformer, allowing the windings to be biased at different potentials. Interwinding microstrip spiral inductors to magnetically couple independent conductors is a logical extension of this concept, and results in a monolithic transformer as shown in Figure 9.7.9(a). Frlan and Rabjohn [7] demonstrated square spiral transformers on alumina and GaAs substrates, and developed circuit simulation tools based upon the extraction of a lumped element model for the transformer from physical and geometric parameters. This modeling technique was later extended to the analysis of planar structures on conductive substrates, such as silicon. In the recent literature, there are many examples of monolithic transformers fabricated in silicon IC technology for use in RF circuits, such as preamplifiers, oscillators, mixers, and power-amplifiers. For the transformer, magnetic flux produced by current iP flowing into the primary winding at terminal P, induces a current in the secondary winding that flows out of terminal S. This produces a positive voltage, vS across a load connected between terminals S and S¯. The main electrical parameters of interest to a circuit designer are the transformer turns ratio n, and the coefficient of magnetic coupling, km. The current and voltage transformations between windings in an ideal transformer are related to the turns ratio by the equation n¼

vS iP ¼ ¼ vP i S

rﬃﬃﬃﬃﬃ LS LP

(9:7:3)

where the primary and secondary voltages (vP, vS) and currents (iP, iS) are defined in Figure 9.7.9(b), and LP, LS are the self-inductances of the primary and secondary windings, respectively. The strength of the magnetic coupling between windings is indicated by the k-factor, M km ¼ pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ LP LS

(9:7:4)

where M is the mutual inductance between the primary and secondary windings. The self-inductance of a given winding is the inductance measured at the transformer terminals with all other windings opencircuited. If the magnetic coupling between windings is perfect (i.e., no leakage of the magnetic flux), km is unity, while uncoupled coils have a k-factor of zero. A practical transformer will have a k-factor somewhere between these two extremes. Since the materials used in the fabrication of an IC chip have magnetic properties similar to air, there is poor confinement of the magnetic flux in a monolithic

P iP

iS 1:n

P

P

S

vP S

vS P

S

S (a) Physical layout

(b) Schematic symbol

FIGURE 9.7.9 A 1:1 Frlan-type planar transformer. (After JR Long. IEEE Journal of Solid-State Circuits 35:1368– 1382, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.7-1017

Wireless Building Blocks Using SiGe HBTs

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ transformer and M < LP LS . Thus, the k-factor is always substantially less than one for a monolithic transformer, however, coupling coefficients as high as 0.9 are realizable on-chip. The phase of the voltage induced at the secondary of the transformer depends upon the choice of the reference terminal. For an ac signal source with the output and ground applied between terminals P and P¯, there is minimal phase shift of the signal at the secondary if the load is connected to terminal S (with S¯ grounded). This is the noninverting connection. In the inverting connection, terminal S¯ is grounded and S is connected to the load so that the secondary output is antiphase to the signal applied to the primary. Aside from the phase shift between input and output ports, other aspects of the transformer’s electrical behavior depend upon the choice of terminal configuration. An example of a compact model for a transformer with four independently driven ports (i.e., P, P¯, S, and S¯) and turns ratio 1:n is shown in Figure 9.7.10. In many applications, the compact model can be further simplified because one (or more) of the ports is grounded. At the core of the model is an ideal linear transformer with magnetizing inductance, Lm and turns ratio 1:n. The path for magnetic flux between windings has the same permeability as free space for conventional IC technologies (unless, for example, a ferromagnetic layer is used in fabrication), and therefore, the magnetizing inductance is lossless and the magnetic path is highly linear. Note that this is an advantage in RF IC applications, where the dynamic range (and hence linearity) requirements are very demanding. Inductances LP and LS are placed in series with the primary and secondary windings of the linear transformer to account for imperfect coupling or leakage of the magnetic flux between the windings. Resistors rP and rS are placed in series with the leakage inductances representing ohmic losses in the windings, which are significant due to the relatively thin layers of metal available in an IC process. The interwinding capacitance is modeled by capacitors connected between primary and secondary, C0 and Cx. The dominant capacitive parasitics between each winding and the underlying substrate (Zsh) are represented by the series connection of capacitors Cox and CSi, and substrate loss is included through the addition of resistor rSi in parallel with CSi, as in the inductor models. Multifilament transformers can also be constructed on-chip. These devices are used to implement power dividers or combiners and baluns. A balun is a device, which couples a balanced circuit to an unbalanced one. There are many structures used to implement baluns at RF and microwave frequencies, although a differential amplifier is the most commonly used circuit for unbalanced to balanced signal conversion on-chip. Microwave balun structures such as the Lange, rat-race, and branch line coupler

Cx1

Leakage and series losses

Co1 P r P/2

S

L P/2 1:n

Zsh1 CP

L S/2

Zsh3

Substrate Parasitics

CS

Lm

Ideal Transformer Zsh4

Zsh2 r P/2 P

r S/2

L S/2

L P/2 Co2

r S/2 S

Cx2

FIGURE 9.7.10 1:n transformer compact model. (After JR Long. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.7-1018

The Silicon Heterostructure Handbook

require physical dimensions on the order of the signal wavelength and so these devices consume too much chip area when operating below approximately 15 GHz. The transformer shown in Figure 9.7.9 can also implement a balun by grounding one of the windings at the electrical center, or center tap. The electrical and physical centers of an asymmetric winding differ, which is a disadvantage of asymmetric layouts. A square symmetric layout, first proposed by Rabjohn [7] and illustrated in Figure 9.7.11, solves this problem. This transformer consists of two groups of interwound microstrip lines that are divided along a line of symmetry running horizontally, as shown in the figure. The groups of lines are interconnected in a way, which brings all four terminals to the outside edge of the transformer layout, which is an advantage when connecting the transformer terminals to other circuitry. Also, the mid-point between the terminals on each winding, or the center tap, can be located precisely in the symmetric layout as indicated in Figure 9.7.11. The turns ratio for the example shown is 4:5 between primary and secondary. The measured and simulated responses for this balun are compared in Figure 9.7.12. The experimental transformer is designed with OD ¼ 325 mm, 8 mm linewidth, and 3 mm line spacing. The slight

OD 4:5

P P

ID

P

Center taps

S

S

c.t.

c.t.

S Axis of symmetry

S

P

FIGURE 9.7.11 Square symmetric (Rabjohn) balun. (After JR Long. IEEE Journal of Solid-State Circuits 35:1368– 1382, 2000. With permission.) 4:5, W=8 µm, S=3 µm, OD=325 µm dB|S31| tuned

dB|S21| untuned

dB|S31| untuned

Transmission coefficient magnitude (dB)

0.0

Phase error (tuned) Effect of interwinding capacitance

−5.0

5.0

−10.0

0.0

−15.0

−5.0

−20.0

0.0

1.0

2.0 3.0 Frequency (GHz)

4.0

Phase error (degrees)

dB|S21| tuned

−10.0 5.0

FIGURE 9.7.12 Frequency response of a monolithic transformer balun. (After JR Long. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.7-1019

Wireless Building Blocks Using SiGe HBTs

difference in magnitude response at the inverting and noninverting secondary ports is clearly seen from the measurements. This is due to the effect of interwinding capacitance. The effect is not reduced by adding tuning capacitance in shunt with the transformer ports. Capacitors connected at the input and output ports (425 fF across the primary and 1.7 pF across each secondary winding) tune the balun to match the (50 V) source to the secondary load, and the tuned response is also plotted in Figure 9.7.12. The measured transmission loss is reduced from over 5 dB to very close to the ideal (3 dB) by tuning. The phase error between secondary ports of the tuned balun is also shown in the figure, where the phase error is the deviation from a 1808 phase difference between ports. This error is on the order of 18 in the desired passband for the balun (2 to 3 GHz).

Bipolar versus CMOS Transistors Relevant performance attributes of current silicon MOS and bipolar (BJT) devices are compared in Table 9.7.1. The ratio of bias current to transconductance (I/gm) is an indication of the gain that can be realized at a given supply current. This ratio for a MOSFET depends on the effective gate bias voltage (VGSVT), which is on the order of 300 mV, compared to the thermal voltage (kT/q, approximately 25 mV at 278C) for the bipolar. The impedance levels in RF and high-speed circuits are usually kept low because of bandwidth restrictions, so transconductance largely defines the active gain at RF (note that voltage or current gain can also arise from impedance matching; this is a ‘‘passive’’ gain), while the product of the transconductance and output resistance (gm * ro) sets the maximum active gain at low frequency. Gain also depends on parasitics, and the ratio of input to ground to the Miller capacitance (Cin/Cm) in the common-source (or common-emitter) configuration indicates the relative importance of the device parasitic capacitances. Bipolar devices have a clear advantage in both gain and bandwidth. In addition, the input impedance at RF is relatively low compared to a MOSFET. MOS devices can realize voltage gain at the input if a matching network is used to match the transistor input impedance to an RF source (e.g., a 50 V generator). However, low-loss matching elements (with a high Q-factor) are needed. This gives a narrowband frequency response that is susceptible to tolerances and usually requires trimming in manufacture. A bipolar transistor, on the other hand, has a relatively low input impedance making the transistor easier to match to the typical RF source off-chip using a simple, low-Q matching network. Flicker noise is important at frequencies up to the flicker corner frequency (1/f corner), where thermal and flicker noise levels in a device are equal. Aside from baseband circuity, 1/f noise affects oscillator phase noise and mixer noise figure in homodyne receivers with intermediate frequency stages that operate below the flicker corner frequency. Therefore, it is desirable that 1/f corner frequency should be kept as low as possible. Breakdown voltage is important in circuits where either high voltages or high power outputs are required. For MOS devices, the breakdown depends mainly on the gate oxide, which will fail when the applied voltage exceeds the breakdown strength. This is 1.8 V for 0.18 mm gate length devices, but downscaling of the gate length in future generations of MOS devices will lower the breakdown voltage even further (e.g., 1.2 V for 0.13 mm technologies). In bipolar technology, breakdown voltage is defined by the collector–emitter breakdown voltage when there is a high impedance path for current flow from the base terminal to ground. The collector–base breakdown voltage (which is two to three times higher TABLE 9.7.1 Silicon MOSFET and BJT Comparison Parameter

MOS

BJT

I/gm Cin/Cm 1/f corner ro at 5 mA bias Breakdown voltage

Veff/2 3 1 MHz 1 kV 1.8 V

VT 10 1 kHz 10 kV 2–5 V

© 2006 by Taylor & Francis Group, LLC

9.7-1020

The Silicon Heterostructure Handbook

than VCEO) is more relevant to RF circuits, since excess electrons created by impact ionization in the base region have a relatively low impedance path out of the transistor’s base terminal. The Johnson limit, which is the product of breakdown voltage (VCEO) and fT for the BJT is approximately constant, and is approaching 300 GHz-V for current SiGe devices. Other considerations for high-frequency are CAD model accuracy and the accuracy of the CAD design kits that are available to the designer. Deep sub-micron MOS models (e.g., the industry-standard, BSIM3) are not scalable or accurate enough for RF analog design without extensive modification. Newer generations of MOS models (e.g., BSIM4 or Philips’ MOS Model 13 and above) offer substantial improvements in small- and large-signal simulation accuracy. Bipolar models have improved considerably over the past decade. The latest bipolar models (VBIC, MEXTRAM, and HiCuM) are fully scalable and have demonstrated excellent accuracy in RF and high-speed applications.

9.7.3 RF Amplifiers Radio-frequency amplifiers are used in both broadband and narrowband applications. Broadband applications in the 1990s were dominated by high-speed data communication using optical fiber. However, the demand for wireless functionality and greater data throughput have opened up new opportunities for wireless circuits operating in bands from below 500 MHz to above 60 GHz. These systems can be considered ‘‘broadband,’’ as their operating bandwidth is greater than 10% of the midband frequency. For example, 1 GHz of bandwidth centered at 10 GHz is a broadband signal according to this definition. SiGe bipolar and BiCMOS are enabling technologies for these new wireless applications, which will develop over the coming decade. However, SiGe technology has already had a considerable impact on the evolution of cellular telephony and third-generation (3G) mobile telephone hardware. LNAs for receivers are described in this section.

Low-Noise Amplifiers The low-noise preamplifier (LNA) suppresses noise introduced by the mixer and subsequent stages in the receive chain. The other design objectives for the preamplifier in a radio receiver are: adequate gain, low intermodulation distortion, and terminal impedances, which match the system impedance (50 V is usually assumed). The maximum input signal range for the receiver should be determined by the mixer, so the linearity of the LNA must be greater than the linearity of the mixer (i.e., when mixer linearity is referred to the receiver input). The demand for greater linearity drives up power consumption as more quiescent current is needed to increase linearity for a class A preamplifier. In addition, interfaces at the input and output of the integrated circuit amplifier are, in general, off-chip. Therefore, transmission line effects and impedance matching must be considered in the design. Amplifiers or mixers intended for use in the RF and microwave frequency range are characterized using performance measures that are often very different from those used for low-frequency circuits. The power gain and terminal impedances over the amplifier passband are usually specified by the four S-parameters for a two-port network. In addition to these small-signal characteristics, the dynamic range of the amplifier must also be specified. The spurious-free dynamic range (SFDR) is defined by the difference between the signal overload point and the minimum discernible or acceptable signal level at the amplifier input. The minimum input signal level, or sensitivity, can be determined from the amplifier noise figure. The upper limit of the dynamic range is usually set by the distortion (e.g., intermodulation distortion) or gain compression characteristics of the circuit. Third-order intermodulation distortion (i.e., frequencies 2f1–f2 and 2f2–f1 produced by closely spaced input tones at f1 and f2) falls within the desired intermediate frequency (IF) channel bandwidth, and could interfere with signal reception in a heterodyne (or low-IF) radio. The second-order intermodulation distortion products (i.e., frequencies f1–f2 and f2–f1 produced by closely spaced input tones at f1 and f2) have a similar effect in homodyne receivers. The intermodulation distortion is characterized by the intercept specification (e.g., third-order intercept, IP3 or second-order intercept, IP2). The intercept

© 2006 by Taylor & Francis Group, LLC

9.7-1021

Wireless Building Blocks Using SiGe HBTs

point is measured by applying two signal frequencies at the mixer RF input (the two-tone test) and observing the third-order distortion products at the output. The third-order intercept point referred to the input (IIP3) is related to the output intercept (OIP3) by the amplifier gain. Two possible topologies for a common-emitter preamplifier are shown in Figure 9.7.13. The common-emitter (CE) configuration is the best compromise between noise figure, gain and terminal impedances at frequencies approaching the device fT. Parasitic lead inductance from a bond-wire and package pin connected in series with the common (i.e., emitter) terminal adds degeneration to the LNA and lowers the gain. The gain is also affected by the finite output conductance of the transistor, the load impedance, and feedback via the Miller capacitance. A cascode preamplifier (Figure 9.7.13(b)) uses the low impedance of a common-base amplifier to reduce the gain of the input common-emitter stage and suppress the Miller effect. There are other methods of achieving this, however, the cascode is a relatively simple circuit which increases the noise figure by only a small amount (typically 0.5 dB). With a 2.7 V supply, the two transistors in cascode can be biased with sufficient headroom if a resonant tank is used for the output load. Modern SiGe bipolar devices in production have f Ts exceeding 100 GHz, which is well above the operating frequencies for most commercial wireless products (e.g., mobile telephones or wireless computer networking equipment). Therefore, bandwidth can be traded-off for reduced power consumption in the LNA. In addition, the collector–base feedback capacitance (which causes the Miller effect) in a typical common-emitter preamplifier is low enough that a single device (i.e., not a cascode) can be used to realize a gain of 15 to 20 dB at a bias current of a few milli-Amperes. When on-chip resonant circuits are used as loads, the transistor can be biased from a supply as low as VBE (approximately 0.9 V), thereby realizing a true low-voltage and low-power LNA with excellent RF performance. The common-mode rejection inherent in differential and symmetric circuit topologies helps improve the isolation between RF blocks in integrated radio circuits, which is one of the main reasons why the higher power consumption in these circuits is tolerated. The differential pair (Figure 9.7.14(a)) has (ideally) the same noise figure and gain as the single-ended equivalent, but doubles the power consumption compared to a single transistor LNA. As the RF input power is now split across two transistor base–emitter junctions, the distortion produced by the amplifier for a given input power level is lower than for a single transistor amplifier. Also, an explicit ground connection is not required as there is a virtual ground at the common terminal in a differential amplifier driven by a balanced (i.e., differential) signal, so ground path parasitics (e.g., bondwire inductance and package inductance, Figure 9.7.14(b)) do not affect the amplifier’s gain. When distortion is considered, the linearity of the common-emitter amplifier alone (i.e., without feedback) is poor, with the input-referred third-order intercept (IIP3) typically in the 12 to 20 dBm

VCC VCC i µ≈

Miller effect: ZLOAD

i µ = (Av–1)sCµ•Vin

(

–g m1 g m2

(

VOUT VIN

Parasitic degeneration

Cµ

Q1 LEE

Z LOAD

–1 sCµ•Vin

VOUT Q3

Q2

VAGC+ VIN

VAGCCµ

Q1 LEE

(a) Common-emitter amplifier

(b) Cascode CE with AGC

FIGURE 9.7.13 Simple common-emitter and cascode preamplifier topologies.

© 2006 by Taylor & Francis Group, LLC

9.7-1022

The Silicon Heterostructure Handbook

V CC V CC Z LOAD

V IN+

Z LOAD

V OUT − + Virtual ground Q1

Q2

V IN-

Z LOAD V IN

Q1

V OUT Parasitics from bondwire and package often dominate

L EE L EE (a) Differential amplifier

FIGURE 9.7.14

(b) Common-emitter amplifier

Differential and common-emitter preamplifiers.

range. Intermodulation and harmonic distortions can be avoided by increasing the transistor bias current and the power supply voltage. However, a large bias current and a high supply voltage (which would be chosen to achieve high gain and good linearity) cannot be used in a low-power or low-voltage amplifier design. The amplitude of the base–emitter voltage drives the ‘‘active’’ or device-related distortion produced by the transistor. Negative feedback is often applied to an amplifier to reduce the base–emitter voltage for a given output voltage swing, thereby improving the linearity at the expense of lower gain. Hence, feedback can be an alternative to increasing the bias current for a low-power design, since it is well known that negative feedback can improve the linear input signal range of an amplifier, even though the active device itself might be operating in a relatively non-linear manner. The impedances presented at the input and output ports of an RF amplifier at frequencies other than the desired operating frequency (i.e., frequencies other than the fundamental) also have a profound effect on the intermodulation (IM) distortion in common-emitter amplifiers [15–17]. The amplitude and phase of unwanted sum and difference frequencies caused by device nonlinearities contribute to third-order intermodulation distortion by mixing with the RF signal at the input. One source of distortion is the difference frequency between two in-band RF input tones. This relatively low frequency signal can be attenuated by keeping the impedance of the bias path at the amplifier input as small as possible at low frequencies. However, it has been shown that the optimum value of the impedance seen at low frequencies is not zero, but rather finite and complex [16]. Also, the second harmonic of the RF signal is fed from the output back to input via the collector–base capacitance, where it mixes with the fundamental tones thereby generating third-order IM distortion. Attenuating the second harmonic at the RF input will reduce this source of distortion. Neutralizing the feedback from output back to input will also diminish this source of inter-modulation distortion. Circuitry (often passive), which eliminates the low frequency and second harmonic signal at the input, are called out-of-band terminations. Fifth-order intermodulation also has a greater effect on signal fidelity as third-order intermodulation distortion is reduced. While these impedances placed at the input to terminate out-of-band harmonics demonstrably reduce the IM distortion, experimental measurements also show that the improvement decreases with input amplitude and operating frequency. As the fundamental frequency approaches the bandwidth limitations of the transistor, the IM distortion increases. Moreover, the IM distortion improvement is realized only in the small-signal regime and distortion increases rapidly with RF input amplitude (power levels greater than about 30 dBm for a 50 V input impedance). Cascode LNAs Cascode preamplifier designs are popular because they offer wide bandwidth and excellent reverse isolation, which simplifies impedance matching and minimizes local oscillator (LO) leakage from the mixer back to the antenna via the LNA. The tendency of single-ended cascodes to oscillate is lower for a differential design because the base terminals of the cascode devices are at a virtual ground for the differential-mode signal. However, the series connection of two devices does require a larger supply

© 2006 by Taylor & Francis Group, LLC

9.7-1023

Wireless Building Blocks Using SiGe HBTs

voltage for proper biasing. A single-ended equivalent circuit for a differential cascode preamplifier biased from a 2.7 V supply is shown in Figure 9.7.15. The collector inductor has virtually no dc voltage drop and allows the output node to swing to 2VCC. Saturation of Q1 must be avoided so VCE1 is set to 1 V (about 100 mV greater than VBE). The maximum voltage swing across Q2 is therefore 1.5 V-pk if 0.2 V is allowed for VCEsat of Q2. The bias current is typically chosen to meet linearity requirements from consideration of the clipping level at the output. Insight into the optimization of microwave transistor noise figure comes from an analysis by Fukui, who derived an analytical solution for the transistor noise figure based on the hybrid-p model for the BJT. Fukui derived complete algebraic expressions for the four noise parameters in terms of the hybrid-p equivalent circuit parameters, including the effects of packaging parasitics. These expressions contain a large number of terms, and such detail is already captured in a modern CAD tool for use by RF designers today. However, the results of the analysis show that the minimum noise figure at high frequency for the device can be estimated using the following formulation for the minimum noise factor, Fmin, Fmin jhigh frequency

rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ! 2 1þh 1þ 1þ h

(9:7:5)

where 0 h ¼ gm rbb

2 f fT

(9:7:6)

Here, it is assumed that the dc and low-frequency current gains (bdc and bo) of the transistor are large. These current gains depend upon a number of factors, such as the technology (e.g., base doping), the collector current and the ambient temperature. The dc and ac current gains for SiGe bipolar transistors are both approximately 100 at low-medium collector current densities, so this condition is normally fulfilled. There is an additional restriction; the dc current gain should satisfy the following condition: 2 fT bdc > 10 f

(9:7:7)

Assuming an operating margin (i.e., fT/f ) greater than three and a dc current gain of 100, this restriction will also be satisfied. Fukui’s estimate for the minimum noise factor at high frequency (Equation (9.7.5) and Equation (9.7.6)) indicates that the collector bias current, which determines the transconductance (gm) and the transit frequency ( fT) of the device, must be selected in conjunction with the device size in

V CC = 2.7 V RL

0V

Q2 1.85 V

1.7 V Q1

0.85 V

1V Lee

AssumeV BE=0.85 V

FIGURE 9.7.15 Single-ended equivalent circuit for a differential bipolar preamplifier showing bias voltages.

© 2006 by Taylor & Francis Group, LLC

9.7-1024

The Silicon Heterostructure Handbook

order to minimize the transistor noise figure. As the frequency increases, the factor ‘‘h’’ also increases, which results in an increase in the minimum noise factor as predicted by Equation (9.7.5) for a typical bipolar device. Thus, the dominant term in the noise factor for a common-emitter amplifier at high frequencies is Noise factor ¼ agm

0 rbb

2 f fT

(9:7:8)

Minimum noise figure, NFmin (dB) at 5.5 GHz

This prediction is consistent with the dominant noise sources being collector current shot noise (since 0 collector current density determines fT) and the thermal noise generated by rbb . At a given frequency, 0 temperature and bias current, only rbb and fT in Equation (9.7.8) vary with emitter area. Thus, the device 0 , until the collector current shot noise causes an emitter area can be increased in order to reduce rbb unacceptable degradation of the noise figure because of a reduction in the transistor fT. Example plots of the minimum noise figure for three emitter areas are plotted as a function of base current density in Figure 9.7.16. The flat portion of the noise figure curve (i.e., below 0.3 mA/mm) corresponds to the region where the noise figure is dominated by the extrinsic base resistance of the transistor. As the emitter area of the BJT increases, the base resistance decreases, however, the collector current also increases for a given current density and so the minimum noise figure remains almost constant (as predicted by Equation (9.7.5) and Equation (9.7.6)). At large collector currents the fT of the transistor begins to decrease, causing a rise in the minimum noise figure. Note that the minimum noise figure is almost independent of the emitter area selected, and that there is a broad range of bias points over which the noise figure of a typical common emitter amplifier can be minimized. The noise figure is also frequency dependent. As the operating frequency begins to approach the device fT, the gain of the transistor begins to decrease and hence the collector current shot noise begins to dominate. For a constant collector current, the transistor transit frequency is lowest for larger area devices, and therefore the noise figure of a large area transistor will increase more rapidly with frequency than for smaller transistor designs. Since the relative contribution of the transistor noise sources to the overall signal-to-noise ratio depends upon the source impedance seen at the transistor input terminal, there is an optimum source impedance which results in the lowest noise figure. In general, this optimum noise match is not equal to the conjugate of the transistor input impedance required for maximum power transfer. An inductor placed in series with the emitter lead of the BJT modifies the optimum noise match, and under certain conditions the minimum noise figure and the maximum power transfer at the input can be achieved Emitter width = 0.2 µm

4 3.5

1⫻10 µm2

3

1⫻20 µm2

2.5 2 1.5

1⫻5 µm2

1 0.5 0

10−3

10−2

10−1

1

10

Collector current density, J C (mA / µm)

FIGURE 9.7.16

NFmin versus current density for various emitter lengths at VCE ¼ 1.5 V, f ¼ 5.5 GHz.

© 2006 by Taylor & Francis Group, LLC

9.7-1025

Wireless Building Blocks Using SiGe HBTs

simultaneously, making this approach very attractive [18]. However, the amount of feedback which can be applied to the preamplifier is limited by the constraints of gain and power consumption, and in most cases only a small amount of feedback can be applied [19]. Examples of impedance matching networks are shown in Figure 9.7.17. The input is matched by adding inductance in series with the transistor input. At the output, a tapped capacitor impedance transformer matches a low impedance (e.g., 50 V) load to the collector impedance. A possible physical layout for the tapped capacitor is also shown in Figure 9.7.17, where metal– insulator–metal capacitors are implemented using the multiple layers of metal in a VLSI technology. Note that the bottom plate of capacitor CB shields the tapped capacitor from the conductive substrate. Transformer Feedback Amplifiers As the supply voltage of digital circuitry shrinks with technology scaling, RF circuit topologies require sub-1 V operation. This is because integration of analog–RF and digital circuitry on the same die is desirable from both cost and packaging considerations. In addition, as operating frequencies increase, amplifier designers can no longer neglect the effects of the collector–base feedback capacitance Cbc, on performance. Feedback via Cbc is reduced using a cascode configuration, however, a two-transistor stack is not optimal for operation at the lowest possible supply voltage. The transformer feedback amplifier employs reactive negative feedback through an on-chip transformer to neutralize Cbc, while also allowing a collector bias voltage equal to the supply voltage (i.e., VCE ¼ VCC). As a result, gain and dynamic range are not compromised when only a single active device is used. Circuit techniques that mitigate the effect of Cbc are usually grouped into two categories: unilateralization and neutralization. Unilateralization decreases reverse signal flow and thus coupling between output and input ports of an amplifier. Neutralization cancels signal flow through Cbc by adding signal paths around the amplifier that cancel signal flow via Cbc. This technique increases the forward gain and reverse isolation for a given power consumption but does not necessarily reduce the effect of Cbc on the input capacitance. An alternative approach to neutralization uses a feedback transformer, which introduces magnetic coupling between collector and emitter inductors of a common-emitter transistor amplifier as shown in Figure 9.7.18 [20, 21]. Feeding back a portion of the output signal via the transformer can effectively cancel the feedback from output to input through the Miller capacitance (Cbc) and neutralize the amplifier. This increases the amplifier gain for a given bias current and improves the isolation between output and input. The circuit parameters that define this condition are n Cbe k Cbc

V IN

(9:7:9)

L bond+L pkg+L Match C M2

RIN

C M1

parallel equivalent input circuit of the LNA (valid only at a single frequency)

C IN

R IN = R G Input matching network

VC

VC CA LC

R OUT = r p

CB

CB CA

V OUT CB

RL

VCC Collector load

Tapped capacitor layout

FIGURE 9.7.17 LNA impedance matching (single-ended equivalent networks).

© 2006 by Taylor & Francis Group, LLC

IMD-4 IMD-3 IMD-2 IMD-1 FOX SILICON

V OUT

9.7-1026

The Silicon Heterostructure Handbook

Reverse signal flows cancel Cµ RG⬘

M np:ns

RL

CS

VCC

FIGURE 9.7.18

A transformer feedback amplifier.

using nonideal magnetic coupling in the transformer. Therefore, neutralization is achieved when the effective transformer turns ratio n/k is set equal to capacitance ratio Cbe/Cbc. Note that there is no frequency dependence in the neutralization condition, implying that transformer-feedback can be used as a wide-bandwidth neutralization technique restricted only by the bandwidth of the transformer. For a given LNA design, the transformer turns ratio (n) is often constrained by linearity, gain, and noise specifications. In these cases, the coupling coefficient (k) is the extra degree of freedom that can be adjusted to achieve amplifier neutralization. This can be accomplished by adjusting the spacing between the transformer primary and secondary windings. An example of a transformer feedback amplifier fabricated in a 0.5 mm SiGe bipolar technology is shown in Figure 9.7.19 [22]. The 2.4 GHz LNA draws 2.5 mA from a 0.9 V supply. The step-up ratio between primary and secondary of the transformer is realized by sectioning one winding (e.g., the primary) into a number of single turns rather than one continuous winding. These single-turn windings are then connected in parallel to form the step-up ratio between primary and secondary of the transformer. The 1:4 step-up design shown in Figure 9.7.19 consists of eight turns of 10-mm wide topmetal with a 3 mm conductor spacing, and measures 350 mm on each side. The step-up transformer is an almost ideal feedback element for an RF amplifier, and can be used as a narrowband alternative to a broadband, resistive network. The impedance match for the LNA input is off-chip so that either 50 V or minimum noise figure matching between the source and the amplifier input could be selected. When matched for optimal noise performance, the measured preamplifier noise figure is 0.95 dB at a gain of 10.5 dB (biased at 2.5 mA from 0.9 V). When a 50 V impedance match is used, the gain rises to 11 dB at a noise figure of 1.75 dB. At the same bias point, the third-order intercept point (IIP3) of the preamplifier is 4.5 dBm for both matching situations. This combined performance (i.e., noise figure, gain, power consumption, and IIP3) is excellent, regardless of the technology. LNA Comparison and Summary A performance summary of some recently reported LNAs fabricated in SiGe are compared to representative examples from other technologies in Table 9.7.2. The first entry in the table is an early example of a transformer-feedback amplifier as described in the previous section. This design is a demonstration of very low current consumption from a sub-1 V supply that can realize a noise figure of 0.95 dB. The gain is limited by the transformer step-up ratio and the circuit was not optimized for IM3 performance. The second entry demonstrates the benefits of eliminating low frequency at second-order harmonic feedback at the LNA input on the IP3 of an LNA [23]. The amplifier demonstrates an excellent third-order intercept point (IIP3) of þ8 dBm for PCS telephony using a single 0.5 mm SiGe BJT (i.e., no cascode). The low-frequency signal path at the RF input is via an external choke to an on-chip dc bias circuit. The third entry in Table 9.7.2 is a 0.25 mm SiGe bipolar LNA that consumes a comparable amount of DC power to the single-ended LNA from Ref. [23], but includes automatic gain control (AGC) in a fully differential circuit [24]. Two recently reported

© 2006 by Taylor & Francis Group, LLC

9.7-1027

Wireless Building Blocks Using SiGe HBTs

1:4 Step-Up Transformer

RFout

RFin

FIGURE 9.7.19 A 2.4 GHz transformer feedback amplifier in 0.5 mm SiGe bipolar technology. (After JR Long, M Copeland, S Kovacic, D Malhi, and D Harame. Proceedings of the International Solid-State Circuits Conference, 1996, pp. 82–83. With permission.) TABLE 9.7.2 Frequency in GHz

LNA Comparison Gain in dB

NF in dB

IIP3 in dBm

VCC in Volts

PD in mW

2.4 1.96

10.5 15.4

0.95 1.6

4 8.3

0.9 3

2.25 23

2 17.2 61.5 2.14 1.57

14.5 17.5 17 15 16.5

1.6 2.4 4.2 1 1.3

5 0.5 8.5 7.3 5

3 2.2 1.8 3 1.5

30 10.6 10.8 25.5 9

Notes

Technology

Transformer feedback c-e with harmonic termination Differential with AGC Differential cascode c-b/c-b cascode LNA þ bypass sw. CMOS cascode

0.5 mm SiGe bipolar [22] 0.5 mm SiGe-BiCMOS [23] 0.25 mm SiGe-BiCMOS [24] 0.18 mm SiGe-BiCMOS [25] 0.13 mm SiGe-BiCMOS [26] 0.5 mm PHEMT [27] 0.25 mm CMOS [28]

Source: From JR Long, M Copeland, S Kovacic, D Malhi, and D Harame. RF analog and digital circuits in SiGe technology. Proceedings of the International Solid-State Circuits Conference, 1996, pp. 82–83. V Aparin, P Gazzerro, J Shou, B Sun, S Szabo, E Zeisel, T Segoria, S Ciccarelli, C Persico, C Narathong, and R Sridhara. A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability. IEEE International Solid-State Circuits Conference, 2002, pp. 234–235. M Tanabe, T Fukuda, and K Nishii. Step gain amplifier with impedance unchanged in gain control. IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 209–212. SY Yue, D Ma, JR Long, and DL Harame. A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3 subharmonic injection locking. IEEE International Solid-State Circuits Conference, 2004, pp. 388–399. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz transceiver circuits in SiGe bipolar technololgy. IEEE International Solid-State Circuits Conference, 2004, pp. 442–443. S Kumar, M Vice, H Morkner, and W Lam. Enhancement mode GaAs PHEMT LNA with linearity control (IP3) and phased matched mitigated bypass switch and differential active mixer. Proceedings of the IEEE International Microwave Symposium, 2003, pp. 1577–1580. P Leroux, M Steyaert, V Vassilev, and H Maes. A 1.3 dB NF CMOS LNA for GPS and 3 kV HBM ESD-protection. Proceeding of ESSCIRC, 2002, pp. 335–338. With permission.

LNAs designed for millimeter-wave frequencies follow Refs. [25, 26], which demonstrate the high operating frequencies enabled by the latest deep submicron SiGe-BiCMOS technologies. The final two entries in the table list recently reported data for LNAs designed around a III–V PHEMT [27] and an n-type MOSFET from a 0.25 mm CMOS technology [28]. In comparison, the SiGe BJToffers comparable RF performance (i.e., noise figure and linearity) to the PHEMT LNA and it allows greater integration of RF

© 2006 by Taylor & Francis Group, LLC

9.7-1028

The Silicon Heterostructure Handbook

and baseband functions in a lower cost BiCMOS technology. Also, the SiGe LNAs enable operation at higher frequencies or with lower power consumption than state-of-the-art CMOS alternatives.

9.7.4 RF Mixers The RF mixer is one of the most important and, from a theoretical standpoint, poorly understood components in radio engineering. The nonlinear nature of the mixing process makes analysis of some important performance aspects of the mixer, such as the signal-to-noise ratio, a formidable task. Consequently, discrete mixer circuits have primarily evolved through experimental refinement, rather than a design evolution based upon a solid theoretical foundation and engineering principles. The factors that influence the noise figure of a single diode mixer, for example, have been known since the early days of radio. However, a consistent theoretical analysis of single-diode mixer noise was not published until 1978. The mixer in a radio receiver is an analog multiplier, which downconverts the received signal from the RF band to an IF, or directly to the baseband for demodulation and detection (the mixer in a transmitter up converts a signal from baseband or IF to RF). The effectiveness of the mixer as a frequency converter is measured by the degradation in signal-to-noise ratio and distortion of the input signal. The impedances at the mixer ports must be well defined and controlled, because in a typical radio implementation, the mixer interfaces with off-chip signals at all three I/O ports. Isolation of large signals (such as the LO) from the smaller signals at the other mixer ports, such as the (potentially) tiny received signal at the receive mixer RF input, must also be considered. This is particularly important in a direct conversion receiver design. The range of the input signal from the minimum detectable level to the overload point defines the dynamic range. These limitations define the performance capabilities of the receiver to a large extent, although noise introduced by the mixer in a receiver is normally suppressed by a low-noise preamplifier. Aside from these two main performance specifications, other important mixer characteristics are: the port-to-port signal isolation, the port impedances as a function of frequency, and the mixer conversion gain. An ideal downconverting mixer in a radio receiver produces an IF output signal only at the sum and difference frequencies between the RF and the LO input signals. However, in a practical circuit there are a number of spurious components that are generated by the mixing process, some of which may be suppressed through the use of balanced circuitry. Also, the circuit complexity and the minimum noise figure, which can be realized for a given topology, are related. An elaborate circuit topology that places more active and passive components and their associated noise sources in the RF signal path will usually have a higher noise figure. The most widely used mixer in silicon technology is Gilbert’s four-quadrant multiplier (shown in Figure 9.7.20). The RF input is converted to in-phase and anti-phase signal currents by the differential transistor pair, Q1 and Q2, and fed to the upper four transistors, Q3 to Q6 (often referred to as the switching quad), which are driven by the LO signal. Differential to single-ended conversion is normally required at the mixer output because most passive filters are single-ended, although balanced filters are available. The outputs of the mixer can be buffered to a low impedance load (e.g., 50 V) by a singleended output buffer circuit, or the differential signal can be combined by a passive power combining circuit to drive the following stages. The emitter degeneration resistor, Ree, improves the linear range of the differential input amplifier and it is connected so that no dc bias current flows through the resistor. This is done to ensure that the voltage drop across all components in the bias current path between the power supply and ground is as large as possible. Even so, the absolute minimum supply voltage (VCC) for this circuit is approximately 2.7 V. In order to minimize the noise contributed by the upper four transistors, the LO input is normally driven with a large amplitude signal. This minimizes the period of time when all four transistors in the quad are in the active region and contribute noise to the IF output. Ideally, the large LO drive signal (i.e., vLO > VT) switches the collector current in each transistor quickly between aIEE and zero. When

© 2006 by Taylor & Francis Group, LLC

9.7-1029

Wireless Building Blocks Using SiGe HBTs

V CC

RC

RC

v IF −

v LO

+

v IF + Q3 Q4

Q5 Q6

R LO

Q1

v RF

Q2 CD

R ee Q7

Q8

V cs R cs

R cs

FIGURE 9.7.20 An IC mixer based upon the Gilbert multiplier.

this assumption is made, the differential output current can be modeled as the input signal current at the collectors of Q1 and Q2 multiplied by a switching function which alternates between þaIEE and aIEE at the LO frequency (vLO). Many of the limitations of the Gilbert multiplier as an RF mixer arise from design constraints imposed by the input differential pair. The linear range of the mixer, for example, is determined by the linearity of the input pair. This is approximately equal to the input voltage required to force all the bias current through one of the two transistors, either Q1 or Q2. It can be shown that this voltage is in the order of the bias current–emitter degeneration resistance product, and hence the linear range of the mixer can be improved by increasing the degeneration at the emitter of the input pair. This could be accomplished by either increasing the total bias current from Q7 and Q8, or by increasing Ree. However, a large bias current increases both the power dissipation and the noise from transistor shot noise sources, and an increase in the emitter degeneration resistance also degrades the signal-to-noise ratio at the IF output. Thus, using emitter degeneration to reduce distortion will increase the noise figure of the Gilbert multiplier and as a result, realizing a dynamic range suitable for radio receiver applications has proven difficult using this circuit. The linearity of the input pair (which acts as a preamplifier for the mixing quad) can also be improved by removing the low frequency and second harmonic of the RF signal using passive circuits in a manner similar to the technique described in the ‘‘Low Noise Amplifier’’ section. Another disadvantage of the Gilbert multiplier as a high-frequency mixer is the relatively high input impedance of the differential input pair of transistors at RF. When the mixer RF input is driven from another circuit on the same chip, impedance matching is not an issue. When driven by an off-chip source, an impedance match is necessary at the mixer RF input, and off-chip components are required for the best performance (i.e., low dissipation and low tolerance). This increases the receiver parts count and makes an integrated solution less attractive in terms of cost and performance when compared to a discrete implementation, where components can be selected for optimum performance and lowest cost. A Class-AB input stage [29, 30] of Figure 9.7.21 has been developed to lower the distortion produced by an IC mixer for large-signal inputs, since it is the linearity of the mixer that normally defines the

© 2006 by Taylor & Francis Group, LLC

9.7-1030

The Silicon Heterostructure Handbook

RF +

Q1

To mixing quad

RF −

V BB

RF In CD Q2

FIGURE 9.7.21

Q3

Class-AB mixer input stage.

overall linearity in a properly designed RF receiver. This consists of a common-base amplifier Q1 and current mirror Q2/Q3. Small-signal RF input signals are buffered to one pair of mixing transistors in the Gilbert quad by the common-base stage, while the mirror inverts the input signal and couples it to the second pair of mixing devices in the quad. For large input signal amplitudes, the current mirror– common-base combination operates in Class B mode, where the signal current in the common-base or current mirror stages increases in response to negative and positive excursions of the input signal, respectively. Diode connected transistor Q2 is required to bias transistor Q3, but because it is in the RF signal path it degrades the signal-to-noise ratio and noise figure of the mixer.

Transformer Balun-Coupled Mixer The transformer-coupled mixer also offers an improvement in performance when compared to the Gilbert multiplier [20]. The input differential pair of the Gilbert multiplier acts like an ‘‘active’’ balun circuit, because it splits the RF input signal into two components, one in-phase and the other anti-phase to the RF input signal. An alternate method of deriving differential signal currents uses a monolithic transformer balun to split the RF input signal into differential components, which are then fed to the switching quad of transistors as shown in Figure 9.7.22. This circuit configuration retains many of the benefits of the Gilbert multiplier, such as the balanced topology and compatibility with silicon monolithic circuit technology, while allowing the designer the flexibility to design a mixer that has a wider dynamic range and operates with lower power consumption. A balanced circuit is required to obtain good port-to-port isolation and rejection of spurious signals. The switching quad from the Gilbert multiplier is well suited to monolithic integration. Transformer coupling of the RF input signal retains the advantages of a doubly balanced topology while improving upon the performance of the active circuit used to generate differential RF signal currents in Gilbert’s multiplier. The RF input signal to the mixer (refer to Figure 9.7.22) is split into in-phase and anti-phase components by balun T1. These signals are then fed to the cross-coupled switching quad of transistors, Q1 to Q4. Bias current is fed from current source Q5 to the switching quad through the center-tap in the balun secondary. The signal current is chopped by the transistor quad at the LO rate in order to downconvert the input signal from RF to the desired IF. Package and bondwire parasitics have a relatively small influence on the IF port matching and a good impedance match can be achieved through the proper selection of the collector load resistance, RC. Approximately, ideal transformer behavior can be assumed as the balun primary and secondary windings are resonant tuned. The LO inputs of the switching quad are driven with a large amplitude

© 2006 by Taylor & Francis Group, LLC

9.7-1031

Wireless Building Blocks Using SiGe HBTs

V CC RC

L1

RC

IF −

IF + Q1

LO +

L1

Q3 Q4

Q2

LO − CP T1

RFin CS

CS Q5

V cs

CD

R cs

FIGURE 9.7.22 Balun-coupled mixer.

signal, and therefore, two of the transistors in the quad are biased in the active region, and the other transistors in the quad are cutoff for a large portion of each cycle (e.g., when LOþ is much larger than LO, Q1 and Q4 are ‘‘on’’ and Q2 and Q3 are cutoff in Figure 9.7.22). The transistors biased in the active mode operate in the common-base configuration and amplify each phase of the received signal to the intermediate frequency output. The transformed source resistance (rSRC) degenerates the common-base amplifier and extends its linear range of operation. The transformer has been used advantageously here to match the source impedance to the mixer and improve the mixer linearity without causing a significant increase in the overall noise figure. This occurs because no additional dissipation has been added to the circuit other than the losses in the transformer windings, which are relatively small. Linearization of conventional IC mixers, such as the Gilbert-type balanced demodulator, will require the addition of degeneration resistance which causes a large degradation in the mixer noise figure when high linearity is desired. The noise introduced by the mixing process is difficult to determine analytically, but can be simulated. There is some degradation caused by the dominant transistor noise sources of the common-base amplifier, which are collector current shot noise and thermally generated noise from the extrinsic base resistance. Operating the mixer at a low bias current reduces the shot noise contributed by each active device. However, the switching speed of the transistors in the quad is also important when attempting to realize a lower noise figure. When the LO inputs are close to the same potential, very little of the signal at the mixer RF input appears at the IF output, because of the balanced circuit connection. All four transistors in the quad are forward biased in this condition and contribute noise to the IF output. Thus, the signal-to-noise ratio at the IF output is very low during the switching interval, and fast switching of the transistor quad is needed to reduce this portion of each LO cycle. Switching speed is not the only consideration because of the trade-off between emitter area and the extrinsic base resistance of the bipolar transistor. Careful selection of the emitter area for the transistors in the switching quad is therefore required in order to achieve a good mixer noise figure. A compromise is needed between a small transistor that can switch quickly between states and a larger transistor with less thermally 0 generated noise from the transistor extrinsic base resistance, rbb

© 2006 by Taylor & Francis Group, LLC

9.7-1032

The Silicon Heterostructure Handbook

TABLE 9.7.3 Mixer Comparison RF Input in GHz 2.4 1.96

Gain in dB

SSB NF in dB

8 13.4

9.5 7.1

IIP3 in dBm

VCC in Volts

PD in mW

4 4.7

1.2 3

6 63.3

0.9 17.1

2 6.0

12 18

9 3.6

3 2.2

12 19.4

62

9

13

—

2.7

19.2

12

7

0

3

24

3

3

39.3

2.14 1.9

6.5

8.5

Notes

Technology

Balun-coupled Single-balanced mixer with harmonic term, including LO buffer Class-AB input Double-balanced image-reject Single-balanced

0.5 mm SiGe bipolar [22] 0.5 mm SiGe-BiCMOS [23]

Gilbert mixer including LO buffer Gilbert mixer including LO buffer

0.4 mm Si-bipolar [31] 0.18 mm SiGe-BiCMOS [25] 0.13 mm SiGe-BiCMOS [26] 0.5 mm PHEMT [27] 0.8 mm CMOS [32]

Source: From JR Long, M Copeland, S Kovacic, D Malhi, and D Harame. RF analog and digital circuits in SiGe technology. Proceedings of the International Solid-State Circuits Conference, 1996, pp. 82–83. V Aparin, P Gazzerro, J Shou, B Sun, S Szabo, E Zeisel, T Segoria, S Ciccarelli, C Persico, C Narathong, and R Sridhara. A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability. IEEE International Solid-State Circuits Conference, 2002, pp. 234–235. SY Yue, D Ma, JR Long, and DL Harame. A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3 subharmonic injection locking. IEEE International Solid-State Circuits Conference, 2004, pp. 388–399. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz transceiver circuits in SiGe bipolar technololgy. IEEE International Solid-State Circuits Conference, 2004, pp. 442–443. S Kumar, M Vice, H Morkner, and W Lam. Enhancement mode GaAs PHEMT LNA with linearity control (IP3) and phased matched mitigated bypass switch and differential active mixer. Proceedings of the IEEE International Microwave Symposium, 2003, pp. 1577–1580. J Durec. An integrated silicon bipolar receiver subsystem for 900-MHz ISM band applications. IEEE Journal of Solid-State Circuits 33:1352–1372, 1998. PJ Sullivan, BA Xavier, and WH Ku. Low voltage performance of a microwave CMOS Gilbert cell mixer. IEEE Journal of Solid-State Circuits 32:1151–1155, 1997. With permission.

Mixer Comparison and Summary A summary of recently reported mixers fabricated in SiGe are compared to representative examples from other technologies in Table 9.7.3. The first entry in the table is a transformer balun-coupled doublebalanced mixer as described in the previous section. This design demonstrates low voltage operation and low current consumption (5 mA from a 1.2 V supply). The supply voltage could be pushed below 1 V if the bias current source (Q5 from Figure 9.7.22) were replaced by a current limiting resistor. The 4:5 balun step-up ratio allows a 50 V match to the RF input. The second entry in Table 9.7.3 demonstrates the improvement in IP3 that can be realized by eliminating low-frequency energy and second-order harmonic feedback at the input to a single-balanced multiplier [23]. The mixer demonstrates a high input third-order intercept point (IIP3) with both high conversion gain (13.4 dB) and low noise figure (50 V SSB NF of 7.1 dB) in a 0.5 mm SiGe-BiCMOS technology. The third entry in Table 9.7.3 is a 0.4 mm silicon bipolar mixer with a Class-AB input stage [31]. This circuit offers high linearity at low dc bias current (þ9 dBm IIP3 at 4 mA), but at the cost of noise figure. It is likely that a SiGe implementation would be capable of similar performance but with greater operating bandwidth. The fourth entry in the table is a full image-reject mixer (i.e., two double-balanced mixers driven by quadrature LOs) operating at 17.1 GHz. It demonstrates the high operating bandwidth offered by deep submicron SiGeBiCMOS processes and low power consumption. The following entry is also a millimeter-wave mixer, but operating in the 60 GHz band proposed for IEEE 802.16 wireless communication. This singlebalanced circuit was designed in a 0.13 mm BiCMOS technology. The final two entries in the table list data for mixers designed in a 0.5 mm GaAs PHEMT [27] and a 0.8 mm CMOS technologies [32]. SiGe BJT mixers offer comparable RF performance to their GaAs counterparts, but in a lower cost technology

© 2006 by Taylor & Francis Group, LLC

9.7-1033

Wireless Building Blocks Using SiGe HBTs

with large-scale integration possibilities. SiGe mixers are also competitive with CMOS designs, but offer lower current consumption or greater operating bandwidth at a given technology node.

9.7.5 Voltage-Controlled Oscillators Oscillators are indispensable to electronic systems. They provide carrier signals for modulation in analog communications, and in a digital system, bit streams must be sampled or synchronized with some reference timing that originates from a stable, locally generated source. Determination of the oscillation amplitude and frequency for weakly nonlinear oscillators has been considered by many researchers; van der Pol was probably the first to publish work in this area and many others have followed. The classical approaches to this problem start from a basic assumption about the nonlinear transfer characteristic within the active element and assume some filtering in the loop. The basic problem in oscillator design, however, is not the solution of the oscillation condition itself but characterization of the nonlinearities within the loop. Nonlinear CAD tools have been developed, which can predict the oscillation amplitude and the random fluctuations in the output phase (i.e., phase noise). This has given researchers the ability to identify the sources of phase noise degradation in the most popular circuit topologies and to develop modifications that improve performance. The RF power spectrum is a common method of characterizing oscillator performance in the frequency domain. A plot of rms power versus frequency, such as seen on a spectrum analyzer, is a measure of phase noise when the noise introduced by amplitude modulation of the signal measured is insignificant. The spectrum is symmetric about the carrier frequency. Examining one side of this spectrum, the ratio of the single-sideband (SSB) to the carrier power spectral density at a frequency offset of fd Hz away from the carrier, or L(fd), is used as a measure of the phase noise. The importance of the oscillator phase noise in a wireless transceiver application is illustrated in Figure 9.7.23. The received RF signal strength in the desired channel and the maximum signal strengths in the adjacent channels are shown in part (a) of the figure. The oscillator spectral characteristics are also shown, where the phase noise density of the oscillator must be well below the peak at a frequency offset equal to the channel spacing, fch. The down converted spectrum is illustrated as two parts in Figure 9.7.23(b). One component is the ‘‘desired’’ block of signals in the lower part of the diagram, which are down converted by an (idealized) sinusoidal component at the nominal LO frequency, fLO. The second or ‘‘interfering’’ block of signals arise from the down conversion of the RF signal spectrum by a sinusoidal component of the oscillator spectrum that is offset from the main carrier lobe by the channel spacing. The amplitude of the interference at the IF is directly proportional to the phase noise of the LO, and as a consequence, the level of adjacent channel interference increases as the phase noise of the LO increases. On the transmit side, the phase noise introduced by the LO used to up-convert a signal for transmission is a potential source of interference in the system. The channel spacing in many cellular telephone systems is on the order of kHz, and consequently the demands on the spectral purity of the oscillator are much greater than in system such as cordless telephones where the channel spacing is on the order of 1 MHz. For example, in the American IS-54 system, the oscillator phase noise spectral density requirement is approximately 115 dBc/Hz at a 60 kHz offset from the carrier (the channel bandwidth in IS-54 is 30 kHz). In an oscillator, the phase noise produced by the gain element (i.e., an amplifier) is passed through a frequency selective circuit or resonator (with quality factor Q), that acts as a bandpass filter to reject undesired noise components and feeds the desired frequency component from the amplifier output back to the input. For fluctuations in the output frequency measured with respect to the carrier frequency, the transfer function of the tuned circuit can be described by a lowpass filter response, H(fd), where H(fd ) ¼

© 2006 by Taylor & Francis Group, LLC

1 j2Qfd 1þ f0

(9:7:10)

9.7-1034

The Silicon Heterostructure Handbook

Adjacent channels

RF signal strength

Desired channel

Frequency

LO output

S(f) Phase noise in dBc at f ch Spurious tone fL0 fch

Frequency

(a) RF and LO signals

IF output

Interfering signal due to phase noise at f ch

Desired channel

Frequency

(b) Resulting baseband output

FIGURE 9.7.23

Effect of oscillator phase noise on down converted signal in a receiver.

f0/2Q is the half-bandwidth of the bandpass filter with quality factor Q, and fd ¼ f f0, which is the frequency deviation with respect to the carrier at f0 Equation (9.7.10) describes the transfer function of the feedback network. The amplitude of the spectral components in the amplifier output that are produced by phase fluctuations at the input (i.e., the phase modulated sidebands) will pass unattenuated up to the half-bandwidth of the tuned circuit. The phase response of the resonator is given by 2Qfd 2Qfd ¼ u(fd ) ¼ a tan f0 f0

for small fd

(9:7:11)

Equation (9.7.11) shows that if the frequency deviation is small, the phase of the resonator output is linearly related to the frequency deviation, fd. If the deviation is large, then the output phase approaches a constant value, which is independent of the frequency deviation. The open-loop phase noise spectrum, Dfin(fd), is produced by the effect of circuit noise sources on the amplifier input signal. The equivalent low-pass transfer function for the resonator (H(fd) from

© 2006 by Taylor & Francis Group, LLC

Wireless Building Blocks Using SiGe HBTs

9.7-1035

Equation (9.7.10)) is used to model the feedback network effects on the oscillator phase noise. Most of the oscillator noise close to the carrier in a high-quality oscillator is phase or FM noise, because the limiting mechanisms (e.g., an AGC circuit to control the amplifier gain) tend to eliminate AM noise. The closed-loop response of the phase feedback loop is given by jf0 (Dfin (fd ) ) Dfout (fd ) ¼ 1 þ 2Qfd

(9:7:12)

Equation (9.7.12) describes the phase modulation due to noise (or phase noise) at the amplifier output (output frequency fo). The phase noise at the input to the amplifier (Dfin) is enhanced by positive feedback because for small frequency deviations (i.e., small fd) the output phase noise will be greater than the input phase noise. Or, as described by Equation (9.7.11), feedback through the resonator forces a phase change at the amplifier input (or resonator output) to be linearly related within the resonator bandwidth. Outside of this bandwidth, the feedback through the resonator approaches zero as fd increases, and the output phase noise (Dfout) is the same as the input phase noise (Dfin) because the amplifier gain is unity. A simplified model of oscillator phase noise called Leeson’s model [33] predicts the spectral characteristics of a feedback oscillator in terms of known circuit parameters (the equivalent input noise of the simplify, the tuned circuit Q-factor, etc.) when a high Q tank is used. Leeson’s model predicts that the single-sideband phase noise spectral density at frequency offset fd (L(fd)) is given by the following equation: " 2 2 # 1 fo 1 fc FkTB 1þ 1þ L(fD ) ¼ 2fD fD Psig 2 Qloaded

(9:7:13)

where Qloaded is the loaded Q-factor of the resonator. The first term (in square brackets) shows the strong effect of resonator Q-factor and the offset from the carrier frequency on the phase noise spectrum, the second term is due to the flicker noise sources in active devices (given by flicker corner frequency, fc) and the last term is the ratio of thermal noise (gain block noise factor F, Boltzmann’s constant k, noise bandwidth B, and temperature T) to output signal power (rms power Psig). This equation predicts the four major causes of oscillator noise: upconverted 1/f noise or flicker FM noise, the thermal FM noise, the flicker phase noise, and the thermal noise floor. Equation (9.7.13) has been confirmed by experimental measurements on high-quality microwave signal sources. Leeson’s model predicts that oscillator phase noise is minimized by: 1. Minimizing the bandwidth of the feedback network (i.e., maximize loaded resonator Q) 2. Avoiding hard nonlinearity and saturation of the BJT. Nonlinearity in the oscillator increases the amplitude of noise components at frequencies close to the carrier, thereby increasing the phase modulation of the input signal (Dfin) 3. The signal voltage relative to the equivalent noise voltage should be made as high as possible to reduce the phase modulation caused by additive noise sources 4. Choose active devices that have low flicker (1/f) noise Highly integrated oscillators suffer from low-quality passive components compared to passive (off-chip) filtering technologies such as surface and bulk acoustic wave resonators. However, methods of predicting IC oscillator phase noise both quantitatively and qualitatively have been developed [34–38], and the important parameters that influence phase noise in the oscillator’s output identified. These results confirm the guidelines 1 to 3 listed in the preceding paragraph derived heuristically by Leeson. However, it has also been shown that the effect of low-frequency noise sources such as flicker noise can be reduced substantially through the use of a fully symmetric circuit topology, such as the differential Colpitt’s oscillator [39].

© 2006 by Taylor & Francis Group, LLC

9.7-1036

The Silicon Heterostructure Handbook

Resonant Tanks Much of the work on oscillator development in monolithic circuit technologies has centered around the development of high-quality resonant tanks. This is understandable given the importance of the resonator Q on oscillator performance as indicated by Equation (9.7.13). The resonant tank in a VCO consists of a monolithic inductor in parallel with a capacitor that is electronically tunable (a varactor). The design and performance of these two components are outlined in the following sections. Inductors The peak Q-factor of an inductor fabricated on silicon has improved from approximately 5 in the early 1990s to 15 to 20 for an inductor in the 5 to 10 nH range. This progress is due to thicker metal films (e.g., 2 to 3 mm thick top metal) [40], differential drive [41], and substrate shielding [42]. Smaller inductance values (e.g., 1 to 3 nH) show inherently higher peak-Q, but realize their best performance above the frequency where Q peaks for a larger inductance. This implies a compromise between the operating frequency and performance factors related to tank Q, such as phase noise suppression in a VCO. Since the parallel equivalent impedance of a tank circuit at resonance is proportional to its inductance, multi-kV tank impedances are possible as the inductance Lp increases. Specifications like gain and power consumption are proportional to the tank impedance, so a large inductance is preferred from a lowpower RF design perspective (other parameters being equal). In a differential circuit implementation such as a typical monolithic VCO, a pair of spiral inductors are used in the physical layout (as shown in Figure 9.7.24(a)). Although the overall circuit may be differential, the excitation of each inductor is ‘‘single-ended.’’ That is, one terminal of the spiral is excited Common node (Port 3)

Underpass

i1 i2

i1

i2 Port 1

Inductor 1

s1−2

Inductor 2

Port 2

(a) two asymmetric spiral inductors Underpass Axis of symmetry

Common node (Port 3)

i1

Inductor 1

i2

Port 1 Port 2

Inductor 2

(b) symmetric microstrip inductor

FIGURE 9.7.24 Microstrip inductor physical layouts for differential drive. (After M Danesh and JR Long. IEEE Transactions on Microwave Theory and Techniques 50:332–341, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

Wireless Building Blocks Using SiGe HBTs

9.7-1037

by an ac source while the other is connected to a common reference point (e.g., the supply voltage or ground). Note that signal currents associated with ports 1 and 2 (i.e., i1 and i2) flow in opposite directions, and hence some physical separation (s1–2) is required to limit the negative mutual magnetic coupling between the two inductors. The fully symmetric spiral inductor of Figure 9.7.24(b) is designed for differential excitation (i.e., voltages and currents at the terminals are 1808 out of phase). When driven differentially, the voltages on adjacent conducting strips are anti-phase, however, current flows in the same direction along each adjacent conductor shown in Figure 9.7.24(b) (i.e., signal currents i1 and i2 flow in the same direction on any side). This reinforces the magnetic field produced by the parallel groups of conductors and increases the overall inductance per unit area. The symmetric microstrip inductor is realized by joining groups of coupled microstrips from one side of an axis of symmetry to the other using a number of cross-over and cross-under connections. This style of winding was first applied to monolithic transformers for coupling both primary and secondary coils by Rabjohn [7]. One advantage of a fully symmetric layout is that the two separate spirals are replaced by a single coil, which has both electrical and geometric symmetry. This symmetry is important when locating the common node (a convenient bias point for active circuits), which separates the spiral into two inductances that have identical substrate parasitics at ports 1 and 2. As stated previously, a pair of asymmetric inductors must be spaced far enough apart to limit unwanted coupling (both magnetic and electric) between the inductor pair, which is not an issue for symmetric inductors. This is one of the reasons why a reduction in chip area results for the symmetric inductor. Also, the symmetric inductor is well suited for connection to active devices as the input terminals are on the same side of the structure. Q-factor improvement resulting from differential drive can be estimated from the lumped-element equivalent circuit shown in Figure 9.7.25(a). This equivalent circuit accurately models the electrical behavior of the inductor up to the first resonance frequency. For differential excitation, the signal is applied between the terminals and the differential input impedance Zd is the parallel combination of 2ZP and ZL. The substrate parasitics present higher equivalent shunt impedance in the differential case, and therefore Zd approaches the value of ZL over a wider range of frequencies than Zse. At lower frequencies the input impedance in either the shunt or the differential connections is approximately the same, but as the frequency increases, substrate parasitics CP and RP come into play. For differential excitation, these parasitics have higher impedance at a given frequency than in the single-ended connection. This reduces the real part and increases the reactive component of the input impedance. Therefore, the inductor Q is improved when driven differentially, and the self-resonant frequency (or usable bandwidth of the inductor) increases due to the reduction in the effective parasitic capacitance from CP þ CO to CP/2 þ CO. From these simplified models, the ratio of differential to single-ended Q-factors is Qd 2RP k RL ¼ Qse RP k RL

(9:7:14)

where and RL ¼ r(1 þ QL2) for QL ¼ vL/r. At low frequencies, RP RL and the two Q-factors are approximately the same. At lower frequencies, QL dominates in both cases and the Q-factor increases for increasing frequency. At higher frequencies, RL is increasing (as QL / f) and RP decreasing, so the differential Q-factor becomes larger than the single-ended Q. Eventually, RP dominates the inductor dissipation and the Q-factor decreases with increasing frequency. The peak-Q occurs at a higher frequency when driven differentially due to the reduced effect of substrate parasitics in the differential case. This analysis predicts Q improvement from differential excitation and that (ideally) the Q-factor can be doubled in the differential connection (i.e., when RP ¼ RL in Equation (9.7.14)) with no modifications in IC technology or processing. The symmetric layout is also useful to preserve the balance desired in the differential implementations most often used on RF ICs. A comparison between Q-factors from experimental measurements, three-dimensional electromagnetic simulation, and a lumped-element (SPICE) inductor model are shown in Figure 9.7.26. Good

© 2006 by Taylor & Francis Group, LLC

9.7-1038

The Silicon Heterostructure Handbook

Co Port 1

Port 2

rs(f )

Ls

Cox1

Cox2 RSi1 CSi2

CSi1

RSi2

(a) Lumped-element equivalent circuit model Port 1 Z se =

ZP × ZL ZP + ZL

L

+ V se

C P+C o

_

RP

r ZL

ZP

(b) Single-ended excitation equivalent circuit (Port 2 g rounded) Port 1 Zd =

2Z P × Z L 2Z P + Z L

r +

2RP

V diff

Co+C P/2

L

_

ZL

2Z P

Port 2 (c) Differential excitation equivalent circuit

FIGURE 9.7.25 Lumped equivalent circuit model of a microstrip inductor, and circuit equivalents for single-ended and differential excitations. (After M Danesh and JR Long. IEEE Transactions on Microwave Theory and Techniques 50:332–341, 2002. With permission.)

agreement is seen between measurement and simulation. At lower frequencies, the difference in Q between the differential and single-ended excitations is not significant (<1%) because the shunt capacitive parasitic components do not affect the low-frequency input impedance. Hence, the two cases can be represented by a series L–r model. However, as the frequency increases, the difference between the input impedances becomes substantial and the difference between Q-factors in the differential and singleended cases illustrates this point. The peak in the Q-factor is a result of the shunt parasitics as previously described. Lower parasitics for differential excitation result in a higher peak Q-factor and broadening of the Q peak compared with the single-ended (conventional) connection. The Q of inductors in production VLSI technologies is primarily limited by the silicon substrate, which has a typical resistivity of 10 to 15 V-cm for mixed-signal and RF IC work. Substrate dissipation decreases when a high-resistivity substrate is used, or when a patterned shield connected to the on-chip ground is placed between the inductor and the substrate. A simplified illustration of this is shown in Figure 9.7.27(a). The shield is designed to block current flow by magnetic induction but allows capacitive current to flow. The shield fingers also block the electric field from entering the underlying

© 2006 by Taylor & Francis Group, LLC

9.7-1039

Wireless Building Blocks Using SiGe HBTs 12 Measurement Simulation SPICE Model

10.3 10 9.3 8.7

Quality factor, Q

8 Differential 6.6 6

4

Single-ended

2

0

0

1

1.6

2

2.5

3

4

5

6

Frequency (GHz) FIGURE 9.7.26 Q-factors for single-ended and differential excitations. (After M Danesh and JR Long. IEEE Transactions on Microwave Theory and Techniques 50:332–341, 2002. With permission.)

substrate. However, they add capacitance that reduces the inductor’s self-resonant frequency. Gaps between the fingers block currents induced in the shield (limiting them to small eddy currents in each finger) but not in the ground line, which must be carefully designed. Any induced current decreases the total magnetic field, the inductance, and the Q. Differential shielding does not require an explicit ground connection, leading to a simpler implementation. Figure 9.7.27(b) shows the differential shield implementation. A balanced transmission line is capacitively coupled to orthogonal metal strips placed beneath it. Due to the balanced excitation, a virtual ground on the strips shields the entire transmission line.

Ground line I signal

Iinduced

Signal line

E

Shield fingers (a) Grounded shield Isignal +

Signal line

E

Virtual Ground Isignal “Floating” Shield Fingers (b) Differential shield

FIGURE 9.7.27 Conductor shielding. (After D Cheung and JR Long. IEEE Custom Integrated Circuits Conference, 2003, pp. 95–98. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.7-1040

The Silicon Heterostructure Handbook

1µm wide

1µm spacing

3rd metal layer 4th metal layer

FIGURE 9.7.28 Differentially shielded symmetric inductor. (After D Cheung and JR Long. IEEE Custom Integrated Circuits Conference, 2003, pp. 95–98. With permission.)

An example of a shielding pattern for the inductors is illustrated in Figure 9.7.28 [42]. This mesh pattern is comprised of horizontal and vertical strips that span the length and width of the inductor. A voltage induced on a strip along one side of the coil is compensated for by an equal but opposite voltage induced at the other end of the strip, when the inductor is driven differentially. The net electric potential induced on the strips is zero. Induced current is inhibited by placing the strips orthogonal to the inductor winding. The Q-factor for differential shielding is compared to an unshielded design in Figure 9.7.29. The measured low-frequency inductance is about 7.4 nH for both inductors. The parasitics of a differential shield lower the self-resonant frequency of the inductor by less than 3%. There is less than 2% difference in the inductance between shielded and unshielded inductors, which indicates that current induced in the shielding strips from the coil’s magnetic field is very small. In other words, the addition of a differential shield does not diminish the useful frequency range or the inductance value. Figure 9.7.29 shows that differential shielding improves the Q-factor by 35%. Varactors The varactor is a voltage-variable capacitor (controlled by the dc bias voltage) that is used to vary the resonant frequency of an LC tank and the operating frequency of the VCO. It is a passive device which can be modeled using a series R–C equivalent circuit (e.g., lumped capacitor Cs, in series with resistor rs) at a given frequency, resulting in a figure-of-merit Q-factor, Qv ¼ 1/vCsrs. Ideally rs is zero, but losses of the ac current path through the varactor result in a finite Q. Unlike the inductor, the varactor Q is largest 35 mesh

Quality factor

30 25 20

unshielded

15 10 5

0

1

2

3

4 5 6 7 Frequency (GHz)

8

9

10

FIGURE 9.7.29 Measured inductor Q-factor on a 10 V-cm substrate. (After D Cheung and JR Long. IEEE Custom Integrated Circuits Conference, 2003, pp. 95–98. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.7-1041

Wireless Building Blocks Using SiGe HBTs

at low frequencies and decreases with increasing frequency. Typically, Qs on the order of 50 to 100 can be realized on-chip for a varactor capacitance of 1 pF at 1 GHz. The bias voltage across the varactor changes the capacitance (CV) seen across the tank according to CV ¼ Cj0 =(1 VD =Vj )mj

(9:7:15)

where Cj0 is the zero-bias capacitance and VD is the applied voltage. A simple bias-dependent capacitor can be implemented using the depletion capacitance of a reverse biased p–n junction. The depletion region width of a reverse-biased diode varies inversely proportional to the reverse bias. If one side of the junction is lightly doped and the other highly doped, the depletion region is confined to the lightly doped layer, which can improve the linearity of the capacitance–voltage characteristic. Back-to-back diodes (see Figure 9.7.30(a)) are required to ensure that one diode is always reverse biased during the complete cycle of the oscillation across the tank in a differential circuit. Diode varactors can be implemented using the source–drain diffusions and well implant for an MOS device (either pþ/n or nþ/p junctions) of the collector–base junction of a bipolar transistor (nþp junction) in a BiCMOS technology. The Q of these varactors is limited by ohmic losses in the semiconductor (i.e., depletion region and the bulk). Decreases in capacitance from zero to full reverse bias of about 1.5:1 for a 2 to 3 V change in bias voltage are typical for diodes fabricated in modern VLSI silicon technologies (see Figure 9.7.31 for an example). This can be improved to 3:1 if the p–n junction doping profile can be made hyper-abrupt using a dedicated implant step to form the varactor junction, although this adds an additional mask step in fabrication. In addition to a larger capacitance change with voltage, hyper-abrupt p–n junction varactors also can have higher Q-factors when properly designed. MOS capacitors (i.e., gate-to-channel capacitance in the transition from depletion to accumulation, or between depletion and strong inversion modes) are also used to implement varactors on-chip. The capacitance–voltage (C–V) characteristics of the accumulation (A-MOS, Figure 9.7.30(c)) and inversion (I-MOS, Figure 9.7.30(b)) mode varactors are shown in Figure 9.7.31. When the channel underlying the gate oxide in an MOS transistor is in inversion (or accumulation) mode, the capacitance from gatesource–drain is maximum. As the carrier density decreases due to a change in bias voltage, the capacitance decreases, although the transition is much more abrupt than for a typical p–n junction varactor. The shape of the C–V curve is important as the nonlinearity of the capacitance with applied

Vctrl RF+

RF− (a) p+/n-junction Vctrl

RF+

RF−

VSS (b) Inversion-mode MOS Vctrl RF+

RF−

(c) Accumulation-mode MOS

FIGURE 9.7.30 Varactor diodes for use in differential VCOs.

© 2006 by Taylor & Francis Group, LLC

9.7-1042

Normalized Capacitance

The Silicon Heterostructure Handbook 1.0 ++ + + + + + + + + + + +

++

P-N

1.5 A-MOS

3.0 0.0

++

0.5

+ + + + +

I-MOS

++

1.0 1.5 2.0 Control Voltage, in Volts

+++

++

2.5

FIGURE 9.7.31 Normalized capacitance versus bias voltage for MOS and p–n junction varactors. (After P Andreani and S Mattisson. IEEE Journal of Solid-State Circuits 35:905–910, 2000. With permission.)

voltage does affect the phase noise of a VCO [44]. Q-factors for the MOS varactors are typically a factor of 2 higher than for a p–n junction varactor, and the capacitance variation between bias extremes is about 3:1. Technology scaling will improve this capacitance ratio as gate oxide thicknesses continue to decrease with newer generations. One advantage of most SiGe-BiCMOS technologies for RF design is the wealth of device options available. For varactors, there are usually three types of devices (one or more p–n junction, and also MOS varactors) available. Differential VCO tuning is desirable for a VCO in order to reject common-mode noise generated by other wireless blocks at the tuning control input. This can improve phase noise and make the design more robust. By matching the C–V characteristics of inversion-mode PMOS and NMOS devices, a varactor which (to the first-order) responds to a differential tuning voltage can be implemented [45].

Integrated Circuit Oscillators The full integration of a VCO with spectral purity sufficient to meet cellular telephony specification such as IS-95 has proven elusive. The greatest technical challenge preventing full integration is the quality of the resonator that can be implemented on-chip, due to the limited Q-factor of monolithic inductors and varactor diodes. However, there are a number of other constraints, which make integration a challenge. The recent trend to low supply voltages limits the available dynamic range and lowers the maximum signal-to-noise that is possible on-chip. Also, in any manufacturable design, the tuning range of the VCO must be sufficient to accommodate the entire range of component tolerances caused by process and temperature variations. However, as the tuning range is broadened, noise on the frequency control line of the VCO begins to cause a significant modulation of the oscillation frequency, resulting in higher phase noise from the VCO. There are numerous circuit topologies for oscillators, such as the Colpitts, Clapp, Hartley, Pierce, and push–pull. The most widely used design for silicon RFICs is the differential Colpitts oscillator, consisting of a cross-coupled differential amplifier (a negative-R cell) and resonant load as shown in Figure 9.7.32. The differential topology offers rejection of common-mode noise, which improves the immunity of the circuit to potential interference generated by other circuit blocks on the same chip. Bipolar transistors have low 1/f noise and higher transconductance (gm) for a given bias current compared to MOS devices, which can result in lower phase noise and lower current consumption for the VCO. The higher gain available in a single stage is also useful when designing power-efficient oscillator buffers to drive a mixer stage or buffer signals off-chip (Q3 and Q4 in Figure 9.7.32). The resonant tank formed by the inductor shunted by opposing varactor tuning diodes and capacitors is shown in Figure 9.7.32 (left). When the jRj of the negative-R cell is less than the total shunt dissipation of the resonator, the circuit will oscillate. The negative resistance seen at the tank must be sufficient to overcome losses in the tank and other parts of the circuit. A simple low-frequency analysis of the negative resistance cell formed by the positive feedback around transistors Q1 and Q2 gives the following equation for resistance seen between the collectors of the differential pair:

© 2006 by Taylor & Francis Group, LLC

9.7-1043

Wireless Building Blocks Using SiGe HBTs

V CC L1 C C D1

D1

RT

RT

L1 CC

V CC Output

Vtune C F1

C F1 Q1 C F2

R E3

Q2 R E2

R E1 RB

Q4

C F2 RB

V BB

Q5 R E4 V CS

Q6 R CS2

Q3

V CS L CS R CS1

FIGURE 9.7.32 Negative R cell-based VCO and output buffer.

rdiff ¼

2(1 þ gm RE(1,2) ) gm

(9:7:16)

where gm is the transconductance of each transistor in the differential pair and RE is the emitter degeneration resistance (i.e., RE ¼ RE1 ¼ RE2). The transconductance depends upon the selection of bias current. Capacitive feedback using capacitors CF (similar to the capacitive impedance transformer in a singleended Colpitt’s oscillator) closes the positive feedback loop. This improves the range of possible bias points for the R cell (using bias voltage VBB via large-valued isolation resistors RB) while eliminating the power consumed by emitter followers in a positive feedback network. It also ensures a large swing across the tank without driving transistors Q1 and Q2 into heavy saturation. Degeneration of current source Q3 using a low-Q inductor (Q < 3) reduces phase noise caused by upconversion of noise from the bias circuitry. The back-to-back tuning diodes (D1) are referenced to ground and capacitively coupled (via CC) to symmetric inductor L2. This reduces frequency modulation of the VCO caused by changes in the supply voltage (i.e., supply pulling). Tuning voltage Vtune is isolated from the RF path by large resistors (RT) as the bias current required by the tuning diodes is small. The processing tolerances inherent in varactors and on-chip inductors cause a shift in the resonant frequency away from the design value in manufacture. The tuning range of the resonant tank must be wide enough to accommodate this variation, which can be as high as 20%. Additional capacitors (switch selectable using digitally control switches) are typically used to adjust the oscillation frequency of a VCO in a power-up calibration sequence.

VCO Comparison and Summary Numerous VCO designs have been described in conference and journal publications. A brief summary comparing silicon (Si) and SiGe bipolar with Si-CMOS VCOs is given in Table 9.7.4. The phase noise

© 2006 by Taylor & Francis Group, LLC

9.7-1044

TABLE 9.7.4 VCO Comparison Maximum Oscillator Frequency in GHz

Phase Noise, in dBc/Hz (at fD)

3.4 1.2 1.56 11 47 2 1.8

Adjusted Phase Noise (dBc)

Tuning Range (%)

RF Pout in dBm

PD in mW (at VCC)

129 at 1 MHz 106 at 100 kHz 126 at 1 MHz 87 at 100 kHz 108.5 at 1 MHz 134 at 3 MHz

199.6 188 190 188 201.9 191

25 — 10 5 8 20

— 28 10 11.8 5.6 —

22.5 (2.5 V) 5.0 (2.7 V) 29.7 (2.7 V) 24.0 (3.0 V) 280 (5.5 V) 2.0 (2.0 V)

142 at 3 MHz

198

27.5

—

32.4 (1.8 V)

Notes

Technology

Differential Colpitts Differential Colpitts with AGC Differential Hartley Single-ended Clapp Common-collector diff. Colpitts Differential Colpitts, bondwire inductor Differential Colpitts

0.5 mm SiGe-bipolar [46] 25GHz Si-bipolar [47] 25GHz Si-bipolar [48] 0.5 mm SiGe bipolar [49] 70 GHz fT SiGe-bipolar [50] 0.5 mm CMOS [51] 0.25 mm CMOS [52]

© 2006 by Taylor & Francis Group, LLC

The Silicon Heterostructure Handbook

Source: From J-M Mourant, J Imbornone, and T Tewksbury. A low phase noise monolithic VCO in SiGe BiCMOS. IEEE Radio Frequency Integrated Circuits Symposium, 2000, pp. 65–68. MA Margarit, JL Tham, RG Meyer, and MJ Deen. A low-noise, low-power VCO with automatic amplitude control for wireless applications. IEEE Journal of Solid-State Circuits 34:761–771, 1999. M Zannoth, J Fenk, A Springer, and R Weigel. A single-chip Si-bipolar 1.6 GHz VCO with integrated bias network. IEEE Radio Frequency Integrated Circuits Symposium, 1999, pp. 117–120. M Soyuer, JN Burghartz, HA Ainspan, KA Jenkins, P Xiao, AR Shahani, MS Dolan, and DL Harame. An 11-GHz 3-V SiGe voltage controlled oscillator with integrated resonator. IEEE Journal of Solid-State Circuits 32:1451–1454, 1997. H Li, H-M Rein, R Kreienkamp, and W Klein. 47 GHz VCO with low phase noise fabricated in a SiGe bipolar production technology. IEEE Microwave and Wireless Components Letters 12:79–81, 2002. F Svelto, S Deantoni, and R Castello. A 1 mA, 120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO. IEEE Custom Integrated Circuits Conference, 2000, pp. 577–580. B DeMuer, N Itoh, M Borremans, and M Steyaert. A 1.8 GHz highly-tunable low-phase-noise CMOS VCO. IEEE 2000 Custom Integrated Circuits Conference, 25-5, 2000, pp. 585–588. With permission.

Wireless Building Blocks Using SiGe HBTs

9.7-1045

reported by the authors for each oscillator from the literature has been adjusted to account for different center and offset frequencies using the following equation Adjusted phase noise ¼ 10 log [(fo )2 =(fD )2 ] L(fD )in dBc=Hz

(9:7:17)

which gives a positive number (in units of dBc/Hz). Many figures-of-merit (FOMs) for ranking oscillator performance have been proposed in the literature to account for power consumption, oscillator tuning sensitivity, and other factors in addition to phase noise. Rather than weighting the phase noise with one of more of these other factors, data for center frequency, tuning range, and power consumption are listed separately in Table 9.7.4. The first three entries are differential Colpitts VCOs fabricated in SiGe [46] (entry 1) and silicon bipolar (entries 2 and 3) technologies [47, 48]. The first entry illustrates the advantages of SiGe-BiCMOS technology: a wide tuning range, higher operating frequency, and lower phase noise than its silicon counterparts. The manufacturability of the SiGe VCO is extended by using MOS capacitors and MOSFET switches to either add or remove capacitance in parallel with the tank in order to trim the operating frequency. The second entry in Table 9.7.4 is remarkable because it uses an AGC loop to regulate the amplitude of the oscillator’s output rather than rely on limiting of the signal amplitude due to the finite supply voltage. In theory, this will result in lower phase noise from the oscillator. However, this is not apparent from comparison of the AGC oscillator with the 3.4 GHz SiGe design in Table 9.7.4. One reason is the tank Q-factor, which has a strong influence on the phase noise. Q-factor is inversely proportional to top metal thickness, which is 4 mm in the SiGe technology compared to 1 to 2 mm for the 25 GHz bipolar technology used to fabricate the oscillator with AGC. The third design uses coupled coils in a Hartley configuration to feedback the signal from the tank to the input of the differential pair, thereby replacing feedback capacitors CF in Figure 9.7.32. This does not appear to offer any performance advantage or disadvantage from the reported results. The following two entries in Table 9.7.4 (4 and 5) illustrate the higher frequency capabilities of SiGe technologies [49, 50]. The 11 GHz VCO trades off reduced phase-noise performance for similar power consumption to the 3.4 GHz design, while the 47 GHz VCO attains similar phase noise performance at the expense of greater power consumption. The last two entries in the table are results from two recently reported CMOS differential Colpitts designs. The 2 GHz VCO [51] uses a bondwire inductor, which gives a much greater Q-factor than can be achieved with an on-chip inductor and allows the designer the freedom to lower power consumption while preserving phase-noise performance. The 1.8 GHz CMOS design [52] demonstrates low phase noise for a fully monolithic oscillator, but requires a comparatively larger bias current. Both CMOS designs require a buffer in order to minimize loading of the oscillator by the load (such as a mixer) in an RF transceiver application.

Acknowledgments The author would like to thank David Harame of IBM Microelectronics and Robert Hadaway of Northern Telecom Electronics for fabrication access.

References 1. J Sevenhans, F Op’t Eynde, and P Reusens. The silicon radio decade. IEEE Transactions on Microwave Theory and Techniques 50:235–244, 2002. 2. AA Abidi, PR Gray, and RG Meyer. Integrated Circuits for Wireless Communications. Piscataway, NJ: IEEE Press, 1999. 3. AA Abidi. Low-power radio-frequency ICs for portable communications. Proceedings of the IEEE 83:544–569, 1995.

© 2006 by Taylor & Francis Group, LLC

9.7-1046

The Silicon Heterostructure Handbook

4. JP Maligeorgos and JR Long. A 5.1–5.8 GHz image-reject receiver with wide dynamic range. IEEE Journal of Solid-State Circuits 35:1917–1926, 2000. 5. H Hasegawa, M Furukawa, and H Yanai. Properties of microstriplines on Si–SiO2 system. IEEE Transactions on Microwave Theory and Techniques 19:869–881, 1971. 6. JR Long. Passive components for silicon RF and MMIC design. IEICE Transactions on Electronics of Solid-State Circuits E86-C-6:1022–1031, 2003. 7. GG Rabjohn. Monolithic microwave transformers. M.Eng. thesis, Carleton University, 1991. 8. J Zhang, MK Jackson, and JR Long. Millimeter-wave characteristics of SiGe heterojunction bipolar transistors and monolithic interconnects in silicon technologies. Proceedings of the International Solid-State Circuits Conference, 2001, pp. 274–275. 9. R Aparicio and A Hajimiri. Capacity limits and matching properties of intermetal capacitors. IEEE Journal of Solid-State Circuits 37:384–393, 2000. 10. NM Nguyen and RG Meyer. Si IC-compatible inductors and LC passive filters. IEEE Journal of SolidState Circuits 25:1028–1031, 1990. 11. JR Long and MA Copeland. The modeling, characterization and design of monolithic inductors for silicon RF ICs. IEEE Journal of Solid-State Circuits 32:357–369, 1997. 12. JR Long and MA Copeland. Modeling of monolithic inductors and transformers for silicon RFIC design. Proceedings of the IEEE MTT-S International Symposium on Technologies for Wireless Applications, 1995, pp. 129–134. 13. AM Niknejad and RG Meyer. Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs. IEEE Journal of Solid-State Circuits 33:1470–1481, 1998. 14. JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. 15. SA Maas. Nonlinear Microwave and RF Circuits. Boston, MA: Artech House, 1997. 16. V Aparin and C Persico. Effect of out-of-band terminations on intermodulation distortion in common-emitter circuits. Proceedings of the IEEE International Microwave Symposium, 1999, pp. 977–980. 17. KL Fong. High-frequency analysis and linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network. IEEE Journal of Solid-State Circuits 35:1249– 1252, 2000. 18. SP Voinigescu, MC Maliepaard, JL Showel, GE Babcock, D Marchesan, M Schroeter, P Schvan, and DL Harame. A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE Journal of Solid-State Circuits 32:1430–1439, 1997. 19. JR Long. A low-voltage 5.5–5.8 GHz image-reject downconverter RF IC. IEEE Journal of Solid-State Circuits 35:1320–1328, 2000. 20. JR Long and MA Copeland. A 1.9 GHz low-voltage silicon bipolar RF front-end for wireless personal communications systems. IEEE Journal of Solid-State Circuits 30:1438–1448, 1995. 21. D Cassan and JR Long. A 1 V transformer-feedback low noise amplifier for 5–6 GHz WLAN in 0.18 mm CMOS. IEEE Journal of Solid-State Circuits 38:427–435 2003. 22. JR Long, M Copeland, S Kovacic, D Malhi, and D Harame. RF analog and digital circuits in SiGe technology. Proceedings of the International Solid-State Circuits Conference, 1996, pp. 82–83. 23. V Aparin, P Gazzerro, J Shou, B Sun, S Szabo, E Zeisel, T Segoria, S Ciccarelli, C Persico, C Narathong, and R Sridhara. A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability. IEEE International Solid-State Circuits Conference, 2002, pp. 234–235. 24. M Tanabe, T Fukuda, and K Nishii. Step gain amplifier with impedance unchanged in gain control. IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 209–212. 25. SY Yue, D Ma, JR Long, and DL Harame. A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3 subharmonic injection locking. IEEE International Solid-State Circuits Conference, 2004, pp. 388–399.

© 2006 by Taylor & Francis Group, LLC

Wireless Building Blocks Using SiGe HBTs

9.7-1047

26. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz transceiver circuits in SiGe bipolar technololgy. IEEE International Solid-State Circuits Conference, 2004, pp. 442–443. 27. S Kumar, M Vice, H Morkner, and W Lam. Enhancement mode GaAs PHEMT LNA with linearity control (IP3) and phased matched mitigated bypass switch and differential active mixer. Proceedings of the IEEE International Microwave Symposium, 2003, pp. 1577–1580. 28. P Leroux, M Steyaert, V Vassilev, and H Maes. A 1.3 dB NF CMOS LNA for GPS and 3 kV HBM ESD-protection. Proceeding of ESSCIRC, 2002, pp. 335–338. 29. WE Main and JC Durec. A linear class AB single-ended to differential transconverter suitable for RF circuits. Proceedings of the IEEE International Microwave Symposium, 1996, pp. 1071–1074. 30. B Gilbert. The micromixer: a highly linear variant of the Gilbert mixer using a bisymmetric class-AB input stage. IEEE Journal of Solid-State Circuits 32:1412–1423, 1997. 31. J Durec. An integrated silicon bipolar receiver subsystem for 900-MHz ISM band applications. IEEE Journal of Solid-State Circuits 33:1352–1372, 1998. 32. PJ Sullivan, BA Xavier, and WH Ku. Low voltage performance of a microwave CMOS Gilbert cell mixer. IEEE Journal of Solid-State Circuits 32:1151–1155, 1997. 33. DB Leeson. A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE 54:329– 330, 1966. 34. A Hajimiri and TH Lee. A general theory of phase noise in electrical oscillators. IEEE Journal of Solid-State Circuits 33:179–194, 1998. 35. A Demir, A Mehrotra, and J Roychowdhury. Phase noise in oscillators: a unifying theory and numerical methods for characterization. IEEE Transactions on Circuits and Systems I 47:655–674, 2000. 36. A Demir. Phase noise and timing jitter in oscillators with colored-noise sources. IEEE Transactions on Circuits and Systems I 49:1782–1791, 2002. 37. P Vanassche, G Gielen, and W Sansen. On the difference between two widely publicized methods for analyzing oscillator phase behavior. IEEE ICCAD, 2002, pp. 229–233. 38. Y Ou, N Barton, R Fetche, N Seshan, T Fiez, UK Moon, and K Mayaram. Phase noise simulation and estimation methods: A comparative study. IEEE Transactions on Circuits and Systems I 49:635–638, 2002. 39. A Hajimiri and TH Lee. Design issues in CMOS differential LC oscillators. IEEE Journal of SolidState Circuits 34:717–724, 1999. 40. JN Burghartz, DC Edelstein, M Souyer, HA Ainspan, and KA Jenkins. RF circuit aspects of spiral inductors on silicon. IEEE Journal of Solid-State Circuits 33:2028–2034, 1998. 41. M Danesh and JR Long. Differentially-driven symmetric spiral inductors. IEEE Transactions on Microwave Theory and Techniques 50:332–341, 2002. 42. D Cheung and JR Long. Differentially shielded monolithic inductors. IEEE Custom Integrated Circuits Conference, 2003, pp. 95–98. 43. P Andreani and S Mattisson. On the use of MOS varactors in RF VCOs. IEEE Journal of Solid-State Circuits 35:905–910, 2000. 44. JWM Rogers, JA Macedo, and C Plett. The effect of varactor non-linearity on the phase noise of completely integrated VCOs. IEEE Journal of Solid-State Circuits 35:1360–1367, 2000. 45. NHW Fong, J-O Plouchart, N Zamdmer, L Duixian, LF Wagner, C Plett, and NG Tarr. A 1-V 3.8 — 5.7-GHz wide-band VCO with differentially tuned accumulation MOS varactors for common-mode noise rejection in CMOS SOI technology. IEEE Transactions on Microwave Theory and Techniques 51:1952–1959, 2003. 46. J-M Mourant, J Imbornone, and T Tewksbury. A low phase noise monolithic VCO in SiGe BiCMOS. IEEE Radio Frequency Integrated Circuits Symposium, 2000, pp. 65–68. 47. MA Margarit, JL Tham, RG Meyer, and MJ Deen. A low-noise, low-power VCO with automatic amplitude control for wireless applications. IEEE Journal of Solid-State Circuits 34:761–771, 1999.

© 2006 by Taylor & Francis Group, LLC

9.7-1048

The Silicon Heterostructure Handbook

48. M Zannoth, J Fenk, A Springer, and R Weigel. A single-chip Si-bipolar 1.6 GHz VCO with integrated bias network. IEEE Radio Frequency Integrated Circuits Symposium, 1999, pp. 117–120. 49. M Soyuer, JN Burghartz, HA Ainspan, KA Jenkins, P Xiao, AR Shahani, MS Dolan, and DL Harame. An 11-GHz 3-V SiGe voltage controlled oscillator with integrated resonator. IEEE Journal of SolidState Circuits 32:1451–1454, 1997. 50. H Li, H-M Rein, R Kreienkamp, and W Klein. 47 GHz VCO with low phase noise fabricated in a SiGe bipolar production technology. IEEE Microwave and Wireless Components Letters 12:79–81, 2002. 51. F Svelto, S Deantoni, and R Castello. A 1 mA, 120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO. IEEE Custom Integrated Circuits Conference, 2000, pp. 577–580. 52. B DeMuer, N Itoh, M Borremans, and M Steyaert. A 1.8 GHz highly-tunable low-phase-noise CMOS VCO. IEEE 2000 Custom Integrated Circuits Conference, 25-5, 2000, pp. 585–588.

© 2006 by Taylor & Francis Group, LLC

9.8 Direct Conversion Architectures for SiGe Radios 9.8.1 9.8.2 9.8.3 9.8.4

Overview of Direct Conversion Architectures .... 9.8-1050 Direct Conversion System Aspects and IC Abstraction ....................................................... 9.8-1051 Choice of Differential Architecture ..................... 9.8-1051 Transmitter and Receiver Considerations ........... 9.8-1054 Nonidealities in the Signal Paths . Considerations in the Transmitter Signal Path . Considerations in the Receiver Signal Path . Signal Generation Path for Transmitter and Receiver

9.8.5

Impacts of System Performance........................... 9.8-1057 Impact of System Performance on Device Technology . Impact of System Performance on Circuits

9.8.6

SiGe Direct Conversion Radio: A Practical Example.................................................................. 9.8-1059 System Considerations . Circuit Design . Low-Noise Amplifier (LNA) . Downconversion Mixers . Downconversion Mixers: Practical Example . Signal Generation Path

Sudipto Chakraborty and Joy Laskar Georgia Institute of Technology

9.8.7 9.8.8 9.8.9 9.8.10 9.8.11

The Integration: Interfaces and Layout............... 9.8-1067 Characterization of Receiver Front End.............. 9.8-1069 Fabricated Hardware and Results ........................ 9.8-1069 Compensation and Corrections ........................... 9.8-1071 Future of Direct Conversion Radios.................... 9.8-1072

In this chapter, we describe direct conversion architectures for radio applications and the impact of silicon germanium technology on such architectures. First, we describe the radio architecture and illustrate various challenges in the development of such architecture from an integration standpoint. Later, we demonstrate the development of two variants of fully monolithic radios in a second-generation silicon germanium BiCMOS technology. We also cover various practical aspects of these radios, with an appreciative viewpoint of both the simplicity as well as the complexity of such developments in a siliconbased environment. Afterwards, we present case studies of direct conversion radios for IEEE802.11a standard. While this standard is a representative of high data rate wireless system, similar approaches can be taken for other wireless standards as well.

9.8-1049 © 2006 by Taylor & Francis Group, LLC

9.8-1050

The Silicon Heterostructure Handbook

9.8.1 Overview of Direct Conversion Architectures Since its inception in the early 20th century, wireless engineering has come a long way. Most of the basic principles of the sophisticated radio architectures and their abstractions, as we see it today, were developed using vacuum tubes around 1930 [1]. Starting with the basic foundation laid down by Maxwell (1883), and with subsequent inventions in wave propagation and wireless telegraphy by Hertz, Bose, Marconi, and others, wireless technology was born around 1900 in a very primitive form. Demonstration of the superheterodyne receiver by Armstrong dates back to as early as 1924. Armstrong’s superheterodyne receiver underwent considerable refinement during the 1920s and 1930s. This was the time when radio pioneers considered the use of homodyne architectures for single vacuum tube receivers. Following the invention of the transistor in 1947, and many more refinements in the semiconductor platform, the concept of integrated circuit gradually changed focus from small scale to medium and large scale, leading to the vision of ‘‘system-on-chip (SOC)’’ or ‘‘fully monolithic implementation’’ to support extremely diverse applications. A radio is a complex mixture of highly diverse functionalities, and the challenges to realize a miniaturized high-performance integrated radio are quite significant. The challenges exist in all levels of communication systems, integrated circuits, and device technologies. Traditional superheterodyne architectures result in very high performance, while requiring high-quality factor components for radio functionality. The success of direct conversion architectures for practical applications was quite delayed due to its performance limitations, which require careful trade-off among system, circuit, and integration perspectives. Vance at ITT was the first to apply direct conversion for pager applications by means of a single-chip receiver [2]. During the early 1980s, direct conversion receivers were developed at Motorola as a possible way to implement compact radios. The major obstacle for the success of the direct conversion architectures is the presence of spectral component around DC for various physical layer standards, requiring careful system-level considerations. The evolution of radio architectures, and their silicon abstractions has primarily focused on the frequency planning, and reducing the number of analog processing blocks (e.g., filters, amplifiers). This decision is also based on a number of unwanted external signals (e.g., blockers, cross-talk among various wireless terminals), as well as internal real estate (utilization of single oscillator versus multiple oscillators and PLLs). The benefits of superheterodyne architecture could not be fully realized without judicious frequency planning and utilization of high-quality filters. However, to minimize the real estate for radio abstractions in silicon, the architectures have continuously scaled from high intermediate frequency (IF) to medium IF to very low IF, leading to zero IF. In this section, we will limit our scope to system-level challenges with implementation details for a zero IF (or direct conversion) radio. What is so different and attractive about a direct conversion radio? Why is every radio abstraction targeted to be direct conversion architecture in the first place irrespective of the application, given the fact that it is well known as ‘‘difficult-to-implement’’? The answer to the first question is quite straightforward. A superheterodyne architecture requires more than one stage of frequency shifting (upconversion or downconversion, and use of two or more IF frequencies). This usually leads to the choice of multiple oscillators on chip, and filtering requirements for image rejection purposes. Direct conversion eliminates these considerations, and simplifies the task of a system designer in terms of a judicious choice of IF frequencies such as to achieve a desired radio performance in terms of blockers (modulated or unmodulated). The elimination of several IF stages also helps realize a compact die area for such implementations. The answer to the second question follows from the previous argument; proven the fact that it is lowest area approach, we always lean toward understanding the fundamental limitations of an integrated direct conversion radio abstraction as well as envisioning silicon germanium as a technology platform to implement such systems.

© 2006 by Taylor & Francis Group, LLC

Direct Conversion Architectures for SiGe Radios

9.8-1051

9.8.2 Direct Conversion System Aspects and IC Abstraction Any communication system design is a combination of performance parameters of different building blocks, the big envelope of which includes gain, linearity, and noise. These three performance aspects are also accompanied by the power dissipation and the cost of implementation for each of the building blocks, and should be optimized by an intuitive, rather clever approach using a combination of techniques, such as frequency planning, various interfacing impedances, etc. To appreciate the classification of building blocks in this manner, we consider a high-frequency low-noise amplifier and a highfrequency oscillator. Noise contributed by each of these blocks is different not only from a circuit perspective, but also from fundamentals of device noise characteristics. The noise contribution from the amplifier is also dependent on the interfacing impedance at the input. The traditional 50 V interfacing impedance standard was established as a compromise between signal handling power and attenuation for coaxial cables since the World Ware II times, and has been used ever since. One could reasonably deviate from that for an integrated circuit perspective. Thus, the noise, gain, and linearity parameters can vary significantly depending on the interfacing impedance, and our definition and calculation based on 50 V interfaces need to be refined to consider such possibilities. Communication building blocks are usually separated from each other in terms of their functionalities (such as frequency conversion and amplification etc.). Hence, depending on the architecture, the choices and the distribution of the system parameters in terms of gain, linearity, and noise should be performed by system designer as prior to the silicon implementation. Often times the traditional 50-V-based interface does not prove optimum from power consumption and real estate perspectives. Also, given a fixed amount of power dissipation, one variable usually trades off with another in any particular circuit abstraction (e.g., for a fixed gain, the noise figure of a circuit might exhibit a trade-off with the linearity performance with a given power consumption). In this section, we would classify the unwanted system variables in terms of external and internal effects. An interference signal (in-band or out of band, modulated or unmodulated) can be categorized as an external factor as it is picked up from the environment, and a leakage from the VCO to the other parts of the integrated system could be considered as an internal factor. Both categories impact the system in different ways, such as consuming more current in the circuit block to enhance linearity, or careful isolation and frequency planning techniques in the front-end to mitigate SNR degradation of the message spectrum. Like other radio architectures, direct conversion could also be visualized as a combination of two fundamental functionalities: down or up conversion and demodulation or modulation. In this section, we will focus primarily on the front-end implementations considering down or up conversion and their impact on the demodulation or modulation functionality. We will also see that some of the system impairments affect a superheterodyne architecture in a different manner compared to direct conversion architecture. With this introduction, let us explore the various system-level challenges in a direct conversion radio architecture as shown in Figure 9.8.1. The critical considerations for such architectures are also illustrated in Table 9.8.1. The scheme is essentially an I/Q modulator in the transmitter path, followed by a single sideband mixing technique and amplification, depending on the necessary output power level and coverage. In the receiver, differential signals are generated at the amplifier or after the amplifier, using a balun, with an I/Q signal planning for down conversion to baseband. In the following sections, we describe the key elements to the success of direct conversion architectures.

9.8.3 Choice of Differential Architecture In both the transmitter and the receiver, LO leakage and linearity requirements pose restrictions on the system design. The architecture must conform to a fully differential topology to cancel any common mode noise components, an extremely critical consideration for high-frequency circuits and systems. These advantages trade-off with additional power and area requirements of such implementations to

© 2006 by Taylor & Francis Group, LLC

9.8-1052

The Silicon Heterostructure Handbook

MIX_I

DSP

ADC MIX_Q LNA

VGA

Receiver 0 Signal path

90

Quadrature Generator

Transmitter

MIX_Q

PA

X2

270 180

VGA

BPF(active)

DAC

VCO & PLL

DBLR

DSP

MIX_I

(a)

MIX_I

ADC

DSP

MIX_Q LNA

VGA

Receiver /2

Signal path

VCO & PLL Divider & Quadrature

Transmitter

MIX_Q

PA

VGA

DAC

DSP

MIX_I (b)

FIGURE 9.8.1 Two different variants of direct conversion radios: (a) 1/2X architecture and (b) 2X architecture.

© 2006 by Taylor & Francis Group, LLC

9.8-1053

Direct Conversion Architectures for SiGe Radios TABLE 9.8.1

Impact of Building Blocks in Direct Conversion Radios

Building Blocks

Performance Metrics

Critical Considerations

VCO

Output voltage swing Usually differential topology Tuning range Phase noise Area Frequency dividers I/Q accuracy

Lower phase noise needed for closely spaced channels 1/f noise impacts the SNR of the message spectrum

Quadrature generators

Output voltage swing

Mixers

Clock waveform characteristics Division ratio: 2X/4X, etc. Noise degradation Polyphase networks Signal loss Bandwidth Accuracy (I/Q imbalance) Gain (Tx and Rx) Linearity (Tx and Rx) Noise figure (mostly Rx)

Variable gain amplifier (VGA)

Power consumption (Tx and Rx) Sideband suppression (mostly Tx) LO to RF isolation Mismatch IIP2 (mostly receiver) Gain

Linearity

Low noise amplifier

Noise figure Gain step Dynamic range Gain

Frequency dividers I/Q amplitude imbalance implies LO feedthrough in transmitter, phase imbalance implies sideband suppression Clock duty cycle error leads to the amplitude and phase imbalance

1/f noise from the switch pairs in case of downconversion mixer Transconductor core for broadband and small narrowband linearity characteristics LO to RF isolation impacts the DC offset performance (dynamic) Mismatch results in DC offset (static) IIP2 causes SNR degradation due to blocker (and cross modulation)

Different topologies (current steering, load switching, current switching) impact the performances in different ways Care must be taken not to saturate these amplifiers High dynamic range (80 to 90 dB) for cellular specification is a challenge

Similar considerations for other receiver architectures

Linearity Noise figure Stability Power consumption Single ended/differential

their single-ended counterparts. However, often, due to the symmetrical nature of differential topology, it helps eliminate any common-mode parasitic components (such as bondwire inductance, or parasitic node capacitance), which may lead to stability considerations in single-ended counterparts at high frequencies. Differential topology also enhances the dynamic range, and suggests the possibility of neutralization techniques using parasitic components at opposite phases [3]. In modern integrated radios, the realization of a fully differential architecture has been a necessary practice. Even if there is an absolute necessity to be single ended (a case where single-ended antennas need to be integrated with

© 2006 by Taylor & Francis Group, LLC

9.8-1054

The Silicon Heterostructure Handbook

LNA or PA directly), it is desirable that we adopt to the differential topology in the signal path as early as possible.

9.8.4 Transmitter and Receiver Considerations Nonidealities in the Signal Paths As described earlier, tremendous space compaction in the integrated direct conversion radios takes place due to the elimination of IF processing blocks (filters and amplifiers) and multiple oscillators in various parts of the transmitter and receiver chains. However, from a practical standpoint, there exists nonidealities in signal paths mainly due to the two reasons: (a) finite reverse isolation of RF building blocks and (b) imbalance in the signal paths in terms of amplitude and phase, leading to the SNR degradations. The first nonideality can be attributed to two effects. The first is the finite reverse isolation capability of the transistor (e.g., the reverse isolation is not infinite), which reflects to the finite reverse isolation of the whole circuit block. The second in this family is the finite isolation capability of low-resistivity semiconductor substrate (e.g., silicon). The substrate can be represented by a mesh of resistive and capacitive components in most part. In an integrated circuit, a signal can also propagate in the pad ring, causing unwanted disturbances. The imbalance in the signal path can be attributed to the presence of unequal traces in the signal path, and the accuracy with which the balance is maintained between different signal paths. A classic example of this effect would be the susceptibility of unequal load or presence of any signal dependent (nonlinear) behavior of components in the signal path.

Considerations in the Transmitter Signal Path In case of direct conversion radios, any nonideality in the transmitter signal processing chain would result in an in-band SNR degradation around the LO carrier frequency. In the transmitter signal path, any imbalance in the I/Q signal paths would give rise to LO leakage. The amplitude imbalance usually leads to LO feed through, which creates in band SNR degradation, while phase imbalance is responsible for the sideband suppression. The transmitter also needs to accommodate for the dynamic range, which can be quite high for certain applications (e.g., cellular, 80 to 90 dB dynamic range). It is quite important that the upconverted signal out of the I/Q modulators be at a level much higher than the input referred noise floor of the variable gain amplifier that is used to create such high dynamic range. Another important consideration for the transmitter is the error vector magnitude (EVM) requirements, which denotes the rotation of the constellation, and needs to be fairly low for a dense constellation (e.g., 64QAM, etc.). Apart from all these considerations, the transmitter must meet the FCC requirements in terms of spectral mask constraint. Noise is usually not a very critical consideration in the transmitter, and depending on the crest factor of the modulated signal judicious decision must be made in determining the amplifier operation (linear or nonlinear). However, it is quite challenging to accommodate the high dynamic range requirement in the VGA.

Considerations in the Receiver Signal Path Analogous to the issues present the transmitter, nonidealities in the direct conversion receiver lead to impairments around the zero frequency (or DC). SNR degradation happens in this case due to DC offset and 1/f noise from the devices. DC offset can be divided into two categories: (a) static DC offset, which results from the mismatches in the circuit components, such as transistors, resistors, etc., (b) dynamic DC offset, which is essentially caused by the finite reverse isolation present in a down conversion mixer, caused by the self-mixing, or any other mechanism (such as substrate leakage), leading to the self-mixing phenomenon. A classic example of dynamic DC offset is the DC offset variation effect in the receiver when a wireless terminal experiences different signal reflections from surrounding objects in the environment, and the degradations vary with time. Static DC offsets can be tuned out by some form of a calibration mechanism performed when the IC is powered up, but the dynamic DC offset needs

© 2006 by Taylor & Francis Group, LLC

Direct Conversion Architectures for SiGe Radios

9.8-1055

time-dependent averaging and cancellation, which is usually performed at baseband. Due to this effect, in any successful prototype demonstrating direct conversion architecture, the LO frequency is different from the RF frequency to minimize the number of nodes operating at the RF frequency (hence leading to self-mixing). The order of LO frequency determines the frequency scheme. If the LO frequency is n times the RF frequency, the architecture is referred to as ‘‘nX’’ architecture. Along with the DC offset phenomenon, 1/f noise resulting from the devices is also one cause of impairment in case of receivers. Any device technology, which is fast enough to accommodate the RF carrier frequencies, while exhibiting a low 1/f corner, is definitely the choice in this case. SNR degradation due to 1/f noise is a resultant of two factors, the first one is from the phase noise behavior of the VCO (where the device flicker noise essentially gets upconverted to the carrier frequency), and the second one is from the baseband amplifiers. At the baseband processing blocks, it is prohibitive to utilize capacitors due to area restraint, and filter out the 1/f components. As with the case of any building blocks, the input referred noise is minimized by maximizing the gain, to support the incoming signal with the required bandwidth, the gain should increase with a considerable increment in bias current, thus the baseband blocks in a direct conversion tend to consume more current, and it is very difficult to attribute direct conversion architecture as the lowest power radio architecture. Another way to assess this aspect is that the direct conversion receiver usually provides lower gain in the receiver frontend, thus requiring more baseband gain (while supporting the entire message spectrum bandwidth) to fall within the dynamic range of the preceeding signal-processing blocks. Direct conversion radio architecture is a low real estate implementation, but its success is dependent on the area of the DC offset compensation circuits, which is often a function of the physical layer communication standard under consideration. Apart from the fundamental analogies between direct conversion transmitter and receiver, one fundamental difference exists between the two in terms of second-order intermodulation parameter, IIP2. In direct conversion receivers, the second-order intermodulation becomes quite important to accommodate the effect of the blockers present with a reasonable SNR degradation. Intuitively, two blockers present at frequencies F1, and F2, where jF1–F2j is within the message bandwidth would lead to SNR degradation. The situation would be worse if there is a spreading effect in the process (i.e., any or both the blockers are modulated sources with some finite bandwidth around them), as the modulation can get transferred to the desired signal (also referred to as ‘‘cross modulation’’). This is a major concern for many cellular-based systems. Figure 9.8.2 shows the various degradation aspects of direct conversion receivers. Dynamic range of a receiver is determined by the noise floor and the maximum detectable signal level. The noise floor is essentially determined by the thermal noise floor along with the bandwidth, while the maximum allowable signal consideration is dependent on the linearity of the frontend. This is the case when transmitter and receiver do not operate simultaneously (time division duplex system, TDD). A fundamental deviation from this consideration occurs when transmitter and receiver operate simultaneously on closely spaced frequency bands (frequency division duplex, FDD). Such is the case with WCDMA systems and even using a diplexer system to perform frequency selective filtering, the finite amount of transmitter power leaks into the receiver and raises the noise floor. Thus, high-sensitivity FDD cellular phones usually pose most stringent system specification on practical implementations.

Signal Generation Path for Transmitter and Receiver With the illustration of the signal paths of transmitter and receivers, let us consider the various aspects of the signal-generation path and impacts on the performance of the transceiver subsystem. The major considerations in this regard would be on the amplitude and phase imbalances of the various signal paths, and the frequency planning. Various circuit blocks generate harmonics (and not subharmonics) due to standard nonlinearity effects (such as odd-order frequency components in a hard-driven differential pair) or mismatch effects (a mismatched differentia pair would give rise to second- or even-order components). Let us consider the integrated direct conversion transceiver architecture shown in Figure 9.8.1. There have been two different approaches to design the signal generation path:

© 2006 by Taylor & Francis Group, LLC

9.8-1056

The Silicon Heterostructure Handbook

fLO

SAW

Flicker Noise

fa fb

fIMAGE

f1 f2 2f1-f2

IF

fLO

out of band interference fa fb

f1 f2

LPF

2f1-f2

(a)

RF

2f2-f1

RF Spectrum

Flicker Noise HPF

Dc-offset IM2 IM3 image desired signal

LNA

Signal+ dcLO(t)+dcimb

2f2-f1

RF Spectrum

Demodulated signal

RF signal

Leakage and radiation LO (b)

AM Noise (c)

AM modulated interferer

FIGURE 9.8.2 Illustrations of direct conversion frequency scheme: (a) comparison with superheterodyne scheme (the upper half of the down converted spectrum is described for illustration of 1/f noise and second-order intermodulation), (b) causes of DC offset, and (c) effect of second-order nonlinearity, and SNR degradation due to cross modulation.

(a) generate a lower frequency than the RF frequency (usually a subharmonic tone), and multiply by a frequency multiplier with the generation of necessary quadrature phases from a phase shifter, (b) generate a higher frequency than the RF frequency (usually a harmonic tone) and divide down by frequency dividers. The frequency dividers utilize static frequency division topology using D-type flipflops, and a divide by 2 or a divide by 4 topology is fairly common. The choice of one architecture over the other is performed by system consideration in terms of I/Q accuracy, bandwidth of accurate quadrature generation, requirements of buffers, the power dissipation for the VCO operation at desired frequency, and the VCO pulling effects caused by the nonlinearity of other parts of the integrated transceiver. One example of approach (a) consisting of differential VCO, frequency multiplier, harmonic filter, and polyphase filter is shown in Figure 9.8.1(a), with the summary shown in Table 9.8.2. The benefit of such approaches in terms of using a low-frequency VCO is offset by the losses and parasitics incurred in polyphase filters and the power consumption of the buffers for signal boosting. Polyphase filters are quite susceptible to the various injected harmonics of the signal, and an appropriate filtering must be performed. Use of a passive inductor for superior phase noise leads to bigger real estate. Also, such schemes prove immune to the pulling problems, as there is no scope of a subharmonic tone generation (and hence leakage associated) from the high-power amplifiers at high frequency. However, one drawback of this approach is the accuracy of quadrature generated from the polyphase filters over relatively narrow bandwidth, susceptibility to parasitics, and asymmetric phase shifts due to unequal loading effects. In comparison, the architecture option in (b) results in fairly accurate quadrature signals, while consuming more power in the differential VCO core (due to its high-frequency operation), as well as small real estate (due to miniaturization of inductor dimension at high frequency). However, this

© 2006 by Taylor & Francis Group, LLC

9.8-1057

Direct Conversion Architectures for SiGe Radios TABLE 9.8.2

Comparison of the Different Architectures in the Signal Path for Direct Conversion Radios

Building Blocks

Submultiple Frequency Planning (1/2X)

Multiple Frequency Planning (2X)

VCO

Consumes less power Occupies more area (with passive inductor) Not susceptible to pulling effects Frequency multiplier

Consumes more power Occupies less area (with passive inductor) Susceptible to pulling effects Frequency divider

Accuracy is consideration Generates harmonics, requiring on-chip filtering Requires phase shifting in the input signals (usually 908) to avoid any DC perturbation at the output

Usually quite accurate Usually static divider configuration using master/slave D flip-flops Usually no filtering needed

Frequency conversion blocks

Polyphase filters

Generates quadrature Provides signal loss, leading to additional consumption in buffers Susceptible to parasitics Susceptible to imbalances in the signal path, and harmonics of the input tone Susceptible to unequal loading in the various signal paths

Susceptible to duty cycle errors, clock skews, requiring cancellation circuitry Not applicable

approach is susceptible to VCO pulling effects resulting from high-power PAs (VCO frequency is divided by 2 using dividers, and then second-order nonlinearity resulting from high-power PA results in the same frequency as the VCO and interacts with it). Some of these effects can be mitigated by using a fully differential scheme (generation of lower quantities of 2X frequencies due to mismatch), or moving to a 4X frequency scheme, leading to even lower VCO pulling and real estate, while consuming more power in the VCO core. Another important consideration is the susceptibility of such approaches to duty cycle errors in the differential signals resulting from the VCO. Transitioning of frequency divider at both the edges of signal waveforms would be quite susceptible to duty cycle errors, whereas a frequency divider operating at the same edges of the incoming VCO signal would be immune to such effects, but be susceptible to clock jitter. All the above effects are further complicated by the process and temperature variation effect in the semiconductor processes.

9.8.5 Impacts of System Performance Impact of System Performance on Device Technology It might seem at this point that availing the advantages of various semiconductor process technologies and integrating them in a system in package is the most optimum approach, as in that case we could avail the semi-insulating property of different substrates to reduce leakage and to realize high-quality factor passive components in the RF domain. While the option remains attractive from a fundamental standpoint, in most of the cases it is frustrated by the complexity in terms of interfacing impedances and packaging considerations. Silicon, as a platform is cheaper compared to its counterparts, and hence judicious circuit–system partitioning should be performed for the success of direct conversion radios. Hence, one should continuously look for silicon platforms, which support high cutoff frequency devices, and superior passives, while maintaining a reasonable cost. Given the above considerations, we revert to the fundamental requirement of direct conversion architectures. Any high-frequency block requires high fT, fmax, low-noise and high-breakdown capabilities. SiGe BiCMOS technology offers the flexibility to utilize bipolar and MOS transistors along with the

© 2006 by Taylor & Francis Group, LLC

9.8-1058

The Silicon Heterostructure Handbook

high-quality factor passives. MOS transistors usually consume more current for the same transconductance in a given area, and exhibit more parasitic capacitances, thus lowering the speed. As a surface device, the noise characteristics of MOS transistors are usually an order of magnitude worse compared to that of the bipolar transistors. Broadband noise is important for all receivers, in terms of the noise floor, but 1/f noise is the most degrading factor in case of direct conversion architecture, indicating the superiority of bipolar devices in this regard. Also, the choice of bipolar transistors proves optimum as a low input impedance stage as part of a low-noise amplifier. Bipolars also prove superior as part of the LO buffers, as they exhibit very low input parasitic capacitance, eliminating the need of inductive loading. However, MOS proves advantageous compared to bipolars in various aspects such as (a) linear differential transconductor cells and (b) switching elements (MOS performs switching without a voltage shift from input to the output). Both devices are fundamentally capable of realizing direct conversion radio abstraction, but the high 1/f corner of MOS might prohibit its use in many sophisticated wireless applications. Another drawback of utilizing MOS transistors is the presence of body bias, which leads to significant nonlinearity effects at large swing operation. Inductors perform a major role to achieve various functionalities, and the benefit of passive inductors in terms of higher dynamic range over their active counterparts almost always come with the compromise in die area, and electromagnetic interactions with similar elements depending on the direction of current flow. Apart from the standard technology (actives: MOS, bipolar, passives: resistor, capacitor, inductor, etc.), it sometimes proves quite effective to avail a Schottky barrier diode. Schottky barrier diodes are potentially the highest frequency nonlinear devices available in a given technology module, and can be effectively used as mixing devices. Mixing techniques using Schottky barrier diodes, as well as several interesting harmonic effects, are quite attractive for direct conversion architectures [4]. RF system performances are sometimes impacted by the mismatches in the devices, which essentially result from the inaccuracy caused by the variation in the minimum fabrication dimension (length in case of deep submicron CMOS, emitter width in case of bipolars). Hence, the choice of device dimension might trade-off with matching characteristics in some cases. For highly sensitive building blocks at RF frequencies, various isolation structures are beneficial from a signal injection perspective, and the success of a mixed-signal system is heavily dependent on such features.

Impact of System Performance on Circuits The circuits in direct conversion system must also provide a high level of reverse isolation. For the case of a LNA, a cascode topology provides about 30 dB reverse isolation, which is quite attractive in terms of direct conversion architecture. It might seem to the reader that an increasing number of such stages might give all the reverse isolation we would need to have DC offset under control, if we were to enjoy the freedom of consuming more current in the front end. While this proves to be a viable option, the actual implementation may be frustrated by the substrate leakage and presence of feedback loops, resulting in potential stability problems. The front-end circuits in their generic form consist of one or more of building blocks such as a transconductor core (V-I), a current switching core, an impedance network, etc. The signal levels and frequencies could define the functionality of the same circuit as a mixer, frequency multiplier, cascode amplifier, and a variable gain amplifier. Bipolar devices enjoy the benefit of the fact that the transconductance is only dependent on the bias currents, thus not requiring any scaling (hence lower parasitics) in geometry, leading to lower parasitics in most cases (except low noise requirements), implying the potential elimination of inductors in the LO buffer to minimize die area. Degeneration can be used to enhance linearity, and the output impedance from the current source should be high to realize higher IIP2 from the mixer cores, and high common mode rejection in case of differential amplifier topology. Input offset voltage and input referred noise of an amplifier could be reduced by increasing the gain of the amplifier. Offset voltage should be paid careful attention at low frequencies and near DC, while noise is important at RF frequencies.

© 2006 by Taylor & Francis Group, LLC

Direct Conversion Architectures for SiGe Radios

9.8-1059

Irrespective of various efforts and reports of research, it has been observed that fundamental developments in the area of circuit topology and functionality have been rather slow. Due to tremendous developments in the area of different communication technologies, and the continued maturity of semiconductor platforms and integration requirements, RF circuits have been looked into from different perspectives, each of which is quite different from the other. The beauty of RF circuits lies in their interrelations with other peripheral blocks, approaches from analog and microwave domains, and presence of more number of performance variables than the number of circuit components. While some of these are true for analog circuits, one key distinction enjoyed by RF circuits is the presence of distributed nature of circuit components, which are most appropriately captured in microwave domain. This vision, along with the fundamental considerations of device noise and physical behavior at high frequencies, presence of uncertainties make RF circuits ever interesting to work with.

9.8.6 SiGe Direct Conversion Radio: A Practical Example With all the illustrations provided above, we now describe the design, implementation, and characterization of two SiGe BiCMOS radio front ends. For the sake of simplicity, and to illustrate the design complexity better, we focus mostly on the front end in this section. This implementation is done in 5 to 6 GHz band, with a target specification of IEEE802.11a high data rate wireless standard.

System Considerations Let us start our approach by understanding the IEEE802.11a standards to design an integrated receiver. We focus on two approaches. In the first approach, we study the design and implementation of the receiver system based on a 50 V interfacing impedance, and in the second approach, we illustrate the development of the receiver radios in an integrated fashion (i.e., a non-50-V-based approach). Operating in the 5 to 6 GHz frequency range, IEEE802.11a utilizes orthogonal frequency division multiplexing (OFDM) to achieve high data rate, while providing robustness to multipath interference effects (intersymbol interference). This standard is capable of supporting high data rates up to 54 Mbps and more. However, due to the high crest factor (also referred to as peak to average ratio) of the OFDMmodulated signal waveform, the RF front end blocks require much higher linearity than that for standard quadrature phase shift keying (QPSK) or FM receivers. However, success of OFDM scheme lies in the use of efficient signal-processing algorithms and simplicity in baseband processing. The 5 to 6 GHz band is divided into two parts. The lower U-NII band contains eight channels within 200 MHz (5.15 to 5.35 GHz) and the upper U-NII band contains four channels within 100 MHz (5.725 to 5.825 GHz) [5]. Figure 9.8.3 shows the frequency allocation of such systems. An interesting observation can be made from Figure 9.8.3. Each channel consists of 52 OFDM subcarriers, arranged symmetrically around the zero carrier, each of which spans over 312.5 kHz. We can utilize the zeroth carrier as a null (no transmission at this subcarrier), leading to the implementation of ‘‘direct conversion friendly’’ system architecture due to the ‘‘DC-free’’ modulation scheme, with the compromise on the overall throughput by a small amount. At the receiver, a simple high pass filtering can be used to eliminate the unwanted degradation components (DC-offset and 1/f noise) without much SNR degradation for the message spectrum. With these considerations, two simple architectures can be defined as shown in Figure 9.8.4. The first one is a traditional approach based on 50 V interfacing impedance, thus simplifying the system-level calculations to derive the specifications of building blocks. The second approach is based on more integration, eliminating the ‘‘50 V’’ concept for the interfacing circuits. Placement of the filter before the LNA provides a better system design for rejecting out of band interferers and facilitates comparison of both the system architectures. However, the placement of the filter in-between the LNA and mixer helps to lower the noise figure of the entire receiver, and reject out of band blockers. The dashed portions indicate the front-end circuit blocks that we will discuss. A differential configuration in the front-end mixers minimizes the effect of common mode noise and provides high IIP2 needed for direct conversion

© 2006 by Taylor & Francis Group, LLC

9.8-1060

The Silicon Heterostructure Handbook

1/f noise

HPF response 312.5 kHz 30 M

20 M

20 M

30 M

20 M

f 5.15 G

FIGURE 9.8.3 receivers.

5.35 G

5.725 G

5.825 G

Illustration of frequency planning for IEEE802.11a, and the consideration of direct conversion

I /I I

Antenna

BPF

/I

RC HPF, LPF, BB Amp

Q

LNA

A/D and DSP

/Q Q

/Q /2

11.6 GHz

Freq. divider (a)

I /I I

Antenna

BPF

/I

RC HPF, LPF, BB Amp

Q

LNA

A/D and DSP

/Q Q

/Q /2

11.6 GHz

Freq. divider (b)

FIGURE 9.8.4 Two direct conversion receiver architectures under consideration: (a) 50-V-based interface and (b) non-50-V-based integrated approach.

© 2006 by Taylor & Francis Group, LLC

9.8-1061

Direct Conversion Architectures for SiGe Radios

receivers. A 2X frequency scheme has been adopted in this design for the ease of design for the frequency divider and the relatively high accuracy of the quadrature signals in the signal generation path. Thus, the frequency divider accepts differential signals at 11.6 GHz, while providing quadrature phases at 5.8 GHz at its output, to be interfaced with the downconverting mixers. The system calculations include the gain distribution, noise, I/Q imbalance, linearity parameters (IIP2, IIP3, P1dB). A detailed description of these calculations is provided in Ref. [6].

Circuit Design The design platform under consideration is a second-generation SiGe BiCMOS technology consisting of five metal layers with an additional thick metal layer for high Q inductor realization. The substrate resistivity is 10 to 20 V cm and bipolar transistors with emitter widths of 0.32, 0.44, and 0.8 mm are available. The process utilizes high-performance graded bandgap base NPN with fT and fMAX of 47 and 60 GHz, respectively, for standard NPN HBTs, and fT of 27 GHz for high breakdown NPN HBTs. It uses breakdown voltages of 3 and 5 V, respectively, for standard and high breakdown voltage devices. The high fT transistors use a pedestal structure, which prevents spreading of the currents in different directions as opposed to the conventional BJT structure, thus improving the fT. Gate oxide thickness of 5 and 7 nm used for MOSFETs (normal and 3.3 V, respectively). The NMOS and PMOS transistors have gate lengths of 0.24 mm. The top metal (called analog metal, AM) is 4-mm thick, and used for inductors and low loss interconnects. Isolation mechanisms include deep trench (DT) and shallow trench (ST). While selecting the technology modules for circuit design, several trade-offs exist. The minimum width devices exhibit lowest possible noise contribution due to small base spreading resistance, and poor device matching properties due to susceptibility to process variations. However, lowest width devices exhibit more peak fT compared to the other geometry variants. Choice of passive components (such as resistors and capacitors) is dependent on their parasitic component, temperature coefficient, and tolerance limits. These considerations result in an appropriate choice of components from a semiconductor platform, while building circuits.

Low-Noise Amplifier (LNA) The LNA is realized in a cascode topology with a switched gain configuration as shown in Figure 9.8.5. As can be shown from the figure, Q2 transforms the input voltage to current, Q1 accepts input current

VCC L2

C2 OUT C3 Q1

M1

RF_in C1 Vbias CTRL

Q2 R1

L1 M2

FIGURE 9.8.5 Circuit schematic for the cascode switch gain LNA.

© 2006 by Taylor & Francis Group, LLC

L3

9.8-1062

The Silicon Heterostructure Handbook

and provides output current, and the load network generates the voltage at the output. While the functionality of the load network is quite linear, the major component of nonlinearity is contributed by Q2, which is often improved by using degeneration, as other analog feedback techniques prove detrimental in terms of parasitics and stability at high frequency. A cascode topology is often used for high-frequency low-noise amplifier (LNA) circuit due to several advantages: (a) isolation of input and output, leading to separate matching considerations at both ports, (b) reduction of Miller multiplication effect, (c) high reverse isolation from output to the input. While the first two are important in case of any radio architectures, the reverse isolation aspect is critical to the success of direct conversion radios. Use of inductive degeneration helps realize a 50 V impedance at the input in a narrowband fashion. The high transconductance and superior noise performance are the key performance parameters for the choice of bipolar transistors over MOS. Due to the higher transconductance, the inductor dimension gets reduced, leading to space compaction on die. Other benefits of using bipolars in the main signal path are the presence of very low parasitic capacitances, which reduces signal attenuation and noise contribution from the cascode transistor (Q1), and at the same time favoring the presence of low impedance, such as 50 V (the optimum noise impedance of bipolar is usually lower compared to that of MOS due to the presence of significant current noise spectral density at the base). The input and output matching is implemented using fully monolithic inductor implementation. The input transistor Q2 transforms the input voltage into current by the transconductance property. Gain switching functionality has been realized by NMOS transistor pair, M1 and M2. When the control voltage is ‘‘LOW’’ or 0 V, both M1 and M2 are turned off, and the LNA functionality is governed by the bipolar transistors Q1 and Q2. This is referred to as the ‘‘high gain’’ mode operation of the LNA. The low gain mode occurs when the control voltage is at a ‘‘HIGH’’ state, typically raised to the supply voltage of the circuit. In this case, both the transistors, M1 and M2 are turned on. M2 provides a bypassing path to the input RF signal, and M1 provides a short between input and output terminals. This ensures a very little current flow to the base of the transistor, Q2, hence reduces the gain significantly. This particular gain switching approach disturbs the input match by a significant amount in the low gain mode. The gain step is about 20 to 25 dB while incorporating this technique. However, if it is desirable that the input match and the RF characteristics (such as broadband noise and linearity) remain constant, the approaches shown in Figure 9.8.6 prove to be better alternatives than are shown in Figure 9.8.5. Figure 9.8.6(a) provides a scheme where current steering approach has been adopted, while Figure 9.8.6(b) provides a scheme where input and output match is kept constant while using the middle stage as a gain control stage (or bypassing stage). In practical receivers, the control voltage is determined by a

Out Q2 Q3

Out

Vc Q1

Q1

In

Q2 Vc

In

(a)

FIGURE 9.8.6 Alternate methods of providing gain switching in LNA.

© 2006 by Taylor & Francis Group, LLC

(b)

Q3

9.8-1063

Direct Conversion Architectures for SiGe Radios

digital control from the baseband DSP, after the signal strength has been detected by the receiver signal strength indicator (RSSI). A PTAT current source is desirable to obtain a constant transconductance (gm ¼ Ic / Vt) over the temperature range. The input matching of the LNA is kept the same for both the architectures, while the output network is combined with the downconversion mixers.

Downconversion Mixers The basis of the mixer architectures is the presence of a transconductor cell, followed by the switch core and the load network. The transconductor core converts the input voltage to current, and hence the dominating source of nonlinearity in the mixer. The switch network switches the current generated by the transconductor core, by the application of an auxiliary waveform called ‘‘local oscillator.’’ The load network is used to perform current to voltage conversion, and works in a fairly linear fashion (exceptions to this are the use of a voltage-dependent capacitance in an RC low pass filter as the load network of a high voltage gain mixer, where the high output voltage swing can change the capacitance value, and hence the cutoff frequency). This configuration is the basis of a Gilbertcell mixer as shown in Figure 9.8.7 in terms of a single-ended interface, where a current source is also employed to provide a fixed current (which is essential to mixer’s conversion gain, noise, and linearity performances). In this section, we first demonstrate the key functional elements of Gilbertcell mixers, followed by a detailed explanation of the specific implementation details. Many considerations apply to many similar families of differential circuits.

VCC R6

C6

C5

R7 Q11

LO_M

Q10

Vbias Q1

Q2

Q3

Q4

IF+ R5

LO_P

RF_in

R8

Q5

Q6

C1

R 10

R4

L2

L1 VCC

C3

R2 Q8

Q9 Q7

C2

C4 R9

R1

R3

FIGURE 9.8.7 Circuit schematic of single-ended Gilbertcell mixer.

© 2006 by Taylor & Francis Group, LLC

IFR 11

9.8-1064

The Silicon Heterostructure Handbook

The Current Source Let us pay close attention to the specific implementations of such mixers at high frequencies. The current source should provide high output impedance (for high rejection of common mode and secondorder effects), low parasitic capacitance at the output node (not to create a pole at the high frequencies, which essentially is transformed into a zero at the output), low voltage swing (to reduce headroom, and minimum common mode voltage to accommodate high signal swing). Even order effects become significant when the transconductor core is driven asymmetrically (not a fully balanced fashion). Bipolar transistors prove to be superior compared to MOS in this regard, as the headroom needed is much less (Vce,sat) in case of a bipolar transistor, while providing high output impedance, and much lower parasitic capacitance at the output node. In an MOS (rather NMOS) implementation, however, the common practice is using wide swing cascode current source, which exhibits significant parasitics at high frequency, as the headroom is an inverse square root function of the transistor geometry [7]. Placement of the current source in the middle of the differential pair would also cancel the current source noise in a correlated fashion at the differential outputs. Choice of Transconductor From a differential transconductor’s perspective, a bipolar transconductor provides lower linearity (due to tanh transfer characteristics, which is limited till 78 mV of differential swing), compared to an MOS differential pair square law characteristics, limits set by the overdrive voltage. However, use of an MOS differential pair as a high impedance stage is frustrated by the presence of large input device capacitance. To achieve similar transconductance performance with a given bias current, MOS usually consumes more area compared to a bipolar, leading to higher parasitics. Thus, use of bipolars at current densities slightly lower than that to achieve peak (to accommodate variations) Ft is usually preferred for higher transconductance, and a degeneration inductor can be utilized to provide higher linearity, at the expense of reduced transconductance due to the presence of negative feedback. Inductors do not consume voltage headroom and do not generate noise. In a downconversion mixer, the thermal noise of the transconductor stage becomes an important design criterion. The transconductor proves to be a good voltage-controlled current source if the input impedance of the stage is much higher compared to the driving source impedance (so that the full voltage drops across the input stage), and the output impedance is fairly high (which is basic property of a current source). We also desire that the node parasitics remain extremely small for any unwanted noise perturbation and signal attenuation. The basic operation of the transconductor is similar to the input stage of a differential pair [8], and would be omitted here to avoid duplicity. A fundamental difference exists between the transmit and receive mixers in terms of linearity considerations. In case of transmitter transconductance core, the linearity consideration is a combination of broadband harmonic effects (harmonics of the input tones fall in band, such as 3X, 5X harmonics of the input differential tone at 10 MHz fall inside the band and corrupt the signal) and narrowband phenomenon (intermodulations of the input tones can also fall in band), while in case of receiver it is a narrowband phenomenon as the harmonics of the input tone almost always fall out of band (harmonics of 2.4 GHz tone falls at 7.2G, 12G etc., assuming a differential operation). However, the intermodulations (IM2 and IM3) usually fall in-band in case of a receiver, and cause degradation. Since the harmonic generation and intermodulation phenomena are caused by the nonlinearity of the transconductor stage, the transconductor stage at the transmitter would usually require higher linearity. The Switching Pair The switching pair is usually a combination of differential pairs, driven in proper phases. While the principle of operation is similar to that of a differential pair, careful attention should be paid to the use of choice of devices and important aspects for the RF performances, such as noise and linearity. Switching pair has two inputs: (a) an input current at RF frequency from a high output impedance source (e.g., the transconductor), (b) a switching waveform (called ‘‘local oscillator’’) in the voltage domain characterized by the amplitude and the frequency of operation. The switching core usually

© 2006 by Taylor & Francis Group, LLC

Direct Conversion Architectures for SiGe Radios

9.8-1065

presents fairly low input impedance to the input RF current source (assuming the lead impedance is much smaller compared to the output impedance of the transistors, which is usually the case), which is desirable for a current amplifier interface. The input impedance of the switching pair is mostly dominated by parasitics, which requires inductors in the LO buffers for cancellation purposes. Hence, low parasitic and high-speed devices, such as bipolar transistors, are ideal candidates for the switching core. Due to the lower parasitic capacitance presented at various nodes, the bandwidth limitation in a bipolar implementation is also quite negligible. In the switching pair, the exponential characteristics of a bipolar differential pair become attractive, as a fairly low signal swing is needed to completely steer the current from one device to another in the differential pair, leading to low current consumption in the LO buffers and possible elimination of an inductive load, leading to further miniaturization. It is important at this stage that we identify the sources of noise from a switching pair. The most dominating source of noise from the switching pair is the flicker noise, of the transistors, which is transferred to the output node without any frequency translation, at the zero crossing of the switching instants of the LO waveform. The noise contribution reduces with increasing the slope of the LO waveform, presence of lower parasitic capacitance at the emitter (or source), and inherent low flicker noise of the devices. Since the switching occurs in the current domain (and not in the voltage domain), there is no fundamental drawback such as voltage shift of bipolar transistors from emitter to collector (which hinders their use for a sample and hold switch) for using bipolars in a current mode switch core. Hence, bipolar transistors are the preferred choice for switch core devices. The high output impedance of bipolars also helps realize a summing node of the downconversion mixer core. One important consideration in the switching core is the mismatch of the devices. A fully differential operation is conducive to high-performance direct conversion receivers in terms of perfect LO cancellation, and sideband suppression effects. However, in practical implementation, mismatches are always present, and difficult to completely eliminate even with the best preventive (such as common centroid layout) and predictive (such as extensive statistical simulations based on device mismatches) methods. Hence, the choice of devices usually is a judicious selection to satisfy the flicker noise performance, matching, input loading, and the optimum voltage swing for the switches. The Load Network The load network usually utilizes highly linear passive elements (such that the cutoff frequency does not vary with voltage swing across them). The commonly used components include resistors, capacitances, and inductances. The key aspects of these load networks include: (a) headroom consumed, (b) matching between the components to minimize DC offset (static), (c) noise contribution, and (d) bandwidth. Often times these networks describe a filtering action to eliminate the out of band high-frequency components. The signal swing can get higher at the transmitter and the receiver, leading to significant nonlinearity and shift in the filter poles when the voltage dependence of such components is considerable (which is usually the case with high-density capacitors, used in a low pass filter at the receiver output). The passive elements in the load network can also bring significant parasitic capacitance (distributed capacitance from a resistor or bottom plate parasitic of a capacitor), leading to bandwidth limitation and gain degradation for the circuit. To achieve optimum performance of the transmit and receive mixers, the switching core might require a different bias current compared to the transconductor core. A bleeder network (auxiliary current source and sink) can be used to achieve this functionality. Buffers A buffer circuitry serves the following purposes: (a) isolation between different functional blocks, (b) transforming impedances through interfaces, (c) boosting or attenuating voltages and currents, and (d) interfacing with the test equipment for controlling the output impedance of the test chip. Two common examples of buffer topologies are: (a) differential pair, class A stages (frequently used in the signal paths to control common mode voltages) and boosting gain and (b) emitter (or source) follower, which is used to isolate sensitive blocks, and realize a low output impedance.

© 2006 by Taylor & Francis Group, LLC

9.8-1066

The Silicon Heterostructure Handbook

Buffers are usually single-ended circuits, and consume a certain bias current for its functionality. The capacitance at the output node (emitter or source) should be observed for stability considerations. The emitter follower also exhibits nonlinearity effects at large signal swings, which is dependent on the quiescent current of the stage. Bipolar stages would be preferred here, due to higher transconductance and hence lower output impedance (1/gm), lower parasitic capacitance, and absence of linearity problems due to body effects. The Bias Network Various types of bias circuits have been discussed in Refs. [1, 7]. These include constant current, constant gm, PTAT, constant Vdsat, etc. Bias circuits utilize large noise bypassing capacitors to reduce noise injection to sensitive RF circuits. It is also important that the output impedances of the bias circuit are carefully adjusted (high or low) depending on the application under consideration. Often times the bias circuits include several loops inside them and the loop gains must be carefully adjusted to prevent any oscillations at high frequency to any small part of the RF signal leaking to the bias network. Usually bias network uses many MOS transistors for current scaling purposes (as they do not exhibit a base current, eliminating the need of base current compensation techniques), and few bipolar devices to utilize their exponential characteristics.

Downconversion Mixers: Practical Example Let us focus on the practical implementations of two different variants of Gilbertcell mixers. The first one is a micromixer as shown in Figure 9.8.8, originally proposed by Gilbert [9], using a class AB-type input stage using quasi-symmetric bipolar transistors (Q5 and Q10). The transistors Q5, Q6, Q9, and Q10 form a translinear loop, and the product of collector currents of Q5 and Q10 is equal to that from Q6 and Q9. The switching core is similar to a traditional Gilbertcell mixer. The input impedance of the circuit is formed by the parallel combination of the impedances seen in the two paths formed by: (a) the combined series impedance of L3, diode connected Q10, and R3, and (b) the combined series impedance of R1, L2, and emitter resistance of Q5 at high frequencies, it is quite important to maintain the balance between the two paths. Micromixers exhibit several interesting properties. The first one is the large signal operation of the class — AB stage. Each of the transistors, Q5 and Q10 exhibit exponential nonlinearity, but the difference of the currents (which is significant for the switching operation) remains linear [9]. Thus, even if the individual stages exhibit nonlinearity, the differential operation remains linear, leading to very high linearity of such mixers at low bias currents. Another interesting property is their low input impedance due to high transconductance of bipolar transistors. The level of input impedance also varies with the input signal, leading to gain expansion at higher input signal swing as illustrated in Ref. [9]. The imbalance in the quasi-symmetric stages is adjusted by series combination of the passive elements. However, the diode-connected transistor at the input contributes significant noise, and thus micromixers remain attractive for a 50 V impedance standard, and high linearity, while contributing higher noise. Transistors Q12 and Q13 form emitter-coupled buffers to isolate the mixer from the testing equipment. Capacitors C2 and C7 have been used as noise bypassing capacitors to minimize noise contributions from the bias circuit. Transistors Q7 and Q8, along with pull-down resistors, are used as offset nulling elements to cancel static DC-offset effects. The second variant is a high impedance inductively degenerated Gilbertcell mixer (shown in Figure 9.8.8) used for a non-50-V-based architecture, and the similar descriptions would apply. The filter networks have been adjusted to accommodate the spectrum of interest, and the bipolar switching pair also requires low LO swing for the mixing operation. The operating frequency of the degeneration inductors should be less than: (a) self-resonating frequency (SRF) of the inductors (L1 and L2) and (b) resonating frequency of the network formed by the degeneration inductor (L1) and the base to emitter capacitance of the bipolar transistor (Q5) at the input stage.

© 2006 by Taylor & Francis Group, LLC

9.8-1067

Direct Conversion Architectures for SiGe Radios

VCC R5

R6

C6

C5

Q13 LO_M

Q12 Q1

Q2

Q3

Q4

IF+

Vbias LO_P

Q6

Q5 L2 L1

R8

R7

C 1 Z1

R1

Z2

L3

Q7

Q8

NullP

NullM

IFR9

Q9 RF_in

Q11

R2 Q10

C2

C7

L4 R 10

R3

R4

FIGURE 9.8.8 Circuit schematic of Gilbert-micromixer.

Signal Generation Path In the signal generation path, 2X frequency scheme has been adopted due to the considerations illustrated earlier. Two emitter coupled D flip-flop circuits have been utilized to realize the master– slave configuration needed for a static frequency divider, which operate at different clock edges. The scheme is shown in Figure 9.8.9. It starts with generation of differential signals from a single– ended input at 11.6 GHz, followed by the conversion to suitable voltage levels by appropriate buffers. The D flip-flop core generates quadrature signals, which in turn is amplified by the buffers to provide necessary LO swing to the mixer-switching core. The accuracy of such implementation is strongly dependent on the balance in the differential signal path, and any imbalance at the input of the divider network leads to the imbalance of the outputs in quadrature. Quasi-symmetric micromixer stage can be used here to achieve the desired matching for a 50 V interface.

9.8.7 The Integration: Interfaces and Layout Having illustrated the details about the operation of the building blocks, we now focus on the integration of these circuits. From a circuit interface point of view, the frequency divider, along with the buffers, should be interfaced with the LO terminal of the mixers and the chain should be optimized for the desired signal swing at the LO terminals needed for switching. A resistive load in the LO buffer might suffice in this regard due to the lower parasitic capacitances of the bipolar transistors. In the signal

© 2006 by Taylor & Francis Group, LLC

9.8-1068

The Silicon Heterostructure Handbook

IN

BALUN

+ −

BUFFER

+ −

D Q /D /Q clk DFF /clk

D Q /D /Q clk DFF /clk

I

FIGURE 9.8.9

Q

Block diagram of frequency divider (input at 11.6 GHz).

path, the voltage gain peak must be observed at the LNA-mixer interface, and the output impedance of the LNA should be combined with the input impedance of the mixer for area optimization. The integrated blocks should be designed for gain, noise, time-domain behavior, frequency response, linearity, and robustness to process and temperature variations, etc. While the circuit design considerations are somewhat straightforward and intuitive to explain, there exist tremendous challenges in the layout of the integrated blocks, which usually come from experience, and mistakes performed in the early test chips. For any high-frequency silicon design, the layout plays a very important role in the circuit performance due to the lossy nature of the substrate. There are many generic design guidelines toward mixed signal layout, but in this section we will consider only those, which are pertinent toward the chosen application. Since the circuit integrates both sensitive analog and digital building blocks, care should be taken to separate the two power supplies, thus minimizing the effect of any common mode noise from the power supplies. Also, the digital circuitry (frequency divider in this case) should be surrounded by deep trench and substrate contacts to minimize the noise generated by digital switching on the other analog circuit blocks of the receiver. Substrate contacts (also referred to as ‘‘taps’’) also help in isolating one circuit block from another and fully absorb the ground current in the substrate. Input trace to the LNA should be kept small to minimize any noise figure degradation. Usually, the top metal is used for interconnection and routing due to lower parasitic capacitances. Separation and orientation of inductors are important factors to minimize the flux coupling effect. Shielding of the input signals from the substrate is also very important. This is performed by having the input signals in topmost metal layer with the ground as stacked up M1 and M2 running together surrounding the chip and underneath the pads. Layout symmetry is extremely critical in receiver front ends, and any asymmetry in this regard destroys the fully differential nature of the front end, leading to unwanted components. I/Q imbalance associated with the mixers is very sensitive to the layout symmetry. Hence, in the layout, equal trace length must be respected from the RF input to the mixers. This is even more critical in the D flip-flop layout in terms of the clock distribution network. If the transistors are not identical and the layout traces are not equal, it results in deviation of the duty cycle from 50%, directly affecting the system performance. Sometimes shielding of the layout traces becomes very important. If the metal line connecting the base goes underneath the metal line connecting collector and vice versa, it gives rise to additional Miller capacitance, which might degrade the high-frequency performance. Hence, another metal layer can be used as shielding the two traces. DC bias lines may lead to unwanted inductive effect, which may affect the RF performance. Large DC blocking capacitors should be provided between the power supply and ground to minimize the effect of noise from the supply voltages (supply voltage variation) as well as to prevent any kind of ringing effect from DC supplies. The building blocks for both the receiver architectures were laid out for on wafer probing technique, and all the inputs at high frequency were assumed to be single ended to minimize the number of pads, leading to area compaction.

© 2006 by Taylor & Francis Group, LLC

9.8-1069

Direct Conversion Architectures for SiGe Radios

9.8.8 Characterization of Receiver Front End Any description of design and layout of integrated circuits is incomplete without its characterization and hardware debugging. A flow chart for the complete receiver testing is demonstrated in Figure 9.8.10. The measurement setups were performed exactly the way the front end was simulated. The micromixer and integrated receiver were characterized using S-parameters (by network analyzer), conversion gain (by spectrum analyzer), linearity (P1dB, IIP2, and IIP3) (by spectrum analyzer), I/Q imbalance (by oscilloscope), 50 V input match (by network analyzer), noise figure (by noise figure meter), and DCoffset (by multimeter). The developed circuits utilized wafer probing techniques for characterization purposes. During characterization, several subtle issues need to be addressed, such as: (a) The power up sequence should be properly respected. (b) The interfaces (such as differential to single-ended converter or transformer) used for noise characterization must utilize components that do not provide additional noise of their own. (c) The interfaces (differential to single-ended buffer) used for gain and linearity characterization should utilize components with very high linearity and high input impedance, so that they do not introduce nonlinearity and do not load the signal path. (d) Both time and frequency domain characterization should be performed to conclude about the functionality of the test-chip. (e) During the IM2 test, it must be ensured that no component from IM3 tree affects the IM2 component. (This happens when the receiver is tested with 5.8003, and 5.8004 GHz tones in the presence of 11.6 GHz tone, so that the IM2 ¼ 10 MHz coincides with IM5 tone.) (f) For any transceiver characterization, the basic test should include characterization with discrete tones to eliminate the necessity for highly sophisticated modulated signal generation equipments.

9.8.9 Fabricated Hardware and Results Following the above discussions, let us concentrate on the measurement results and learning from them. Figure 9.8.11 and Figure 9.8.12 show the microphotographs of the fabricated hardwares, with their performance descriptions provided in Table 9.8.3 and Table 9.8.4, respectively. From a direct conversion perspective, we would expect an extremely low value of DC offset, high value of IIP2, and lower value of

Unexpectedly High current? N

Y

DC test N

Shift to another die

More than 5 times?

Functionality test pass?

N

Y

Fail, short somewhere

Nonfunctional

Y

Gain

S-param

IIPn,P1dB

DC-offset

FIGURE 9.8.10 A complete flow chart for mixer or receiver testing.

© 2006 by Taylor & Francis Group, LLC

I/Q balance

NF

9.8-1070

The Silicon Heterostructure Handbook

Input LO signal (11.6 G) Frequency Divider

1.6 mm

1mm

IF-I

IF-Q

Mixer-Q

Mixer-I

Die photograph of fully monolithic micromixer IC.

Input LO signal (11.6 G) Frequency Divider

Mixer-Q

Mixer-I

IF-Q

IF-I

1.6 mm

1.3mm

FIGURE 9.8.11

Input RF signal (5.8G)

LNA

FIGURE 9.8.12

Input RF signal (5.8 G)

Die photograph of fully monolithic receiver IC.

TABLE 9.8.3 Performance Summary of Direct Conversion Micromixer IC (Two Micromixers with Frequency Divider) Performance Gain (dB) NF (dB) ICP (dBm) IIP3 (dBm) IIP2 (dBm) Amplitude imbalance (dB) Phase imbalance (deg) Power consumption (mW) Input match (dB) LO power (dBm) LO to RF leakage (dB) Dynamic DC offset (mV)

© 2006 by Taylor & Francis Group, LLC

Micromixer 9.23 19.5 3 þ6 þ32 0.25 2.4 32 16 12 58 <1.6

9.8-1071

Direct Conversion Architectures for SiGe Radios TABLE 9.8.4 Performance Summary of the Integrated Direct Conversion Receiver (LNA, I/Q Mixers, Frequency Divider) Performance Gain (dB) NF (dB) ICP (dBm) IIP3 (dBm) IIP2 (dBm) Amplitude imbalance (dB) Phase imbalance (deg) Power consumption (mW) Input match (dB) LO power (dBm) LO to RF leakage (dB) Dynamic DC offset (mV)

Integrated Receiver 20.2 7.1 15.5 3 þ31 0.9 5 64 15 10 78 <1

I/Q imbalance parameters. While the first one is satisfied due to careful layout and reverse isolation techniques, the IIP2 is affected by the choice of a single-ended stage of the transconductors for simplicity of interfaces. Imbalances are a function of several aspects (assuming perfect layout symmetry): (a) inherent circuit imbalance due to unequal parasitic components at high frequency, (b) imbalances of single to differential conversion stage, (c) generation of additional imbalance from circuits in the signal path with imbalanced inputs. Another cause of imbalance comes from unequal grounding effects in the I/Q paths, which can cause severe degradation as noted in Table 9.8.4.

9.8.10 Compensation and Corrections The above description of direct conversion radios addresses only its open loop operation. Although such description is quite simplistic to appreciate the fundamental operations from the circuits and device perspectives, it is far from complete from a system viewpoint. A major part of any transceiver system (and more so in case of direct conversion radio) is embedded in its baseband controls and signalprocessing functionalities, offset cancellation, and tuning circuitry for robustness of operation. Any transceiver continuously communicates with its baseband controller during its operation, sometimes in an adaptive way. This is essential for DC offset cancellation, and any offset corrections. Fundamentally, the resultant effect of all mismatches leads to unwanted offset voltage at the baseband, which is stored on a capacitor, and by controlling the polarity of the capacitors, the offset is subtracted from the incoming signal. There could be other examples, such as comparison of circuit performances with a reference design to detect the process corner and compensate the circuit elements according to the process variations. Even if the principles are quite simple, such methods enhance the robustness of any successful prototypes. Although compensation schemes could be fundamentally feasible at RF [10], robust implementations and parasitic considerations at high frequency hinder their applicability in successful prototypes. While static offset corrections are easier to perform (at the expense of more area on chip), and usually require a single time effort (usually at power up), dynamic corrections are extremely difficult to perform. For example, to compensate for dynamic DC offsets (whose levels can vary over several orders of magnitude depending on the surrounding environment), one can employ averaging techniques, or other second-order techniques, depending on the allowable time window in the communication protocol. It is inefficient to provide a filtering function, as it would degrade the SNR by considerable amount, consume area (large capacitors would be needed), and result in a long settling time.

© 2006 by Taylor & Francis Group, LLC

9.8-1072

9.8.11

The Silicon Heterostructure Handbook

Future of Direct Conversion Radios

Direct conversion architectures are viewed as potential candidates for the success of small form factor wireless transceivers. The implementation of direct conversion radios is a combination of architecture selection, communication technology, and semiconductor platform. Due to the presence of tremendous diversity in each of these selections, the direct conversion radios enjoy quite large variation in terms of their actual implementations. Future generation applications also require low voltage, low power implementations. An intuitive approach from circuit topologies indicates that to realize low power in the integrated radios, more functionality should be combined in a given bias current, leading to headroom problems if the blocks are stacked within the supply rails. Scaling of processes usually increases the fabrication cost (due to the need for sophisticated lithography techniques), but helps reduce the power consumption of the RF processing blocks by a significant amount. In case of CMOS scaling, the subthreshold region gets pushed further in high-frequency regime, thus potentially leading to low power operation. These approaches should be judiciously used to achieve a reasonable noise performance acceptable to wireless standards. To achieve high linearity in the front-end building blocks, number of voltage to current converter stages (V-I stages, e.g., transconductor) should be minimized, as this is a potential reason for nonlinearity in the front end. An interesting consideration is the use of inductive components. Use of inductor not only increases the overall chip dimension, but also results in unwanted coupling with other inductors present in the radio architecture, leading to careful floor plan considerations. Quality factor of inductor should be carefully adjusted to accommodate narrowband and broadband communication systems. Active inductor eliminates these issues, while posing significant limits to the dynamic range. Hence, for superior performance, inductors should be judiciously used and designed for minimizing lateral area (footprint), and simultaneously realizing the necessary quality factor for the specific operations. It should also be observed at this point that transceiver circuits pose many challenges to a circuit designer. Designing in a ‘‘CMOS-only’’ platform eliminates the possible use of any bipolar transistors except in the bias networks where substrate BJTs are used. At deep submicron regime, the gate leakage becomes quite significant, requiring similar techniques to base current compensation for bipolar transistors. Use of ‘‘bipolar-only’’ platform eliminates many considerations required for transistor scaling, etc. However, use of a high-speed platform such as ‘‘SiGe BiCMOS’’ leads to a much more variety of circuit topologies and the judicious use of MOS and bipolar transistors.

References 1. W.R. Maclaurin. Invention and Innovation in the Radio Industry. New York: The Macmillan Company, 1949. 2. I.A.W. Vance. Fully integrated radio paging receiver. Proceedings of IEE 129(1), 1982, 2–6. 3. T.H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998. 4. M. Shimozawa, T. Katsura, N. Suematsu, K. Itoh, Y. Isota, and O. Ishida. A passive-type even harmonic quadrature mixer using simple filter configuration for direct conversion receiver. IEEE International Microwave Symposium, June 2000, pp. 517–520. 5. IEEE Draft Supplement to IEEE Std 802.11, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-Speed Physical Layer in the 5 GHz Band, September 1999. 6. J. Laskar, B. Matinpour, and S. Chakraborty. Modern Receiver Front-Ends: Systems, Circuits and Integration. John Wiley Publisher, 2004. 7. P.E. Allen and D. Holdberg. CMOS Analog Circuit Design, 2nd ed. Oxford University Press, 2002. 8. P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer. Analysis and Design of Analog Integrated Circuits, 4th ed. John Wiley Publisher, 2001.

© 2006 by Taylor & Francis Group, LLC

Direct Conversion Architectures for SiGe Radios

9.8-1073

9. B. Gilbert. The MICROMIXER: a highly linear variant of Gilbert mixer using a bisymmetric class-AB input stage. IEEE J. Solid State Circuits 32(9), 1997, 1412–1423. 10. B. Matinpour, S. Chakraborty, and J. Laskar. Novel DC-offset cancellation techniques for even-harmonic direct conversion receiver. IEEE Trans. Microwave Theory Tech. 48(12), 2000, 2554–2559.

© 2006 by Taylor & Francis Group, LLC

9.9 RF MEMS Techniques in Si/SiGe 9.9.1 9.9.2 9.9.3

John Papapolymerou

Introduction............................................................. 9.9-1075 RF MEMS Switches................................................. 9.9-1076 Application Circuits ................................................ 9.9-1080 Reconfigurable Low-Loss Resonators and Bandpass Filters . Reconfigurable Bandstop Filter . Reconfigurable Matching Networks (Tuners)

Georgia Institute of Technology

9.9.1 Introduction During the last four decades microwave and millimeter-wave systems have been used in a wide variety of commercial, medical, and military applications due to their advantages over other bands of the electromagnetic spectrum (unlike infrared and optical wavelengths they have the ability to permeate fog, dust, and smoke) and the lack of lower frequencies for new services. Some of these applications include satellite-to-earth communication systems, plane and missile navigation, early warning radars, earth remote sensing, short-haul line-of-sight transmission links for personal communication links (PCNs), wireless cable, wireless radio local area networks (LANs), mobile broadband systems, automotive anticollision radars, and hyperthermia for cancer treatment [1]. Until the early 1980s most of the microwave/mm-wave components were built with waveguide technology (rectangular or cylindrical) that offers low-loss and high quality factors at the price of increased size, weight, fabrication cost, and complexity [2]. In addition, the bandwidth of those systems was limited by the bandwidth of the employed waveguides. With the maturity of integrated circuit techniques and solid-state device technology the electromagnetics research community started focusing its attention on monolithic microwave/mm-wave integrated circuits (MMICs) that dominate today’s communication systems. MMICs offer the advantages of small size and weight, low cost, increased reproducibility and reliability, broadband operation, and easy integration of active devices [2]. All of the previously mentioned advantages are essential for today’s cost-driven commercial and military microwave industry that seeks to achieve high-performance flexible systems with maximum density and speed. The requirements for high density, high speed, and high operating frequencies along with the advancements in materials science technology, semiconductor processing techniques, and solid-state devices have provided the stimulus for system-on-a-chip solutions. With these solutions, both active and passive components are monolithically integrated on a semiconductor substrate (Si/SiGe) for miniature lightweight and highly reliable microwave systems [3]. However, design and fabrication of entire microwave/mm-wave systems on a single chip pose new problems and challenges. Limitations in the performance of the different components relative to the waveguide ones, co-existence with other circuits (e.g., digital), power consumption and handling, signal switching, and packaging are a few significant samples. To address these issues, researchers in the last 10 9.9-1075 © 2006 by Taylor & Francis Group, LLC

9.9-1076

The Silicon Heterostructure Handbook

years have implemented solutions based on micromachining and microelectromechanical systems (MEMS) techniques, widely used in the sensor and transducer areas since the 1960s [4]. Micromachining techniques generally refer to the selective removal of the silicon substrate material with a variety of methods (chemical, plasma, laser) to create new and interesting structures. The term also encloses the techniques where one builds relatively thick (more than 10 mm) structures on top of the substrate (LIGA, SU-8). MEMS generally relates to the development of electromechanical structures on the surface of the silicon substrate. All MEMS devices provide for a certain amount of mechanical flexibility in the physical construction of the circuit, in addition to the traditional electronic functions. The combination of micromachined and MEMS structures with microwave/mm-wave systems not only creates new interesting challenges, but also provides the opportunity for using revolutionary ideas and concepts to address next generation system requirements. The latter are dictated by the demand to create small chips that are able to sense, think, act, and communicate with the outside world. Monolithic integration, therefore, of Si (or SiGe) circuits, advanced MEMS devices, micromachined analog components, and digital CMOS-based processing circuits into one wafer is the next leap beyond the current state-of-the-art used in the system-on-a-chip approach [3]. In this chapter we will review briefly the fundamentals of RF MEMS switches and provide some application circuits on silicon substrates. Realizing that there exists a variety of MEMS structures that have been developed on silicon substrates, we will focus only on RF switches due to the extensive growth and research interest in their technology, as well as their dominant role in signal routing and distribution. Taking into account the extraordinary growth of the MEMS field up to this point and its market potential for the next 5–10 years, it is anticipated that MEMS technology will enable a new class of microwave/mm-wave components and subsystems and revolutionize the way people think about integrated systems on a chip.

9.9.2 RF MEMS Switches RF MEMS switches can be developed by using surface micromachining, where thin-film layers (usually polysilicon, various metals, SiO2, Si3N4) are deposited on the semiconductor surface (usually Si) and machined in a way that they can be released from the substrate and thus be able to move and flex in order to provide the desired function. In some cases, the free-standing structures are anchored at one or more positions, and in other cases, they are free to rotate around a pin joint [5]. The electromotive force used to ‘‘move’’ or rotate the above structures on the wafer surface is typically electrostatic attraction, although magnetic, thermal, and piezoelectric actuation mechanisms have been reported [6, 7]. RF MEMS switch technology has emerged during the last 10 years as an alternative to traditional solid-state switching technology. RF MEMS switches typically consist of a moving metallic membrane that can ‘‘make’’ or ‘‘break’’ contact when it is actuated by a DC control voltage. The main advantages of RF MEMS switches are low insertion loss up to W-band (0.3 dB), low intermodulation distortion (IIP3 > 65 dBm), negligible power consumption ( a few mW), high isolation up to W-band, cutoff frequencies between 20 and 80 THz and low fabrication cost [8]. Switching times are in the range of 1–300 ms, while power handling capabilities are on the order of a few watts [8]. Several companies and universities have developed a wide variety of ohmic and capacitive switches on Si, GaAs, and quartz substrates with excellent performance [9–16]. A schematic of a typical cantilever and air-bridge type of MEMS switch is shown in Figure 9.9.1a and 1b, respectively. More specifically, Figure 9.9.1a depicts a cantilever ohmic contact switch, while Figure 9.9.1b depicts an air-bridge capacitive switch. The switch typically consists of a movable membrane suspended a few microns above the silicon substrate. With the application of an electrostatic voltage between the membrane and a pull-down electrode an electrostatic force is applied to the membrane, and as a result the membrane starts moving closer to the substrate. When the voltage and, thus, the electrostatic force go beyond a certain threshold value the membrane is pulled completely down. Typically the membrane is pulled down at height values around one third the original distance from the substrate.

© 2006 by Taylor & Francis Group, LLC

RF MEMS Techniques in Si/SiGe

FIGURE 9.9.1.

9.9-1077

Schematic of (a) cantilever ohmic switch and (b) capacitive MEMS switch.

At Georgia Tech we have developed both ohmic and capacitive MEMS switches [17, 18]. Photos of cantilever type switches are shown in Figure 9.9.2. The main difference between the two switches is that in the case of the ohmic switch the contact is metal-to-metal, whereas in the capacitive case there is a thin layer of dielectric between the two metals providing a capacitive short. Capacitive switches typically have lower loss at higher frequencies, whereas ohmic switches have smaller loss at lower frequencies. Both switches are activated using an electrostatic force that results from the application of a DC bias voltage. A bias electrode is typically used to apply the DC voltage separately from the RF signal. Typical fabrication steps for a MEMS switch include: (a) formation of the bottom electrode layer by depositing 2000 A˚ of gold with e-beam evaporation and patterning of the layer; (b) deposition of a thin layer of silicon nitride (typically 1000–2000 A˚) by PECVD techniques and patterning by reactive ion etching (RIE) to cover the bottom pull-down electrode area and the RF contact area for the capacitive switch only; (c) patterning of the first metal layer and electroplating to a thickness of 1–3 mm to provide the contact point between the membrane and this layer; (d) patterning of 2-mm-thick photoresist layer (‘‘sacrificial’’ layer) that will be used to form the movable membrane; (e) electroplating of the membrane areas to a total thickness of 1–3 mm depending on the switch design; (f) removal (release) of the sacrificial layer with solvents and drying of the switches with a critical point drier (step f can be replaced by RIE of the sacrificial layer). The performance of the ohmic and capacitive switch can be seen in Figure 9.9.3 and Figure 9.9.4, respectively. From Figure 9.9.3 one can observe that when actuated the ohmic switch has a loss of 0.3 dB at 20 GHz, while when unactuated it yields an isolation of 17 dB at 20 GHz. The switch actuation voltage is varied between 20 and 40 V. The equivalent switch model consists of a resistor (RS) in series with an inductor for the ON state, and a capacitor (COFF) for the OFF state. The modeled values are RS ¼ 0.5 V and COFF ¼ 15 fF. The actuation time of the ohmic switch was measured to be around 5–10 ms. From Figure 9.9.4 it can be seen that the capacitive switch yields a loss of 0.15 dB at 18 GHz in the ON state and an isolation of 12 dB at 18 GHz in the OFF state. The equivalent switch model is a series combination of an inductor, capacitor, and a resistor with values of L ¼ 140 pH, R ¼ 0.5 V, CON ¼ 900 fF and COFF ¼ 20 fF. The actuation voltage of the capacitive switch was 30–60 V. Capacitive switches typically have higher power handling capability than ohmic switches with values ranging between 2 and 5 W of a CW RF signal applied between switch actuation (‘‘cold switching’’). Reliability and low-cost packaging are probably the two most important remaining challenges for full commercialization of the RF MEMS switch technology. Several companies and universities have been

© 2006 by Taylor & Francis Group, LLC

9.9-1078

The Silicon Heterostructure Handbook

(a)

Memb

rane

Transm ission line Botto

m ele

ctrod

e

(b)

FIGURE 9.9.2.

Photos of cantilever: (a) ohmic switch and (b) capacitive MEMS switch.

focusing during the last 4 to 5 years on addressing these two issues that are interdependent. New material technology, new switch designs, as well as new biasing algorithms have been implemented to improve switch lifetime and package performance. The mechanisms that lead to switch failure (e.g. stiction) are typically different in ohmic vs. capacitive switches. For example, microwelding can reduce the lifetime of ohmic switches, while dielectric charging can reduce it for capacitive switches. Debris in the contact area is a major consideration for both switching types, as well as environmental conditions such as increased levels of relative humidity. It is generally agreed in the research community that an appropriate package is absolutely necessary for increased switch reliability and, eventually, mass

© 2006 by Taylor & Francis Group, LLC

9.9-1079

RF MEMS Techniques in Si/SiGe

0 −5 −0.1

S-Parameters (dB)

−10 −15

−0.2

−20 −0.3

−25 −30

−0.4

−35 −40

S11 -- meas S11 -- model

−45 −50

0

5

10

15

S21 -- meas S11 -- model

20

25

30

−0.5

35

Frequency (GHz)

(a)

−5

0

S-Parameters (dB)

−0.6 40

−0.1

−10

−0.2

−15

−0.3

−20

−0.4

−25

−0.5

−30

−0.6

−35

−0.7 −0.8 −0.9 −1

0

(b)

5

10

15

−40

S21 -- meas S21 -- model

S11 -- meas S11 -- model

20

25

30

−45 35

−50 40

Frequency (GHz)

FIGURE 9.9.3 Measured and simulated S-parameters for an ohmic switch in the: (a) ON state and (b) OFF state. (From G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. With permission.)

production and commercialization. Self-actuation under high RF power levels can also lead to reduced lifetimes for both types. At the time this chapter was written typical wafer capped lifetimes of ohmic switches for low RF power levels exceeded 20 billion cycles, while several devices with more than 100 billion cycles were also reported. Ohmic switches with 2 W of RF input power had achieved a lifetime of 2.5 billion cycles [19]. Capacitive switches had statistically demonstrated lifetimes higher than 35 billion cycles, while several devices had achieved more than 70 billion cycles [19]. Near hermetic or hermetic wafer-level packaging is also considered to be the most promising low-cost solution for packaging of RF MEMS switches with increased reliability and low loss. RF and DC interconnects that provide low-loss signal connections in and out of the capped switch are also under investigation. It is expected that within a short period of time RF MEMS switch reliability will statistically exceed values of 90 billion cycles for relatively low RF power levels (up to 2 W).

© 2006 by Taylor & Francis Group, LLC

9.9-1080

The Silicon Heterostructure Handbook

−5

−0.1

−10

−0.2

−15

−0.3 −0.4

−25 −0.5

−30

−0.6

−35

S11 -- meas S11 -- model

−40 −45

4

6

8

S21 -- meas S21 -- model

10

12

−0.7

14

16

−0.8 18

Frequency (GHz)

(a) 0

−12

−0.1

−14

−0.2

−16 −18

−0.4 −20

−0.5

−22

−0.6 S21 -- meas S21 -- model

−0.7 −0.8

S21 (dB)

−0.3 S11 (dB)

S21 (dB)

S11 (dB)

−20

4

6

8

(b)

10

12

S11 -- meas S11 -- model 14

16

−24 −26 18

Frequency (GHz)

FIGURE 9.9.4 Measured and simulated S-parameters for a capacitive switch in the: (a) ON state and (b) OFF state. (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

9.9.3 Application Circuits In this section we will present some examples of microwave circuits utilizing RF MEMS switches to achieve performance characteristics that are impossible with other microwave switching devices. It should be noted that there is a variety of RF MEMS based microwave circuits that cannot be covered in the extent of one chapter only.

Reconfigurable Low-Loss Resonators and Bandpass Filters There is an increased interest in low loss, low power, small size tunable microwave filters for receiver applications to replace filter banks that traditionally take more space and use high-Q bulky structures.

© 2006 by Taylor & Francis Group, LLC

9.9-1081

RF MEMS Techniques in Si/SiGe

Reconfigurable filters based on MEMS switches offer a viable alternative to filters using pin diodes or varactors that typically suffer from high losses. This section presents resonators and filters using ohmic contact switches combined with low loss digital capacitive loads to achieve reconfigurability. Their implementation in wide tuning range, low loss band pass filters is demonstrated, showing the interest of this technique [18]. A capacitance quality factor Q is defined as Q¼

1 2p f R C

(9:7:1)

where f is the operation frequency, C the capacitance value, and R the series resistance of the capacitor. Figure 9.9.5a presents an electrical model of a digital capacitive load to ground, with a DC contact switch and its biasing network. Biasing is coupled to the capacitive load through the actuation pad capacitance Cact. This capacitance is strongly increased when the switch is turned on. Consequently in the switch ON and OFF states, the biasing network has an important influence. Thus, for microstrip planar capacitors losses are not only due to the switch resistance Ron but also to the biasing network. It can be proven that this effect can be highly reduced with the integration of high resistances Rbias in the biasing network. Indeed these resistances permit to isolate the RF device from its biasing network at microwave frequencies, while the electrostatic actuation of the switch is not affected by the presence of the resistance. In the proposed designs, a short open-ended microstrip transmission line is used as the high-Q capacitance to ground. In this configuration, the capacitance value depends on the line dimensions (length and width) and substrate properties (permittivity and thickness). Using this topology, one can obtain very high Q, reproducible capacitors. By careful selection of various capacitive values one can design a capacitor bank that can be switched between different states to achieve reconfiguration in terms of resonant frequency. Using this topology, different digital capacitive loads have been developed, following the implementation presented in Figure 9.9.5a. These loads are fabricated on a 400-mm-thick high-resistivity silicon substrate and very high value resistors (0.8–1 MV) are integrated in the biasing network. Since a thick low loss metal (>3.5 mm thick gold) is being used for the switch and the load metallization, the switch is the main source of loss in this design. Each DC contact switch used here has two contacts resulting in 0.25 V series resistance per switch. Because of the parallel combination of several MEMS switches, these losses can be highly reduced. But, on the other hand, the total isolation is also degraded: a trade-off between ON state losses and OFF state isolation therefore exists. Hence, only two or three MEMS switches are associated to each digital load. Table 9.9.1 shows the computed quality factor for the digital loads implemented in this work. At 10 GHz, they exhibit a high Q value that relies on the capacitance value and the number of switches used. One can note that loads 3 and 4 use a reduced number of switches for a practical implementation in the circuits shown in this section. The resonator developed has been designed by loading a planar resonator with two digital capacitive loads presented in Figure 9.9.5b and Table 9.9.1. The unloaded resonator is fabricated using a half wavelength microstrip line (3400 mm long and 400 mm wide). It presents a simulated quality factor of 105 at 15.6 GHz and uses an S-shaped line to facilitate the load integration. Each load decreases the resonator frequency, when it is turned on. With two capacitive loads, four combinations are possible and four different frequencies are obtained. A photo of the fabricated resonator along with measured results are shown in Figure 9.9.6. A summary of full-wave simulations and measured results can be found in Table 9.9.2. As seen, an unloaded quality factor of around 77 is achieved for all four different resonant frequencies. Using the resonator presented previously, we have designed a bandpass filter based on a two-pole topology. Indeed, a two-pole filter is an easy way to demonstrate the digital capacitive load potential for filtering devices. Usually a two-pole filter frequency response depends on the coupling between each resonator and also on the coupling between the excitation lines and the resonators. These parameters determine the filter prototype. The main challenge with the tunable filter is to control the coupling

© 2006 by Taylor & Francis Group, LLC

9.9-1082

The Silicon Heterostructure Handbook

RF input

Switch

CLoad

Cact Coff Off state Rbias Ron

Vbias

Off state

(a)

Biasing line

Resistor

Switch Capacitive load 500 µm

23−Aug−03

(b)

FIGURE 9.9.5 (a) Electrical equivalent circuit of a digital capacitive load to ground with its biasing network and (b) SEM picture of a MEMS digital capacitive load and its biasing network fabricated on a high-resistivity silicon substrate. (From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.)

TABLE 9.9.1

Computed Performance of the Fabricated Capacitive Loads.

Capacitive Load Length (mm) Width (mM) Capacitance to ground (fF) @ 10GHz Number of switches used Quality factor (@ 10 GHz)

1

2

3

4

320 400 135 2 625

500 750 260 3 465

500 750 260 2 330

900 1300 570 3 210

Source: From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.

© 2006 by Taylor & Francis Group, LLC

9.9-1083

RF MEMS Techniques in Si/SiGe

FIGURE 9.9.6 (a) SEM photo of reconfigurable resonator with MEMS switches on silicon substrate and (b) measured performance of the resonator. (From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.)

TABLE 9.9.2 Simulated and Measured Results for Resonator with 43% Tuning Range. Resonator state Capacitance load turned on Simulated frequency (GHz) Measured frequency (GHz) Simulated quality factor Measured quality factor

1

2

3

4

None 15.18 15.03 102 79

#3 13.13 13. 07 101 77

#4 11.19 11.13 90 80

#3 & #4 9.69 9.7 89 75

Source: From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.

© 2006 by Taylor & Francis Group, LLC

9.9-1084

The Silicon Heterostructure Handbook

FIGURE 9.9.7 (a) SEM photo of two-pole MEMS filter with 44% tuning range and (b) measured performance of the filter. (From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.)

variation when the frequency shifts in order to get the desired filter response. For large frequency shifts, the effect of not controlling the coupling is generally a degradation of the filter loss and the filter fractional bandwidth. In our case, the two microstrip resonators are coupled to each other using their magnetic fields while the capacitive loads maintain a correct input–output coupling. The two-pole filter topology chosen is tolerant to frequency shifting, and proves the concept of microstrip MEMS tunable filters using MEMS DC switches. However, a design methodology similar to the one described in Ref. [20] should be applied for multipole and more complex structures. A photo of the fabricated filter on silicon along with measured results is shown in Figure 9.9.7. The filter exhibits a low level of insertion loss (less

© 2006 by Taylor & Francis Group, LLC

9.9-1085

RF MEMS Techniques in Si/SiGe TABLE 9.9.3 Summary of Measured Results for Two-Pole Filter with 44% Tuning Range Filter state Capacitance load turned on Measured frequency (GHz) Measured bandwidth (MHz) Fractional bandwidth % Insertion losses (dB)

1

2

3

4

None 14.95 870 5.8 2.6

#1 13.11 700 5.3 2.8

#2 11.05 600 5.4 2.6

All 9.55 520 5.4 3.2

Source: From A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. With permission.

than 3.2 dB) within the filter bandwidth. The return loss level is also very high (>15 dB), showing good filter matching for the four combinations. The full-wave simulations (method of moments), including metal losses and the biasing network influence, are in very good agreement with the measurements. For the measurements, a TRL calibration procedure has been used to de-embed the CPW to microstrip transition that excites the filters. The filter results are summarized in Table 9.9.3. The filter can be reconfigured from 9 to 15 GHz with a very small amount of loss. Of paramount importance is the DC biasing network as it can considerably increase losses due to RF leakage.

Reconfigurable Bandstop Filter One type of tunable filter that is very important in RF receivers for communication and radar systems is the bandstop filter. This section presents a monolithic, reconfigurable, microstrip-based bandstop filter utilizing RF MEMS capacitive switches. The goal of this work is to develop a four-state or ‘‘2-bit’’ tunable bandstop filter from 8 to 15 GHz [17]. More specifically, the filter is designed to have a notch at 8, 10, 13 and 15 GHz, respectively, that can be selected electronically by activating the appropriate MEMS switches. One useful application of this filter is to provide a good image rejection if the microwave receiver experiences signal interferences. The cantilever beam capacitive MEMS switch with electrostatic actuation was chosen for the filter design based on its advantages as follows: first, comparing with ohmic contact switch, it can typically handle more RF power; second, it is easier to design and fabricate for microstrip circuits over the air-bridge capacitive switch. The bandstop filter using quarter-wavelength open-circuited resonators is one type of configuration commonly used for this type of filtering [21, 22]. The electrical length of the shunt stubs and the distance between the shunt stubs is lg/4 at the center or design frequency. The four filters that resonate at 8, 10, 13, and 15 GHz were first designed as if a bandstop filter with a single resonant frequency were desired. The characteristic impedances of the filter stubs were calculated at each resonant frequency as given in the following eqution: Zon ¼

4Z0 pgn D

(9:9:2)

where n ¼ 1, 2, 3, . . . Zon is the characteristic impedance of each stub, Z0 is the characteristic impedance of the feed line equal to 50 V, gn is the low-pass prototype value, which can be found in Refs. [21, 22] and D is the fractional bandwidth. In order to develop one bandstop filter that can resonate at four different frequencies with some tunable devices, such as MEMS switches, these four individual filters needed to be combined together. To achieve this, the 50 V transmission line width at 10 GHz was chosen as the feedline for the tunable filter since it is around the center of the full frequency range. The difference between the stub lengths was first replaced with lumped components using the following equations:

© 2006 by Taylor & Francis Group, LLC

9.9-1086

The Silicon Heterostructure Handbook

1 ¼ Zon cot (bl) jˆC

(9:9:3)

jˆL ¼ Zon cot (bl)

(9:9:4)

where C is the capacitance, L is the inductance, Zon is the characteristic impedance of the stub, b is the propagation constant, and l is the length of the microstrip stub. Since the electrical lengths of the microstrip stubs are different at different resonant frequencies, the corresponding lumped element could be a capacitor (C) or an inductor (L). The equivalent values of the lumped elements at 8, 10, 13, and 15 GHz are: 1.12 nH, 45 fF, 264.5 fF, and 356 fF, respectively. These lumped components were then broken into two parallel subcircuits. In each subcircuit, there are two lumped components in series, which are a two-state capacitance with a fixed larger capacitance or larger inductance as shown in Figure 9.9.8. The two-state variable capacitance is used as the circuit model value of the MEMS switch, which is very small ( 20–30 fF) at the off-state and very large (0.9–1 pF) at the on-state; the other lumped component will be an appropriate fixed capacitance or inductance. By choosing the MEMS switch to be on- or off-state, the total reactance can be easily determined as it should be equal to the reactance before the lumped components were broken into two subcircuits. When the MEMS switch is at the off-state with a very small capacitance, its value will be the dominant one to determine the resonant frequency; but when the switch is at the on-state, its capacitance is relatively large, thus the lumped component which connects to the MEMS switch will be the dominant component to determine the resonant frequency. In other words, by selecting MEMS switches on or off, different resonant frequencies will be selected. To make the circuit monolithic, the fixed lumped components were replaced by microstrip lines with radial stubs. Based on the equivalent capacitances/inductances calculated above and the schematic diagram of Figure 9.9.8, the required capacitances and inductances were re-calculated and the resulting values are: C1 ¼ C2 ¼ 20=900 f F, C3 ¼ 356 f F, and L4 ¼ 1:12 nH. The tunable filter with lumped elements has now been designed, and the resonant frequency is determined by selecting the different combinations of capacitors C1 and C2. The S-parameters of the fabricated filters were measured with an Agilent 8510 network analyzer and a Cascade probe station. A multiline Thru-Reflect-line (TRL) calibration technique was used to de-embed the probe pad-to-circuit transitions and move the reference planes to the locations shown in Figure 9.9.9. A summary of the measured results and a comparison with the same filter design utilizing perfect open and short circuits instead of MEMS switches are shown in Table 9.9.4. For the bandstop filter with

C/Z Z1⬘

C1 C

C

Z2⬘

C2

C C3

L4

FIGURE 9.9.8 Schematic of the capacitor of each path breaking into two subcircuits. (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.9-1087

RF MEMS Techniques in Si/SiGe

Reference plane

Reference plane

CPW RF probe pad to microstrip transition

Microstrip to CPW RF probe transition

(a)

TRL calibration lines

Discrete MEMS switches

Tunable bandstop filter (b)

FIGURE 9.9.9 (a) Layout of reconfigurable bandstop filter and (b) fabricated filters on silicon. (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

the MEMS switches, the measured rejection at the notch frequencies was 23, 27, 21, and 20 dB and the 10 dB bandwidth was 9.7%, 6.5%, 7%, and 5% for 8, 10, 13, and 15 GHz, respectively, while the insertion loss at the passband was measured to be around 0.5 dB. The measured results were also compared with simulated results (Figure 9.9.10 to Figure 9.9.13) where the MEMS switches were modeled as 28 fF at off-state, and 1000 fF at the on-state. The simulation was done in two main steps: (1) the layout simulation was done in Agilent Momentum, but in the simulation, the MEMS switches were removed and six pairs of internal ports were inserted into the gaps; (2) the simulated results from Momentum were imported into the Agilent ADS schematic simulation and the six capacitors with variable values were then connected between these six different pairs of internal ports. As shown in Figure 9.9.10, Figure 9.9.11, and Figure 9.9.13 the measurements and the simulations agree very well at 8, 10, and 15 GHz. Figure 9.9.12 shows that the bandwidths of the measured and the simulated results at 13 GHz are different. This is caused by the fact that when all the MEMS switches are at the on state, there is RF leakage through the DC bias lines. It should be noted

© 2006 by Taylor & Francis Group, LLC

9.9-1088

The Silicon Heterostructure Handbook TABLE 9.9.4 Center Frequency and Bandwidth Comparison between the Measurement with MEMS Switches and Perfect Open-/Short Circuits.

Off–off/open–open

Off–on/open–short

On–off/short–open

On–on/short–short

Center Freq/Rejection (GHz/dB) Bandwidth (GHz)a Percentage BW (%)a Center Freq/Rejection (GHz/dB) Bandwidth (GHz)a Percentage BW (%)a Center Freq/Rejection (GHz/dB) Bandwidth (GHz)a Percentage BW (%)a Center Freq/Rejection (GHz/dB) Bandwidth (GHz)a Percentage BW (%)a

MEMS switches

Perfect open or short

10.16/-27 0.42 5 8.62/23 0.84 9.7 15.13/21 0.97 6.5 13.275/20 1.05 7

11.5/-23 0.34 3 9/40 0.7 7.8 16.015/22 0.89 5.6 13.42/20 0.72 5.4

a The bandwidth was calculated as the 10 dB bandwidth. Source: From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.

8 GHz 0 −5

S-Parameters (dB)

−10 −15 −20 −25 −30 −35

S21-- sim S21 -- meas

−40 −45

4

6

8

10

12

14

16

18

Frequency (GHz)

FIGURE 9.9.10 Measurement vs simulation results for the off–on state of the filter with MEMS switches (8 GHz response). (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

here that integrated resistors that provide a perfect open at the switch location were not used in this implementation. As a result of the RF leakage or loss, the larger bandwidth is more pronounced for the measurements of Figure 9.9.12 when compared to the other measurements. For Figure 9.9.11, where all the switches are at the off-state, an ideal agreement can be observed between simulated and measured data as the DC bias lines are not loading the circuit.

© 2006 by Taylor & Francis Group, LLC

9.9-1089

RF MEMS Techniques in Si/SiGe

10 GHz 0 −5

S-Parameters (dB)

−10 −15 −20 −25 −30 −35

S21 -- sim S21 -- meas

−40 −45

4

6

8

10 12 Frequency (GHz)

14

16

18

FIGURE 9.9.11 Measurement vs simulation results for the off–off state of the filter with MEMS switches (10 GHz response). (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

13 GHz 0 −5

S-Parameters (dB)

−10 −15 −20 −25 −30 −35

S21 -- sim S21 -- meas

−40 −45

4

6

8

10 12 Frequency (GHz)

14

16

18

FIGURE 9.9.12 Measurement vs simulation results for the on–on state of the filter with MEMS switches (13 GHz response). (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.9-1090

The Silicon Heterostructure Handbook

15 GHz 0 −5 S-Parameters (dB)

−10 −15 −20 −25 −30 −35

S21 -- sim S21 -- meas

−40 −45

4

6

8

10 12 Frequency (GHz)

14

16

18

FIGURE 9.9.13 Measurement vs simulation results for the on–off state of the filter with MEMS switches (15 GHz response). (From G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. With permission.)

Reconfigurable Matching Networks (Tuners) Matching networks are fundamental circuit components in RF front ends since they minimize reflection losses and maximize power transfer from one stage to the other. They are widely used in antenna and amplifier designs, as well as other components. This section presents a reconfigurable, planar double-stub tuner that utilizes capacitive RF MEMS switches and achieves the widest tuning range from 10 to 20 GHz with the highest VSWR [23]. The basic design procedure for a double-stub tuner, outlined in Ref. [23], was used to determine the susceptances of each stub and the lengths between them to match the desired range of loads. The range of loads to be matched was arbitrarily chosen to be 20 to 80 V real part and 150 to þ150 V imaginary. It was assumed that the desired match was to 50 V. The first step in the design process is to determine the distance of the first stub to the load. It was assumed that this distance was zero. The second step is to choose the distance d between the two stubs. This distance is important since it limits the range of loads that can be matched. A large distance will decrease the range of loads that can be matched while a small distance may be impractical to fabricate. For this tuner, the distance d was chosen to be relatively small (0.1 l) to maximize the range of matchable loads while sacrificing the frequency sensitivity of the circuit. Once the distance between the stubs has been chosen, the susceptances of each stub that will match the range of loads to 50 V need to be determined. The equations for the susceptance of the two stubs can be found in Ref. [21]. Once the susceptance values are calculated, the stub capacitances can be evaluated at the design frequency (C ¼ B/2pfd). The next step in the design is the implementation of the variable susceptance stubs. Knowing that RF MEMS switches would be used to make the circuit reconfigurable a ‘‘digital’’ approach was pursued, where different capacitances were realized by a combination of a switch and a fixed capacitor. For each stub, four such combinations were used (Figure 9.9.14), resulting in a ‘‘4bit 4bit’’ double-stub tuner. The more the bits used, the wider the range of load impedances that can be matched. If fewer bits are used, the more simplistic the circuit is to design and use and the less area it occupies. For our

© 2006 by Taylor & Francis Group, LLC

9.9-1091

RF MEMS Techniques in Si/SiGe

Csw

Csw

Csw

Csw

Cfixed,1

Cfixed,2

Cfixed,3

Cfixed,4

FIGURE 9.9.14 Schematic of ‘‘four-bit’’ reconfigurable tuner that consists of fixed capacitors and MEMS switches. (From J. Papapolymerou, K. Lange, C. Goldsmith, A. Malczewski, and J. Kleber, Reconfigurable double stub tuners using MEMS switches for intelligent RF front ends, IEEE Trans. Microwave Theory Techn., 51(1), 271–278, 2003. With permission.)

FIGURE 9.9.15 Photo of fabricated RF MEMS tuners. (From J. Papapolymerou, K. Lange, C. Goldsmith, A. Malczewski, and J. Kleber, Reconfigurable double stub tuners using MEMS switches for intelligent RF front ends, IEEE Trans. Microwave Theory Techn., 51(1), 271–278, 2003. With permission.)

implementation the design frequency was chosen at 20 GHz. The RF MEMS switches were capacitive switches, with an ‘‘off ’’ capacitance of 35 fF and an ‘‘on’’ capacitance of 3 pF [9]. The fixed capacitors were realized as open stubs and were fabricated on high-resistivity silicon along with the switches. The remainder of the transmission lines was fabricated on low-loss alumina and ribbon bonds were used to connect the two substrates. A photo of the fabricated tuner is shown in Figure 9.9.15. The tuner size was approximately 18 mm11 mm. The tuner response was simulated using HFSS and Agilent ADS. The former tool was used to extract the response of the switch–stub combination that was incorporated in ADS for the calculation of the entire circuit response. Measured and simulated results for the ‘‘4bit4bit’’ tuner at 20 and 15 GHz are shown in Figure 9.9.16 and Figure 9.9.17, respectively. As can be seen in Figure 9.9.16, the tuner can match at 20 GHz load impedances with 1.5 V< Re{ZL}< 109 V and 107 V < Im{ZL}< 48 V. In addition, the measured and simulated results agree very well. This circuit by far provides the largest range of matchable load impedances equivalent to three quadrants of the Smith chart. Furthermore, measurements show that a

© 2006 by Taylor & Francis Group, LLC

9.9-1092

The Silicon Heterostructure Handbook

FIGURE 9.9.16 Simulated (O) and measured (X) range of matched load impedances for the 20 GHz-optimized, 4-bit by 4-bit tuner at 20 GHz. (From J. Papapolymerou, K. Lange, C. Goldsmith, A. Malczewski, and J. Kleber, Reconfigurable double stub tuners using MEMS switches for intelligent RF front ends, IEEE Trans. Microwave Theory Techn., 51(1), 271–278, 2003. With permission.)

FIGURE 9.9.17 Simulated (O) and measured (X) range of matched load impedances for the 20 GHz-optimized, 4-bit by 4-bit tuner at 15 GHz. (From J. Papapolymerou, K. Lange, C. Goldsmith, A. Malczewski, and J. Kleber, Reconfigurable double stub tuners using MEMS switches for intelligent RF front ends, IEEE Trans. Microwave Theory Techn., 51(1), 271–278, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

RF MEMS Techniques in Si/SiGe

9.9-1093

maximum VSWR of 99 was achieved at the fourth quadrant and 15.7 at the second and third quadrants of the Smith chart. This is attributed to the low loss nature of the MEMS components. Thus, the MEMS tuner performance is superior compared to conventional tuners using FET devices that typically achieve VSWRs less than 20. At 15 GHz, this circuit can match load impedances with 1 V< Re{ZL}<155 V and 68 V< Im{ZL}< 79 V, equivalent to three quadrants of the Smith chart. There are some minor discrepancies between the measured and simulated data that arise mostly from the variation of ribbon bond lengths and placements. In addition, the spacing between the alumina and the silicon substrates that were bonded together was not modeled in the HP-ADS simulations. Also, it should be noted that while the simulated and measured data agree fairly well at the design frequency, the two data sets agreed less at other frequencies. To overcome some of the limitations and challenges of the hybrid MEMS tuner, such as shifting of the load range due to wire bonds and the relatively large size, a fully monolithic microstrip tuner has also been developed [24]. The latter is the first monolithic, microstrip-type reconfigurable X-band tuner on a silicon substrate using ohmic contact MEMS switches for maximizing the efficiency of X-band class-E power amplifiers [25]. Unlike the hybrid tuner, the monolithic one is designed to achieve a specific tuning matching range for the amplifier and not to maximize the overall load tuning range. In this mode of operation, the active device is driven hard into saturation, and small device-to-device and parasitic variations have a large effect on efficiency. A load-pull technique combined with measurements on around 30 hybrid class-E 10 GHz power amplifiers determines the optimal output impedances range required of the output tuner. The resulting output impedances for class-E operation are obtained to be ZEMAX ¼ (34.1 þ j39.3) V and ZEMIN ¼ (22:7 þ j26:2) V, while the nominal impedance is ZENOM ¼ (27.3 þ j31.5) V. The microstrip-based double-stub tuner with the MEMS switches was designed to provide the impedance tuning range required above. The design procedure is as follows: first of all, a doublestub tuner was designed with the fixed stub length to provide the nominal impedance required by the power amplifier, which is 34þj37 V (this value takes into account the interconnects between the Si tuner and the amplifier circuit), and then each stub was split into three paths and the microstrip transmission lines were replaced with radial stubs as shown in Figure 9.9.18. Each radial stub is connected with the main RF line through an ohmic contact MEMS switch; this connection will enable the selection of different radial stubs depending on the different combinations (on/off states selection) of the MEMS switches. The dimensions of the radial stubs were chosen so that by selecting the different on and off states of the MEMS switches, they will provide the sufficient tuning range. In order to properly actuate the MEMS switches, the DC bias lines were designed to provide the DC path while blocking the RF path to keep the RF signal from leaking; the high resistive material indium tin oxide (ITO) was used to form the DC bias lines. The average sheet resistance measured was 10 KV/square and the DC bias lines were designed as 100 squares. A photo of the fabricated monolithic tuners is shown in Figure 9.9.19. Tuner measurements were performed with an Agilent 8510C network analyzer using GGB Picoprobes. The switches were activated using Cascade DC probes and one probe card. The actuation voltage of the MEMS switches was found to be around 60 V. The simulated and the measured results for the total of 64 states are shown in Figure 9.9.20 and Figure 9.9.21, respectively. From Figure 9.9.20 and Figure 9.9.21, it can be seen that the simulated and the measured results have a good agreement. In Figure 9.9.20, marker 1 (33.4þj33.8 V) is the required nominal impedance for the output of the power amplifier. Correspondingly, in Figure 9.9.21, marker 1 shows the measured result with exactly the same combinations of the MEMS switches. The marker reading in this case is 27.7 þ20.6 V. The real and the imaginary parts of the impedance from the simulation and measurement in this case are slightly different. The reason for this might be from the simulation and measurement error, and slight shift of the reference plane during the measurement. Overall, the

© 2006 by Taylor & Francis Group, LLC

9.9-1094

The Silicon Heterostructure Handbook

5

4

321

SW2 SW3

SW1

Output

Input

SW6 SW5

SW4

11

10

9

876

FIGURE 9.9.18 Layout of monolithic tuner with DC bias lines shown. (From G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. With permission.)

FIGURE 9.9.19 Photo of fabricated monolithic tuners. (From G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.9-1095

RF MEMS Techniques in Si/SiGe

S (1,1)

m4

m4 freq-10.00\GHz m4 = 0.418 / 94.006 swp_index = 38.000000 impedance = 33.476 + j33.803

Freq (10.00GHz to 10.00Ghz)

FIGURE 9.9.20 Simulated impedance tuning range with the same measured 64 different MEMS switch on/off states. (From G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. With permission.)

S (1,1)

m1

m4 freq-10.00\GHz m1 = 0.378 / 122.485 swp_index = 38.000000 impedance = 27.670 + j20.585

Freq (10.00GHz to 10.00Ghz)

FIGURE 9.9.21 Measured impedance tuning range for the 64 different MEMS switch on/off states. (From G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.9-1096

The Silicon Heterostructure Handbook

monolithic tuner can match loads that are within the desired impedance range of a class-E amplifier. The measured maximum VSWR is 38 and the tuner size is 6 mm7 mm. A max VSWR of 83 has also been achieved with the same design that had higher per square resistance for the DC bias lines. The size reduction is at least threefold compared to the hybrid tuner that was designed around 20 GHz. The insertion loss of the tuner was also calculated based on the measurements, and the average loss was found to be around 1 dB.

References 1. H.H. Meinel, Commercial applications of millimeter waves: history, present status and future trends, IEEE Trans. Microwave Theory Techn., 43(7), 1639–1653, 1995. 2. I. Papapolymerou, MMIC passive and active structures, PhD dissertation, The University of Michigan, Ann Arbor, 1999. 3. K.J. Herrick, J.G. Yook, and L.P.B. Katehi, Microtechnology in the development of threedimensional circuits, IEEE Trans. Microwave Theory Techn., 46(11), 1832–1844, 1998. 4. E.R. Brown, RF MEMS switches for reconfigurable integrated circuits, IEEE Trans. Microwave Theory Techn., 46(11), 1868–1880, 1998. 5. K. Petersen, Silicon as a mechanical material, Proc. IEEE, 70(5), 420–457, 1982. 6. J.H. Comtois, Structures and techniques for implementing and packaging complex, large scale microelectromechanical systems using foundry fabrication, PhD dissertation, Air Force Institute of Technology, 1996. 7. J.J. Sniegowski and E.J. Garcia, Microfabricated actuators and their application to optics, Proc. SPIE — Int. Soc. Opt. Eng. (USA), Vol. 2383, San Jose, CA, February 7–9, 1995, pp. 46–64. 8. G. M. Rebeiz, RF MEMS: Theory, Design and Technology, Wiley Interscience, 2003. 9. C. Goldsmith, Z. Yao, S. Eshelman, and D. Denniston, Performance of low-loss RF MEMS capacitive switches, IEEE Microwave Guided Wave Lett., 8(8), 269–271, 1998. 10. S. Pacheco, C. Nguyen, and L. Katehi, Micromechanical electrostatic K-band switches, IEEE MTT-S International Microwave Symposium Digest, pp. 1569–1572, Baltimore, MD, June 1998. 11. J. Muldavin and G. Rebeiz, Inline capacitive and DC-contact MEMS shunt switches, IEEE Microwave Wireless Components Lett., 11(8), 334–336, 2001. 12. R. Mihailovich, M. Kim, J. Hacker, E. Sovero, J. Studer, J. Higgins, and J. DeNatale, MEM relay for reconfigurable RF circuits, IEEE Microwave Wireless Components Lett., 11(2), 53–55, 2001. 13. D. Hyman and M. Mehregany, Contact physics of gold microcontacts for MEMS switches, IEEE Transactions Comp. Packaging Technol., 22(3), 357–364, 1999. 14. G. Wang, S. Barstow, A. Jeyakumar, J. Papapolymerou, and C. Henderson, Low cost RF MEMS switches using photodefinable mixed oxide dielectrics, 2003 IEEE International Microwave Symposium Digest, Vol. 3, pp. 1633–1636, Philadelphia, PA, June 2003. 15. S.C. Chen and M. Feng, Low actuation voltage RF MEMS switches with signal frequencies from 0.25 GHz to 40 GHz, Proceedings IEEE International Electronics Device Meeting, pp. 689–692, December 1999. 16. G. Ponchak, N. Varaljay, and J. Papapolymerou, Ka-band, RF MEMS switches on CMOS grade silicon with a polyimide interface layer, 2003 European Microwave Conference, Vol. III, pp. 971–974, October 2003. 17. G. Zheng and J. Papapolymerou, Monolithic reconfigurable bandstop filter using RF MEMS switches, Int. J. RF Microwave Computer Aided Engineering (special issue on RF Applications of MEMS and Micromachining), 14(4), 373–382, 2004. 18. A. Pothier, J.-C. Orlianges, E. Zheng, C. Champeaux, A. Catherinot, D. Cros, P. Blondy, and J. Papapolymerou, High Tuning Range Bandpass Filters using MEMS DC Contact Switches, IEEE Trans. Microwave Theory Techn., 53(1), 354–360, 2005. 19. Reliability testing and reliability enhancement of RF MEMS switches, 2004 IEEE International Microwave Symposium Workshop Notes, Fort Worth, TX, June 2004.

© 2006 by Taylor & Francis Group, LLC

RF MEMS Techniques in Si/SiGe

9.9-1097

20. G. Torregrosa-Penalva, G. Lopez-Risueno, J.I. Alonso, A simple method to design wide band electronically tunable comb-line filters, IEEE Trans. Microwave Theory Techn., 50(1), 2002. 21. David M. Pozar, Microwave Engineering, 2nd edition, John Wiley & Sons, Inc., New York. 22. G. Matthaei, L. Young, and E. M. T Jones, Microwave Filters, Impedance Matching Networks, and Coupling Structures, Artech House, New Jersey, 1980. 23. J. Papapolymerou, K. Lange, C. Goldsmith, A. Malczewski, and J. Kleber, Reconfigurable double stub tuners using MEMS switches for intelligent RF front ends, IEEE Trans. Microwave Theory Techn., 51(1), 271–278, 2003. 24. G. Zheng, P. Kirby, S. Pajic, A. Pothier, P. Blondy, J. Papapolymerou, and Z. Popovic, A monolithic reconfigurable tuner with ohmic contact MEMS switches for efficiency optimization of X-band power amplifiers, 2004 IEEE Topical Meeting on Si Monolithic Integrated Circuits in RF Systems, pp. 159–162, Atlanta, GA, September 2004. 25. S. Pajic and Z. Popovic, An efficient 16-element X-band spatial combiner of switched-mode power amplifiers, IEEE Trans. Microwave Theory Techn., 51(73), 2003.

© 2006 by Taylor & Francis Group, LLC

9.10 Wideband Antennas on Silicon 9.10.1

Microstrip Antennas on Cavity-Etched Silicon Substrate .................................................. 9.10-1100

9.10.2

Microstrip Antennas on Hole-Perforated Silicon Substrate .................................................. 9.10-1108 Tapered Slot Antennas on Micromachined Silicon Substrates [17] ........................................ 9.10-1109 Surface Micromachined Monopoles for W-Band Applications [21] ................................. 9.10-1111

SiO2 . Polyimide . SiO2 versus Polyimide

Manos M. Tentzeris and Rong Lin Li Georgia Institute of Technology

9.10.3 9.10.4

In modern sensor and communication systems, there is an increasing demand for the monolithic integration of the antennas with the RF front-ends to avoid external transmission line connections or sophisticated packaging, thus reducing manufacturing cost and improving system performances [1, 2]. Especially, microstrip antennas are used in a broad range of applications from communication systems (WLAN, radars, telemetry, and navigation) to biomedical systems, primarily due to their simplicity, conformability, and low manufacturing cost. They are commonly utilized in wireless applications due to the fact that can be planar or conformal, can be fed in numerous conﬁgurations and also are compact and suitable for antenna array designs. In general, they can be used in applications requiring highperformance compact low-cost planar antennas. With the recent development of microwave- and millimeter-wave integrated circuits and the trend to incorporate all microwave devices on a single chip for low-cost and high density, there is a need to fabricate microstrip antennas in a monolithic fashion with the rest of the circuitry on semiconducting materials such as silicon, GaAs, or InP. One of the main limitations of these microstrip antennas is the excitation of surface waves in the silicon substrate, especially in cases where the bandwidth and the radiation efﬁciency requirements demand large values of the substrate thickness, resulting in compromised efﬁciency, reduced bandwidth, and degradation of the radiation pattern [4, 5]. Furthermore, in monolithic designs the feedlines share in most cases the same interface with the antennas and lead into parasitic radiation, which deforms the antennas’ pattern and increases crosstalk. The suitability of high-resistivity silicon as a substrate material for microwave- and millimeter-wave circuits has been demonstrated in numerous examples [6, 7]. However, direct use of silicon substrates with patch antennas results in strong surface-wave modes and reduced bandwidth. The ideal solution requires the capability to integrate the antenna on electrically thick low-dielectric constant regions while the circuitry remains on the high-dielectric constant regions in the same substrate. This requirement can be satisﬁed by selecting the substrate that offers optimum component performance; unfortunately this leads to hybrid integration schemes and high development cost. As the frequency increases, moreover, this approach becomes increasingly difﬁcult and costs are prohibitively high [8]. In addition, the lowresistivity Si wafer used for traditional microwave circuit is troublesome due to the high loss. Several methods have been recently used to overcome this problem, including drilling a well-designed cavity 9.10-1099 © 2006 by Taylor & Francis Group, LLC

9.10-1100

The Silicon Heterostructure Handbook

underneath the antenna [8–14], and etching few holes underneath the antenna to disturb the formation of substrate modes [15–17]. In this review, we ﬁrst focus on two categories of micromachined antennas (i.e., micromachined cavity and micromachined holes’ perforation) and their design methodologies. Micromachining of silicon is a process where the semiconductor substrate is mechanically altered, either by removing parts of the substrate (bulk micromachining) or by adding layers and structures to the top of the wafer (surface micromachining). Finally, we will introduce the development of surface micromachined monopoles for W-Band applications.

9.10.1

Microstrip Antennas on Cavity-Etched Silicon Substrate

When a microstrip patch antenna is fabricated on a cavity-etched silicon substrate (as shown in Figure 9.10.1), the resonant frequency of the antenna with length and width L and W is determined by [8, 18] fr ¼

c pﬃﬃﬃﬃﬃﬃﬃﬃ 2(L þ 2DL) «reff

(9:10:1)

where «

«reff ¼ «cavity

DL ¼ 0:412t

fringe L þ 2DL «cavity

!

L þ 2DL

(«reff þ 0:3)(W =t þ 0:264) («reff 0:258)(W =t þ 0:8)

(9:10:2)

(9:10:3)

with «fringe «air þ («sub «air )xair ¼ «cavity «air þ («sub «air )xfringe

(9:10:4)

«air «sub «air þ («sub «air )xfringe

(9:10:5)

«cavity ¼

The thickness parameters xair and xfringe are ratio of the air to full substrate thickness in the mixed and fringing ﬁeld regions, respectively [8]. A plot of the theoretical and measured effective dielectric constant versus the air gap thickness for silicon substrate is shown in Figure 9.10.2, where an effective dielectric constant of approximately 2.2 is achieved for a mixed air–silicon ratio of 1:1 using the capacitor model (Equation (9.10.2) with DL ¼ 0) and 3:1 ratio for the capacitor model with DL extension length (Equation (9.10.2) with DL calculated from Equation (9.10.3)). The dimensions for the micromachined patch that was used to produce the results of Figure 9.10.2 are listed in Table 9.10.1. The ﬁnite difference time-domain (FDTD) calculation was based on a three-dimensional (3D) full-wave scheme that yields the return loss of the micromachined antenna and the effective permittivity of a 1:1 air–silicon substrate for a range of frequencies. Once the resonant frequency is determined from the return loss, the effective permittivity of interest is found. Regarding the measured (micromachined) data point, the resonant frequency of the fabricated antenna was measured and was used to extract the dielectric constant of the substrate of a patch having the same dimensions as the measured one. Two antennas were fabricated on silicon, with resonant frequencies in the K-band and air–substrate thickness ratios of 1:1. In the silicon micromachined patch antenna, the conductor has been electroplated to a metal thickness of approximately 3.2 mm and the substrate is chemically etched (EDP

© 2006 by Taylor & Francis Group, LLC

9.10-1101

Wideband Antennas on Silicon

C

b

W

L

a

t

tair

Efective dielectric constant, eeff

FIGURE 9.10.1 Microstrip patch antenna on a cavity-etched silicon substrate. (From J Papapolymerou, RF Drayton, and LPB Katehi. IEEE Trans. Antennas Propagat. 46:275–283, 1998. With permission. Copyright IEEE.)

12 Capacitor model (CAP) CAP with ∆L exension FDTD Theory Micromachined

10 8 6 4 2 0 0

20 40 60 80 Air gap thickness, Xair (%)

100

FIGURE 9.10.2 Effective dielectric constant versus air gap thickness (%) for the silicon-based micromachined patch using the cavity and FDTD model compared to the measured response. (From J Papapolymerou, RF Drayton, and LPB Katehi. IEEE Trans. Antennas Propagat. 46:275–283, 1998. With permission. Copyright IEEE.)

TABLE 9.10.1 Patch Regular Micromachined

Design Parameters for the Antennas on Silicon Substrates t (mm)

tair (mm)

L (mm)

w (mm)

a (mm)

b (mm)

c (mm)

0.355 0.355

0 0.165

2.019 3.616

4.08 3.445

0 3.616

0 8.108

0 0

Source: From J Papapolymerou, RF Drayton, and LPB Katehi. Micromachined patch antennas. IEEE Trans. Antennas Propagat. 46:275–283, 1998.) With permission. Copyright IEEE.

© 2006 by Taylor & Francis Group, LLC

9.10-1102

The Silicon Heterostructure Handbook

Return loss (dB)

0

−10

−20 Regular Micromachined −30 10

15

20 Frequency (GHz)

25

30

FIGURE 9.10.3 Measured return loss for the regular and micromachined patch antenna printed on a full thicknesss substrate and substrate with mixed air–silicon thickness ratio (1:1), respectively. (From J Papapolymerou, RF Drayton, and LPB Katehi. IEEE Trans. Antennas Propagat. 46:275–283, 1998. With permission. Copyright IEEE.)

process) in a single-etch step underneath the antenna. Return loss measurements are shown in Figure 9.10.3 where the 10 dB bandwidth increases from 2.9% for the regular antenna to 5% for the micromachined patch. The fabrication process of a micromachined patch antenna is shown in Figure 9.10.4 [11] for an antenna used for satellite communications (around 16 GHz). The ﬁrst 254 mm-thick high-resistivity silicon wafer is used to support the microstrip patch. The lift-off process shown in Figure 9.10.4(a) is employed to produce a required patch and feed line patterns on top of the silicon wafer. A second silicon

Silicon Photoresist Aluminum

Silicon wafer Deposit photoresist Photolithography Deposit metal film Lift-off photoresist (a)

Silicon wafer Etched wafer (b)

FIGURE 9.10.4. Fabrication of cavity-etched patch antenna: (a) lift off process and (b) etching process. (From M Zheng, Q Chen, PS Hall, and VF Fusco. Electron. Lett. 34:3–4, 1998. With permission. Copyright IEE.)

© 2006 by Taylor & Francis Group, LLC

9.10-1103

Wideband Antennas on Silicon

wafer of the same thickness is used to produce a 0.254 mm 12 mm 12 mm cavity as shown in Figure 9.10.4(b) by using an abrasive etching method. Finally, two wafers and a polished brass carrier are assembled together using silver epoxy to form a complete air-ﬁlled-cavity-backed microstrip patch antenna, which is depicted in Figure 9.10.5 with tair/t ¼ 50% (H1 ¼ H2). The measured and calculated results for input return loss of the antenna are presented in Figure 9.10.6 and demonstrate good agreement. The calculation was carried out using a 3D FEM model. It is found that the effective dielectric constant of the patch antenna is only 2.8, compared to 9.7 of a noncavitybacked antenna of the same thickness. The drastic reduction in the permittivity of the patch antenna by partially etching out the silicon material underneath the patch, obviously results in the increase of the antenna’s bandwidth and efﬁciency. The 10 dB impedance bandwidth of the antenna is 12.5%, which is much larger than the typical value of 2% and 4.4% for conventional microstrip patch antennas of dielectric constants of 10 and 2.2 with the same substrate thickness-to-wavelength ratio [18]. The measured radiation patterns are plotted in Figure 9.10.7, where the patterns in the E-plane are not symmetrical because of the disturbance from the feed line. The gain of the antenna is measured to be 6.6 dBi.

patch HRSi

H1

LRSi H2

ground metal (a)

LO

(b)

FIGURE 9.10.5 Cavity-backed microstrip patch antenna (H1 ¼ H2 ¼ 254 mm, L ¼ 5 mm, W ¼ 7 mm, L1 ¼ 2.95 mm. L0 ¼ 1.3 mm; (a) side view, (b) top view). (From M Zheng, Q Chen, PS Hall, and VF Fusco. Electron. Lett. 34:3–4, 1998. With permission. Copyright IEE.)

© 2006 by Taylor & Francis Group, LLC

9.10-1104

The Silicon Heterostructure Handbook

0

Input loss, dB

−5 −10 −15 −20 −25 10

12

14 16 Frequency (GHz)

18

20

FIGURE 9.10.6 Input return of the cavity-etched patch antenna () measured, (- -) calculated. (From M Zheng, Q Chen, PS Hall, and VF Fusco. Electron. Lett. 34:3–4, 1998. With permission. Copyright IEE.)

00

−90

−10 −20 −30 −40 −50

180 (a)

00

90

−90

−10 −20 −30 −40 −50

90

180 (b)

FIGURE 9.10.7 Measured radiation patterns of the cavity-etched patch antenna: (a) E-plane and (b) H-plane. E-plane, H-plane (), and cross-polarization patterns (- -) are shown. (From M Zheng, Q Chen, PS Hall, and VF Fusco. Electron. Lett. 34:3–4, 1998. With permission. Copyright IEE.)

In Ref. [12], a micromachining approach that allows etching a shallow cavity directly under the area of microstrip antenna, and then ﬁlls the cavity with lower permittivity materials, such as silicon dioxide or polyimide, is presented. A metal layer is deposited between the low permittivity material and the silicon underneath. The thin layer of low permittivity substrate can reduce the loss and the excitation of surface waves. The tradeoff is that the very small thickness of this layer makes the realization of practical bandwidths for this type of microstrip antennas very difﬁcult. Finding the most efﬁcient thickness, in terms of fabrication feasibility and bandwidth of the antenna, is the most critical problem of these designs. One important factor of the antenna performance is the choice of the optimum feeding options. Microstrip antennas are usually fed with either probe, coplanar waveguide (CPW), or microstrip feed. The radiating structures of Ref. [12] use a coplanar CPW feed to the microstrip antenna [13], in order to minimize the interaction of the coplanar mode ﬁelds with the lossy Si substrate. The latter will prevent loss of power in the feeding network. In addition, CPW interfaces very well with the pad-probes of most measurement equipment. To integrate the microstrip antenna in the CPW feeding network, a simple, low-loss, compact and via-less CPW to microstrip transition was designed and optimized for operation around 30 GHz [14]. The material used was a silicon substrate with relative permittivity («r) of 11.8,

© 2006 by Taylor & Francis Group, LLC

9.10-1105

Wideband Antennas on Silicon

conductivity (s) of 100 S/m, and thickness of 500 mm at 30 GHz. With these high values of thickness and conductivity, it was assumed that the substrate provided a virtual ground, below which the E-ﬁeld would be less than 5% of the E-ﬁeld on the antenna. The attenuation constant (a) for such a material can be calculated with vﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 0sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1ﬃ u 00 2 u 0 « um« @ 1þ 1A a ¼ vt 2 «0

(9:10:6)

where «0 ¼ «r«0 and «00 ¼ s/v, giving a value of a ¼ 3120.41 Np/m for the above silicon substrate. Using this attenuation constant in the formula [19] jE(z)j ¼ jE0 jeaz

(9:10:7)

the electric ﬁeld left at the bottom of the silicon is approximately 21.01% of the electric ﬁeld on top. This means that there is still energy left at the bottom of the substrate, which excites signiﬁcant substrate modes and could potentially distract the radiation of the antenna, unless a metal plane is added to the bottom. To alleviate this problem, a shallow cavity was etched directly under the area of microstrip antenna, and then ﬁlled with lower permittivity materials, such as silicon dioxide or polyimide. A metal layer was added at the horizontal planar interface between the low permittivity material and the silicon underneath. Figure 9.10.8 shows the top view of this antenna. Figure 9.10.9 and Figure 9.10.10 are the side views of the antenna with SiO2 and polyimide underneath, respectively. The entire structure, including CPW, microstrip line, and the patch antenna are on top of the cavity. The CPW and microstrip line are designed to match a 50 V characteristic impedence. The thickness of the cavity depends on the material used to ﬁll the cavity. The dimension of the antenna is 3300 mm 2600 mm. To match the 50 V input impedence, the antenna is fed at 600 mm from the edge. The width of the microstrip transmission line is 452 mm and the distance from the edge of the antenna to the end of the cavity is 350 mm on the side and 511.3 mm in the front. The SiO2 has «r ¼ 3.5. The cavity depth with SiO2 ﬁlling has been simulated at 50, 100, and 200 mm. The bottom of the cavity is metalized with gold. The polyimide has «r ¼ 3.2. During the fabrication, the polyimide is applied using a spin coating method that results in an extra layer of polyimide over the cavity and the silicon. The depths of the cavity that are simulated are equal to 50, 100, and 200 mm.

Antenna

Silicon

SiO2 Feed line Silicon

Side view of antenna

FIGURE 9.10.9 Side view of antenna with SiO2. Cavity

Polyimide Silicon

FIGURE 9.10.8 Top view of the antenna.

© 2006 by Taylor & Francis Group, LLC

FIGURE 9.10.10

Side view of antenna with polyimide.

9.10-1106

The Silicon Heterostructure Handbook

TABLE 9.10.2 SiO2 Filled Cavity for Different SiO2 Thickness Values SiO2 Thickness (mm)

Resonant Frequency (GHz)

Bandwidth (%)

Directivity (dBi)

28.946 29.165 29.430

1.4 1.7 2.4

6.736 6.766 6.809

50 100 200

Source: From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.

0 S11 (dB)

−5 −10 −15 −20 −25 −30 20

25

30 35 Frequency (GHz) 50 µm 100 µm 200 µm

40

FIGURE 9.10.11 Simulated S11 for SiO2 cavity. (From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.)

SiO2 Table 9.10.2 summarizes the results and Figure 9.10.11 is a graphical presentation of the S11 values versus frequency for the three different simulated thicknesses of SiO2 layers, 50, 100, and 200 mm. All three designs show a resonant frequency around 30 GHz. The curves for 50 and 100 mm are almost identical with only 0.3% difference of the bandwidth. The 200 mm design shows more bandwidth, but the maximum return loss is slightly higher than for the thinner layers. The 200 mm design is the only one having a bandwidth close to the commonly required value of 3%. However, fabrication of the 200 mm design is difﬁcult, since growing such large oxidation thicknesses on silicon is very time-consuming and technologically challenging.

Polyimide The polyimide structure is also simulated with three different thicknesses: 50, 100, and 200 mm. Table 9.10.3 and Figure 9.10.12 summarize the results. At 30.975 GHz, the 200 mm design has a return loss of 16.5 dB, and a bandwidth of 2.7% (83.63 MHz). As a conclusion, the simulation results show that with 200 mm of polyimide, both the resonant frequency and the bandwidth are in a desirable range. TABLE 9.10.3 Polyimide Filled Cavity for Different Polythickness Values Polymide Thickness (mm) 50 100 200

Resonant Frequency (GHz)

Bandwidth (%)

Directivity (dBi)

30.318 29.474 30.975

1.3 1.3 2.7

6.616 7.223 6.809

Source: From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.

© 2006 by Taylor & Francis Group, LLC

9.10-1107

S11 (dB)

Wideband Antennas on Silicon

0 −5 −10 −15 −20 −25 −30 20

25

30 35 Frequency (GHz)

50 µm

100 µm

40

200 µm

FIGURE 9.10.12 Simulated S11 for polyimide cavity. (From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.)

SiO2 versus Polyimide

S11 (dB)

Figure 9.10.13 is a plot of S11 for the structures with 200 mm of material, both SiO2 and polyimide. It can3 be easily observed that there is a shift of the resonant frequency for the two substrates. This is due to the fact that the polyimide has an extra layer on top of silicon that creates a cavity of a noncanonical shape. In addition, this introduces a dielectric interface of Z-shape in comparison to the dielectric interface of L-shape for SiO2 (Figure 9.10.9 and Figure 9.10.10), leading to a slightly lower value of effective dielectric constant and thus to a higher resonant frequency for the same physical dimensions. Both simulations demonstrate a bandwidth of approximately around 2.5%. SiO2 shows better return loss at the resonant frequency, though it is more difﬁcult to fabricate. On the contrary, polyimide-ﬁlled geometry is more feasible in terms of fabrication. In order to decrease the difference between the resonant frequencies of the SiO2 and polyimide antennas, the size of the latter antenna was changed from 3300 mm 2600 mm to 3300 mm 2650 mm. The result shows a maximum return loss of 29.09 dB at 30.022 GHz, and the bandwidth is 2.7%. Figure 9.10.14 shows the comparison from this optimized dimension to the SiO2 result. The central bandwidth is offset by 600 MHz, which is 2%. The difference can be attributed to different dielectric constants and numerical errors due to the simulation tools. As a conclusion, preliminary designs of planar antenna structures on top of low-resistivity silicon with a layer of low-permittivity material in between were presented and evaluated in terms of return loss and bandwidth. The materials used are SiO2 and polyimide and simulation results show that to achieve bandwidths above 2.5%, it is necessary to have at least 200 mm of either material. Polyimide is easier to fabricate, but SiO2 could provide a better performance in terms of the return loss.

0 −5 −10 −15 −20 −25 −30 20

25

30 35 Frequency (GHz)

Polyimide

40

SiO2

FIGURE 9.10.13 Simulated S11 for the same thickness (200 mm) of SiO2 and polyimide. (From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.10-1108

The Silicon Heterostructure Handbook

0 −5 S11 (dB)

−10 −15 −20 −25 −30

20

25

30 35 Frequency (GHz) Polyimide* SiO2

40

FIGURE 9.10.14 Simulated S11 for same thickness (200 mm) of SiO2 revised polyimide. (From EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824. With permission.)

9.10.2

Microstrip Antennas on Hole-Perforated Silicon Substrate

Another commonly used technique to alleviate the problem of surface waves in Si-based antenna structures is the perforation of the silicon substrate with holes (Figure 9.10.15) [15, 16], leading to an effective dielectric constant given by «reff ¼

«rhole þ 1 «rhole 1 12t 1=2 þ 1þ 2 2 W

(9:10:8)

The hole-perforated dielectric constant «rhole was derived using «rhole ¼ «sub (1 x) þ x

(9:10:9)

10 cm

Many holes per λd (>10) low effective er

7 cm

cm 7

10

cm

L

W

RF connector

Substrate (e r = 10.8)

Ground plane

Microstrip antenna εr

εr synth

FIGURE 9.10.15 Microstrip patch antenna on a hole-perforated substrate. (From GP Gauthier, A Courtay, and GM Rebeiz. IEEE Trans. Antennas Propagat. 45:1310–1314, 1997. With permission. Copyright IEEE.)

© 2006 by Taylor & Francis Group, LLC

9.10-1109

Wideband Antennas on Silicon

x¼

pdh2 2dc2

(9:10:10)

where x is the proportion of volume removed, dh the hole diameter, and dc the center-to-center spacing in a triangular lattice grid.

9.10.3 Tapered Slot Antennas on Micromachined Silicon Substrates [17] The tapered slot antenna (TSA) is a wideband antenna desirable for millimeter-wave applications, such as phased arrays and focal-plane imaging systems, due to its compact design and endﬁre radiation pattern. The main limitation of the TSA comes from its sensitivity to the thickness and dielectric constant of the supporting substrate. An effective thickness, which represents the electrical thickness of pﬃﬃﬃﬃ the substrate, has been deﬁned as teff ¼ t( «r 1). An accepted range for good operation of a TSA has been experimentally determined by Yngvesson et al. [20] to be 0.005 < teff /l0 < 0.03. For substrate thickness above the upper bound, unwanted substrate modes degrade the performance of the TSA, while antennas on thinner substrates suffer from decreased directivity. The upper bound on the effective thickness teff/l0 < 0.03 requires mechanically thin substrates for millimeter-wave applications, especially for high dielectric constant substrate such as silicon, GaAs, or InP. In fact, to operate at 90 GHz, the maximum allowable thickness on silicon is 42 mm. This results in a mechanically fragile antenna and therefore is not practical in large arrays. Another approach is to micromachine holes in the substrate, resulting in a lower effective dielectric constant. In this section, the hole-micromachining technique at 90 to 100 GHz (W-band) on silicon substrate for the TSA applications is introduced. The W-band TSA is designed and fabricated on 100-mm-thick silicon substrate («r ¼ 11.7, r > 10,000 V cm) with (a) 300-mm and (b) 600-mm wide holes etched from the backside (as shown in Figure 9.10.16). A 100-mm thick silicon wafer with 4000 A˚ of oxide on both sides is ﬁrst mounted on a 500-mm thick mechanical wafer, and the holes are patterned using a 500-mm thick photoresist ﬁlm. The oxide is then etched in the holes using buffered HF and the silicon is exposed to the deep silicon RIE etcher, The etch rate is 4.5 to 5 mm/min, resulting in a total etch time of 20 min for 90- to 100-mm deep holes. The sidewall etch proﬁle is 848 steep and the width of the etched hole increases by 10 to 15 mm. The wafer is then ﬂipped and mounted again on a 500-mm thick mechanical wafer. The antenna metal layer is patterned using a lift-off process has a thickness of 5000 A˚. The 100-mm wafer is released from the mechanical support wafer and attached at its edge to a glass microslide. The holes’ pattern shown in Figure 9.10.16 results in «eff ¼ 5.1 and teff / l0 ¼ 0.037 at 90 GHz as per Equation (9.10.11) and Equation (9.10.12) by choosing the spacing between the holes W is such that D/W ¼ 0.625, where D is the diameter of the holes, which is chosen to be D ¼ 300 and 600 mm, respectively. The effective dielectric constant does not depend on the hole diameter but only on the ratio D/W

«reff ¼ «r

! p D 2 p D 2 þ 1 ¼ 5:1 2 W 2 W

(9:10:11)

for micromachined silicon wafers, and pﬃﬃﬃﬃﬃﬃﬃ teff =l0 ¼ t ð «eff 1Þ=l0 ¼ 0:037

(9:10:12)

for micromachined silicon at 90 GHz. For reference, the TSA on silicon without any etched holes, «eff ¼ «r ¼ 11.7 gives teff / l0 ¼ 0.075 at 90 GHz. The effective thickness is well above the upper limit of the Yngvesson condition and should

© 2006 by Taylor & Francis Group, LLC

9.10-1110

The Silicon Heterostructure Handbook

4λ (13.3 mm)

Diode placement

a + Video signal −

2a

Interdigital capacitors CL = 570 µm

D

2CW CW = CL 5 (a)

W

(b)

FIGURE 9.10.16 Picture of the W-band TSA fabricated on 100-mm thick silicon substrate with (a) 300-mm and (b) 600-mm wide holes etched from the backside. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379–383, 2002. With permission. Copyright IEEE.)

result in bad radiation pattern. For comparison purpose, the same antenna is also fabricated on a quartz substrate («eff ¼ «r ¼ 3.78) whose thickness (150 mm) was chosen to give an effective thickness (0.042) close to the one of the micromachined 100-mm thick silicon TSA. Figure 9.10.17 to Figure 9.10.20 show the radiation pattern for the antennas at 90 GHz. It is clear that the TSA on 100-mm thick silicon does not perform well, and micromachining is essential to reduce the effective dielectric constant. It is important to notice the similar radiation patterns of the TSA on 150mm quartz and the micromachined TSAs on silicon with 300- and 600-mm wide holes. These antennas have almost the same effective thickness (teff / l0 ¼ 0.042), and therefore, the improvement in the micromachined silicon TSA is directly related to the effective dielectric constant of the substrate, and not to a substrate mode suppression phenomena due the presence of the periodic holes. The 300-mm wide hole antenna and the 150-mm quartz antenna resulted in very similar cross-polarization components. The improvement in the micromachined TSA starts to deteriorate for a hole diameter of 750 mm. In fact, in these cases, the hole diameter is so large that only two hole period are deﬁned in the TSA aperture at the edge of the substrate. Therefore, the volumetric average of the dielectric constant cannot be used accurately. Still the E-plane pattern is quite acceptable, but the H-plane pattern starts to break down. The measured sidelobe at 458 is due to the large diameter hole and move to þ458 if the antenna is ﬂipped. The quart TSA and the micromachined silicon TSA with 300 mm holes were also measured at 105 GHz and shown in Figure 9.10.21. The measured patterns of the quartz and the micromachined TSA are very similar and are much better that the nonmicromachined case. This shows that the effective dielectric constant model is quite wideband and the design shown in Figure 9.10.16 can easily cover the 80 to 110 GHz range.

© 2006 by Taylor & Francis Group, LLC

9.10-1111

Wideband Antennas on Silicon

0 Co-pol −5

0 −5

dB

−10

Co-pol X-pol

−20

−10 dB

−30 −90

−20 −25

−60

−30 0 30 Angle (deg.)

60

90

0 Co-pol −60

−30 0 30 Angle (deg.)

60

90

-5 −10

0 dB

−5 −10 −15

dB

Co-pol X-pol

−20

−15 −20

−60

−30

0

30

60

90

Angle (deg.)

FIGURE 9.10.17 Measured patterns for TSA on 100mm thick silicon wafer with no holes. (a) E-plane pattern and (b) H-plane pattern, at 90 GHz. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379– 383, 2002. With permission. Copyright IEEE.)

X-pol

−25 −30 −90

−25 −30 −90

X-pol

−25

−15

−30 −90

−15

−60

−30

0 30 Angle (deg.)

60

90

FIGURE 9.10.18 Measured patterns for TSA on 100mm thick micromachined silicon wafer with 300-mm wide holes (dashed line) and on 150-mm thick quartz (solid line). (a) E-plane pattern and (b) H-plane pattern, at 90 GHz. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379–383, 2002. With permission. Copyright IEEE.)

9.10.4 Surface Micromachined Monopoles for W-Band Applications [21] Printed circuit antennas are often used in compact millimeter-wave systems as a low-cost solution [22]. Nevertheless, microstrip patch antennas often suffer from low bandwidth, high loss, and perturbation of radiation pattern caused by surface wave, which limit their application in broadband modules and have led to various bandwidth improvement techniques [23]. On the contrary, thin wire or cylindrical monopoles have broad impedance bandwidths and might be better candidates for broadband radiation. The major roadblock for their wide application is that the 3D transition from the preceding planar transmission lines to the monopole radiation structures is more complicated than those of printed circuit antennas. It is well known that in lower frequency systems, the cylindrical monopole is usually fed from the backside by a coaxial line, requiring the use of an etching process. In compact millimeter-wave

© 2006 by Taylor & Francis Group, LLC

9.10-1112

The Silicon Heterostructure Handbook

0

0

Co-pol

Co-pol

−5

−5

−10 dB

dB

−10 −15

−20

−20

−60

−30 0 30 Angle (deg.) (a)

60

−30 −90

90

−30 0 30 Angle (deg.)

60

90

0 Co-pol

Co-pol −5

−5

−10

−10

−15

−15

dB

dB

−60

(a)

0

X-pol (750 µm)

−20

−20 −25 −30 −90

X-pol (750 µm)

−25

X-pol (600 µm)

−25 −30 −90

−15

−25

X-pol (600 µm) −60

−30 0 30 Angle (deg.)

60

90

(b)

FIGURE 9.10.19 Measured patterns for TSA on 100mm thick micromachined silicon wafer with 300-mm (dashed line) and 600-mm wide holes (solid line). (a) E-plane pattern and (b) H-plane pattern, at 90 GHz. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379–383, 2002. With permission. Copyright IEEE.)

−30 −90

−60

−30 0 30 Angle (deg.)

60

90

(b)

FIGURE 9.10.20 Measured patterns for TSA on 100mm thick micromachined silicon wafer with 300-mm (dashed line) and 750-mm wide holes (solid line). (a) E-plane pattern and (b) H-plane pattern, at 90 GHz. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379–383, 2002. With permission. Copyright IEEE.)

systems, this process should be avoided for the reasons of cost reduction and fabrication compatibility with coplanar transmission lines. Therefore, a transition from a two-dimensional CPW structure to a 3D monopole is essential for the effective realization of this concept [24]. A novel cylindrical monopole that is vertically mounted on silicon substrate operating in W-band is presented for the ﬁrst time in Ref. [21]. The work has been enabled by surface micromachining technology and can be realized on other substrates as well. This scheme is proposed as an alternative for traditional leaky wave mode and microstrip radiators. It is via-free, and thus a low-cost solution. In the future, this structure is expected to be easily integrated with other key RF front-end components in millimeter-wave systems. The general conﬁguration and the illustration of key geometrical parameters are shown in Figure 9.10.22. The quarter-wavelength monopole is vertically mounted at the end of the center conductor of the CPW line. The two sides of the ground plane are connected radially to enclose the monopole bottom

© 2006 by Taylor & Francis Group, LLC

9.10-1113

Wideband Antennas on Silicon

0 Co-pol −5

dB

−10 −15 −20 −25 −30 −90

X-pol 750 µm −60

−30

0

30

60

90

Angle (deg.) (a) 0 Co-pol −5

dB

−10 −15 −20 −25 −30 −90

X-pol 750 µm −60

−30

0

30

60

90

Angle (deg.) (b)

FIGURE 9.10.21 Measured patterns for TSA on 100-mm thick micromachined silicon wafer with 300-mm (dashed line) and 150-mm thick quartz (solid line). (a) E-plane pattern and (b) H-plane pattern, at 105 GHz. (From JB Rizk and GM Bebeiz. IEEE Trans. Antennas Propagat. 50:379–383, 2002. With permission. Copyright IEEE.)

FIGURE 9.10.22 (a) Conﬁguration of the structure and (b) illustration of the key geometrical parameters. (From B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for lowcost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, Fort-Worth, TX, June 2004, pp. 1935–1938. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.10-1114

The Silicon Heterostructure Handbook

[24]. The radius of monopole r, the radius of the ground aperture R, the center conductor line width s, and the gap width w between center conductor and ground have been optimized with Ansoft HFSS9.0. The characteristic impedance of CPW lines on silicon has been calculated as a function of normalized center conductor width, using LineCalc of Agilent ADS, and is depicted in Figure 9.10.23. The gap width is ﬁxed to 50 mm for these curves and the ground is assumed to be inﬁnite. In order to get compatibility with both fabrication process and measurement facilities, the center conductor width and gap width have been chosen appropriately. The theoretical input impedance of the quarter-wave length monopole is 36.5 V at resonance. On some substrates, the width of center conductor for 50 V characteristic impedance will be comparable to and even signiﬁcantly larger than the diameter of the monopole. On other side, in order to get a symmetrical radiation pattern, the transition discontinuity should be only a small portion of the circumference of the ground aperture. Considering this, we have two alternative choices for the feeding: (a) use a thinner line width to feed the monopole and transform it to wider lines with the aid of different types of matching networks; (b) from Figure 9.10.23, we can observe that the characteristic impedance is still around 50 V when using a narrow line width of 80 mm, if the diameter of the monopole is 100 mm. Therefore, simply connecting the CPW line without other impedance transforming techniques would also be a reasonable choice. These two schemes have been simulated and compared. In choice (b) the central operating frequency for the monopole was chosen as 85 GHz and the theoretical height of the monopole was 800 mm. Simulation results with Ansoft HFSS 9.0 are shown in Figure 9.10.3 and Figure 9.10.4. Figure 9.10.24 shows S11 for silicon and sapphire substrates, while radiation pattern for silicon given in Figure 9.10.25. The results predict greater than 10 dB return loss from 82 to 92 GHz. As for the radiation performance, a symmetrical far ﬁeld pattern has been achieved for all three substrates. The far ﬁeld radiation parameter calculation tool in HFSS 9.0 was utilized to estimate the radiation efﬁciency and led to the observation that most of the energy is radiated from the monopole.

400

Central conductor width (um)

350

Glass Silicon

300

Sapphire

250 200 150 100 50 40

45

50

55

60

CPW characteristic impedance Zc (ohm)

FIGURE 9.10.23 CPW dimensions versus characteristic impedances on different substrates (gap width ﬁxed to 50 mm). (From B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for low-cost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, FortWorth, TX, June 2004, pp. 1935–1938. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.10-1115

Wideband Antennas on Silicon

0

Silicon

−2

Sapphire

S11 (dB)

−4 −6 −8 −10 −12 −14 −16 60

70

80

90

100

110

Frequency (GHz)

FIGURE 9.10.24 Simulated input return loss for the monopole on silicon substrate and sapphire substrate. (From B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for lowcost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, Fort-Worth, TX, June 2004, pp. 1935–1938. With permission.)

FIGURE 9.10.25 Simulated radiation pattern for the monopole on silicon substrate. (From B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for low-cost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, Fort-Worth, TX, June 2004, pp. 1935– 1938. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.10-1116

The Silicon Heterostructure Handbook

850 µm

10 mm (a)

(b)

FIGURE 9.10.26 (a) A photomicrograph of 3 3 monopole array and (b) an SEM image of a single monopole antenna. (From B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for low-cost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, FortWorth, TX, June 2004, pp. 1935–1938. With permission.)

Figure 9.10.26(a) and (b) shows a photomicrograph of a fabricated monopole antenna array (3 3) and an SEM image of a single monopole antenna, respectively. The fabricated structures were measured to be approximately 850 mm high, which usually vary between 800 and 880 mm.

References 1. KK O, K Kim, et al. Wireless communications using integrated antenna. Proceedings of the IEEE Interconnect Technology Conference, 2003. pp. 111–113. 2. B Strassner and K Chang. Integrated antenna system for wireless RFID tag in monitoring oil drill pipe. Proceedings of IEEE Antenna and Propagation Society International Symposium, 2003, pp. 208–211. 3. JJ Lin, L Gao, A Sugavanam, X Guo, R Li, JE Brewer, and KK O. Integrated antennas on silicon substrates for communication over free space. IEEE Electron Device Lett. 25:1–3, 2004. 4. DH Schaubert and KS Yngvesson. Experimental study of a microstrip array on high permittivity substrate. IEEE Trans. Antennas Propagat. 34:72–97, 1986. 5. MO Thieme and EM Biebl. Calculation of the surface-wave excitation in multilayered structures. IEEE Trans. Antennas Propagat. 46:686–693, 1998. 6. EM Biebl. Integrated active antennas on silicon. Proceedings of Microwave and Optoelectronics Conference, 1997, pp. 279–284. 7. P Russer. Si and SiGe millimeter-wave integrated circuits for sensor and communications applications. Proceedings of 12th International Conference on Microwaves and Radar, 1998, pp. 330–344. 8. J Papapolymerou, RF Drayton, and LPB Katehi. Micromachined patch antennas. IEEE Trans. Antennas Propagat. 46:275–283, 1998. 9. DR Jackson, JT Williams, and AK Bhattacharyya. Microstrip patch designs that do not excite surface waves. IEEE Trans. Antennas Propagat. 41:1026–1037, 1993. 10. JG Yook and PB Katehi. Micromachined microstrip patch antenna with controlled mutual coupling and surface waves. IEEE Trans. Antennas Propagat. 49:1282–1289, 2001. 11. M Zheng, Q Chen, PS Hall, and VF Fusco. Broadband microstrip patch antenna on micromachined silicon substrates. Electron. Lett. 34:3–4, 1998. 12. EY Tsai, A M Bacon, M Tentzeris, and J Papapolymerou. Design and development of novel micromachined patch antennas for wireless applications. Proceedings of the 2002 Asian-Paciﬁc Microwave Symposium, Kyoto, 2002, pp. 821–824.

© 2006 by Taylor & Francis Group, LLC

Wideband Antennas on Silicon

9.10-1117

13. G Gauthier, LP Katehi, and GM Rebeiz. W-band ﬁnite ground coplanar waveguide (FGCPW) to microstrip line transition. Proceedings of the 1998 IEEE IMS Symposium, Baltimore, MD, June 1998, pp. 107–109. 14. G Zheng, J Papapolymerou, and MM Tentzeris. Wideband coplanar waveguide RF probe pad to microstrip transitions without via holes. IEEE Microwave Wireless Components Lett. 13:544–546, 2003. 15. GP Gauthier, A Courtay, and GM Rebeiz. Microstrip antennas on synthesized low dielectricconstant substrates. IEEE Trans. Antennas Propagat. 45:1310–1314, 1997. 16. MJ Vaughan, KY Hur, and RC Compton. Improvement of microstrip patch antenna radiation patterns. IEEE Trans. Antennas Propagat. 42:882–885, 1994. 17. JB Rizk and GM Bebeiz. Millimeter-wave Fermi tapered slot antennas on micromachined silicon substrates. IEEE Trans. Antennas Propagat. 50:379–383, 2002. 18. R Garg, P Bhartia, I Bahl, and A Ittipiboon. Microstrip Antenna Design Handbook. Norwood, MA, Artech House, 2001. 19. F Ulaby. Fundamentals of Applied Electromagnetics. Prentice Hall, Upper Saddle River, NJ, 1999. 20. KS Yngvesson, DH Schaubert, TL Korzeniowski, EL Kollberg, T Thungren, and JF Joansson. Endﬁre tapered slot antennas on dielectric substrate. IEEE Trans. Antennas Propagat. 33:1392– 1400, 1985. 21. B Pan, Y Yoon, J Papapolymerou, MM Tentzeris, and M Allen. A W-band surface micromachined monopole for low-cost wireless communication systems. Proceedings of the IEEE IMS symposium, 2004, Fort-Worth, TX, June 2004, pp. 1935–1938. 22. FK Schwering. Millimeter wave antennas. Proc. IEEE 80:92–102, 1992. 23. DM Pozar. Considerations for millimeter wave printed antennas. IEEE Trans. Antenna Propagation 31:740–747, 1983. 24. D Staiculescu, J Laskar, and M Tentzeris. Flip chip design rule development for multiple signal and ground bump conﬁgurations. Proceedings of the 2000 Asian-Paciﬁc Microwave Conference, 2000, pp. 136–139.

© 2006 by Taylor & Francis Group, LLC

9.11 Packaging Issues for SiGe Circuits 9.11.1 9.11.2 9.11.3

Background .......................................................... 9.11-1119 IC Package Evolutions ........................................ 9.11-1120 Recent Package Technology Trend ..................... 9.11-1120 Ball Grid Arrays (BGA) . Flip Chip Technology Multichip Module

Kyutae Lim, Stephane Pinel, and Joy Laskar Georgia Institute of Technology

9.11.4 9.11.5 9.11.6

.

Future Direction .................................................. 9.11-1123 Package Design Consideration ........................... 9.11-1124 Summary .............................................................. 9.11-1125

9.11.1 Background The role of the SiGe package is more important than other IC packages, since the SiGe devices make it possible to integrate digital, analog, and radio frequency (RF) functions on the same die and process. More care should be taken to minimize the noise and parasitic in the package of the SiGe die than the usual integrated circuit (IC) package. Packaging is a method for allowing electrical connection to an integrated circuit while maintaining and regulating its operating environment, and achieving performance, reliability, and cost requirements. The primary function of a package is to provide a means for electrical connectivity from the semiconductor device to a printed wiring board (PWB), also known as a printed circuit board (PCB). It provides a path for power to be applied to the chip as well as a way for the data signals to be transmitted into and out of the chip. Its secondary function is to house and protect the fragile chip from harsh environmental conditions, like moisture, light, and dust, that might hinder its performance. Finally, the package provides a pathway for dissipating the heat generated by the semiconductor device [1]. In its early evolution, the influence of the package on performance was limited; however, as the systems evolve to provide increasing performance and operation frequencies, the package must evolve to keep up, and packaging design must ensure that it optimally enables the systems. From the traditional role of a protective mechanical enclosure, the modern package has been transformed into a sophisticated thermal and electrical management platform. Furthermore, system architecture and design techniques can have significant impact on the complexity and cost of packaging. The need to optimize the total solution (chip, package, board, and assembly) has never been more important to maximize performance and minimize cost. Recent advances in packaging indicate a migration from wirebond (where the chip or die is interconnected to the package only on the periphery of the die) to flip chip (where the die is interconnected to the package using the entire die area) [2]; and from ceramic to organic packages, with cartridge and multichip technologies emerging as key form-factors. With the emergence of the ‘‘segmented’’ market (mobile, desktop, server, and associated subsegments), we see a significant proliferation of packaging types tailoring functionality and costs to the different application specifications. 9.11-1119 © 2006 by Taylor & Francis Group, LLC

9.11-1120

9.11.2.

The Silicon Heterostructure Handbook

IC Package Evolution

The original packaging devices were typically large. They connected to the outside world by means of long leads or pins that needed to be inserted through holes in the PCBs. These devices came to be known as ‘‘through-hole’’ devices for that reason and were made of metal, ceramic, and plastic. The most predominant of these packages in the 1970s and 1980s was the dual-in-line package (DIP) [3], which is still in use today. The DIP’s main limitation is the lead count with an upper limit of 64 pins. After that point, the package simply becomes too large for any practical application. A solution to this is the pin grid array (PGA), which uses a two-dimensional array of pins protruding from the bottom of the package. The PGA package can have around 200 pins on average [4]. The main problem with through-hole devices was their size. Furthermore, their performance in high frequencies was quite limited. The trend in PCB manufacturing was to increase density while decreasing board area and increasing signal frequencies. Through-hole devices did not easily allow this to happen. In the 1980s, through-hole devices began to give way to a new packaging technology called surface mount technology (SMT) [5]. The leads from these packages mount directly to rectangular pads on the surface of the PCBs. They did not require holes to be drilled into the PWBs. As a result, the width of the leads could be smaller and the spacing between the leads (lead pitch) could be decreased. This allowed for a package with the same number of pins as a traditional through-hole device to be significantly smaller, despite the fact that these devices were made with the same materials as the through-hole devices. Common surface mount devices included the plastic leaded chip carrier (PLCC) and the small outline integrated circuit (SOIC). In recent years, the quad flat pack (QFP) has become a predominant fine pitch, high lead count package solution. Figure 9.11.1 illustrates most of the previous topologies and Figure 9.11.2 shows some popular packaging devices used through the 1980s and 1990s [1]. Today, as semiconductor technology continues the minimization trend, the level of complexity on a single silicon chip is increasing. This leads to more functionality in a smaller area, higher I/O counts, higher frequencies, and higher heat dissipation requirements. All of the technologies listed up to this point are inadequate and impractical to satisfy all of these requirements. This is not to say that they do not have a place anymore in modern integrated circuit design, but they will not meet the needs of leading-edge technologies and, in particular, in the case of very high-performance systems, such as RF and millimeter waves integrated systems. New packaging technologies have emerged in the last 10 years that are aimed at solving the I/O and heat challenges. The first of these solutions continue to use the same wire bonding technology used in traditional packages. However, these packages can also accommodate advances in interconnect technology. Flip chip technology (also called direct chip attach [DCA]) has emerged as a possible alternative to wire bonding [6]. Regardless of the interconnect technology, the most promising packaging technology being pursued at the present is the ball grid array (BGA) package [7], which is a descendant of the PGA package discussed earlier. Instead of through-hole pins, the BGAs have small conductive balls that are soldered directly to the surface of PCBs. As the balls are located at the bottom of the package, an obvious disadvantage is the inability to visually inspect the connections between the package and the PWB. As a result, the assembly process for PWBs using BGA technology must be very precise with very low tolerance for error. Its advantages in I/O count, I/O density, and heat dissipation easily outweigh this somewhat minor disadvantage.

9.11.3.

Recent Package Technology Trend

Ball Grid Arrays (BGA) BGA packages allow for PWB space savings since an array of solder bumps (or balls) are used in place of traditional package pins. An example of a BGA applied to a 3D integrated module concept is presented in Figure 9.11.3 [8].

© 2006 by Taylor & Francis Group, LLC

9.11-1121

Packaging Issues for SiGe Circuits

Transistor-outline can

Single-in-line package

Plastic dual-in-law package

Small-outline IC

Ceramic leadless chip carrier

Plastic leaded chip carrier

Metal flatpack

Ceramic flatpack

Ceramic pin-grid array

Assortment of level 1 IC packages

FIGURE 9.11.1 Various types of IC packaging through 1970 to 1980.

FIGURE 9.11.2 Packaging evolution through 1980 to 1990s.

© 2006 by Taylor & Francis Group, LLC

9.11-1122

The Silicon Heterostructure Handbook

Filter

Antenna RF building blocks µBGA LTCC board Embedded RF passives BGA

FR4 mother board FIGURE 9.11.3 BGA package-based 3D module.

BGAs are expected to be the solutions for packages requiring over 200 pins and will be implemented using wire bonding in the lower I/O density parts and flip chip in the higher I/O count and higher power devices. Ultrafine pitch (UFP) wire bond technology will allow for a larger die to be placed on smaller substrates and an effective pad pitches below 60 mm. Increasing circuit density can accommodate more than 1000 I/O devices and enables shrinking of die size by 20–50%. Placing a larger die with more functionality on a smaller substrate results in significant cost savings, as the substrate is a driving factor in the cost of the device. Recent trends indicate that I/O counts for leading-edge devices grow at a rate of approximately ten times every 14 years. Liquid-encapsulant underfills are expected to be needed to relieve the stress due to CTE differences between the chip and the package substrate in the flip chip devices. Chip scale packages using fine pitch BGAs with a size in the order of the chip size will be the next level of advancement for applications where low weight and small package size are required. As the technology matures and processes become cheaper, BGAs have the potential to become the workhorse of packaging technologies, like the DIP was for the 1970s and 1980s.

Flip Chip Technology Flip chip is actually a 30-year-old technology that has only recently matured to be widely accepted and costeffective for the semiconductor industry. It refers to flipping a silicon die or chip and mounting it face down on a substrate. A schematic of a flip chip transition from CPW to CPW is presented in Figure 9.11.4 [9]. Of the 60 billion integrated circuits produced in 1998, approximately 1.5% of them were manufactured using flip chip technology. From 1997 to 1998, the number of flip chip dies grew by 40%. An average annual growth rate of 48% for flip chip is expected over the next several years. Advantages of flip chip include efficient die access, high assembly yields using solder attachment, elimination of an interconnect layer, lower inductance, and the potential for low cost. Efficiency of die access comes from the fact that the entire surface of the die is available for electrical connection (as opposed to just the edges in wire bonding.) Using solder attachment, instead of conductive adhesives, provides the possibility of high assembly yields due to the self-alignment properties of the solder. The wire bond is eliminated, providing higher reliability by reducing one level of interconnect. The removal of the ‘‘long-lead’’ wire bond also reduces the inductance, an important feature for RF applications. The opportunity for low cost comes from the fact that flip chip is created at the wafer level. This cost savings is only realizable with a well-understood, controlled, efficient assembly process.

Multichip Module The term multichip module (MCM) refers to the packaging of multiple silicon dies into one device [10]. MCMs offer the ability to reduce package pin count by combining two or more high pin count devices that would normally connect to each other at the board level into one package where the interconnect is

© 2006 by Taylor & Francis Group, LLC

9.11-1123

Packaging Issues for SiGe Circuits

Mounting substrate CPW

CPW Mounting substrate

FIGURE 9.11.4 Flip chip configuration.

performed at the chip level. The resulting packaged system only needs a reduced set of pin to connect power and signals from the outside world. It can also serve to reduce PWB real estate (an expensive commodity) and presents the following advantages: .

.

.

.

.

.

.

Improved performance, such as shorter interconnect lengths between die (resulting in reduced delay time, lower RF parasitic and losses), lower power supply inductance, lower capacitance loading, less cross talk, and lower off-chip driver power. Miniaturization, since MCMs result in a smaller overall package when compared to packaged components performing the same function, hence resulting I/O to the system board is significantly reduced. Shorter time-to-market, making them attractive alternatives to ASICs, especially for products with short life cycles. Low-cost silicon sweep, allowing integration of mixed semiconductor technology, such as SiGe or GaAs. Hybrid configurations, including surface mount devices in the form of chip scale or micro-BGA packages and discrete chip capacitors and resistors. Simplification of board complexity by integrating several devices onto one package, thereby reducing total opportunities for error at the board assembly level. Capability of accommodating a variety of second-level interconnects. While BGA are the most popular ones, lead-frame solutions can be employed for plugability, enabling modularity for upgrades.

The widespread use of MCMs has been hurt by a few factors. It is a relatively high-cost process. Since not all of the signals are connected to the outside world, package level testing is difficult, so effort must be made to insure that the die being put into the chip is good. Obtaining such ‘‘known good die’’ (KGD) is still a challenge. Also, the proliferation of flip chip, BGAs, and chip scale packages for single-chip package solutions has reduced the need for chip-level system integration.

9.11.4.

Future Direction

The needs of assembly and packaging are driven equally by silicon technology and marketing requirements. As always, cost will be the driving factor. It is expected that packaging costs per pin will decrease in the coming years, but the overall packaging pin count is expected to increase at a faster rate than the cost decrease. The increase in pin count is also expected to affect the substrate and the system-level costs. The roadmap identifies thermal management as a significant challenge. Handheld devices that do not use forced air and rely on the operator’s hand to dissipate the heat from the unit will need new heat sink technologies and materials with better thermal conductivity. The cost-performance market (desktop processors) requires forced air-cooling. Flip chip could be a possible enhancement to the forced air-cooling as the front-side of the silicon chip provides a ‘‘direct, efficient heat path from the chip to the heat sink.’’ Existing heat sink solutions are predicted to be ineffective above 50 W in applications where forced air is not a viable solution due to market requirements. A reduction of internal thermal resistance and better air-cooling techniques will be critical for

© 2006 by Taylor & Francis Group, LLC

9.11-1124

The Silicon Heterostructure Handbook

future thermal solutions. The high-end market, with predicted power consumption between 110 and 120 W per chip will pose an even greater challenge. A closed-loop cooling system that meets market and customer requirements will be necessary. In general, flip chip is predicted to become the predominant technology for chip-to-next levels interconnect. Commodity products will continue to use advanced forms of wire bonding until the cost of flip chip becomes affordable for that market. Flip chip is especially desirable because it is possible to reduce a level of interconnect when using this technology. Another important RF packaging challenge is matching the coefficient of thermal expansion (CTE) between the silicon chip and the substrate. When using organic substrates, underfills will be required with high reliability, ease of manufacturability, stronger attachment at the interface, and higher resistance to moisture. Liquid-crystal polymers (LCP) with engineered CTE could be a substrate solution [11]. High-frequency packaging geometries are often sorted in two independent areas of focus, single-chip and multichip packages. The single-chip packages include the technologies discussed above in the ‘‘Background’’ section. Devices like QFPs will reach a maximum lead count of 304 and lead pitch will reach a minimum of 0.5 mm. After this point, the package body size and the surface mount assembly complexity become cost ineffective and multichip solutions have to be investigated. The RF front-end module is the core of these systems and its integration poses a great challenge. Microelectronics technology, since the invention of the transistor, has revolutionized many aspect of electronics product. This integration and cost path has led the microelectronics industry to believe that this kind of progress can go on forever, leading to the so-called ‘‘system-on-chip’’ (SOC) for all applications [12]. But it is becoming clear that it is still a dream to produce a complete on-chip solution for the novel wireless communication front-ends. Considering the characteristics of the RF front-end modules, such as high performance up to 100 GHz operating frequency, large number of high-performance discrete passive components, design flexibility, reconfigurable architecture, low power consumption, compactness, customized product, short time to market and low cost, the ‘‘system-on-package’’ (SOP) approach, has emerged as the most effective way to provide a realistic integration solution [13].

9.11.5.

Package Design Consideration

The major issues are manufacturing cost, size and weight, signal integrity, low high-frequency loss, heat dissipation, mechanical, stability, testability, reliability: .

.

.

Manufacturability and cost: Materials, fabrication steps, and IC Costs incurred from testing, rework, yield loss. Manufacturability depends on process control, cycle time, repirability, equipment downtime, design tolerances Electrical design: Interconnect speed now plays a dominant role in determining performance limits. Each connection has parasitic capacitance, resistance, and inductance that limit speed, potentially distort signals, and add noise Leads for connections are also a source of reliability problems Several factors need to be considered, including: — Lead length — Matched impedances — Low ground resistance — Simultaneous switching and power supply spiking Thermal design: Objective: remove heat from the junctions of the ICs (to keep dopants from moving and avoid self heating effects) Techniques: forced air, liquid cooling, monophase cooling, dual phase cooling Considerations: 1. How to remove heat (from the front or backside of the IC)? 2. Air or liquid? mono or dual phase?

© 2006 by Taylor & Francis Group, LLC

Packaging Issues for SiGe Circuits

9.11-1125

3. Thermal conductivity of the substrate 4. Stresses induced due to CTE mismatches .

Mechanical design: Susceptibility to thermal stresses must be considered in design Tensile modulus (‘‘stiffness’’) also a consideration

9.11.6.

Summary

In this section, IC package technology was reviewed and the future direction has been discussed. Package requirement for the SiGe IC package is more stringent than that for the conventional package, especially when the IC deals with mixed signal applications. In designing of those packages, the designers should take more care to minimize the high-frequency noise as well as 1/f noise. Also Ohmic loss and parasitic effect should be considered together since the I/Os deal with the low frequency to RF frequency at the same time. Recent progress in the system shows SOC and SOP approaches are the direction for the future system. In other words, a full system function can be realized in a single die thanks to SiGe process. Or for the more demanding system, a system can be realized in a single package. So it becomes very important to decide how the system would be realized. By properly allocating the functions to the IC or package, we can optimize the system in performance and cost. In the package technology itself, significant challenges lie ahead to achieve the package I/O densities, lead pitch, power dissipation, and circuit speeds required of today’s and tomorrow’s high-performance integrated circuits. Packaging solutions are being pursued to meet these challenges. Each option has its own advantages and associated challenges to make it a feasible, cost-effective solution. BGAs utilizing wire bonding is a short-term solution. The proliferation of flip chip and its application into BGAs provides the next level solution. MCMs offer even further solutions. Of course, these are not all the answers. There are other packaging technologies that have not been discussed here. These are, however, the solutions for the foreseeable future. Advances beyond today’s technology will produce new packaging options and with these options, more challenges as well.

References 1. R. Tummala, E. Rymaszewski, and A. Klopfenstein, Microelectronics Packaging Handbook – Part II, Second Edition, Kluwer Academic Publishers, Dordrecht, 1997. 2. D. Staiculescu, K. Lim, A. Sutono, H. Liang, M. Tentzeris, and J. Laskar, Flip chip vs. wirebond, Printed Circuit Design Magazine, June 2002, pp. 12–16. 3. M. DiOrio and S. Pinamaneni, Material effects on the performance and reliability of high-power molded dual-in-line packages, Proceedings of the 38th Electronics Components Conference, May 1988, pp. 406–410. 4. G.C. Phillips, Jr. Planar pin grid array (PGA) ceramic packaging, Proceedings of the 38th Electronics Components Conference, May 1988, pp. 350–354. 5. R. Chroneos, D. Mallik, and S. Prough, Packaging alternatives for high lead count, fine pitch, surface mount technology, Proceedings of Electronics Manufacturing Technology Symposium, September 1991, pp. 181–186. 6. M. Christensen, Flip Chip: A Technology Reborn. Solid State Technology; Pennwell Publishing Co., 1999. 7. D. Dunn, BGAs given a couple of boosts. Electronic Buyer’s News. CMP Media, Inc. November 29, 1999. 8. M.J. Kuzawinski, IBM’s Ultra Fine Pitch Wire Bond PBGA Modules, IBM Microelectronics Web Site, http://www.chips.ibm.com/micronews/vol4_no4/pbga.html, 1998. 9. D. Staiculescu, J. Laskar, and M.M. Tentzeris, Design rule development for microwave flip chip applications, IEEE MTT Journal, 48(9), 2000, 1476–1481.

© 2006 by Taylor & Francis Group, LLC

9.11-1126

The Silicon Heterostructure Handbook

10. C. Mitchell, Assembly and reliability study for the micro-ball grid array, Proceedings of the 16th IEEE/CPMT IEMT Symposium, September 1994, pp. 344–346. 11. S. Pinel, M. F. Davis, V. Sundaram, K. Lim, J. Laskar, G. White, and R. Tummala, High Q passives on Liquid Crystal Polymer substrates and mBGA technology for 3D integrated RF front-end module, IEICE Transactions on Electronics. E86–C(8), 2003, 158–1592. 12. A. Matsuzawa, RF-SoC — expectations and required conditions, Invited Paper, IEEE Transactions on MTT, 50(1), 2002, 245–253. 13. K. Lim, S. Pinel, M.F. Davis, A. Sutono, C-H. Lee, D. Heo, A. Obatoynbo, J. Laskar, M. Tentzeris, and R. Tummala, RF-SOP for wireless communications, IEEE-Microwave Magazine, 3(1), 2002, 88–99.

© 2006 by Taylor & Francis Group, LLC

9.12 Industry Examples of the State-of-the-Art: IBM — High-Speed Circuits for Data Communications Applications 9.12.1 9.12.2

Optical Link Overview . Technology Overview . Receiver Circuit . 40 Gb/sec Transmitter Implementations using Half-Rate and Full-Rate Architectures

Daniel J. Friedman and Mounir Meghelli IBM T.J. Watson Research Center

Introduction......................................................... 9.12-1127 Transmitter and Receiver Chip Set at 43 Gb/sec .............................................................. 9.12-1128

9.12.3

Summary .............................................................. 9.12-1140

9.12.1 Introduction The advent of advanced SiGe technologies in the 0.18 [1] and 0.13 mm [2] nodes has enabled the implementation of silicon-based wired data communications circuits operating at data rates of 40 Gb/ sec and beyond [3–8] targeting standards such as SONET OC-768. Two key classes of circuits for high data rate communications are serializers, built from a clock multiplying PLL and a multiplexer, and deserializers, built from a clock and data recovery PLL and a demultiplexer. The raw multiplexing and demultiplexing functions are critical not only for communications systems, but also for high-speed test equipment such as pattern generators, which typically generate output patterns in parallel form at low data rates and multiplex these to generate the high-speed output, and bit error rate testers, which typically check input patterns in parallel form after a demultiplexing stage. There are many challenges that must be addressed in the execution of very high data rate circuit designs. Specifications for random and deterministic jitter tend to be very stringent and must be satisfied over fairly broad process, temperature, and supply regimes. Signal integrity must be addressed not only at the package and board level, but must be considered on-chip as well. High-speed clock distribution is difficult and consumes large amounts of power, making architectures that enable minimal, efficient clock distribution extremely desirable. Finally, testing of such circuits is very demanding, in part because small problems like loose cable connections can significantly degrade results, but also because when data rates become sufficiently high, there is no standard test equipment available. 9.12-1127 © 2006 by Taylor & Francis Group, LLC

9.12-1128

The Silicon Heterostructure Handbook

The design of a 40 Gb/sec serializer and deserializer chip set implemented in a 0.18 mm SiGe BiCMOS process will be the focus of this chapter, with emphasis placed on recently reported technical results [7–10]. In the course of describing the chip set, key building blocks will be presented, as well as an architecture and performance comparison of two approaches to the implementation of the serializer.

9.12.2

Transmitter and Receiver Chip Set at 43 Gb/sec

Optical Link Overview A key application for advanced SiGe technologies is optical data communication. In a typical optical link and associated electronics (Figure 9.12.1) the transmit subsystem takes relatively low-speed parallel data, multiplexes it onto a high-speed serial line, and converts these data from an electrical to an optical format for transmission over an optical fiber. The receive subsystem converts the serial optical signal at its input to an electrical format and demultiplexes the resulting serial data stream to create multiple lower speed parallel outputs. The transmit electrical serialization function is implemented by a multiplexer, which converts the multiple parallel data inputs to a single serial output, and an associated clock multiplier unit, which generates the clock frequencies and phases necessary for multiplexer operation. The multiplexer output is typically translated to the optical domain via a laser diode driver driving a laser diode for many 10 Gb/sec and slower systems, and via a modulator driver driving an electro-absorption modulator used to modulate a continuous wave laser output for 40 Gb/sec systems. On the receive side, a photodetector is used to convert the optical signal to an electrical current and a combination of a transimpedance amplifier and a limiting amplifier is typically used to generate an input signal with sufficient amplitude to be used by the deserializer. Because no explicit clock is sent with the data over the optical link, the deserializer must execute a clock and data recovery function in addition to the demultiplexing and thus consists of a clock and data recovery (CDR) phase locked loop (PLL) and a demultiplexer. In the case of 40 Gb/sec optical data transmission, the SONET OC-768 standard effectively provides a specification for the performance requirements of the elements of a link. The data rate range of 39.8 to 43 Gb/sec is set by the base OC-768 transmission rate at the low end and by the line rate when forward error correction (ITU-T G.709) is used at the high end. For the serializer and deserializer circuits that are the main topics of this chapter, transmit jitter generation specifications and receive jitter tolerance specifications can also be derived from this standard.

Receiver

Transmitter

E/O

optical fiber

O/E

synthesized clock Tx PLL

E/O: Electrical to optical conversion O/E: Optical to electrical conversion

Ref clock

FIGURE 9.12.1 Typical high data rate optical link block diagram.

© 2006 by Taylor & Francis Group, LLC

Data Retiming

DMUX

recovered clock Rx PLL

Ref clock

4 parallel data out

4 parallel data in

MUX

Industry Examples of the State-of-the-Art: IBM

9.12-1129

Technology Overview The circuits described in this section were implemented in a production-level 0.18 mm SiGe BiCMOS process. This technology [1] features 120 GHz fT, 100 GHz fmax HBTs, thick metal enabling inductor implementations, MIM capacitors, and a full suite of 0.18 mm CMOS devices. The bipolar logic family chosen for this work was emitter-coupled logic (ECL) because this choice enabled the use of a lower supply voltage, hence lower power consumption logic blocks, without sacrificing significant performance as compared to alternate, more headroom-hungry approaches such as emitter–emitter coupled logic (E2CL). Differential internal swing levels were chosen to be between 500 and 600 mV in these designs, here reflecting a compromise between signal-to-noise ratio and limiting headroom (and thus supply voltage) requirements.

Receiver Circuit The task of the receiver circuit is to take an input 40 Gb/sec serial data stream and demultiplex it. The data is sent with an implicit clock that must be recovered from the incoming data to enable proper retiming of the input. The serial data will be corrupted by deterministic and random jitter accumulated in its journey from the transmitter, through electrical to optical conversion, through a fiber, and through optical to electrical conversion. A key measure of the quality of the receiver is thus its jitter tolerance, or the degree of data impairment for which the receiver is still able to correctly recover the original data. Furthermore, the amplitude of the input signal may be small, particularly if the signal is taken directly from a transimpedance amplifier without passing through a limiting amplifier. Because of the extremely high data rate of the input, details of physical design and clock distribution have a significant impact on architecture, along with traditional factors like device performance. In the receiver design, a half-rate architecture was chosen over a full-rate architecture, thus enabling a lower power implementation that did not unduly stress the limits of the high-speed HBTs in the technology. This choice did incur costs, however, with main drawbacks of using a half-rate architecture in the receiver being the degradation of jitter tolerance due to the effects of duty cycle distortion and this architecture’s requirement for quadrature clock generation. In the section covering the transmitter, the half-rate versus full-rate architecture question will be revisited for that circuit block. Design Details of Key Receiver Circuit Blocks The receiver itself (Figure 9.12.2) includes an integrated limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector [7]. The intent of executing this design was to demonstrate the high-speed core of the deserializer function while keeping the input and output counts at a manageable level for a test site implementation. Note that a common implementation choice for a SONET product-level receiver would integrate the clock and data recovery function with a 1:16 demultiplexer [4]. As a precursor to implementing the receiver, a 1:4 demultiplexer was implemented as a stand-alone design, with the architecture of the stand-alone block used in large measure in the full receiver. Highspeed building blocks of this type, as well as multiplexers, dividers, and latches, have been reported at high data rates and in multiple technologies [9,12–18]. Such blocks serve as technology demonstration vehicles, as parts of home-grown high data rate test environments for more complex circuits, and as elements in testers themselves. The stand-alone demultiplexer used in the receiver described in this chapter (Figure 9.12.3) uses a tree architecture with a recursive series of 1:2 demultiplexer stages, with a half-rate clock input used for the first 1:2 demultiplexing stages. A quarter-rate clock is generated from the half-rate input clock using a static divider to perform the last 1:2 demultiplexing stages. In the standalone implementation, input clock and data are received with double stage, wide bandwidth Cherry– Hooper [19] amplifiers, improving input sensitivity. The output buffers for the parallel data are implemented as differential pair stages with on-chip resistor terminations. In the physical design of the demultiplexer, transmission lines are used on long on-chip runs, a design approach followed in all high data rate designs described in this chapter. The stand-alone demultiplexer was demonstrated

© 2006 by Taylor & Francis Group, LLC

9.12-1130

The Silicon Heterostructure Handbook

2:4 DMUX D-even

Parallel data

2:4 Demux

D-odd

4⫻10.75Gb/s

/2 On-chip capacitor

Limiting amplifier Serial Data 43Gb/s

CDR

Amp Input buffer

I

Phase detector

Amp

External Trim.bits 4

Liner amp

Charge pump

Amp

I/Q VCO 21.5 GHz

Q

bang-bang control

Ref. clock selection

Frequency acquisition aid

Ref. clock (C16, C64)

C4 10.75 GHz

Divider chain Lock detector

Frequency acquisition aid

Lock ind.

FIGURE 9.12.2 Block diagram of 40 Gb/sec receiver, including CDR and 1:4 demultiplexer. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.) D00 1:2 Data

D01

1:2 D10 1:2

Clock

D11

/2

Clock/2

Bit skip

Data

Latch

D DB

FF1

Q QB

Latch

D DB

CB C

Q QB

D1

CB C

Clock C CB D DB

Latch

C CB

C CB D DB

Q QB

FF2

Latch

Q QB

D DB

Latch

Q QB

D0

FIGURE 9.12.3 Simplified block diagram of the 1:4 demultiplexer circuit. (From M Meghelli, A Rylyakov, and L Shan. IEEE Journal of Solid-State Circuits 37:1790–1794, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples of the State-of-the-Art: IBM

9.12-1131

operational to input serial data rates exceeding 60 Gb/sec, more than ample performance for use as a building block in the 40 Gb/sec receiver implementation. In the full receiver (CDR plus 1:4 demultiplexer) implementation, the Cherry–Hooper stage was included at the receiver input, effectively serving as a limiting amplifier. In this application, the Cherry– Hooper architecture was realized using a pair of emitter followers with 50 V on-chip termination resistors for impedance matching as an input buffer, followed by a single amplifier stage driving two parallel amplifier stages. The tree drive architecture reduces loading on the high-speed nets, enabling improved input sensitivity while maintaining bandwidth. Common approaches for band-limited signals, inductive peaking and shunt peaking, were not followed in this design due to the risk of incurring a deterministic jitter penalty in the signal provided to the CDR for retiming. The CDR recovers half-rate quadrature clocks from the input random data stream, using these to recover the incoming 40 Gb/sec data. The capture range of the CDR is narrow, so a dual-loop architecture is used to extend the PLL capture range to an acceptable level. The second loop, used for frequency acquisition, locks the VCO to an input reference clock [20,21]. An on-chip lock detector counts reference clock pulses against divided VCO output pulses and indicates frequency lock when these count values agree to within +0.1%. Once the loop has achieved frequency lock, the data recovery loop is activated. Because the reference clock is set such that the VCO frequency will be close to half the data rate, at switchover the data rate falls within the capture range of the CDR and the loop locks very quickly. The lock detector continues to monitor the recovered clock against the reference clock and will switch the PLL back to frequency acquisition mode if the detector flags an unlocked condition during operation. The lock detector itself is built using on-chip standard-cell CMOS. Because a supply voltage of 3.6 V was used for the analog circuits in this design and the standard-cell CMOS library was designed for a nominal 1.8 V ground-referenced supply, it was decided to use a 1.8 V supply voltage (1.8 V above the 3.6 V analog supply) for the CMOS. This approach not only enabled the use of standard CMOS library elements, but also as the lock detector consumes less than 3 mA, power for the detector could be supplied by an on-chip voltage regulator with virtually no power impact on the scale of the complete design, although it was provided via a separate pin in this implementation. In the fullrate transmitter described later in this chapter, the lock detector was supplied from an on-chip regulator. The half-rate architecture of the receiver demanded the use of a quadrature VCO (Figure 9.12.4). Several implementation approaches for this circuit are possible, including ring oscillators, coupled bipolar LC oscillators, and coupled CMOS LC oscillators. In this design, coupled CMOS LC oscillators [22] were chosen, enabling the combination of the phase noise performance of an LC implementation with an easy coupling scheme using FET switches. Each of the coupled CMOS LC-VCOs is implemented with cross-coupled inverters creating the negative resistance required for oscillation. In order to further improve the phase noise performance of the VCO, the gain of the VCO in the control loop was reduced, with overall tuning range requirements addressed by the use of digitally controlled band-switching varactors. The total tuning range for this VCO is 2.3 GHz, taking into account band-switching and loop control, with overlap between adjacent bands sufficient to ensure that once the proper initial band of the 16 available is chosen, the PLL stays locked under temperature and supply drift conditions without requiring a change to a new band. The VCO frequency control is provided in two paths. A proportional path provides low-latency update pulses directly to the VCO, bypassing the charge pump and linear amplifier and enabling quick effective phase adjustments by the VCO [23]. The integral path passes through the charge pump and linear amplifier and acts to set the center frequency of the VCO. In the design, an external control to set the amplitude of the proportional bang–bang pulses can be used to adjust PLL loop bandwidth. The phase detector (Figure 9.12.5) chosen for this implementation has advantages in its low gate count and simple clock distribution [20]. When adapted for half-rate operation, the complexity of this block increases as compared to a full-rate implementation, but the benefits accrued in the logic gate performance by going to a slower clock rate more than compensate for this effect. The phase detector receives the quadrature clock inputs from the VCO in the form of an in-phase (I) clock and a quadrature phase (Q) clock, as well as the buffered data. The phase detector is built from three double-edge

© 2006 by Taylor & Francis Group, LLC

9.12-1132

The Silicon Heterostructure Handbook

4bits

Vtrim

4bits

Var

Vtrim

Var

˚

˚

Q (270)

Q (90)

˚

(180)

˚ (0)

Vee

FIGURE 9.12.4 Quadrature CMOS LC-VCO. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.)

D

C D Q LATCH

Z

U1

C

DETDFF

D1 D2

I Q XOR

D

C

D0

U2 Transition detection U3 D1 L2 D0 D1 VCO I-clock Z

D2

Selector

Data

LATCH D Q C

Q

Q

D Q LATCH

U2

L1 C

D1 C

C

Data

DETDFF

U3

Q

M-DETDFF LATCH D Q C

Q

D1 C

C D Q LATCH

Selector

Data

LATCH D Q C

Selector

U1

VCO Late

PD Q

D2

VCO Q-clock

FIGURE 9.12.5 Phase detector block diagram and timing example for VCO lagging data. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1133

Industry Examples of the State-of-the-Art: IBM

triggered master-slave flip-flops U1, U2, and U3, latches L1 and L2, and a XOR gate, all implemented with ECL logic. U1 samples the incoming data stream on the rising and falling edges of the I clock; similarly, U2 samples the incoming data stream on the rising and falling edges of the Q clock. Depending on the relative phase of the clock with respect to the data, the U1 output will lead or lag the U2 output by 908. U3 samples the output of U2 on every transition of U1. If the U1 output leads the U2 output, on every rising edge of the U1 output, the U2 output will still be low, while on every falling edge of the U1 output, the U2 output will still be high. By inverting either the rising edge or falling edge sampled data (in U3, the rising edge data), therefore, a constant output from U3 will be generated as long as the U1 output leads the U2 output. Similarly, if the U1 output lags the U2 output, U3 will generate a constant output with the opposite polarity of that generated in the lead case. The U3 output thus indicates whether the VCO leads or lags the data (the latter is illustrated in Figure 9.12.5) and can be used to drive the loop into phase lock. Under locked conditions, the Q clock edges will be aligned with the data transitions and the I clock transitions will be centered within the data eye, independent of process, temperature, and supply voltage variation, provided the quadrature relationship between I and Q is robust and the duty cycle distortion in these half-rate clocks is small. Another desirable feature in a phase detector–charge pump combination is the ability to provide correction signals only when transitions in the data have occurred and to produce a tri-state or neutral output otherwise. In this way, loop drift during long runs of consecutive ones or zeros in the input data stream is minimized. In the phase detector described here, the outputs of latches L1 and L2, which are generated 908 out of phase and correspond to the even and odd 1:2 demultiplexed data, are compared in the XOR gate. The XOR output is used in a tri-level logic gate (Figure 9.12.6) to enable the creation of positive, negative, and neutral control signals for the charge pump. When the XOR gate output is 1, a transition has occurred and the normal differential path in the tri-level gate is selected, resulting in a positive or negative differential output signal. When the XOR gate output is 0, however, no transition has occurred and the balanced output path is chosen, resulting in a neutral differential output signal. Receiver Measurement Results The receiver was measured on-wafer and in packaged form using a 43 Gb/sec 231 1 pseudo-random bit sequence (PRBS) input data pattern [7]. Error-free operation (bit error rate [BER] < 10 15) was

From XOR gate

Z ZB OB O

From double edge triggered flip-flop U3

PB PDB

VB VBB VR

subs

FIGURE 9.12.6 Gate generating three-level phase detector final output. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1134

The Silicon Heterostructure Handbook

measured for temperatures from 25 to 1008C and supply voltages from 3.3 to 3.9 V. To evaluate the success of the tri-state feature of the phase detector in enabling the loop to handle long strings of consecutive bits, data patterns including up to 192 consecutive ones or zeros followed by 64 bits of alternating ‘‘10’’ were presented to the receiver at 43 Gb/sec; the receiver was able to recover such patterns without errors. The performance of the Cherry–Hooper input stage was tested by providing low-amplitude single-ended input to the receiver. For a BER < 10 9, less than 40 mV single-ended input was successfully recovered. The VCO lock range within a given band was typically 700 MHz, which, since the VCO is running at half-rate, is equivalent to a data rate range of 1.4 Gb/sec. The overall frequency band over which the CDR was able to operate successfully was 39.5 to 44 Gb/sec. The free-running phase noise of the VCO itself was measured to be 103 dBc/Hz at a 1 MHz offset from a 21.5 GHz operating frequency. VCO temperature sensitivity was less than 1.9 MHz/8C, while VCO supply voltage sensitivity was less than 133 MHz/V. The jitter generation of the recovered clock of interest in SONET repeater applications can be assessed from the phase noise plot (Figure 9.12.7) of a clock-divided-by-2 output of the chip. In the figure, the divided CDR clock output is shown along with the corresponding free-running divided-by-2 output of the VCO and the clock source for the input data, also divided by 2 to match the VCO frequency. The jitter generation was measured by integration over a 10 kHz to 1 GHz bandwidth, resulting in a recovered clock jitter generation as low as 188 fsec rms under typical conditions and less than 230 fsec rms under worst case temperature and supply voltage conditions. This low level of generated jitter validates the design strategy of using coupled LC VCOs combined with band-switching within the VCO. The jitter tolerance of the receiver for SONET compliance would typically be measured by evaluating BER performance of the CDR against input phase modulated with sine jitter of various amplitudes corresponding to a defined jitter mask. When this part was evaluated, integrated test equipment to measure jitter tolerance in this manner did not exist, although some researchers developing alternate receiver chips built a custom test environment to make such measurements [5]. In our testing, tolerance to both sinusoidal and deterministic jitter was measured. In the case of the sinusoidal jitter, however, the

FIGURE 9.12.7 Phase noise performance of reference, free-running VCO, and locked VCO in CDR. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples of the State-of-the-Art: IBM

9.12-1135

modulation bandwidth of the clock source was unfortunately much less than the bandwidth of the PLL, so while the CDR passed the test, this result merely served to verify the tracking capabilities of the PLL. The deterministic jitter testing was done by providing an input data stream that had been passed through a low bandwidth, high loss cable, thus introducing significant input signal degradation. The testing was performed on a CDR–demultiplexer chip packaged on a 1 in. 1.2 in. Arlon substrate with 50 V microstrip transmission lines connected to GPPO connectors within an overall brass housing [24]; an eye diagram of the degraded input and one of the four recovered demultiplexed outputs shown in Figure 9.12.8. The power consumption of the receiver chip was quite low at 2.4 W under nominal operating conditions; the power consumption of similar designs reported in the same time frame as this result in similar or identical technologies was far higher, in part because of more conservative supply voltage and logic family choices made in those implementations [4–6].

40 Gb/sec Transmitter Implementations using Half-Rate and Full-Rate Architectures The function of each of the two transmitter circuits described in this section is to serialize four input parallel data streams, creating a 40 Gb/sec output data stream minimally corrupted by jitter, whether

FIGURE 9.12.8 Receiver 43 Gb/sec input eye diagram (top) and one demultiplexed eye diagram (bottom), triggered with BERT clock. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1136

The Silicon Heterostructure Handbook

random or deterministic. A key question in the implementation of this block is whether or not a full-rate architecture should be used. A full-rate approach enables the use of a baud-rate retiming latch just prior to the output driver, creating a very favorable design point for minimizing deterministic jitter at the cost of a very high-performance latch, the need to generate and distribute a full-rate clock to the full-rate latch, and the requirement that a very precise timing relationship between data and clock for that latch be satisfied. The half-rate approach reduces the stress on technology and timing introduced by the final latching stage while easing the VCO design challenge, at the cost of potential additional deterministic jitter introduced by duty cycle distortion. The technology used for these designs is the same productionlevel 0.18 mm SiGe BiCMOS process as that used for the receiver design. In both the full-rate and halfrate designs, the design target was a combined clock multiplier unit and a 4:1 multiplexer (Figure 9.12.9).

Data input buffers D00 4⫻10.75 Gbs/s Single-ended data input

D10

Data output buffer

4:1 MUX

D01 D11

43 Gb/s Serial output data 4:1 MUX CMU

CLK/2

CLK/8

Divider Clock output buffer Charge pump

Phase/Freq detector

2.6875 GHz Clock

Linear amp Off-chip loop filter

VCO CLK

21.5 GHz

4 External Trim. bits

D0 D1

4:1 Mux

D2

Serial data

D3 Clk/4

Clk/4 Clk/2 Div 2/4

Ref. clk

Clk/4

PFD

Clock distribution and dividers

Charge pump

Amp

Voltage regulator

Lock detect Lock indicator

Clk

Ext. filter

Clk (full rate)

VCO 4 CMU

External frequency band selection

FIGURE 9.12.9 Block diagrams of half-rate (top) and full-rate (bottom) transmitters, each including a clock multiplier unit and a 4:1 multiplexer. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003; M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1137

Industry Examples of the State-of-the-Art: IBM

Half-Rate and Full-Rate Transmitter Designs The half-rate transmitter design features a clock multiplier unit (CMU) generating an output frequency in the 20 to 22 GHz range, supporting 40 to 44 Gb/sec data rates, as well as a multiplexer designed to work with the half-rate clock. A key design decision that must be made is the loop bandwidth of the CMU PLL, if not set by standard requirements. Inside the loop bandwidth, random jitter will be dominated by noise from the reference and subcircuits contributing to in-band noise such as the charge pump, phase-frequency detector, and divider; outside the loop bandwidth, random jitter is dominated by the performance of the VCO. In the half-rate CMU design, the loop bandwidth was set to 3 MHz. The reference multiplication factor chosen for the CMU PLL was 8. As in the case of the 1:4 demultiplexer used in the receiver, the 4:1 multiplexer design was implemented as a stand-alone circuit prior to its inclusion in the transmitter design. A tree architecture with a recursive series of 2:1 multiplexer stages was used for this design (Figure 9.12.10). The stand-alone

D00 2:1 D01

Clock

Output

2:1

l2

Clock/2

D10 2:1 D11

D0

Latch Sel

D2 1

2

1

2

2:1

2

2:1

D3

1

2

1

2

2:1

MS-DFF

2

Clk

2

2 2 2

D1

2

Serial output

908

Clk/4 1

2

l2

50 Ω-drivers

D2

Clk/2

2

2

D0

PI

l2 08

CMU

Ref. 1 Clk

FIGURE 9.12.10 Simplified block diagram of the 4:1 multiplexer as used in the half-rate (top) and full-rate (bottom) transmitter implementations. (From M Meghelli, A Rylyakov, and L Shan. IEEE Journal of Solid-State Circuits 37:1790–1794, 2002; M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1138

The Silicon Heterostructure Handbook

multiplexer takes four parallel single-ended data as input and uses a half-rate clock with internal clock divider to perform input data latching, 4:2 multiplexing, and 2:1 multiplexing. The clock receiver in this multiplexer was designed with a Cherry–Hooper amplifier. The output driver was a critical design as it must support broadband operation up to a bandwidth sufficient for target data rates. The broadband requirement limits the amount of peaking that can be applied to the design problem, while maximizing the output data rate stresses the capabilities of the technology; the driver must operate at the same rate regardless of half-rate or full-rate architecture choice. The output driver was built using a simple differential pair with 50 V termination resistors for impedance matching. The first implementation of this block included series peaking in the termination that created undesirable, jitter-inducing excessive peaking in the driver’s transfer function; the second implementation of this circuit did not include series peaking and worked with very low jitter to far higher data rates than did the first. Feedback emitter resistors were used to reduce output ringing, shunted with a capacitor to enhance bandwidth. The packaged version of the second implementation of this block operated to 70 Gb/sec output data rates, far in excess of the performance required in the 40 Gb/sec transmitter implementation. A subsequent implementation of a half-rate architecture multiplexer implemented in a 0.13 mm SiGe bipolar process was demonstrated with open output data eyes to 132 Gb/sec [8]. In the complete half-rate transmitter implementation, the multiplexer architecture and output driver design were taken from the stand-alone design, with the clock source for the multiplexer block being the output of the CMU. The oscillator in the PLL is a bipolar LC-VCO (Figure 9.12.11), employing a positive feedback cross-coupled differential pair to generate the negative resistance necessary to sustain oscillation. As in the receiver VCO design, a band-switching architecture was used to enable lower VCO gain in the fine tune control loop, thus improving random jitter performance while still supporting a broad tuning range capability via digitally controlled multiple overlapping frequency bands. The phase and frequency detector used in the transmitter is a conventional design built from a NOR gate and two synchronously set, asynchronously reset flip-flops. One of the flip-flops is set by the reference clock, the other by the feedback divider clock, and both are reset by the NOR gate output. In the locked condition, narrow, matched up and down pulses are generated. The NOR gate includes dummy devices that allow the flip-flops to drive nominally identical loads, thus minimizing sources of static phase error from this circuit block. While the full-rate transmitter design retains much of the design used for the half-rate version, significant modifications to key blocks are required. The 4:1 multiplexer block in the full-rate design (Figure 9.12.10) includes a full-rate clock retiming circuit implemented with a master–slave data flipflop. In order to ensure proper operation of the 2:1 selector gate, data retiming latches are used by each 2:1 multiplexing stage to offset the two parallel input data streams with respect to each other by half a bit time. The full-rate clock is generated on-chip by the CMU and is used at that frequency to clock the retiming flip-flop, and at divided frequencies to time the multiplexing operation. In this design, the reference clock was chosen to be the same frequency as that used for the half-rate design, demanding a reference multiplication factor of 16 and thus a divide-by-16 circuit in the CMU loop. A primary benefit in full-rate transmit architectures is the ability to include full-rate retiming of the data just prior to the output driver, but achieving the correct timing relationship between full-rate clock arrival and multiplexed data arrival at the retiming flip-flop data and clock ports is nontrivial. Effectively, the sum of the propagation delay of the first divide by two circuit plus the propagation delay of the last 2:1 multiplexer stage should be less than one full-rate clock period, which is less than 24 psec at a data rate of 43 Gb/sec. The clock phase margin requirements of the retiming flip-flop further erode the available time. To ease this problem, the full-rate design implemented here (Figure 9.12.10) introduces a block which interpolates between the 08 and 908 outputs of the first divider stage, with the interpolator output used to drive the multiplexing tree. In this way, the data phase can be moved over 908 of half-rate clock phase, corresponding to 1808 of full-rate clock phase. Control of the interpolator setting will thus enable the establishment of an optimal timing relationship between the multiplexed data and the full-rate clock at the retiming flop-flop inputs. Because this approach allows phase adjustment in the less power-hungry and less technology-stressful half-rate clock domain, it was chosen

© 2006 by Taylor & Francis Group, LLC

9.12-1139

Industry Examples of the State-of-the-Art: IBM

bit n 4 bits bits 0

Vcc Vvar Vout

Vout

V bias

FIGURE 9.12.11 VCOs used in half-rate (top) and full-rate (bottom) transmitter implementations. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003; M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.)

over alternatives [25] that use extra delay stages operating at the full clock and data rates to establish appropriate timing. The second circuit for which significant changes were required by the full-rate architecture as compared to the half-rate one is, of course, the VCO. The cross-coupled HBT-based VCO used in the half-rate design was replaced by a differential bipolar LC-VCO based on the Colpitts architecture in the full-rate VCO design (Figure 9.12.11). Varactors for band switching (not shown in the figure) and finetuning in this design are composed of nFETs operated in inversion mode. A key consideration in the half-rate versus full-rate decision is that if the phase noise performance of the VCO degrades by more than 6 dB as compared to the half-rate VCO, the RJ performance of the full-rate design will not be able to match that of the half-rate design. This is a difficult challenge to meet as the Q factor of the varactors available in a given technology tend to degrade significantly as the frequency increases from that required for half-rate to that required for full-rate. Because the 4 MHz PLL bandwidth of the full-rate design is similar to the 3 MHz PLL bandwidth of the half-rate design (while the feedback divider value is

© 2006 by Taylor & Francis Group, LLC

9.12-1140

The Silicon Heterostructure Handbook

doubled), the in-band phase noise performance of the full-rate PLL must match or exceed that of the half-rate PLL to maintain in-band RJ performance. Measurement Results from Half-Rate and Full-Rate Transmitters The half-rate design was measured on-wafer and in packaged form, using parallel 10.75 Gb/sec 231 1 PRBS inputs and a 2.6875 GHz reference clock, yielding error-free operation (BER < 10 15) measured at the multiplexer serial output port at temperatures to 1008C over supply voltages ranging from 3.3 to 3.9 V. The full-rate design was measured only on-wafer under similar conditions, but above 508C the on-chip divider began to fail at the high end of the VCO tuning range. Half-rate and full-rate implementations of the stand-alone multiplexer block show the same qualitative behavior; at 1008C, the half-rate multiplexer ran to 60 Gb/sec output data rates as compared to 44 Gb/sec output data rates for the full-rate design. The tuning range of the PLL in the half-rate design was 20.2 to 22 GHz, whereas that of the full-rate design was 41.8 to 45.8 GHz. While neither implementation succeeded in covering the target frequency range exactly in hardware, no problem is anticipated in achieving this range from a theoretical perspective for either architecture choice. The phase noise of the full-rate VCO is significantly degraded as compared to that of the half-rate design (Figure 9.12.12), a performance decline of 14 dB, 8 dB in excess of the 6 dB budget that would enable similar phase noise performance between the half- and fullrate VCOs. As a result, the 260 fsec rms measured jitter integrated over a 10 kHz to 1 GHz bandwidth for the full-rate CMU is far greater than the 140 fsec rms value achieved by the half-rate design. Recall that a key reason for pursuing a full-rate design was the opportunity to reduce duty cycle distortion. In the output eye diagrams (Figure 9.12.13), this benefit, as well as a reduction in the clock feed through, is clearly visible, although the half-rate design’s performance still yields wide open data eyes with a signal-to-noise ratio greater than 12. The price for this benefit is high, however; in addition to the reduced robustness over temperature and generated jitter performance, the power consumption of the full-rate design was 2.31 W as compared to an expected 1.61 W for a half-rate design using logic gates powered commensurately with those used in the full-rate design (the actual half-rate design, done first, conservatively used higher power per logic gate targeting operation at a given data rate than the subsequent full-rate design), with much of the extra full-rate power absorbed in the added current needed for clock distribution and first two divider stages. In our estimation, the half-rate architecture represents the best compromise for 40 Gb/sec transmitter serializers implemented in the 0.18 mm technology used for this design. A performance summary of the two transmitters is provided in Table 9.12.1. Die photos of the three designs discussed in this chapter can be found in Figure 9.12.14.

9.12.3

Summary

In this chapter, we presented a brief overview of an optical data link at 40 Gb/sec and then focused on the high-speed serializer and deserializer circuitry components of such a link implemented in a 0.13 mm

TABLE 9.12.1 Performance Summary for Half-Rate and Full-Rate Transmitter Implementations Measured Key Parameter

Full-Rate Tx

Half-Rate Tx [8]

Nominal data rate Clock rms jitter generation Data jitter Data SNR Data duty cycle distortion Free-running VCO phase noise Maximum chip temperature Supply voltage

41.8 to 45.8 Gb/sec 260 fsec 600 fsec rms, 4.6 psec pp 12.3 1.4% 98 dBc/Hz at 1 MHz, 10.75 GHz 508C 3.3 to 3.9 V

40.5 to 44 Gb/sec 140 fsec 540 fsec rms, 3.4 psec pp 12.7 2.3% 100 dBc/Hz at 1 MHz, 21.5 GHz 1008C 3.3 to 3.9 V

Source: From M Meghelli. A 43 Gb/s full-rate clock transmitter in 0.18 mm SiGe BiCMOS technology. IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With Permission.

© 2006 by Taylor & Francis Group, LLC

9.12-1141

Industry Examples of the State-of-the-Art: IBM

FIGURE 9.12.12 Phase noise plots for half-rate (top) and full-rate (bottom) transmitter implementations. (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003; M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.)

Full-rate clock design

100 mV/div

Half-rate clock design

5 ps/div

FIGURE 9.12.13 Output eye diagrams from full-rate (left) and half-rate (right) transmitter implementations. (From M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.12-1142

The Silicon Heterostructure Handbook

Limiting Amp. 2:4 DMUX

Phase Detector

VCO

Loop Filter Capacitor

VCO

PFD/CP

Divider

4:1 MUX

Serial output

Ref Clk

Clock distribution

VCO

Clk/4

PLL 4:1 MUX

D3

D1

D0

D2

FIGURE 9.12.14 Die photos of the receiver (top), the half-rate transmitter implementation (middle), and the fullrate transmitter implementation (bottom). (From M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003; M Meghelli. A IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. With permission.) © 2006 by Taylor & Francis Group, LLC

Industry Examples of the State-of-the-Art: IBM

9.12-1143

SiGe BiCMOS process. Design details for a half-rate receiver–demultiplexer as well as half-rate and full-rate transmitter–multiplexer were presented, including key performance metrics, circuit approaches, and hardware results. In order to develop the high speed, relatively complex designs described in this chapter, we first implemented and validated key smaller high-speed pieces of the design, specifically, the 1:4 demultiplexer and the 4:1 multiplexer. This approach enabled us to correlate hardware performance against models, identify and correct unexpected problems, and was critical in the success achieved in the first-pass designs of the full receiver and transmitters presented here. In addition, because they could be clocked from an external source, these blocks allowed us to explore technology performance limits more effectively than was possible in the complete transmitter and receiver designs. The half-rate receive architecture achieved excellent jitter generation and tolerance performance at very low power, validating supply voltage, architecture, and building block choices for such designs. The full-rate and half-rate architecture transmitter designs also achieved excellent jitter generation at low power, with the realized expected duty cycle distortion improvement from the full-rate design outweighed by its degraded phase noise performance and narrower range of operating temperature as compared to the half-rate design. These design examples explore circuit and architectural tradeoffs in high-speed serializer and deserializer design. Ultimately, the results achieved in this work confirm the viability of half-rate architectural approaches for 40 Gb/sec serializer and deserializer design in technologies with device performance like that of the chosen technology.

Acknowledgments The authors would like to acknowledge the SiGe technology group of IBM Microelectronics for the fabrication of all chips described in this chapter. The authors would also like to thank Alexander Rylyakov, Michael Sorna, Steven Zier, Lei Shan, Mehmet Soyuer, and Modest Oprysko for their contributions and support.

References 1. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Alhgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC-compatible CMOS using copper interconnect. IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2001, pp. 143–146. 2. A Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — Expanding the horizons of SiGe BiCMOS. International SolidState Circuits Conference Technical Digest of Papers, 2002, pp. 181–182. 3. M Reinhold, C Dorschky, E Rose, R Pullela, P Mayer, F Kunz, Y Baeyens, T Link, and J-P Mattia. A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology. IEEE Journal of Solid-State Circuits 36:1937–1944, 2001. 4. A Ong, S Benyamin, V Condito, Q Lee, J-P Mattia, D Shaeffer, A Shahani, X Si, H Tao, M Tarsia, W Wong, and M Xu. A 40–43 Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology. IEEE Journal of Solid-State Circuits 38:2155–2168, 2003. 5. D Shaeffer, H Tao, Q Lee, A Ong, V Condito, S Benyamin, W Wong, X Si, S Kudszus, and M Tarsia. 40/43 Gb/sec SONET OC-768 SiGe 4:1 MUX/CMU chipset with SFI-5 compliance. IEEE Journal of Solid-State Circuits 38:2169–2180, 2003. 6. A Koyama, T Harada, H Yamashita, R Takeyari, N Shiramizu, K Ishakawa, M Ito, S Suzuki, T Yamashita, S Yabuki, H Ando, T Aida, K Watanabe, K Ohhata, S Takeuchi, H Chiba, A Ito, H Yoshioka, A Kubota, T Takahashi, and H Nii. 43 Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology. International Solid-State Circuits Conference Technical Digest of Papers, 2003, pp. 232–233.

© 2006 by Taylor & Francis Group, LLC

9.12-1144

The Silicon Heterostructure Handbook

7. M Meghelli, A Rylyakov, S Zier, M Sorna, and D Friedman. A 0.18-mm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. IEEE Journal of Solid-State Circuits 38:2147–2154, 2003. 8. M Meghelli. A 108 Gb/s 4:1 multiplexer in 0.13 mm SiGe-bipolar technology. International SolidState Circuits Conference Technical Digest of Papers, 2004, pp. 236–237. 9. M Meghelli, A Rylyakov, and L Shan. A 50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems. IEEE Journal of Solid-State Circuits 37:1790–1794, 2002. 10. M Meghelli. A 43 Gb/s full-rate clock transmitter in 0.18 mm SiGe BiCMOS technology. IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2004, pp. 289–292. 11. H Rein and M Moller. Design considerations for very-high-speed Si-Bipolar IC’s operating up to 50 Gb/s. IEEE Journal of Solid-State Circuits 31:1076–1090, 1996. 12. A Rylyakov. A 51 GHz master-slave latch and static frequency divider in 0.18 mm SiGe BiCMOS. IEEE Proceedings of the Bipolar Circuits and Technology Meeting, 2003, pp. 75–77. 13. A Rylyakov, L Klapproth, B Jagannathan, and G Freeman. 100 GHz dynamic frequency divider in SiGe bipolar technology. Electronics Letters 39:217–218, 2003. 14. Y Suzuki, Y Amamiya, Z Yamazaki, S Wada, H Uchida, C Kurioka, S Tanaka, and H Hida. 110 Gb/s multiplexing and demultiplexing ICs. International Solid-State Circuits Conference Technical Digest of Papers, 2004, pp. 232–233. 15. T Suzuki, T Takahashi, K Makiyama, K Sawada, Y Nakasha, T Hirose, and M Takikawa. Under 0.5 W 50 Gb/s full-rate 4:1 MUX and 1:4 DEMUX in 0.13 mm InP HEMT technology. International SolidState Circuits Conference Technical Digest of Papers, 2004, pp. 234–235. 16. T Yamamoto, KM Horinaka, D Yamazaki, H Nomura, K Hashimoto, and H Onodera. A 43 Gb/s 2:1 selector IC in 90nm CMOS technology. International Solid-State Circuits Conference Technical Digest of Papers, 2004, pp. 236–237. 17. A Felder, M Moller, M Wurzer, M Rest, T Meister, and H Rein. 60 Gbit/s regenerating demultiplexer in SiGe bipolar technology. Electronics Letters 33:1984–1985, 1997. 18. M Muller, H Rein, A Felder, and T Meister. 60 Gb/s time-division multiplexer in SiGe bipolar technology with special regard to mounting and measuring technique. Electronics Letters 33:679– 680, 1997. 19. E Cherry and D Hooper. The design of wide-band transistor feedback amplifiers. Proceedings of the IEEE 110:375–389, 1963. 20. M Meghelli, B Parker, H Ainspan, and M Soyuer. SiGe BiCMOS 3.3 V clock and data recovery circuits for 10 Gb/s serial transmission systems. International Solid-State Circuits Conference Digest of Technical Papers, 2000, pp. 56–57. 21. D Friedman, M Meghelli, B Parker, J Yang, H Ainspan, and M Soyuer. A single-chip 12.5 Gbaud transceiver for serial data communication. IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 145–148. 22. A Rofougaran, J Rael, M Rofougaran, and A Abidi. A 900 MHz CMOS LC oscillator with quadrature outputs. International Solid-State Circuits Conference Digest of Technical Papers, 1996, pp. 392– 393. 23. R Walker, C Stout, and C-S Yen. A 2.488 Gb/s Si bipolar clock and data recovery IC with robust loss of signal detection. International Solid-State Circuits Conference Digest of Technical Papers, 1997, pp. 246–247. 24. L Shan, M Meghelli, J Kim, and J Trewhella. Millimeter wave package design: a comparison of simulation and measurement results. IEEE 10th Topical Meeting on Electrical Performance of Electrical Packaging, 2001, pp. 29–34. 25. Y Nakasha, T Suzuki, H Kano, A Ohya, K Sawada, K Makiyama, T Takahashi, M Nishi, T Hirose, M Takikawa, and Y Watanabe. A 43 Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology. International Solid-State Circuits Conference Digest of Technical Papers, 2002, pp. 190–191.

© 2006 by Taylor & Francis Group, LLC

9.13 Industry Examples at the State-of-the-Art: Hitachi 9.13.1 9.13.2

Introduction......................................................... 9.13-1145 IC and LSI for Optical Transmission Systems.. 9.13-1145 IC Chipset and LSIs for 40-Gb/s Optical-Fiber-Links . Single-Chip 10 Gb/s Transceiver LSI

9.13.3

Frequency-Divider ICs . 5.8-GHz ElectronicToll-Collection Transceiver IC . Other ICs

Katsuyoshi Washio 9.13.4

Hitachi, Ltd.

9.13.1.

IC for Wireless Communication Systems ......... 9.13-1148 Summary .............................................................. 9.13-1152

Introduction

High-speed monolithic integrated circuits (ICs) and large-scale ICs (LSIs) are the key components for multi-gigabit data communication systems and wide-bandwidth radio communication systems. These systems include backbone networks, intercity communication networks, local area networks, and Ethernet for data communications, and microwave and millimeter-wave mobile networks, fixed wireless access (FWA), and intelligent transport systems (ITS) for radio communications. As applications of the SiGe HBT and BiCMOS technologies described in Chapter 3.7, an IC chipset and LSIs for 40-Gb/s optical-fiber links, a single-chip 10-Gb/s transceiver LSI, frequency-divider ICs, a 5.8-GHz electronictoll-collection (ETC) transceiver IC, and other ICs that are applicable to optical transmission and microwave/millimeter-wave wireless communication systems have been implemented.

9.13.2.

IC and LSI for Optical Transmission Systems

IC Chipset and LSIs for 40-Gb/s Optical-Fiber-Links To meet the demand for an expansion of the transmission capacity that accompanies the rapid growth of multimedia communications, the development of a 40 Gb/s optical transmission system for backbone networks is an effective solution. The IC chipset should be capable of operation at up to about 50 Gb/s or 50 GHz for practical use; it must also be sufficiently inexpensive to receive widespread commercial approval. The SiGe HBT can therefore be considered a promising candidate. Several ICs for 40 Gb/s optical-fiber-link communication systems have been developed by using self-aligned SEG SiGe HBTs [1–4]. A block diagram of a transmitter and a receiver built with the fabricated IC chipset for 40 Gb/s optical-fiber-link communication systems is shown in Figure 9.13.1. The IC chipset includes a 4:1 multiplexer in the transmitter, and a transimpedance preamplifier, an automatic gain-control (AGC) amplifier, a full-wave rectifier, a limiting amplifier, and a 1:4 demultiplexer with a decision circuit in the 9.13-1145 © 2006 by Taylor & Francis Group, LLC

9.13-1146

The Silicon Heterostructure Handbook

Transmitter 1

10 Gb/s

4:1 multiplexer

LD Optical fiber

2

40 Gb/s

3

Driver IC

Modulator 40 Gb/s

4 1

40 Gb/s PD

2

Filter

10 Gb/s

Preamplifier

AGC amplifier

Receiver

Full-wave rectifier

3

40 GHz 1:4 demultiplexer

Limiting amplifier

4

FIGURE 9.13.1 Block diagram of a transmitter and a receiver built with the IC chipset fabricated by using selfaligned SEG SiGe HBTs. The system is for 40-Gb/s optical-fiber-link communication systems. The IC chipset includes a 4:1 multiplexer in the transmitter, and a transimpedance preamplifier, an automatic gain-control (AGC) amplifier, a full-wave rectifier, a limiting amplifier, and a 1:4 demultiplexer with a decision circuit in the receiver. (From K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.) Data input buf. 2:1 MUX (M1) Di0 D1 Q Di2 D2 C

Di1 Di3

2:1 MUX (M2) D1 Q D2 C

1/4 clock

2:1 MUX (M3) D1 Q D2 C

Output buffer

Dout/Dout

Internal clock buffer MS-TFF Q C

Clock output buffer

MS-DFF D Q C

MS-TFF Q C

Clock Clock buffer

FIGURE 9.13.2 Block diagram of a 4:1 multiplexer. (From T. Masuda, K. Ohhata, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, H. Shimamoto, M. Kondo, T. Harada, and K. Washio. 40 Gb/s 4:1 multiplexer and 1:4 demultiplexer IC module using SiGe HBTs. Digest of the IEEE International Microwave Symposium, Phoenix, 2001, pp. 1697–1700. With permission.)

receiver. The block diagram of the 4:1 mutiplexer (4:1 MUX) is shown in Figure 9.13.2. The 2:1 multiplexer (2:1 MUX), the core circuit of the 4:1 MUX, is designed to maximize the phase margin between the input data transitions and the select clock. The 4:1 MUX consists of three 2:1 MUXs connected in a tree structure, an output master–slave delayed flip-flop (MS-DFF), an output

© 2006 by Taylor & Francis Group, LLC

9.13-1147

Industry Examples at the State-of-the-Art: Hitachi

(a) 400 mV

25 psec (b) 400 mV

20 psec

FIGURE 9.13.3 Output waveform of a 4:1 multiplexer at (a) 40 Gb/s and (b) 50 Gb/s. (From T. Masuda, K. Ohhata, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, H. Shimamoto, M. Kondo, T. Harada, and K. Washio. 40 Gb/s 4:1 multiplexer and 1:4 demultiplexer IC module using SiGe HBTs. Digest of the IEEE International Microwave Symposium, Phoenix, 2001, pp. 1697–1700. With permission.)

TABLE 9.13.1 Performance of the IC Chipset for 40 Gb/s Optical-Fiber-Link Communication Systems Developed by Using Self-Aligned SEG SiGe HBTs. IC

Performance

Remarks

Multiplexer Preamplifier AGC amplifier Limiting amplifier Full-wave rectifier Demultiplexer

>50 Gb/s (probe), 48 Gb/s (module) 45 GHz, 50 dBV 48 GHz, 0.5–21.5 dB 32 dB, 500 mVpp @ 40 GHz 90 mVpp (filter output) @ 40 GHz 48 Gb/s (probe), 45 Gb/s (module)

4:1, full-rate Cin ¼ 0.1 pF 40 Gb/s (module) BW ¼ 49 GHz 1:4, full-rate

Source: From K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.

buffer, and two master–slave toggle flip-flops (MS-TFFs) in series. The output eye diagrams of the 4:1 MUX IC for a 40-Gb/s and a 50-Gb/s pseudorandom bit sequence (PRBS) measured on-wafer probes are shown in Figure 9.13.3. Well-opened eye diagrams with output voltage swing of 400 mVpp were obtained. The performance of the IC chipset is summarized in Table 9.13.1. These excellent results indicate that the self-aligned SEG SiGe HBT technology, which offers high reliability and cost-effectiveness, will play an important role in optical-fiber-link systems, operating at a data rate of 40 Gb/s, for global communications. To meet recent demand for high functionality, 43-Gb/s full-rate-clock 16:1 MUX and 1:16 DEMUX LSIs with a Serdes Framer Interface Level 5 (SFI-5) interface [6], and a fully integrated 39.8 to 43-Gb/s 16:1 MUX and 1:16 DEMUX chipset [7], have been developed.

Single-Chip 10 Gb/s Transceiver LSI Optical transmissions at a data rate of 10 Gb/s are the highest serial data links commercially available for use in backbone networks, and are expected as candidates for use in the next generation of Ethernet, local area networks, and intercity communication networks for data communication. The demand for low-cost, high-productivity, small physical structure, and low power dissipation is therefore very strong.

© 2006 by Taylor & Francis Group, LLC

9.13-1148

The Silicon Heterostructure Handbook

FIGURE 9.13.4 Photomicrograph and rough block diagram of a single-chip 10-Gb/s transceiver LSI developed by using the SiGe BiCMOS technology. A 1:16 DEMUX (demultiplexer) and a CDR (clock and data recovery) circuit in the receiver, a 4-bit 16-channel data input FIFO (fast-in fast-out) memory, a 16:1 MUX (multiplexer), and a 10-GHz PLL circuit with a 155-MHz external voltage control oscillator (VCO) control circuit in the transmitter, and a 231-1 pseudorandom bit sequence (PRBS) generator and an error detector for self-testing are all integrated in a single chip. (From S. Ueno, K. Watanabe, T. Kato, T. Shinohara, K. Mikami, T. Hashimoto, A. Takai, K. Washio, R. Takeyari, and T. Harada. Single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2001, pp. 82–83. With permission.)

The SiGe BiCMOS technology can be used to provide high-speed and sophisticated-function system LSIs at low power because of its combination of high-fT and fmax SiGe HBTs and highly integrated CMOS. A photomicrograph and rough block diagram of a single-chip 10-Gb/s transceiver LSI developed by using SiGe BiCMOS technology are shown in Figure 9.13.4 [5]. This all-in-one transceiver LSI integrates: a 1:16 DEMUX (demultiplexer) and a clock and data recovery (CDR) circuit in the receiver; a 4-bit 16-channel data input fast-in fast-out (FIFO) memory, a 16:1 MUX (multiplexer), and a 10-GHz phase-locked loop (PLL) circuit with a 155-MHz external voltage control oscillator (VCO) control circuit in the transmitter; and a 231-1 PRBS generator and an error detector for self-testing. It occupies an area of 5.6 5.3 mm and contains 26,000 active elements, i.e., 16,000 SiGe HBTs and 10,000 CMOS transistors. CMOS transistors are used for the interfaces and test circuit to get the best characteristics in terms of operation at low supply voltage for low power consumption. This chip demonstrates that SiGe BiCMOS is a suitable technology for producing high-level integrated system LSIs to be used in optical transmission networks.

9.13.3

IC for Wireless Communication Systems

Frequency-Divider ICs To satisfy the explosively growing demand for wide-bandwidth radio communication systems that accompany the availability of large-bandwidth spectra and the allocation of such frequency bands for commercial use, the development of monolithic millimeter-wave ICs has been advancing rapidly. Such systems include wireless local area networks (WLAN), local multiple-distribution services (LMDS), and consumer radar systems (automotive radars). Here, the availability and ease of use of low-cost monolithic ICs are essential for the penetration of millimeter-wave systems into the fields of consumer and commercial electronics. The high-speed frequency divider (FD) is a key circuit for many applications. Two types of FD ICs have been developed by using self-aligned SEG SiGe HBTs [8–11]. The circuits are a 1/4 pre-tracking static FD and a 1/4 dynamic FD (DFD), and have respective maximum operating

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Hitachi

9.13-1149

Int. buffer

Dynamic TFF

Input buffer

frequencies of 81 and 92.4 GHz. Chip micrographs of the DFD, zooming in to the main circuit region in two steps, are shown in Figure 9.13.5. It consists of a 50-V-terminated three-emitter–follower input buffer, a dynamic toggle flip-flop (D-TFF) based on the regenerative frequency division principle as the first divide-by-two stage, a static MS-TFF as the second divide-by-two stage, internal buffers to reform the output signal of each TFF, and an output buffer driving 50-V lines. The internal single-ended voltage swing for the D-TFF was designed to be 500 mV, which was optimized by taking into account the gain cutoff frequency of a Gilbert multiplier. The single-ended voltage swing of the MS-TFF is 250 mV. To increase the operating speed, two emitter followers were used and the emitter size of each emitter follower transistor was optimized to reduce the loading of the flip-flops. An input sensitivity of the DFD max up to 92.4 GHz is shown in Figure 9.13.6(a). The operational bandwidth of the dynamic FD for f toggle was a broad 57 GHz (35–92 GHz) without tuning. Figure 9.13.6(b) shows the 23.1 GHz divided-by-four

Master−slave TFF

Output buffer

IN

OUT MIM capacitors

FIGURE 9.13.5 Chip micrographs of the 1/4 dynamic frequency divider, zooming in to the main circuit region in two steps. The DC bias terminals are connected via MIM capacitors to obtain a stable voltage supply. The area of the D-TFF is 40 50 mm, and that of the main circuit region is 420 150 mm. (From K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Harada, and M. Kondo, 82 GHz dynamic frequency divider in 5.5 ps ECL SiGe HBTs. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 210–211. With permission.)

© 2006 by Taylor & Francis Group, LLC

FIGURE 9.13.6 (a) Input sensitivity of the 1/4 dynamic frequency divider up to its maximum operating frequency of 92.4 GHz. (b) The 23.1-GHz divided-byfour output waveform for a 92.4-GHz input. (From K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, and H. Shimamoto. Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic Frequency Dividers. IEEE Trans. Electron Devices 49:1755–1760, 2002. With permission.)

9.13-1150

The Silicon Heterostructure Handbook

output waveform for a 92.4 GHz input to the dynamic FD. These results indicate that this SiGe HBT technology will play an important role in the monolithic millimeter-wave communication systems of the near future.

5.8-GHz Electronic-Toll-Collection Transceiver IC High-performance wireless communication systems in the 5-GHz band, such as FWA, microwave mobile networks, and ITS, have become increasingly popular. For these systems to enter commercial service, the necessary items of equipment must be small and cheap. When several separate chips are used to implement a necessary operation, extra space and cost for assembly is incurred, so a fully integrated single-chip solution is most desirable. A single-chip 5.8-GHz ETC transceiver IC has been developed by using the SiGe BiCMOS technology as a demonstrator for 5-GHz wireless communication systems [12]. A chip photomicrograph is shown in Figure 9.13.7; the chip occupies an area of 2.65 2.5 mm. This fully integrated ETC chip consists of four blocks, i.e., a receiver (RX), a demodulator (DEMO), a PLL, and a transmitter (TX). The chip includes a matching network circuit (MC), a low-noise amplifier (LNA), a down-conversion mixer, and RF detector circuits for the RX, a received signal strength indicator (RSSI) circuit and an amplitude-shift-keying (ASK) demodulator for the DEMO, a varactortuned LC-VCO and a synthesizer for the PLL, and a modulator, a variable-gain amplifier (VGA), and power amplifier (PA) for the TX (Figure 9.13.8). The receiver transfer characteristic is shown in Figure 9.13.9. The receiver is composed of an LC-matching circuit, two-stage LNAs, and a Gilbert-type doublebalanced mixer. The load resistance is 1 kV, equal to input impedance of an external band-pass filter. The single-ended gain, the input 1-dB compression point, and the double-side-band noise figure were 31 dB, 40 dBm, and 8 dB, respectively. The 54 dBm local oscillation signal leakage at RF input terminal is attributed to low parasitic capacitance of SiGe HBT. The input VSWR of 1.2 at 5.835 GHz results from well-matched MC considering the parasitic effect of bond-wire and the package. This transceiver chip is intended for use in ETC systems, but all of the circuits and the implementation technique have many other potential applications. The good measurement results for the IC in a plastic package indicate the suitability of SiGe BiCMOS as the base technology of single-chip transceiver ICs for 5-GHz-band wireless communication systems.

FIGURE 9.13.7 Chip photomicrograph of a single-chip 5.8-GHz electronic-toll-collection (ETC) transceiver IC using SiGe BiCMOS technology. This fully integrated ETC chip consists of four blocks: a receiver (RX), a demodulator (DEMO), a phase-locked loop (PLL), and a transmitter (TX). (From T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, and K. Washio. Singlechip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 96–97. With permission.)

© 2006 by Taylor & Francis Group, LLC

9.13-1151

Industry Examples at the State-of-the-Art: Hitachi

RSSI out

RF-DET IF BPF out RSSI DET

RFDET

ANT RFin

RSSI Peak Peak hold

RSSI

ASK demodulator

ASKDemo out

MC LNA

TX/RX SW TXout Vcc Gnd

PD

Vcs

Charge pump

Mode control circuit TX/RX

Swallow counter

VCNT

PA

(3.0 V)

Prescaler

LC-VCO

VGA

Standby Baseband data

REFcounter

Control data generator

BPF

PLL control signal

XOSC

Lock-DET out

LPF

FIGURE 9.13.8 Block diagram of a single-chip 5.8-GHz ETC transceiver IC. (From T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, and K. Washio. Singlechip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 96–97. With permission.) 0

IF output power (dBm)

−10 −20 −30 LO

−40 RFin

−50 −60 −70

MC LNA

−60

IFout Rload (1 kΩ)

−50 −40 −30 RF input power (dBm)

−20

FIGURE 9.13.9 Receiver transfer characteristics of a single-chip 5.8-GHz ETC transceiver IC. (From T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, and K. Washio. Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 96–97. With permission.)

Other ICs A PA IC for wideband code-division multiaccess (WCDMA) modulation cellular phone systems has been developed [13]. By optimizing total emitter area, this PA exhibited 44% power-added efficiency and 27.3-dBm output power with an adjacent-channel power ratio of less than 40 dBc at 1.95 GHz and 3.4-V bias voltage.

© 2006 by Taylor & Francis Group, LLC

9.13-1152

The Silicon Heterostructure Handbook

Two other microwave/millimeter-wave ICs have been developed for wireless applications, specifically microwave link, WLAN, and radar systems. These ICs again demonstrated the strong potential and suitability of self-aligned SEG SiGe HBT. One is a one-dimensional travelling-wave amplifier (TWA) with a bandwidth extending into the millimeter-wave region [14]. This TWA exhibited a bandwidth of about 67 GHz with a gain of 6 dB. The chip occupies approximately an area of 1 1 mm and consumes 23 mA at a supply voltage of 3.3 V. The other is a LNA for operation in the 23-GHz band [15]. The LNA exhibited a gain of 21 dB and noise figure of 4.1 dB at 23 GHz, and consumed 20 mA at a 2.5-V single supply voltage.

9.13.4

Summary

An IC chipset and LSIs for 40-Gb/s optical-fiber-links, a single-chip 10-Gb/s transceiver LSI, frequencydivider ICs, a 5.8-GHz ETC transceiver IC, and other ICs have been implemented by applying the SiGe HBT and BiCMOS technologies.

Acknowledgments The author would like to express his sincere thanks to Dr. A. Anzai and Dr. Y. Hatta at the Hitachi Device Development Center (HDDC), and Dr. O. Kanehisa, Dr. K. Seki, and K. Kimura at the Hitachi Central Research Laboratory (HCRL) for their encouragement. The author would also like to express his sincere thanks to T. Masuda, Dr. K. Ohhata, N. Shiramizu, F. Arakawa, T. Nakamura, Dr. M. Kondo, R. Hayami, R. Takeyari at HCRL, and to T. Harada, K. Mikami, S. Ueno, A. Koyama, K. Watanabe at HDDC, to T. Nagashima at Hitachi Digital Media Systems R&D Division, and to Dr. M. Mokhtari, Dr. Y. Li, Dr. B. Hansson, and Dr. T. Lewin at Ericsson Microwave Systems for their extensive contributions throughout this work.

References 1. T. Masuda, K. Ohhata, F. Arakawa, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, M. Kondo, T. Harada, and K. Washio: 45 GHz transimpedance 32 dB limiting amplifier and 40 Gb/s 1:4 high-sensitivity demultiplexer with decision circuit using SiGe HBTs for 40 Gb/s optical receiver. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 60–61. 2. K. Ohhata, F. Arakawa, T. Masuda, N. Shiramizu, and K. Washio: 40-Gb/s analog IC chipset for optical receivers — AGC amplifier, full-wave rectifier and decision circuit — implemented using self-aligned SiGe HBTs. Digest of the IEEE International Microwave Symposium, Phoenix, 2001, pp. 1701–1704. 3. T. Masuda, K. Ohhata, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, H. Shimamoto, M. Kondo, T. Harada, and K. Washio. 40 Gb/s 4:1 multiplexer and 1:4 demultiplexer IC module using SiGe HBTs. Digest of the IEEE International Microwave Symposium, Phoenix, 2001, pp. 1697–1700. 4. K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. 5. S. Ueno, K. Watanabe, T. Kato, T. Shinohara, K. Mikami, T. Hashimoto, A. Takai, K. Washio, R. Takeyari, and T. Harada. Single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2001, pp. 82–83. 6. A. Koyama, T. Harada, H. Yamashita, R. Taketari, N. Shiramizu, K. Ishikawa, M. Ito, S. Suzuki, T. Yamashita, S. Yabuki, H. Ando, T. Aida, K. Watanabe, K. Ohhata, S. Takeuchi, H. Chiba, A. Ito, H. Yoshioka, A. Kubota, T. Takahashi, and H. Nii. 43 Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2003, pp. 232–233.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Hitachi

9.13-1153

7. K. Watanabe, A. Koyama, T. Harada, R. Sotomura, T. Aida, A. Ito, T. Murata, H. Yoshioka, M. Sonehara, H. Yamashita, K. Ishikawa, M. Ito, N. Shiramizu, T. Nakamura, K. Ohhata, F. Arakawa, T. Kusunoki, H. Chiba, T. Kurihara, and M. Kuraishi. A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp. 166–167. 8. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Harada, and M. Kondo, 82 GHz dynamic frequency divider in 5.5 ps ECL SiGe HBTs. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 210–211. 9. K. Washio, R. Hayami, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, and M. Kondo. 67-GHz static frequency divider using 0.2-mm self-aligned SiGe HBTs. IEEE Trans. Microwave Theory Tech. 49: 31– 34, 2000. 10. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, and H. Shimamoto. Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic Frequency Dividers. IEEE Trans. Electron Devices 49:1755–1760, 2002. 11. K. Washio, E. Ohue, R. Hayami, A. Kodama, H. Shimamoto, M. Miura, K. Oda, I. Suzumura, T. Tominari, and T. Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Trans. Electron Devices 50:2417–2424, 2003. 12. T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, and K. Washio. Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 96–97. 13. M. Kondo, I. Miyashita, M. Koshimizu, Y. Kagotoshi, H. Nagai, and K. Washio. High-efficiency power characteristics for WCDMA applications of SiGe HBT devices using a novel form of base-bias resistance. Digest of the IEEE International Microwave Symposium, Philadelphia, 2003, pp. 2205– 2208. 14. B. Kerzar, M. Mokhtari, Y. Li, B. Hansson, K. Washio, T. Harada, and T. Lewin. Millimeter-wave bandwidth, SiGe-HBT travelling wave amplifier. Technical Digest of the IEEE Gallium Arsenide Integrated Circuit Symposium, Seattle, 2000, pp. 57–59. 15. G. Schuppener, T. Harada, and Y. Li. A 23-GHz low-noise amplifier in SiGe heterojunction bipolar technology. Digest of the IEEE Radio Frequency Integrated Circuits Symposium, Phoenix, 2001, pp. 177–180.

© 2006 by Taylor & Francis Group, LLC

9.14 Industry Examples at the State-of-the-Art: ST 9.14.1 9.14.2 9.14.3 9.14.4 9.14.5

Didier Belot ST Microelectronics

9.14.6 9.14.7 9.14.8 9.14.9 9.14.10 9.14.11 9.14.12

Introduction....................................................... 9.14-1155 Process Definition ............................................. 9.14-1157 Switched Gain LNA Implementation .............. 9.14-1160 Down Mixers and PMA Implementation ................................................. 9.14-1162 Variable Gain Amplifier (VGA) and Low-Pass Filter (LPF) ....................................... 9.14-1164 LNA-Mixer Isolation Strategy .......................... 9.14-1166 Receiver Implementation.................................. 9.14-1167 Validation Strategy ............................................ 9.14-1167 RF and Analog Blocks Validation .................... 9.14-1168 RF and Analog Receiver Validation ................. 9.14-1171 WCDMA Receiver Global Test ......................... 9.14-1172 Summary ............................................................ 9.14-1173

9.14.1 Introduction Whereas the trends for wireless transceivers design are in the direction of integration of most of the blocks to reduce the cost, two main terminal families are identified: – The low-end terminals should serve voice centric standards like GSM, and should be time duplex mode operation (TDD). These standards permit global integration, RF–analog–digital, approach. This means that the best process candidate for this family is the VLSI CMOS if the cointegration between RF, analog, and digital is demonstrated. – The high-end terminals will serve multimode, multimedia applications; they will integrate frequency domain mode operation (FDD). Due to the complexity of the RF–analog and the complexity of the DSP, it seems that, in a first time at least, two main circuits must be developed, a pure state-of-the-art VLS CMOS for the DSP, and an RF–analog one. The BiCMOS SiGecarbon process is the best candidate to help the integration of such an analog–RF parts of this kind of wireless transceivers on silicon. To be ready for the next 3GPP generation of the handset, a focus on the WCDMA standard was made, taking into account the specificity of the GSM, in order to have the possibility to develop a reconfigurable multimode receiver in a second time. This approach imposes several challenges for the integration instead of developing multimode reconfigurable receiver [1]. The main issue is the full duplex mode operation (FDD) of the receiver and the transmit paths. This leads to aggressive requirements of the

9.14-1155 © 2006 by Taylor & Francis Group, LLC

9.14-1156

The Silicon Heterostructure Handbook

receiver due to the strong modulated TX leakage of 23 dBm at the low-noise amplifier (LNA) input while the receiver sensitivity must be met with a wanted modulated channel of 110 dBm. Noise factor, conversion gain, and out of band second- and third-order linearity are the major parameters to be guaranteed to fulfil the WCDMA requirements. For this receiver, the direct conversion architecture has been chosen for its capacities to integrate both analog and RF blocks, and the flexibility offered by this kind of architecture in order to implement more than one standard in the receiver. However, an external interstage SAW filter centered at 1.95 GHz must be added off-chip to reduce the TX power at the down mixer input. This choice introduces the discussion about the process selection and the partitioning. A zero IF architecture is very sensitive to the DC offset, the matching especially on IIP2 linearity parameter, and the 1/f noise, especially for narrow band applications. A silicon germanium bipolar is the best answer to solve these issues. Another issue to take into account is the substrate noise immunity, we will see in the process paragraph how we can easily modulate an MOS transistor by the bulk, and this is not the case with the bipolar collector. The receive path is shown in Figure 9.14.1. An external duplexer filter is connected to the antenna to separate the RX and the TX bands. Then, the signal feeds into the single-ended switched gain LNA. After the LNA, the TX leakage is attenuated by 50 dB to relax the IIP2 linearity requirements of the Quadrature downconverter mixers (DCM) [1]. The Quadrature signals are generated by a divide-by-two based on a cascaded D-latch flip flop. As the frequency synthesizer was not integrated, the 4-GHz local oscillator (LO) differential signals are coming from external inputs. The DCM output current is then converted into voltage by the postmixer amplifier (PMA). This PMA performs a common mode voltage shifting and 4 MHz pre-filtering of the adjacent channels to relax the linearity requirements of the analog base-band (ABB) filter. The analog base-band filter includes a first-stage VGA followed by a fifth-order Butterworth low-pass filter and exhibits 22 dB/þ38 dB variable gain by 2 dB step. The overall low-pass 3 dB cutoff frequency 2.4 MHz is fixed by the unitary resistor and capacitor (RC) module, which is tuned by the calibrator to keep the RC product constant in case of process and temperature spreading. To compensate the static DC offset on each I and Q paths coming from the PMA and LPF mismatches, 8 bits current DAC are connected at the PMA inputs. The dynamic range of the DAC allows the cancellation of the +5 V DC-offset at the receiver outputs in the maximum gain.

Antenna

DAC

DCM

PMA

VGA-LPF

RF

BBI OL

LNA

SAW

QUAD 0⬚ LO 90⬚

CAL

F REF

OL

Duplexer

FIGURE 9.14.1 Zero-IF WCDMA architecture.

© 2006 by Taylor & Francis Group, LLC

RF

BBQ

9.14-1157

Industry Examples at the State-of-the-Art: ST

A read/write three wires serial bus allows the set-up of all the functionalities such as power-down, LNA and VGA gain modes, DC-offset calibration, and PLF cutoff frequency calibration. This chip also includes separate currents biasing (with external reference resistor) and voltage bandgap, respectively, used for RF parts (LNA, mixers, LO Quadrature and DAC) and for the ABB filters.

9.14.2 Process Definition The zero IF architecture permits a reconfigurable multimode approach, and is cost effective in terms of external components such as SAW filters but it is very sensitive to the Mixer IIP2, the DC offset, and the 1/f noise in base band. A way to increase the IIP2 is to design a pure differential mixer, in that case the second-order linearity depends on the mismatching between the LO switching transistors and the LO phase mismatching at the input of these transistors, in a first order. The use of bipolar transistors, in the switching pair, due to their better matching than MOS transistors, allows to increase this second-order linearity parameter. The DC offset is shared by the down-converter mixer offset, the postmixer amplifier offset, the voltage gain amplifier and the analog base-band filter offset. It is well known that bipolar offset is, at least, ten times lower than CMOS one at same operating point. The 1/f noise is another issue of CMOS transistors; pink noise frequency corner is in the 10–100 kHz range when the bipolar pink range is in the 10–100 Hz range, which gives a significant advantage to the bipolar. If we want to go deeper in the integration toward a transceiver, we have to take into account the substrate coupling effects, and to analyze the substrate noise immunity of the devices [2, 3]. The substrate modulation mechanism in an MOS transistor is described in the Figure 9.14.2, the recombination of positive loads with the substrate increases the negative loads collected by the drain, which modifies the threshold voltage of the transistor, as given by the equation included in Figure 9.14.2 VT ¼ VT0 þ gb

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃ (2wF VBS ) 2wF c

This VT variation creates new intermodulation products inside the RF amplifiers and the RF mixers, which can affect dramatically the receiver performances. A solution to reduce this effect is the possibility of using an extra-cost N buried layer, in order to create an isolated bulk; this is efficient low frequency, but it behaves as a transmit capacitor at high frequency, thus LO harmonics, RF harmonics can create intermodulation products. It seems that this limitation is one of the main issues of using CMOS processes in an FDD standard.

source

Gate

N+

Drain

N+ Depletion area

Substrate I sub Bulk

FIGURE 9.14.2 MOS substrate modulation.

© 2006 by Taylor & Francis Group, LLC

9.14-1158

The Silicon Heterostructure Handbook

We have identified some issues, which define why a bipolar transistor is well suited for FDD standards, but we have to continue this process in order to define why we need SiGeC transistors instead of classic Si bipolar ones. The global receiver noise figure (NF), in order to satisfy the IEEE-3GPP requirement, has been estimated to be 7.5 dB, which is very challenging and needs to design an LNA with an NF less than 2 dB at 2.2 GHz in the worst case. The silicon–germanium–carbon transistor allows to maintain the transition frequency, particularly reducing the base collector capacitor and reducing the base resistance, which reduces the intrinsic noise figure of the transistor, and increases its intrinsic linearity as it is described in the following study. The objective of this study is to understand the nonlinear behavior of the heterojunction bipolar transistor (HBT) at 2 GHz. A quantitative method validating an equivalent nonlinear HBT [4] allowed to identify the nonlinearity sources (mainly Cbc) and to observe the second and third order distortion compensations. However, it presents limitation factors, which do not permit to fulfill, understand the HBT implications. In order to accurately observe the compensation an analytic method based on Volterra series has been developed. In this transfer functions theory [5], the second and third order intermodulation currents (IMD2 and IMD3, at respective frequencies ( f1f2, f1þf2) and (2f1f2, 2f2f1)) and first- and secondorder harmonics (H1 and HD2, at respective frequencies f1 and f2) are defined through HBT parameters and the source and load impedances. (Figure 9.14.3). In order to validate this approach, a common emitter LNA was studied. The main results are given in Figure 9.14.4 where the entire contributor to the IMD3 is presented. The main contributors are the Cbc capacitor and the transconductance Gm. Taking into account the high compensation between second and third order nonlinearity of Cp and Gm, the third order of Cbc is mainly implicated. This nonlinearity is given by the following equation: I Cbc

IMD3

¼ C 2 V bc,w2 V bc,w2w1 þ C 2 V bc,w1 V bc,2w2 þ (3=4)C 3 V 2bc,w2 V bc,w1

The amplitude of this one is due for 83% to the third order term C3V2bc, w2Vbc,w1. A 20% reduction of C3 reduces directly the IMD3 by 13%. The SiGeC HBT, reducing this capacitor, increases its third order linearity.

Vdd

ICbc(f = 10 MHz) M1

CIN (0.71 pF)

RSOURCE 50 Ω

DC_block

LIN (6.5nH)

Sources RF 2 GHzet 2.01 GHz 5.25 mA

FIGURE 9.14.3 Transfer function HBT.

© 2006 by Taylor & Francis Group, LLC

CBC

RB

RPI

CPI IB0

RE

LD (1nH)

RC

GM

CCS

LOUT (3.8 nH)

COUT (1.6 pF) RLOAD 50 Ω

9.14-1159

Industry Examples at the State-of-the-Art: ST

Gm2

Image (IMD3) Gm

C bc2 Rπ3

Cπ

C π2

Cπ3 Rπ C bc C bc3

Real (IMD3)

R π2 Gm3

FIGURE 9.14.4 Main contributors to IMD3 in a HBT. TABLE 9.14.1 Criteria Vcc (V) NFmin Icoll (mA) Rn (V) Mod (G opt) Ph(G opt) (8) S21 (dB) S12 (dB) S11 / 50 V S22 / 50 V IIP1 (dBm) IIP3 (dBm)

Noise Figure Improvements NR671A10 SiGeC HBT 0:25 mm

NR671A20 SiGe HBT 0:35 mm

NR671A10 SiGe HBT 0:25 mm

LNA kit part with NR671A20 SiGe HBT

2.5 0.405 4.8 7.5 0.18 3 21.65 26 0.21–j1.63 1.25–j3.5

2.7 0.95 5.5 9 0.47 70 15.7 22.15 0.1–j0.48 0.93–j1.06

2.5 0.9 3.5 15.53 0.267 3 19.5 22.72 0.3–j1.54 1.12–j2.71

2.7 NF ¼ 1.1 dB 5.5

14.7 19.1 14.5 dB 18.5 dB 0.2 10.5

Finally, the noise figure, mainly due to the base resistor, is reduced in a SiGeC HBT, due to the higher level of doping profile in the germanium base; Table 9.14.1 gives, examples of noise figure improvement between a SiGe HBT process and a SiGeC one. At a same level of generation, we can see an improvement of noise figure by 0.5 dB at the same collector current, mainly due by a dramatic reduction of Rn. In conclusion, for these different topics, it has been decided to design the circuit with a SiGeC BiCMOS process based on a 0.25 mm CMOS. The main characteristics of this process are given below. 50 A as CMOS base process — 5 nm gate oxide thickness — 0.25 mm gate lengths — 2.5 V supply voltage — Isolated NMOS (optional) SiGeC heterojunction bipolar transistor (HBT) — Deep trench isolation — LV and HV with 3 and 6 V BVCE0, respectively — Low noise characteristics (Nfmin <0.5 dB) Other active devices — NLDEMOS (2.5 V supply voltage, 15 V BVDS) — Isolated Vertical PNP BJT (Optional) — Lateral PNP

© 2006 by Taylor & Francis Group, LLC

9.14-1160

The Silicon Heterostructure Handbook

Resistors — Silicided N þ Poly — Unsilicided N þ Active — Unsilicided N þ Poly — Unsilicided P þ Poly — Nwell under STI — High-value Poly 1 kohms/sq (option) — 35 ohms/sq TaN resistor (option) Capacitors — 5 fF/mm2 MIM Capacitor — High-value polyresistor — NþPoly/NWell capacitor — NþPoly/Sinker capacitor — 35 fF/mm2 HIDT capacitor (option) Varactors — Pþ/Nwell diode — Pþ/Nwell diode with differential structure — MOS transistor Diodes — Nþ/Psubstrate — Pþ/Nwell Thick metal inductors — Single-ended inductors — Symmetrical inductors (high Q, low area, large L-range) Metal Five metal levels — M1 in Tungsten — M2–M5 in aluminum — Thick M5 (2.5 mm) — Copper M5 level (option) — 50 ohms-cm substrate A cut of the HBT transistor is given in Figure 9.14.5. We will go now more deeper in the design of each block beginning by the LNA, and then will have a discussion on the integration issues, we will also discuss about the opportunity of the use of specific technology for module approach such micromechanical devices (MEMs) and integrated passive devices on glass (IPAD).

9.14.3

Switched Gain LNA Implementation

A single-ended LNA was chosen to minimize the duplexer losses (compared with a single to differential one), which is inserted at the antenna output, the substrate noise sensitivity is managed using bipolar transistors, but it is obvious that this should be an issue in case of a transmit, receive application. This LNA, described in Figure 9.14.6, is based on a cascode topology with degenerated emitter inductor L1 to get the best trade-off between matching and noise factor. As explained in the ‘‘Introduction,’’ the circuit must be, in the final version, flip chipped on a glass module, which creates a constraint for L1 inductor: instead of using bonding inductor, thick metal inductor L1 was integrated. The well-known cascode topology was selected for its abilities to reach higher gain. This helps designers to finally achieve the requested minimum power gain when taking into account all the © 2006 by Taylor & Francis Group, LLC

9.14-1161

Industry Examples at the State-of-the-Art: ST

polysilicon emitter

Si/SiGe:C epitaxy

STI

DTI

FIGURE 9.14.5 SiGeC cross section HBT. VDD C2

L2

C3

RFout VG2

C1 RFIN

C5

M2 C4

R1

M1

−

To Q1 base

Q 2 V LG

Q1 VG1

+

L1

FIGURE 9.14.6 Switched gain LNA simplified schematic.

undesired elements involved in gain reduction, such as RF pads, ESD protection diodes, layout parasitic, and wire bonding. The common gate M2 MOS transistor replaces advantageously the bipolar transistor to enhance the output compression point. As the output compression is limited by the voltage swing across the L2 load inductor, the MOS allows saving precious mV of swing by its lower Vgs than the Vce bipolar. A feedback capacitor array is inserted between the input and the output nodes to increase the overall third order linearity to the detriment of a power gain reduction. In the low gain (LG) mode, the 4.5 mA collector current flowing through Q1 is switched off. Then the Q2 transistor is biased at 50 mA to reduce the power gain to 16 dB. In that configuration, the input matching in the LG mode is done by the input MOS M1 operating in the triode region. The LNA is biased using a DC feedback loop A1, which compares the Q1 collector current with a current reference coming from the bandgap current source. Compared to the mirror current source, this biasing method gives more flexibility to set the Q1 transistor area.

© 2006 by Taylor & Francis Group, LLC

9.14-1162

The Silicon Heterostructure Handbook

Finally, the LNA is simulated with its RF pads including ESD protection diodes and the bonding models associated with the PCB lines extracted with Ansoft HFSS 3D field solver. Separately, the layout parasitic elements were extracted with Cadence ASSURA-RF extractor, which permits a full RLCþK extraction of the selected RF critical nets. Thanks to the 0.25 mm SiGe-carbon process and the lower base–collector capacitance of the BJT, the LNA had some margin to fulfil the 3G specifications requirements at low current. The 5 fF/mm2 metal– metal capacitor at the last metal level exhibits lower bottom to substrate parasitic capacitor and helps to save power gain. At 2.14 GHz, this LNA achieves þ3 dBm IIP3 and 14.7 dB of power gain with 1.3 dB noise factor. The input compression point of 10 dBm is more critical within the 2.7 V supply voltage and the 4.5 mA collector current. In the LG mode, the power gain is reduced to 15 dB with 200 mA consumption. Table 9.14.2 summarizes the main simulated results obtained on this block. The IPAD simulations are dedicated to the flip chipped on glass version, which is the final product, the COB simulations are dedicated to the chip on board, which is the tested one in this chapter, and AST spec columns give the specifications for this LNA. Blocker ¼ 20 dBm at 2 GHz Simulations including: COB, ESD, Layout RC estimated parasitic Figure 9.14.7 gives a layout view of the LNA, the adaptation self-inductance being the smaller, and the bigger one is the output load. The LNA core area is 500510 mm.

9.14.4

Down Mixers and PMA Implementation

The direct conversion mixer (DCM), described in the Figure 9.14.8, is based on a differential input transconductor Q1 and Q2 with an emitter degenerating inductor. The 3.5 mA tail current source I0 is shared between the I and Q paths; this biasing method is helpful to compensate the symmetry error of the incoming signals (specially when the RF signals are coming from outside the chip) that contribute to increase IIP2 parameter. A 200-Ohm input differential impedance matching requested by the interstage SAW filter is achieved at 2.14 GHz with 10 nH series external inductors. The Q1, Q4 . . . Q8 bases voltage comes from a bandgap reference and an operational amplifier. The output base-band current at the Q3 Q6 collector enters in the differential postmixer amplifier (PMA) based on the Rauch topology, which converts current to voltage. The transimpedance R1 value

TABLE 9.14.2

Simulate Results IPAD

ICC (mA) S11 (dB) S21 (dB) S12 (dB) S22 (dB) NF (dB) GP (dBm) IIP3 (dBm) IIP1 K Settling time (ms) DNF GP-1 dB

COB

AST SPEC

HG

LG

HG

LG

HG

LG

4.84 15 15.40 22.6 10 1.60 15.60 0.00 12.1 1.20 4.00 0.10 12

0.65 12.8 16.8 22.8 4 21 16.8 13 11 18.00 4.00 0.80 T.B.D

T.B.D 10 14.1 21 7.5 1.56 14.1 þ3 10a 1.13 N.A N.A N.A

T.B.D 11 16 20.6 4.6 20 15.9 11 11.4a 15 N.A N.A N.A

5 12 N.A 18 12 2 14 1 8 N.A 10 N.A

0.5 9.5 N.A 18 9.5 20 17 12 13 N.A 10 N.A

a

Process ¼ Typ.

© 2006 by Taylor & Francis Group, LLC

9.14-1163

Industry Examples at the State-of-the-Art: ST

FIGURE 9.14.7 Switched gain LNA layout view.

Vcc

Vcc

+

+ R1 Q6

Q3 TO Q

Q4 R2

− A1

Q5

+

R2

RF

RF Q2

Q1

R1

l0

FIGURE 9.14.8 Down-converter mixer and PMA simplified schematic.

was chosen as 2400 ohm in order to reach 22 dB of typical gain when PMA and DCM are cascaded. The PMA (Figure 9.14.3) also exhibits a second-order low-pass Butterworth frequency response to filter out the 10 and 20 MHz adjacent blocking channels by, respectively, 10 and 20 dB. The 5.8 MHz cutoff frequency is high enough to avoid phase distortion of the receive channel. The PMA fully differential operational amplifier A1 uses fT ¼ 6 GHz vertical isolated PNP transistors into the input pairs. These transistors bring the lowest 1/f noise available in the process offer. The PMA achieves 380 MHz of gain–bandwidth product in order to present good linearity behavior when the 10 and 20 MHz adjacent spurious signals are received. The I/Q down-converters and PMA consumption are, respectively, 3.5 and 3 mA for a voltage gain of 22 dB with an IIP3 equal to 0 dBm and 4.3 nV/sq.Hz of equivalent input noise.

© 2006 by Taylor & Francis Group, LLC

9.14-1164

The Silicon Heterostructure Handbook

FIGURE 9.14.9

Down-converter mixer and PMA layout.

The next gives the simulated results of the DCMþPMA obtained in the worst case in temperature/ process/power supply. Figure 9.14.9 gives a layout view of the down-converter mixer with the postmixer amplifier, the mixer being on the right. The total area of this block is 500 mm by 500 mm.

9.14.5

Variable Gain Amplifier (VGA) and Low-Pass Filter (LPF)

Following the postmixer amplifier, the VGA ensures that the signal remains in an acceptable dynamic. A classical inverting amplifier structure has been selected; a description is given in Figure 9.14.10. The VGA is located before the low-pass filter to satisfy the noise requirement; on the other hand, it must be more linear to support adjacent blockers. The low-pass filter is an active RC fifth-order Butterworth filter. The main parameter of the filter is the accuracy of the 3 dB cutoff frequency, maximum specification being 5% deviation. In order to achieve this performance an internal RC calibrator has been designed. This calibrator compares the time constant of an RC structure to a reference period and provides a 6-bit digital control word, which adjusts the capacitor to correct process and temperature drift. The RC structure of the calibrator cell is then adjusted with 3.2% resolution. A specific care is given to the layout in order to guarantee this accuracy; the capacitor layout in the filter should be exactly the same as the one of the calibrator.

© 2006 by Taylor & Francis Group, LLC

9.14-1165

Industry Examples at the State-of-the-Art: ST

IN_P

+

−

+

−

+

−

+

−

+

−

VOM

IN_M

−

+

−

+

−

+

−

+

−

+

VOP

FIGURE 9.14.10 Fifth-order low-pass filter schematic.

FIGURE 9.14.11 Low-pass filter operational amplifier schematic.

By taking resistor and capacitor matching between calibrator and filter into account (1% and 0.5% respectively) it leads to 3.5% RC product accuracy in the filter. If we want to guarantee the 5% accuracy of the band pass filter, we should avoid any parasitic effect that may degrade the cutoff frequency. As a consequence, the gain bandwidth product of the filter’s operational amplifier should be high enough, in order to maintain the 3 dB band pass. The gain–bandwidth (GBW) product of the operational amplifier is 300 MHz for a 2.4 MHz filter bandwidth. The linearity (IIP3) and the group delay specifications also require a high GBW in order to get a high gain in the feedback loop. The use of npn bipolar input stage and pnp current mirrors is very helpful to achieve the wanted trade-off between GBW, DC offset, and power consumption. Figure 9.14.11 describes the operational amplifier schematic. Moreover, bipolar transistor allows a huge reduction of the flicker noise contribution of analog blocks regarding to a pure CMOS design [6]. It is not so important for WCDMA application, but it becomes a tremendous advantage when making the analog blocks design compatible with both WCDMA and GSM standards at low power. The GSM bandwidth in zero-IF architecture being around 100 KHz, it is not possible to integrate a kind of DC blocker, like a capacitor path. The specifications of this Analog base-band are given below: First (VGA þ FILTER) stage: Gain: 15 dB to þ15 dB in steps of 2 dB Filter: Third order — with a cutoff frequency of 2.68 MHz + 5% Input noise < 28 nV/SQR(Hz) IIP3 > 3 dBVp out of band

© 2006 by Taylor & Francis Group, LLC

9.14-1166

The Silicon Heterostructure Handbook

Second (VGA þ FILTER) stage Gain: 7 dB to þ23 dB in steps of 2 dB Filter: Second-order with a cutoff frequency of 2.94 MHz + 5% Figure 9.14.12 gives a layout view of the analog base-band, the block area is around 700 mm by 500 mm.

9.14.6

LNA-Mixer Isolation Strategy

Since WCDMA is a full duplex system, Receive (RX) and Transmit (TX) signals are simultaneously present at the antenna. Even if filtered by the front-end duplexer, the TX signal remains at 23 dBm at the LNA input and very much constraints its IIP3 requirement. In order to filter out this TX leakage before mixer, an external SAW filter is used between the LNA and the mixer used is as shown in Figure 9.14.1. This SAW filter rejects out TX signal by 40 dB. An LNA and Mixer floor planning has been studied in order not to bypass these 40 dB attenuation by internal coupling. There are both magnetic and electrical coupling on chip, after Cadence ASSURA-RF and Cadence SubstrateStorm postextracted simulations; it was found that the main contribution to the coupling effect between these two blocks was the magnetic one. Indeed, inductors are used in the mixer input stage in order to optimize the noise-linearity trade-off in the cells, and magnetic coupling between LNA output inductor and Mixer input inductors could bypass the external filter attenuation of the TX signal. Differential structure of the Mixer increases its coupling immunity but due to the layout constraint the position of LNA inductors is not symmetrical with the mixer positions. The coupling coefficient between these inductors has been estimated to be 6104 that leads to 90 dB isolation from LNA output to Mixer input (simulated with ESD protection diodes). This value means that internally there is not any

FIGURE 9.14.12 Analog base-band layout.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

9.14-1167

risk to bypass the SAW filter, but the circuit, in the validation module is bonded to board module, which means that the LNA output should be coupled to the Mixer inputs through the wire bonding. A specific model of the wire bonding ring was made using Ansoft HFSS, in order to define the coupling factor between the different inputs and outputs. After extraction of these coupling factors, a solution was found with 50 dB bonding coupling between the LNA outputs and the Mixer inputs, to guarantee the 40 dB rejection of TX signal by the external filter. The drawback of this isolation constraint is that we had to increase the distance between LNA and Mixer. This free space was used to place the offset compensation DACs and the postmixer amplifier that leads to a nonoptimal base-band signal path.

9.14.7 Receiver Implementation Figure 9.14.13 gives a layout view of the WCDMA receiver, the core area of this function is 1.8 mm2, and the total power consumption is 25 mA in high gain and 20 mA in low gain. The LNA is on the right side, its input is on the right, and its output is on the top, in order to respect a 908 angle between the two-wire bonding, which allows to reduce the coupling effect drastically. Between the LNA and the Mixer we can see the PMA at the right of the Mixer and the DACs in order to increase the distance between the two RF blocks. This floor plan constraint creates a distance to manage between the PMA and VGA-Filter. On the bottom of this layout, we can discover the serial bus, which drives this function and in the final product; the global transceiver, this die being the receiver prototype of the global transceiver program.

9.14.8 Validation Strategy The validation strategy was thought out early in the project, and was at the same level as the process selection, with the architecture and the designs as the main concerns for success of the layout. First of all, this circuit, being a step to a transceiver, has to be validated in chip on board (COB) configuration, and will be used in an intermediate version in flip chipped (FC) on glass. That means that the validation strategy must cover these two cases. In a second time, this circuit must be validated at an RF–analog level, before going to a chip-set application; these considerations have guided our approach.

FIGURE 9.14.13 Receiver layout: 2.9 mm1.4 mm.

© 2006 by Taylor & Francis Group, LLC

9.14-1168

The Silicon Heterostructure Handbook

FIGURE 9.14.14 COB module and FC module.

In order to satisfy the first constraint, a module approach was defined, which allows to develop two compatible modules, one for the COB version and one for the FC configuration. In order to satisfy to the second constraint, the two modules interface with the same RF board, which is a part of the global chip-set board. Figure 9.14.14 shows the two modules. On the left side, the COB module exhibits the external SAW filter between the LNA and the Mixer at the top with its adaptation network, while it is integrated in the integrated passive devices on glass in the FC version. The two modules are symmetric, due the fact that the circuit is flip chipped in the FC version. The targeted objective of this approach is to guarantee the global RF analog behavior of the module to the customer, which needs to validate the path from the module inputs/outputs to the internal circuit. In order to aim this target, a modelization of board lines was made, and a global simulation was performed as shown in Figure 9.14.15. Finally, the RF validation board was designed to be compatible with the global application chip-set board; a description of this board is given in Figure 9.14.16.

9.14.9

RF and Analog Blocks Validation

To validate the functions separately, three different versions were processed: the stand-alone analog baseband, the PMA-down-mixer, and the complete RX path shown in Figure 9.14.1. The integrated LNA could also be validated separately as the RF output enters the SAW filter. The validation board was split into two parts: the IC is wire bounded on an RF module, which is reported on a motherboard; this allows more flexibility to test several dies. The RF module contains the RF external elements such as impedance matching, supply capacitors, and SAW filter. This module also includes the de-embedding footprints to validate separately the scattering parameters of the LNA, SAW filter, and input mixer in order to help impedance matching between these RF blocks. The LNA S11 and S22 parameters show good agreements with the simulations: 2.2 nH series inductor is added in series at the LNA input while the output is matched to 50 ohms without external elements. At 2.14 GHz, the measured power gain is 13.4 dB and the noise factor is 1.85 dB. In band IIP3 was measured at 0 dBm with the 10 MHz offset two tones interferers for 5 mA current supply at 2.7 V. A summary of the measured results is given in Table 9.14.3.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

9.14-1169

FIGURE 9.14.15 Board to chip simulation flow.

The I/Q PMA down-converter and LO Quadrature generator were validated together with the SAW filter (measurements have been done at the analog–base-band outputs with 0 dB of VGA gain). The input return loss seen at the SAW filter input is around 6 dB in the middle of the RX band. With 4 nH series inductors between the SAW filter and the mixer, the power gain reaches 16.7 dB, with an in band IIP3 of 4 dBm. The noise factor is around 14.5 dB when the VGA gain is set to 16 dB. On this sample, we report þ47 dBm IIP2 for the cascaded mixer-PMA-VGA with 38 and 0.06 dB of Quadrature phase error and gain error, respectively, at the base-band outputs. These measured results are in line with the simulations except for the in band IIP3 that is 3 dB lower than predicted. A summary of measurement results is given in Table 9.14.4. The analog VGA low-pass filter exhibits þ38 dB maximum gain with 22 nV/Hz input referred noise. The frequency response shows 26 and 84 dB attenuation at 5 and 20 MHz, respectively, with 62 nsec group delay variation (from 1 kHz to 1.92 MHz). At the maximum VGA gain, the linearity reached 7 dBVp IIP3 for 6 mA of current consumption (I and Q). A summary of the measurement results is given in Table 9.14.5.

© 2006 by Taylor & Francis Group, LLC

9.14-1170

FIGURE 9.14.16

The Silicon Heterostructure Handbook

RF analog board picture.

TABLE 9.14.3

Measurement Results Simulated Performances

Gain (dBm to dBVp) Input linear operation (dBm) IIP3 (dBm) SSB noise figure (dB)

TABLE 9.14.4

ICC S11 S21 S12 S22 NF IIP3 IIP1

54.5 13 7 14.8

Measurement Results HG

LG

5.00 15 13.2 22 17 1.85 0.00 12.5

0.20 23 18.5 22 12 N.A N.A > 10

HG means high-gain configuration, while LG means low gain, ICC is given in mA, S parameters and NF in dB, while IIP3 and IIP2 are given in dBm.

© 2006 by Taylor & Francis Group, LLC

9.14-1171

Industry Examples at the State-of-the-Art: ST TABLE 9.14.5

Specifications vs Performance

Worst Case Electrical Performances

AST Specifications

Performances

6 21 3.8 28 2 13

6.3 20 3.6 23 1.5 13.3

Current consumption (mA) Gv (dB) PMA cutoff frequency (MHz) Input linear operation (dBVp) IIP3 (dBVp) SSB noise figure (dB)

9.14.10

RF and Analog Receiver Validation

The I/Q signals at the complete received outputs were sampled at Fs ¼ 38.4 MHz and filtered with a 0.13 mm HCMOS SD ADC-FIR companion chip [7], offering 55 dB equivalent input dynamic range. A first level of test was made in single tone configuration in order to define the sensibility and the selectability of the global receiver integrating the two circuits, the RF–Analog circuit developed in this chapter and its companion chip. The main results are given below.

Reference Sensitivity Test RF In 117 dBm SNR [dB]

Minimum Requested

Measured

10.5

11.5

Note: TX Power at antenna Connector is 22 dBm instead of 24 dBm.

Maximum Input Level RF In 25 dBm SNR [dB]

Minimum Requested

Measured

10.5

>30 dB

Adjacent Channel Selectivity RF In 103 dBm Blk @ 5 MHz 52 dBm SNR [dB]

Minimum Requested

Measured

10.5

20

Intermodulation Characteristics RF In 114 dBm Blk @ 10 MHz 46 dBm Blk @ 20.5 MHz 46 dBm SNR [dB] SIR Input IP3 [dBm]

© 2006 by Taylor & Francis Group, LLC

Minimum Requested 12 17 PA off (not enough RF generators)

Measured 13.2 7.8 dB 9

9.14-1172

The Silicon Heterostructure Handbook Blocking Characteristics RFin: 114 dBm — TX: 22 dBm

SNR [dB]

Spec.

Measured

RFin + 10 MHz RFin + 15 MHz F ¼ 2045 MHz 30 dBm

11 11 11

13 13 12

F ¼ 4090 MHz 15 dBm F ¼ 1760 MHz 15 dBm F ¼ 4280 MHz 15 dBm F ¼ 1070 MHz 15 dBm F ¼ 713 MHz 15 dBm

11 11 11 11 11

12 11 12

Comment

2xBlk-Tx (in spec despite off out spec LNA IIP3 due to not worst case Duplexer Isolation) Blk-Tx 2xTx-Blk 2xRx Rx/2 Not done due to generator harmonics Rx/3 Not done due to generator harmonics

Spurious Emission Up to 7GHz ? 12 GHz

Spec.

Measured

268.8 MHz (H7 Fref.) 4.284 MHz (H2 LO)

57 dBm 47 dBm

80 dBm 64 dBm

These results show that the complete receiver is in the specifications and allow receiving modulated signals, this last step is detailed in the next chapter.

9.14.11

WCDMA Receiver Global Test

This section presents the performance of the receiver platform including the SiGeC RF–Analog receiver, the VLSI-CMOS ADC-FIR, a software modem running in a PC on a Linux real-time platform. The full performance against specification 25.101 by 3GPP was evidenced. RAW BER static condition (ROESTI 1.0) 1.00E.00 Margin Requested-Base Band - NF Receiver - No RF Switch

Probality of error

1.00E.01

1.00E.02

1.00E.03

1.00E.04 −116.7

−114.7

−112.7

−110.7

−108.7 for Simulation Module #1

FIGURE 9.14.17

Simulated bit error rate performance.

© 2006 by Taylor & Francis Group, LLC

−106.7

−104.7

−102.7

−100.7

Industry Examples at the State-of-the-Art: ST

9.14-1173

In order to illustrate this operation, a RAW BER is given in Figure 9.14.17. The circuit exhibits a 5 dB margin with the diplexer, without RF switches, which means that the complete receiver should have a 3 dB margin at least.

9.14.12

Summary

The first BiCMOS SiGe-carbon 0.25 mm/60 GHz fT process has been validated with a complete WCDMA receive chain including switched gain LNA, I/Q down mixers, LO Quadrature generator and VGA fifthorder Butterworth low-pass filter in 4 mm2 silicon area including pads. Thanks to the duplexer TX isolation [8] and to the careful estimation of the coupling (between cells inside the IC and between RF lines on the validation board), the receiver meets all the SNR requirements with þ22 dBm TX power measured at the antenna connector, even if the measured LNA IIP3 is slightly below than expected. This receiver in a WCDMA chip-set including a digital–RF interface, ADC plus FIR, and a software modem, meets the full performance against specification 25.101 by 3GPP.

Acknowledgments The author thanks especially the teams of ST CR&D, which have designed, implemented, founded the circuit and made the electrical validation. The team of ST AST, which was involved in the system definition, the software design, and the application evaluation. The IXL laboratory of the University of Bordeaux has made specific study on the MOS bulk modulation.

References 1. J. Ryyna¨nen et al., A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA, IEEE Journal of Solid-State Circuits, 38(4), 2003, 594–602. 2. T. Taris et al., A 1 V 2 GHz VLSI CMOZS low noise amplifier, RFIC 2003 Conference Proceeding, p. 123. 3. T. Taris et al., A 0.9 V body effect feedback 2 GHz low noise amplifier, ESSCIRC 2003 Conference Proceeding, p. 659. 4. R. Paulin, Etude des causes de non-line´arite´ du transistor bipolaire SiGe 0.25 mm, JNRDM, mai 2003. 5. P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits, Kluwer Academic Publishers, Dordrecht, 1998. 6. K-Y. Lee et al., Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver, IEEE Journal of Solid-State Circuits, 38(1), 2003, 43–53. 7. A. Dezzani and E. Andre, A 1.2-V dual-mode WCDMA/GPRS SD modulator, IEEE International Solid-State Circuits Conference, Session 3, 2003. 8. S. Reynolds et al., A direct-conversion receiver IC for WCDMA mobile systems, IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, 2002, pp. 61–64.

© 2006 by Taylor & Francis Group, LLC

Appendices A.1

Properties of Silicon and Germanium J.D. Cressler ........................................... A.1-1177

A.2

The Generalized Moll–Ross Relations J.D. Cressler ............................................ A.2-1181

A.3

Integral Charge-Control Relations M. Schro¨ter .................................................. A.3-1187 Introduction . Derivation of a General Relationship . Homojunction Transistors . Heterojunction Transistors . Further Extensions . Summary

A.4

Sample SiGe HBT Compact Model Parameters R.M. Malladi.......................... A.4-1201

A.1-1175 © 2006 by Taylor & Francis Group, LLC

A.1 Properties of Silicon and Germanium

John D. Cressler Georgia Institute of Technology

The energy band structures of Si and Ge are depicted in Figure A.1.1, together with (1) their carrier effective mass parameters (Table A.1.1) and (2) their bulk structural, mechanical, optical, and electrical properties (Table A.1.2) [1–3].

Si

2

Ec

2

3

3

Ge

Eg

−1

Energy (eV) 0 1

1 0

Eg

−1

Energy (eV)

Ec

−2

Ev

L

[111]

Γ

[100]

X

−3

−3

−2

Ev

L

[111]

Γ

[100]

X

FIGURE A.1.1 Energy band structure, showing the principal conduction and valence bands of Si and Ge as a function of k-space direction. (From M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. With permission.)

A.1-1177 © 2006 by Taylor & Francis Group, LLC

A.1-1178

The Silicon Heterostructure Handbook

TABLE A.1.1

Carrier Effective Mass Parameters for Si and Ge

Parameter

Units

Effective electron mass (m n*) Longitudinal (4.2 K) Transverse (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

Effective hole mass (m p*) Heavy hole (4.2 K) Light hole (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

TABLE A.1.2

Silicon

Germanium

0.9163 0.1905 1.062 1.090

1.58 0.082 — —

0.537 0.153 0.59 1.15

0.28 0.044 — —

Properties of Bulk Si and Ge

Parameter

Units

Silicon

Germanium

Atomic number Atomic density Atomic weight Density Electronic orbital configuration Crystal structure Lattice constant (298 K) Dielectric constant Breakdown strength Electron affinity Specific heat Melting point Intrinsic Debye length (300 K) Index of refraction Transparency region Thermal conductivity (300 K) Thermal expansion coefficient (300 K) Young’s modulus Energy bandgap (low doping)

— (atoms/cm3) (g/mole) (g/cm3) — — (A˚) — (V/cm) (V) (J/g-8C) (8C) (mm) — (mm) (W/cm-8C) (8C 1) (dyne/cm2) (eV)

Equivalent conduction band minima Effective electron mass (300 K) Effective hole mass (300 K) Intrinsic carrier density (300 K) Effective conduction band DoS (300 K) Effective valence band DoS (300 K) Electron mobility (300 K) Hole mobility (300 K) Electron diffusivity (300 K) Hole diffusivity (300 K) Optical phonon energy Phonon mean free path length Intrinsic resistivity (300 K)

— (mo) (mo) (cm 3) (cm 3) (cm 3) (cm2/V-sec) (cm2/V-sec) (cm2/sec) (cm2/sec) (meV) A˚

14 5.021022 28.09 2.329 (Ne) 3s23p2 Diamond 5.43107 11.7 3105 4.05 0.7 1412 24 3.42 1.1–6.5 1.31 2.610 6 1.91012 1.12 (300 K) 1.17 (77 K) 6 1.18 0.81 1.021010 2.81019 1.041019 1450 500 37.5 13 63 76 3.16105

32 4.421022 72.6 5.323 (Ar) 3d104s24p2 Diamond 5.65791 16.2 1105 4.00 0.31 1240 0.68 3.98 1.8–15 0.60 5.910 6 — 0.664 (291 K) 0.741 (4.2 K) 8 — — 2.331013 1.041019 6.001018 3900 1900 100 49 37 105 47.62

© 2006 by Taylor & Francis Group, LLC

(V cm)

Properties of Silicon and Germanium

A.1-1179

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. 3. R. Hull, editor. Properties of Crystalline Silicon. London: EMIS Datareviews Series, Number 20, INPSEC, 1999.

© 2006 by Taylor & Francis Group, LLC

A.2 The Generalized Moll–Ross Relations

John D. Cressler Georgia Institute of Technology

The classical solution for the collector current density in a Si BJT, derived by Shockley, necessarily assumes a constant base doping profile. In this case, for low-injection conditions, the drift component of the minority carrier transport equation can be neglected, and the minority carrier diffusion equation solved under the Shockley boundary conditions. The resultant equation, under the assumptions of negligible neutral base recombination and forward-active bias, is the well-known expression JC ¼

qDnb 2 DEgbapp =kT qVBE =kT n e e 1 : io W Nab b

(A:2:1)

2 Here, Dnb is the minority electron diffusivity, Nab is the ionized base doping level, nio is the low-doping intrinsic carrier density, given by,

n2io ¼ NC NV eEgo =kT ,

(A:2:2)

and DEgbapp is the heavy-doping induced bandgap narrowing. The path to the generalization of this result to the ‘‘real-world’’ case of a nonconstant base doping profile (Figure A.2.1) is nonobvious, and even a cursory glance at the problem is enough to convince one that it cannot follow the original path in Shockley’s approach. The complexity of this problem results from the addition of the field-driven transport, which is now no longer negligible due to the dopinggradient-induced field. The clever solution to this problem was first presented in the classic paper by Moll and Ross in 1956, the so-called ‘‘Moll–Ross relation’’ [1]. Unfortunately, that solution made two undesirable assumptions: (1) that the minority electron mobility (hence, diffusivity) is constant across the quasineutral base and (2) that the intrinsic carrier density is constant across the quasineutral base. The latter assumption, in particular, fails in the presence of a heavily doped base (i.e., real life), since the apparent bandgap narrowing is inherently position dependent across the base, and hence the effective bandgap in the base is also position dependent.* In essence, then, the problem becomes one of solving for the collector current density in the presence of both nonconstant base doping and nonconstant base bandgap, and is particularly relevant to the graded-base SiGe HBT. This problem remained unsolved for *In fairness, Moll and Ross cannot be blamed for the second assumption since doping-induced bandgap narrowing had not yet been discovered.

A.2-1181 © 2006 by Taylor & Francis Group, LLC

A.2-1182

The Silicon Heterostructure Handbook

Nab−(x)

Space charge n+

n−

p Wb

0 E

x C

B

FIGURE A.2.1 Schematic nonconstant base doping profile used in the derivations.

almost 30 years until the seminal paper by Kroemer in 1985 [2]. Since Kroemer’s ‘‘generalized Moll–Ross relations’’ are the starting point for both the dc and ac analysis of the graded-base SiGe HBT (Chapter 4.2), we present that elegant derivation here (showing all of the mathematical steps that Kroemer neglected to include in his paper). The assumptions in Kroemer’s solution include: (1) 1-D transport, (2) transport by both drift and (x) for all x across the base), (4) negligible diffusion, (3) low-injection conditions (i.e., nb(x) Nab neutral base recombination, and (5) forward-active bias. Importantly, however, there are no assumptions on the position dependence of the base doping profile or the base bandgap.** We begin from the generalized drift–diffusion minority electron transport equation, as expressed in terms of the minority electron quasi-Fermi potential Jn ¼ qmn nrfn ,

(A:2:3)

which for our 1-D Si BJT problem reduces to JC ¼ qmnb (x)nb (x)

dfn (x) : dx

(A:2:4)

In the quasineutral base, the majority carrier (hole) quasi-Fermi potential (fp) in low-injection is constant, such that JC ¼ qmnb (x)nb (x)

d fn (x) fp , dx

(A:2:5)

and from the generalized Shockley boundary condition nb (x)pb (x) ¼ n2ib (x)eq(fn (x)fp )=kT ,

(A:2:6)

kT nb (x)pb (x) ln ¼ fn (x) fp : q n2ib (x)

(A:2:7)

which can be rewritten as

**Interestingly, additional generalizations to Kroemer’s result have been recently offered [3]. Let it never be said that the final word in device physics is ever in.

© 2006 by Taylor & Francis Group, LLC

The Generalized Moll–Ross Relations

A.2-1183

Taking the derivative of both sides we have kT q

n2ib (x) d nb (x)pb (x) d f ¼ (x) f p : n2ib (x) dx n nb (x)pb (x) dx

(A:2:8)

Substituting this result back into Equation (A.2.5), we obtain kT n2ib (x) d nb (x)pb (x) JC ¼ qmnb (x)nb (x) q nb (x)pb (x) dx n2ib (x)

(A:2:9)

We now integrate this expression from some arbitrary point in the base profile to the neutral base boundary (Wb) to obtain ð Wb x

JC pb (x 0 ) 0 nb (x 0 )pb (x 0 )Wb dx ¼ n2ib (x 0 ) x qDnb (x 0 ) n2ib (x 0 )

(A:2:10)

Under the assumptions of negligible neutral base recombination (i.e., JC is a constant to the integration), and using the fact that in forward-active bias, pb (Wb )nb (Wb ) ’ n2ib (Wb )

(A:2:11)

pb (x 0 )dx 0 nb (x)pb (x) ¼1 n2ib (x) Dnb (x 0 )n2ib (x 0 )

(A:2:12)

we find JC q

ð Wb x

At the emitter–base boundary (x ¼ 0), we know from the generalized Shockley boundary condition that nb (0)pb (0) ¼ n2ib (0)eq(fn (0)fp (0) )=kT ,

(A:2:13)

fn (0) fp (0) ¼ VBE ,

(A:2:14)

pb (x)dx ¼ 1 e qVBE =kT , Dnb (x)n2ib (x)

(A:2:15)

and

so that we obtain JC q

ð Wb 0

and thus finally, q(e qVBE =kT 1) , JC ¼ W Ð b pb (x)dx 2 0 Dnb (x)nib (x)

(A:2:16)

This is the ‘‘generalized Moll–Ross relation’’*** for the collector current density in a bipolar transistor with nonconstant base doping and arbitrary position-dependence of the base bandgap. Observe that if ***I personally would have no problem calling this elegant result the ‘‘Kroemer relation.’’

© 2006 by Taylor & Francis Group, LLC

A.2-1184

The Silicon Heterostructure Handbook

we allow pb (x) ¼ Nab (x) ¼ Nab ¼ constant, then we obtain Equation (A.2.1), as expected (the extra negative sign simply accounts for the fact that the electron flow is in the opposite direction of the positive current flow). As detailed in Chapter 4.2, this fundamental result is the starting point of the derivations for collector current density, the current gain, and the output conductance in a graded-base SiGe HBT. In this case, in addition to the bandgap-narrowing-induced position dependence in the base bandgap, we have an additional contribution from the Ge-strained layer (Figure A.2.2). This Ge contribution easily enters the generalized Moll–Ross relation via nib2 in Equation (A.2.16). For more detail on the resultant derivations and the assumptions and approximations involved, the reader is referred to Ref. [4]. An additional desirable feature of Kroemer’s approach is that we can also easily obtain an analytical expression for the base transit time in a device with nonconstant base doping and bandgap. Under a quasistatic assumption we can generally define the base transit time as

q tb ¼ JC

W ðb

nb (x)dx:

(A:2:17)

0

From Equation (A.2.12) and neglecting the unity factor, we can solve for nb (x) as JC n2ib (x) nb (x) ¼ q pb (x)

W ðb x

pb (x 0 )dx 0 Dnb (x 0 )n2ib (x 0 )

(A:2:18)

Substituting this result into Equation (A.2.17), we finally obtain

tb ¼

ð Wb 0

8

W ðb n2ib (x) <

pb (x) :

x

9 pb (y)dy = dx Dnb (y)n2ib (y);

(A:2:19)

Again, observe that if we allow pb(x) ¼ Nab (x) ¼ Nab ¼ constant, we obtain the classical result for a BJT with constant base doping

tb ¼

Wb2 , 2Dnb

(A:2:20)

Ge

Space charge

_ n+

Wb

0 E

FIGURE A.2.2

© 2006 by Taylor & Francis Group, LLC

n−

p B

x C

The Generalized Moll–Ross Relations

A.2-1185

as expected. This second generalized Moll–Ross relation is the starting point for the derivation of base transit in a graded-base SiGe HBT (Figure A.2.2), as detailed in Chapter 4.2 and Ref. [4].

References 1. J. Moll and I. Ross. The dependence of transistor parameters on the distribution of base layer resistivity. Proceedings of the Institute of Radio Engineers 44:72, 1956. 2. H Kroemer. Two integral relations pertaining to electron transport through a bipolar transistor with a nonuniform energy gap in the base region. Solid-State Electronics 28:1101–1103, 1985. 3. SN Mohammad. Generalization of the Moll–Ross relations for heterojunction bipolar transistors. Solid-State Electronics 46:589–591, 2002. 4. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

© 2006 by Taylor & Francis Group, LLC

A.3 Integral ChargeControl Relations A.3.1 A.3.2 A.3.3 A.3.4

Introduction ........................................................... Derivation of a General Relationship .................. Homojunction Transistors .................................... Heterojunction Transistors ...................................

A.3-1187 A.3-1188 A.3-1192 A.3-1195

Box Ge Profile in the (Metallurgical) Base Region . Trapezoidal Profile in the (Metallurgical) Base Region

Michael Schro¨ter University of California at San Diego

A.3.1

A.3.5 A.3.6

Further Extensions................................................. A.3-1198 Summary ................................................................ A.3-1199

Introduction

One of the most important requirements for compact models is an accurate description of the devices’ main current. In an npn bipolar transistor, this is the (generally time dependent) collector current iC which is given by the transport of electrons from emitter to collector. For time (and frequency) dependent quasistatic (q.s.) operation, which is the case in the vast majority of practical applications, the current flowing at the collector terminal can be partitioned into a q.s. transfer current iT and a charging current supplying all charge storage elements connected to the collector terminal. Since the latter elements are described and represented separately in a model, a formulation of iT, which equals IC under d.c. conditions, is of major interest. Before a general relation for iT is derived, a brief historical perspective of the respective theory is given below. The obvious starting point for such an equation is the transport and continuity equation. Since the time derivative term in the latter is taken into account separately by the charge storage elements, and the impact of recombination on iT in modern bipolar transistors is negligibly small, a spatially constant electron current density jnx results (and is observed in device simulation) throughout the structure of a one-dimensional (1D) transistor. This fact can be used to solve the transport equation first for the carrier density and associated charge at a given transfer current, and then reformulate the result to obtain the transfer current at a given charge. The first solution of this kind was published by Moll and Ross in 1956 [1, Equation (13)], exp (V 0 0 =VT ) iT ¼ qmnB n2iB VT R x u B E x l h(x)p(x)dx

(A:3:1)

with p(x) ¼ NB(x), h(x) ¼ 1, VB0 E0 as internal base–emitter voltage, and [xl, xu] as base region. The relation provided a great deal of insight into the dependence of iT (and also the transit time) on doping profile and material parameters in the base region. An improved and more complete expression was later used for one of the first TCAD papers by Ghosh et al. in 1967 [2]. Here, the 2 ) / (mnni2) was included for the first time, but the integral material dependent function h(x) ¼ (mnBniB A.3-1187 © 2006 by Taylor & Francis Group, LLC

A.3-1188

The Silicon Heterostructure Handbook

was evaluated numerically, thus not providing a formulation suitable for compact modeling. Only shortly thereafter, in 1970 Gummel published his well-known paper about the integral charge-control relation (ICCR) [3]. For the first time, a compact formulation for iT was derived, that contained in a consistent relation between iT and stored charge and with all bias-dependent nonideal effects that were relevant for transistors at that time. In one way or the other, the ICCR has been used until today in any reasonably physics-based compact model. Note that the Scharfetter–Gummel discretization, which was first published and applied to a bipolar transistor, also assumes a constant current density between discrete points, which is the main reason for its numerical stability and wide use for device simulation. An extension of the Moll–Ross relation with special emphasis on a spatially variable bandgap in the base layer was derived by Kroemer in 1985 [4]. Here also the doping density was replaced by the biasdependent hole density as in Equation (A.3.1), but no equation suitable for compact modeling was given. In 1993, for both the latter equation and the ICCR a generalization was presented in Ref. [5], with application to compact modeling. The respective generalized ICCR (GICCR) will be discussed in more detail in subsequent sections. During its derivation, the various results mentioned above will be obtained and be referred to again. Since the theories above all apply only to a 1D transistor structure with reasonably smooth material and bandgap changes, and to quasistatic operation, extensions for practical cases are of interest, which will be briefly discussed in A.3.5. The considerations in this chapter apply to Si and SiGe technologies. In the latter, two fundamentally different types of doping profiles can be distinguished which are presently being manufactured and illustrated schematically in Figure A.3.1. The conventional emitter doping (CED) type has a similar profile shape as BJTs, but contains in addition a Ge distribution that increases from the BE junction to the BC junction. In contrast, the low-emitter concentration (LEC) type contains a box Ge profile (or at least a sufficiently high step at the BE junction) that allows to significantly increase the base doping and to lower the emitter doping.

A.3.2

Derivation of a General Relationship

Although the GICCR can be derived for the 3D case, the considerations here will be restricted to the 1D case in order to demonstrate the concept. The assumptions required for the derivation are summarized below: (a) A one-dimensional transistor structure (cf. Figure A.3.1) is considered, with the emitter contact (x ¼ 0) at the mono-silicon surface and the collector contact (x ¼ xC) at the transition from the lightly-doped collector region to the buried layer. This 1D structure does not include the emitter and external collector series resistance. (b) Volume recombination within the above 1D transistor region is negligible. (c) The time derivative is negligible, which corresponds to quasistatic operation. (d) Effects such as thermionic emission and tunneling across the junctions are neglected. They can be accounted for though by separate terms and can be combined with the GICCR solution. Assumptions (a), (b), and (c) together with the electron continuity equation lead to a spatially independent electron current density, Jn ¼ const(x) ¼ JT ¼

IT , AE

(A:3:2)

which can be expressed by the transfer current and area (emitter) AE of the 1D-transistor. The derivation starts with the electron transport equation,

© 2006 by Taylor & Francis Group, LLC

A.3-1189

Integral Charge-Control Relations

0 xe0

N

NE

N

xc0 Wbm

x⬘

mx mGe

NB

NB mGe mp

NC

0

xjC

xjE

NC

NE

xC x

xjC

xjE

0

(a)

xC

x

(b)

FIGURE A.3.1 Sketch of doping and Ge profiles for (a) CED transistors and (b) LEC transistors.

Jn ¼ qmn n

dwn dx

(A:3:3)

where mn, n and wn are the electron mobility, density, and quasifermi potential. Inserting n ¼ ni exp[(c wn) / VT] into (A.3.3) gives c wn dfn exp : Jn ¼ qmn ni exp VT VT dx

(A:3:4)

Note that the effective intrinsic carrier density ni accounts for bandgap differences caused by highdoping effects and bandgap-engineering. This topic will be discussed later. Using the transformation d exp (wn =VT ) 1 w dwn ¼ exp n dx VT VT dx

(A:3:5)

c d exp (wn =VT ) Jn ¼ qVT mn ni exp : VT dx

(A:3:6)

leads to

Separation of the differential variables and rearranging terms gives Jn c w exp dx ¼ d exp n : VT qVT mn ni VT

(A:3:7)

Extension of the l.h.s. by the product ni exp(wp/VT) allows to replace the inconvenient term exp(c/VT) by the hole density, yielding Jn p wn dx ¼ d exp : qVT mn n2i exp (wp =VT ) VT Integration of the above equation over the general spatial interval [xl, xu] gives

© 2006 by Taylor & Francis Group, LLC

(A:3:8)

A.3-1190

The Silicon Heterostructure Handbook

xðu xl

Jn exp (wp =VT ) p dx ¼ qVT mn n2i

exp (wnð (xu )=VT )

w d exp n : VT

(A:3:9)

exp (wn (xl )=VT )

The result for the r.h.s. is exp (wnð (xu )=VT )

w w (xu ) w (xl ) ¼ exp n exp n : d exp n VT VT VT

(A:3:10)

exp (wn (xl )=VT )

The exact value of wn on the r.h.s. depends on the choice of the integration limits and will be discussed later. First though, the left-hand-side of (A.3.9) is integrated, xðu xl

Jn exp (wp =VT ) JT exp (VB0 E0 =VT ) p dx ¼ 2 qVT mnr n2ir qVT mn ni

xðu

h(x)p(x)dx,

(A:3:11)

xl

with h ¼ hghihw as the normalized weighting function of the hole density, and its components hg ¼

mnr n2ir , mn (x)n2i (x)

hi ¼

Jn (x) , JT

VB0 E0 wp (x) : hw ¼ exp VT

(A:3:12)

mnr and nir are the mobility and intrinsic carrier density, respectively, of a reference material. Equating (A.3.10) with (A.3.11), and solving for the desired transfer current yields the ‘‘master’’ equation h i exp VVB0TE0 exp wnV(xT l ) exp wnV(xT u ) Ð xu , JT ¼ qVT2 mnr n2ir x l hg hi hw pdx

(A:3:13)

from which different analytical formulations can be derived. The choice of the reference material (or transistor region) and its associated values for mnr n2ir is arbitrary and will be discussed later. The integration interval is undefined yet, and so is the impact of the various weighting functions on the integral. An attractive choice for the integration limits is [0, xC], which corresponds to the entire 1D transistor region. As a result of this choice, the electron quasifermi potentials in the numerator assume their known internal terminal values (e.g., for common-emitter configuration), wn (xl ) ¼ wn (0) ¼ 0 and

wn (xu ) ¼ wn (xC ) ¼ VC0 E0 ,

(A:3:14)

with VC0 E0 as (internal) collector–emitter voltage. The denominator integral is more difficult to oversee. Thus, Figure A.3.2 shows the spatial dependence of the weighting functions with the hole density superimposed. Since the hole quasifermi potential equals VB0 E0 over the entire base and adjacent space–charge regions, hw equals 1 where p(x) is significant. Similarly, the electron current density is constant and equals JT even in a larger interval, except in a small region close to the emitter contact, where it increases slightly due to the back injection of holes and the corresponding recombination; the maximum deviation can be 1/Bf. Therefore, without introducing a significant error, it is possible for both BJT and HBT to assume an average value for the functions hi and hw that is very close to 1. According to Figure A.3.2, the main spatial dependence of the weighting function h is caused by hg via the bandgap variation of ni. A smaller contribution to the spatial dependence comes from the doping and field dependence of the mobility.

© 2006 by Taylor & Francis Group, LLC

A.3-1191

Integral Charge-Control Relations

1.2 hi h, p (normal.), hp (normal.)

1

p

hϕ, hi

0.8 hg 0.6 hg*p

0.4

0.2

0 0 xje

0.05 xjc

(a)

0.1 x (µm)

0.15

0.2

1.2 hi h, p (normal.), hp (normal.)

1 hϕ, hi 0.8 p hg

0.6

hg*p 0.4

0.2

0 (b)

0

xje

0.05

xjc

0.1 x (µm)

0.15

0.2

FIGURE A.3.2 Spatial dependence of the weighting functions for a CED transistor with the same doping profile: (a) 70 GHz BJT without Ge; (b) 120 GHz HBT with Ge. Bias point (JC ¼ JT,VB0 C0 ) ¼ (0.1 mA/mm2, 0 V). The hole density p, weighting function hg, and their product hgp have been normalized to the respective maximum value. xje and xjc denote the emitter and base junction depth.

Inserting (A.3.14) and hg from (A.3.12) into (A.3.13), extension by q as well as using average values hi and hw yields the basic formulation m n2 exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) Ðx JT ¼ q2 VT nr ir : q 0 C hg pdx hi hw

(A:3:15)

from which practically relevant equations can be derived as shown later. The denominator is not yet suitable for (compact) modeling, but at this point can be prepared for further evaluation by partitioning it into a bias-independent and a bias-dependent portion

© 2006 by Taylor & Francis Group, LLC

A.3-1192

The Silicon Heterostructure Handbook

ð xC q

hg pdx ¼ q

ð xC

0

hg p0 dx þ q

0

ð xC hg Dpdx,

(A:3:16)

0

where p0 is the hole density in equilibrium and Dp is the hole density change in the transistor with respect to equilibrium. Dp consists of depletion and minority components. While the latter density is distributed over the whole base region, the former densities are located around the junctions and related to the (ionized) base doping.

A.3.3

Homojunction Transistors

In homojunction transistors, the variation of hg is only caused by high-doping effects. Thus, hg is fairly constant in the region around the peak hole density (cf. Figure A.3.2a), which contributes most to the integral. Defining an average value 2

m n hg ¼ nr 2ir , mn ni

(A:3:17)

the denominator of (A.3.15) becomes ð xC q xE

mnr n2ir p p(x)dx ¼ hg Q mn n2i

(A:3:18)

with the hole charge per area stored in the 1D transistor structure, p ¼ q Q

ð xC p(x)dx :

(A:3:19)

0

Inserting (A.3.18) and (A.3.19) into (A.3.15) yields JT ¼ c

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p Q

(A:3:20)

which has the same form as Gummel’s ICCR in Ref. [3], but a different definition of the integration region and, thus, of the charge and controlling voltages. The factor m n2ir c ¼ q2 VT nr ﬃ q2 VT mn n2i hi hw hg

(A:3:21)

is assumed to be constant over bias. Usually, the most right term is used only, which is obtained by setting hi ¼ hw ¼ 1 and is an excellent assumption for the 1D case. Since the hole density is concentrated mostly in the base, the value for hg and mn n2i is close to that for the base material. The charge in (A.3.19) can be divided into a bias-independent and a bias-dependent component, Q p ¼ Q p0 þ DQ p. The bias-independent charge Q p0 is defined at VB0 E0 ¼ VB0 C0 ¼ 0 and consists of holes stored mostly in the neutral base region 0 x 0 wB0 at equilibrium: p0 ¼ q Q

ð xC 0

p0 (x)dx ﬃ q

ð wB0 0

p0 (x 0 )dx 0 q

ð wB0

NB (x 0 )dx 0 :

(A:3:22)

0

(Note the use of a different coordinate x 0 in the neutral base region, cf. Figure A.3.1b.) The biasdependent charge component represents all holes, Dp, that for a nonequilibrium bias condition enter the

© 2006 by Taylor & Francis Group, LLC

Integral Charge-Control Relations

A.3-1193

base region (i) to charge the depletion regions, (ii) to compensate the electrons injected into the (neutral) base, and (iii) for the injection into emitter and collector, p ¼ q DQ

ð xC

pE þ Q jE þ Q nB þ Q jC þ Q pC Dp(x)dx ¼ Q

(A:3-23)

0

Here, Q jE and QjC are the BE and BC depletion charge (per unit area), respectively, and the other components are the minority charges (per unit area) stored in E, B, and C. As a consequence of the choice of the chosen integration limits, DQp can actually be measured via the terminals. From a physicsbased point of view, the biggest advantage of the extended ICCR (A.3.20) is its firm link between the quasistatic transfer current and the total hole charge, which resembles the charge-controlled operation principle of a bipolar transistor in a very compact form. Examples for the accuracy of various solutions are shown in Figure A.3.3 for a typical Gummel plot. In all cases, the denominator integral (e.g. Q p in (A.3.20)) has been taken directly from device simulation. As expected, the basic equation (A.3.15) follows exactly the simulated behavior of JT (crosses). For the older generation profile (‘‘25 GHz transistor’’ in Figure A.3.3a), the practically interesting approximation (A.3.20) is very accurate at low and medium current densities, and shows only slight deviations at high current densities, which are tolerable though and typical for homojunction bipolar processes (e.g. [6, 7]). The reason for these small deviations is caused by the assumption of a bias-independent value for hg. However, if the minority charge contributions of emitter and collector, Q pE and Q pC, are neglected in (A.3.20), the model current becomes far too large. Thus, including only the base charge is not a feasible approach. For the profile of a modern generation Si(Ge) transistor (‘‘70 GHz BJT’’ in Figure A.3.3b), Equation (A.3.20) starts to deviate already at medium current densities, affecting the accuracy of the transconductance modeling. This is caused by the increased difference in doping and associated variation of hg across the base region, which requires a different weighting factor for Qp0 and QjE along the same lines as discussed in the next section on HBTs, applying the corresponding equation (A.3.28) gives again a much higher accuracy. The assumption of a bias-independent value for hg deserves some consideration. High-doping effects cause both ni and mn (which is also field dependent) to depend on x within the base region, with the change of ni partially being compensated by the change of mn. Obviously though, as long as the spatial distributions of p and mn n2i do not change with bias, hg remains bias independent. This holds quite well for low and medium current densities where p is concentrated in the base region, and the mobility depends only very slightly on bias. Toward high current densities, however, p spreads out into the collector and partially also into the emitter region. In the collector, for instance, high-doping effects can be neglected but the field (and thus bias) dependence of mn is significant, leading to a different weighting of the hole density in this region. As a consequence, the average value hg defined at low current densities is not quite correct anymore at high current densities and causes the observed small deviation from the exact current. Note though that the field dependence of the mobility around the BC junction decreases at high current densities. At this point, the choice of the integration limits shall be briefly discussed. Fundamentally, there is an infinite number of possible integration intervals. Besides the one selected above (i.e., entire 1D transistor), the other most important choice in literature (e.g., Refs. [3, 4]) is the base region, i.e., x 2 [xjE,xjC]. In this case, hg is only a very weak function of bias, but there are serious disadvantages of this choice: (i) the unknown values for the electron quasi-fermi potentials at the base region boundaries, i.e., wn(xjE) and wn(xjC) in the numerator of (A.3.13), are not easily accessible by measurements; (ii) a separate determination (i.e., measurement) of the base hole charge, in particular the base minority charge, is difficult at medium to high current densities. The original and most famous expression of the ICCR as given by Gummel in Ref. [3], which has the same form as (A.3.20), is in fact based on considering only the base region for the integration and assuming contributions from outside that region to be negligible. Although this was a reasonable assumption at that time for the charge, it was not for the voltage drop toward the contacts.

© 2006 by Taylor & Francis Group, LLC

A.3-1194

The Silicon Heterostructure Handbook

102

(a)

101

JC (mA/µm2)

100 10−1 X XX X XX X

10−2

XX X X X XX X 10−4 X XX XX 10−5 0.6 0.65 0.7 0.75

XXX XXX X X X XX XXXX XX X X X X X X XXXX XXXX X X X X X X X

10−3

0.8 0.85 VBE (V)

0.9

0.95

1

102

(b)

101

X

X X X

JC (mA/µm2)

100 10−1 10−2 10−3 10−4 10−5 0.6

0.65

0.7

0.75

0.8 0.85 VBE (V)

0.9

0.95

1

FIGURE A.3.3 Transfer current density for (a) 25 GHz BJT and (b) 70 GHz BJT: comparison between device simulation (symbols) and analytical calculations from Equation (A.3.15) (solid line), Equation (A.3.24) (dotted line), Equation (A.3.20) (dashed line), as well as Equation (A.3.20) without QpE þ QpC as dash-dotted line in (a) and (A.3.28) as dash-dotted line in (b). The arrow indicates the current density at which the fT peak occurs.

An often found further simplification is to replace the hole density in (A.3.19) by the base doping density NB. As a consequence, the hole charge equals the expression on the most r.h.s. of (A.3.22) and does not contain any bias-dependent ‘‘nonideal’’ effects anymore. Neglecting the voltage drops toward the contacts, Moll and Ross [1] first derived the corresponding expression for the transfer current JT ¼ qVT mnB n2iB

exp (VB0 E =VT ) exp (VB0 C0 =VT ) Ð WB 0 0 NB dx

(A:3:24)

This is a more general relation compared to the classical transistor theory along the lines of Ebers and Moll [9], and aided the understanding that the transfer current is linked to the integral of the base

© 2006 by Taylor & Francis Group, LLC

A.3-1195

Integral Charge-Control Relations

doping and not to some spot value. As shown in Figure A.3.2, Equation (A.3.24) produces an almost ideal characteristic due to the missing bias-dependent charge components.

A.3.4

Heterojunction Transistors

A comparison for the weighting function hg between a SiGe and a Si transistor with the same doping profile was already shown in Figure A.3.2. While the spatial dependence of the hole QFP and electron current density and, thus, of hw and hi is still similar to BJTs, the intentional bandgap differences in HBTs lead to additional variations of ni2 within the integration interval [0,xC]. As a consequence, it is impossible to define a single average value hg over this whole interval. Thus, the denominator integral in (A.3.15) now has to be formulated in terms of charge components in separate transistor regions that are multiplied with an average value of the weighting function hg taken over the respective region. In HBTs the transition from one bandgap value to another usually takes place close to the junctions. Therefore, Ðxc partitioning of the respective integral q hg pdx into neutral and space–charge regions is one reasonable 0

choice in order to obtain separate expressions, in which the weighting function is sufficiently independent on location and bias. This leads generally to ð xC q

p0 þ hg,E Q pE þ hg,jE Q jE þ hg,B Q nB þ hg,jC Q jC þ hg,C Q pC hg pdx ¼ hg,B0 Q

(A:3:25)

0 2

with

m n hg,v ¼ n0r ir mnv n2iv

and

v ¼ {B0, E, jE, B, jC, C}:

(A:3:26)

Choosing the base region as reference and assuming hg,B ¼ hg,B0, all weighting factors can be divided by hg,B giving for the normalized remaining weighting factors hg,v m n2 hv ¼ ¼ nB iB hg,B mnv n2iv

with

v ¼ {E, jE, jC, C},

(A:3:27)

which are considered to be model parameters. Inserting the above expression and charge components into (A.3.15), and making again the valid assumption hi ¼ hw ¼ 1 yields the GICCR as the final expression for 1D-HBTs [5] JT ¼ q2 VT mnB n2iB

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p,T Q

(A:3:28)

with the modified (‘‘transfer current related’’) charge density p,T ¼ Q pE þ hjE Q jE þ Q jC þ hC Q pC , p0 þ DQ p,T ¼ Q p0 þ hE Q nB þ hjC Q Q

(A:3:29)

in which — as for BJTs — still a bias-independent hole charge, Qp0, and a bias-dependent portion can be distinguished. According to Refs. [5, 8], and also as Figure A.3.4 shows, (A.3.28) with (A.3.29) using bias-independent values for hn leads to a significant improvement over the conventional ICCR (A.3.20). Thus, the GICCR results in an accurate description of the transfer current characteristics and the respective derivatives over the entire bias range of interest (up to high current densities). Again, as in Figure A.3.3, the charges and weighting factors have been calculated directly from device simulation results to avoid any errors introduced by analytical approximations. For ‘‘ideal’’ doping profiles like in Figure A.3.1, the weighting factors hn in (A.3.2) can be calculated analytically using (A.3.15). This aids the physical understanding of the impact of the Ge profile on device characteristics and shall be demonstrated below for two Ge profile examples. However, the calculation can be extended to other profiles but just becomes more elaborate.

© 2006 by Taylor & Francis Group, LLC

A.3-1196

The Silicon Heterostructure Handbook

101

JC (mA/µm2)

100

10−1

10−2

10−3 X X 0.6

X

X

X

X

X

0.65

X

X

X

X

X

0.7

X

X

X

X

X

X

XXXXXXXXXX XX XX XX XX

0.75 VBE (V)

0.8

0.85

FIGURE A.3.4 Transfer current density for the 120 GHz HBT: comparison between device simulation (symbols) and analytical calculations from Equation (A.3.15) (solid line), Equation (A.3.28) (dashed line), Equation (A.3.24) (dotted line), and Equation (A.3.28) without QpE þ QpC (dash-dotted line).

Box Ge Profile in the (Metallurgical) Base Region In this case, mn n2i is constant over the base region and the portion of the space–charge regions that are associated with the base. For the sake of simplicity, low injection is assumed first. Setting mnr n2ir ¼ mnB n2iB yields hg ¼ 1 already in the integral over the base region and, thus, hjE ¼ hjC ¼ 1. In the emitter and collector region, hE ¼ mnB n2iB =mnE n2iE >> 1 and hC ¼ mnB n2iB =mnC n2iC >> 1, respectively, due to the much larger bandgap in those regions. As a consequence of this bandgap, the hole charges Q pE and Q pC are very small and do not significantly impact the dynamic transistor behavior, regardless of the respective doping profile. However, according to (A.3.28) these charges can have a significant impact on the transfer current due to the large weighting factors hE and hC. The respective terms hE QpE and hC QpC in (A.3.28) actually cause the ‘‘saturation’’ of the IC(VBE) characteristics at high injection observed in Figure A.3.2b. In HBTs with a box Ge profile, Equation (A.3.28) can be simplified to [5] exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT mnB n2iB pE þ (hC 1)Q pC , Qp þ (hE 1)Q

(A:3:30)

which contains the total hole charge as a lumped variable and correction factors in the denominator. In pC is described directly by a compact expression rather than separately by Ref. [8], the product (hC 1)Q the weighting factor and charge component.

Trapezoidal Profile in the (Metallurgical) Base Region Consider the Ge profile in Figure A.3.1b. For the sake of simplicity it is assumed that the Ge mole fraction mGe and the respective bandgap voltage increase over the width of the neutral base (x0 2 [xe0,xc0]) only, but stay constant across the space–charge regions. Choosing the Si-base without Ge contents as reference material, the bandgap voltage differences DVGp ¼ DVG(x0 ¼ xe0) and DVGx ¼ DVG(x0 ¼ xc0), respectively, can be defined. Hence, the intrinsic carrier density within the neutral base with the width wB0 ¼ xc0 xe0 can be written as

© 2006 by Taylor & Francis Group, LLC

A.3-1197

Integral Charge-Control Relations

DVGp þ aG (x 0 xe0 ) n2i ¼ n2iB,Si exp VT

(A:3:31)

with the slope factor aG ¼ (DVGx DVGp)/wB0. Neglecting the (much smaller) dependence of the mobility on field and Ge contents, and applying the above relation to (A.3.16) with p0 ¼ NB yields for the bias-independent term xðC

q 0

mnr n2ir p0 dx 0 ﬃ q mn n2i

xðc0 xe0

DVGp þ aG (x 0 xe0 ) NB dx 0 exp VT

(A:3:32)

which gives after evaluating the r.h.s. integral xðC

q 0

mnr n2ir mn n2i

p0 dx 0 ﬃ

VT aG

h i DV Gx exp VTGp exp DV VT wB0

p0 ¼ hg,B0 Q p0 Q

(A:3:33)

p0 ¼ qNB wB0 . As can be seen, the average weighting factor depends exponentially on the bandgap with Q voltages at the beginning and the end of the neutral base. For the bias-dependent portion in (A.3.16), one can write at low current densities xðC

q

2 6 hg Dpdx ﬃ q4

xðe0 xe

0

exp

N B dx 0 þ DVGp VT

xðc xc0

xðjC

3

N n B dx 0 þ dx 0 7 5 ~xe0 ) DVGp þaG (x 0 n DVGx ~ exp n exp VT VT x

(A:3:34)

jE

The first two terms represent the depletion components that are only to be evaluated between the SCR boundary (i.e., xe, xc) at the given bias point and the respective equilibrium SCR boundaries (i.e., xe0, xc0); it also has been assumed that the bandgap (i.e., Ge mole) change within (xe0xe) and (xc0xc) is jC ¼ qNB (xc xc0 ). For jE ¼ qNB (xe0 xe ) and Q still negligible. The resulting depletion charges are Q the case that the electric field in the base due to Ge grading causes the electrons to travel with saturation drift velocity vs , i.e. n ¼ JT/(qvs) does not depend on x0 , the resulting base minority charge is then Q nB ¼ JT wB/vs. With these charge expressions, one obtains after evaluating all terms on the r.h.s. of (A.3.34) xðC

q 0

DVGp DVGx nB , QjE þ exp QjC þ hg,B0 Q hg Dpdx ﬃ exp VT VT

(A:3:35)

where the last term follows the same evaluation as (A.3.32). The final step is to insert the components in (A.3.33) and (A.3.35) back into (A.3.15) and to normalize the denominator to the base weighting factor, hgB0 given by Equation (A.3.33). The resulting expression then reads mnB,Si n2iB,Si exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT jE þ hjC Q jC þ Q nB : p0 þ hjE Q hi hw hg ,B0 Q |ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ} c10

(A:3:36)

which has the same form as (A.3.28), but for low current densities and with known analytical expressions of the weighting factors from the above analysis: DV exp VTGp v exp (v) , ¼ hjE ¼ exp (v) 1 hg,B0

© 2006 by Taylor & Francis Group, LLC

Gx exp DV VT v hjC ¼ : ¼ exp (v) 1 hg,B0

(A:3:37)

A.3-1198

The Silicon Heterostructure Handbook

with v ¼ [DVGX DVGP]/VT as normalized bandgap difference between beginning and end of the base region (cf. Figure A.3.1b) . The dependence of the weighting factors as a function of v is shown in Figure A.3.5 for a practically relevant range. From the above results, the forward Early voltage at low injection, can be calculated: VEf ¼

p p0 exp (v) 1 Q Q : v hjC CjCi CjCi

(A:3:38)

According to (A.3.37), a 20% difference in Ge across the base region corresponds to an about 40 times increase in Early voltage, which is a significant enhancement factor over a Si-BJT or a SiGe HBT with a Ge box profile (v ¼ 0). In addition to the strong variation in ni, the mobility varies within the transistor as a function of both doping and bias (via the electric field). The variation caused by the latter is most pronounced in the BC junction and collector region. In general, mn and ni possess an opposite dependence on doping, leading to a partial compensation within hg. However, the influence of ni still remains much stronger than that of mn. As a consequence, the weighting function hg always deviates strongly from 1 and has to be considered for all processes.

A.3.5

Further Extensions

All of the considerations so far apply to a 1D transistor structure and quasistatic operation. Extensions in both directions have been investigated and proposed. A solution of the time-dependent continuity equation led to the transient ICCR (TICC) [10], in which the ‘‘in-phase’’ component gives the same expression as the ICCR for the for q.s. transfer current, while the ‘‘out-of-phase’’ solution yields a physical definition of the charging currents flowing through the E and C contact. Hence, the out-ofphase solution defines a physics-based capacitance matrix associated with the E and C terminals, that includes the case of non-quasistatic operation. Extensions of the TICC towards including recombination and non-1D effects were presented in, for example, Ref. [11]. The application of the TICC results in a compact model, however, is quite challenging due to the bias-dependent weighting functions in the integrals defining the charging components.

6 5

hjE, hjC

4 hjE 3 2 1 hjC 0

0

1

2

3 v

4

5

6

FIGURE A.3.5 Weighting factors of the depletion charges according to Equation (A.3.37) as a function of the normalized bandgap difference v ¼ (DVGx DVGp)/VT .

© 2006 by Taylor & Francis Group, LLC

A.3-1199

Integral Charge-Control Relations

As shown in Ref. [7], it is possible to extend the GICCR to two- and three-dimensional transistor structures. The respective derivation is beyond the scope of this chapter, but the result shall be briefly discussed. For instance, the resulting 2D-GICCR reads h i Bcon ) exp (VB0 E0 =VT ) exp (VB0 C0 =VT 2(yBconbþb þ 2bbBcon E E , (A:3:39) IT ¼ c10 Qp0,T þ DQp,T where the constant c10 depends on an enlarged (effective) emitter width bE ¼ bE0 þ 2

ð yBcon bE0 =2

wn (x ¼ 0,y) dy: exp VT

(A:3:40)

bE0 is the emitter window width, yBcon is the edge of the base contact or polysilicon next to the emitter, and bBcon is the base contact or polysilicon width on mon-silicon. DQp,T is defined as in (A.3.29), but now includes, among others, the impact of electron current crowding. This also applies to Qp0,T, which introduces a bias-dependent geometry dependence at higher current densities. In practice, Qp0,T can be approximated by a constant value to first order.

A.3.6

Summary

A set of integral charge-control relations has been derived and put in perspective to the (classical) literature. It was shown that a ‘‘master’’ equation exists, from which integral charge-control relations of different complexity and accuracy can be derived. The most general form, that is suitable for accurately describing the transfer current in a compact model for HBTs and BJTs, is the GICCR, which includes bandgap differences in the various device regions and also contains the weakest assumptions among the known theories for the transfer current. The GICCR is a powerful tool to analytically derive the relationship between transfer current, stored charges, and physical as well as structural parameters of a transistor. The GICCR can be very accurate, provided that the respective weigthing factors as a function of device structure and the hole charge as a function of bias are accurately modeled. Notice that the latter is a prerequisite for the description of high-speed applications in any way. Also, since the hole charge has to be continuously differentiable with respect to bias, the transfer current is also automatically continuously differentiable over all bias regions and, hence, is modeled via a single-piece formulation. This is a very desirable feature of the (G)ICCR for compact models. Applying the ‘‘master’’ equation to compact modeling requires partitioning of the hole charge and analytical approximations for its various components. These measures as well as the determination of charge model parameters and appropriate weighting factor values introduce additional inaccuracies with respect to the results shown here, which are unavoidable though for any compact model equation.

Acknowledgments The author would like to thank H. Tran for performing simulations and model calculations.

References 1. J.L. Moll and J.M. Ross, The dependence of transistor parameters on the distribution of base layer resistivity, Proc. IRE, 44, 1956, S72–S78. 2. H.N. Ghosh, F.H. De La Moneda, and N.R. Dono, Computer-aided transistor design, characterization, and optimization, Proc. IEEE, 55, 1967, 1897–1912. 3. H.K. Gummel, A charge-control relation for bipolar transistors’’, Bell System Technical J., 49, 1970, S115–S120.

© 2006 by Taylor & Francis Group, LLC

A.3-1200

The Silicon Heterostructure Handbook

4. H. Kroemer, Two-Integral equations pertaining to the electron transport through a bipolar transistor with nonuniform energy gap in the base region, Solid-State Electron., 28, 1985, 1101–1103. 5. M. Schroter, M. Friedrich, and H.-M. Rein, A generalized integral charge-control relation and its application to compact models for silicon based HBTs, IEEE Trans. Electron Dev., 40, 1993, 2036– 2046. 6. H.-M. Rein, H. Stu¨bing, and M. Schroter, Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities, IEEE Trans. Electron Dev., 32, 1985, 1070– 1076. 7. M. Schroter, A compact physical large-signal model for high-speed bipolar transistors with special regard to high current densities and two-dimensional effects, PhD thesis (in German), RuhrUniversity Bochum, Bochum, Germany, 1988. 8. M. Friedrich and H.-M. Rein, Analytical current–voltage relations for compact SiGe HBT models, IEEE Trans. Electron Dev., Vol. ED-46, 2001, 1384–1401. 9. J.J. Ebers and J.L. Moll, Large-signal behavior of junction transistors, Proc. IRE, 42, 1761–1772, 1954. 10. H. Klose and A. Wieder, The transient integral charge–control relation — a novel formulation of the currents in a bipolar transistor, IEEE Trans. Electron Dev., ED-34, 1090–1099, 1987. 11. J.S. Hamel and C.R. Selvakumar, The general transient charge–control relation: a new charge– control relation for semiconductor devices, IEEE Trans. Electron Dev., ED-38, 1467–1476, 1991.

© 2006 by Taylor & Francis Group, LLC

A.4 Sample SiGe HBT Compact Model Parameters

Ramana M. Malladi IBM Microelectronics

This appendix contains a sample set of compact model parameters for a representative 0.3216.8 mm2 first-generation npn SiGe HBT with a peak fT of 50 GHz, for each of the three dominant higher-order SiGe compact models available in the public domain and in leading circuit simulators: HICUM, MEXTRAM, and VBIC. Each model was carefully calibrated to a comprehensive set of measured dc and ac data.

A.4-1201 © 2006 by Taylor & Francis Group, LLC

A.4-1202

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters Group

Name

Parameter Description

Value

Transfer current

c10 qp0 ich hjei hjci mcf hfe hfc

Constant for ICCR (= Is.qp0) Zero-bias hole charge in the base High-current correction to account for 2D and 3D effects BE depletion charge weighting factor for HBTs BC depletion charge weighting factor for HBTs Forward nonideality factor for transfer current for HBTs Emitter minority charge weighting factor for HBTs Collector minority charge weighting factor for HBTs

8.51031 A2 S 1.41013 C 10 A 2 0.1 1 1 0.2

Base–emitter currents

ibeis mbei ibeps mbep ireis mrei ireps mrep

Internal BE sauration current Internal BE non-ideality factor Peripheral BE saturation current Peripheral BE non-ideality factor Internal BE saturation current (recombination) Internal BE non-ideality factor (recombination) Peripheral BE saturation current (recombination) Peripheral BE non-ideality factor (recombination)

71020 1.005 71022 1 11017 2 11020 2

Base–collector currents

ibcis mbci ibcxs mbcx

Internal BC saturation current Internal BC saturation current ideality factor External BC saturation current External BC saturation current ideality factor

1.51018 A 1.02 21019 A 2

Base–emitter tunnelling current

ibets abet

BE tunneling saturation current BE tunneling factor

11021 A 36

Base–collector avalanche current

favl qavl

Avalanche current factor Exponent for avalanche current

19.3 V1 1501015 C

Series resistances — base, emitter, and collector

rbi0 rbx fdqr0 fgeo fqi fcrbi

Internal base resistance at zero bias Extrinsic base resistance Correction factor for modulation by BE and BC SCR Geometry factor for current crowding Ratio of internal to total minority charge Ratio of shunt capacitance (parallel to Rbi) to total internal capacitance

20 V 6V 0.2 0.67 1.0 0

Emitter

re

Emitter series resistance

3V

A A A A

rcx

Extrinsic collector series resistance

23 V

Substrate transistor

iscs

CS diode saturation current

41021 A

© 2006 by Taylor & Francis Group, LLC

The Silicon Heterostructure Handbook

Collector

1 2.51019 A 1 1 21012 sec

Substrate network

rsu csu

Substrate resistance Substrate capacitance

50 V (layout dependent) 31018 F

Self-heating

rth cth

Thermal resistance Thermal capacitance

700 K/W 350 pJ/K

Base–emitter junction capacitance

cjei0 vdei zei aljei cjep0 vdep zep aljep ceox

Internal zero-bias BE depletion capacitance Internal BE built-in voltage Internal BE grading coefficient Maximum internal depletion capacitance divided by cjei0 Peripheral zero-bias BE depletion capacitance Peripheral BE built-in voltage Peripheral BE grading coefficient Maximum peripheral depletion capacitance divided by cjep0 Emitter oxide (overlap) capacitance

351015 F 1.0 V 0.32 2.0 51015 F 1.0 V 0.32 2.2 181015 F

Base–collector junction capacitance

cjci0 vdci zci vptci cjcx0 vdcx zcx vptcx ccox fbc

Internal zero-bias BC depletion capacitance Internal BC built-in voltage Internal BC grading coefficient Punch-through voltage of internal BC junction External zero-bias BC depletion capacitance External BC built-in voltage External BC grading coefficient Punch-through voltage of external BC junction BC overlap capacitance Partitioning factor for cjcx and ccox over rbx

71015 F 0.7 V 0.3 2.5 V 301015 F 0.73 V 0.4 100 V 2.51015 F 0.8

Collector–substrate junction capacitance

cjs0 vds zs vpts

Zero-bias CS depletion capacitance CS built-in voltage CS grading coefficient Punch-through voltage of CS junction

401015 F 0.6 V 0.3 11010 V

Diffusion capacitances/transit times — low currents

t0 dt0h tbvl

Low current forward transit time at Vcb ¼ 0 V Time constant for base and BC space charge layer width modulation Time constant for modeling carrier jam at low Vce

2.61012 sec 0.91012 sec 0.71012 sec

High currents

tef0 gtfe

Neutral emitter storage time Exponent for current dependence of neutral emitter storage time

401015 sec 1.0 (Continues)

© 2006 by Taylor & Francis Group, LLC

A.4-1203

CS diode non-ideality factor Transfer saturation current of substrate transistor Forward non-ideality factor of substrate transfer current Reverse non-ideality factor of substrate transfer current Transit time (forward operation) — substrate

Sample SiGe HBT Compact Model Parameters

msc itss msf msr tsf

Parameter Description

Value

thcs alhc fthc vces rci0 vlim vpt tr

Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Factor for partitioning this into base and collector portion Internal C-E saturation voltage Internal collector resistance at low electric field Voltage separating ohmic (low field) and saturation velocity (high field) regime Collector punch-through voltage Storage time for inverse operation

251012 sec 0.53 0.6 0.1 V 20 V 0.7 V 15 V 201012 sec

Non-quasistatic effects

alqf alit

Factor for additional delay time of minority charge Factor for additional delay time of transfer current

0.125 0.45

Noise parameters

kf af krbi

Flicker noise factor Flicker noise exponent factor Noise factor for internal base resistance

22106 2.5 1

Temperature effect parameters

tnom vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0

Measurement temperature Bandgap voltage Temperature coefficient of current gain Temperature coefficient of favl Temperature coefficient of qavl Temperature coefficient for mobility in epi-collector (i.e., for collector resitance) Relative temperature coefficient of saturation drift velocity Relative temperature coefficient of vces Temperature coefficient for mobility in internal base (i.e., for internal base resistance) Temperature coefficient for mobility in extrinsic base (i.e., for extrinsic base resistance) Temperature coefficient for mobility in extrinsic collector (i.e., for extrinsic collector resistance) Temperature coefficient for emitter resistance First-order temperature coefficient of t0 Second-order temperature coefficient of t0

25 C 1.17 V 6103 5105 K1 2104 K1 1.6 1103 K1 0.4103 K1 0.6 0.2 0.2 0 1103 K1 1105 K2

© 2006 by Taylor & Francis Group, LLC

The Silicon Heterostructure Handbook

Name

Group

A.4-1204

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters (Continued)

Name

Parameter Description

Value

Forward and reverse currents

is ik bf ibf mlf xibi bri ibr vlr xext

Transistor main saturation current Knee current for high-injection effects in the base Ideal forward current gain Saturation-current of the non-ideal forward base current Non-ideality factor of the non-ideal forward base current Sidewall component of ideal base current Ideal reverse current gain Saturation current of the non-ideal reverse base current Cross-over voltage of the non-ideal reverse base current Partitioning factor for the extrinsic region

51018 A 4.5102 A 95 21017 A 1.545 0 3.77 1.71015 A 1102 V 0.19

Early voltage

ver vef

Reverse Early voltage Forward Early voltage

4.8 V 65 V

Weak avalanche

wavl vavl sfh

Epilayer thickness used in weak-avalanche model Voltage determining curvature of avalanche current Current spreading factor of avalanche model (when exavl ¼ 1)

2.44107 M 0.63 V 1.7

Resistances and quasisaturation

re rbc rbv rcc rcv scrcv ihc axi

Emitter resistance Constant part of the base resistance Zer-bias value of the bias-dependent base resistance Constant part of the collector resistance Resistance of the un-modulated epilayer Space charge resistance of the epilayer Critical current for velocity saturation in the epilayer Smoothness parameter for the onset of quasi-saturation

3.0 V 6V 20 V 17 V 52 V 54 V 3.56103 A 0.21

Base–emitter junction capacitance

cje vde pe xcje cbeo

Zero-bias emitter–base depletion capacitance Emitter–base diffusion voltage Emitter–base grading coefficient Fraction of the emitter–base depletion capacitance that belongs to the side-wall Emitter–base overlap capacitance

421015 F 0.9 V 0.23 0 181015 F

Base–collector junction capacitance

cjc vdc pc xp

Zero–bias collector–base depletion capacitance Collector–base diffusion voltage Colector–base grading coefficient Constant part of cjc

71015 F 0.75 V 0.28 1103 (Continues)

© 2006 by Taylor & Francis Group, LLC

A.4-1205

Group

Sample SiGe HBT Compact Model Parameters

TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters

Parameter Description

Value

mc xcjc cbco

Coefficient for the current modulation of the collector–base depletion capacitance Fraction of the collector–base depletion capacitance under the emitter Collector–base overlap capacitance

0.5 8.7102 2.51015 F

cjs vds ps vgs mtau taue taub tepi taur

Zero-bias collector–substrate depletion capacitance Collector–substrate diffusion voltage Collector–substrate grading coefficient Bandgap voltage of the substrate Non-ideality factor for the emitter stored charge Minimum transit time of stored emitter charge Transit time of stored base charge Transit time of stored epilayer charge Transit time of reverse extrinsic stored base charge

451015 F 0.6 V 0.3 1.17 V 0.388 521015 sec 1.441012 sec 14.41012 sec 201012 sec

HBT parameters

deg xrec

Bandgap difference over the base Pre-factor of the recombination part of ideal base current

0.03 eV 0

Temperature coeffcients

aqbo ae ab aepi aex ac as dvgbf dvgbr vgb vgc vgj dvgte

Temperature coefficient of the zero-bias base charge Temperature coefficient of the resistivity of the emitter Temperature coefficient of the resistivity of the base Temperature coefficient of the resistivity of the epilayer Temperature coefficient of the resistivity of the extrinsic base Temperature coefficient of the resistivity of the buried layer Temperature coefficient for Iss and Iks (for a closed buried layer, as¼ac and for an open buried layer, as¼aepi) Bandgap voltage difference for forward current gain Bandgap voltage difference for reverse current gain Bandgap voltage of the base Bandgap voltage of the collector Bandgap voltage: recombination of the emitter–base junction Bandgap voltage difference of emitter stored charge

0.34 0 1.22 1.88 8.7107 1 0.76 3.75102 V 4.38102 V 1.15 V 1.18 V 1.15V 0.236 V

1/f Noise

af kf kfn

Exponent of the flicker noise Flicker-noise coefficient of the ideal base current Flicker noise coefficient of the non-ideal base current

2.5 22106 201012

Substrate transistor

iss iks

Base-substrate saturation current Base-substrate high-injection knee current

2.51019 A 50 A

Self-heating network

rth cth

Thermal resistance Thermal capacitance

700 K/W 350 pJ/K

Collector–substrate junction capacitance

Diffusion capacitances/transit times

© 2006 by Taylor & Francis Group, LLC

The Silicon Heterostructure Handbook

Name

Group

A.4-1206

TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters (Continued)

Name

Parameter Description

Value

Saturation currents and ideality factors

is ibei iben ibci ibcn isp ibcip ibcnp ibeip ibenp nf nei nen nr nci ncn nfp ncip ncnp

Transport saturation current (collector) Ideal base–emitter saturation current Nonideal base–emitter saturation current Ideal base–collector saturation current Nonideal base–collector saturation current Parasitic transport saturation current Ideal parasitic base–collector saturation current Nonideal parasitic base–collector saturation current Ideal parasitic base–emitter saturation current Nonideal parasitic base–emitter saturation current Forward emission coefficient Ideal base–emitter emission coefficient Nonideal base–emitter emission coefficient Reverse emission coefficient Ideal base–collector emission coefficient Nonideal base–collector emission coefficient Parasitic forwad emission coefficent Ideal parasitic base–collector emission coefficient Nonideal parasitic base–collector emission coefficient

4.851018 A 71020 A 11015 A 1.51018 A 11034 A 31019 A

Knee currents

ikf ikr ikp

Forward knee current Reverse knee current Parasitic knee current

4.5102 A 4.8103 A 10 A

Avalanche breakdown

avc1 avc2

Base–collector weak avalanche parameter 1 Base–collector weak avalanche parameter 2

19.2 23.6 V

Series resistances

rbi rbx rbp re rcx rs

Intrinsic base resistance Extrinsic base resistance Parasitic base resistance Emitter resistance Extrinsic collector resistance Substrate resistance

20 V 6V 1V 3V 23 V 50 V

Self-heating

rth cth

Thermal resistance Thermal capacitance

700 K/W 350 pJ/W

11040 A 2.521018 A 11028 A 1.0003 1.026 2.5 1 1.02 1.00 1.00 1.00 2

(Continued)

© 2006 by Taylor & Francis Group, LLC

A.4-1207

Group

Sample SiGe HBT Compact Model Parameters

TABLE A.4.3 VBIC SiGe HBT Model Parameters

Name

Parameter Description

Value

Quasi-saturation parameters

rci vo gamm hrcf qco

Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Epi-charge parameter

40 V 11010 V 51013 V 11013 1.41015

Early effect parameters

vef ver

Forward Early voltage Reverse Early voltage

65 V 5.5 V

Base–emitter junction capacitance

cje me pe cbeo fc aje

Base–emitter zero-bias capacitance Base–emitter grading coefficient Base–emitter built-in potential Extrinsic base–emitter overlap capacitance Forward bias depletion capacitance limit Base–emitter capacitance switching parameter

42 fF 1.0 0.3 V 181015 F 0.93 0.1

Base–collector junction capacitance

cjc mc pc cbco cjep ajc

Base–collector intrinsic zero-bias capacitance Base–collector grading coefficient Base–collector built-in potential Extrinsic base–collector overlap capacitance Base–collector extrinsic zero bias capacitance Base–collector capacitance switching parameter

71015 F 0.3 0.7 V 2.51015 F 301015 F 0.1

Collector–substrate junction capacitance

cjcp ms ps ccso ajs

Substrate–collector zero bias capacitance Substrate–collector grading coefficient Substrate–collector built-in potential Fixed collector–substrate capacitance Substrate–collector capacitance switching parameter

401015 F 0.3 0.6 V 3e18 F 0.9

Transit times and their bias dependence

tf itf vtf qtf td

Forward transit time Coefficient of tf dependence of ic Coefficient of tf dependence of Vbc Variation of tf with base-width modulation Forward excess-phase delay time

21012 sec 0.32 23.7 0 0.71012 sec

Temperature effect parameters

ea eaie eaic eais eanc

Activation energy Activation energy Activation energy Activation energy Activation energy

1.17 V 1.17 V 1.17 V 1.17 V 1.17 V

© 2006 by Taylor & Francis Group, LLC

for is for ibei for ibci and ibeip for ibcip for ibcn/ibenp

The Silicon Heterostructure Handbook

Group

A.4-1208

TABLE A.4.3 VBIC SiGe HBT Model Parameters (Continued)

Activation energy for iben Activation energy for ibcnp Temperature coefficient for ibei, ibci, ibeip, and ibcip Temperature coefficient for iben, ibcn, ibenp, and ibcnp Temperature coefficient for is Temperature coefficient for re Temperature coefficient for rbi Temperature coefficient for rc Temperature coefficient for rs Temperature coefficient for vo Temperature coefficient for avc2

1.17 V 1.17 V 2.0 2.0 1.9 0 0 0 0 0 250106 V

Sample SiGe HBT Compact Model Parameters

eane eans xii xin xis xre xrb xrc xrs xvo tavc

A.4-1209

© 2006 by Taylor & Francis Group, LLC

A.4-1210

The Silicon Heterostructure Handbook

References 1. HICUM bipolar transistor model: http://www.iee.et.tu-dresden.de/iee/eb/comp_mod.html 2. Mextram bipolar transistor model: http://www.semiconductors.phillips.com/acrobat/other/phillipsmodels/NLUR2000811_7.pdf 3. VBIC bipolar transistor model: http://www.designers-guide.org/VBIC/references.html

© 2006 by Taylor & Francis Group, LLC