Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy

Silicon Heterostructure Handbook Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy

© 2006 by Taylor & Francis Group, LLC

Silicon Heterostructure Handbook Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy

Edited by

John D. Cressler

Boca Raton London New York

A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc.

© 2006 by Taylor & Francis Group, LLC

Published in 2006 by CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2006 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-10: 0-8493-3559-0 (Hardcover) International Standard Book Number-13: 978-0-8493-3559-4 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Catalog record is available from the Library of Congress

Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com Taylor & Francis Group is the Academic Division of T&F Informa plc.

© 2006 by Taylor & Francis Group, LLC

and the CRC Press Web site at http://www.crcpress.com

For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success. I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings. And . . . For Maria: My beautiful wife, best friend, and soul mate for these 22 years. For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts. May your journey of discovery never end.

© 2006 by Taylor & Francis Group, LLC

He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth. Plato ¯Œ
 ı 
Ø 
Ø  łı ı   `ª ªØÆ Ł  ŒÆØ `º ŁØ Æ, ŒÆØ 
Ø `Œ Ł
 ªØÆ  , ‚Æ  Ø  ¢ æÆ æ
  ø ºº Æ Œ
Ø Œł
Ø `ŁÆ
 ŒÆØ ¨

, ¯  æØŁ
   `ºŁ
ØÆ. Pl atvna§

© 2006 by Taylor & Francis Group, LLC

Preface

While the idea of cleverly using silicon–germanium (SiGe) and silicon (Si) strained-layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality. The final success of creating novel Si heterostructure transistors with performance far superior to their Si-only homojunction cousins, while maintaining strict compatibility with the massive economy-of-scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world. In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications. As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations. This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this handbook are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty-first century. While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings-it-all-together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applications. Each chapter is written by a leading international expert, ensuring adequate depth of coverage, up-to-date research results, and a comprehensive list of seminal references. A novel aspect of this handbook is that it also contains ‘‘snap-shot’’ views of the industrial ‘‘state-of-the-art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry. So who should buy this 1,200þ page beast? The Silicon Heterostructure Handbook is intended for a number of different audiences and venues. It should prove to be a useful resource as: 1. A hands-on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications 2. A hands-on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting-edge integrated circuit technologies vii © 2006 by Taylor & Francis Group, LLC

viii

Preface

3. A textbook for use in graduate-level instruction in this field or 4. A reference for technical managers and even technical support/technical sales personnel in the semiconductor industry. It is assumed that the reader has some modest background in semiconductor physics and semiconductor devices (at the advanced undergraduate level), but each chapter is self-contained in its treatment. In this age of extreme activity, in which we are all seriously pressed for time and overworked, my success in getting such a large collection of rather famous people to commit their precious time to my vision for this project was immensely satisfying. I am happy to say that my authors made the process quite painless, and I am extremely grateful for their help. The list of contributors to this handbook actually reads like a global ‘‘who’s who’’ of the silicon heterostructure field, and is impressive by any standard. I would like to formally thank each of my colleagues for their hard work and dedication to executing my vision of producing a lasting Si heterostructure ‘‘bible.’’ In order of appearance, the ‘‘gurus’’ of our field include: Bernard S. Meyerson, IBM Systems and Technology Group, USA Bernd Tillack, IHP, Germany Peter Zaumseil, IHP, Germany Didier Dutartre, ST Microelectronics, France F. Dele´glise, ST Microelectronics, France C. Fellous, ST Microelectronics, France L. Rubaldo, ST Microelectronics, France A. Talbot, ST Microelectronics, France Michael Oehme, University of Stuttgart, Germany Erich Kasper, University of Stuttgart, Germany Thomas N. Adam, IBM Microelectronics, USA Anthony R. Peaker, University of Manchester, United Kingdom V.P. Markevich, University of Manchester, United Kingdom Armin Fischer, IHP, Germany Judy L. Hoyt, Massachusetts Institute of Technology, USA H. Jo¨rg Osten, University of Hanover, Germany C.K. Maiti, Indian Institute of Technology, Kharagpur, India S. Monfray, ST Microelectronics, France S. Borel, CEA-LETI, France Thomas Skotnicki, ST Microelectronics, France David L. Harame, IBM Microelectronics, USA Jin Cai, IBM Thomas J. Watson Research Center, USA Tak H. Ning, IBM Thomas J. Watson Research Center, USA Joachim N. Burghartz, Delft University of Technology, The Netherlands Alvin J. Joseph, IBM Microelectronics, USA James S. Dunn, IBM Microelectronics, USA Paul H.G. Kempf, Jazz Semiconductor, USA Katsuyoshi Washio, Hitachi, Japan Thomas F. Meister, Infineon, Germany H. Scha¨fer, Infineon, Germany W. Perndl, Infineon, Germany J. Bo¨ck, Infineon, Germany Dieter Knoll, IHP, Germany Alain Chantre, ST Microelectronics, France M. Laurens, ST Microelectronics, France B. Szelag, ST Microelectronics, France

© 2006 by Taylor & Francis Group, LLC

Preface

ix

H. Baudry, ST Microelectronics, France P. Chevalier, ST Microelectronics, France J. Mourier, ST Microelectronics, France G. Troillard, ST Microelectronics, France B. Martinet, ST Microelectronics, France M. Marty, ST Microelectronics, France A. Monroy, ST Microelectronics, France Badih El-Kareh, Texas Instruments, USA Scott Balster, Texas Instruments, USA P. Steinmann, Texas Instruments, USA Hiroshi Yasuda, Texas Instruments, USA Roy Colclaser, Philips Semiconductors, USA Peter Deixler, Philips Semiconductors, USA Guofu Niu, Auburn University, USA David R. Greenberg, IBM Thomas J. Watson Research Center, USA Jae-Sung Rieh, Korea University, Korea Greg Freeman, IBM Microelectronics, USA Andres Stricker, IBM Microelectronics, USA Kem Ken (Rim) IBM Thomas J. Watson Research Center, USA Scott E. Thompson, University of Florida, USA Sanjay Banerjee, University of Texas at Austin, USA Soichiro Tsujino, Paul Scherrer Institute, Switzerland Detlev Gru¨tzmacher, Paul Scherrer Institute, Switzerland Ulf Gennser, CNRS-LPN, France Eugene A. Fitzgerald, Massachusetts Institute of Technology, USA Robert Hull, University of Virginia, USA Kang L. Wang, University of California at Los Angeles, USA S. Tong, University of California at Los Angeles, USA H.J. Kim, University of California at Los Angeles, USA Lorenzo Colace, University ‘‘Roma Tre’’, Italy Gianlorenzo Masini, University ‘‘Roma Tre’’, Italy Gaetano Assanto, University ‘‘Roma Tre’’, Italy Wei-Xin Ni, Linko¨ping University, Sweden Anders Elfving, Linko¨ping University, Sweden Douglas J. Paul, University of Cambridge, United Kingdom Robert A. Groves, IBM Microelectronics, USA David C. Sheridan, IBM Microelectronics, USA Jeffrey B. Johnson, IBM Microelectronics, USA Rajendran Krishnasamy, IBM Microelectronics, USA Michael Schro¨ter, University of California at San Diego, USA Slobodan Mijalkovic´, Delft University of Technology, The Netherlands Sue E. Strang, IBM Microelectronics, USA Raminderpal Singh, IBM Systems and Technology Group, USA Youri V. Tretiakov, RF Micro Devices, USA Qingqing Liang, Georgia Institute of Technology, USA Lawrence E. Larson, University of California at San Diego, USA Donald Y.C. Lie, Dynamic Research Corporation and University of California at San Diego, USA Leo C.N. de Vreede, Delft University of Technology, The Netherlands Mark P. van der Heijden, Delft University of Technology, The Netherlands Hermann Schumacher, University of Ulm, Germany Johann-Friedrich Luy, DaimlerChrysler, Germany

© 2006 by Taylor & Francis Group, LLC

x

Preface

John R. Long, Delft University of Technology, The Netherlands Sudipto Chakraborty, Georgia Institute of Technology, USA Joy Laskar, Georgia Institute of Technology, USA John Papapolymerou, Georgia Institute of Technology, USA Manos Tentzeris, Georgia Institute of Technology, USA Rong Lin Li, Georgia Institute of Technology, USA Kyutae Lim, Georgia Institute of Technology, USA Stephane Pinel, Georgia Institute of Technology, USA Daniel A. Friedman, IBM Thomas J. Watson Research Center, USA Mounir Meghelli, IBM Thomas J. Watson Research Center, USA Didier Belot, ST Microelectronics, France Ramana M. Malladi, IBM Microelectronics, USA I would also like to thank my graduate students and post-docs, past and present, for their dedication and tireless work in this fascinating field. I rest on their shoulders. They include: David Richey, Alvin Joseph, Bill Ansley, Juan Rolda´n, Stacey Salmon, Lakshmi Vempati, Jeff Babcock, Suraj Mathew, Kartik Jayanaraynan, Greg Bradford, Usha Gogineni, Gaurab Banerjee, Shiming Zhang, Krish Shivaram, Dave Sheridan, Gang Zhang, Ying Li, Zhenrong Jin, Qingqing Liang, Ram Krithivasan, Yun Luo, Tianbing Chen, Enhai Zhao, Yuan Lu, Chendong Zhu, Jon Comeau, Jarle Johansen, Joel Andrews, Lance Kuo, Xiangtao Li, Bhaskar Banerjee, Curtis Grens, Akil Sutton, Adnan Ahmed, Becca Haugerud, Mustayeen Nayeem, Mustansir Pratapgarhwala, Guofu Niu, Emery Chen, Jongsoo Lee, and Gnana Prakash. Finally, I am grateful to Tai Soda at Marcel Dekker (now Taylor & Francis) for talking me into this project, and supporting me along the way. I would also like to thank the production team at Taylor & Francis for their able assistance (and patience!), especially Jessica Vakili, Kavitha Kuttikan, Joanne Blake, Jim McGovern, Irina Eirush, Jacqueline Callahan, and David Grubbs. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. In the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life on planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay attention. It has been immensely satisfying to see both the dream of Si/SiGe bandgap engineering, and this handbook, come to fruition. I hope our efforts please you. Enjoy!

John D. Cressler Editor

© 2006 by Taylor & Francis Group, LLC

Foreword

Progress in a given field of technology is both desired and expected to follow a stable and predictable long-term trajectory. Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound. Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades. One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long-term prospects for the continuance of device density scaling itself. New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely. Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future. This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path. The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry. Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor-operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies. However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors. Bipolar junction transistor (BJT) technology, dominant in high-end computing applications during the mid-1980s, was being aggressively scaled to provide the requisite performance for future systems. By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions. This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day. Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20–30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant. Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage. This was due to the onset of band-to-band tunneling between heavily doped emitter and base regions, rendering such devices unreliable. This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence. Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing. A revolution in bipolar fabrication methodology, moving xi © 2006 by Taylor & Francis Group, LLC

xii

Foreword

from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon-based bipolar transistor performance to levels never anticipated. It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz. A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition. The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate ecosystem to enable its effective creation and utilization. This text is meant to describe the eco-system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented. Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development. Rapid device progress that followed drove silicon-based technology (recall that SiGe technology is still a silicon-based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques. As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control. Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe-based HEMTs, tunneling devices, mobilityenhanced CMOS, optical detectors, and more to come. Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling. Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level. Access to high-performance SiGe technology has spurred a rich diversity of exploratory and commercial circuit applications, many elaborated in this text. Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high-performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS. These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions. In its transition from scientific curiosity to pervasive technology, SiGe-based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed.

Bernard S. Meyerson IBM Systems and Technology Group

© 2006 by Taylor & Francis Group, LLC

The Editor

John D. Cressler received a B.S. in Physics from the Georgia Institute of Technology (Georgia Tech), Atlanta, Georgia, in 1984, and an M.S. in 1987 and Ph.D. in Applied Physics in 1990 from Columbia University, New York. From 1984 to 1992 he was on the research staff at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York, working on high-speed Si and SiGe bipolar devices and technology. In 1992 Dr. Cressler left IBM Research to join the faculty at Auburn University, Auburn, Alabama, where he served until 2002. At the time of his leaving Auburn University, he was Philpott–Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and Director of the Alabama Microelectronics Science and Technology Center. In 2002, Dr. Cressler joined the faculty at Georgia Tech, where he is currently Byers Professor of Electrical and Computer Engineering. His research interests include SiGe devices and technology; Si-based RF/ microwave/millimeter-wave devices and circuits; radiation effects; device-circuit interactions; noise and linearity; cryogenic electronics; SiC devices; reliability physics; extreme environment electronics, 2-D/3-D device-level simulation; and compact circuit modeling. He has published more than 300 technical papers related to his research, and is author of the books Silicon–Germanium Heterojunction Bipolar Transistors (with Guofu Niu, Artech House, 2003), and Reinventing Teenagers: The Gentle Art of Instilling Character in Our Young People (Xlibris, 2004) (a slightly different genre!). Dr. Cressler was Associate Editor of the IEEE Journal of Solid-State Circuits (1998–2001), and is currently Associate Editor of the IEEE Transactions on Nuclear Science (2003–2006). He served on the technical program committees of the IEEE International Solid-State Circuits Conference (1992–1998, 1999–2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995–1999), the IEEE International Electron Devices Meeting (1996–1997), and the IEEE Nuclear and Space Radiation Effects Conference (1999–2000, 2002–2004). He currently serves on the executive steering committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as international program advisor for the IEEE European Workshop on Low-Temperature Electronics, on the technical program committee for the IEEE International SiGe Technology and Device Meeting, and as subcommittee chair of the 2004 Electrochemical Society Symposium of SiGe: Materials, Processing, and Devices. He was the Technical Program Chair of the 1998 IEEE International Solid-State Circuits Conference, and the Conference Co-Chair of the 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Dr. Cressler was appointed an IEEE Electron Device Society Distinguished Lecturer in 1994 and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program. He received the 1996 C. Holmes MacDonald National Outstanding Teacher Award by Eta Kappa Nu, xiii © 2006 by Taylor & Francis Group, LLC

xiv

Foreword

the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, and an IEEE Third Millennium Medal in 2000. He is an IEEE Fellow. On a more personal note, John’s hobbies include hiking, gardening, bonsai, all things Italian, collecting (and drinking!) fine wines, cooking, history, and carving walking sticks, not necessarily in that order. He considers teaching to be his vocation. John has been married to Maria, his best friend and soul mate, for 22+ years, and is the proud father of three budding scholars: Matt (21), Christina (19), and Jo-Jo (16).

© 2006 by Taylor & Francis Group, LLC

Table of Contents

1 1.1 1.2

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

Introduction The Big Picture ........................................................................................................................ 1.1-3 J.D. Cressler A Brief History of the Field .................................................................................................. 1.2-15 J.D. Cressler

SiGe and Si Strained-Layer Epitaxy Overview: SiGe and Si Strained-Layer Epitaxy ................................................................... 2.1-31 J.D. Cressler Strained SiGe and Si Epitaxy ................................................................................................ 2.2-33 B. Tillack and P. Zaumseil Si/SiGe(C) Eptiaxy by RTCVD.............................................................................................. 2.3-45 D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot MBE Growth Techniques ...................................................................................................... 2.4-85 M. Oehme and E. Kasper UHV/CVD Growth Techniques ............................................................................................ 2.5-95 T.N. Adam Defects and Diffusion in SiGe and Strained Si ................................................................. 2.6-107 A.R. Peaker and V. Markevich Stability Constraints in SiGe Epitaxy................................................................................. 2.7-127 A. Fischer Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys.......................................... 2.8-143 J.L. Hoyt Carbon Doping of SiGe....................................................................................................... 2.9-157 H.J. Osten Contact Metallization on Silicon–Germanium................................................................ 2.10-171 C.K. Maiti Selective Etching Techniques for SiGe/Si......................................................................... 2.11-187 S. Monfray, S. Borel, and T. Skotnicki

xv © 2006 by Taylor & Francis Group, LLC

xvi

3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

3.11 3.12

4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Table of Contents

Fabrication of SiGe HBT BiCMOS Technology Overview: Fabrication of SiGe HBT BiCMOS Technology .............................................. 3.1-213 J.D. Cressler Device Structures and BiCMOS Integration ..................................................................... 3.2-215 D.L. Harame SiGe HBTs on CMOS-Compatible SOI .............................................................................. 3.3-233 J. Cai and T.H. Ning Passive Components ............................................................................................................ 3.4-249 J.N. Burghartz Industry Examples at State-of-the-Art: IBM ..................................................................... 3.5-265 A.J. Joseph and J.S. Dunn Industry Examples at State-of-the-Art: Jazz...................................................................... 3.6-283 P.H.G. Kempf Industry Examples at State-of-the-Art: Hitachi ................................................................ 3.7-295 K. Washio Industry Examples at State-of-the-Art: Infineon .............................................................. 3.8-307 T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck Industry Examples at State-of-the-Art: IHP...................................................................... 3.9-321 D. Knoll Industry Examples at State-of-the-Art: ST ...................................................................... 3.10-343 A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy Industry Examples at State-of-the-Art: Texas Instruments ........................................... 3.11-357 B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda Industry Examples at State-of-the-Art: Philips............................................................... 3.12-371 R. Colclaser and P. Deixler

SiGe HBTs Overview: SiGe HBTs .......................................................................................................... 4.1-389 J.D. Cressler Device Physics...................................................................................................................... 4.2-391 J.D. Cressler Second-Order Effects........................................................................................................... 4.3-411 J.D. Cressler Low-Frequency Noise .......................................................................................................... 4.4-427 G. Niu Broadband Noise ................................................................................................................. 4.5-439 D.R. Greenberg Microscopic Noise Simulation ............................................................................................ 4.6-459 G. Niu Linearity ............................................................................................................................... 4.7-475 G. Niu pnp SiGe HBTs..................................................................................................................... 4.8-489 J.D. Cressler

© 2006 by Taylor & Francis Group, LLC

Table of Contents

4.9 4.10 4.11 4.12 4.13 4.14

5

xvii

Temperature Effects............................................................................................................. 4.9-497 J.D. Cressler Radiation Effects................................................................................................................ 4.10-511 J.D. Cressler Reliability Issues ................................................................................................................ 4.11-525 J.D. Cressler Self-Heating and Thermal Effects .................................................................................... 4.12-539 J.-S. Rieh Device-Level Simulation.................................................................................................... 4.13-553 G. Niu SiGe HBT Performance Limits ......................................................................................... 4.14-571 G. Freeman, A. Stricker, J.-S. Rieh, and D.R. Greenberg

Heterostructure FETs

5.1

Overview: Heterostructure FETs ........................................................................................ 5.1-585 J.D. Cressler 5.2 Biaxial Strained Si CMOS ................................................................................................... 5.2-587 K. Rim 5.3 Uniaxial Stressed Si MOSFET............................................................................................. 5.3-601 S.E. Thompson 5.4 SiGe-Channel HFETs ........................................................................................................... 5.4-615 S. Banerjee 5.5 Industry Examples at State-of-the-Art: Intel’s 90 nm Logic Technologies ..................... 5.5-629 S.E. Thompson

6

Other Heterostructure Devices

6.1

Overview: Other Heterostructure Devices ........................................................................ 6.1-645 J.D. Cressler 6.2 Resonant Tunneling Devices............................................................................................... 6.2-647 S. Tsujino, D. Gru¨tzmacher, and U. Gennser 6.3 IMPATT Diodes ................................................................................................................... 6.3-661 E. Kasper and M. Oehme 6.4 Engineered Substrates for Electronic and Optoelectronic Systems................................. 6.4-679 E.A. Fitzgerald 6.5 Self-Assembling Nanostructures in Ge(Si)–Si Heteroepitaxy .......................................... 6.5-699 R. Hull

7 7.1 7.2

Optoelectronic Components Overview: Optoelectronic Components............................................................................. 7.1-717 J.D. Cressler Si–SiGe LEDs........................................................................................................................ 7.2-719 K.L. Wang, S. Tong, and H.J. Kim

© 2006 by Taylor & Francis Group, LLC

xviii

Table of Contents

7.3

Near-Infrared Detectors ...................................................................................................... 7.3-731 L. Colace, G. Masini, and G. Assanto 7.4 Si-based Photonic Transistors for Integrated Optoelectronics ........................................ 7.4-751 W.X. Ni and A. Elfving 7.5 Si–SiGe Quantum Cascade Emitters .................................................................................. 7.5-763 D.J. Paul

8 8.1 8.2 8.3 8.4 8.5 8.6 8.7

8.8 8.9

9 9.1 9.2 9.3 9.4 9.5 9.6 9.7

Measurement and Modeling Overview: Measurement and Modeling ............................................................................. 8.1-779 J.D. Cressler Best-Practice AC Measurement Techniques ...................................................................... 8.2-781 R.A. Groves Industrial Application of TCAD for SiGe Development .................................................. 8.3-793 D.C. Sheridan, J.B. Johnson, and R. Krishnasamy Compact Modeling of SiGe HBTs: HICUM....................................................................... 8.4-807 M. Schro¨ter Compact Modeling of SiGe HBTs: MEXTRAM................................................................. 8.5-825 S. Mijalkovic CAD Tools and Design Kits ................................................................................................ 8.6-847 S.E. Strang Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs ......................................................................................... 8.7-859 R. Singh Transmission Lines on Si .................................................................................................... 8.8-871 Y.V. Tretiakov Improved De-Embedding Techniques................................................................................ 8.9-883 Q. Liang

Circuits and Applications Overview: Circuits and Applications ................................................................................. 9.1-899 J.D. Cressler SiGe as an Enabler for Wireless Communications Systems............................................. 9.2-901 L.E. Larson and D.Y.C. Lie LNA Optimization Strategies.............................................................................................. 9.3-923 Q. Liang Linearization Techniques .................................................................................................... 9.4-937 L.C.N. de Vreede and M.P. van der Heijden SiGe MMICs ......................................................................................................................... 9.5-979 H. Schumacher SiGe Millimeter-Wave ICs................................................................................................... 9.6-997 J.-F. Luy Wireless Building Blocks Using SiGe HBTs .................................................................... 9.7-1007 J.R. Long

© 2006 by Taylor & Francis Group, LLC

Table of Contents

xix

9.8

Direct Conversion Architectures for SiGe Radios .......................................................... 9.8-1049 S. Chakraborty and J. Laskar 9.9 RF MEMS Techniques in Si/SiGe ..................................................................................... 9.9-1075 J. Papapolymerou 9.10 Wideband Antennas on Silicon ...................................................................................... 9.10-1099 M.M. Tentzeris and R.L. Li 9.11 Packaging Issues for SiGe Circuits................................................................................. 9.11-1119 K. Lim, S. Pinel, and J. Laskar 9.12 Industry Examples at State-of-the-Art: IBM ................................................................. 9.12-1127 D.J. Friedman and M. Meghelli 9.13 Industry Examples at State-of-the-Art: Hitachi ............................................................ 9.13-1145 K. Washio 9.14 Industry Examples at State-of-the-Art: ST .................................................................... 9.14-1155 D. Belot

Appendices A.1 Properties of Silicon and Germanium ............................................................................ A.1-1177 J.D. Cressler A.2 The Generalized Moll-Ross Relations ............................................................................. A.2-1181 J.D. Cressler A.3 Integral Charge-Control Relations .................................................................................. A.3-1187 M. Schro¨ter A.4 Sample SiGe HBT Compact Model Parameters ............................................................. A.4-1201 R.M. Malladi

© 2006 by Taylor & Francis Group, LLC

1 Introduction 1.1

The Big Picture J.D. Cressler......................................................................................... 1.1-3 The Communications Revolution . Bandgap Engineering in the Silicon Material System . Terminology and Definitions . The Application Space . Performance Limits and Future Directions

1.2

A Brief History of the Field J.D. Cressler.................................................................. 1.2-15 Si–SiGe Strained Layer Epitaxy . SiGe HBTs . SiGe–Strained Si FETs and Other SiGe Devices

1.1-1 © 2006 by Taylor & Francis Group, LLC

1.1 The Big Picture 1.1.1 1.1.2

John D. Cressler Georgia Institute of Technology

1.1.3 1.1.4 1.1.5

The Communications Revolution................................ 1.1-3 Bandgap Engineering in the Silicon Material System ............................................................. 1.1-5 Terminology and Definitions ....................................... 1.1-6 The Application Space .................................................. 1.1-7 Performance Limits and Future Directions .............. 1.1-11

1.1.1 The Communications Revolution We are at a unique juncture in the history of humankind, a juncture that amazingly we engineers and scientists have dreamed up and essentially created on our own. This pivotal event can be aptly termed the ‘‘Communications Revolution,’’ and the twenty-first century, our century, will be the era of human history in which this revolution plays itself out. This communications revolution can be functionally defined and characterized by the pervasive acquisition, manipulation, storage, transformation, and transmission of ‘‘information’’ on a global scale. This information, or more generally, knowledge, in its infinitely varied forms and levels of complexity, is gathered from our analog sensory world, transformed in very clever ways into logical ‘‘1’’s and ‘‘0’’s for ease of manipulation, storage, and transmission, and subsequently regenerated into analog sensory output for our use and appreciation. In 2005, this planetary communication of information is occurring at a truly mind-numbing rate, estimates of which are on the order of 80 Tera-bits/sec (1012) of data transfer across the globe in 2005 solely in wired and wireless voice and data transmission, 24 hours a day, 7 days a week, and growing exponentially. The world is quite literally abuzz with information flow — communication.* It is for the birth of the Communications Revolution that we humans likely will be remembered for 1000 years hence. Given that this revolution is happening during the working careers of most of us, I find it a wonderful time to be alive, a fact of which I remind my students often. Here is my point. No matter how one slices it, at the most fundamental level, it is semiconductor devices that are powering this communications revolution. Skeptical? Imagine for a moment that one could flip a switch and instantly remove all of the integrated circuits (ICs) from planet Earth. A moment’s reflection will convince you that there is not a single field of human endeavor that would not come to a grinding halt, be it commerce, or agriculture, or education, or medicine, or entertainment. Life as we in the first world know it in 2005 would simply cease to exist. And yet, remarkably, the same result would not have been true 50 years ago; even 20 years ago. Given the fact that we humans have been on planet Earth in our present form for at least 1 million years, and within communities

*I have often joked with my students that it would be truly entertaining if the human retina was sensitive to longer wavelengths of electromagnetic radiation, such that we could ‘‘see’’ all the wireless communications signals constantly bathing the planet (say, in greens and blues!). It might change our feelings regarding our ubiquitous cell phones!

1.1-3 © 2006 by Taylor & Francis Group, LLC

1.1-4

The Silicon Heterostructure Handbook

having entrenched cultural traditions for at least 15,000 years, this is truly a remarkable fact of history. A unique juncture indeed. Okay, hold on tight. It is an easy case to make that the semiconductor silicon (Si) has single-handedly enabled this communications revolution.** I have previously extolled at length the remarkable virtues of this rather unglamorous looking silver-grey element [1], and I will not repeat that discussion here, but suffice it to say that Si represents an extremely unique material system that has, almost on its own, enabled the conception and evolving execution of this communications revolution. The most compelling attribute, by far, of Si lies in the economy-of-scale it facilitates, culminating in the modern IC fabrication facility, effectively enabling the production of gazillions of low-cost, very highly integrated, remarkably powerful ICs, each containing millions of transistors; ICs that can then be affordably placed into widgets of remarkably varied form and function.y So what does this have to do with the book you hold in your hands? To feed the emerging infrastructure required to support this communications revolution, IC designers must work tirelessly to support increasingly higher data rates, at increasingly higher carrier frequencies, all in the design space of decreasing form factor, exponentially increasing functionality, and at ever-decreasing cost. And by the way, the world is going portable and wireless, using the same old wimpy batteries. Clearly, satisfying the near-insatiable appetite of the requisite communications infrastructure is no small task. Think of it as job security! For long-term success, this quest for more powerful ICs must be conducted within the confines of conventional Si IC fabrication, so that the massive economy-of-scale of the global Si IC industry can be brought to bear. Therein lies the fundamental motivation for the field of Si heterostructures, and thus this book. Can one use clever nanoscale engineering techniques to custom-tailor the energy bandgap of fairly conventional Si-based transistors to: (a) improve their performance dramatically and thereby ease the circuit and system design constraints facing IC designers, while (b) performing this feat without throwing away all the compelling economy-of-scale virtues of Si manufacturing? The answer to this important question is a resounding ‘‘YES!’’ That said, getting there took time, vision, as well as dedication and hard work of literally thousands of scientists and engineers across the globe. In the electronics domain, the fruit of that global effort is silicon–germanium heterojunction bipolar transistor (SiGe HBT) bipolar complementary metal oxide semiconductor (BiCMOS) technology, and is in commercial manufacturing worldwide and is rapidly finding a number of important circuit and system applications. In 2004, the SiGe ICs, by themselves, are expected to generate US$1 billion in revenue globally, with perhaps US$30 billion in downstream products. This US$1 billion figure is projected to rise to US$2.09 billion by 2006 [2], representing a growth rate of roughly 42% per year, a remarkable figure by any economic standard. The biggest single market driver remains the cellular industry, but applications in optical networking, hard disk drives for storage, and automotive collisionavoidance radar systems are expected to represent future high growth areas for SiGe. And yet, in the beginning of 1987, only 18 years ago, there was no such thing as a SiGe HBT. It had not been demonstrated as a viable concept. An amazing fact. In parallel with the highly successful development of SiGe HBT technology, a wide class of ‘‘transport enhanced’’ field effect transistor topologies (e.g., strained Si CMOS) have been developed as a means to boost the performance of the CMOS side of Si IC coin, and such technologies have also recently begun **The lone exception to this bold claim lies in the generation and detection of coherent light, which requires direct bandgap III–V semiconductor devices (e.g., GaAs of InP), and without which long-haul fiber communications systems would not be viable, at least for the moment. y Consider: it has been estimated that in 2005 there are roughly 20,000,000,000,000,000,000 (2
1019) transistors on planet Earth. While this sounds like a large number, let us compare it to some other large numbers: (1) the universe is roughly 4.2
1017sec old (13.7 billion years), (2) there are about 1
1021 stars in the universe, and (3) the universe is about 4
1023 miles across (15 billion light-years)! Given the fact that all 2
1020 of these transistors have been produced since December 23, 1947 (following the invention of the point-contact transistor by Bardeen, Brattain, and Shockley), this is a truly remarkable feat of human ingenuity.

© 2006 by Taylor & Francis Group, LLC

The Big Picture

1.1-5

to enter the marketplace as enhancements to conventional core CMOS technologies. The commercial success enjoyed in the electronics arena has very naturally also spawned successful forays into the optoelectronics and even nanoelectronics fields, with potential for a host of important downstream applications. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of our twenty-first century. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. As I have argued, in the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life of planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay close attention.

1.1.2 Bandgap Engineering in the Silicon Material System As wonderful as Si is from a fabrication viewpoint, from a device or circuit designer’s perspective, it is hardly the ideal semiconductor. The carrier mobility for both electrons and holes in Si is comparatively small compared to their III–V cousins, and the maximum velocity that these carriers can attain under high electric fields is limited to about 1
107 cm/sec under normal conditions, relatively ‘‘slow.’’ Since the speed of a transistor ultimately depends on how fast the carriers can be transported through the device under sustainable operating voltages, Si can thus be regarded as a somewhat ‘‘meager’’ semiconductor. In addition, because Si is an indirect gap semiconductor, light emission is fairly inefficient, making active optical devices such as diode lasers impractical (at least for the present). Many of the III–V compound semiconductors (e.g., GaAs or InP), on the other hand, enjoy far higher mobilities and saturation velocities, and because of their direct gap nature, generally make efficient optical generation and detection devices. In addition, III–V devices, by virtue of the way they are grown, can be compositionally altered for a specific need or application (e.g., to tune the light output of a diode laser to a specific wavelength). This atomic-level custom tailoring of a semiconductor is called bandgap engineering, and yields a large performance advantage for III–V technologies over Si [3]. Unfortunately, these benefits commonly associated with III–V semiconductors pale in comparison to the practical deficiencies associated with making highly integrated, low-cost ICs from these materials. There is no robust thermally grown oxide for GaAs or InP, for instance, and wafers are smaller with much higher defect densities, are more prone to breakage, and are poorer heat conductors (the list could go on). These deficiencies translate into generally lower levels of integration, more difficult fabrication, lower yield, and ultimately higher cost. In truth, of course, III–V materials such as GaAs and InP fill important niche markets today (e.g., GaAs metal semiconductor field effect transistor (MESFETs) and HBTs for cell phone power amplifiers, AlGaAs- or InP-based lasers, efficient long wavelength photodetectors, etc.), and will for the foreseeable future, but III–V semiconductor technologies will never become mainstream in the infrastructure of the communications revolution if Si-based technologies can do the job. While Si ICs are well suited to high-transistor-count, high-volume microprocessors and memory applications, RF, microwave, and even millimeter-wave (mm-wave) electronic circuit applications, which by definition operate at significantly higher frequencies, generally place much more restrictive performance demands on the transistor building blocks. In this regime, the poorer intrinsic speed of Si devices becomes problematic. That is, even if Si ICs are cheap, they must deliver the required device and circuit performance to produce a competitive system at a given frequency. If not, the higher-priced but faster III–V technologies will dominate (as they indeed have until very recently in the RF and microwave markets). The fundamental question then becomes simple and eminently practical: is it possible to improve the performance of Si transistors enough to be competitive with III–V devices for high-performance applications, while preserving the enormous yield, cost, and manufacturing advantages associated with conventional Si fabrication? The answer is clearly ‘‘yes,’’ and this book addresses the many nuances

© 2006 by Taylor & Francis Group, LLC

1.1-6

The Silicon Heterostructure Handbook

associated with using SiGe and Si-strained layer epitaxy to practice bandgap engineering in the Si material system, a process culminating in, among other things, the SiGe HBT and strained Si CMOS, as well as a variety of other interesting electronic and optoelectronic devices built from these materials. This totality can be termed the ‘‘Si heterostructures’’ field.

1.1.3 Terminology and Definitions A few notes on modern usage and pronunciation in this field are in order (really!). It is technically correct to refer to silicon–germanium alloys according to their chemical composition, Si1xGex , where x is the Ge mole fraction. Following standard usage, such alloys are generally referred to as ‘‘SiGe’’ alloys. Note, however, that it is common in the material science community to also refer to such materials as ‘‘Ge:Si’’ alloys. A SiGe film that is carbon doped (e.g., less than 0.20% C) in an attempt to suppress subsequent boron out-diffusion (e.g., in HBTs) is properly referred to as a SiGe:C alloy, or simply SiGeC (pronounced ‘‘silicon germanium carbon,’’ not ‘‘silicon germanium carbide’’). This class of SiGe alloys should be viewed as optimized SiGe alloys, and are distinct from SiGe films with a much higher C content (e.g., 2% to 3% C) that might be used, for instance, to lattice-match SiGeC alloys to Si. Believe it or not, this field also has its own set of slang pronunciations. The colloquial usage of the pronunciation \’sig-ee\ to refer to ‘‘silicon–germanium’’ (begun at IBM in the late 1990s) has come into vogue (heck, it may make it to the dictionary soon!), and has even entered the mainstream IC engineers’s slang; pervasively.z In the electronics domain, it is important to be able to distinguish between the various SiGe technologies as they evolve, both for CMOS (strained Si) and bipolar (SiGe HBT). Relevant questions in this context include: Is company X’s SiGe technology more advanced than company Y’s SiGe technology? For physical as well as historical reasons, one almost universally defines CMOS technology (Si, strained Si, or SiGe), a lateral transport device, by the drawn lithographic gate length (the CMOS technology ‘‘node’’), regardless of the resultant intrinsic device performance. Thus, a ‘‘90-nm’’ CMOS node has a drawn gate length of roughly 90 nm. For bipolar devices (i.e., the SiGe HBT), however, this is not so straightforward, since it is a vertical transport device whose speed is not nearly as closely linked to lithographic dimensions. In the case of the SiGe HBT it is useful to distinguish between different technology generations according to their resultant ac performance (e.g., peak common-emitter, unity gain cutoff frequency (fT), which is (a) easily measured and unambiguously compared technology to technology, and yet is (b) a very strong function of the transistor vertical doping and Ge profile and hence nicely reflects the degree of sophistication in device structural design, overall thermal cycle, epi growth, etc.) [1]. The peak fT generally nicely reflects the ‘‘aggressiveness,’’ if you will, of the transistor scaling which has been applied to a given SiGe technology. A higher level of comparative sophistication can be attained by also invoking the maximum oscillation frequency ( fmax), a parameter which is well correlated to both intrinsic profile and device parasitics, and hence a bit higher on the ladder of device performance metrics, and thus more representative of actual large-scale circuit performance. The difficulty in this case is that fmax is far more ambiguous than fT , in the sense that it can be inferred from various gain definitions (e.g., U vs. MAG), and in practice power gain data are often far less ideal in its behavior over frequency, more sensitive to accurate deembedding, and ripe with extraction ‘‘issues.’’ We thus term a SiGe technology having a SiGe HBT with a peak fT in the range of 50 GHz as ‘‘first generation;’’ that with a peak fT in the range of 100 GHz as ‘‘second generation;’’ that with a peak fT in the range of 200 GHz as ‘‘third generation;’’ and that with a peak fT in the range of 300 GHz as ‘‘fourth generation.’’ These are loose definitions to be sure, but nonetheless useful for comparison purposes.

z

I remain a stalwart holdout against this snowballing trend and stubbornly cling to the longer but far more satisfying ‘‘silicon–germanium.’’

© 2006 by Taylor & Francis Group, LLC

1.1-7

The Big Picture

SiGe HBT BiCMOS technology evolution by generation

CMOS gate length

90 nm

4th

3rd

0.12 µm

0.18 µm

2nd

0.25 µm

1st 50 GHz

100 GHz

200 GHz

300 GHz

SiGe HBT peak cutoff frequency FIGURE 1.1.1 Evolution of SiGe HBT BiCMOS technology generations, as measured by the peak cutoff frequency of the SiGe HBT, and the CMOS gate length.

A complicating factor in SiGe technology terminology results from the fact that most, if not all, commercial SiGe HBT technologies today also contain standard Si CMOS devices (i.e., SiGe HBT BiCMOS technology) to realize high levels of integration and functionality on a single die (e.g., singlechip radios complete with RF front-end, data converters, and DSP). One can then speak of a given generation of SiGe HBT BiCMOS technology as the most appropriate intersection of both the SiGe HBT peak fT and the CMOS technology node (Figure 1.1.1). For example, for several commercially important SiGe HBT technologies available via foundry services, we have: . . . . . .

IBM SiGe 5HP — 50 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) IBM SiGe 7HP — 120 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IBM SiGe 8HP — 200 GHz peak fT SiGe HBT þ 0.13 mm Si CMOS (third generation) Jazz SiGe 60 — 60 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) Jazz SiGe 120 — 150 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IHP SiGe SGC25B — 120 GHz peak fT SiGe HBT þ 0.25 mm Si CMOS (second generation)

All SiGe HBT BiCMOS technologies can thus be roughly classified in this manner. It should also be understood that multiple transistor design points typically exist in such BiCMOS technologies (multiple breakdown voltages for the SiGe HBT and multiple threshold or breakdown voltages for the CMOS), and hence the reference to a given technology generation implicitly refers to the most aggressively scaled device within that specific technology platform.

1.1.4 The Application Space It goes without saying in our field of semiconductor IC technology that no matter how clever or cool a new idea appears at first glance, its long-term impact will ultimately be judged by its marketplace ‘‘legs’’ (sad, but true). That is, was the idea good for a few journal papers and an award or two, or did someone actually build something and sell some useful derivative products from it? The sad reality is that the semiconductor field (and we are by no means exceptional) is rife with examples of cool new devices that

© 2006 by Taylor & Francis Group, LLC

1.1-8

The Silicon Heterostructure Handbook

never made it past the pages of the IEDM digest! The ultimate test, then, is one of stamina. And sweat. Did the idea make it out of the research laboratory and into the hands of the manufacturing lines? Did it pass the qualification-checkered flag, have design kits built around it, and get delivered to real circuit designers who built ICs, fabricated them, and tested them? Ultimately, were the derivative ICs inserted into real systems — widgets — to garner leverage in this or that system metric, and hence make the products more appealing in the marketplace? Given the extremely wide scope of the semiconductor infrastructure fueling the communications revolution, and the sheer volume of widget possibilities, electronic to photonic to optoelectronic, it is useful here to briefly explore the intended application space of Si heterostructure technologies as we peer out into the future. Clearly I possess no crystal ball, but nevertheless some interesting and likely lasting themes are beginning to emerge from the fog. SiGe HBT BiCMOS is the obvious ground-breaker of the Si heterostructures application space in terms of moving the ideas of our field into viable products for the marketplace. The field is young, but the signs are very encouraging. As can be seen in Figure 1.1.2, there are at present count 25 þ SiGe HBT industrial fabrication facilities on line in 2005 around the world, and growing steadily. This trend points to an obvious recognition that SiGe technology will play an important role in the emerging electronics infrastructure of the twenty-first century. Indeed, as I often point out, the fact that virtually every major player in the communications electronics field either: (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers, is a remarkable fact, and very encouraging in the grand scheme of things. As indicated above, projections put SiGe ICs at a US$2.0 billion level by 2006, small by percentage perhaps compared to the near trillion dollar global electronics market, but growing rapidly. The intended application target? That obviously depends on the company, but the simple answer is, gulp, a little bit of everything! As depicted in Figure 1.1.3 and Figure 1.1.4, the global communications landscape is exceptionally diverse, ranging from low-frequency wireless (2.4 GHz cellular) to the fastest high-speed wireline systems (10 and 40 Gbit/sec synchronous optical network (SONET)). Core CMOS technologies are increasingly being pushed into the lower frequency wireless space, but the compelling drive to higher carrier frequencies over time will increasingly favor SiGe technologies. At present, SiGe ICs are making inroads into: the cellular industry for handsets [global system for mobile communications — GSM, code division multiple access (CDMA), wideband CDMA (W-CDMA), etc.], even for power amplifiers; various wireless local area networks (WLAN) building blocks, from components to fully integrated systems ranging from 2.4 to 60 GHz and up; ultrawide band (UWB) components; global positioning systems (GPS); wireless base stations; a variety of wireline networking products, from 2.5 to 40 Gbit/sec (and higher); data converters (D/A and A/D); highspeed memories; a variety of instrumentation electronics; read-channel memory storage products; core analog functions (op amps, etc.); high-speed digital circuits of various flavors; radiation detector

Industrial fabrication facilities

25 20

SiGe HBT BiCMOS Strained–Si CMOS

15 10 5 0 1993

1995

1997

1999 Year

2001

2003

FIGURE 1.1.2 Number of industrial SiGe and strained Si fabrication facilities.

© 2006 by Taylor & Francis Group, LLC

2005

1.1-9

The Big Picture

FIGURE 1.1.3 The global communications landscape, broken down by the various communications standards, and spanning the range of: wireless to wireline; fixed to mobile; copper to fiber; low data rate to broadband; and local area to wide area networks. WAN is wide area network, MAN is metropolitan area network, the so-called ‘‘last mile’’ access network, LAN is local area network, and PAN is personal area network, the emerging in-home network. (Used with the permission of Kyutae Lim.) Some application bands for SiGe ICs Defense Radar

Radar Navigation

GPS

Radar Automotive Collision avoidance

Polling

Cellular / PCS / Satellite / UWB

Communications WLAN

Bands: L 1

2

S

C

3

5

W

Ka

X

Ku

10

20 30

ISM

50

100

Frequency (GHz)

FIGURE 1.1.4 Some application frequency bands for SiGe integrated circuits.

electronics; radar systems (from 3 to 77 GHz and up); a variety space-based electronics components; and various niche extreme environment components (e.g., cryogenic (77 K) hybrid superconductor–semiconductor systems). The list is long and exceptionally varied — this is encouraging. Clearly, however, some of these components of ‘‘everything’’ are more important than others, and this will take time to shake out. The strength of the BiCMOS twist to SiGe ICs cannot be overemphasized. Having both the high-speed SiGe HBT together on-chip with aggressively scaled CMOS allows one great flexibility in system design, the depths of which is just beginning to be plumbed. While debates still rage with respect to the most cost-effective partitioning at the chip and package level (system-on-a-chip versus system-in-a-package,

© 2006 by Taylor & Francis Group, LLC

1.1-10

The Silicon Heterostructure Handbook

etc.), clearly increased integration is viewed as a good thing in most camps (it is just a question of how much), and SiGe HBT BiCMOS is well positioned to address such needs across a broad market sector. The envisioned high-growth areas for SiGe ICs over the new few years include: the cellular industry, optical networking, disk drives, and radar systems. In addition, potential high-payoff market areas span the emerging mm-wave space (e.g., the 60 GHz ISM band WLAN) for short range, but very high data rate (Gbit/sec) wireless systems. A SiGe 60 GHz single-chip/package transceiver (see Figure 1.1.5 for IBM’s vision of such a beast) could prove to be the ‘‘killer app’’ for the emerging broadband multimedia market. Laughable? No. The building blocks for such systems have already been demonstrated using third-generation SiGe technology [4], and fully integrated transceivers are under development. The rest of the potential market opportunities within the Si heterostructures field can be leveraged by successes in the SiGe IC field, both directly and indirectly. On the strained Si CMOS front, there are existent proofs now that strained Si is likely to become a mainstream component of conventional CMOS scaling at the 90-nm node and beyond (witness the early success of Intel’s 90-nm logic technology built around uniaxially strained Si CMOS; other companies are close behind). Strained Si would seem to represent yet another clever technology twist that CMOS device technologists are pulling from their bag of tricks to keep the industry on a Moore’s law growth path. This was not an obvious development (to me anyway) even a couple of years back. A wide variety of ‘‘transport enhanced’’ Si-heterostructure-based FETs have been demonstrated (SiGe-channel FETs, Si-based high electron mobility transistors (HEMTs), as well as both uniaxially and biaxially strained FETs, etc). Most of these devices, however, require complex substrate engineering that would have seemed to preclude giga-scale integration level needs for microprocessor-level integration. Apparently not so. The notion of using Si heterostructures (either

Radiation

Vision of a 60 GHz SiGe wireless transceiver Package mold

Wirebond pad

Wirebond C4-Balls

Tx/Rx flip-Antenna

Mix

Filter structure

Q-signal

90 VCO I-signal

Underfill

Su

bs

tra

te

Mix Mix Q-signal LNA

I/Q

90 VCO I-signal

PLL

Mix

I/Q

QFN-package Package pin

FIGURE 1.1.5 Vision for a single-chip SiGe mm-wave transceiver system. (Used with the permission of Ullrich Pfeiffer.)

© 2006 by Taylor & Francis Group, LLC

1.1-11

The Big Picture

uniaxial or biaxial strain or both) to boost conventional CMOS performance appears to be an appealing path for the future, a natural merging point I suspect for SiGe strained layers found in SiGe HBT BiCMOS (which to date contains only conventional Si CMOS) and strained Si CMOS. From the optoelectronics camp, things are clearly far less evolved, but no less interesting. A number of functional optoelectronic devices have been demonstrated in research laboratories. Near-term successes in the short wavelength detector arena and light emitting diodes (LEDs) are beginning to be realized. The achievement of successful coherent light emission in the Si heterostructure system (e.g., via quantum cascade techniques perhaps) would appear to be the ‘‘killer app’’ in this arena, and research in this area is in progress. More work is needed.

1.1.5 Performance Limits and Future Directions We begin with device performance limits. Just how fast will SiGe HBTs be 5 years from now? Transistorlevel performance in SiGe HBTs continues to rise at a truly dizzying pace, and each major conference seems to bear witness to a new performance record (Figure 1.1.6). Both first- and second-generation SiGe HBT BiCMOS technology is widely available in 2005 (who would have thought even 3 years ago that fully integrated 100þ GHz Si-based devices would be ‘‘routine’’ on 200 mm wafers?), and even at the 200 GHz (third-generation) performance level, six companies (at last count) have achieved initial technology demonstrations, including IBM (Chapter 3.5), Jazz (Chapter 3.6), IHP (Chapter 3.9), ST Microelectronics (Chapter 3.10), Hitachi (Chapter 3.7), and Infineon (Chapter 3.8). Several are now either available in manufacturing, or are very close (e.g., [5]). At press time, the most impressive new stake-in-the-ground is the report (June 2004) of the newly optimized ‘‘SiGe 9T’’ technology, which simultaneously achieves 302 GHz peak fT and 306 GHz peak fmax, a clear record for any Si-based transistor, from IBM (Figure 1.1.7) [6]. This level of ac performance was achieved at a BVCEO of 1.6 V, a BVCBO of 5.5 V, and a current gain of 660. Noise measurements on these devices yielded NFmin/Gassoc of 0.45 dB/14 dB and 1.4 dB/8 dB at 10 and 25 GHz, respectively. Measurements of earlier (unoptimized) fourth-generation IBM SiGe HBTs have yielded record values of 375 GHz peak fT [7] at 300 K and above 500 GHz peak fT at 85 K. Simulations suggest that THz-level (1000 GHz) intrinsic transistor performance is not a laughable proposition in SiGe HBTs (Chapter 4.14). This fact still amazes even me, the eternal optimist of SiGe performance! I, for one, firmly believe that we will see SiGe HBTs

400 4th

Cutoff frequency (GHz)

350 300 250 3rd 200 150

2nd

100 50 0 0.1

1st

1.0 10 Collector current density (mA/mm2)

100

FIGURE 1.1.6 Measured cutoff frequency as a function of bias current density for four different SiGe HBT technology generations.

© 2006 by Taylor & Francis Group, LLC

1.1-12

The Silicon Heterostructure Handbook

400 f T + f max = 400 GHz

Peak f max (GHz)

350

600 GHz f T = f max

300 250 200 GHz

200 150 100

SiGe+SiGe: C HBT 300 K

50 0

0

50

100

150

200

250

300

350

400

Peak f T (GHz)

FIGURE 1.1.7 Measured maximum oscillation frequency versus cutoff frequency for a variety of generations of SiGe HBT BiCMOS technology shown in Figure 1.1.1.

above-500 GHz peak fT and fmax fully integrated with nanometer-scale (90 nm and below) Si CMOS (possibly strained Si CMOS) within the next 3 to 5 years. One might logically ask, particularly within the confines of the above discussion on ultimate market relevance, why one would even attempt to build 500 GHz SiGe HBTs, other than to win a best-paper award, or to trumpet that ‘‘because-it’s-there’’ Mount Everest mentality we engineers and scientists love so dearly. This said, if the future ‘‘killer app’’ turns out to be single-chip mm-wave transceiver systems with on-board DSP for broadband multimedia, radar, etc., then the ability of highly scaled, highly integrated, very high performance SiGe HBTs to dramatically enlarge the circuit/system design space of the requisite mm-wave building blocks may well prove to be a fruitful (and marketable) path. Other interesting themes are emerging in the SiGe HBT BiCMOS technology space. One is the very recent emergence of complementary SiGe (C-SiGe) HBT processes (npn þ pnp SiGe HBTs). While very early pnp SiGe HBT prototypes were demonstrated in the early 1990s, only in the last 2 years or so have fully complementary SiGe processes been developed, the most mature of which to date is the IHP SGC25C process, which has 200 GHz npn SiGe HBTs and 80 GHz pnp SiGe HBTs (Chapter 3.9). Having very high-speed pnp SiGe HBTs on-board presents a fascinating array of design opportunities aimed particularly at the analog/mixed-signal circuit space. In fact, an additional emerging trend in the SiGe field, particularly for companies with historical pure analog circuit roots, is to target lower peak fT , but higher breakdown voltages, while simultaneously optimizing the device for core analog applications (e.g., op amps, line drivers, data converters, etc.), designs which might, for instance, target better noise performance, and higher current gain-Early voltage product than mainstream SiGe technologies. One might even choose to park that SiGe HBT platform on top of thick film SOI for better isolation properties (Chapter 3.11). Another interesting option is the migration of high-speed vertical SiGe HBTs with very thin film CMOS-compatible SOI (Chapter 3.3). This technology path would clearly favor the eventual integration of SiGe HBTs with strained Si CMOS, all on SOI, a seemingly natural migratory path. If one accepts the tenet that integration is a good thing from a system-level perspective, the Holy Grail in the Si heterostructure field would, in the end, appear to be the integration of SiGe HBTs for RF through mm-wave circuitry (e.g., single-chip mm-wave transceivers complete with on-chip antennae), strained Si CMOS for all DSP and memory functionality, both perhaps on SOI, Si-based light emitters, SiGe HBT modulator electronics, and detectors for such light sources, together with on-chip waveguides to steer the light, realized all on one Si wafer to produce a ‘‘Si-based optoelectronic superchip’’ [8], that could do-it-all. These diverse blocks would be optional plug-in modules around a core SiGe

© 2006 by Taylor & Francis Group, LLC

The Big Picture

1.1-13

HBT þ strained Si CMOS IC technology platform, perhaps with flip-chip (or other) packaging techniques to join different sub-die to the main superchip (e.g., for a Si-based detector or laser). I know, I know. It is not obvious that even if each of these blocks could be realized, that it would make economic sense to do so for real systems. I have no quarrel with that. I think such a Si-based superchip is a useful paradigm, however, to bind together all of the clever objects we wish to ultimately build with Si heterostructures, from electronic to photonic, and maintain the vision of the one overarching constraint that guides us as we look forward — keep whatever you do compatible with high-volume manufacturing in Si fabrication facilities if you want to shape the path of the ensuing communications revolution. This Si-based superchip clearly remains a dream at present. A realizable dream? And if realizable, commercially viable? Who knows? Only time will tell. But it is fun to think about. As you peruse this book you hold in your hands, which spans the whole Si heterostructure research and development space, from materials, to devices, to circuit and system applications, I think you will be amazed at both the vision, cleverness, and smashing successes of the many scientists and engineers who make up our field. Do not count us out! We are the new architects of an oh-so-very-interesting future.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. ‘‘SiGe devices market to hit $2 billion in 2006,’’ article featured on CompoundSemicoductor.net, http://compoundsemiconductor.net/articles/news/8/3/22/1 3. F Capasso. Band-gap engineering: from physics and materials to new semiconductor devices. Science 235:172–176, 1987. 4. S Reynolds, B Floyd, U Pfeiffer, and T. Zwick. 60 GHz transciever circuits in SiGe bipolar technology. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp 442–443. 5. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp 180–182. 6. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeter-wave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp 395–398. 7. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cutoff frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp 771–774. 8. R Soref. Silicon-based photonic devices. Technical Digest of the IEEE International Solid-State Circuits Conference, 1995, pp 66–67.

© 2006 by Taylor & Francis Group, LLC

1.2 A Brief History of the Field John D. Cressler Georgia Institute of Technology

1.2.1 1.2.2 1.2.3

Si–SiGe Strained Layer Epitaxy.................................. 1.2-15 SiGe HBTs .................................................................... 1.2-17 SiGe–Strained Si FETs and Other SiGe Devices ....... 1.2-20

In the historical record of any field of human endeavor, being ‘‘first’’ is everything. It is often said that ‘‘hindsight is 20–20,’’ and it is tempting in many cases to ascribe this or that pivotal event as ‘‘obvious’’ or ‘‘easy’’ once the answer is known. Anyone intimately involved in a creative enterprise knows, however, that it is never easy being first, and often requires more than a little luck and maneuvering. Thus the triumphs of human creativity, the ‘‘firsts,’’ should be appropriately celebrated. Still, later chroniclers often gloss over, and then eventually ignore, important (and sometimes very interesting) twists and turns, starts and stops, of the winners as well as the second and third place finishers, who in the end may in fact have influenced the paths of the winners, sometimes dramatically. The history of our field, for instance, is replete with interesting competitive battles, unusual personalities and egos, no small amount of luck, and various other fascinating historical nuances. There is no concise history of our field available, and while the present chapter is not intended to be either exhaustive or definitive, it represents my firm conviction that the history of any field is both instructive and important for those who follow in the footsteps of the pioneers. Hopefully this brief history does not contain too many oversights or errors, and is offered as a step in the right direction for a history of pivotal events that helped shape the Si heterostructures field.

1.2.1 Si–SiGe Strained Layer Epitaxy The field of Si-based heterostructures solidly rests on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor ‘‘black arts’’ associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. What may seem routine today was not always so. The Si heterostructure story necessarily begins with materials, and circuit designers would do well to remember that much of what they take for granted in transistor performance owes a great debt to the smelters of the crystalline world. Table 1.2.1 summarizes the key steps in the development of SiGe–Si strained layer epitaxy. Given that Ge was the earliest and predominant semiconductor pursued by the Bell Laboratories transistor team, with a focus on the more difficult to purify Si to come slightly later, it is perhaps not surprising that the first study of SiGe alloys, albeit unstrained bulk alloys, occurred as early as 1958 [1]. It was recognized around 1960 [2] that semiconductor epitaxy* would enable more robust and controllable transistor fabrication. Once the move to Si-based processing occurred, the field of Si epitaxy was

*The word ‘‘epitaxy’’ (or just ‘‘epi’’) is derived from the Greek word epi, meaning ‘‘upon’’ or ‘‘over.’’

1.2-15 © 2006 by Taylor & Francis Group, LLC

1.2-16

The Silicon Heterostructure Handbook TABLE 1.2.1

Milestones in the Development of SiGe–Si Strained Layer Epitaxy

Historical Event

Year

Ref.

First investigation of the bandgap of unstrained SiGe alloys First epitaxially grown layer to be used in a transistor First investigation of high-temperature Si epitaxy Concept of critical thickness for epitaxial strained layers Energy minimization approach for critical thickness Force-balance approach for critical thickness First growth of SiGe strained layers First growth of SiGe epitaxy by MBE First stability calculations of SiGe strained layers First measurements of energy bandgap in SiGe strained layers First growth of Si epitaxy by LRP-CVD First 2D electron gas in the SiGe system First growth of Si epitaxy by UHV/CVD First measurements of band alignments in SiGe–Si First growth of SiGe epitaxy by UHV/CVD First step-graded relaxed SiGe substrate First growth of SiGe epitaxy by LRP-CVD First growth of Si epitaxy by AP-CVD First 2D hole gas in the SiGe system First growth of SiGe epitaxy by AP-CVD First majority hole mobility measurements in SiGe First minority electron mobility measurements in SiGe First growth of lattice-matched SiGeC alloys First growth of SiGe layers with carbon doping First stability calculations to include a Si cap layer

1958 1960 1963 1963 1963 1974 1975 1984 1985 1985 1985 1985 1986 1986 1988 1988 1989 1989 1989 1991 1991 1992 1992 1994 2000

[1] [2] [3] [4] [5] [6] [7] [8] [9] [10,11] [12] [13] [14] [15] [16] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]

launched, the first serious investigation of which was reported in 1963 [3]. Early Si epitaxy was exclusively conducted under high-temperature processing conditions, in the range of 11008C, a temperature required to obtain a chemically pure and pristine growth interface on the Si host substrate for the soon-to-be-grown crystalline Si epi. High-temperature Si epi has been routinely used in basically this same form for over 40 years now, and represents a mature fabrication technique that is still widely practiced for many types of Si devices (e.g., high-speed bipolar transistors and various power devices). Device engineers have long recognized the benefits of marrying the many virtues of Si as a host material for manufacturing electronic devices, with the bandgap engineering principles routinely practiced in the III–V system. Ultimately this requires a means by which one can perform epitaxial deposition of thin Si layers on large Si substrates, for both p- and n-type doping of arbitrary abruptness, with very high precision, across large wafers, and doping control at high dynamic range. Only a moment’s reflection is required to appreciate that this means the deposition of the Si epi must occur at very low growth temperatures, say 5008C to 6008C (not ‘‘low’’ per se, but low compared to the requisite temperatures needed for solid-state diffusion of dopants in Si). Such a low-temperature Si epi would then facilitate the effective marriage of Si and Ge, two chemically compatible elements with differing bandgaps, and enable the doping of such layers with high precision, just what is needed for device realizations. Clearly the key to Si-based bandgap engineering, Si-heterostructures, our field, is the realization of device quality, low-temperature Si epi (and hence SiGe epi), grown pseudomorphically** on large Si host substrates. Conquering this task proved to be remarkably elusive and time consuming. In the III–V semiconductor world, where very low processing temperatures are much easier to attain, and hence more common than for Si, the deposition of multiple semiconductors on top of one another proved quite feasible (e.g., GaAs on InP), as needed to practice bandgap engineering, for instance, **The word ‘‘pseudo’’ is derived from the Greek word pseude¯s, meaning ‘‘false,’’ and the word ‘‘morphic’’ is derived from the Greek word morphe¯, meaning ‘‘form.’’ Hence, pseudomorphic literally means false-form.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-17

resulting in complex material composites having differing lattice constants in intimate physical contact. To accommodate the differing lattice constants while maintaining the crystallinity of the underlying films, strain is necessarily induced in the composite film, and the notion of a film ‘‘critical thickness,’’ beyond which strain relaxation occurs via fundamental thermodynamic driving forces, was defined as early as 1963 [4], as were the energy minimization techniques needed for calculating such critical thicknesses [5]. Alternative ‘‘force-balance’’ techniques for addressing the so-called stability issues in strained layer epitaxy came from the III–V world in 1974, and were applied to SiGe strained layer epitaxy in 1985 [9]. Interestingly, however, research continues today on stability in complicated (e.g., compositionally graded) SiGe films, and only very recently have reasonably complete theories been offered which seem to match well with experiment [25]. The first reported growth of SiGe strained layers was in 1975 in Germany [7], but the field did not begin to seriously heat up until the early 1980s, when several teams pioneered the application of molecular beam epitaxy (MBE) to facilitate materials studies of device-quality strained SiGe on Si in 1984 [8]. Optical studies on these films resulted in encouraging findings concerning the beneficial effects of strain on the band-edge properties of SiGe [10, 11], paving the way for serious contemplation of devices built from such materials. Parallel paths toward other low-temperature Si epi growth techniques centered on the ubiquitous chemical vapor deposition (CVD) approach were simultaneously pursued, culminating in the so-called limited-reaction-processing CVD (LRP-CVD) technique (Si epi in 1985 [12], and SiGe epi in 1989 [17]), the ultrahigh-vacuum CVD (UHV/CVD) technique (Si epi in 1986 [14] and SiGe epi in 1988 [16]), and various atmospheric pressure CVD (AP-CVD) techniques (e.g., Si epi in 1989 [18], and SiGe epi in 1991 [20]). These latter two techniques, in particular, survive to this day, and are widely used in the SiGe heterojunction bipolar transistor (HBT) industry. Device-quality SiGe–Si films enabled a host of important discoveries to occur, which have important bearing on device derivatives, including the demonstration of both two-dimensional electron and hole gases [13, 19], and the fortuitous observation that step-graded SiGe buffer layers could be used to produce device-quality strained Si on SiGe, with its consequent conduction band offsets [16]. This latter discovery proved important in the development of SiGe–Si heterostructure-based FETs. Both majority and minority carrier mobility measurements occurred in the early 1990s [21, 22], although reliable data, particularly involving minority carriers, remain sparse in the literature. Also in the early 1990s, experiments using high C content as a means to relieve strain in SiGe and potentially broaden the bandgap engineering space by lattice-matching SiGe:C materials to Si substrates (a path that has to date not borne much fruit, unfortunately), while others began studying efficacy of C-doping of SiGe, a result that ultimately culminated in the wide use today of C-doping for dopant diffusion suppression in SiGe:C HBTs [23, 24]. The Si–SiGe materials field continues to evolve. Commercial single wafer (AP-CVD) and batch wafer (UHV/CVD) Si–SiGe epi growth tools compatible with 200 mm (and soon 300 mm) Si wafers exist in literally dozens of industrial fabrication facilities around the world, and SiGe growth can almost be considered routine today in the ease in which it can be integrated into CMOS-compatible fabrication processes. It was clearly of paramount importance in the ultimate success of our field that some of the ‘‘black magic’’ associated with robust SiGe film growth be removed, and this, thankfully, is the case in 2005.

1.2.2 SiGe HBTs Transistor action was first demonstrated by Bardeen and Brattain in late December of 1947 using a point contact device [26]. Given all that has transpired since, culminating in the Communications Revolution, which defines our modern world (refer to the discussion in Chapter 1.1), this pivotal event surely ranks as one of the most significant in the course of human history — bold words, but nevertheless true. This demonstration of a solid-state device exhibiting the key property of amplification (power gain) is also unique in the historical record for the precision with which we can locate it in time — December 23,

© 2006 by Taylor & Francis Group, LLC

1.2-18

The Silicon Heterostructure Handbook

1947, at about 5 p.m. Not to be outdone, Shockley rapidly developed a theoretical basis for explaining how this clever object worked, and went on to demonstrate the first true bipolar junction transistor (BJT) in 1951 [27]. The first BJT was made, ironically in the present context, from Ge. The first silicon BJT was made by Teal in 1954 using grown junction techniques. The first diffused silicon BJT was demonstrated in 1956 [28], and the first epitaxially grown silicon BJT was reported in 1960, see Ref. [2]. The concept of the HBT is surprisingly an old one, dating in fact to the fundamental BJT patents filed by Shockley in 1948 [29]. Given that the first bipolar transistor was built from Ge, and III–V semiconductors were not yet on the scene, it seems clear that Shockley envisioned the combination of Si (wide bandgap emitter) and Ge (narrow bandgap base) to form a SiGe HBT. The basic formulation and operational theory of the HBT, for both the traditional wide bandgap emitter plus narrow bandgap base approach found in most III–V HBTs, as well as the drift-base (graded) approach used in SiGe HBTs today, was pioneered by Kroemer, and was largely in place by 1957 [30–32]. It is ironic that Kroemer in fact worked hard early on to realize a SiGe HBT, without success, ultimately pushing him toward the III–V material systems for his heterostructure studies, a path that proved in the end to be quite fruitful for him, since he shared the Nobel Prize in physics in 2000 for his work in (III–V) bandgap engineering for electronic and photonic applications [33]. While III–V HBT (e.g., AlGaAs–GaAs) demonstrations began appearing in the 1970s, driven largely by the needs for active microwave components in the defense industry, reducing the SiGe HBT to practical reality took 30 years after the basic theory was in place due to material growth limitations. As pointed out [34] the semiconductor device field is quite unique in the scope of human history because ‘‘science’’ (theoretical understanding) preceded the ‘‘art’’ (engineering and subsequent technological advancement). Once device-quality SiGe films were finally achieved in the mid-1980s, however, progress was quite rapid. Table 1.2.2 summarizes the key steps in the evolution of SiGe HBTs. The first functional SiGe HBT was demonstrated by an IBM team in December 1987 at the IEDM [35]. The pioneering result showed a SiGe HBT with functional, albeit leaky, dc characteristics; but it was a SiGe HBT, it worked (barely), and it was the first.y It is an often overlooked historical point, however, that at least four independent groups were simultaneously racing to demonstrate the first functional SiGe HBT, all using the MBE growth technique: the IBM team [35], a Japanese team [62], a Bell Laboratories team [63], and a Linko¨ping University team [64]. The IBM team is fairly credited with the victory, since it presented (and published) its results in early December of 1987 at the IEDM (it would have been submitted to the conference for review in the summer 1987) [35]. Even for the published journal articles, the IBM team was the first to submit its paper for review (on November 17, 1987) [65]. All four papers appeared in print in the spring of 1988. Other groups soon followed with more SiGe HBT demonstrations. The first SiGe HBT demonstrated using (the ultimately more manufacturable) CVD growth technique followed shortly thereafter, in 1989, first using LRP-CVD [17], and then with UHV/CVD [36]. Worldwide attention became squarely focused on SiGe technology, however, in June 1990 at the IEEE VLSI Technology Symposium with the demonstration of a non-self-aligned UHV/CVD SiGe HBT with a peak cutoff frequency of 75 GHz [37, 38]. At that time, this SiGe HBT result was roughly twice the performance of state-of-the-art Si BJTs, and clearly demonstrated the future performance potential of the technology (doubling of transistor performance is a rare enough event that it does not escape significant attention!). Eyebrows were raised, and work to develop SiGe HBTs for practical circuit applications began in earnest in a large number of industrial and university laboratories around the world.} The feasibility of implementing pnp SiGe HBTs was also demonstrated in June 1990 [40]. In December 1990, the simplest digital circuit, an emitter-coupled-logic (ECL) ring oscillator, using selfy

An interesting historical perspective of early SiGe HBT development at IBM is contained in Ref. [61]. A variety of zero-Dt, mesa-isolated, III–V-like high-speed SiGe HBTs were reported in the early 1990s (e.g., Ref. [66]), but we focus here on fully integrated, CMOS-compatible SiGe HBT technologies, because they are inherently more manufacturable, and hence they are the only ones left standing today, for obvious reasons. }

© 2006 by Taylor & Francis Group, LLC

1.2-19

A Brief History of the Field TABLE 1.2.2 Milestones in the Development of SiGe HBTs Historical Event

Year

Ref.

First demonstration of transistor action Basic HBT concept First demonstration of a bipolar junction transistor First demonstration of a silicon bipolar transistor Drift-base HBT concept Fundamental HBT theory First epitaxial silicon transistors First SiGe HBT First ideal SiGe HBT grown by CVD First SiGe HBT grown by UHV/CVD First high-performance SiGe HBT First self-aligned SiGe HBT First SiGe HBT ECL ring oscillator First pnp SiGe HBT First operation of SiGe HBTs at cryogenic temperatures First SiGe HBT BiCMOS technology First LSI SiGe HBT integrated circuit First SiGe HBT with peak fT above 100 GHz First SiGe HBT technology in 200-mm manufacturing First SiGe HBT technology optimized for 77 K First radiation tolerance investigation of SiGe HBTs First report of low-frequency noise in SiGe HBTs First SiGe:C HBT First high-power SiGe HBTs First sub-10 psec SiGe HBT ECL circuits First high-performance SiGe:C HBT technology First SiGe HBT with peak fT above 200 GHz First SiGe HBT with peak fT above 300 GHz First complementary (npn þ pnp) SiGe HBT technology First C-SiGe technology with npn and pnp fT above 100 GHz First vertical SiGe HBT on thin film (CMOS compatible) SOI First SiGe HBT with both fT and fmax above 300 GHz

1947 1948 1951 1956 1954 1957 1960 1987 1989 1989 1990 1990 1990 1990 1990 1992 1993 1993 1994 1994 1995 1995 1996 1996 1997 1999 2001 2002 2003 2003 2003 2004

[26] [29] [27] [28] [30] [31, 32] [2] [35] [17] [36] [37, 38] [39] [39] [40] [41] [42] [43] [44, 45] [46] [47] [48] [49] [50] [51, 52] [53] [54] [55] [56] [57] [58] [59] [60]

aligned, fully integrated SiGe HBTs was produced [39]. The first SiGe BiCMOS technology (SiGe HBT þ Si CMOS) was reported in December 1992 [42]. Theoretical predictions of the inherent ability of SiGe HBTs to operate successfully at cryogenic temperatures (in contrast to Si BJTs) were first confirmed in 1990 [41], and SiGe HBT profiles optimized for the liquid nitrogen temperature environment (77 K) were reported in 1994 [48]. The first LSI SiGe HBT circuit (a 1.2 Gsample/sec 12-bit digital-to-analog converter — DAC) was demonstrated in December 1993 [43]. The first SiGe HBTs with frequency response greater than 100 GHz were described in December 1993 by two independent teams [44, 45], and the first SiGe HBT technology entered commercial production on 200-mm wafers in December 1994 [46]. The first report of the effects of ionizing radiation on advanced SiGe HBTs was made in 1995 [48]. Due to the natural tolerance of epitaxial-base bipolar structures to conventional radiation-induced damage mechanisms without any additional radiation-hardening process changes, SiGe HBTs are potentially very important for space-based and planetary communication systems applications, spawning an important new sub-discipline for SiGe technology. The first demonstration that epitaxial SiGe strained layers do not degrade the superior low-frequency noise performance of bipolar transistors occurred in 1995, opening the way for very low-phase noise frequency sources [49]. Carbon-doping of epitaxial SiGe layers as a means to effectively suppress boron out-diffusion during fabrication has rapidly become the preferred approach for commercial SiGe technologies, particularly those above first-generation performance levels. Carbon-doping of SiGe HBTs has its own interesting

© 2006 by Taylor & Francis Group, LLC

1.2-20

The Silicon Heterostructure Handbook

history, dating back to the serendipitous discovery [50] in 1996 that incorporating small amounts of C into a SiGe epi layer strongly retards (by an order of magnitude) the diffusion of the boron (B) base layer during subsequent thermal cycles. Given that maintaining a thin base profile during fabrication is perhaps the most challenging aspect of building a manufacturable SiGe technology, it is somewhat surprising that it took so long for the general adoption of C-doping as a key technology element. I think it is fair to say that most SiGe practitioners at that time viewed C-doping with more than a small amount of skepticism, given that C can act as a deep trap in Si, and C contamination is generally avoided at all costs in Si epi processes, particularly for minority carrier devices such as the HBT. At the time of the discovery of C-doping of SiGe in 1996, most companies were focused on simply bringing up a SiGe process and qualifying it, relegating the potential use of C to the back burner. In fairness, most felt that C-doping was not necessary to achieve first-generation SiGe HBT performance levels. The lone visionary group to solidly embrace C-doping of SiGe HBTs at the onset was the IHP team in Germany, whose pioneering work eventually paid off and began to convince the skeptics of the merits of C-doping. The minimum required C concentration for effective out-diffusion suppression of B was empirically established to be in the vicinity of 0.1% to 0.2% C (i.e., around 1
1020 cm3). Early on, much debate ensued on the physical mechanism of how C impedes the B diffusion process, but general agreement for the most part now exists and is discussed in Chapter 2.9. The first high-performance, fully integrated SiGe:C HBT technology was reported in 1999 [54]. The first ‘‘high-power’’ SiGe HBTs (S band, with multiwatt output power) were reported in 1996 using thick collector doping profiles [51, 52]. The 10-psec ECL circuit performance barrier was broken in 1997 [53]. The 200-GHz peak fT performance barrier was broken in November 2001 for a nonself-aligned device [55], and for a self-aligned device in February 2002 [67]. By 2004, a total of six industrial laboratories had achieved 200 GHz performance levels. A SiGe HBT technology with a peak fT of 350 GHz (375 GHz values were reported in the IEDM presentation) was presented in December 2002 [56], and this 375 GHz fT value remains a record for room temperature operation (it is above 500 GHz at cryogenic temperatures), and an optimized version with both fT and fmax above 300 GHz was achieved in June 2004 [60]. This combined level of 300þ GHz for both fT and fmax remains a solid record for any Si-based semiconductor device. Other recent and interesting developments in the SiGe HBT field include the first report of a complementary (npn þ pnp) SiGe HBT (C-SiGe) technology in 2003 [57], rapidly followed by a C–SiGe technology with fT for both the npn and pnp SiGe HBTs above 100 GHz [58]. In addition, a novel vertical npn SiGe HBT has been implemented in thin-film (120 nm) CMOS-compatible SOI [59]. Besides further transistor performance enhancements, other logical developments to anticipate in this field include the integration of SiGe HBTs with strained-Si CMOS for a true all-Si-heterostructure technology. Not surprisingly, research and development activity involving SiGe HBTs, circuits built from these devices, and various SiGe HBT technologies, in both industry and at universities worldwide, has grown very rapidly since the first demonstration of a functional SiGe HBT in 1987, only 18 years in the past.

1.2.3 SiGe–Strained Si FETs and Other SiGe Devices The basic idea of using an electric field to modify the surface properties of materials, and hence construct a ‘‘field-effect’’ device, is remarkably old (1926 and 1935), predating even the quest for a solid-state amplifier [68]. Given the sweeping dominance of CMOS technology in the grand scheme of the electronics industry today, it is ironic that the practical demonstration of the BJT preceded that of the MOSFET by 9 years. This time lag from idea to realization was largely a matter of dealing with the many perils associated with obtaining decent dielectric materials in the Si system — doubly ironic given that Si has such a huge natural advantage over all other semiconductors in this regard. Bread-and-butter notions of ionic contamination, de-ionized water, fixed oxide charge, surface state passivation, and clean-room techniques in semiconductor fabrication had to be learned the hard way. Once devicequality SiO2 was obtained in the late 1950s, and a robust gate dielectric could thus be fabricated, it was

© 2006 by Taylor & Francis Group, LLC

1.2-21

A Brief History of the Field

not long until the first functional MOSFET was demonstrated in 1960 [69]. The seemingly trivial (remember, however, that hindsight is 20–20!) connection of n-channel and p-channel MOSFETs to form low-power CMOS in 1963 [70] paved the way (eventually) to the high-volume, low-cost, highly integrated microprocessor, and the enormous variety of computational engines that exist today as a result. Like their cousin, the SiGe HBT, SiGe–strained Si FETs did not get off the ground until the means for accomplishing the low-temperature growth of Si epitaxy could be realized. Once that occurred in the mid-1980s the field literally exploded. Table 1.2.3 summarizes the milestones in the evolution of SiGe– strained Si FETs, as well as a veritable menagerie of other electronic and optoelectronic components built from SiGe–strained Si epitaxy. It was discovered as early as 1971 that direct oxidation of SiGe was a bad idea for building gate dielectrics [71]. Given that gate oxide quality, low-temperature deposited oxides, did not exist in the mid-1980s, the earliest FET demonstrations were modulation-doped, Schottky-gated, FETs, and both n-channel and p-channel SiGe MODFETs were pioneered as early as 1986 using MBE-grown material [72, 73]. Before the SiGe MOSFET field got into high gear in the 1990s, a variety of other novel device demonstrations occurred, including: the first SiGe superlattice photodetector [74], the first SiGe Schottky barrier diodes (SBD) in 1988 [75], the first SiGe hole-transport resonant tunneling diode (RTD) in 1988 [76], and the first SiGe bipolar inversion channel FET (BiCFET) in 1989, a now-extinct dinosaur [77]. Meanwhile, early studies using SiGe in conventional CMOS gate stacks to minimize dopant depletion effects and tailor work functions, a fairly common practice in CMOS today, occurred in 1990 [78], and the first SiGe waveguides on Si substrates were produced in 1990 [79]. The first functional SiGe channel pMOSFET was published in 1991, and shortly thereafter, a wide variety of other approaches aimed at obtaining the best SiGe pMOSFETs (see, for instance, Refs. [93–95]). The first electron-transport RTD was demonstrated in 1991 [81], and the first LED in SiGe

TABLE 1.2.3 Milestones in the Development of SiGe–Strained Si FETs and Other Devices Historical Event

Year

Ref.

Field effect device concept First Si MOSFET First Si CMOS First oxidation study of SiGe First SiGe nMODFET First SiGe pMODFET First SiGe photodetector First SiGe SBD First SiGe hole RTD First SiGe BiCFET First SiGe gate CMOS technology First SiGe waveguide First SiGe pMOSFET First SiGe electron RTD First SiGe LED First SiGe solar cell First a-SiGe phototransistor First SiGe pMOSFET on SOI First strained Si pMOSFET First strained Si nMOSFET First SiGe:C pMOSFET First SiGe pFET on SOS First submicron strained Si MOSFET First vertical SiGe pFET First strained Si CMOS technology

1926 1960 1963 1971 1986 1986 1986 1988 1988 1989 1990 1990 1991 1991 1991 1992 1993 1993 1993 1994 1996 1997 1998 1998 2002

[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92]

© 2006 by Taylor & Francis Group, LLC

1.2-22

The Silicon Heterostructure Handbook

also in 1991 (a busy year for our field). In 1992, the first a-SiGe solar cell was discussed [83], and in 1993, the first high-gain a-SiGe phototransistor [84]. The first SiGe pMOSFETs using alternate substrate materials were demonstrated, first in SOI in 1993 [85], and then on sapphire in 1997 [88], the first SiGe:C channel pMOSFET was demonstrated in 1996 [89], and the first vertical SiGe FET was published in 1998 [92]. Because of the desire to use Si-based bandgap engineering to improve not only the p-channel MOSFET, but also the n-channel MOSFET, research in the early- to mid-1990s in the FET field began to focus on strained Si MOSFETs on relaxed SiGe layers, with its consequent improvement in both electron and hole transport properties. This work culminated in the first strained Si pMOSFET in 1993 [87], and the first stained Si nMOSFET in 1994 [88], and remains an intensely active research field today. Key to the eventual success of strained Si CMOS approaches was that significant mobility enhancement could be achieved in both nFETs and pFETs down to very short (sub-micron) gate lengths, and this was first demonstrated in 1998 [90]. Strained Si CMOS at the 90-nm node and below is rapidly becoming mainstream for most serious CMOS companies, and the first commercial 90 nm strained Si CMOS technology platform was demonstrated by Intel in 2002 [91]. At last count, there were upwards of a halfdozen companies (e.g., Texas Instruments and IBM) also rapidly pushing toward 90 nm (and below) strained Si CMOS technologies, utilizing a variety of straining techniques, and thus it would appear that strained Si CMOS will be a mainstream IC technology in the near future, joining SiGe HBT BiCMOS technology. This is clearly outstanding news for our field. The merger of SiGe HBTs with strained Si CMOS would be a near-term logical extension.

References 1. R Braunstein, AR Moore, and F Herman. Intrinsic optical absorption in germanium–silicon alloys. Physical Review B 32:1405–1408, 1958. 2. HC Theuerer, JJ Kleimack, HH Loar, and H Christensen. Epitaxial diffused transistors. Proceedings of the IRE 48:1642–1643, 1960. 3. BA Joyce and RR Bradley. Epitaxial growth of silicon from the pyrolysis of monosilane on silicon substrates. Journal of the Electrochemical Society 110:1235–1240, 1963. 4. JH van der Merwe. Crystal interfaces. Part I. Semi-infinite crystals. Journal of Applied Physics 34:117–125, 1963. 5. JH van der Merwe. Crystal interfaces. Part II. Finite overgrowths. Journal of Applied Physics 34:123–127, 1963. 6. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations in layers. Journal of Crystal Growth 27:118–125, 1974. 7. E Kasper, HJ Herzog, and H Kibbel. A one-dimensional SiGe superlattice grown by UHV epitaxy. Journal of Applied Physics 8:1541–1548, 1975. 8. JC Bean, TT Sheng, LC Feldman, AT Fiory, and RT Lynch. Pseudomorphic growth of GexSi1x on silicon by molecular beam epitaxy. Applied Physics Letters 44:102–104, 1984. 9. R People and JC Bean. Calculation of critical layer thickness versus lattice mismatch for GexSi1x/Si strained layer heterostructures. Applied Physics Letters 47:322–324, 1985. 10. R People. Indirect bandgap of coherently strained Si1xGex bulk alloys on h0 0 1i silicon substrates. Physical Review B 32:1405–1408, 1985. 11. DV Lang, R People, JC Bean, and AM Sergent. Measurement of the bandgap of GexSi1x/Si strainedlayer heterostructures. Applied Physics Letters 47:1333–1335, 1985. 12. JF Gibbons, CM Gronet, and KE Williams. Limited reaction processing: silicon epitaxy. Applied Physics Letters 47:721–723, 1985. 13. G Abstreiter, H Brugger, T Wolf, H Joke, and HJ Kerzog. Strain-induced two-dimensional electron gas in selectively doped Si/SixGe1x superlattices. Physical Review 54:2441–2444, 1985. 14. BS Meyerson. Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition. Applied Physics Letters 48:797–799, 1986.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-23

15. R People and JC Bean. Band alignments of coherently strained GexSi1x/Si heterostructures on h0 0 1i GeySi1y substrates. Applied Physics Letters 48:538–540, 1986. 16. BS Meyerson, KJ Uram, and FK LeGoues. Cooperative phenomena is silicon/germanium low temperature epitaxy. Applied Physics Letters 53:2555–2557, 1988. 17. CA King, JL Hoyt, CM Gronet, JF Gibbons, MP Scott, and J Turner. Si/Si1x/Gex heterojunction bipolar transistors produced by limited reaction processing. IEEE Electron Device Letters 10:52–54, 1989. 18. TO Sedgwick, M Berkenbilt, and TS Kuan. Low-temperature selective epitaxial growth of silicon at atmospheric pressure. Applied Physics Letters 54:2689–2691, 1989. 19. PJ Wang, FF Fang, BS Meyerson, J Mocera, and B Parker. Two-dimensional hole gas in Si/Si0.85Ge0.15 modulation doped heterostructures. Applied Physics Letters 54:2701–2703, 1989. 20. P Agnello, TO Sedgwick, MS Goorsky, J Ott, TS Kuan, and G Scilla. Selective growth of silicon– germanium alloys by atmospheric-pressure chemical vapor deposition at low temperatures. Applied Physics Letters 59:1479–1481, 1991. 21. T Manku and A Nathan. Lattice mobility of holes in strained and unstrained Si1xGex alloys. IEEE Electron Device Letters 12:704–706, 1991. 22. T Manku and A Nathan. Electron drift mobility model for devices based on unstrained and coherently strained Si1xGex grown on h0 0 1i silicon subtrate. IEEE Transactions on Electron Devices 39:2082–2089, 1992. 23. K Erbel, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Applied Physics Letters 60:3033–3035, 1992. 24. HJ Osten, E Bugiel, and P Zaumseil. Growth of inverse tetragonal distorted SiGe layer on Si(0 0 1) by adding small amounts of carbon. Applied Physics Letters 64:3440–3442, 1994. 25. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 26. J Bardeen and WH Brattain. The transistor, a semi-conductor triode. Physical Review 71:230–231, 1947. 27. W Shockley, M Sparks, and GK Teal. p–n junction transistors. Physical Review 83:151–162, 1951. 28. M Tanenbaum and DE Thomas. Diffused emitter and base silicon transistors. Bell System Technical Journal 35:23–34, 1956. 29. See, for instance, W Shockley. U.S. Patents 2,502,488, 2,524,035, and 2,569,347. 30. H Kroemer. Zur theorie des diffusions und des drifttransistors. Part III. Archiv der Elektrischen Ubertragungstechnik 8:499–504, 1954. 31. H Kroemer. Quasielectric and quasimagnetic fields in nonuniform semiconductors. RCA Review 18:332–342, 1957. 32. H Kroemer. Theory of a wide-gap emitter for transistors. Proceedings of the IRE 45:1535–1537, 1957. 33. B Brar, GJ Sullivan, and PM Asbeck. Herb’s bipolar transistors. IEEE Transactions on Electron Devices 48:2473–2476, 2001. 34. RM Warner. Microelectronics: Its unusual origin and personality. IEEE Transactions on Electron Devices 48:2457–2467, 2001. 35. SS Iyer, GL Patton, SL Delage, S Tiwari, and J.M.C. Stork. Silicon–germanium base heterojunction bipolar transistors by molecular beam epitaxy. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 874–876. 36. GL Patton, DL Harame, JMC Stork, BS Meyerson, GJ Scilla, and E Ganin. Graded-SiGe-base, polyemitter heterojunction bipolar transistors. IEEE Electron Device Letters 10:534–536, 1989. 37. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 63-75 GHz fT SiGe-base heterojunction-bipolar technology. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 49–50. 38. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, GJ Scilla, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 75 GHz fT SiGe base heterojunction bipolar transistors. IEEE Electron Device Letters 11:171–173, 1990.

© 2006 by Taylor & Francis Group, LLC

1.2-24

The Silicon Heterostructure Handbook

39. JH Comfort, GL Patton, JD Cressler, W Lee, EF Crabbe´, BS Meyerson, JY-C Sun, JMC Stork, P-F Lu, JN Burghartz, J Warnock, K Kenkins, K-Y Toh, M D’Agostino, and G Scilla. Profile leverage in a selfaligned epitaxial Si or SiGe-base bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 21–24. 40. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base PNP transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 41. EF Crabbee´, GL Patton, JMC Stork, BS Meyerson, and JY-C Sun. Low temperature operation of Si and SiGe bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20. 42. DL Harame, EF Crabbe´, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, J Malinowski, and AJ Dally. A high-performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1992, pp. 19–22. 43. DL Harame, JMC Stork, BS Meyerson, KY-J Hsu, J Cotte, KA Jenkins, JD Cressler, P Restle, EF Crabbe´, S Subbanna, TE Tice, BW Scharf, and JA Yasaitis. Optimization of SiGe HBT technology for high speed analog and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 71–74. 44. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Techncial Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 79–81. 45. EF Crabbe´, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 46. DL Harame, K Schonenberg, M Gilbert, D Nguyen-Ngoc, J Malinowski, S-J Jeng, BS Meyerson, JD Cressler, R Groves, G Berg, K Tallman, K Stein, G Hueckel, C Kermarrec, T Tice, G Fitzgibbons, K Walter, D Colavito, T Houghton, N Greco, T Kebede, B Cunningham, S Subbanna, JH Comfort, and EF Crabbe´. A 200 mm SiGe-HBT technology for wireless and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, Washington, 1994, pp. 437–440. 47. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter cap SiGebase bipolar technology for liquid nitrogen temperature operation. IEEE Electron Device Letters 15:472–474, 1994. 48. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Transactions on Nuclear Science 42:1558–1566, 1995. 49. LS Vempati, JD Cressler, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minnneapolis, 1995, pp. 129–132. 50. L Lanzerotti, A St Amour, CW Liu, JC Sturm, JK Watanabe, and ND Theodore. Si/Si1xyGexCy /Si heterojunction bipolar transistors. IEEE Electron Device Letters 17:334–337, 1996. 51. A Schu¨ppen, S Gerlach, H Dietrich, D Wandrei, U Seiler, and U Ko¨nig. 1-W SiGe power HBTs for mobile communications. IEEE Microwave and Guided Wave Letters 6:341–343, 1996. 52. PA Potyraj, KJ Petrosky, KD Hobart, FJ Kub, and PE Thompson. A 230-Watt S-band SiGe heterojunction junction bipolar transistor. IEEE Transactions on Microwave Theory and Techniques 44:2392–2397, 1996. 53. K Washio, E Ohue, K Oda, M Tanabe, H Shimamoto, and T Onai. A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-Gate Delay. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1997, pp. 795–798. 54. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-25

55. SJ Jeng, B Jagannathan, J-S Rieh, J Johnson, KT Schonenberg, D Greenberg, A Stricker, H Chen, M Khater, D Ahlgren, G Freeman, K Stein, and S Subbanna. A 210-GHz fT SiGe HBT with nonself-aligned structure. IEEE Electron Device Letters 22:542–544, 2001. 56. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz.Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 57. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M. Waitschull, JW Weijtmans, and C Willis. A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 211–214. 58. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 59. J Cai, M Kumar, M Steigerwalt, H Ko, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 215–218. 60. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeterwave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp. 395–398. 61. DL Harame and BS Meyerson. The early history of IBM’s SiGe mixed signal technology. IEEE Transactions on Electron Devices 48:2555–2567, 2001. 62. T Tatsumi, H Hirayama, and N Aizaki. Si/Ge0.3Si0.7 heterojunction bipolar transistor made with Si molecular beam epitaxy. Applied Physics Letters 52:895–897, 1988. 63. H Temkin, JC Bean, A Antreasyan, and R Leibenguth. GexSi1x strained-layer heterostructure bipolar transistors. Applied Physics Letters 52:1089–1091, 1988. 64. D-X Xu, G-D Shen, M Willander, W-X Ni, and GV Hansson. n-Si/p-Si1x /n-Si double-heterojunction bipolar transistors. Applied Physics Letters 52:2239–2241, 1988. 65. GL Patton, SS Iyer, SL Delage, S Tiwari, and JMC Stork. Silicon–germanium-base heterojunction bipolar transistors by molecular beam epitaxy. IEEE Electron Device Letters 9:165–167, 1988. 66. A Gruhle, H Kibbel, U Ko¨nig, U Erben, and E Kasper. MBE-Grown Si/SiGe HBTs with high b, fT, and fmax. IEEE Electron Device Letters 13:206–208, 1992. 67. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 68. H. Lilienfeld Patent, 1926; O. Heil, British patent number 439,457, 1935. 69. D Khang and MM Atalla. Silicon–silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, 1960. 70. FM Wanlass and CT Sah. Nanowatt logic using field-effect metal-oxide-semiconductor triodes (MOSTs). IEEE International Solid-State Circuits Conference, Philadelphia, 1963, pp. 32–33. 71. P Balk. Surface properties of oxidized germanium-doped silicon. Journal of the Electrochemical Society 118:494–495, 1971. 72. H Daembkes, H-J Herzog, H Jorke, H. Kibbel, and E Kasper. The n-channel SiGe/Si modulation doped field-effect transistor. IEEE Transactions on Electron Devices 33:633–638, 1986.

© 2006 by Taylor & Francis Group, LLC

1.2-26

The Silicon Heterostructure Handbook

73. TP Pearsall and JC Bean. Enhancement and depletion-mode p-channel GexSi1x modulation-doped field effect transistor. IEEE Electron Device Letters 7:308–310, 1986. 74. H Temkin, TP Pearsall, JC Bean, RA Logan, and S. Luryi. GexSi1x strained-layer superlattice waveguide photodetectors operating near 1.3 mm. Applied Physics Letters 48:963–965, 1986. 75. RD Thompson, KN Tu, J Angillelo, S Delage, and SS Iyer. Interfacial reaction between Ni and MBE grown SiGe alloys. Journal of the Electrochemical Society 135:3161–3163, 1988. 76. HC Liu, D Landheer, M Buchmann, and DC Houghton. Resonant tunneling diode in the Si1xGex system. Applied Physics Letters 52:1809–1811, 1988. 77. RC Taft, JD Plummer, and SS Iyer. Demonstration of a p-channel BiCFET in the GexSi1x /Si system. IEEE Electron Device Letters 10:14 –16, 1989. 78. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 253–256. 79. RA Soref, F Namavar, and JP Lorenzo. Optical waveguiding in a single-crystal layer of germanium– silicon grown on silicon. Optics Letters 15:270–272, 1990. 80. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. Enhancement-mode quantum-well GexSi1x PMOS. IEEE Electron Device Letters 12:154–156, 1991. 81. K Ismail, BS Meyerson, and PJ Wang. Electron resonant tunneling in Si/SiGe double barrier diodes. Applied Physics Letters 59:973–975, 1991. 82. DC Houghton, JP Noel, and NL Rowell. Electroluminescence and photoluminesence from SiGe alloys grown on (1 0 0) silicon by MBE. Materials Science and Engineering B 9:237–244, 1991. 83. DS Chen, JP Conde, V Chu, S Aljishi, JZ Liu, and S Wagner. Amorphous silicon–germanium thinfilm photodetector array. IEEE Electron Device Letters 13:5–7, 1992. 84. S-B Hwang, YK Fang, K-H Chen, C-R Liu, J-D Hwang, and M-H Chou. An a-Si:H/a-Si, Ge:H bulk barrier phototransistor with a-SiC:H barrier enhancement layer for high-gain IR optical detector. IEEE Transactions on Electron Devices 40:721–726, 1993. 85. DK Nayak, JCS Woo, GK Yabiku, KP MacWilliams, JS Park, and KL Wang. High mobility GeSi PMOS on SIMOX. IEEE Electron Device Letters 14:520–522, 1993. 86. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. High-mobility p-channel metal-oxide semiconductor field-effect transistor on strained Si. Applied Physics Letters 62:2853–2855, 1993. 87. J Welser, JL Hoyt, and JF Gibbons. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Device Letters 15:100–102, 1994. 88. SK Ray, S John, S Oswal, and SK Banerjee. Novel SiGeC channel heterojunction pMOSFET. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1996, pp. 261–264. 89. SJ Mathew, WE Ansley, WB Dubbelday, JD Cressler, JA Ott, JO Chu, PM Mooney, KL Vavanagh, BS Meyerson, and I Lagnado. Effect of Ge profile on the frequency response of a SiGe pFET on sapphire technology. Technical Digest of the IEEE Device Research Conference, Boulder, 1997, pp. 130–131. 90. K Rim, JL Hoyt, and JF Gibbons. Transconductance enhancement in deep submicron strained-Si n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1998, pp. 707–710. 91. KC Liu, SK Ray, SK Oswal, and SK Banerjee. Si1xGex /Si vertical pMOSFET fabricated by Ge ion implantation. IEEE Electron Device Letters 19:13–15, 1998. 92. S Thompson, N. Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, J Bielefeld, R Bigwood, J Brandenburg, M Buehler, S Cea, V Chikarmane, C Choi, R Frankovic, T Ghani, G Glass, W Han, T Hoffmann, M Hussein, P Jacob, A Jain, C Jan, S Joshi, C Kenyon, J Klaus, S Klopcic, J Luce, Z Ma, B McIntyre, K Mistry, A Murthy, P Nguyen, H Pearson, T Sandford, R Schweinfurth, R Shaheed, S Sivakumar, M Taylor, B Tufts, C Wallace, P Wang, C Weber, and M Bohr. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm2 SRAM Cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64.

© 2006 by Taylor & Francis Group, LLC

A Brief History of the Field

1.2-27

93. VP Kesan, S Subbanna, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, and JA Ott. High performance 0.25 mm p-MOSFETs with silicon–germanium channels for 300 K and 77 K operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 25–28, 1991. 94. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, AC Megdanis, CL Stanis, AA Bright, GMW Kroesen, and AC Warren. High-mobility modulation-doped, graded SiGe-channel p-MOSFETs. IEEE Electron Device Letters 12:447–449, 1991. 95. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Transactions on Electron Devices 41:90–102, 1994.

© 2006 by Taylor & Francis Group, LLC

2 SiGe and Si Strained-Layer Epitaxy 2.1

Overview: SiGe and Si Strained-Layer Epitaxy J.D. Cressler.................................. 2.1-31

2.2

Strained SiGe and Si Epitaxy B. Tillack and P. Zaumseil ........................................ 2.2-33 Introduction . Heteroepitaxy of SiGe and SiGe:C on Si . Characterization of Strained SiGe and Si Layers . Growth of Strained SiGe on Si . Summary

2.3

Si/SiGe(C) Epitaxy by RTCVD D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot.............................................................................................. 2.3-45 Introduction . Rapid Thermal Chemical Vapor Deposition . Epitaxy Processes . Epitaxy Integration . Recent Applications . Summary

2.4

MBE Growth Techniques M. Oehme and E. Kasper................................................. 2.4-85 Introduction . Requirements on an SiGe MBE System . UHV Conditions . Sources of Atomic and Molecular Beams . Substrate Heating and Cleaning . In Situ Analysis . Summary

2.5

UHV/CVD Growth Techniques T.N. Adam ............................................................. 2.5-95 Introduction . Chemistry . Low Temperature and Low Pressure . Alloys, Doping, and Selective Epitaxial Growth . Substrate Cleaning . Reactors

2.6

Defects and Diffusion in SiGe and Strained Si A.R. Peaker and V.P. Markevich.................................................................................. 2.6-107 Introduction . Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge . Effects of SiGe Alloy Composition and Strain on Defect Characteristics . Specific Defects in SiGe . Diffusion . Dislocations . Summary

2.7

Stability Constraints in SiGe Epitaxy A. Fischer ................................................... 2.7-127 Introduction . Image-Force Method for Strained Layer Relaxation . Surface Relaxation Stress . Interaction between Internal Stress and External Stress . Critical Thickness and Film Stress of SiGe/Si Layers . Plastic Deformation and Work Hardening in SiGe/Si . Force Balance Model for Buried SiGe Strained Layers . Summary

2.1-29 © 2006 by Taylor & Francis Group, LLC

2.1-30

The Silicon Heterostructure Handbook

2.8

Electronic Properties of Strained Si/SiGe and Si1-yCy Alloys J.L. Hoyt ........... 2.8-143 Introduction . Strain and its Impact on Energy Bands . Measurements of Energy Band Lineups . Introduction to Transport Properties . Summary

2.9

Carbon Doping of SiGe H.J. Osten........................................................................ 2.9-157 Introduction . Basic Considerations . Growth of C-Containing Alloys . Control of Dopant Diffusion by Adding Carbon . Strain Manipulation in Si1 x yGexCy Layers . Microscopic Structure of SiGeC Layers . Strain-Stabilized Layers with High C Concentration . Thermal Stability . Impact of Carbon on Electrical Layer Properties . Summary

2.10

Contact Metallization on Silicon–Germanium C.K. Maiti .............................. 2.10-171 Introduction . Contact Metallization: Current Status . Contact Metallization: Challenges . Poly-SiGe Gate Technology . Silicidation of SiGe . Silicidation of SiGeC . Summary

2.11

Selective Etching Techniques for SiGe/Si S. Monfray, S. Borel, and T. Skotnicki......................................................................................... 2.11-187 Introduction . Process Development for Industrial Applications . Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology . Summary

© 2006 by Taylor & Francis Group, LLC

2.1 Overview: SiGe and Si Strained-Layer Epitaxy

John D. Cressler Georgia Institute of Technology

The field of silicon heterostructures necessarily begins with materials, and the crystal growers of our field have learned through much hard work how to practice modern miracles in their growth of near defectfree, nanoscale films of Si and SiGe strained-layer epitaxy, which are compatible with conventional highvolume silicon integrated circuit manufacturing. Section 2 of this book tells the materials side of the story, and details the many advances in the Si–SiGe strained-layer epitaxy for device applications. Chapter 2.2, ‘‘Strained SiGe and Si Epitaxy,’’ by B. Tillack of IHP, reviews the underlying materials science of Si–SiGe epitaxy, while Chapters 2.3 to 2.5 discuss modern SiGe epitaxial growth techniques: RTCVD in Chapter 2.3, ‘‘SiGe:C Eiptaxy by RTCVD,’’ by D. Dutartre of ST Microelectronics, MBE in Chapter 2.4, ‘‘MBE Growth Techniques,’’ by M. Oehme and E. Kaspar of the University of Stuttgart, and UHV/CVD in Chapter 2.5, ‘‘UHV/CVD Growth Techniques,’’ by T. Adam of IBM. The complexity of epi defects and the dopant diffusion characteristics in such films are discussed by A. Peaker of the University of Manchester in Chapter 2.6, ‘‘Defects and Diffusion in Strained SiGe and Si,’’ and the most recent (and robust) stability theory is covered in Chapter 2.7, ‘‘Stability Constraints in SiGe Epitaxy,’’ by A. Fischer of IHP. The electrical transport properties of SiGe, strained Si, and Si–C alloys are detailed by J. Hoyt of MIT in Chapter 2.8, ‘‘Electronic Properties of Strained Si–SiGe and Si1 yCy alloys.’’ The basic mechanisms underlying the now-pervasive use of Cdoping in SiGe HBTs as a boron-doping diffusion inhibitor are reviewed in Chapter 2.9, ‘‘Carbon Doping of SiGe,’’ by J. Osten of the University of Hanover, and Chapter 2.10, ‘‘Contact Metallization on SiGe,’’ by C. Maiti of IIT, covers ohmic and Schottky contacts to SiGe and strained Si. Finally, Chapter 2.11, ‘‘Selective Etching Techniques for SiGe–Si,’’ by S. Monfray of ST Microelectronics, discusses the use of SiGe for selective etching in various emerging MEMS applications. In addition to this material, and the numerous references contained in each chapter, a number of review articles and books on SiGe–strained Si materials exist, including Refs. [1–6].

References 1. R People. Physics and applications of GexSi1 Quantum Electronics 22:1696–1710, 1986.

x /Si

strained layer heterostructures. IEEE Journal of

2.1-31 © 2006 by Taylor & Francis Group, LLC

2.1-32

The Silicon Heterostructure Handbook

2. JC Bean. Silicon-based semiconductor heterostructures: column IV bandgap engineering. Proceedings of the IEEE 80:571–587, 1992. 3. B Meyerson. UHV/CVD growth of Si and SiGe alloys: chemistry, physics, and device applications. Proceedings of the IEEE 80:1592–1608, 1992. 4. SC Jain. Germanium–Silicon Strained Layers and Heterostructures. New York, NY: Academic Press, 1994. 5. E Kaspar. Properties of Strained and Relaxed Silicon Germanium. London: INSPEC, EMIS Datareviews Series No. 12, 1995. 6. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. London: The Institute of Electrical Engineers, 2001.

© 2006 by Taylor & Francis Group, LLC

2.2 Strained SiGe and Si Epitaxy 2.2.1 2.2.2 2.2.3

Bernd Tillack and Peter Zaumseil IHP

2.2.4 2.2.5

Introduction................................................................. 2.2-33 Heteroepitaxy of SiGe and SiGe:C on Si................... 2.2-33 Characterization of Strained SiGe and Si Layers ....................................................................... 2.2-36 Growth of Strained SiGe on Si .................................. 2.2-39 Summary ...................................................................... 2.2-42

2.2.1 Introduction By adding Ge to Si new properties of the material can be created, which offer applications in a wide range of electronic devices. In this way the capability of Si electronics is widened. The SiGe heterojunction bipolar transistor (SiGe HBT), which makes use of SiGe bandgap engineering and strain, has reached industrial level (see Refs. [1, 2]) with increasing market potential. For future CMOS technologies SiGe and Si strained layers are becoming increasingly important, for instance, for higher mobility channel material [3, 4]. After the first report on growth of epitaxial SiGe layers dating back to 1962 [5], the pioneering work of Kasper (see, e.g., Ref. [6]) and Meyerson (see, e.g., Ref. [7]) became important milestones for the development of SiGe strained-layer epitaxy. After demonstrating the stability and high-volume production capability of SiGe strained-layer epitaxy for HBT base deposition using ultrahigh vacuum CVD (UHV CVD) [8] and low-pressure CVD (LP CVD) [9] the low-temperature epitaxial deposition of SiGe by CVD was ready to be used in manufacturing. Especially, the demonstration of the ability to grow device-quality SiGe layers without using UHV deposition techniques [10–14] has greatly influenced the development of strained-layer deposition process technology and tools. Adding C to SiGe has extended the capability of the material and has been another important step in the success story of SiGe:C strained-layer epitaxy for HBT application [15, 16]. C can significantly suppress B diffusion without negative impact on device parameters [16, 17]. The first BiCMOS technology using SiGe:C HBTs was demonstrated by IHP in 1999 [18]. As an example, Figure 2.2.1 shows a transmission electron microscopy (TEM) cross section of an HBT with SiGe:C base layer deposited by CVD. In this chapter, we will review the basic considerations regarding SiGe heteroepitaxy (Section 2.2.2) and strain relaxation. Moreover, characterization of SiGe layers (Section 2.2.3) and process aspects of growth of strained SiGe and SiGe:C on Si (Section 2.2.4) will be discussed.

2.2.2 Heteroepitaxy of SiGe and SiGe:C on Si Silicon and germanium have the same crystallographic structure. Both materials can be alloyed as Si1
xGex with any value of 0  x  1. The lattice constant of Ge is 4.18% larger than that of Si, and 2.2-33 © 2006 by Taylor & Francis Group, LLC

2.2-34

The Silicon Heterostructure Handbook

SiGe:C Base

100 nm

FIGURE 2.2.1

TEM cross section of HBT with pseudomorphic SiGe:C on Si (IHP’s first SiGe:C HBT generation).

for a Si1
xGex alloy it does not exactly follow Vegard’s law. The relative change of the lattice constant is given by [19] «¼

aSiGe
aSi ¼ 0:00501x 2 þ 0:03675x: aSi

Growing a Si1
xGex layer with x > 0 on a Si substrate means that the layer is under compressive stress. A perfect epitaxial growth of such a strained heteroepitaxial layer is only possible as long as its thickness does not exceed a critical thickness of stability [20]. Above this value, the strain is relaxed through the formation of misfit dislocations. The dislocation-free (pseudomorphic) SiGe layer on a 001 Si substrate surface shows a tetragonally distorted unit cell (see also Figure 2.2.2) with in-plane (ak) and perpendicular (a?) lattice constants given by ak ¼ aSi ;

a? ¼ aSi (1 þ k«);

with k ¼1þ

2C12 ffi 1:75: C11

In this case, the degree of relaxation is zero. For a fully relaxed layer the lattice constants ak and a? are equal:

© 2006 by Taylor & Francis Group, LLC

2.2-35

Strained SiGe and Si Epitaxy

a|| a⊥

SiGe

Si

(a)

(b)

FIGURE 2.2.2 Structural scheme of pseudomorphic (a) and fully relaxed (b) SiGe layer grown on Si substrate.

ak ¼ a? ¼ aSi (1 þ «): For a partly relaxed layer the lattice constants depend on both the Ge content and the degree of relaxation [21]. The consequence is that always ak and a? must be measured to determine the Ge content (and the degree of relaxation) as long as it is not definitely clear that a SiGe layer is either pseudomorphic or fully relaxed. Experimentally it was found that using low deposition temperatures (5508C and lower) it was possible to deposit pseudomorphic SiGe layers with thicknesses exceeding the critical thickness value [22, 23]. In these cases films are metastable. Nevertheless, by capping metastable SiGe films with Si, stabilization could be obtained resulting in SiGe–Si stacks that withstand thermal treatment during device processing (see Chapter 2.7, ‘‘Stability Constraints in SiGe Epitaxy’’). The strain situation is completely different for Si1
yCy layers. Carbon atoms are much smaller than Si atoms, and in consequence the lattice constant of Si1
yCy is smaller than that of silicon. Here, a deviation from Vegard’s law was also found [24]: «¼

aSiC
aSi ¼ 0:10504y 2
0:44909y: aSi

A Si1
x
yGexCy layer can be treated in first approximation as a mixture of a Si1
xGex and a Si1–yCy layer. The compressive strain of the SiGe can be (partly) compensated by the tensile strain of the added C, which will be demonstrated in detail in Section 2.2.3. Different modes were found during heteroepitaxy depending on the strain in the heteroepitaxial film and the growth conditions (mainly growth temperature) (Figure 2.2.3). Which growth mode for the epitaxial deposition is taking place is determined by the free energy of the interfaces and the lattice mismatch of the heteroepitaxial system. For most of the applications layer-by-layer growth (two-dimensional growth) is desired. In this case, the pseudomorphic films are obtained if the strain in the film does not exceed the critical thickness limitation or if the films are metastable, and partly relaxed films are obtained if the strain is relaxed by misfit dislocation formation [20, 25]. The mode can change from two-dimensional to three-dimensional (island growth) during growth if the strain increases or for high deposition temperatures (Stranski–Krastanow growth). Dislocation-free Stranski–Krastanow growth in particular has been investigated (e.g., Ref. [26]) because of its capability for optical applications. For selective heteroepitaxial growth it was found that the dislocation density depends on the area of the deposited films [27]. The dislocation density decreases with decreasing area. Even dislocation-free films with thicknesses above the critical thickness are possible for small areas.

© 2006 by Taylor & Francis Group, LLC

2.2-36

The Silicon Heterostructure Handbook

(a) Layer-by-layer growth

(b) Island growth

(Frank−van der Merwe)

(Volmer−Weber)

(c) Layer-by-layer followed by island growth (Stransky−Krastranow)

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

Substrate

FIGURE 2.2.3 Growth modes for heteroepitaxial systems. (From JW Matthews and AE Blakeslee. Defects in epitaxial multilayers. III. Preparation of almost perfect layers. J Cryst Growth 32:265–273, 1976; JH Van der Merwe. Crystal interfaces. Part II. Finite overgrowth. J Appl Phys 34:123–127, 1963; L Vescan, W Ja¨ger, C Dieker, K Schmidt, A Hartmann, and H Lu¨th. Formation of heterogeneous thickness modulations during epitaxial growth of LPCVDSi1
xGex /Si quantum well structures. MRS Symposium Proceedings, Vol. 263, Mechanism of Heteroepitaxial Growth Symposium, 1992, pp. 23–28. With permission.)

2.2.3 Characterization of Strained SiGe and Si Layers One of the main structural features of SiGe or SiGe:C layers is the difference in its lattice constant relative to the silicon substrate, which was already mentioned in Section 2.2.2. This difference in lattice constant, or strain, which correlates in the case of a pseudomorphically grown SiGe layer directly to the Ge content, offers the possibility of an easy characterization by X-ray diffractometry (XRD), where the lattice constant is transferred to a measurable diffraction angle via Bragg’s law 2d sin Q ¼ nl: In the following, we will discuss the application of XRD to characterize SiGe and SiGe:C structures. Later on, we will compare the results obtained by XRD with those obtained by other techniques, and give an outlook to further developments. Here, we restrict our discussion to pseudomorphic structures; fully or partly relaxed structures will be discussed elsewhere. The typical XRD arrangement consists of the X-ray source, a monochromator or collimator, the sample, and the detector. In the simple case, the collimator consists of a perfect Si crystal of the same orientation as the sample (Figure 2.2.4). Modern diffractometers often use the so-called Bartel’s monochromators and additional mirrors as collimator to make the arrangement more flexible. For some applications, an additional analyzer crystal is used in front of the detector. A rocking curve is measured by rotating the sample around a substrate diffraction peak DQ (typically of the netplanes parallel to the surface) and correcting the detector position in such a way that the diffracted beam enters the detector window at the same position always (Q/2Q scan). How the diffractometer arrangement influences the measured rocking curve of a SiGe structure was demonstrated in Ref. [28]. Figure 2.2.5 shows as an example the CuKa-400-diffraction of a 117 nm thick Si0.8Ge0.2 layer with a 56 nm thick Si cap layer on top. For such a relatively simple structure, the Ge content can be directly obtained from the angular distance between Si and SiGe peak. The width of the SiGe peak is a direct measure of the SiGe layer thickness. But, the comparison with the calculated curve without the Si cap layer shows that it is difficult to estimate the thickness of the cap layer from the diffraction pattern directly. The situation becomes even worse for more complicated structures, for example, structures with graded SiGe layers (see below). The determination of the depth profile of such structures is only possible by creating a reasonable layer model, simulation of the diffraction curve of this model, and fitting the simulated curve to the experimental one by modification of free parameters.

© 2006 by Taylor & Francis Group, LLC

2.2-37

Strained SiGe and Si Epitaxy

Detector

Collimator

2 ∆Q X-ray source

∆Q

Sample

FIGURE 2.2.4 Scheme of a double crystal diffractometer arrangement.

10−1 10−2

exp.: 56 nm Si /117 nm Si0.8Ge0.2 /Si sim.: no cap/117 nm Si0.8Ge0.2 /Si

x

Reflectivity

10−3

dSiGe

10−4

10−6 10−7 −3000

−2500

−2000 −1500 −1000 −500 Delta theta (arcsec)

Si substrate

SiGe layer

10−5

0

500

FIGURE 2.2.5 Experimental diffraction curve of a SiGe layer with a Si cap layer on top and a simulated curve without the cap layer; CuKa radiation, 400 reflection. The simulated curve is shifted by one order of magnitude relative to the experimental one.

For Si1
yCy layers, the diffraction curve would be similar but with the Si1
yCy peak on the right-hand side of the Si substrate peak (high angle side). A Si1
x
yGexCy layer can be treated in first approximation as a mixture of a Si1
xGex and a Si1–yCy layer. The compressive strain of the SiGe can be (partly) compensated by the tensile strain of the SiC. Figure 2.2.6 shows an XRD measurement with calculated rocking curves of a 100-nm thick SiGeC layer with 20% Ge. The SiGeC peak shift as a function of the C content indicates strain compensation by adding C to SiGe. Since XRD measures primarily the strain of the layer relative to the substrate, and for Si1
x
yGexCy this strain is the sum of two components, it is impossible to determine the Ge and the C content without independent information about one of the components. Usually, to get the C content of a SiGeC layer we deposit a SiGe layer with the same Ge deposition parameters for comparison. Then the Ge content is measured at the SiGe sample, and assuming the same for the SiGeC sample the C content can be obtained. To characterize an HBT structure under conditions of a routine process control, the following requirements must be fulfilled: the depth resolution should be in the order of about 1 nm; the accuracy of the absolute Ge content should be better than 0.5%; it must be nondestructive, fast, and reliable. This is a real challenge for XRD, especially when the Ge content is not constant over the layer thickness as in typical HBT structures.

© 2006 by Taylor & Francis Group, LLC

2.2-38

The Silicon Heterostructure Handbook

10−1 Carbon content

Reflectivity

10−2 10−3

0%

0.5% 1% 1.5% 0.25% 0.75% 1.25%

1.75%

10−4 10−5 10−6 10−7 −2500 −2000 −1500 −1000 −500

0

500

Delta theta (arcsec)

FIGURE 2.2.6 Calculated rocking curves of a 100 nm thick SiGeC layer with 20% Ge and increasing carbon content; CuKa radiation, 400 reflection.

100

(b)

xmax = 20.9 ± 0.5 %

20 Ge content (%)

Reflectivity

10−1

25 exp. sim.

(a)

10−2 10−3 10−4 10−5

15 10

10−6 −3000

−2000 −1000 0 Delta theta (arcsec)

0 1000

dSiGe (nm)

dSi cap (nm) 59.6 ± 1.2

5

0

20

40

45.9 ± 0.6 60

80

100

120

140

Depth (nm)

FIGURE 2.2.7 XRD rocking curve (a) of a SiGe HBT structure. The full line represents the best-fitted simulated curve. The Ge depth profile is shown in (b).

Figure 2.2.7 shows as an example the characterization of an HBT structure. Due to the gradient part of the Ge profile, the rocking curve (a) shows less details compared to the simple layer structure (Figure 2.2.5). Here, it is absolutely necessary to simulate curves with a suited model and to fit this in a trial-anderror procedure to the experimental one, since it is practically impossible to get any direct information from the rocking curve. The depth profile of Ge content that gave the best fit of the rocking curve is shown in Figure 2.2.7b. The gradient part of the Ge profile is divided into 11 lamellae of constant strain. Since the thickness of each lamella is a free parameter in the fitting process, the shape of this profile part need not be linear. It should fit to the real shape within the sensitivity limits of this technique. The accuracy depends on the stability of the fitting procedure, supposing the model used describes the real situation in a proper way [29]. This is mainly influenced by the statistical intensity fluctuations (noise) in the RC range far away from the Si substrate peak. Following this, the accuracy is given by the intensity of the X-ray source used or the measuring time. For similar structures to that shown in Figure 2.2.7, an error in the layer thickness of 0.4 to 1.0 nm and of less than 0.4% of the maximum Ge content is typically achievable with an intensity of about 500 kcps in the incident beam and a measuring time of less than 1 h.

© 2006 by Taylor & Francis Group, LLC

2.2-39

Strained SiGe and Si Epitaxy TABLE 2.2.1

Summary of Main Features of Investigated Techniques for HBT Stack Characterization

Technique

Destructive

XRD XRR SE AES SIMS TEM

No No No Yes Yes Yes

Accuracy of Measurement

Area

2

>0.5  0.5 mm (cm) 14  28 mm2 0.1  0.1 mm2 60  60 mm2 (mm)

IF Roughness

dSi cap (nm)

dSiGe (nm)

xmax(%)

1.0 0.5 1.0 — 3.0 1.0

0.6 0.5 1.0 5.0 3.0 1.0

0.5 3–6 1 1–3 3–5 —

(
) þþ


(þ)

Besides XRD, there are many other analytical techniques available to study SiGe or SiGe:C HBT structures. In Ref. [30], the capabilities of six different techniques are discussed; three nondestructive methods: XRD, X-ray reflectometry (XRR), and spectroscopic ellipsometry (SE); and three destructive methods: Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS), and TEM. The main result was that every technique has its advantages and disadvantages, and they all can be used successfully either in process development, failure analysis, or in-line monitoring of the epitaxy process. Within the error limits of each technique, the HBT parameters obtained agreed quite well. Table 2.2.1 summarizes the main features of these techniques. XRD plays an outstanding role, since this technique was used to calibrate other techniques, such as SE, AES, and SIMS, with suitable simple SiGe layer structures. The main disadvantage of XRD for an inline routine application is its limited lateral resolution. A minimum spot size for laboratory devices of about 0.5  0.5 mm2 is sufficient to measure on monitoring areas of the same size [31] but far too large for measurements on real device structures. The alternative for future use is SE. This method allows measurements in micrometer areas; it is fast and well established in microelectronics technology. The procedure [32] includes the creation of databases for the refractive index dispersion of all components of HBT stacks using simple one-layer structures with thickness and composition calibrated by XRD. Then these databases (e.g., SiGe:C optical constants versus Ge-content) can be applied for thickness and composition determination of graded HBTs with different shapes of profiles. The achievable accuracy in layer thickness and Ge content determination is comparable to XRD.

2.2.4 Growth of Strained SiGe on Si The critical thickness limitation and the thermal stability (metastable layers) of strained SiGe films on Si cause severe limitations for the integration into Si process technology. The deposition of pseudomorphic SiGe layers itself requires low-temperature process technique. For the integration into CMOS or BiCMOS technologies the impact of the thermal budget of the deposition process on existing structures as well as the interaction of thermal treatment of the processing with the deposited SiGe layer has to be considered. The low temperature requirement for the deposition techniques has different aspects: 1. For low-temperature deposition the moisture and oxygen level in the reaction chamber is more critical compared to high temperature. 2. The low-temperature deposition process is controlled by the kinetics, which means that process conditions, especially process temperature and partial pressures of source gases, are essentially impacting the parameters of the deposited films like deposition rate, incorporation of Ge, C, and dopants. To grow films according to manufacturing requirements with uniform thickness, composition, and dopant distribution, the temperature has to be controlled during the process and across the wafer very accurately.

© 2006 by Taylor & Francis Group, LLC

2.2-40

The Silicon Heterostructure Handbook

3. For the integration of SiGe into CMOS or BiCMOS low thermal budget deposition is required. The thermal budget of SiGe heteroepitaxy using CVD techniques is mainly determined by the H2 prebake before deposition to clean the substrate surface at temperatures typically between 9508C and 10008C. Different low-temperature deposition techniques have been developed for strained SiGe epitaxy on Si. Today, heteroepitaxy by CVD is in production with proven stability and manufacturability. In the following part, key aspects, requirements, and challenges for SiGe CVD epitaxy will be discussed. For the deposition of epitaxial SiGe layers with low defect densities a clean substrate surface with low contamination level is essential. Cleaning of the substrate is achieved by combination of ex situ wet chemical treatment and in situ H2 prebake in the reaction chamber before epitaxial deposition [33, 34]. The cleaning effect of the prebake improves with increasing temperature. However, it has to be compromised with the demand of a minimum thermal budget necessary for process integration into CMOS and BiCMOS. The kind of surface passivation after wet chemical treatment impacts the minimum H2 prebake temperature necessary for effective contamination removal. An oxide passivation was achieved by a final SC-2 treatment at standard conditions (HCl þ H2O2 þ H2O at 758C to 858C). The chemically grown oxide during SC-2 has to be removed during the prebake, resulting in higher bake temperatures of about 8908C. By applying hydrogen passivation generated by final DHF dip followed by a DI water rinse in combination with an optimized bake regime (maximum temperature for about 3 sec, with a ramp rate of higher than 708C/sec) the bake temperature could be lowered to temperatures below 8008C [33]. Figure 2.2.8 demonstrates, by means of SIMS, the effect of the prebake temperature on the O and C concentrations at the interface between substrate and epitaxial layer for oxygen-passivated surface (Figure 2.2.8a) and hydrogen-passivated surface (Figure 2.2.8b). The impact of defects caused by insufficient H2 prebake during the growth of the epitaxial Si–SiGe–Si layer stack on HBT leakage currents was shown in Ref. [34].

8908 C

1021

7608C

1021

Si epitaxy | substr.

Si epitaxy | substr. 1020

1019 O C

1018 1017

8608 C Si epitaxy | substr.

1021 1020

O, C Concentration (cm-3)

O, C Concentration (cm-3)

1020

C

1018

O

1017 7308C

1021

Si epitaxy | substr. 1020 1019

1019 O C

1018 1017

1019

C

1018

O

1017 0

(a)

50 100 150 200 250 Depth (nm)

0 (b)

50 100 150 200 250 Depth (nm)

FIGURE 2.2.8 SIMS profiles illustrating the oxygen and carbon removal at the epitaxy substrate interface for (a) oxygen passivated (standard RCA cleaning), and (b) hydrogen passivated surface (DHF treatment) with corresponding hydrogen prebake temperatures.

© 2006 by Taylor & Francis Group, LLC

2.2-41

Strained SiGe and Si Epitaxy

After cleaning of the Si surface by H2 prebake the SiGe (or SiGe:C) heteroepitaxy is performed at temperatures typically between 5008C and 7008C depending on the target layer parameters, especially the Ge content. In this temperature range the growth is kinetically controlled. Figure 2.2.9 shows the growth rate as a function of the reciprocal temperature for different GeH4 partial pressures at constant SiH4 partial pressure. GeH4 and SiH4 are the sources for the SiGe layer growth. Hydrogen is used as carrier gas. The activation energies determined from the plots in Figure 2.2.9 are decreasing with increasing GeH4 partial pressure (increasing Ge concentration). For the lowest GeH4 partial pressure, the activation energy is 1.9 eV, which is close to the value obtained for pure Si deposition and discussed as the activated energy of the desorption of H from the Si surface. Adding GeH4 is supporting the desorption of H, resulting in lower activation energies. Deposition pressures between low-pressure conditions (typical 1 to 2 Torr) to atmospheric pressure have been used. The most common tools are working in the reduced pressure range of about 100 Torr for the deposition. The Ge concentration in the SiGe layer is controlled by the GeH4 partial pressure for constant SiH4 partial pressure and temperature (Figure 2.2.10). The incorporation of Ge is impacted by the growth

0.4 Pa 0.24 Pa 0.14 Pa 0.06 Pa

Rate (nm/min)

100

10

EA 1,31 ± 0.01 eV

1 1,65 ± 0.05 eV 1,81 ± 0.08 eV

0.1 1.05

1,90 ± 0.11 eV

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1000/T (K-1)

FIGURE 2.2.9 SiGe deposition rate as function of the reciprocal temperature for different GeH4 partial pressures, constant SiH4 pressure and H2 as carrier gas, and resulting activation energies.

Ge concentration (at.%)

40

30

20 500
C 550
C 600
C 650
C 700
C

10

0 0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

GeH4 /SiH4

FIGURE 2.2.10

Ge concentration in SiGe as a function of the GeH4 to SiH4 ratio for different growth temperatures.

© 2006 by Taylor & Francis Group, LLC

2.2-42

The Silicon Heterostructure Handbook

temperature. The Ge content in the SiGe layer decreases with increasing temperature for constant GeH4 and SiH4 partial pressure. Therefore, for higher Ge content lower growth temperatures have to be applied. Moreover, for SiGe layers with high Ge content grown at high temperature, island growth and relaxation are more likely. In the case of SiGe:C epitaxy the growth temperature is impacting the incorporation of C into SiGe. Lower growth temperatures are beneficial for incorporation of C on substitutional sites. At high growth temperature (and high C content), C tends to be incorporated interstitially degrading the crystalline and electrical properties of the layers.

2.2.5 Summary Today SiGe-strained epitaxy is meeting manufacturing requirements and it is a proven process in microelectronics technology for bipolar (HBT) and CMOS (strained Si) applications. There is still a great potential of SiGe, Si, and Ge layers for future devices and technologies. Despite the fact that strained-layer epitaxy is managed very well using commercially available deposition tools there is room for further improvement, for example, in low-temperature processing and increase in throughput. A very interesting topic for further development of epitaxy is the atomic layer processing approach for atomic level control of doping and deposition [35–37].

Acknowledgment The authors would like to thank the IHP technology team for support and for the preparation of the SiGe–SiGe:C layers and HBT processing.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. R Singh, DL Harame, and MM Oprysko. Silicon Germanium Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 3. S Verdonckt-Vanderbroek, F Crabbe, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe channel heterojunction p-MOSFET’s. IEEE Trans Electron Dev 41:90–101, 1994. 4. T Ghani, M Armstrong, C Auth, M Bost, P Charvat, G Glass, T Hoffmann, K Johnson, C Kenyon, J Klaus, B McIntyre, K Mistry, A Murthy, J Sandford, M Siberstein, S Sivakumar, P Smith, K Zawadzki, S Thompson, and M Bohr. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 978–980. 5. KJ Miller and MJ Grieco. Epitaxial silicon-germanium alloy films on silicon substrates. J Electrochem Soc 109:70–71, 1962. 6. E Kasper and HJ Herzog. Elastic strain and misfit dislocation density in Si0.92Ge0.08 films on silicon substrates. Thin Solid Films 44:357–370, 1977. 7. BS Meyerson. UHV/CVD growth of Si and Si:Ge alloys: Chemistry, physics, and device applications. Proc IEEE 80:1592–1608, 1992. 8. DC Ahlgren, M Gilbert, D Greenberg, SJ Jeng, J Malikowski, D Nguyen-Ngoc, K Schonenberg, K Stein, R Groves, K Walter, G Hueckel, D Colavito, G Freeman, D Sunderland, DL Harame, and B Meyerson. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1996, pp. 859–862. 9. B Tillack, D Bolze, G Fischer, G Kissinger, D Knoll, G Ritter, P Schley, and D Wolansky. SiGe heteroepitaxy for high frequency circuits. MRS Symposium Proceedings, Vol. 525, Rapid Thermal and Integrated Processing VII, 1998, pp. 379–384.

© 2006 by Taylor & Francis Group, LLC

Strained SiGe and Si Epitaxy

2.2-43

10. G Ritter, B Tillack, and D Knoll. Successful preparation of high frequency HBT by integrated RTCVD processes. MRS Symposium Proceedings, Vol. 387, Rapid Thermal and Integrated Processing IV, 1995, pp. 341–346. 11. D Dutartre, P Warren, I Berbezier, and P Perret. Low temperature silicon and Si1
xGex epitaxy by rapid thermal chemical vapour deposition using hydrides. Thin Solid Films 222:52–56, 1992. 12. JC Sturm, PV Schwartz, EJ Prinz, and H Manoharan, Growth of Si1
xGex by rapid thermal chemical vapor deposition and application to heterojunction bipolar transisitors. J Vac Sci Technol B 9:2011– 2016, 1991. 13. WB de Boer and DJ Meyer. Low temperature chemical vapor deposition of epitaxial Si and SiGe layers at atmospheric pressure. Appl Phys Lett 58:1286–1288, 1991. 14. CA King, JL Hoyt, DB Noble, CM Gronet, JF Gibbons, MP Scott, SS Laderman, TI Kamins, and J Turner. Epitaxial growth of Si1
xGex /Si heterostructures by limited reaction processing for minority carrier device applications. MRS Symposium Proceedings, Vol. 146, Rapid Thermal Annealing /Chemical Vapor Deposition and Integrated Processing Symposium, 1989, pp. 71–82. 15. B Heinemann, D Knoll, G Fischer, D Kru¨ger, G Lippert, HJ Osten, H Ru¨cker, W Ro¨pke, P Schley, and B Tillack. Control of steep boron profiles in Si/SiGe heterojunction bipolar transistors. ESSDERC: Proceedings of the 27th European Solid-State Device Research Conference, Stuttgart, 1997, pp. 544–547. 16. HJ Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe heterobipolar transistor performance and process margin. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1997, pp. 803–806. 17. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillack, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 18. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116. 19. JP Dismukes, L Ekstrom, and RI Paff. Lattice parameter and density in germanium–silicon alloys. J Phys Chem 68:3021–3027, 1964. 20. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers. III. Preparation of almost perfect layers. J Cryst Growth 32:265–273, 1976. 21. P Zaumseil. A fast X-ray method to determine Ge content and relaxation of partly relaxed Si1
xGex layers on silicon substrates. Phys Stat Sol (a) 141:155–161, 1994. 22. R People, and J Bean. Erratum: calculation of critical layer thickness versus lattice mismatch for GexSi1
x /Si strained-layer heterostructures. Appl Phys Lett 49:229, 1986. 23. E Kasper, A Schuh, G Bauer, B Holla¨nder, and H Kibbel. Test of Vegard’s Law in thin epitaxial SiGe layers. J Cryst Growth 157:68–72, 1995. 24. F Berti, D De Salvador, A V Drigo, F Romanato, J Stangl, S Zerlauth, F Scha¨ffler, and G Bauer, Lattice parameter in Si1
yCy epilayers: deviation from Vegard’s rule. Appl Phys Lett 72:1602–1604, 1998. 25. JH Van der Merwe. Crystal interfaces. Part II. Finite overgrowth. J Appl Phys 34:123–127, 1963. 26. L Vescan, W Ja¨ger, C Dieker, K Schmidt, A Hartmann, and H Lu¨th, Formation of heterogeneous thickness modulations during epitaxial growth of LPCVD-Si1
xGex /Si quantum well structures. MRS Symposium Proceedings, Vol. 263, Mechanism of Heteroepitaxial Growth Symposium, 1992, pp. 23–28. 27. T Stoica and L Vescan. Misfit dislocations in finite lateral size Si1
xGex films grown by selective epitaxy. J Cryst Growth 131:32–40, 1993. 28. P Zaumseil. A comparison of different multiple-crystal diffractometer arrangements to measure the reflection curve of SiGe layers on Si substrates. Cryst Res Technol 31:529–537, 1996. 29. P Zaumseil. High resolution determination of the Ge depth profile in SiGe heterobipolar transistor structures by X-ray diffractometry. Phys Stat Sol (a) 165:195–204, 1998.

© 2006 by Taylor & Francis Group, LLC

2.2-44

The Silicon Heterostructure Handbook

30. P Zaumseil, D Kru¨ger, R Kurps, O Fursenko, and P Formanek. Precise measurement of Ge depth profiles in SiGe HBT’s — a comparison of different methods. Solid State Phenomena 95–96:473–482, 2004. 31. P Zaumseil, TA Lafford, and M Taylor. Inline characterization of SiGe structures on 8-inch Si wafers using the Bede QC200 X-ray diffractometer. J Phys D Appl Phys 34:A52–A56, 2001. 32. O Fursenko, J Bauer, P Zaumseil, D Kru¨ger, A Goryachko, Y Yamamoto, K Ko¨pke, and B. Tillack. Spectroscopic ellipsometry for in-line process control of SiGe:C HBT. Proceedings of the Second International SiGe Technology and Device Meeting, ISTDM 2004, Frankfurt(Oder), Germany, 2004, pp. 53–54. 33. D Wolansky, B Tillack, K Blum, KD Bolze, KD Glowatzki, K Ko¨pke, D Kru¨ger, R Kurps, G Ritter, and P Schley. Low temperature clean for Si/SiGe epitaxy for CMOS integration of HBTs. Electrochem Soc Proc 98-1:812–821, 1998. 34. D Wolansky, GG Fischer, D Knoll, D Bolze, B Tillack, P Schley, and Y Yamamoto. Impact of defects on the leakage currents of Si/SiGe/Si heterojunction bipolar transistors. Solid State Phenomena 95–96:249–254, 2004. 35. J Murota, M Sakuraba, and B Tillack. Atomically controlled technology for future Si-based devices. Solid State Phenomena 95–96:607–616, 2004. 36. B Tillack, Y Yamamoto, D Knoll, B Heinemann, P Schley, B Senapati, and D Kru¨ger. High performance SiGe:C HBTs using atomic layer base doping. Appl Surf Sci 224:55–58, 2004. 37. B Tillack, B Heinemann, and D Knoll. Atomic layer doping of SiGe — fundamentals and device applications. Thin Solid Films 369:189–194, 2000.

© 2006 by Taylor & Francis Group, LLC

2.3 Si–SiGe(C) Epitaxy by RTCVD 2.3.1 2.3.2

Introduction................................................................. 2.3-45 Rapid Thermal Chemical Vapor Deposition ............ 2.3-46 Background . Equipments . Process Capabilities Pros and Cons

2.3.3

.

Epitaxy Processes......................................................... 2.3-49 Surface Preparation . Low-Temperature Epi . Germanium Incorporation . Carbon Incorporation . Selective Epitaxy

2.3.4

Epitaxy Integration...................................................... 2.3-63 Thermal Budget Limitation . Loading Effects . Deposition Morphology . Pattern-Induced Defectivity

D. Dutartre, F. Dele´glise, C. Fellous, L. Rubaldo, and A. Talbot

2.3.5

Recent Applications..................................................... 2.3-74

ST Microelectronics

2.3.6

Summary ...................................................................... 2.3-80

SEG-Based Bipolar . Double Gate MOS . FD-SOI

2.3.1 Introduction At this time, about 15 to 20 years after a real breakthrough in Si1
xGex (SiGe) growth, it is of interest to reflect upon developments and progress made in this field. On the one hand, Si-based alloys, namely Si1
x
y GexCy (SiGeC), are well known to be key materials for extending the capabilities of the silicon technology that is very dominant in electronics. These alloys, indeed, are fully compatible with this technology and have various characteristics (electronic, chemical, mechanical, and optical) that can be used for a number of proven and potential applications as detailed throughout this book. On the other hand, the development of SiGe growth techniques has been highly competitive, it is probably unique that the deposition of a material was simultaneously studied over the complete pressure domain available, from 10
8 Torr by molecular beam epitaxy to 760 Torr by chemical vapor deposition (CVD), and using a variety of CVD techniques like ultrahigh vacuum (UHV), very low pressure, low pressure, reduced pressure, atmospheric and plasma-enhanced CVD, chemical beam epitaxy, etc. However, rapid thermal chemical vapor deposition (RTCVD), first invented and developed in homemade tools or in prototypes, made rapid and impressive progresses, especially in low-temperature SiGe epitaxy (epi), and was rapidly introduced in industrial tools. Finally, this technique took the leadership for SiGe epi. Today, one can say that RTCVD and SiGe(C) epitaxy have been married for the better: RTCVD has been demonstrated to be a very effective technique for growing SiGe epitaxial layers and SiGe a powerful booster for RTCVD. Thus, blanket epitaxies of SiGe on full-sheet silicon wafers, and after SiGeC ones, were rapidly demonstrated in pioneer RTCVD studies. However, epitaxial depositions that are required today may

2.3-45 © 2006 by Taylor & Francis Group, LLC

2.3-46

The Silicon Heterostructure Handbook

be much more complex, and have in most cases to be integrated in advanced technologies: i.e., on wafers patterned with very fine structures and with drastic thermal budget limitations. This chapter focuses on the current developments of SiGe and SiGeC epitaxies by RTCVD and their integration in complex technologies. Section 2.3.2 presents the RTCVD technique in terms of equipments and process capabilities for SiGe epi. This technique is also compared to the other important epi techniques and our conclusion at the advantage of RTCVD is in accordance with the success of this technique. Section 2.3.3 details the important points of the Si-based alloy epitaxy: surface preparation, low-temperature epi (LTE), germanium and carbon incorporation, and selective epi. LTE is usually obtained with hydrides like silane- or chlorides-like dichlorosilane (for selective epi). Both systems are considered and surface reactions that are known to play a major role are reviewed. On the other hand, the main features of strained SiGe epi and of carbon incorporation are reported and discussed. Section 2.3.4 is devoted to the integration issues. Among the huge number of possible points, we chose those that are actually met by the process engineer who has to manage epi for the creation of devices in modern technologies. Note that some of these points, pattern-induced defectivity as an example, are not so frequently reported in literature. Finally, Section 2.3.5 illustrates the RTCVD capabilities giving a few examples of current applications developed at STMicroelectronics. As a number of applications will be detailed in following chapters, the selection is very limited: epitaxial base of heterojunction bipolar transistor, epi for gate-all-around MOS and epi on ultrathin silicon on insulator films. Examples were chosen in order to give a certain panorama of applications and of epi issues.

2.3.2 Rapid Thermal Chemical Vapor Deposition Background CVD consists in the deposition of a solid film on a substrate by the reaction of vapor-phase reactants (precursors). The substrate temperature provides the energy to activate the chemical reactions. As illustrated in Figure 2.3.1, the sequential steps of this process are the following: . . . . .

Transport of precursor gas into reactor by forced convection Diffusion to surface and adsorption of precursor molecules on surface Surface reactions (decomposition and recombination) and incorporation into solid film Desorption of by-product molecules and diffusion into the gas phase Evacuation of gaseous by-products from reactor

RTCVD is defined as a CVD technique capable of a rapid switching of the process temperature. This technique is very interesting as the temperature agility allows the thermal budget to be minimized and different films to be grown using different ‘‘adapted’’ temperatures. Gibbons et al. [1] first reported such a technique, and referred it as ‘‘limited reaction processing’’ (LRP); a stable gas flow was established with the wafer at low temperature and deposition was switched on and off by rapidly heating and cooling the

(e) Product evacuation

(a) Precursor transport

(d) Product desorption

(b) Gas diffusion Adsorption

(c) Surface reactions

Nuclei

Growth

Substrate

FIGURE 2.3.1 Generic steps of a CVD process: (a) reactant transport, (b) reactant diffusion, (c) surface reactions, (d) by-product desorption, and (e) by-product evacuation.

© 2006 by Taylor & Francis Group, LLC

2.3-47

Si–SiGe(C) Epitaxy by RTCVD

wafer. This technique was demonstrated to be very effective for some processes, Si epitaxy as an example, but it also presents important drawbacks especially in terms of process control. Thus, the majority of investigators preferred to use gas flow switching rather than temperature to control growth, and then the technique has been more often referred as RTCVD. On the other hand, RTCVD has been found to significantly relax the stringent temperature or cleanliness conditions for epitaxial growth; and within a few years, a considerable amount of research was devoted to the application of this technique to the silicon and SiGe epi. The present contribution will be restricted to these applications.

Equipments Beyond the pioneer work, various reactors were developed and important refinements were introduced: infrared pyrometer for temperature control and loadlock for moisture contamination reduction [2, 3]. Basically, the minimal common features of these systems were: single-wafer susceptor-less configuration, lamp heating, cold walls, and low pressure (a few Torr). Rapidly, using relatively simple tools, very impressive material demonstrations were made in the domain of Si–SiGe epi: high structural quality epi (proved by excitonic emission) [4, 5], functional HBTstructures [6], ultra-abrupt dopant profiles [7], etc. However, in the majority of RTCVD reactors, as a consequence of poor temperature control and gas flow design, the deposition uniformity was not good enough for industrial applications. Around 1990, for the first time a new production epitaxy reactor, the ‘‘Epsilon One’’ from ASM company [8], included some above-mentioned features for RTCVD: single-wafer, lamp heating, loadlock, etc., but it also used a susceptor and substrate rotation for better temperature control and uniformity improvement. More recently, ‘‘Applied Materials’’ also introduced the ‘‘Centura-HTF’’ reactor, which is a similar system. Despite the temperature ramps are slowed down by the presence of a rotating susceptor, in the author’s opinion these tools have been considered as RTCVD epi reactors. The schematics of these modern vapor-phase epitaxy (VPE) systems typically consists of four modules: the process module, the transfer module, the gas control box, and automation. These systems are fully automatic and 25 or 50 wafers can be processed either using a given recipe, in production mode, or various recipes, for research and development (R&D); a variety of process parameters and hardware configurations can also be controlled. The gas distribution system is designed with ultrapurity standards and allows precise gas injection onto the wafer with short (<1 sec) switching transients. The transfer module, preferably at reduced pressure, isolates the process chamber from any atmospheric contamination at each loading or unloading of wafers. These systems process a single wafer at a time in a low-profile, horizontal deposition chamber that is shown schematically in Figure 2.3.2. The chamber walls are made of fused quartz, and air-cooling allows the quartz to remain at moderate temperatures, about half the wafer temperature (in Celsius). Any stainless steel part is outside of the chamber or protected by quartz liners, and is water-cooled,

Quartz wall Radiative emission

Radiative heating

Heat conduction

Process gas flow

Wafer

Ring

Susceptor Rotation

FIGURE 2.3.2 Schematic cross section of a typical RTCVD reactor. The process gases make a single pass over the rotating wafer and susceptor assembly that are heated from top and bottom by tungsten halogen lamps.

© 2006 by Taylor & Francis Group, LLC

2.3-48

The Silicon Heterostructure Handbook

this way any metal corrosion by chloride is minimized. For process, the wafer is placed on a SiC-coated graphite susceptor and both parts are radiantly heated from both sides by external tungsten halogen lamps. The top and bottom heating allow the temperature difference between the wafer and the susceptor to be minimized, then improving control and uniformity of temperature (see ‘‘Low-Temperature Epi’’). In the same way, the radiative heating can be adjusted along the wafer radius to tune the radial uniformity. For control, temperature is measured either by a pyrometer (Applied Materials) or a thermocouple (ASM). A process gas enters from the right of the figure and makes a single pass over the wafer. Finally, the chamber is evacuated by combination of a high-capacity Roots blower with a mechanical dry pump, and processes can be run in a large pressure range (1 to 760 Torr).

Process Capabilities Let us start with temperature agility, the first characteristic of RTCVD. In susceptor-less lamp-heated systems, the time constant, related to the thermal inertia of wafer, like in rapid thermal annealing tools, is in the range 1 to 4 sec. That roughly corresponds to the time of ramp up and down between a process temperature and a temperature significantly lower (a temperature at which the kinetics of important physical mechanisms has decreased by a decade). Unfortunately, the systems with the highest level of development do have a susceptor. In this case, the time constant is less aggressive, between 10 and 30 sec as a function of system and process. This characteristic is nevertheless useful to facilitate and make some processes more effective, including epi. A rapid hydrogen bake is possible, 30 sec at 9008C for example, and the epi temperature can be adapted to the epi deposition or even to the different parts of a complex stack. As seen below, silicon epi requires higher temperatures, as compared to SiGe epi. On the other hand, the temperature control, maybe the most critical point as it is not as perfect as desired, will be discussed in ‘‘Low-Temperature Epi.’’ Considering the chamber design, we believe that the low-profile horizontal geometry is important. In most of the experimental conditions, it induces first a laminar flow beneficial in terms of uniformity and particles, and second a relatively high chemical efficiency as precursor molecules have to pass close to the wafer. On the other hand, the susceptor rotation, with a significant speed (10 to 50 rpm), is useful to smooth temperature variations and to level the flow and depletion of reactants. In addition, as the two industrial tools mentioned present the capability of reduced pressure, the residence time of precursors in chamber can be then reduced by an important (10 to 100) factor. This reduced time, together with a limited hot volume because of the cold walls, will eliminate or minimize the possibility of homogeneous gas-phase nucleation. Thus, it appears that RTCVD is a technique well adapted for the utilization of very reactive precursor gases. Typical processes and some process details will be given in the next section. However, the major advantages of this important technique can be summarized as follows: . . . . . . . . .

Temperature agility Cold walls (at least significantly colder than the substrate) External heater Cleanliness of gases Process flexibility (temperature and pressure range) Chemistry flexibility (hydrides and chlorides) Ability to work in both deposition regimes (surface or mass transport-limited kinetics) In situ chamber cleaning (usually with HCl at high temperature) Mature and industrial technique

as well as the main drawbacks: . . .

Complex temperature uniformity and temperature control Complexity of CVD growth kinetics Productivity of low-temperature and growth rate processes

© 2006 by Taylor & Francis Group, LLC

2.3-49

Si–SiGe(C) Epitaxy by RTCVD TABLE 2.3.1

Performances of Current Epitaxy Techniques for Si and SiGe(C) Applications

Process Capabilities

Technique PECVD (single)

Epi domain Thin films Thick films Temperature domain High T Low T Ultralow T Process domain Surface-limited Mass transport Selective epi (against Si3N4) Crystal quality Low defectivity: particle-induced High chemical purity Process flexibility (P, T, etc.) Memory effect elimination In situ chamber etch Chemistry flexibility Temperature agility (T change) Repeatability Uniformity (all elements) Productivity (>6 w/h) Industrial tool (8/12 in.)

MBE (single)

CBE (single)

UHVCVD (batch)

LPCVD (batch)

RTCVD (single)

Y Y?

Y N

Y N

Y N

Y N

Y Y

N Y Ya

N? Y Ya

N? Y N

N Y N

N Y N

Y Y N

? Y N Y? Y? Y? Some Y? Y Y? N Y? Y? Y Y?

Y? Y N Y Y? N?c Some N N Yd N N N? N N

Y? Y Y? Y Yb Y Some Y? N Y Y? Y Yf N? N

Y N N Y Y? Y Some N? N N Ne Y ? Y N

Y N N? Y Y? Y Some N? N? N Ne Y ? Y Y

Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

?, questionable. a Questionable crystal quality. b Y if H2 bake possible. c Metal contamination often observed [9]. d In terms of atoms or evaporated radicals. e Difficult. f Not proved for any element.

Pros and Cons In order to complete the picture, RTCVD is compared to the other existing techniques in Table 2.3.1. In comparing these pros and cons to those of other techniques, the balance is clearly in favor of RTCVD. That certainly explains the extensive development and success of these equipments. Today, they are sold in large numbers for conventional epitaxies in manufacturing plants, as well as for advanced epitaxies and R&D at major semiconductor suppliers and institutes.

2.3.3 Epitaxy Processes Today, epitaxy technology is facing new challenges, which come from the continuous progress of silicon technology, namely smaller geometries and new epi applications in devices (epitaxial base of HBTs as an example). In addition, as technology and devices, especially CMOS transistors, approach their theoretical limits (optical lithography limit, tunnel current through the gate oxide, etc.), great efforts are made in order to improve or exchange device architecture. For these applications, epitaxial deposition of new materials like Si-based alloys is very desirable, and in most cases it has to be run in the course of device fabrication.

© 2006 by Taylor & Francis Group, LLC

2.3-50

The Silicon Heterostructure Handbook

Most of the well-established epi processes in production today are carried out by CVD with a silicon precursor diluted in hydrogen; they are run in the very front end of technology at high temperatures (1000 to 11008C). However, as soon as a substantial amount of the device is present on the wafer and strained or metastable materials are concerned, conventional epitaxy processes with high thermal budgets can no longer be used. This section presents and discusses the important issues that are specific to Si and SiGeC processes required by new epi applications and new devices in Si technology.

Surface Preparation Epitaxy essence is that the growing material forms a monocrystal that prolongs the substrate lattice. That is to say that the presence of an amorphous film on the surface cannot be tolerated; the typical example is the native oxide that naturally exists on silicon substrates. In the same way, to achieve high-quality epi, it is essential to remove any particles and contamination from the substrate surface prior deposition initiation. Contaminants would prevent surface migration of silicon atoms and form precipitates, generating lattice defects. Thus, the perfection of the epitaxial growth on silicon substrates relies critically upon the surface preparation, and all the following conditions are required: . . . .

No oxide on the surface A good crystal quality (etching or implant may have been used in previous operations) No precipitates of dopant or other impurities No surface contamination or particles

In conventional epi processes carried out at high temperature, the silicon surface preparation relies on both a wet ex situ clean and an in situ hydrogen bake. The ex situ clean generally consists of an RCA cleaning procedure [10] that eliminates particles, native oxide, organics, metal and carbon, and repassivates the reactive silicon surface with a thin (0.6 nm) layer of suboxide that is hydrophilic, stable, not highly reactive and relatively easily removed in situ. The substrate is then submitted to a hightemperature hydrogen bake (above 10008C) to remove the RCA-regrown oxide before epi deposition. It is admitted that this oxide is reduced via the two following reactions: SiO2 (solid) þ Si(solid) ! 2SiO(gas)

(2:3:1)

SiO2 (solid) þ H2 (gas) ! SiO(gas) þ H2 O(gas)

(2:3:2)

Since reaction (2.3.1) is very effective each time a silicon–oxide interface is in direct contact with vapor and the RCA oxide is somewhat porous, the author supposes that it is the most effective in the case of pre-epi bake. The hydrogen bake that is also capable to anneal eventual crystal imperfections, to dissolve or diffuse eventual high dopant concentrations or contamination, and to dissolve or evaporate most of small particles is very beneficial to the epi. Thus, this combination of ex situ and in situ cleanups, usually carried out on ‘‘full-sheet’’ silicon wafer, is very effective in producing high-quality epi. In the domain of LTE, there are two very different situations. In a first situation, epitaxy has to be run at low temperature because metastable films (strained, SiGeC, etc.) or sharp dopant profiles have to be created, but the substrate is resistant enough to high temperatures. This corresponds to processes placed at the very front end of the technology, or used for R&D structures basically deposited on full-sheet wafers. In this case, a conventional surface preparation is used and very low defect densities (a few defects per wafer) are achieved. In a second situation, which is more frequent, as sensitive structures are already present, the substrate cannot withstand high temperatures. In this case, the strategy of surface preparation has to be changed. Indeed, at moderate temperatures (below 9008C), reactions (2.3.1) and (2.3.2) responsible for the oxide reduction are not effective enough to remove the superficial oxide. It is admitted that a 6-A˚ thick chemical oxide as prepared by RCA

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-51

cleaning requires a hydrogen bake above 10008C to be fully removed and to leave a perfectly clean surface suited for high-quality epi. The best solution would be to use etch processes, carried out directly in the epitaxy chamber or in an clustered annex, that would remove effectively the chemical oxide at low temperatures. Various treatments have been proposed. Low-energy plasmas (hydrogen, argon, etc.) have been investigated. Encouraging results have been obtained but these solutions were not developed at an industrial level [11]. However, as the interest for low thermal budgets becomes stronger and stronger these treatments may come back on the scene. Vapor-phase HF cleaning has also been developed and more or less integrated in epi tools. However, this chemistry presents some difficulties: the oxide etch rate from anhydrous HFbased process is unstable and the process control difficult, and maybe more tricky is the fact that hydrocarbons on the oxide surface block the adsorption of the species that are required for etching [12]. All these new chemistries, carried out in prototype reactors, are not yet common. Consequently, most researchers today adopt a strategy based on the more conventional ‘‘HF-last’’ clean. The HF bath removes the oxide from the wafer surface and passivates the silicon surface with atomic hydrogen. The UHV/CVD growth process reported by Meyerson is based on such a HF-last clean [13]. Originally, the wafers were etched in diluted HF just prior to loading, without any water rinse. However, this procedure presents two major difficulties: (i) transport and manipulation of the wafers coming from HF acid without any rinse are very critical and (ii) removal of the residual HF is very difficult when hydrophilic patterns are present on the wafer surface. Because of these difficulties, a possible and more widely used surface preparation procedure is: RCA clean þ HF last þ water rinse þ IPA dry þ loading in the epi tool þ in situ hydrogen bake (8008C to 9008C for about 1 min). Of course, a wet clean using an ‘‘in situ’’ rinse, made by displacing an extremely diluted HF solution with DI water in the same tank, is recommended because it eliminates the transfer of hydrophobic wafers from the HF to the DI-water bath. On the other hand, clustering this precleaning with the epitaxy tool would also be preferable [14]. In the author’s opinion, this type of surface preparation allows high-quality epitaxies to be grown: typically, no oxygen or carbon is visible by SIMS at the interface (detection limit around 1  1012 atoms/ cm2), and defect densities are in the range of 0.1 to 10 defects /cm2 (light point defect > 0.16 mm), depending on precise experimental conditions. Such low values measured on silicon full-sheets are also expected on patterned wafers. On the other hand, some operations, such as dry-etch or implant, can cause the silicon at the surface and in the subsurface region to be highly defective and not compatible with a high-quality epitaxial growth. In these cases, the processes of these operations require modifications in order to respect the crystalline quality of the silicon (for example, by adding a soft-etch step to an etch recipe), or a sacrificial oxide, typically 10 to 20 nm thick, can be grown (and removed) for damage removal before epitaxy.

Low-Temperature Epi Silicon epi can be deposited using SiCl4 (sil tet), SiHCl3 (TCS), SiH2Cl2 (DCS), SiH4, Si2H6, or even Si3H8 as precursors. Growth rate (GR) depends on several parameters: reactor geometry, temperature, gas source, flow rate, deposition pressure, and concentrations. According to the gas source, for similar conditions it is admitted that the deposition kinetics increases when Cl atoms are reduced and Si atoms increased in the molecule, namely from SiCl4 to Si3H8. However, as the reactivity increases, the stability decreases, and these molecules are increasingly subject to thermal decomposition and gas-phase nucleation. Thus, hydrides have to be used at lower temperatures and smaller partial pressures, as compared to chlorides. Thus, as a function of their properties, each precursor is attractive for particular film specifications and deposition conditions; today, chlorides are used for thick epi at high temperature, usually above 10008C, and hydrides for thin epi at lower temperatures, below 9008C. In pioneer RTCVD reports, DCS [15], silane [16], and to a less extent disilane [17] were studied for low-temperature applications. As an illustration, Figure 2.3.3 reports the Arrhenius plots of Si growth rate obtained with DCS and silane. First, we note that each system exhibits two deposition regimes.

© 2006 by Taylor & Francis Group, LLC

2.3-52

The Silicon Heterostructure Handbook

Growth rate (A/min)

10,000

Ea = 2.1 eV 1000

100 Ea = 3 eV

SiH4 SiH2Cl2 10 7.5

8

8.5

9 9.5 10,000/T (K−1)

10

10.5

11

FIGURE 2.3.3 Arrhenius plot for silicon growth rate from silane and dichlorosilane in similar conditions. In the low-temperature domain, silane chemistry presents a smaller activation energy and a much higher kinetics compared to dichlorosilane.

At high temperatures, the growth rate is almost insensitive to temperature and, in most cases, is controlled by precursor gas-phase mass transport. At low temperatures, the growth rate is strongly dependent on temperature, and the variation is attributed to a thermally activated process. As this process is supposed to take place on the wafer surface, this domain is often referred to as ‘‘surface ratelimited.’’ Second, as the curves correspond to deposition carried out in a given reactor and with similar conditions of gas flow, we conclude that the silane deposition kinetics is much faster than that of DCS, and with a smaller activation energy. The advantage of silane corresponds to more than one decade in terms of growth rate, or 100 K in temperature, and to a less temperature-sensitive process. These significant changes will enable the process to be more easily controlled and the thermal budget, which could be capital in some applications, to be reduced. As a consequence, DCS is often used for selective depositions because Cl atoms help at selectivity, as discussed in ‘‘Selective Epitaxy’’ but today silane is preferred and has been adopted for most of the nonselective epitaxies. Considering the epi kinetics from silane at low temperature, the Arrhenius plot given in Figure 2.3.3 reveals an exponential dependence of GR with an activation energy of about 46 kcal /mol, which is in accordance with the majority of values reported in the literature for various experimental conditions [16, 18–20]. This value also accords very well with the activation energy for hydrogen desorption from a Sih1 0 0i surface (47 kcal /mol) [21]. Thus, growth kinetics is supposed to be correlated with equilibrium hydrogen surface coverage as depicted in Figure 2.3.4: the reactive adsorption of silane molecules produces adsorbed hydrogen atoms whose desorption is not immediate; this hydrogen surface coverage regulates further SiH4 adsorption [18]. Consequently, hydrogen desorption is the mechanism that limits the growth rate (via silane adsorption), which is ultimately independent of silane pressure. Initially developed in a domain of very low pressure, this model was then applied in a number of experiments. It was also further refined; for example, taking the adsorption of molecular hydrogen quantitatively into account [16]. Finally, these calculations agree extremely well with experimental data covering a wide range of pressures and temperatures, suggesting a high level of understanding in the growth kinetics of silicon epitaxy using silane. A simplified form of reaction pathway can be written as

© 2006 by Taylor & Francis Group, LLC

SiH4 þ 2
! Si þ 2H þ H2

(2:3:3)

H* þ H ! H2 þ 2


(2:3:4)

H2 þ 2
! 2H

(2:3:5)

2.3-53

Si–SiGe(C) Epitaxy by RTCVD

SiH4

H

H2

H

H

H

H

Si

H

H2 H

H

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

FIGURE 2.3.4 Schematic of low-temperature silane-based epitaxy. Silane molecules are supposed to adsorb on two Si sites leaving two adsorbed H atoms that passivate the surface. Growth kinetic corresponds then to the balance between silane adsorption and hydrogen desorption.

where _ denotes a site that is available for adsorption, X a specie that is adsorbed, H* corresponds to an excited state of hydrogen (following Ref. [21] hydrogen desorption is first-order relative to atomic adsorbed hydrogen) and no difference is made between the Si on surface and in bulk. On the other hand, there are some precautions to be taken when using silane. First, the presence of impurities in the gas phase, even at very small concentrations, will not be purged in a compressed gas (silane) in the same way they are in a liquid (DCS). Second, the low stability of silane molecules makes it susceptible to gas-phase nucleation of particles, which can ‘‘rain down’’ and become incorporated in the growing film. However, this limitation is not so severe since silane is chosen for thin epi and low processing temperatures. In conclusion, it should be noted that this hydrogen coverage of the silicon surface during lowtemperature growth is of considerable importance. It will control or directly influence a number of epitaxy characteristics such as: dopant incorporation, film morphology, differential poly or mono growth, and the structural quality of epitaxy, etc. The author also considers this phenomenon, which has an important surfactant-like effect, to be the main differentiation between CVD and MBE techniques (to the advantage of CVD).

Germanium Incorporation Solid Si and Ge have both the diamond crystal structure, and they form a solid solution that is almost ideal (negligible mixing enthalpy) and stable in the entire composition domain. These SixGe1
x alloys have a lattice parameter that varies almost linearly with the Ge content from 5.431 A˚ (aSi) to 5.667 A˚ (aGe) when described by the diamond cubic lattice: aSi1
x Gex ¼ aSi þ x(aGe
aSi )

(2:3:6)

At the same time, the incorporation of Ge in the Si lattice leads to a significant bandgap narrowing. This bandgap narrowing is of interest for the creation of devices based on bandgap variations or energy band offsets. Thus, SiGe alloys opened the way of bandgap engineering and strained heterostructures to the silicon technology. On a more general point of view, SiGe alloys present a variety of properties and characteristics that can be used in silicon technology. One can list: bandgap variations, band offsets, dopant diffusion reduction, chemical properties (selective etching), dopant activation improvement, strain management, optical properties, etc. SiGe epitaxies receive then an impressive attention for all their possible applications. Effect on Kinetics In RTCVD, SiGe alloys are deposited using either DCS, SiH4, Si2H6, or even Si3H8 as the Si precursor and almost exclusively GeH4 as the Ge precursor. Like in Si epitaxy, and for the same reasons, it is admitted that the deposition kinetics increases from DCS to Si3H8. And these precursors with different

© 2006 by Taylor & Francis Group, LLC

2.3-54

The Silicon Heterostructure Handbook

reactivities give rise to a variety of epi domains. Thus, SiH4 is the standard gas for NSEG and DCS for SEG. The disilane and, more recently, the trisilane are considered for very low thermal budget applications [22]. The GeH4 molecule that exists as a compressed gas, stable enough (more than 1 year in a cylinder), and reactive enough to allow significant (>10 nm /min) deposition kinetics at low temperature (below 5008C) [12] is really convenient for epi via CVD. GeH4, even expensive, is then commercially available and widely used in industry. As a consequence, other molecules as GeCl4 did not receive much attention up to now. In terms of kinetics, the main characteristic of SiGe alloy deposition is the dramatic increase of growth rate, as compared to pure silicon. This effect is illustrated in Figure 2.3.2 where the kinetics of SiGe and Si depositions from SiH4–GeH4–H2 chemistry at reduced pressure have been plotted as Arrhenius plots. In the low-temperature domain (5508C to 7508C) the SiGe deposition is thermally activated, with kinetics much higher than that of Si, about one decade around 6008C, and much lower apparent activation energy. At this point, one has to note that the SiGe kinetics reported in Figure 2.3.5 corresponds to a fixed germane /silane ratio but not to a constant solid composition. Indeed, increasing the temperature while fixing the germane and silane partial pressures causes a decrease in the Ge content of the alloy. In such a case, the kinetics limitation cannot be considered as a single and simple mechanism, and then the curve does not strictly correspond to an Arrhenius law. As it will provide some important ‘‘keys’’ for the epi engineer, it is interesting to look little more closely at this kinetics enhancement. In gas phase, germane is supposed to behave like silane, and to undergo a similar reactive adsorption on two neighboring sites (same notations as Equations (2.3.3) to (2.3.5)) GeH4 þ 2
! Ge þ 2H þ H2

(2:3:7)

In fact GeH4 molecules are much more reactive than SiH4molecules, and Equation (2.3.7) is more rapid and corresponds to a higher (5) ‘‘sticking’’ coefficient as compared to Equation (2.3.3). This results in a deposition that is much more Ge-rich than the gas mixture. As soon as Ge atoms are incorporated in solid, they act as preferential desorption sites for H atoms. This comes from the fact that Ge

H bonds are less robust than those of Si

H (smaller binding energy). In case of SiGe deposition, Equation (2.3.4) is then more rapid and less limiting for the subsequent deposition as compared to silicon case. Note also that the easy H desorption from Ge is consistent with the very small activation energy of the Ge deposition kinetics reported in Ref. [12]. Other mechanisms like sticking coefficient variations, Ge

GR (A/min)

1050 10,000

900

T (⬚C) 800

700

600

Si0.88Ge0.12

1000

100 Si

10 7.5

8.5

9.5 10.5 10,000/T (K−1)

11.5

FIGURE 2.3.5 Pseudo-Arrhenius plot for SiGe growth rate from silane–germane–hydrogen compared to Si growth rate obtained in similar conditions. In the low-temperature domain, SiGe deposition presents a smaller apparent energy of activation and a much higher kinetics compared to silicon.

© 2006 by Taylor & Francis Group, LLC

2.3-55

300 nm

Si–SiGe(C) Epitaxy by RTCVD

105 3 µm

FIGURE 2.3.6 undulations.

Stranski–Krastanov growth mode in SiGe–Si epitaxy observed by AFM. Note the h1 0 0i-aligned

segregation, H-atom site exchanges (from Si to Ge), etc. may also take place but are not essential to get a good picture of SiGe deposition. Strain Effects Because of the lattice parameter variation given in Equation (2.3.6), SiGe epitaxies that are grown pseudomorphically on silicon substrates exhibit a large biaxial compressive stress (negative strain). The mechanical energy of these films increases (as the product thickness *x 2Ge ), and if critical values of xGe and thickness are exceeded, the film quality can be degraded by Stranski–Krastanov (SK) growth or misfit dislocations. Figure 2.3.6 illustrates the surface morphology specific to the SK growth mode. This mode exhibits quasiperiodic undulations that grow exponentially with time–film thickness, and very rapidly with 6 8 –xGe function of the stress–xGe; very simple models demonstrate that their amplitude has to grow as xGe model simplifications. These surface undulations are generated without any extended crystalline defects like dislocations or stacking faults, and are aligned along the two h1 0 0i directions on a (0 0 1) Si surface. It is a kind of elastic relaxation: the top of the undulations has released a part of its stress and the mechanical energy of the system has been reduced. The plastic relaxation corresponds to the nucleation and propagation of misfit dislocations. As illustrated in the Figure 2.3.7 (top view), misfit dislocations are easily identified as they usually glide in {1 1 1} crystalline planes. They usually lie near the SiGe–Si interface and allow the above-lying SiGe film to be relaxed. However, since the dislocation core corresponds to some excess energy, dislocations can extend only when the relaxation gain is larger than the dislocation loss. This energy balance corresponds to the well-known critical thickness for stability against dislocation formation due to the lattice mismatch. For a single Si0.80Ge0.20 layer (without any silicon capping layer), the equilibrium critical thickness is less than 20 nm. Films with thickness smaller than this value are stable; films with larger thickness are metastable, relaxation can occur if they are exposed to high temperatures, especially if efficient dislocation sources are present in the film. The relative severity of the two relaxation mechanisms depends on the nature of the film (xGe) and experimental conditions of deposition (temperature and chemistry). However, for both mechanisms, the lower the temperature, the larger the xGe–thickness process window. At this point, it is important to note that the dramatic kinetics increase induced by the Ge incorporation allows keeping a certain process window against these mechanisms: the growth of Ge-rich films requires lower temperatures, and lower temperatures can be used owing to the Ge-catalyzed kinetics.

© 2006 by Taylor & Francis Group, LLC

2.3-56

The Silicon Heterostructure Handbook

FIGURE 2.3.7 Top view of misfit dislocations observed by optical microscopy after chemical decoration.

Carbon Incorporation Background Solid carbon presents different crystalline structures: diamond, graphite, etc. And even if the diamond structure is similar to that of silicon, the lattice parameter presents a large size offset, aSi /adiamond ¼ 1.52. On the other hand, according to the Si

C phase diagram, there is a compound that is very stable, stochiometric SiC, and the carbon solubility in solid silicon is very low, a few 1017 atoms /cm3 at melting temperature. Consequently, the incorporation of carbon in Si or SiGe crystal is more complex than that of germanium in Si, and its incorporation in substitutional sites is by nature a nonequilibrium process. However, it was demonstrated that, by using low-temperature (<6508C) depositions, it is possible to incorporate significant amounts (percent range) of substitutional carbon in silicon lattice [23] to form metastable Si1
yCy and Si1
x
yGexCy epitaxies. The incorporation of carbon in silicon and SiGe layers was first investigated to extend the capabilities of the SiGe system. Indeed, in the previous section, pseudomorphic SiGe layers on Si were found to have fortuitous properties that made them very successful. They however suffer from significant limitations. First, the concept of critical thickness is not really compatible with applications that would require thick nondislocated SiGe layers on silicon, for light emission or detection as examples. Second, almost the entire bandgap offset was reported in the valence band, the SiGe–Si structures do not exhibit any significant conduction band offset and electron modulation is impossible in simple structures. In the case of substitutional carbon incorporation, the lattice parameter of SiGeC material can be estimated using the following equation: aSi1
x
y Gex Cy ¼ aSi þ x(aGe
aSi ) þ y(aC
aSi )

(2:3:8)

Equation (2.3.8) is a first estimation, and nonlinear variations may have to be taken into account. Nevertheless, it shows that the incorporation of C atoms, smaller than Si, can serve to reduce or even eliminate the strain in SiGe layers. Calculations as well as experiments show that carbon atom roughly compensates for about ten germanium atoms. It means that if x /y ratio is fixed at this value the ternary layer is perfectly matched to the silicon, and the critical thickness is no more a limitation. Carbon incorporation is also of particular interest as it leads to significant conduction-band offset and to strain effects that are reverse to the Ge-induced ones.

© 2006 by Taylor & Francis Group, LLC

2.3-57

Si–SiGe(C) Epitaxy by RTCVD

On the other hand, the presence of substitutional carbon atoms at relatively low concentrations, as low as 0.1%, has been found to dramatically reduce both diffusion and transient-enhanced diffusion of impurities like boron in Si and SiGe [24]. This fortuitous effect is widely used to fabricate highly borondoped bipolar bases that are very thin. Note that this effect could or should be used in CMOS transistor for channel doping or shallow junction control as well. Incorporation Kinetics In RTCVD, the most common chemistry used for SiGeC epitaxy is SiH4–GeH4–SiCH6 diluted in H2 at reduced pressure. Other carbon precursors like C2H4 were also found to be effective, to a less extent, in producing substitutional carbon incorporation [25], but single alkanes like CH4 that seem to not decompose the right way are not well suited for this application. Other silicon sources like disilane or trisilane seem attractive, but they are not currently used because of some difficulties such as cost, molecule stability, liquid source control, etc., as compared to silane. Figure 2.3.8 presents an example of carbon incorporation in Si and SiGe layers [26]. The total carbon concentration [Ctot] measured by SIMS is given as a function of the methylsilane (MS)/silane flow ratio for a variety of process conditions like different silane flows, Ge contents, and deposition temperatures. Note that the gas flow ratio corresponds to the flows through the mass flow controllers and do not correspond exactly to the partial pressures above the wafer surface. One observes that all the experimental points roughly follow a proportional variation with the gas flow ratio. This proportionality in a large experimental domain suggests that MS would undergo a surface-sorption similar to that of silane that requires two adjacent available sites (see Equation (2.3.3)). The fact that the carbon concentration in solid is smaller than the gas ratio also suggests that MS would have a sticking coefficient slightly smaller than silane. Note that it has also been reported that the carbon incorporation increases when the total pressure is decreased and when the temperature is increased [12]. Such trends that are opposite to the germane behavior are also expected from a molecule with a smaller sticking coefficient (germane coefficient is higher). On the other hand, contrarily to the effect of germane, the presence of MS partial pressure does not have significant effect on the deposition kinetics; accurate measurements allowed us to detect only a small growth rate reduction and a negligible xGe variations in the experimental conditions explored [26]. Nature of Incorporation Contrarily to Ge, and for the basic reasons given above, carbon atoms are not necessarily incorporated in substitutional sites. They can easily form interstitial complexes or even react with silicon to form stochiometric SiC precipitates.

[C total]/[Si] (%)

3

2

1 620⬚C 680⬚C 0 0

0.02

0.04

0.06

MS/silane (%)

FIGURE 2.3.8 Total carbon incorporation as a function of the methylsilane–silane flow ratio for a variety of process conditions: different silane flows, germanium contents, and deposition temperatures.

© 2006 by Taylor & Francis Group, LLC

2.3-58

The Silicon Heterostructure Handbook

Intensity (cps)

For a long time, carbon contamination on a silicon wafer surface has been known to cause a large defectivity in epi. Indeed, at high temperature, during the hydrogen bake for example, carbon atoms form nanoprecipitates of SiC that induce dislocations or stacking faults. For the same reason, highquality SiGeC epitaxies require relatively low deposition temperatures (well below 9008C): too high temperatures would allow the carbon precursor to react with the silicon surface to form SiC nuclei. In addition, even if such SiC precipitates are not formed, there is still an important challenge, that is to incorporate the carbon in substitutional sites; i.e., to avoid or minimize the incorporation of carbon in interstitial sites, as well as the formation of interstitial complexes or any other microdefects. Substitutional carbon concentration can be easily quantified from its influence on the lattice parameter. Figure 2.3.9 shows the typical X-ray diffraction (XRD) rocking curves from pseudomorphic SiGeC grown on Si (1 0 0). The present diagrams correspond to layers grown with increasing MS/silane gas ratios, all other conditions being constant. The angular shift between the Si substrate peak and the SiGeC layer peak is a direct measure of the lattice mismatch of the epitaxy. And, as the presence of MS in the gas phase does not induce significant changes in Si and Ge deposition kinetics, the shift is directly related to the content of substitutional carbon. In the present case, we observe that the compressive stress induced by a Ge content of 14% is reduced by carbon incorporation in substitutional sites, or even eliminated when the C content is around 1.5%. In the same way, similar incorporation of carbon in pure silicon would have induced important tensile stresses. The crystalline perfection of SiGeC epitaxies is an important concern in a number of applications. The experimental domain where high-quality epitaxies can be achieved is then of great interest, it has to be determined and optimized. As a first approach, XRD is a convenient, and routinely used, technique to determine the crystal quality of pseudomorphic layers on silicon. This way, the maximal carbon incorporation in terms of crystal quality has been explored as a function of temperature and germanium content, and the results obtained at 6208C and 6808C are given as examples in Figure 2.3.10a and b, respectively. In the figure, high-quality epitaxies (closed symbols) and poor-quality epitaxies (open symbols) are represented in the plane (xc, xGe); the quality criterion being the discrepancy between measured XRD diagram and theoretical simulations (a significant broadening of the main SiGeC peak or the disappearance of the higher order oscillations). At each temperature, there are two domains, a ‘‘good quality’’ one at the bottom left and a ‘‘poor quality’’ one at the top right. It is observed that, for given experimental conditions, there is a maximal carbon concentration beyond which the epitaxial quality is not maintained, and this maximal limit is found to be reduced as the xGe is increased. The comparison of the two figures also indicates that the good-quality domain is enlarged by a temperature reduction. In other words, the lower the temperature, the larger the process window. Such a trend is also valid in other techniques like MBE and in various experimental conditions. 1⫻107

0% Ctotal

1⫻106

0.1% Ctotal

1⫻105

0.15% Ctotal 0.3% Ctotal

1⫻104

0.6% Ctotal 1⫻103

0.9% Ctotal

1⫻102

1.2% Ctotal

1⫻101

1.5% Ctotal

1 0

500

1000

1500

2000

2500

3000

Diffraction angle offset (arcsec)

FIGURE 2.3.9 X-ray rocking curves from pseudomorphic SiGeC grown on Si (1 0 0). Diagrams correspond to layers with a fixed Ge content (about 14%) and C contents increasing from 0% to 1.5%. They show the reduction of the lattice parameter induced by substitutional carbon incorporation.

© 2006 by Taylor & Francis Group, LLC

2.3-59

Si–SiGe(C) Epitaxy by RTCVD

Total carbon (%)

3 Bad quality

620⬚C Good quality

2

1

0 0

10

20

30

XGe (%)

(a)

Total carbon (%)

3 Bad quality 2 Good quality 1 680⬚C 0 0

10

(b)

20 XGe (%)

30

FIGURE 2.3.10 Quality of SiGeC epitaxies deposited by RTCVD as a function of germanium and carbon contents: (a) 6208C and (b) 6808C. Low temperatures lead to larger process windows in term of carbon incorporation.

1.2

680⬚C, XGe = 6% 680⬚C, XGe = 9% 680⬚C, XGe = 13% 620⬚C, XGe = 13% 620⬚C, XGe = 31%

Csub/Ctotal

1 0.8 0.6 0.4 0.2 0 0.000

0.010

0.020

0.030

0.040

Ctotal (%)

FIGURE 2.3.11 Proportion of substitutional carbon as a function of the carbon content in SiGeC epi grown at 6808C and 6208C.

Another important challenge of SiGeC epitaxy is how to minimize the number of interstitial atoms and to incorporate all carbon atoms in substitutional sites. The presence of interstitial atoms is indeed not desirable as they are admitted to induce detrimental effects in a number of material characteristics like minority carrier lifetime, mobility, and maybe impurity diffusion, etc. It is then crucial to know the variation of the Csubtitutional /Ctotal ratio as a function of the main growth parameters such as growth temperature, partial pressures, etc. The most important trends are illustrated in Figure 2.3.11 that gives the evolution of the ratio in RTCVD epitaxies as a function of the total carbon incorporation, and for different temperatures and different germanium contents. The substitutional carbon was deduced from XRD measurement and total concentration from SIMS. It is observed that whatever the temperature, the

© 2006 by Taylor & Francis Group, LLC

2.3-60

The Silicon Heterostructure Handbook

ratio of substitutional carbon decreases with increasing total carbon incorporation, and that the substitutional carbon increases with decreasing deposition temperature and with decreasing Ge content. All these trends are well admitted and have been qualitatively reported for different techniques. They have even been modeled in the case of MBE with simple first-order kinetics of thermally activated interstitial incorporation [27]. However, if we compare the present results with MBE results, we note an important difference. In MBE, substitutional incorporation requires deposition temperatures below 5508C, 4508C preferred, whereas in RTCVD, a significant substitutional ratio is obtained with temperatures as high as 6808C to 7008C. In the opinion of the author, this dramatic change has to be attributed to the presence of an important hydrogen surface coverage that blocks the movement of carbon atoms or eventually improves the stability of the substitutional position. One has also to note that such a crucial role of surface coverage, sometimes referred as a surfactant-like effect, is consistent with all the trends reported above.

Selective Epitaxy Selective epitaxial growth (SEG) is very desirable because, as a fully self-aligned process, it leads to fully self-aligned device architectures that are simpler, or even to novel device structures (see Section 2.3.4). By essence, SEG has to be run on patterned wafers, and the epi characteristics depend on the process and on the precise nature of the patterned wafers as well. Namely, we can list: epitaxy perfection, selectivity limit, thickness and doping in the different windows, and exact morphology of deposition (mainly faceting at the edge of deposition). As a consequence, in addition to complex process developments, SEG process may also present important integration problems, and some of them are discussed in Section 2.3.3. The concept of SEG is based on the fact that silicon has to undergo a nucleation step before deposition over a dielectric and not over silicon. This nucleation step corresponds to a certain amount of energy, and the barrier is large enough to produce selective deposition if the process is well chosen. Various SEG processes have been published via RTCVD, but the most common ones are based on the DCS–HCl–H2 chemistry. Apart from the DCS choice, the addition of a certain flow of HCl is generally required to totally inhibit any deposition on the dielectric, especially when using Si3N4 and utilizing an industrial reactor working at pressures exceeding a few Torr. As such, DCS-based epitaxy and DCS–HCl-based SEG are presented below. DCS chemistry is widely used in conventional epitaxy and has been studied for SiGe deposition at low temperature. As such, experimental data on kinetics are available in literature, however the modeling and understanding of this process is not as clear as for silane. Following the Arrhenius plot of the DCS–H2 epitaxy kinetics given in Figure 2.3.3, for temperature of interest here (<8508C) deposition is kinetically limited. Although they are supposedly predominant, surface reactions are still uncertain. It is supposed that DCS molecules adsorb directly on the silicon surface and undergo a reactive dissociation into Si, H, and Cl, and that these species can desorb, depending on the temperature, as H2, HCl, or SiCl2. A simplified form of the reaction pathway proposed first by Coon et al. [27] may be written as follows: SiH2 Cl2 þ 4
! Si þ 2H þ 2Cl

(2:3:9)

H* þ H ! H2 þ 2


(2:3:4)

H þ Cl ! HCl þ 2


(2:3:10)

2Cl ! Cl2 þ 2


(2:3:11)

Si þ 2Cl ! SiCl2 þ 2


(2:3:12)

(same notations as Equation (2.3.3) to Equation (2.3.5)). However, as epi is often performed in hydrogen ambient, and as hydrogen is known to increase the GR of silicon compared to Ar, N2, or He, we prefer to include its influence with the following reaction suggested in [28]:

© 2006 by Taylor & Francis Group, LLC

2.3-61

Si–SiGe(C) Epitaxy by RTCVD

2Cl þ H2 ! 2HCl þ 2


(2:3:13)

The apparent activation energy of DCS–H2 kinetics given in Figure 2.3.3 is about 70 kcal /mol; a value very similar to the activation energies of the desorption reactions (2.3.10) and (2.3.13) that are supposed to be the limiting steps. Kinetics limitations in DCS–H2 system are reported in Figure 4 of Ref. [29]. Silicon growth rate has been plotted as a function of DCS flow (or partial pressure) for different temperatures, all other parameters being constant. For low DCS flows, GR is proportional to the flow, but above a given flow, GR exhibits a very clear saturation indicating that reactions (2.3.10) and (2.3.13) would be very effective. At 7508C, for example, GR is roughly constant (about 13 nm /min) for DCS pressures exceeding 0.05 Torr. Thus, the surface coverage would regulate DCS adsorption and growth rate. And based on Hierlemann calculations [27], chlorine coverage would dominate in most of the experimental conditions, bringing about an important variation as compared to silane chemistry. Silicon SEG based on DCS–HCl–H2 chemistry has given rise to a large amount of work, but SEG is a complex process with a number of parameters (any comparison is very difficult as experimental conditions are different); no (or almost no) conclusive attempts have been made to relate the SEG process to the underlying surface reaction physics. Reactions (2.3.9) to (2.3.13) are still valid but a significant HCl adsorption, with reactions reverse to reactions (2.3.10) and (2.3.13), has to be taken into account. And consequently, the growth rate is depressed because of an increased Cl surface coverage, and reaction (2.3.12) is much more effective in removing Si adatoms from the dielectric surface, compared to the DCS–H2 chemistry. A perfect selectivity against dielectrics like SiO2 or Si3N4 can be then obtained in the DCS–HCl–H2 system by HCl flow adjustment. This is illustrated in Figure 2.3.12, where the nucleus density on full-sheet Si3N4 CVD films on 200 mm wafers has been plotted as a function of the HCl flow. Deposition process was carried out in a commercial epitaxy reactor, and nuclei were measured with an optical inspection tool that enables the full wafer to be scanned. We observe a relatively abrupt selectivity threshold (a 10% variation in HCl flow changes the level of defects by 2 to 3 decades) and a very high degree of selectivity (not published to the author’s knowledge) as nucleus densities or defectivity lower than 0.1/cm2 are measured. To conclude the silicon SEG part, and as discussed in Ref. [29], we can draw the following general rule: the HCl flow requested to obtain full selectivity has to be increased with any of the following parameters: DCS flow (but the ratio DCS–HCl can be decreased), temperature, pressure, doping level (boron), and Si coverage. Germanium and carbon can be incorporated in selective epi via the addition of GeH4 and MS in the previous chemistry.

Nucleus density (cm−2)

100 H2 /DCS/HCl chemistry T = 850⬚C 10

1

0.1 0

100

200

300

HCl flow (sccm)

FIGURE 2.3.12 Selectivity threshold of silicon deposition on CVD Si3N4. The nucleus density was measured as light point defects using a Surfscan that allows the entire 200 mm wafer to be inspected. In the present conditions, a perfect selectivity is obtained when using 140 sccm of HCl and more. Note that the points located on the bottom and top axes correspond to densities below 0.1 and above 100 LPD/cm2.

© 2006 by Taylor & Francis Group, LLC

2.3-62

The Silicon Heterostructure Handbook

In terms of kinetics, the main characteristic of SiGe alloy deposition is the dramatic increase of growth rate, as compared to pure silicon. As for hydrogen, it is supposed that the much lower Cl

Ge binding energy, as compared to Cl

Si, facilitates the Cl desorption and allows much more rapid kinetics. Note that a part of this kinetic enhancement may also come from a chemical reduction of DCS radicals by atomic hydrogen that is produced by GeH4 decomposition. However, up to now, these mechanisms were not properly modeled. Indeed, the kinetics, already not so simple for pure Si, becomes much more complex, especially in the low-temperature domain where a number of surface reactions should be taken into account. On the other hand, as xGe (new parameter) has a high influence on kinetics, the deposition domain becomes very extended and the number of experiments to explore it very huge. As an example of SiGe SEG kinetic, Figure 2.3.13 gives the variations of GR and germanium content as functions of the DCS partial pressure, all other conditions being constant. We observe that when the GeH4 /DCS gas ratio is reduced by a factor of 5 via a DCS increase, the germanium content roughly decreases from 25% to 20% and the GR decreases from 17.5 to 11 nm /sec. In other words, the germanium content follows a really nonlinear variation, and the GR variation is opposite to the main active gas (DCS) partial pressure change: dependencies that are not straightforward for xGe or even counterintuitive for the GR. In terms of selectivity, the germanium incorporation plays a very positive role. It is observed that SiGe deposition is much more selective as compared to pure silicon. Whatever the dielectric, SiO2 or Si3N4, the Ge-rich epi, the more selective. Different possible explanations were proposed in literature, but none of them is really convincing. In the opinion of the author, this increased selectivity would come from the interface–surface energies larger for SiGe and then less favorable to nucleation, as compared to Si (this is still under experimentation). Indeed, a larger SiO2–SiGe interfacial energy (and to a less extent a larger SiGe surface energy) would induce a much higher nucleation barrier and then would lead to an easier intrinsic selectivity. On the other hand, substitutional carbon incorporation in chloride chemistry is more delicate as this incorporation requires low temperatures and chloride kinetics higher deposition temperatures, as compared to silane. However, some interesting compromises do exist as selective SiGeC epi were already reported in the literature [30, 31]. In both cases, the depositions allowed to fabricate high-performance HBTs, and this point will be illustrated in Section 2.3.5.

50

200

HCl = 0 sccm

HCl = 0 sccm HCl = 40 sccm

120 80

HCl = 80 sccm

30 20 10

40 0

HCl = 40 sccm

40

HCl = 80 sccm XGe (%)

Growth rate (A/min)

160

0 0

0.01

0.02

0.03

DCS pressure (Torr)

0.04

0.05

0

0.01

0.02

0.03

0.04

0.05

DCS pressure (Torr)

FIGURE 2.3.13 SiGe SEG kinetics as a function of the DCS partial pressure (flow). Note that the nonlinear variation of xGe and the counterintuitive variation of GR that decreases with increasing active gas (DCS) flows.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-63

2.3.4 Epitaxy Integration Compared to standard high-temperature blanket epi, new epi processes are facing new challenges. Some difficulties come from the properties of the epitaxial layer that has to be deposited: metastable-strained layers (SiGe), nonstable materials (substitutional carbon), etc. and have been discussed previously. Others difficulties come from the device application requirements, and from integration in modern technologies. On one hand, new devices like the base of HBTs require very complex stacks that correspond up to 8 to 18 parameters that have to be controlled. In addition, as the base is an active part of the device that is very critical, it has to be well controlled. On the other hand, as a part of the devices is already present, the global thermal budget of epi is strictly limited and the epi has to be run on patterned wafers. Today, new (established or potential) applications are very numerous, and all of them are not precisely specified. Thus, it is difficult to detail all possible issues in an exhaustive way. However, the major ones can be tentatively listed as: . . . . . . . . . . . . . . . . .

Very limited thermal budget (H2 bake) Low deposition temperature (complex kinetics and structural quality problem) Abrupt dopant profiles (at the nanometer scale) Strained epitaxies: SiGe, SiGeC Metastable materials: SiGeC Different doping types and levels Cleaning of structured substrates Deposition on structured substrates (very different as compared to prime Si wafers) Epitaxy in presence of various materials: TEOS, Si3N4, SiO2, poly or amorphous silicon, etc. Epitaxy in very complex structures Epitaxy after etching and implant steps Selective epitaxy: Si, SiGe, SiGeC, etc. Control of facets or poly–epitaxy interfaces Local or global loading effects (LE) Complex film stacks Differential epi or poly growth rate Control of poly roughness in nonselective epitaxy

In the following, we discuss some general difficulties that are present in LTE by RTCVD for new applications, namely, thermal budget limitation, LE, deposition morphology, and pattern-induced defectivity.

Thermal Budget Limitation As a very general approach, one could consider that the thermal budget has to be reduced at each technology node according to the design size reduction and to the gradients required. Based on the boron diffusion that is a limitative mechanism in a number of applications, the thermal budget reduction from one technology node to the next one can be estimated to 158C to 208C (Dboron /2 or diffusion length  0.7). This rule holds for established epi applications that would follow a constant integration scheme. For a new application, the thermal limitation can be even more demanding and severe. As there is no reference, any request is possible; the general trend being the more advanced the technology and the later (in the process flow) the epi integration, the lower the allowed thermal budget. This way, in most recent applications we had to move from the ‘‘RCA þ high-temperature H2 bake’’ clean strategy to the ‘‘HF-last þ moderate-temperature H2 bake’’. Taking the bipolar transistor that is demanding in terms of epi quality as an example, collectors (buried layers) are grown with the first strategy for decades, whereas the more recent epitaxial bases of HBTs are generally deposited using the second one. Note also that in some

© 2006 by Taylor & Francis Group, LLC

2.3-64

The Silicon Heterostructure Handbook

cases, the process flow, and then the device architecture, has to be designed taking into account for epi limitations. In the case of HBTs in BiCMOS, the epi base is usually run before CMOS S/D implantation. This way a significant thermal budget can be used to optimize the surface cleaning and epitaxial deposition perfection. In some other applications like the deposition of elevated S/D in the most advanced CMOS or SOICMOS technologies (65 to 45 nm node and below), as a function of the process flow we may have to go to the ‘‘HF-last þ low-temperature H2 bake’’ strategy. For very demanding applications, even the deposition temperature has to be reduced and SiGe depositions may be preferred to silicon epi because of their much higher kinetics. As an example, hydride chemistry at 6008C with fixed conditions gives typical GR of 1, 10, and 50 nm /min for germanium contents of 0%, 13%, and 26%, respectively. Thus, SiGe depositions can be considered for industrial applications, with significant throughputs, at temperatures much lower than 6008C. In such a case of thermal budget reduction, we have to keep in mind that, as stated previously, the surface cleaning may be not efficient enough, and any surface imperfection can induce important epi defectivity. Indeed, any particle or precipitate will not be eliminated and can be the source of crystalline defects, especially in strained epi. Figure 2.3.14 gives an example of such a high defectivity observed in Si–SiGe epi deposited with a low thermal budget. The image of the epitaxial zone (800  800 mm2) has been obtained by room temperature photoluminescence [32]: dark areas outside the box are due to polycrystal deposition, and dislocations randomly appear in the box as dark lines and points. In this case, a poor surface preparation associated with a low-temperature H2 bake has left a high density of defects such as particles or precipitates that have induced crystalline defects and misfit dislocations. On the other hand, the deposition temperature reduction may also affect the quality of the epitaxy. Indeed, as soon as the partial pressure of active gases is increased and the temperature decreased, minority carrier transport and photoluminescence properties are usually affected, supposedly because of punctual defects. At the limit, if the deposition conditions are pushed further, we may even cross the amorphous or crystalline deposition transition. As a conclusion, the epi process that determines the film quality has to be chosen in proper accordance with the application requirements. And, as an example, epitaxial bases of HBT and elevated S/D of CMOS with different requirements probably should have to be deposited with different conditions.

FIGURE 2.3.14 Room temperature photoluminescence image of a Si–SiGe epitaxial structure. Dark areas outside the box are due to polycrystal deposition, and dislocations appear in box as dark lines or points. The important defect density is due to an improper surface preparation associated with a low-temperature H2 bake.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-65

Loading Effects In RTCVD, the growth rate of Si (or SiGeC) in the active areas of patterned wafer usually depends on the pattern. Differences that are observed by changing the absolute size of exposed silicon areas on a given substrate are referred to as ‘‘local loading.’’ Differences from one wafer to the other, due to the total exposed silicon surface or to any other wafer change, is referred to as ‘‘global loading.’’ It means that a fixed process recipe (chemistry, temperature target, pressure, etc.) does give different depositions on different substrates or in different locations. These LE are an important difficulty in industrial applications where epi depositions have to be precisely (specifications smaller than a few percentages) controlled in any devices and on any wafer. On the other hand, as a function of the root cause of these differences, temperature variations or chemical changes (most probably in the gas-phase composition), one usually classifies the effects as ‘‘thermal’’ LE or ‘‘chemical’’ LE. At the origin, LE referred almost exclusively to thickness variations found in Si SEG as these ones were strong and easily detected. Such a view is, however, too restrictive and has to be enlarged: the LE concept is valid, and has to be considered, for the incorporation of any element that is present in deposit. This way, LE may affect thickness but also other parameters like germanium content, carbon incorporation, and dopant level. In addition, as it is not yet reported in literature, it is important to note here that LE may also induce growth rates and dopant incorporations that are not constant within the film thickness. Thermal Loading In existing RTCVD epi tool, the wafer rests on a SiC-coated graphite susceptor and both pieces are lampheated inside a cold-wall chamber possibly under low hydrogen pressure. As temperature measurements on wafers with patterns and complex film stacks are very delicate, only the susceptor temperature is used to control the process. However, in such equipment, which do not follow the blackbody emission, the actual temperature of an object is a function of its absorptance or emissivity. As a consequence, the wafer temperature T does not match exactly the susceptor temperature Tsusc, and a temperature offset DT can be written as [29]: 4 3
K2 (Tsusc
298)]=(8«sTsusc þ K1 þ K2 ) DT ¼ [«lamp P
«sTsusc

(2:3:14)

where DT ¼ T
Tsusc, «lamp is the emissivity of wafer corresponding to the lamp wavelengths, P, the radiative power density from lamps, «, the silicon emissivity corresponding to its own emission, K1, the constant of heat conduction between the wafer and the susceptor backside, K2, the conduction coupling between the wafer and the chamber, and the other letters have their usual meaning. Note that susceptor 3 , and emissivity was taken to unity. In practical cases, we have relations : K1 >> K2 and K1 >> 8«sTsusc Equation (2.3.14) can then be simplified as 4
K2 (Tsusc
298)]=K1 DT ¼ [«lamp P
«sTsusc

ð2:3:15Þ

During epi process, Tsusc is well controlled and can be considered as constant and repeatable. However, as DT is not necessarily equal to zero, Equation (2.3.14) and Equation (2.3.15) establish that, in a general way, the precise temperature of process T varies with wafer emissivity, top and bottom lamp power repartition (via P), susceptor design and gas conductivity (via K1). Note that, in equipments, which use thermocouple placed at the susceptor bottom for temperature control, the situation is even worse as an additional temperature offset, between susceptor and thermocouple, is introduced. As a consequence, a fixed process (chemistry, temperature target, pressure, etc.) does not give the same deposition on different substrates. Figure 2.3.15 gives the SiGe growth kinetics as a function of the germane gas flow, measured on blanket Si wafers and on typical product wafers. The comparison shows clearly that growth rate is lower when using structured substrates compared to full-sheet wafers. Basically, this change can be attributed to two different causes: a global ‘‘thermal’’ LE or a global ‘‘chemical’’ LE. The actual causes of the GR

© 2006 by Taylor & Francis Group, LLC

2.3-66

The Silicon Heterostructure Handbook

1500

25

Fullsheet Patterned

1000 15 Fullsheet Patterned

XGe

GR (A/min)

20

10 500 5 0

0

0 0.02

0.04 0.06 GeH4/SiH4

0.08

0

0.02

0.04 0.06 GeH4/SiH4

0.08

FIGURE 2.3.15 SiGe growth kinetics as a function of the germane–silane flow ratio for silicon full-sheet and device wafers. In the present conditions, growth rate variations are mainly due to thermal loading effects.

variations presented in Figure 2.3.15 have been studied in detail [33]. In these specific conditions, it was clearly established that: .

.

Silicon deposition did not present any significant chemical LE and the observed GR variation is due to the thermal effect (about 68C). SiGe growth did present both a thermal LE (to the same extent in Celsius than the silicon one), and a chemical LE that is smaller.

The present results are specific to the conditions used for deposition. Nevertheless, they demonstrate that, in a general way, the deposition on device wafers is different from an eventual calibration using full-sheet wafers. Because of the presence of polycrystalline silicon on field oxide, the emissivity of product wafers is significantly smaller than that of blanket wafers, and the first term of Equation (2.3.14) and Equation (2.3.15) is decreased more significantly than the second one. Thus, the wafer temperature is decreased as compared to prime wafers, in agreement with the result of Figure 2.3.15. Note that the thermal LE are supposed to vary during deposition as wafer emissivity varies with the poly thickness. Finally, despite severe simplifications made, Equation (2.3.14) and Equation (2.3.15) explain perfectly how the actual process temperature varies with the wafer optical properties, giving rise to the thermal LE. On the other hand, thermal LE reported in Figure 2.3.15 correspond to global effects. However, local thermal LE play a certain role each time that important surface emissivity nonuniformities are present on the wafer at large lateral scales (greater than a few mm); any lateral thermal gradient at smaller scales is effectively smoothed by the high thermal conductivity of the silicon substrate. It is also interesting to note that thermal LE, illustrated here for NSEG, are operative for any process, and that LE reported for SEG as chemical LE usually are in fact a mix between thermal and chemical effects. Chemical Loading Chemical LE, often referred as ‘‘loading effects,’’ are reported for a long time in silicon SEG. They are, however, almost not modeled even in the case of pure silicon deposition, as the kinetics with DCS–HCl– H2 chemistry is not perfectly understood. Because of the additional parameters, namely the silicon surface coverage and the size of the windows, complex variations may be found as a function of silicon coverage or HCl partial pressure (see as an example Figure 10 of Ref. [29]). Indeed, in different experimental conditions, LE may present opposite variations, a behavior attributed to the fact that the kinetics is dominated by DCS or HCl molecules.

© 2006 by Taylor & Francis Group, LLC

2.3-67

Si–SiGe(C) Epitaxy by RTCVD

T (⬚C) 700 650

750

600

650

600

30

1000

25 Ge content (%)

Growth rate (A/min)

T (⬚C) 700

750

100

10

1 9.5

Si area = 1% Si area = 23% Si area = 100% 10.0

10.5 11.0 10,000/T (K−1)

20 15 10 5

11.5

0 9.5

Si area = 1% Si area = 23% Si area = 100% 10.0

10.5 10,000/T

11.0

11.5

(K−1)

FIGURE 2.3.16 Global loading effect in DCS–GeH4–HCl–H2-based SiGe SEG. Growth rates are plotted as a function of reciprocal temperature for wafers with silicon coverages of 1%, 23%, and 100%.

In the case of SiGe or SiGeC deposition, the situation is even more complex as the deposition domain is enlarged very much by the addition of parameters (germane or MS partial pressures). Figure 2.3.16 gives the growth rate of SiGe SEG as a function of reciprocal temperature on wafers with different silicon coverages. The DCS–GeH4–HCl–H2 chemistry was used and the deposition conditions were chosen close to the selectivity threshold. In such a case, the kinetics and LE are dominated by DCS and germane (and not HCl), and we observe that whatever the deposition temperature, the smaller the silicon coverage, the higher the growth rate. In the same way, we also observed that the smaller the silicon coverage, the higher the Ge content. In these experiments, special care has been taken in order to eliminate any thermal contribution of the different patterned or blanket wafers resulting from the optical properties of wafers and the results only report the actual chemical LE [34]. The present interpretation is that the germane depletion (that increases with the silicon coverage) with the subsequent Ge content reduction is the main cause for the significant GR decrease (a factor of 3 to 4). Note at this point that a more important global LE would be expected with smaller Ge contents as the relative germane depletion would increase and as the kinetics would be more sensitive to xGe. Local LE are also observed in these deposition conditions. Figure 2.3.17 gives the growth rate and Ge content of SiGe SEG as a function of the silicon window area [34]. We observe that the smaller the window, the higher the growth rate and the Ge content. In the same way as for global LE, a local germane depletion would induce locally both the GR and xGe decreases. We also note that for smaller and smaller silicon windows, the GR and xGe seem to saturate. This trend has been confirmed by SEM cross sections where no significant offset was found between submicron and larger windows. It means that optical measurements carried out in windows as large as several tens of microns are representative of epi in submicron devices. At this point, we have to note that the results are reported as a function of the window area. However, this parameter is fundamental only for isolated windows, and in a more general design all the surrounding patterns will play a role and have to be taken into account. In this section, chemical LE were presented in the case of SiGe SEG. For the sake of simplicity, we have presented simple variations that are obtained in an experimental domain properly chosen. However, we have to keep in mind that the volume of the experimental domain, with a number of parameters, is huge, and that more complex variations of global and local LE are usually found in larger or not wellchosen domains. On the other hand, even if often neglected, NSEG also present chemical LE that can be important. As an example, boron doping presents both local and global LE in Si or SiGe epi as a consequence of an important ‘‘differential’’ incorporation (a ratio of 2) between polycrystalline and epitaxial deposition.

© 2006 by Taylor & Francis Group, LLC

2.3-68

The Silicon Heterostructure Handbook

140

36

120

32

80 60

30 GR-650⬚C

40

%Ge-650⬚C

Ge content (%)

Growth rate (A/min)

34 100

28

20 0 10

100

1000

10,000

100,000

26 1,000,000

Si window area (µm2)

FIGURE 2.3.17 Local loading effect in DCS–GeH4–HCl–H2-based SiGe SEG. Growth rate and Ge content are plotted as a function of the silicon window area (silicon coverage of wafer was about 1% of the total surface).

Deposition Morphology The epi morphology of blanket depositions can be usually described in a simple way: thickness being usually the unique parameter. Only in a few cases, when exhibiting a Stranski–Krastanov growth mode for example, a more complete description is required. On patterned wafer, the situation is different and epitaxial films always present a morphology that is more or less complex. This point is illustrated in the following. In SEG, LE can induce depositions that vary from one epi window to the other, or from the window edge to the center; these effects were discussed previously. On the other hand, facets that are well-known problems are usually observed. They come in the form of flat surfaces that correspond to certain atomic plans. They are caused by the important variations of the growth rate as a function of crystal orientation. Indeed, dense atomic planes like {1 1 1}, {3 1 1}, {1 1 0}, etc., which may present significant nucleation barriers, exhibit slower GR as compared to {1 0 0}, and become apparent in convex-growing zones just like in a Wulf construction. In fact, facets do not correspond to a minimization of the crystal energy but are rather the crystal response, dominated by kinetics effects, to a certain environment. As a consequence, their development depends on several dominant factors that are: . . . . .

Structure conformation: orientations of dielectric edge and surface, etc. Nature of dielectric: SiO2, Si3N4, etc. Crystal orientation: {1 0 0} Si wafers are usual Nature of deposition (Si, SiGe, etc.) Process conditions (T, P, gas flows, etc.)

These factors can be combined to give rise to a huge number of different possibilities. All of them cannot be detailed or discussed here, and only the effects of the process conditions and of deposit nature will be illustrated in the following. Figure 2.3.18 illustrates the influence of temperature on the morphology of silicon SEG grown between SiO2 walls. In both cases, epi was carried out by RTCVD using the SiH2Cl2–HCl–H2 chemistry. SiGe markers were introduced in epi and chemically decorated for X-SEM observation in order to analyze the growth surface evolution. These markers were chosen thin and with a low Ge content in order to minimize their influence on the growth. On the left picture (Si epi at 8508C) we observe very clear {3 1 1} facets, defined by an angle of 25.28 with the (0 0 1) plane, that appear at the beginning of the growth. Such experiments also allow to estimate a growth rate ratio between {3 1 1} and {1 0 0} planes of

© 2006 by Taylor & Francis Group, LLC

2.3-69

Si–SiGe(C) Epitaxy by RTCVD

SiO2 Mono Si 400nm

(a)

SiO2

Mono Si

200nm

(b)

FIGURE 2.3.18 SEM cross sections of Si SEG grown at 8508C (a) and 7508C (b) with the SiH2Cl2–HCl–H2 chemistry and between SiO2 walls. Thin SiGe markers were introduced and chemically etched (dark) in order to visualize the growth surface evolution.

about 0.53, close to the values reported in the literature. On the contrary, no facet can be detected inside the oxide walls on the right picture that corresponds to a Si epi at 7508C. In our opinion, faceting is eliminated because the growth rate ratio (between {3 1 1} and {1 0 0} planes) is significantly increased (as a consequence of the different activation energies), and may be also because of the dramatic surface diffusion decrease due to the lower temperature and the subsequent Cl surface coverage. Figure 2.3.19 shows the morphology of SiGe SEG grown at 7508C in conditions similar to those of Figure 2.3.18 except that germane was added. In this case, Si markers (bright on the picture) were used to visualize to growth morphology. Compared to the silicon growth, SiGe behaves differently. Two systems of facets are clearly visible: the h1 0 0i growth is bordered by {3 1 1} facets, and {1 1 1} facets are present alongside the SiO2 walls. By an important temperature reduction, the authors were able to avoid first (T around 6508C) the {3 1 1} planes and further (T around 6008C) the {1 1 1} ones [35]. In another way, from these conditions it is also possible to delay the facet formation by modifying the surrounding environment and the condition process [35, 36]. As an example, with the integration of nitride instead of oxide and with HCl partial pressure reduction, facets do not appear at the beginning of the growth but after 1000 A˚ or more. In such a case, for applications that are based on films thinner than that, faceting would be no more an issue. When NSEG is carried out on patterned wafers, a technique also referred as ‘‘differential deposition,’’ polycrystalline material is grown on top of dielectric (or polysilicon if present) and epi is grown on the

© 2006 by Taylor & Francis Group, LLC

2.3-70

The Silicon Heterostructure Handbook

monocrystalline Si regions. In this case, in addition to the epi thickness, a number of parameters like the thickness of poly, its nature (grain size and texture), roughness, and the shape or orientation of the poly or mono interface are of interest. Indeed, the poly deposition very often plays a role in the structure and its characteristics have to be taken into account for the application. As an example, in the most common HBT structure that is based on NSEG, the Si–SiGeC poly is a part of the extrinsic base and some of its properties (resistivity, thickness, proclivity to form salicide, etc.) are crucial for the device performances. The poly–epi thickness ratio is an important parameter of a differential deposition. Indeed, once the epi characteristics (thickness, dopant profiles, etc.) are chosen, usually in accordance with the device performances, this ratio determines the thickness of the simultaneously deposited poly. The variation of this poly–epi ratio is given as a function of the deposition temperature for the SiH4–H2 chemistry and given experimental conditions in Figure 2.3.20 [37]. We observe that the ratio as high as 2.4 in the lowtemperature domain decreases down to values close to 1. This variation is supposed to be correlated with the deposition structure that transits from an amorphous nature to a crystalline one. It means that, for a fixed epitaxial structure, the poly thickness (and structure) can be adjusted within a certain domain by a proper choice of deposition conditions.

100%

2.6

80%

2.2

60% 1.8 40% 20%

1.4

Amo content

Poly/epi GR ratio

Amorphous content

FIGURE 2.3.19 SEM cross section of SiGe SEG grown at 7508C with SiH2Cl2–GeH4–HCl–H2 chemistry and between SiO2 walls. Thin Si markers were introduced and chemically decorated (bright) in order to visualize the growth surface evolution.

Growth rate ratio

0% 570

1 620

670 T (⬚C)

720

FIGURE 2.3.20 ‘‘Poly’’–epi growth rate ratio and amorphous content in ‘‘poly’’ as a function of growth temperature. ‘‘Differential deposition’’ was carried out on Si–SiO2 patterns by RTCVD and with the SiH4–H2 chemistry.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-71

On the other hand, we also believe that this ratio plays an important role in the morphology or orientation of the poly–epi interface. When the poly or amo growth rate is much higher than that of epi, the poly growth will push the poly–epi interface toward the epi region to produce a very inclined interface. This interface usually looks like a facet, and in some cases it may correspond or be very close to well-defined facets like the {3 1 1} ones. When the ratio is around 1, the development of the two parts will be more balanced and the interface will be more vertical (perpendicular to the surface). As an illustration, Figure 2.3.21 gives two very different developments of poly–epi interface. At low temperature, with a large growth rate ratio, the poly–epi interface is indeed very inclined. At a higher temperature, the interface is less inclined. And with optimized conditions at 8208C, the interface is almost vertical (not reported here). Between the two extreme conditions (5908C and 8208C), the rule would be: the higher the ratio, the more inclined the poly–epi interface. At this point, we have to note that among the different characteristics of the differential deposition, we preferred to discuss this poly–epi interface orientation because it is a very important characteristic although almost never reported in literature, and also because we are convinced it is somewhat related to the previously discussed faceting effect observed in SEG.

FIGURE 2.3.21 SEM cross sections of silicon NSEG (differential deposition) grown at 5908C (left) and 7208C (right) with SiH4–H2 chemistry (PSiH4 ¼ 0.85 Torr). Dark lines correspond to thin Si0.9Ge0.1 markers submitted to a chemical decoration.

© 2006 by Taylor & Francis Group, LLC

2.3-72

The Silicon Heterostructure Handbook

Pattern-Induced Defectivity As compared to full-sheet, patterns can generate additional epi defectivity via several mechanisms: . . . . .

Possible outgassing from the different materials present on the surface Growth surface can be forced in nonfavorable planes, {3 1 1}, {1 1 1}, etc. Stress field induced by dielectric patterns (STI, etc.) Presence of edges (facets or poly–epi interfaces) causing local shear stress Presence of edges as effective sources of defects

Let us review briefly these points, and note that they may be effective at the same time. As materials and dielectrics present on the surface are deposited increasingly at low temperatures, one may get a significant outgassing of species, like H2O from TEOS films for example, that are capable of oxidizing the silicon surface (during the moderate temperature bake or temperature stabilization) and to induce crystalline defects. This mechanism is even supposed to be more severe in batch systems where the outgassing surface is larger and time longer, and especially in UHVCVD system because the silicon surface may be more sensitive, as compared to single-wafer systems. On the other hand, in some configurations, the epitaxial growth may have to progress via low-kinetics crystalline orientations. As an example, if high aspect-ratio trenches have to be filled on a h1 0 0 i wafer, the epi may have to grow via facets, {3 1 1} or {1 1 1} as a function of the material or conditions (see Figure 2.3.18 and Figure 2.3.19). In such a case, crystalline defects like stacking fault, etc., or even polycrystalline deposition are more easily generated, at least in nonoptimized deposition conditions. These two first points are met in any epi, for pure silicon, for SiGeC alloys as for any other semiconductor materials as well. On the contrary, the two last mechanisms of the list are more specific to strained epi like SiGe or SiGeC on silicon. Indeed, as explained previously, in strained epi there is a strong tendency to relax the mechanical energy of the film by generation and development of misfit dislocations. This behavior has been extensively studied in SiGe–Si blanket wafers and has led to the concept of critical thickness. This concept is twofold. There is the critical thickness that borders the stability domain, a domain that corresponds to the balance between the energy required to extend a misfit segment and the mechanical energy saved by this extension. In practice, one can grow strained epi beyond this limit, and another critical thickness is often defined as the limit of the metastable domain. Note that this limit is not unique and depends on the epi process, especially on the thermal budget. In this domain, it is well established that once nucleated, one misfit is capable to extend on long distances, i.e., the wafer size in some cases. However, there is still one point that is not so clear: where and how the misfit dislocations are generated? In high-quality epi, defects that are not present cannot be supposed to nucleate dislocations, and then wafer edges that are more defective and that present shear stress are supposed to play a major role. In Gerich epi, dislocation loops generations, possibly favored by a SK growth if any, may occur. In the case of patterned wafers, the situation is dramatically changed. Patterns are necessarily associated with edges that correspond to poly–epi interfaces in case of NSEG or to facets in case of SEG, and in both cases the edges will play an important role in dislocation generation. As an example, Figure 2.3.22 gives a photoluminescence image of a Si–SiGe NSEG measured in a 800  800 mm2 window. The Ge content is 22% and the thickness is well above the critical thickness. We observe that all the dislocations (propagating along {1 1 0} directions) are connected to the pattern boundary. Our interpretation is that all dislocations were generated at the epi–poly interface and the poly has then to be considered as an efficient misfit source. As a consequence, in case of NSEG the critical thickness corresponding to the metastable domain is reduced on patterned wafers as compared to full-sheets. It also means that, for a given thickness, patterns will increase the probability to a higher extent to find a misfit in a given epi surface. In SEG, the epi edges certainly also play an important role. However, as their nature is fundamentally different as compared to NSEG, a different behavior can be expected. The NSEG–SEG comparison in terms of misfit dislocation apparition and stress relaxation has been done in certain RTCVD conditions [38]. Figure 2.3.23 reports the density of misfit dislocations for both types of deposition as a function of the film thickness and that summarizes the results. It appears that a significant dislocation density

© 2006 by Taylor & Francis Group, LLC

2.3-73

Si–SiGe(C) Epitaxy by RTCVD

Misfit dislocation

FIGURE 2.3.22 Polycrystal-induced misfit dislocations in SiGe epi observed by room temperature photoluminescence (box area ¼ 800  800 mm2).

Dislocations density (cm−1)

1⫻104

1⫻103

1⫻102

1⫻101

SEG NSEG

1⫻100

0

1000

2000

3000 Thickness (Å)

4000

5000

6000

FIGURE 2.3.23 Dislocation density observed in SiGe layers as a function of epi thickness: comparison between NSEG and SEG. Despite a higher deposition temperature, SEG is more robust than NSEG against misfit dislocations.

(50 dislocations/cm) is obtained for <100 nm in case of NSEG and for about 400 nm in case of SEG. Thus, despite a higher deposition temperature (by about 1008C), SEG is much more robust that NSEG in terms of misfit dislocation generation and plastic relaxation. This dramatic change can be attributed to the different morphology that would give rise to a smaller shear stress (as a consequence of faceting?) and to the absence of poly that would be a dislocation source. This way, SEG is generally observed to provide much larger critical thickness as compared to NSEG. At this point, we have to note that the third point of the list (stress field in substrate) can also play a role in the dislocation appearance, and that it is often mixed with the two last ones in practical applications. However, in the experiments reported above, both epi types were carried out on similar structures and the variations observed have to be attributed then only to the nature of the border, facet or poly. On the other hand, misfit dislocations can also nucleate and propagate during the subsequent operations of the technology as soon as crystalline defects, additional stress or thermal budget are provided. And SEG is expected to be more resistant also against this relaxation.

© 2006 by Taylor & Francis Group, LLC

2.3-74

The Silicon Heterostructure Handbook

2.3.5 Recent Applications At this point, it is interesting to illustrate the possibilities of SiGeC epi by RTCVD with the description of some actual applications of RTCVD. It should help the reader in keeping in mind where and how LTE can be used in practice in electronics. However, as this section contributes to a material chapter, it will be very short. A more complete discussion can be found in Ref. [29]. On the other hand, a number of applications will be detailed in the following chapters. For these reasons, we chose to briefly present only three recent applications we worked on.

SEG-Based Bipolar SiGe LTE has become an accepted technique for the fabrication of the bipolar bases. Initially, HBT technologies were based on SiGe NSEG whereby the epi grown on single-crystal regions forms the intrinsic base and a part of extrinsic base, and the polycrystal deposited on top of dielectric forms a part of the base electrode. More recently, SiGeC was substituted to SiGe for the base formation in order to block boron diffusion during the subsequent thermal budgets. As an illustration of this boron-blocking effect, Figure 2.3.24 reports the SIMS boron profiles of different samples before and after annealing (10008C for 30 sec). Samples were grown with a 10-nm thick boron-doped layer and with different carbon contents, keeping all the other growth parameters constant. The sample measured as-deposited (e) is for control and for SIMS transfer function estimation, and the sample of pure SiGe, without C, measured after annealing (a) gives a reference for diffusion. As compared to pure SiGe, there is dramatically less diffusion in SiGeC samples: in the present conditions the higher the C concentration, the lower the B diffusion. This way, npn HBTs with thinner bases and higher performances have been developed and integrated in complex technologies. And today, all major semiconductor companies already offer a collection of SiGeC-based BiCMOS technologies (see Chapter 3). In addition to carbon incorporation, fully self-aligned (FSA) emitter–base structures are a further step toward high performances. SEG, well suited for the fabrication of a FSA-emitter–base structure [39], has been studied for a long time at STMicroelectronics, first with SiGe epi and more recently with SiGeC [30]. Figure 2.3.25 shows a TEM cross section of such a self-aligned SEG-based SiGeC HBT. The SiGeC epi was grown by RTCVD in a commercially available reactor (Applied Material Centuray), and, in the

1⫻1020

[B] (at/cm3)

1⫻1019

1⫻1018 (b) (a) 1⫻1017

(e) (d) (c) (a) [C] = 0 (b) [C] = C1 (c) [C] = 2*C1 (d) [C] = 4*C1 (e) As-dep

1⫻1016

1⫻1015 0

50 Depth (nm)

100

FIGURE 2.3.24 Boron SIMS profiles after a 30 sec annealing at 10008C in different SiGeC films.

© 2006 by Taylor & Francis Group, LLC

2.3-75

Si–SiGe(C) Epitaxy by RTCVD

FIGURE 2.3.25 TEM cross section of a SiGeC SEG-based HBT.

1⫻10−2

Ic

1⫻10−4

(b)

1⫻10−6

Ib, Ic (A)

Ib

(a) Non-ideal I b

1⫻10−8 1⫻10−10 (a)

1⫻10−12 0

(b) 0.5 Vbe (V)

1

FIGURE 2.3.26 Gummel characteristics of a SiGeC SEG-based HBT: (a) before and (b) after epi optimization.

picture, we note the absence of defects in the base, a smooth epi, and a good link between the epi and the polycrystal. The main difficulty of SiGeC SEG comes from the higher thermal budget, as compared to NSEG. Indeed, if carbon is introduced in too large contents or in improper conditions, significant amounts of carbon atoms will be incorporated in nonsubstitutional sites (interstitial, clusters, etc.) and the epitaxial base will then have poor electronic properties. The first detrimental effect usually detected is an excess base current due to increased recombination. This effect is illustrated by Figure 2.3.26, which reports HBT Gummel plots before and after selective SiGeC epi optimization. When using nonoptimized epi process, the base current at low levels deviates very much from its ideal variation: interstitial carbons or SiC clusters induce more recombination, especially if they are present in the depleted emitter–base region [30]. On the other hand, base current below 10
11 A /mm2 at Vbe ¼ 0.5 V can be achieved with optimized base epitaxy. High-frequency measurements of HBT are another way to characterize our SiGeC SEG process in terms of boron diffusion, as well as to test the validity of the FSA structure in terms of parasitics.

© 2006 by Taylor & Francis Group, LLC

2.3-76

The Silicon Heterostructure Handbook

217.2 217.2 215.8 219.3

Min 206.6

FIGURE 2.3.27

219.0 213.5 208.8 209.5 210.1 210.6

207.6 215.4 213.2 207.9 209.3 209.3 209.8 213.3 Max 220.0

212.3 215.5 212.6 209.0 207.5 209.3 208.5 213.5

214.5 217.8 208.4 206.6 207.7 208.3 210.7 212.5 Mean 212.1

218.7 215.5 206.7 206.8 208.7 211.8

220.0 215.8 212.3 213.1

Stdev 3.9

fT cartography (GHz) of a 0.17  3.6 mm2 bipolar at VCB ¼ 0.5 V and VBE ¼ 0.92 V.

The results obtained for fT (220 GHz) and fmax (240 GHz) [40], and other DC characteristics not reported here, demonstrated that the neutral electrical base was very thin and kept inside SiGe. Thus, despite the significant activation annealing used for CMOS compatibility, the boron diffusion was effectively blocked in the selectively deposited SiGeC base. In addition, the simultaneous high values of fT and fmax demonstrate the low parasitic components of this architecture. On the other hand, SEG processes are often feared for their micro- or macroloading effects even though they can be efficiently solved. Indeed, the fT cartography presented in Figure 2.3.27 shows a standard deviation of less than 2% (4.8% for fmax). These values demonstrate that any process uniformity or macro-LE issue has been solved in the present process. In the same manner other results showed that it does not suffer from micro-LE as well. Thus, no blocking point was detected toward industrialization.

Double Gate MOS Double gate MOS (DG-MOS) transistors present important potential advantages: excellent Ion /Ioff trade-off, good control of short-channel effects (SCE) and drain-induced barrier lowering (DIBL), and higher channel conductivity. They may be the alternative device structure for the ultimate CMOS nodes. The DG devices presented here have been processed in a planar configuration owing to the utilization of the silicon-on-nothing (SON) process and the main operations are detailed in Chapter 2.10. After classical STI formation, a two-step epitaxy is done: a selective epi of SiGe (20 to 40 nm) followed by a thin NSEG of silicon. This Si NSEG leads to a mono-Si layer on active zones with a well-controlled thickness of the conduction channel, and to a poly-Si deposition on STI areas. Then, after source–drain– channel definition by photolithography and etching, the underlying SiGe is selectively etched, thanks to a specific isotropic plasma processing, leaving a silicon bridge (future DG-MOS channel) over the active zone. The SEM view given in Figure 2.3.28 illustrates the situation. One major advantage of this structure on some others reported in literature is related to the fact that the thickness of the silicon channel is defined by epitaxy that is capable of nanometric thickness with excellent uniformity. The remaining silicon bridge is oxidized to form a 20-A˚ thick gate oxide. In situ phosphorus-doped polysilicon is deposited all around the silicon bridge, and top gate and bottom gate are patterned by standard RIE gate etching. After the formation of spacers, extensions are implanted, and because thin Si films are used, elevated S/D were formed by Si SEG before standard 8 nm Co salicidation. A TEM cross section of a finished device with Lgate ¼ 40 nm and TSi ¼ 15 nm is presented in Figure 2.3.29. This picture shows that the morphology of the device is well controlled, whereas additional high-resolution TEM observations proved that the Si channel was a perfect monocrystal. We can also note that we optimized the cleaning step before elevated S/D in order to minimize the TEOS consumption under the offset spacer (as located by the white circle), and that the elevated S/D SEG exhibited some faceting but without any detrimental effect on electrical device characteristics.

© 2006 by Taylor & Francis Group, LLC

2.3-77

Si–SiGe(C) Epitaxy by RTCVD

Poly Si Mono Si

50 nm

FIGURE 2.3.28 Silicon bridge over active zone after SiGe selective etching.

Top gate Spacer Conduction channel Epitaxial raised S/D

S

Bottom gate

D

100 nm

FIGURE 2.3.29 Along-channel TEM cross section of final DG device, Lgate ¼ 40 nm, TSi ¼ 15 nm.

Electrical results confirm that the DG architecture improves considerably the device performances with very high drain currents (more than a factor of 2 as compared to conventional pMOS), small SCE, well-controlled DIBL, and subthreshold slope almost ideal [41]. The best results in terms of drive currents were obtained for a 70 nm gate length coupled with a 30 nm TSi with Ion ¼ 1954 mA /mm (Ioff ¼ 283 nA /mm) for nMOSFETs (more detailed results are reported in Ref. [41]). On the other hand, the geometry of DG devices provides an excellent electrostatic integrity. This effect is illustrated in Figure 2.3.30, which reports the variation of DIBL as function of the gate length and for different silicon channel thicknesses. We observe that the thinner the channel, the lower the DIBL, and that DIBL is excellent as soon as the channel thickness does not exceed a third of the gate length. Ultrathin Si films (10 nm), which can be controlled by epi deposition in the present technology, are thus mandatory for future CMOS technologies with short (32 to 45 nm) gates.

© 2006 by Taylor & Francis Group, LLC

2.3-78

The Silicon Heterostructure Handbook

Tsi 20 nm

80

Tsi 15 nm

70

Tsi 30 nm

DIBL (mV)

100 90

60 50 40 30 20 10 0 0

FIGURE 2.3.30

50 100 150 Largeur de grille (nm)

200

Drain-induced barrier lowering (DIBL) measured for different SOI thicknesses.

FD-SOI Silicon on insulator (SOI) substrates have some traditional advantages like reduced junction capacitance, lower power consumption, and higher RF performances, as compared to bulk silicon. In addition to that, ultrathin SOI with an improved electrostatic integrity should dramatically improve SCE that are important issues in advanced digital CMOS with ultrashort channels. Thus, ultrathin film (UTF) approach is very suited to achieve future CMOS and these substrates may become a standard for these applications. When fabricating CMOS on thin SOI films, the formation of S/D requires that these regions have been thickened. During salicidation, a certain excess of silicon is indeed necessary to insure good channel– silicide continuity. Elevated S/D deposited by SEG are then mandatory, and the situation is illustrated by Figure 2.3.31 that gives the cross section of such a FD-MOS fabricated on thin SOI. However, the manipulation of UTF requires special attention, as they are not stable with temperature. The difficulty is illustrated in Figure 2.3.32a, where a 6-nm-thick SOI film has been submitted to a

Tox

Epitaxy

1.4 nm

25 nm

Lg 60 nm Tsi 17 nm BOX 145 nm

FIGURE 2.3.31 Along-channel TEM cross section of final FD-SOI device with elevated S/D: Lgate ¼ 60 nm, TSi ¼ 15 nm, S/D elevation ¼ 25 nm.

© 2006 by Taylor & Francis Group, LLC

2.3-79

Si–SiGe(C) Epitaxy by RTCVD

Silicon reduction

Gate

Oxide

1µm (a)

Oxide

SOI

Gate No silicon reduction

0.5 µm (b)

FIGURE 2.3.32 SEM top view of a 40-nm thick SEG on ultrathin (6 nm) FD-SOI films: (a) standard process and (b) improved process.

standard Si SEG process. In this case, the H2 bake was carried out at a moderate temperature (<8508C) and selective deposition at 7508C with DCS–HCl chemistry, and we observe an important lateral constriction (about 50 nm) of SOI in active areas, as indicated in white circle. Some experiments were undertaken to examine or quantify if the missing SOI part was removed or displaced by evaporation (Equation (2.3.1) may be effective) or by agglomeration. On the other hand, via a dramatic thermal budget reduction we managed to carry out a 40-nm-thick Si SEG without any film restriction, as shown in Figure 2.3.32b. By further process optimization, we even demonstrated Si SEG on SOI films as thin as 3 nm, results not reported here.

© 2006 by Taylor & Francis Group, LLC

2.3-80

The Silicon Heterostructure Handbook

This application is well illustrative of future material developments that will concern excessively thin films and that will present new issues.

2.3.6 Summary SiGe(C) materials and low-temperature epitaxy are today expanding the capabilities and applications of Si technologies. They have already pushed the Si bipolar technologies to tremendous performances, the fT/fmax values (220 GHz /240 GHz) above-mentioned and obtained in a fully industrial environment, and even more aggressive values reported in literature. On the other hand, LTE is entering the CMOS fabrication domain to give important improvements of MOS performances, using strained channels as an example [42], as well as to develop new innovative architectures like the DG-SON architecture illustrated in the previous section. SiGe(C) materials make the concept of bandgap engineering available in Si technologies. In association with other techniques like the selective etching (see Chapter 2.11), these materials also give a number of new device architectures possible. As a consequence, their (potential) applications are numerous and different. Thus, rather than try an exhaustive list of these applications, an almost impossible task, we prefer to detect what are the main trends in epi science. In our opinion, the most pressing requests are: new metastable materials (epitaxial SiGeC bases of HBT, highly doped epi, strained CMOS channels, etc.), complex stacks of very thin elementary epi films (base–emitter structure of HBTs), and extremely low thermal budgets (elevated source–drains in future CMOS, etc.). These materials requests can be translated into equipment or process requirements. .

.

.

.

.

.

Low deposition temperatures: this may be achieved by a very smart process or technology optimization, but new chemistries or new precursors would be welcome. Advanced gas panel functionality: new processes require a number of gases in the same time or in sequence; the gas panel has to be able to flow every gas needed in a step while it prepares or purges those required for the next step. Efficient gas control: as the elementary films are thinner and thinner, with deposition times possibly short, any lag time in gas flow has to be minimized. The gas pressure of the different gas panel parts has to be matched, and the gas panel design has to be compact with minimal dead volumes. High-temperature agility: with metastable materials and with very sensitive structures, temperature stabilization time may be detrimental and has to be minimized. Low-temperature cleaning: hydrogen bake cannot be carried out on very temperature-sensitive structures; integrated pre-clean (wet, plasma, new chemistries, etc.) will be mandatory if highquality epi is required. Efficient tool: LTE will have to be less expensive for mass production, reactors have then to present robust cleanliness, no memory effect and high uptime.

Note that we do not include the quality of process gases and of reactor atmosphere because the author believes that, although the epi temperature will have to be decreased, these criteria already fulfilled today will not be much more severe in future. As a final note, we believe that LTE will be a key technique to pass the very important roadblocks that are present on the silicon technology roadmap. And, for these reasons and as predicted [29], the present decade is very exciting, especially in SiGeC epi by RTCVD.

Acknowledgments We wish to thank the many people of ST Crolles who made this contribution possible, especially the persons involved in epitaxy: P. Ribot, L. Georjon, T. Ouptier, N. Loubet, and F. Brossard; and those in advanced device applications: H. Baudry, A. Chantre, P. Chevalier, C. Fenouillet, M. Laurens, M. Marty, S. Monfray, A. Monroy, J. Mourier, T. Skotnicki, B. Szelag, G. Troillard, and A. Vandooren.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-81

References 1. J.F. Gibbons, C.M. Gronet, and K.E. Williams. Limited reaction processing: silicon epitaxy. Appl. Phys. Lett. 47, 721, 1985. 2. J.C. Sturm, P.V. Schwartz, E.J. Prinz, and H. Manohara. Growth of Si1
xGex by rapid thermal chemical vapor deposition and application to heterojunction bipolar transistors. J. Vac. Sci. Technol. B 9, 2011, 1991. 3. FUV4 from Jipelec — France. See for example: Thin Solid Films 222, 52, 1992. 4. J.C. Sturm, H. Manoharan, L.C. Lenchyshyn, M.L.W. Thewalt, N.L. Rowel, and D.C. Houghton. Well-resolved band-edge photoluminescence of excitons confined in strained Si1
xGex quantum wells. Phys. Rev. Lett. 66, 1362, 1991. 5. D. Dutartre, G. Bremond, A. Souifi, and T. Benyattou. Excitonic photoluminescence from Si-capped strained Si1
xGex layers. Phys. Rev. B 44, 11525, 1991. 6. C.A. King, J.L. Hoyt, C.M. Gronet, J.F. Gibbons, M.P. Scott, and J. Turner. Si/Si1
xGex heterunction bipolar transistor produced by limited reaction processing. IEEE Electron Dev. Lett. 10, 52, 1989. 7. D. Dutartre, P. Warren, I. Sagnes, P.A. Badoz, J.C. Dupuis, G. Prudon, and A. Perio. Epitaxy and doping of Si and Si1
xGex at low temperature by rapid thermal chemical vapour deposition. J. Vac. Sci. Technol. B 11, 1134, 1993. 8. McD. Robinson and L.H. Lawrence. Characterization of high growth rate epitaxial silicon from a new single wafer reactor. In Semiconductor Fabrication: Technology and Metrology, ASTM STP 990, Dinesh C. Gupta, Ed. American Society for Testing and Materials, Philadelphia, 1989. 9. J.C. Bean. Growth techniques and procedures. In Germanium Silicon: Physics and Properties, Semiconductors and Semimetals, Vol. 56, R. Hull and J.C. Bean, Eds. Academic Press, San Diego, CA, 1998, p. 8. 10. W. Kern and D.A. Puotinen. Cleaning solution based on hydrogen peroxide for use in semiconductor technology. RCA Rev. 31, 187, 1970. 11. T. Hsu, B. Anthony, R. Qian, J. Irby, D. Kinosky, A. Mahajan, S. Banerjee, C. Magee, and A. Tash. Defect microstructure in low temperature epitaxial silicon grown by RPCVD. J. Electron. Mater. 19, 4, 1990. 12. D.J. Meyer. Si-based alloys: SiGe and SiGe:C. In Silicon Epitaxy, Semiconductors and Semimetals, Vol. 72. D. Crippa, D.L. Rode, and M. Masi, Eds. Academic Press, New York, 2001, pp. 345–395. 13. B.S. Meyerson. Low-temperature silicon epitaxy by ultrahigh vacuum /chemical vapour deposition. Appl. Phys. Lett. 48, 797, 1990. 14. See for example the integrated wet clean referred as ‘‘OASIS CleanTM,’’ AMAT Inc, 2003. 15. J.C. Sturm, P.V. Schwartz, E.J. Prinz, and H. Manoharan. Growth of Si1
xGex by rapid thermal chemical vapour deposition and application to heterojunction bipolar transistors. J. Vac. Sci. Technol. B 9, 2011–2016, 1991. 16. D. Dutartre, P. Warren, I. Berbezier, and P. Perret. Low temperature silicon and Si1
xGex epitaxy by rapid thermal chemical vapour deposition using hydrides. Thin Solid Films 222, 52, 1992. 17. G. Pares, J.L. Regolini, J. Mercier, D. Dutartre, and D. Bensahel. Kinetics aspects of epitaxial silicon growth using disilane in a rapid thermal processing system. J. Appl. Phys. 68, 4885, 1990. 18. M. Lier, C.M. Greelief, S.R. Kasi, and M. Offenberg. Kinetics of silicon epitaxy using SiH4 in a rapid thermal chemical vapor deposition reactor. Appl. Phys. Lett. 56, 629, 1990. 19. M. Racanelli and D.W. Greve. Temperature dependance of growth of Si1
xGex by ultra high vacuum chemical vapor deposition. Appl. Phys. Lett. 56, 2524, 1990. 20. D.J. Robbins, J.L. Glasper, A.G. Cullis, and W.Y. Leong. A model of heterogeneous growth of Si1
xGex films from hydrides. J. Appl. Phys. 69, 3729, 1991. 21. K. Sinniah, M. Sherman, L. Lewis, W. Weinberg, J. Yates Jr, and K.C. Janda. New mechanism for hydrogen desorption from covalent surfaces: the monohydride phase on Si (1 0 0). Phys. Rev. Lett. 62, 567, 1989.

© 2006 by Taylor & Francis Group, LLC

2.3-82

The Silicon Heterostructure Handbook

22. M. Todd and D. Weeks. Low temperature, high growth rate epitaxial silicon and SiGe alloy films. First International SiGe Technology and Device Meeting, ISTDM2003, Nagoya, Japan, 2003, p. 153. 23. J.P. Posthill, R.A. Rudder, S.V. Hattangady, C.G. Fountain, and R.J. Markunas. On the feasibility of growing dilute CxSi1
x epitaxial alloys. Appl. Phys. Lett. 56, 734, 1990. 24. L.D. Lanzerotti, J.C. Sturm, E. Stach, R. Hull, T. Buyuklimanli, and C. Magee. Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation. 1996 IEDM Tech. Digest, 1996, p. 249. 25. P.S. Chen, S.W. Li, Y.H. Liu, M.H. Lee, M.J. Tsai, and C.W. Liu. UHVCVD of hetero-epitaxial SiGe:C and SiC thin films on Si(1 0 0) with ethylene (C2H4) precursor as a carbon source. Second International SiGe Technology and Device Meeting, ISTDM2004, Frankfurt /Oder, Germany, 2004, p. 196. 26. F. Deleglise, C. Fellous, and D. Dutartre. Carbon incorporation study for SiGeC epitaxy optimization in RTCVD. First International SiGe Technology and Device Meeting, ISTDM2003, Nagoya, Japan, 2003, p. 151. 27. P.A. Coon, P. Gupta, M.L. Wise, and S.M. George. Adsorption and desorption kinetics for SiH2Cl2 on Si (1 1 1) 7  7. J. Vac. Sci. Technol. A 10, 324, 1993. 28. M. Hierlemann, A. Kersch, C. Werner, and H. Schaefer. A gas-phase and surface kinetics model for silicon epitaxial growth with SiH2Cl2 in a RTCVD reactor. J. Electrochem. Soc. 142(1), 259. 1995. 29. D. Dutartre. Silicon epitaxy: new applications. In Silicon Epitaxy, Semiconductors and Semimetals, Vol. 72, D. Crippa, D.L. Rode, and M. Masi, Eds. Academic Press, New York, 2001, pp. 397–457. 30. C. Fellous, F. Deleglise, A. Talbot, and D. Dutartre. Selective SiGeC epitaxy by RTCVD for high performance self-aligned HBT. 33rd European Solid-State Device Research Conference, Estoril, Portugal, 2003, p. 481. 31. H. Schaefer, J. Boeck, R. Stengl, H. Knapp, K. Aufinger, M. Wurzer, S. Boguth, M. Rest, R. Schreiter, and T.F. Meister. Selective epitaxial growth of SiGe:C for high speed HBTs. Appl. Surf. Sci. 224, 18, 2004. 32. N. Laurent, C. Fellous, and D. Dutartre. Non-destructive defect inspection in SiGe HBT using room temperature photoluminescence. Second International SiGe Technology and Device Meeting Proceedings, 2004, Frankfurt /Oder, Germany, 2004, p. 49. 33. C. Fellous, F. Romagna, and D. Dutartre. Thermal and chemical loading effects in non selective Si / SiGe epitaxy. Mater. Sci. Eng. B 89(1), 323, 2002. 34. P. Ribot and D. Dutartre. Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD. Mater. Sci. Eng. B 89(1), 306, 2002. 35. A. Talbot, J. Arcamone, C. Fellous, F. Deleglise, and D. Dutartre. Investigation of facet formation in RTCVD Si /SiGe selective epitaxie. In SiGe Materials, Processing and Devices, ECS 2004, Honolulu, Hawaii, p. 601. 36. R. Loo and M. Caymax. Avoiding loading effects and facet growth: key parameters for successful implementation of selective epitaxial SiGe deposition for HBT-BiCMOS and high-mobility heterochannel pMOS devices. Appl. Surf. Sci. 224, 24, 2004. 37. A. Talbot, J. Arcamone, C. Fellous, F. Deleglise, and D. Dutartre. Study of the poly/epi kinetics ratio in SiH4-RTCVD for new CMOS architectures. Second International SiGe Technology and Device Meeting, ISTDM2004, Frankfurt /Oder, Germany, 2004, p. 200. 38. C. Fellous, F. Romagna, and D. Dutartre. Comparison of dislocation generation in selective and non-selective SiGe epitaxy. Fifteenth International Symposium on Chemical Vapor Deposition (CVD-XV), May 14–19, 2000, Toronto, Canada, 2000, p. 442. 39. F. Sato, T. Hashimoto, T. Tasumi, H. Kitahata, and T. Tashiro. Sub 20 ps ECL circuits with 50 GHz fmax self-aligned SiGe HBTs. IEDM 1992. Tech. Digest, 1992, p. 397. 40. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C.T. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Bartalat, R. Beerkens, N. Zerounian, F. Aniel, and A. Chantre. Accepted to the 2004 Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, Canada, September 13–14, 2004.

© 2006 by Taylor & Francis Group, LLC

Si–SiGe(C) Epitaxy by RTCVD

2.3-83

41. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Julian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, MP. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteannu, J-L. Autran, and T. Skotnicki. Highly performant double gate MOSFET realized with SON process. IEDM 2003. Tech. Digest, 2003, p. 449. 42. K. Mistry, M. Armstron, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadski, K. Zhang, S. Thompson, and M. Bohr. Delaying Forever: Uniaxial Strained Silicon Transistor in a 90 nm CMOS Technology. 2004 Symposium on VLSI Technology, Hawaii, Honolulu, 2004, p. 50.

© 2006 by Taylor & Francis Group, LLC

2.4 MBE Growth Techniques

Michael Oehme and Erich Kasper University of Stuttgart

2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7

Introduction................................................................. 2.4-85 Requirements on an SiGe MBE System .................... 2.4-85 UHV Conditions ......................................................... 2.4-86 Sources of Atomic and Molecular Beams ................. 2.4-88 Substrate Heating and Cleaning ................................ 2.4-91 In Situ Analysis ............................................................ 2.4-92 Summary ...................................................................... 2.4-93

2.4.1 Introduction In the past few years, the development of modern semiconductor devices utilizing structures with atomic dimensions has been advanced by vertical design. Layer structures with nanometer dimensions featuring quantum effects have become dominant. This would be applicable in some SiGe semiconductor devices such as in the resonant tunneling diode [1] or high electron mobility transistor (HEMT) [2]. Modern epitaxy techniques like the molecular beam epitaxy (MBE) method [3, 4] allow the growth of very thin crystalline silicon germanium layers with well-defined dopants by very low growth temperatures. In this temperature regime volume diffusion is negligible. Furthermore, the critical thickness of SiGe heterostructures is increasing. However, in this low-temperature growth regime, surface segregation of dopant or alloy atoms has turned out to be a dominant mechanism for profile smearing. Knowledge of segregation behavior is necessary for device design and realization based on low-temperature epitaxy. Especially in the case of SiGe MBE surface segregation is observed for alloy atoms and dopants like boron, phosphorus, or antimony [5]. The purpose of this chapter is to describe the SiGe MBE growth techniques with the individual technical components such as the ultrahigh vacuum (UHV) system, the evaporation sources, the substrate heating, and the in situ monitoring of the process.

2.4.2 Requirements on an SiGe MBE System Epitaxy describes the oriented growth of a single crystalline film on a substrate. The growing layer follows the orientation of the substrate. The driving force for the crystalline growth is minimizing of energy because the perfect crystal is the energetically favorable solid. A requirement for epitaxy is a clean substrate surface, otherwise the information about orientation of the substrate is disordered or even destroyed and the consequences are crystalline defects up to polycrystalline or amorphous growth. MBE growth is carried out under conditions far from thermodynamic equilibrium and is dominated mainly by the kinetics of the surface processes occurring when the impinging beams react with the top atomic layer of the substrate.

2.4-85 © 2006 by Taylor & Francis Group, LLC

2.4-86

The Silicon Heterostructure Handbook

An MBE machine involves the generation of molecular beams of matrix material such as silicon or germanium and doping species and their interaction with the substrate surface to form a single-crystal deposit under UHV conditions. The atomic or molecular fluxes of elemental constituents are evaporated or sublimated in special electron beam evaporators (EBEs) or in radiatively heated effusion cells. For a precise control of the beam fluxes over the substrate all sources exhibit rapidly acting mechanical shutters, and the flux of the deposition materials can be measured directly with a flux monitor, for example, a quadrupole mass spectrometer (QMS) or indirectly over the effusion cell temperature (after calibration). This enabled the growth of SiGe layers with controlled Ge content between 0% and 100% with an arbitrary doping structure. Another advantage is the growth of very sharp doping transitions over several decades with special doping strategies. The quality of the vacuum conditions and the purity of the constituent fluxes are fundamental specification of the MBE because the semiconductor properties are sensitive to impurities. Crystal quality and defect density are drastically limited by insufficient partial pressure [6]. For the growth of epitaxial layers with high-purity and crystalline perfection UHV equipment with a basis pressure less than 1
1010 mbar is needed. Really important are the vacuum conditions during the layer growth, where very hot components in the reactor need special materials with a low vapor pressure such as tantalum or molybdenum. From the above discussion, the essential features of an SiGe MBE system are 1. 2. 3. 4.

UHV conditions during growth Clean Sources of atomic and molecular beams Substrate-cleaning scheme with low thermal budget In situ analysis of process conditions and real-time monitoring for close-loop control

In the following sections, we discuss these topics with emphasis on technological aspects. Figure 2.4.1 shows a picture of a commercial 200 mm SiGe MBE equipment (with permission of DCA instruments). The machine can be upgraded to wafers with 300 mm diameter.

2.4.3 UHV Conditions In order to overcome the exchange between air and UHV, an MBE machine consists of at least two chambers, a growth chamber and a load lock. According to different application needs, designs of MBE systems with two [7], three [8], or more [9] chambers are known. A schematic view of the basic unit is shown in

FIGURE 2.4.1 Picture of a commercial 200 mm SiGe MBE equipment (with permission of DCA instruments). The machine can be upgraded to wafers with 300 mm diameter.

© 2006 by Taylor & Francis Group, LLC

2.4-87

MBE Growth Techniques

Figure 2.4.2. It consists of two independently pumped UHV chambers connected with a UHV gate valve. At the left side there is the load lock with the wafer-transfer mechanism. This chamber accommodates a cassette-type magazine for silicon wafers. In modern MBE systems this magazine meets an industrial standard for 25 wafers with diameters of 150 or 200 mm. The load lock is pumped rapidly with a turbomolecular pump or with a cryopump. A typical system achieves a pressure in the range of 108 mbar within 90 min. The wafer transport between the storage chamber and growth chamber is computer controlled, and performed completely under UHV conditions. To minimize the contamination during transfer of a substrate from the load lock into the deposition chamber, multiple wafer loading is often used. These wafers are transferred into a parking stage within a central chamber for storage under UHV with a pressure in the range of 1010 mbar. Figure 2.4.2 (right side) shows a schematic view of a growth chamber. This chamber accommodates all the installations necessary for MBE growth. These are substrate holder, substrate heater, and substrate rotation; evaporation sources for matrix materials and dopants; and monitoring and analyzing facilities. Typically, the growth chamber is evacuated with a pumping cascade existing of an oil-free prevacuum pump, a turbomolecular pump, and a high-speed sorption pump, e.g., a sublimation pump cooled with liquid nitrogen. The growth chamber is always under UHV except for maintenance work or source refilling. After venting the chamber, a conditioning of the MBE system requires bakeout up to 3008C over more than 24 h. For this heater elements in a jacket are welded to the chamber walls from outside. For a minimum of preparation time to the start of bakeout, a layer of thermal isolation fiber is permanently sandwiched between the chamber wall and an aluminum cover. Under growth conditions, cooling water pipes welded to the chamber walls effectively reduce outgassing. Also, all effusion cells exhibit cooled walls to reduce the thermal radiation.

Substrate rotation RGA

Loadlock with transfer mechanism Gate valve QMS

Heater

RHEED

Substrate

Shutter

Si Ge-beam evaporator Effusion cell

Pyrometer

FIGURE 2.4.2 Schematic illustration of an SiGe MBE system; the pumping system is not shown.

© 2006 by Taylor & Francis Group, LLC

2.4-88

The Silicon Heterostructure Handbook

H2 Ion current (arbitrary units)

Total pressure 10−9 mbar Basis pressure (<10−10 mbar)

N2/CO

CO2 0 0

10

20

30

40

50

Mass number

FIGURE 2.4.3 Residual gas spectrum of well-conditioned MBE chamber before (basis pressure <10–10 mbar) and during (total pressure 109 mbar) the growth of an SiGe layer.

The outgassing of equipment materials and surfaces limits the vacuum pressure. Figure 2.4.3 shows a typical residual gas spectrum of a well-conditioned MBE system before and during the growth of an SiGe layer. Hydrogen (H2) is the main detectable residual species in the UHV. Small increases in the heights of CO, and CO2 occur during growth, but the pressure is also dominated by H2. residual H2O, N2

2.4.4 Sources of Atomic and Molecular Beams For typical Si growth rates of the order of nanometers per second flux densities in the range of 5
1014 to 5
1015 cm2 sec1 are required. Si temperatures of about 17008C are necessary when these flux densities are generated by evaporation from a Si-source distance of about 30 cm from the substrate. At such temperatures, molten Si is very reactive and it would cause excessive contamination from the crucible material [10]. A solution for this problem is heating of Si with an electron beam. Figure 2.4.4 shows a schematic view of the major components of a Si EBE. Tungsten filament emits electrons and these are accelerated in an electric field (electron gun) with typical energies between 4 and 12 keV. In a magnetostatic field, the electrons are deflected to an angle of 2708 to avoid contamination by tungsten atoms, which emitted from the filament, as metallic impurities are undesirable in the molten Si. The high-energy electrons impinge on a single-crystal, high-purity (resistivity > 1000 V cm1) Si ingot, which is placed in a water-cooled Cu-crucible. The focused electron beam is partially melting the Si surface. The electron beam can be scanned over the whole crucible. Due to the thermal properties of Si, the molten region is restricted to the area directly heated by the electron beam. Several problems result from the EBE application; electron- and ion-beam-stimulated desorption of gas molecules adsorbed on the system walls and cold shrouds, damage of the grown film by impinging electrons and ions and interference with in situ monitoring instruments. In order to minimize these problems, the EBE is screened by cold walls with defined aperture, which limit the beam cone and reduce the thermal load of the chamber walls. All metal surfaces are covered with high-purity Si plates to reduce the risk of interaction with electrons and ions. The flux monitoring of Si is performed by a QMS. The QMS measures the intensity of the Si isotope, with the mass number 30, directly in the Si molecular beam because this mass is free of fragments of other residual species. The QMS signal is proportional to the flux, respectively the growth rate on the substrate surface.

© 2006 by Taylor & Francis Group, LLC

2.4-89

MBE Growth Techniques

Si-molecular beam

Accelerated electron beam

Magnetic deflection element

Molten Si

Si-crucible

Watercooled Cu-hearth Electron gun

FIGURE 2.4.4 Schematic view of the major components of an Si electron beam evaporator.

The Si EBE is also a source for silicon ions. In the area above the silicon melt, the flux of evaporated atoms is ionized partially by the interaction with the electron beam. A potential up to several kV can be applied to the isolated substrate holder to focus and accelerate the Si ions. Thus, it is possible to use special growth strategies such as doping by secondary ions (DPI) [11], generation of point defects [12], or dislocation annihilation [13]. For the evaporation of Ge there are two possibilities, with an EBE or a single effusion cell. The construction of Ge-EBE is similar to the Si-EBE. However, the turbulence in Ge is much more severe as in Si, because Ge has much smaller thermal conductivity than Si, resulting in complete melting of the Ge reservoir. Contact of the molten Ge with the water-cooled Cu crucible triggers heavy turbulence. To overcome this problem, a liner made from high-purity, single-crystal Si is used. Possible enrichment of Si in the Ge reservoir is acceptable, since usually SiGe layers are grown and both fluxes are monitored simultaneously by a mass spectrometer. The other possibility is the Ge evaporation from a single effusion cell [14]. The particular property of this cell is the co-evaporation of Ge and carbon with a flux ratio of roughly 1000, because the crucible consists of pyrolithical carbon. Carbon is partly dissolved in molten germanium up to the saturation limit. Saturation is obtained by heating the crucible with the germanium–carbon ingot above the melting point. Dissolved carbon evaporates much easier and the germanium /carbon ratio is reduced to three orders of magnitude, which is exactly the right ratio for SiGe-HBT applications with suppressed boron out-diffusion [15]. A technical solution is shown in Figure 2.4.5. Ge is melting in a graphite crucible with a large area opening (4 cm2). The crucible and the graphite support are specially designed to withstand the strong tensile forces exerted by the increase of Ge volume during solidification. The diamond lattice is an open structure with a considerable volume increase both for Si and Ge during solidification. The electrical current heater surrounds the crucible, the outward heat flux is shielded by a graphite cage, tantalum- and Si-shields, and a cold wall. A thermocouple is mounted near the bottom of the crucible. A clear problem of this source after long-time operation seems to be the formation of a thin carbon film, which covers part of the molten germanium like a skin. This carbon skin is probably created by carbon precipitation during cooling down the melt from the operating temperature (typically 13008C) to the standby temperature chosen slightly above the Ge melting point of 9388C. This carbon skin reduces with time the effective area for evaporation for both germanium and carbon. (Remember:

© 2006 by Taylor & Francis Group, LLC

2.4-90

The Silicon Heterostructure Handbook

QMS

Ge-molecular beam with C-atoms

Shutter Si aperture Graphite crucible

Tantalium shields Graphite

Heater

Germanium

Cold wall

Thermocouple Current control

FIGURE 2.4.5

Effusion cell for Ge C co-evaporation with quadrupole mass spectrometer (QMS) flux control.

The evaporation from carbon itself is negligible at the source temperatures.) The source, therefore, cannot be operated at the usual mode of an effusion cell with thermocouple control. Instead a flux control with a QMS is necessary for power regulation. The single effusion cell for germanium evaporation will considerably reduce the effort of carbon doping of MBE-grown HBT structures. In nanoelectronic devices based on Si or SiGe, carbon doping plays an important role for two reasons. First, carbon doping delivers a heterostructure barrier for electrons [16] and may be used for quantum wells with electron confinement. Second, the retarded boron diffusion [17] is utilized in SiGe-HBTs with improved process stability. The sublimation of carbon requires very high temperatures up to 23008C. Special high-temperature sublimation cells achieve C concentrations up to several percent in Si1xyGexCy layers [18]. p-Type and n-type doping over a wide range of concentration and with abrupt doping transitions is necessary for novel device structures. High and moderate levels of dopants of both types are needed to grow devices. In an SiGe MBE several doping techniques are used. Boron is commonly used for p-type doping as it has a larger equilibrium solid solubility and a very low surface segregation. In modern SiGe MBE systems, boron is evaporated using a high-temperature source with special graphite crucibles. Temperatures between 15008C and 20008C are required to achieve doping levels of 1015 cm3 up to several 1020 cm3. n-Type doping during SiGe MBE growth is problematic because of low sticking coefficients and surface segregation. Thus, a limited range of dopant concentrations is available. In an SiGe MBE antimony and phosphorus can be used.

© 2006 by Taylor & Francis Group, LLC

2.4-91

MBE Growth Techniques

Antimony is the more attractive n-type doping material because it can be directly co-evaporated from a controlled source during the growth. However, the extreme temperature sensitivity of surface segregation requires special doping strategies such as prebuildup, flash-off techniques [19], or the DSI [20]. DSI allows doped SiGe layers with very sharp doping transitions over few decades. Elemental phosphorus cannot be used due to its high vapor pressure, which gives rise to high background contamination in an MBE system. For P-doping special sources exist. Possible realizations of such a source are an arch made of phosphorus-doped Si [21] or the doping from a GaP source [22]. Comparison with Sb-doping shows that the segregation behavior in the lower temperature regime is surprisingly similar. In the higher temperature regime, however, surface segregation of Sb is much stronger [5].

2.4.5 Substrate Heating and Cleaning The substrate temperature is one of the most important growth parameters because it influences all adatom processes of the surface, the crystalline growth, the surface morphology, the abruptness of doping transitions, and the relaxation processes in heterostructures. In an SiGe MBE, the substrate is heated radiatively from the backside by a current-powered meander. A typical construction is shown in Figure 2.4.6. The heater is made of meander-shaped pyrolytical graphite. A reflector ring under the substrate and the thickness profiling of the heater element guarantee a homogenous temperature distribution between room temperature and 10008C. A radiation shield of pyrolytical graphite minimizes the thermal losses. This construction is mounted in a water-cooled steel case with a tantalum heat shield in the inner part. The temperature of the graphite meander Tth is monitored by a thermocouple behind the heater. The substrate temperature is measured with a near-infrared pyrometer. The pyrometer measurement is used to calibrate the heater temperature. However, at the typical growth temperatures, only a small overlap of the spectral emission of the radiative heater and the spectral absorption of silicon is given. At 7008C, the maximum of the thermal radiation for a black emitter has a wavelength of 3 mm. In this wavelength range intrinsic silicon is transparent. The heating of substrate is caused mainly by radiative absorption of the free charge carrier. Figure 2.4.7 shows the temperature dependency of a high- and a low-doped substrate as a function of heater temperature measured with a pyrometer. For temperatures above 6508C no differences for this two types of substrates can be seen because the intrinsic carrier concentration in Si is 1018 cm3 at 7008C [23]. However, at lower heater temperatures, the temperature difference between high- and low-doped

Graphite meander Thermocouple

Radiation shields Substrate Reflector ring

FIGURE 2.4.6 Schematic view of a typical radiative heater system.

© 2006 by Taylor & Francis Group, LLC

2.4-92

The Silicon Heterostructure Handbook

Substrate temperature (⬚C)

900

800

700 p+−substrate 600

500 p−−substrate

400 400

500

600

700

800

900

1000

1100

Thermocouple temperature (⬚C)

FIGURE 2.4.7 Temperature dependency of a high- and low-doped substrate as a function of heater temperature measured with a pyrometer.

substrates increases. At Tth ¼ 5008C the difference is 40 K. The consequence is that different calibration curves for high- and low-doped substrates have to be used. High-quality growth needs interfaces with low contamination levels [24]; otherwise strain fields, dislocations, stacking faults, unintentional doping, and reduced carrier lifetimes may result. A very NH4OH and H2O2 HCl (RCA etch) common cleaning scheme employs an ex situ etch with H2O2 followed by an in situ heating at 8608C to 9008C. The thin protective oxide (SiO2) is desorbed as SiO after the reaction Si þ SiO2 ! 2SiO [25] has taken place during heating. Wafer manufacturers deliver their substrates already covered with the thin protective oxide. In an SiGe MBE system, the SiO2 layer is completely desorbed at substrate temperatures above 9008C [8]. If it is possible, the growth starts with an intrinsic Si buffer, which overgrows residual contaminations at the substrate interface such as carbon or SiC cluster.

2.4.6 In Situ Analysis Current process parameters are determined in an MBE system with different in situ analyzing methods such us vacuum monitoring, temperature monitoring and controlling, flux calibration and controlling, or the measurement of layer thickness. These parameters are used for process control or for regulating sources and substrate temperatures. High-temperature compatible thermocouples are used for measuring and controlling the temperatures of the effusion sources and the substrate. For the partial pressure analyzing a residual gas analyzer (RGA) is integrated in the growth chamber. This system consists of a QMS with multiplier. The RGA allows the monitoring of different residual species during the complete growth process. In modern SiGe systems, in situ flux monitoring of the matrix materials like Si and Ge can be performed by a mass spectrometer with Faraday cup detector. After calibration, the mass spectrometer signal gives directly the flux of the matrix materials and is used as a feedback parameter for controlling the EBEs. A multiplexer allows the control of the fluxes of two or more different masses simultaneously, for example, the mass number 30 for Si and 74 for Ge, which is used for the growth of Si SiGe structures. The flux measurement can also be performed with other methods such as quartz crystal resonators or electron-induced emission spectroscopy [26, 27].

© 2006 by Taylor & Francis Group, LLC

MBE Growth Techniques

2.4-93

Silicon ions from the EBE can be measured with a special ion detector [28]. This monitoring system measures the distribution of ion and electron densities over the substrate depending on the substrate voltage. Standard pyrometric measurements cannot be applied during film growth, since interference effects create artifacts and obscure the evaluation via Planck’s law. A combination of a pyrometer and a reflectometer will result in a real-time correction of emissivity «, thus allowing the determination of temperatures even for arbitrary multilayer stacks. This measurement method is called reflectionsupported pyrometric interferometry (RSPI) [29]. RSPI has been proven to be capable of providing in situ real-time information concerning temperature and film thickness for numerous applications in semiconductor manufacturing. Temperature measurements range from around 4508C to over 9008C with a resolution of about 0.18C. In the very low temperature regime (1508C to 4508C) the heater is calibrated with a Pt PtRh thermocouple incorporated in the substrate, and then operated with fixed heater power [30]. Reflection high-energy electron diffraction (RHEED) is an electron diffraction technique that can yield information on surface structure, cleanliness, smoothness, and growth rate [4]. It is particularly useful in MBE because of the determination of surface reconstruction, a re-ordering of the top atomic layer of the crystal by reducing the energy of the free surface.

2.4.7 Summary This chapter has presented an overview of topical SiGe MBE growth techniques. A wide substrate temperature regime (typically 1508C to 6008C) with low thermal budget, a simple in situ cleaning procedure, precise control of doping fluxes, doped heterostructures with abrupt profiles, and sophisticated in situ process monitoring are the main advantages of MBE. Several technical problems also have been discussed, for example, the influence of the epitaxial growth by the quality of the vacuum conditions or the dependence of substrate temperature from the substrate doping. A single Ge C source for MBE growth of C-doped SiGe base layers was presented. This source will considerably reduce the effort for carbon doping of MBE-grown HBT structures.

References 1. K. Eberl, R. Duschl, O. G. Schmidt, U. Denker, and R. Haug. J. Cryst. Growth 227 770 (2001). 2. F. Schaeffler. Semicond. Sci. Technol. 12 1515 (1997). 3. R.A.A. Kubiak, E.H.C. Parker, and S.S. Iyer. In Silicon Molecular Beam Epitaxy, E. Kasper and J.C. Bean, Eds. CRC Press, Boca Raton, FL (1988), p. 5. 4. M.A. Herman and H. Sitter. Molecular Beam Epitaxy. Springer-Verlag, Berlin (1996). 5. H. Jorke. In Properties of Silicon Germanium and SiGe:Carbon, E. Kasper and K. Lyutovich, Eds. INSPEC, Institution of Electrical Engineers, London, 2000, p. 287. 6. E. Kasper and H. Kibbel. Vac. Technol. 33 13 (1983). 7. E. Kasper, H. Kibbel, and F. Schaeffler. J. Electrochem. Soc. 136 1154 (1989). 8. E. Kasper, M. Bauer, and M. Oehme. Thin Solid Films 321 148 (1998). 9. T. Rupp, J. Messarosch, and I. Eisele. J. Cryst. Growth 183 99 (1998). 10. C.W. Pearce. In VLSI Technology, chapter 1, S.M. Sze, Ed. McGraw-Hill, Singapore (1983). 11. H. Jorke, H.-J. Herzog, and H. Kibbel. Appl. Phys. Lett. 47 511 (1985). 12. W.-X. Ni, G.V. Hannson, I.A. Buyanova, A. Henry, W.M. Chen and B. Momemar. Appl. Phys. Lett. 68 238 (1996). 13. M. Bauer, M. Oehme, K. Lyutovich, and E. Kasper. Thin Solid Films 336 104 (1998). 14. M. Oehme, M. Bauer, and E. Kasper. Mater. Sci. Eng. B89 332 (2002). 15. H. Ru¨cker, B. Heinemann, W. Ro¨pke, G. Fischer, G. Lippert, H.J. Osten, and R. Krups. Technical Digest, International Conference Simulates on Semiconductor Processes and Devices, IEEE, Piscataway, NJ, 1997, p. 281.

© 2006 by Taylor & Francis Group, LLC

2.4-94

The Silicon Heterostructure Handbook

16. R. Duschl, O.G. Schmidt, and K. Eberl. In Properties of Silicon Germanium and SiGe:Carbon, E. Kasper and K. Lyutovich, Eds. INSPEC, Institution of Electrical Engineers, London (2000), p. 158. 17. H.J. Osten, G. Lippert, P. Gaworzewski, and R. Sorge. Appl. Phys. Lett. 71 1522 (1997). 18. K. Eberl, S.S. Iyer, S. Zollner, J.C. Tsang, and F.K. Legoues. Appl. Phys. Lett. 60 3033 (1992). 19. S.S. Iyer, R.A. Metzger, and F.G. Allen. J. Appl. Phys. 52 5608 (1981). 20. H. Jorke and H. Kibbel. J. Electrochem. Soc. 133 774 (1986). 21. E. Friess, J. Nu¨tzel, and G. Abstreiter. Appl. Phys. Lett. 60 2237 (1992). 22. R. Duschl, O.G. Schmidt, G. Reitemann, E. Kasper, and K. Eberl. Electron. Lett. 35 1111 (1999). 23. S.M. Sze. Physics of Semiconductor Devices. Wiley Interscience, New York (1969), p. 28. 24. P.J. Grunthaner. Thin Solid Films 183 197 (1989). 25. S.T. Ahn, H.W. Kennel, W.A. Tiller, and J.D. Plummer. J. Appl. Phys. 65 2957 (1989). 26. C.A. Gogol and C. Cipro. Electrochem. Soc. Proc. 85 415 (1985). 27. R.A. Kubiak, S.M. Newstead, A.R. Powell, E.H.C. Parker, T.E. Whall, T. Naylor, and K. Bowen. J. Vac. Sci. Technol. 9 2423 (1991). 28. G. Eifler, E. Kasper, Kh. Ashurov, and S. Morozov. J. Vac. Sci. Technol. A 20 945 (2002). 29. H. Mo¨ller, F.G. Bo¨bel, B. Hertel, T. Lindenberg, and G. Ritter. J. Cryst. Growth 157 327 (1995). 30. M. Bauer, M. Oehme, M. Sauter, G. Eifler, and E. Kasper. Thin Solid Films 369 228 (2000).

© 2006 by Taylor & Francis Group, LLC

2.5 UHV/CVD Growth Techniques 2.5.1 2.5.2 2.5.3 2.5.4

Thomas N. Adam IBM Semiconductor Research and Development Center

2.5.5 2.5.6

Introduction................................................................. 2.5-95 Chemistry..................................................................... 2.5-96 Low Temperature and Low Pressure ......................... 2.5-98 Alloys, Doping, and Selective Epitaxial Growth ......................................................................... 2.5-99 Substrate Cleaning..................................................... 2.5-101 Reactors ...................................................................... 2.5-103

2.5.1 Introduction The aggressive scaling of silicon-based high-performance integrated circuits [1] has led to device dimensions and junction depths that require ultralow thermal processing budgets. For example, stateof-the-art CMOS gate lengths have shrunk below 100 nm over the past few decades. The current International Technology Roadmap for Semiconductors (ITRS) projects physical gate lengths in microprocessors and ASICs of 40 nm in the near future and 10 nm beyond 2015. Without considering suppression and enhancement effects, such as substitutional carbon or transients, the classical pffiffiffiffiffiffi dopant diffusion alone (e.g., boron: D0
0.67 cm2/sec, EA
3.46 eV [2]) exhibits comparable 2 Dt values at 9008C for minute-scale durations. Growth techniques that employ low temperatures (7008C) for homo- and hetero-epitaxy are necessary to maintain abrupt doping profiles and prevent, nearly eliminate, dopant and alloy diffusion, especially in high-performance BiCMOS integration schemes. In particular, pseudomorphically grown silicon–germanium has emerged as an important alloy due to its bandgap properties and strain-induced effects on carrier mobility [3]. Among others, substratecompliant epitaxial SiGe is utilized in the fabrication of heterojunction diodes [4], resonant tunneling diodes [5], heterojunction bipolar transistors [6], modulation-doped field-effect transistors [7], MOS field-effect transistors [8], and photodetectors [9]. Today, the most commonly employed lowtemperature epitaxial deposition methods are molecular beam epitaxy (MBE) [10], gas-source MBE (GSMBE) [11], and chemical vapor deposition (CVD) [12]. The deposition using chemical vapors is practical in a commercial manufacturing environment because it offers high wafer-throughputs by batch processing, outstanding film uniformities, excellent control over alloy composition and dopant concentration, and selective epitaxial growth. However, chemical vapor deposition at atmospheric pressures and in low vacuum was traditionally restricted to high substrate temperatures. Although improvements in gas purity, chamber cleanliness and design, precursor chemistry, and interface cleanliness soon enabled further temperature reductions, only a concurrent and significant reduction in deposition pressure provided the key to defect-free low-temperature epitaxy and manufacturing-friendly batch processing of silicon and silicon–germanium [13, 14]. In this chapter, ultrahigh vacuum chemical vapor deposition (UHV/CVD) is compared to other silicon and silicon–germanium epitaxial deposition methods with emphasis on the ultralow temperature 2.5-95 © 2006 by Taylor & Francis Group, LLC

2.5-96

The Silicon Heterostructure Handbook

regime below 7008C and on 200 to 300 mm substrate size. Substrate surface cleaning and advantages and drawbacks of UHV/CVD are discussed.

2.5.2 Chemistry The deposition of Si and SiGe from chemical vapors is based on the thermal decomposition of appropriate precursors (pyrolysis), most commonly silanes (SiH4, Si2H6, Si3H8, etc.) or chlorosilanes, and germanes (GeH4, Ge2H6, etc.) or chlorogermanes. Diluted (He, H2, or N2 [15]) or undiluted precursors are introduced into a closed system via gas injectors to form a well-controlled gas stream with flow dynamics that are engineered to prevent turbulences and uniformly deliver precursors. The wafer is placed into the gas stream and heated to temperatures at which chemical reactions occur with the transported gas molecules. In general, a reactor may be of batch-type (boat, barrel, platen, etc.) or single-wafer design, while the process of CVD is traditionally divided into pressure regimes, such as atmospheric-pressure CVD (APCVD: 760 Torr), reduced-pressure CVD (RPCVD:
1 to 100 Torr), lowpressure CVD (LPCVD:
100 mTorr to 1 Torr), and UHV/CVD (102 to 104 Torr). Wafer heating is achieved by lamp arrangements or resistive coils, and samples are placed either on flat susceptors, pins, or in boats. Doping is realized by adding gaseous dopant compounds, such as diborane, phosphine, arsine, etc. to the precursor–carrier-gas mix. The overall reaction is commonly described in steps: (a) decomposition of precursors in the gas phase, (b) mass transport of precursors and by-products from the gas stream to the substrate surface, (c) adsorption at the surface, (d) surface diffusion, (e) dissociation, reaction, and bonding with surface atoms, and (f) desorption of by-products and excess precursors into the gas stream. Depending on the process pressure, substrate temperature, reactor design, and choice of precursor mixture, different steps may emerge as the rate-limiting mechanism. In the remainder of the chapter, the UHV low-temperature reaction-limited silane (disilane) deposition characteristics are discussed in detail. In this low-pressure, low-temperature extreme, gas-phase reactions can be neglected. An excellent introduction to UHV/CVD and its applications can be found in Refs. [12, 13]. During the thermal decomposition of silanes on single-crystalline silicon surfaces, various reaction pathways are feasible, involving different simple and multistep hydrogen and group dissociations and trapping. A description of the exact reaction kinetics is beyond the scope of this chapter and the reader is referred to published theories such as the transition state theory (TST) [16], Rice–Ramsperger–Kassel– Marcus (RRKM) [17], or quantum-Ramsperger–Kassel–Marcus (QRKM) theory [18]. Competing temperature and pressure-dependent adsorption, decomposition, and desorption rates of precursor and intermediate molecules complicate an accurate prediction of growth rate and morphology. However, various research groups have found that the primary adsorption species upon exposure of Si (1 0 0) H, with small amounts of SiH2 [19], while Si2H6 adsorbs to SiH4 at low temperatures were SiH3 and Si and reacts mainly by breaking the Si Si bond to form SiH3 fragments, which readily bond to the surface sites [20, 21]. low T

2SiH4 ðgasÞ ! 2SiH3 (ads) þ 2H(ads) for silane low T

Si2 H6 ðgasÞ ! 2SiH3 (ads) for disilane low T

2SiH3 ðadsÞ ! [ H Si Si H ] þ 2H2 (gas)

(2:5:1) (2:5:2) (2:5:3)

In Equations (2.5.1) to (2.5.3), ‘‘ads’’ denotes adsorption, while / and \ indicate bonds to the bulk silicon. As lumped into Equation (2.5.3), the pyrolysis of silane and disilane can be conceptionalized as a series of detachments of atomic hydrogen from the precursor molecule adsorbing on dangling bonds, and H coadsorption, with eventual release of molecular hydrogen. The individual reactions can be traced in vacuum by temperature-programmed desorption (TPD), spectroscopy, RHEED observations, STM, or

© 2006 by Taylor & Francis Group, LLC

2.5-97

UHV/CVD Growth Techniques

ellipsometry. It was shown on an atomic scale by real-time STM that, upon heat treatment, the two nearest neighboring atoms of a clean hydrogen-terminated (1 0 0) silicon surface pair up under hydrogen desorption to form monohydride dimers (bracketed term in Equation (2.5.3)). Dimerization was found to reduce the number of dangling bonds and surface energy [22], giving rise to threedimensional growth. Additionally, this pairing materialized in a well-defined row configuration [23] with rows terminated where atomic steps occurred. As a consequence of the tetragonal bonding nature of silicon, the subsequent atomic layer has dimer rows oriented perpendicular to the previous set of rows. Epitaxy from silanes on monohydride dimer surfaces at low temperatures requires breaking the dimer bond to supply the necessary number of dangling bonds. STM studies revealed different growth modes in the low-temperature regime depending on the exact substrate temperature and amount of precursor exposure, although in most of these studies, disilane rather than silane was used due to a higher sticking coefficient [21]. The reduction of adatom surface mobility at low temperatures suppressed step-flow growth and caused island nucleation and partial passivation, although multilayer growth was still observed [24]. The findings suggest that very low temperatures (<5008C) not only cause drastically reduced growth rates but also result in increased film disorder and roughness, a concern for ultralow temperature epitaxy. The desorption of hydrogen — the primary reaction by-product — from the surface silicon bonds is thermally activated with energies reported between 2.04 and 2.47 eV [16, 25, 26], while the precursor bond-dissociation energies of Si Si, Si C, Si H, and Si Cl bonds were measured ranging between 2.95 eV (Si4H10) and 4.81 eV (SiCl4) [27]. The adsorption (‘‘sticking’’) coefficients of silane, disilane, and trisilane molecules under UHV conditions were found to be dissimilar but only weakly temperaturedependent [28]. It is therefore generally accepted that the desorption of hydrogen is the rate-limiting step at sufficiently low temperatures. This yields the well-observed linear relationship between logarithmic growth rate and inverse temperature in a classical Arrhenius plot, such as depicted in Figure 2.5.1. Epitaxial silicon deposition rates are plotted for RPCVD, LPCVD, and UHV/CVD compiled from published silane data with the remarkable result, that independent of process pressure, precursor dilution, and reactor design, the hydrogen desorption is the apparent absolute limitation in growth rate. Care was taken to compare only true crystalline epitaxial growth. As published by Beers and Bloem

Epitaxial silicon growth rate (Å/min)

800

700

T(⬚C) 600

500 LEPE

103 6 mTorr 102 3 mTorr 0.3 mTorr

101 RP 100

10−1 9

LP 10

11 12 1/T (10,000/K)

13

14

FIGURE 2.5.1 Arrhenius plot of the epitaxial silicon deposition rate as a function of inverse temperature. Only single-crystalline film growth based on diluted and undiluted silane is compared. Representative values published for RPCVD ( [15], " [52]), LPCVD (& — batch-type hot-wall reactor, data provided by A. Little (Kokusai USA, www.ksec.com) and M. Miyamoto (Japan, www.h-kokusai.com) — personal communication), UHV/CVD ( , * [26], [35], $ [37], ^ [40], and ~ [64]), and low-energy plasma-enhanced (LEPE) CVD ( [31]) are included as closed symbols and dotted lines. Open circles denote values obtained employing a UHV/CVD batch reactor.

© 2006 by Taylor & Francis Group, LLC

2.5-98

The Silicon Heterostructure Handbook

[29], silane pyrolysis can be driven into higher deposition rate regimes, but the deposited films were polycrystalline or amorphous. It is understood that this may be due to insufficient surface diffusion of the adsorbed SiHx species to find energetically favorable bonding positions at high deposition rates. UV assistance [30] and more recently, plasma enhancement [31] were demonstrated to boost growth rates while retaining crystallinity due to enhanced precursor gas-phase dissociation, stimulated surface migration, and promoted hydrogen desorption.

2.5.3 Low Temperature and Low Pressure As invented by Meyerson [14], UHV/CVD is performed at pressures of 102 to 104 Torr, while maintaining background pressures of less than 108 Torr. To achieve ultimate background pressures in the UHV range, prevent hydrocarbon backstreaming, and allow unthrottled pressure equilibration in the low-milliTorr range for typical process gas flows (below 200 sccm); the use of turbopumps backed by a stack of rootsblower and mechanical pumps is typically required. If necessary, higher deposition pressures can be accomplished using a throttle valve coupled to a closed-loop pressure control circuit. The use of low process pressures has various favorable consequences. The rate of precursor gas-phase decomposition in the heated reactor volume is significantly reduced, as it is linearly dependent on precursor pressure below 10 Torr [13]. Therefore, thickness nonuniformities originating from spatial variations in silane concentration (and its fragments) are prevented. Undiluted and carrier-gas-free precursors are typically used, which reduces gaseous contamination, such as water vapor, unintentionally introduced by large amounts of carrier gases in other pressure regimes. Of course, contamination is also present in precursors but their partial pressure is well below the values detrimental for epitaxy [32, 33]. It is interesting to note that for a given temperature, precursor-to-layer conversion efficiencies in UHV/CVD, i.e., the number of Si atoms deposited (including tube and boat) per number of silane molecules admitted per minute, remain comparable to those of optimized carrier-gas-based regimes, such as RP or LPCVD. Furthermore, the mean-free path of the precursor molecules at 102 to 104 Torr is tens of centimeters and compared to higher pressure regimes, gas-flow dynamics are simple and without convectional effects. Combined with a small sticking coefficient of silane and long reactor residence times, this results in a homogeneous precursor delivery to all exposed vacuum surfaces and holds great potential for uniform deposition rates in batch-type reactors. Contamination originating from the reactor’s inner periphery is minimized by evacuating the chamber to UHV pressures. Some contamination of the wafer surface from a finite vacuum is unavoidable but can be mitigated by flushing with inert gases during wafer loading and unloading, provided that the reactor leak rate is larger than the rate at which contamination is introduced by the flush gas. The value of necessary background pressure before growth is governed by required minimum partial pressures of O2 and H2O at the target growth rate and temperature [32, 33]. Typically, chamber pressures in the mid-109 Torr range were sufficient for a wide range of substrate temperatures as partial pressures of contaminants were then in the 1011 Torr range, measured using a residual gas analyzer. Pressures in the mid-108 Torr range proved satisfactory for higher temperatures and faster growing SiGe. The clean reactor environment, in turn, enables an extended range of growth temperatures. Very low growth rates of silicon and silicon–germanium (below 1 A˚/min) at ultralow temperatures are thus feasible. Temperatures as low as 4508C were demonstrated to yield clean epitaxial silicon films employing purified silane [26]. However, without substrate rotation and modified gas injection systems, temperatures in excess of 6008C to 6508C can cause substantially degraded thickness uniformities due to gas depletion in the reactor (transport-limited regime). As depicted in Figure 2.5.2 for different substrate temperatures, a saturation of silane-based growth rate occurs in UHV/CVD reactors at low temperatures and pressures, and at lowest temperatures only slightly increasing growth rates were observed with increasing silane pressures. In contrast, no saturation was observed for comparable partial pressures of silane at much higher total pressures. A strong dependence on flow rate (or pressure) is indicative of gas depletion across the reactor, boat, and wafer and results in degraded within-wafer and

© 2006 by Taylor & Francis Group, LLC

2.5-99

UHV/CVD Growth Techniques

104

103

,9 0

0⬚ C

494

2T

750⬚C

102

470

600⬚C

T, 6

510⬚C

00

⬚C

550⬚C 101

40

Epitaxial silicon growth rate (A/min)

Boat

100

10−5

10−4 10−3 10−2 10−1 Silane pressure (Torr)

Top 100

FIGURE 2.5.2 Epitaxial silicon growth rate as function of (partial) silane pressure in UHV/CVD (solid lines: & [36,37], * [37], and ^ [65]) and RPCVD reactors (dotted lines: ~ [15], ! [66]). Steep lines indicate a strong dependence on partial pressure and are undesirable for batch-type configurations. Gas depletion over the wafer and boat can spatially modify the precursor partial pressure, and thus, create deposition inhomogeneities. Best uniformities are obtained using lowest temperatures and undiluted precursors.

−100−80 −60 −40 −20 0 20 40 60 80 100 x (mm)

FIGURE 2.5.3 Silicon thickness contour plot of the center wafer deposited in a low-temperature UHV/ CVD batch reactor. The target thickness was 500 A˚ and local maximum and minimum values are included (in A˚). A total temperature variation of 2.888C across the wafer (2 mm edge exclusion) was inferred from thickness variations obtained using spectroscopic ellipsometry. The orientation of the wafer inside the reactor, i.e., top and bottom (boat), is indicated. The small offset between the wafer and measurement grid was caused by automated stepping with disabled pattern recognition.

within-boat thickness uniformities (transport-limited operation). Operating the reactor in saturation (reaction-limited deposition) ensures excellent uniformities, and one-sigma wafer-to-wafer, withinwafer, run-to-run, and tool-to-tool variations of germanium fractions in SiGe within the range of 3% to 4% and of combined Si and SiGe thicknesses within the range of 1% to 3% are typically achieved in 200 mm UHV/CVD batch reactors. However, intrinsic silicon thickness maps of the center wafer, as displayed in Figure 2.5.3 revealed radially increasing values that were eccentric relative to the wafer and wafer-boat geometry but concentric relative to the reactor–heater axis, in addition to locally modified thicknesses in the vicinity of the structural support from the boat, totaling
6.1% variation. Combined with the measured activation energy and preexponential factor of silane-based silicon epitaxy in the same reactor (
1.74 eV and 7.5  1011 A˚ /min), a total temperature variation across the center wafer of
1.888C was inferred from these measurements. It is apparent that good thickness uniformities and repeatability in UHV/CVD reactors therefore require superior temperature uniformities and stabilities as they are exponentially connected, while precursor delivery is intrinsically simple and noncritical. In contrast, uniformity in mass-transport-limited silicon epitaxy at higher substrate temperatures (most APCVD, RPCVD, and LPCVD reactors) is strongly dependent on even precursor delivery.

2.5.4 Alloys, Doping, and Selective Epitaxial Growth Pseudomorphic alloys of silicon with other group IV elements, such as germanium and carbon, have gained much attention due to bandgap engineering, strain effects, and suppression of dopant diffusion. Epitaxial UHV/CVD of SiGe is typically achieved by adding diluted germane or digermane to the precursor gas flow. However, as depicted in the inset of Figure 2.5.4, the germanium fraction and SiGe deposition rate are nontrivial functions of flow rate (pressure) and substrate temperature, although the Ge fraction appears less sensitive to temperature changes. For batch reactors, the values of listed wafer

© 2006 by Taylor & Francis Group, LLC

2.5-100

The Silicon Heterostructure Handbook

1020

1018 1017 1016 1015 0.1

40 30 20 10 0 0

1 2 3 4 5 Flow of GeH4 (%)

Log. rate (A/min)

1019

Ge (%)

Boron concentration (cm−3)

1021

1 10 Diborane flow (sccm)

FIGURE 2.5.4 Boron concentration in films of silicon ( ) and SiGe ( ) as a function of B2H6 flow (1000 ppm in He) in a UHV/CVD batch reactor, determined by SIMS measurements. The inset depicts the germanium fraction and logarithmic SiGe growth rate in the same batch-reactor as a function of germane flow percentage in SiH4 þ GeH4 þ He for 5258C (dotted lines and diamonds) [40] and 5108C (solid lines and circles). Germanium fractions and layer thicknesses were extracted using XRD, SIMS, Auger, and spectroscopic ellipsometry. Ge fractions between 0% and 25 % appear much less sensitive to temperature variations.

temperature are somewhat arbitrary as large errors may be caused by sensing the vessel temperature using spring-loaded thermocouples. Even if the reactor wall temperature was known with sufficient accuracy, actual wafer temperatures are expected to be several degrees lower. Absolute temperature calibration to growth rates using standard silane flows and pressures should be employed to establish grounds for comparison and repeatability. In single-wafer tools, thermocouples can be placed in direct contact to or within the immediate vicinity of the wafer. Furthermore, eutectic reactions, such as with Au, may be observed through view ports in order to calibrate to the true wafer surface temperature. In general, the addition of GeH4 increases the growth rate [13, 34]. This is believed to occur due to a reduced hydrogen desorption activation energy for Ge H (
1.6 eV) as compared to Si H (
2.0 eV), and a lower binding energy of Ge H (
3.1 eV) compared to Si H (
3.4 eV) [16]. Depending on the substrate temperature, the growth rate of SiGe may reach values that are several times larger than that of silicon. As a consequence, care must be taken to avoid gas-depletion effects at low process pressures, i.e., silane flows. In principle, Si1–xGex with compositions between x ¼ 0% and 100% are attainable by adjusting the flows of silane and germane. However, for increasing germanium fractions, both the apparent and metastable critical thicknesses reduce accordingly [40]. The use of low temperatures during growth, as enabled by UHV/CVD, is expected to result in better alloy metastability because relaxation (dislocation nucleation and glide) exhibits stronger thermally activated behavior as compared to growth (EA
4.2 to 4.75 eV [35]). Low deposition rates also ensure exceptional profile control, repeatability, and atomic abruptness while at the same time, yielding excellent uniformities in batch-type reactors. Sophisticated germanium, carbon, and dopant profiles, such as polynomial or exponential ramps, can be obtained by dynamic (time-dependent) programming of massflow controllers. Typical n-type (p-type) dopants for silicon- and silicon–germanium-based devices are phosphorous, arsenic, and antimony (boron and gallium). B2H6, PH3, AsH3, and also SbH3 are dopant compounds that are employed in chemical vapor deposition. It is generally accepted that the use of low temperatures (<6008C) results in (nearly) complete dopant activation in as-grown films over a wide range of concentrations, eliminating the need for high-temperature annealing steps. Furthermore, dopant diffusivities in both silicon and silicon dioxide are strongly dependent on temperature, with activation energies (3.4 to 4.2 eV in c-Si, 2.4 to 3.9 eV in poly-Si, and 1.3 to 4.7 eV in SiO2 [2]) that are generally much larger than that of epitaxial growth (1.5 to 2.1 eV for silane-based growth [13, 26, 36] and
1.5 eV

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-101

for disilane-based growth [30, 37]). Therefore, dopant diffusion is nearly eliminated for growth temperatures below 6008C and typical deposition durations. However, the incorporation of dopants is dependent on various factors, such as temperature, precursor, chamber environment, and of course gas flow. Not all gaseous dopant sources allow abrupt profiles and high concentrations, even at low substrate temperatures. For example, PH3 and AsH3 have been shown to be unstable at high concentrations during silicon epitaxy [13, 38] and concentration transients after switching the gas flow were detected in RPCVD, LPCVD, and UHV/CVD during silane-based growth. Segregation and surface poisoning were observed for these dopant sources. Phosphine stabilized in SiGe, and also, by using a Cl-containing chemistry that was argued to be caused by an enhanced desorption of P from the surface and formation of volatile phosphorous chlorides at higher temperatures. In addition, when disilane rather than silane was used, the surface saturation and doping transition effects were mitigated [37] possibly due to a higher reactivity and sticking coefficient of Si2H6. A small growth rate reduction was observed for phosphorous-doping in silane and disilane. In contrast, boron incorporation is abrupt and stable at low deposition temperatures [39]. No change of concentration over time was observed during growth, except when boron was incorporated into SiGe. Although no ‘‘memory effect’’ was detected, a steady increase of concentration in SiGe and subsequent decrease in Si were observed by Lafontaine et al. [40]. The authors argued that this may be due to increased boron adsorption in the presence of germane. No noticeable change in growth rate was observed when adding B2H6 to silane [39] while disilane-based boron-doping exhibited a considerable enhancement of growth rate [37]. As depicted in Figure 2.5.4, high boron concentrations and large dynamic doping ranges are achievable in UHV/CVD. Selective epitaxial growth (SEG) during CVD is achieved by adding an appropriate amount of hydrochloric acid to the precursor mixture, which prevents nucleation on oxide and nitride by etching. This method enables the selective intrinsic and in situ doped Si and SiGe epitaxy for arbitrary thicknesses. However, temperatures in excess of 7008C are typically required because the addition of HCl suppresses Si and SiGe growth rates [41]. More recently, low-temperature thickness-limited incubation-time-based SEG has regained attention due to less required total thicknesses and stricter thermal processing budgets in high-performance integration schemes. Kiyota et al. demonstrated SEG at temperatures as low as 6608C using dichlorosilane in LPCVD [42]. Up to 3000 A˚ of Si–SiGe were selectively deposited employing the incubation period of poly-Si–SiGe on SiO2. The authors postulated that the chlorine content in SiH2Cl2 was still somewhat responsible for nuclei etching. Later, the concept of nucleation delay was extended to UHV/CVD in order to further reduce deposition temperatures. Typically, several hundred angstroms of SEG can be achieved in UHV/CVD using Cl-free silane or disilane precursor mixtures, and temperatures as low as 5508C have been demonstrated thus far for an 850 A˚ epi-base in self-aligned HBTs [43]. However, this process is not expected to be 100% selective, and small and isolated nuclei may be found on oxide and nitride areas.

2.5.5 Substrate Cleaning An oxygen- and carbon-free substrate surface is essential for smooth, single-crystalline, and defect-free epitaxy. As much as one monolayer of residual surface oxide can cause polycrystalline or amorphous rather than single-crystalline film growth. Interface contamination gives rise to increased film surface roughness and various crystal defects. Although the exact mechanism is unclear, it is argued that surface contamination reduces the diffusivity of adsorbed SiHx species [44], thus resulting in an increased initial three-dimensional growth. Boron surface contamination commonly occurs as a result of wafer handling in air, while oxide forms by reacting with oxygen and H2O vapor during transport in air and water rinses. Carbon is found as contamination in native oxide and processing liquids, such as hydrofluoric acid or DI-water. ‘‘Backstreaming’’ hydrocarbons originating from hot and turbulent pump oils can cause significant accumulation of carbon on silicon substrates processed in vacuum equipment. Other organic and metal impurities are typically found on the wafer surface after polishing steps, lithography, storage in plastic containers, and handling in air [45].

© 2006 by Taylor & Francis Group, LLC

2.5-102

The Silicon Heterostructure Handbook

Nayak et al. [44] have observed with in situ RHEED and AFM that islands evolve which grow in size during the initial stages of low-temperature growth on contaminated silicon surfaces. Upon further growth, these three-dimensional structures coalesce, and proceed as a disordered 2  1 reconstruction, but free of contamination. They concluded that cleaner interfaces yield smoother and more ordered film growth. Particularly, the pseudomorphic growth of strained layers (SiGe on Si, Si on relaxed SiGe) is affected by interfacial contamination due to enhanced dislocation nucleation [46] and threedimensional growth, visible under the microscope as haze, pitting, or islands. In the past, traditional substrate cleaning involved a combination of ex situ wet chemical etching and in situ high-temperature bake. In a production environment, the ex situ wet chemical clean typically employs an RCA-type procedure [47, 48]. Briefly, a solvating and oxidizing base mixture removes organic, particle, and some metals contamination. It is followed by an oxidizing acid-based solution in which metal contaminants are converted to soluble complexes. After rinsing, the wafers are then immersed in an HF solution to remove the surface oxide and terminate dangling silicon bonds with atomic hydrogen. This procedure has proven to result in a surface that is stable in air against re-oxidation for several minutes [13], with less than 1% coverage with residual oxygen, carbon, and boron (typical interface doses in the mid1012 cm2). The surface can be purified further employing in situ cleans. Most commonly, hightemperature bakes in a reducing atmosphere or vacuum are used. Hydrogen bakes have been reported to be effective only at temperatures above 7508C [41, 49–52] for durations of 30 sec to several minutes. HCl-based etching produces clean and smooth surfaces employing comparable temperatures [45, 53]. Vacuum bakes are typically performed in two steps. A first step at temperatures of 2508C to 2758C desorbs carbon [54], while a subsequent high-temperature bake at 6308C to 13508C for 30 sec to several minutes removes surface oxide [11, 21, 24, 28, 32]. High-temperature in situ precleans of this type are based on the reduction of SiO2 to volatile SiOx compounds. In vacuum bakes, this reduction is achieved by thermal diffusion of oxygen into the underlying substrate, while hydrogen atmosphere also promotes the reduction of the surface oxide to suboxide and water vapor. Lower substrate cleaning temperatures have been achieved employing controlled exposures to Ga molecular beams, where volatile mixed-oxide compounds were formed, which desorbed at temperatures as low as 8008C. Although clean surfaces were produced [55], applicability is limited to MBE or other ultrahigh vacuum single-wafer deposition methods. Morar et al. have shown that a submonolayer coverage of germanium yielded nonstoichiometric germanium-oxides, which desorbed at temperatures as low as 6258C [56], and proposed a low-temperature CVD batch-compatible oxide removal based on brief germane exposures. Similarly, the addition of small amounts of disilane during thermal annealing accelerates the surface oxide decomposition, and annealing temperatures as low as 7808C were successfully demonstrated [57]. Recently, ultralow temperature in situ cleans were developed, such as HF-vapor [58], downstream [59], or plasma-based cleaning. Hydrogen ECR cleaning was demonstrated to be effective in reducing interfacial contaminants at temperatures between room temperature and 6008C [60], while low-energy argon [61] and argon–hydrogen [31] ion bombardment at temperatures below 3008C and 1008C, respectively, yielded defect-free crystalline growth and proved successful in removing molecular contamination. However, higher ion energies, though more effective in removing contamination, resulted in increased surface roughness and argon incorporation [62]. Ma et al. suggested the use of broadband UV radiation in combination with O2 and Cl2 to react adsorbed hydrocarbons and metal contamination to carbon dioxide, water vapor, and volatile metal chlorides, at temperatures below 2508C [63]. The choice of a particular substrate cleaning method is dependent on various process parameters, such as allowable thermal budget, type of available reactor, or tolerable interface dose and surface roughness. For example, a production-environment hot-wall batch-type low-temperature UHV/CVD system cannot be thermally cycled due to time constraints and long-term tube integrity concerns. Therefore, high-temperature in situ precleans are not feasible, unless arranged in a cluster configuration. However, single-wafer UHV/CVD reactors can be equipped with a variety of cleaning accessories.

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-103

2.5.6 Reactors As discussed in the previous section, the use of low processing pressures and substrate temperatures during UHV/CVD permits excellent uniformities in Si and SiGe layer thickness and composition, reduces thermal dopant diffusion, and maximizes as-grown dopant electrical activation. Autodoping is minimized so that ultra-shallow and hyperabrupt junctions and alloy profiles can be formed without growth interruption. Among others, applications include high-performance SiGe heterojunction bipolar transistors, tunneling diodes, and quantum wells. To date, a variety of single-wafer and batch-type reactors are available for substrates up to 200 mm in size. They are generally constructed of stainless steel (cold-wall) or quartz-glass (hot-wall) chambers, which are evacuated to UHV pressures (<108 Torr) by turbopumps and a combination of rootsblower and mechanical pumps. In order to preserve a clean growth environment, the reactors are equipped with UHV-capable load locks and ultrapure precursor, doping, and flush gases are introduced using massflow controllers. Currently, 300 mm tools are predominantly of single-wafer type. Besides cost-related issues, incorrigible temperature gradients across the wafer and excessive chamber sizes may complicate the development of 300 mm reactors to batch-type systems. Single-wafer systems are appropriate for research and development purposes and various aspects are attractive for a manufacturing environment. For example, in situ wafer and chamber precleaning, wafer temperature sensing and uniformity by heater zoning, dynamic temperature control, substrate rotation, in situ film measurements (ellipsometry, interferometry, or spectroscopy), and advanced gas injection systems promise better repeatability, control, and tool failure rates. However, large-scale manufacturing generally requires wafer throughput values that cannot be matched using single-wafer platforms, unless profit margins allow the purchase and operation of multiple tools.

Acknowledgments I would like to acknowledge the team of scientists, engineers, analysts, and technicians at IBM for their open and interdepartmental support. In particular, I would like to thank Paul Ronsheim, Andy Turansky, Harry Hovel, and Anita Madan for outstanding analytical work and leading edge film characterization, and Joseph Kocis and David Rockwell for processing support. Furthermore, I am grateful to Toshiaki Yanagisawa, Huajie Chen, Basanth Jagannathan, Jack Chu, Kevin Chan, Ryan Wuthrich, and Wade Hodge for technical assistance and many fruitful discussions on the various details of UHV/CVD. I wish to thank my colleagues in the BiCMOS and SiGe Technology Development department for help and encouragement, and Dave Ahlgren and Ken Stein for managerial support.

References 1. J.S. Dunn, D.C. Ahlgren, D.D. Coolbaugh, N.B. Feilchenfeld, G. Freeman, D.R. Greenberg, R.A. Groves, F.J. Guarı´n, Y. Hammad, A.J. Joseph, L.D. Lanzerotti, S.A. St.Onge, B.A. Orner, J.-S. Rieh, K.J. Stein, S.H. Voldman, P.-C. Wang, M.J. Zierak, S. Subbanna, D.L. Harame, D.A. Herman Jr., and B.S. Meyerson. IBM J Res Dev 47: 101–139, 2003. 2. S.M. Sze. VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988. 3. P.M. Garone, V. Venkataraman, and J.C. Sturm. IEEE Electron Dev Lett 13: 56–58, 1993. 4. T.G. Jung, C.Y. Chang, C.S. Liu, T.C. Chang, H.C. Lin, W.C. Tsai, G.W. Huang, and L.P. Chen. J Appl Phys 76: 4921–4923, 1994. 5. L.-E. Wernersson, S. Kabeer, V. Zela, E. Lind, J. Zhang, W. Seifert, T. Kosel, and A. Seabaugh. Electron Lett 40: 83–85, 2004. 6. P.S. Chen, Y.T. Tseng, M.-J. Tsai, and C.W. Liu. Semiconductor Manufacturing Technology Workshop, December 10–11, 2002, pp. 145–148. 7. W. Lu, A. Kuliev, S.J. Koester, X.-W. Wang, J.O. Chu, T.-P. Ma, and I. Adesida. IEEE Trans Electron Devices 47: 1645–1652, 2000.

© 2006 by Taylor & Francis Group, LLC

2.5-104

The Silicon Heterostructure Handbook

8. Y.M. Lin, S.L. Wu, S.J. Chang, S. Koh, and Y. Shiraki. IEEE Electron Dev Lett 24: 69–71, 2003. 9. A. Gupta, S.P. Levitan, L. Selavo, and D.M. Chiarulli. Proceedings of 17th International Conference on VLSI Design, 2004, pp. 957–960. 10. J. Kolodzey, P.R. Berger, B.A. Orner, D. Hits, F. Chen, A. Khan, X. Shao, M.M. Waite, S.I. Shah, C.P. Swann, and K.M. Unruh. J Cryst Growth 157: 386–391, 1995. 11. T.R. Bramblett, Q. Lu, T. Karasawa, M.-A. Hasan, S.K. Jo, and J.E. Greene. J Appl Phys 76: 1884– 1888, 1994. 12. B.S. Meyerson. Appl Phys Lett 48: 797–799, 1986. 13. B.S. Meyerson. Proc IEEE 80: 1593–1608, 1992. 14. B.S. Meyerson. U.S. Patent 5,906,680, 1999. 15. P. Meunier-Beillard, M. Caymax, K. Van Nieuwenhuysen, G. Doumen, B. Brijs, M. Hopstaken, L. Geenen, and W. Vandervorst. Appl Surf Sci 224: 31–35, 2004. 16. M. Hierlemann and C. Werner. Mater Sci Sem Proc 3: 31–39, 2000. 17. P.J. Robinson and K.A. Helbrook. Unimolecular Reactions. New York: Wiley Interscience, 1972. 18. A.M. Dean. J Phys Chem 89: 4600–4608, 1985. 19. S.M. Gates, C.M. Greenlief, S.M. Kulkarni, and H.H. Sawin. J Vac Sci Technol A 8: 2965–2969, 1990. 20. S. Hong and M.Y. Chou. Phys Rev B 58: R13363–R13366, 1998. 21. P.-H. Wu and D.-S. Lin. Phys Rev B 57: 12421–12727, 1998. 22. W.K. Liu, S.M. Mokler, N. Ohtani, C. Roberts, and B.A. Joyce. Surf Sci 264: 301–311, 1992. 23. A.R. Laracuente and L.J. Whitman. Surf Sci 545: 70–84, 2003. 24. J.J. Boland. Phys Rev B 44: 1383–1386, 1991. 25. K. Sinniah, M G. Sherman, L.B. Lewis, W.H. Weinberg, J.T. Yates, and K.C. Janda. Phys Rev Lett 62: 567–570, 1989. 26. C.M. Greenlief and M. Armstrong. J Vac Sci Technol B 13: 1810–1815, 1995. 27. R. Walsh. Acc Chem Res 14: 246–252, 1981. 28. S.M. Gates. Surf Sci 195: 307–329, 1988. 29. A.M. Beers and J. Bloem. Appl Phys Lett 41: 153–155, 1982. 30. N. Gonohe, S. Shimizu, K. Tamagawa, T. Hayashi, and H. Yamakawa. Jpn J Appl Phys 26: L1189– L1192, 1987. 31. J. Ramm. III Vs Rev 15(7): 42–45, 2002. 32. F.W. Smith and G. Ghidini. J Electrochem Soc 129: 1300–1306, 1982. 33. G. Ghidini and F.W. Smith. J Electrochem Soc 131: 2924–2928, 1984. 34. A.S. Segal, S. Yu. Karpov, A.P. Sid’ko, and Yu. N. Makarov. J Cryst Growth 225: 268–273, 2001. 35. D.C. Houghton. J Appl Phys 70: 2136–2151, 1991. 36. J.H. Comfort and R. Reif. J Electrochem Soc 136: 2386–2398, 1989. 37. C. Li, S. John, E. Quinones, and S. Banerjee. J Vac Sci Technol A 14: 170–183, 1996. 38. W.B. De Boer, D. Terpstra, and J.G.M. Van Berkum. Mater Sci Eng B 67: 46–52, 1999. 39. B.S. Meyerson, F.K. LeGoues, T.N. Nguyen, and D.L. Harame. Appl Phys Lett 50: 113–115, 1987. 40. H. Lafontaine, D.C. Houghton, D. Elliot, N.L. Rowell, J.-M. Baribeau, S. Laframboise, G.I. Sproule, and S.J. Rolfe. J Vac Sci Technol B 14: 1675–1681, 1996. 41. S. Bodnar, C. Morin, and J.L. Regolini. Thin Solid Films 294: 11–14, 1997. 42. Y. Kiyota, R. Udo, T. Hashimoto, A. Kodama, H. Shimamoto, R. Hayami, E. Ohue, and K. Washio. IEEE Trans Electron Dev 49: 739–745, 2002. 43. K. Washio. IEEE Trans Electron Dev 50: 656–668, 2003. 44. S. Nayak, D.E. Savage, H.-N. Chu, M.G. Lagally, and T.F. Kuech. J Cryst Growth 157: 168–171, 1995. 45. H. Habuka and T. Otsuka. U.S. Patent 6,235,645, 2001. 46. S.R. Stiffler, J.H. Comfort, C.L. Stanis, D.L. Harame, E. de Fre´sart, and B.S. Meyerson. J Appl Phys 70: 1416–1420, 1991. 47. W. Kern and D.A. Puotinen. RCA Rev 31: 187–205, 1970. 48. S. Shwartzman. U.S. Patent 4,261,791, 1981.

© 2006 by Taylor & Francis Group, LLC

UHV/CVD Growth Techniques

2.5-105

49. A. Abbadie, J.M. Hartmann, P. Holliger, M.N. Semeria, P. Besson, and P. Gentile. Appl Surf Sci 225: 256–266, 2004. 50. M.S. Carrol, J.C. Sturm, and M. Yang. J Electrochem Soc 147: 4652–4659, 2000. 51. R. Loo, M. Caymax, I. Peytier, S. Decoutere, N. Collaert, P. Verheyen, W. Vandervorst, and K. De Meyer. J Electrochem Soc 150: G638–G647, 2003. 52. M. Caymax, R. Loo, B. Brijs, W. Vandervorst, D.J. Howard, K. Kimura, and K. Nakajima. Mater Res Soc Symp Proc 533: 339–344, 1998. 53. J.F. Gibbons, C.M. Gronet, and K.E. Williams. Appl Phys Lett 47: 721–723, 1985. 54. S.S. Iyer, M. Arienzo, and E. de Fre´sart. Appl Phys Lett 57: 893–895, 1990. 55. S. Wright and H. Kroemer. Appl Phys Lett 36: 210–213, 1980. 56. J.F. Morar, B.S. Meyerson, U.O. Karlson, F.J. Himpsel, F.R. McFreely, D. Rieger, A. Taleb-Ibrahimi, and J.A. Yarnoff. Appl Phys Lett 50: 463–465, 1987. 57. K. Nozawa, K. Katayama, Y. Kanzawa, G. Sugahara, T. Saitoh, and M. Kubo. Mater Res Soc Symp Proc 569: 83–88, 1999. 58. M. Caymax, S. Decoutere, E. Rohr, W. Vandervorst, M. Heyns, H. Sprey, A. Storm, and J.-W. Maes. Diffus Def Data pt B 65–66: 237–240, 1999. 59. H. Ogawa, T. Arai, M. Yanagisawa, T. Ichiki, and Y. Horiike. Jpn J Appl Phys 41: 5349–5358, 2002. 60. H.W. Kim, K.S. Kim, and J.H. Lee. Met Mat Int 8: 183–190, 2002. 61. T. Ohmi, K. Hashimoto, M. Morita, and T. Shibata. IEDM, 1989, pp. 53–56. 62. J.C. Bean, G.E. Becker, P.M. Petroff, and T.E. Seidel. J Appl Phys 48: 907–913, 1977. 63. Y. Ma, M.L. Green, L.C. Feldman, J. Sapjeta, K.J. Hanson, and T.W. Weidman. J Vac Sci Technol B 13: 1460–1465, 1995. 64. S.-H. Lim, S. Song, T.-S. Park, and E. Yoon. J Vac Sci Technol B 21: 2388–2392, 2003. 65. T.J. Donahue and R. Reif. J Electrochem Soc 131: 1691–1697, 1886. 66. J.L. Regolini, D. Bensahel, Y.I. Nissim, J. Mercier, E. Scheid, A. Perio, and E. Andre. Electron Lett 24: 408–409, 1988.

© 2006 by Taylor & Francis Group, LLC

2.6 Defects and Diffusion in SiGe and Strained Si 2.6.1 2.6.2

Introduction............................................................... 2.6-107 Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge ......................... 2.6-109 The Lattice Vacancy and Vacancy–Impurity Complexes in Si . The Lattice Vacancy and Vacancy–Impurity Complexes in Ge . The Silicon Interstitial and Interstitial-Related Interactions in Si . The Germanium Interstitial and Interstitial-Related Interactions in Ge

2.6.3

Effects of SiGe Alloy Composition and Strain on Defect Characteristics.......................................... 2.6-112 Effect of Alloy Composition on the Formation Energies of Intrinsic Defects in SiGe . Effect of Alloy Composition on Electronic Properties of Defects in SiGe . Effect of Strain on Defect Characteristics

2.6.4

Specific Defects in SiGe ............................................ 2.6-114 Shallow Dopants . Radiation (Implantation)-Induced Defects . Metallic Impurities

2.6.5

A.R. Peaker and V.P. Markevich University of Manchester

Diffusion .................................................................... 2.6-115 The General Picture . Self-Diffusion in Unstrained Si1
xGex . Dopant Diffusion in Unstrained SiGe . The Impact of Strain and Interfaces on Diffusivity

2.6.6 2.6.7

Dislocations................................................................ 2.6-122 Summary .................................................................... 2.6-122

2.6.1 Introduction Defects play a crucial role in semiconductor processing and in finished devices by mediating diffusion, defining junction leakage, and controlling carrier recombination. As a result, issues as wide ranging as junction depth, noise, and memory retention time are critically dependent on the defect population. By far the most important source of point defects is the ion implantation process, which produces high concentrations of intrinsic defects (self-interstitials and vacancies). The issues regarding diffusion enhancement in silicon by intrinsic defects have been studied in great detail in relation to small devices and although some work exists for the SiGe case, the problem is vastly more complicated because of the interaction of defects with strain, interfaces, and, in some cases, the introduction of dislocations. In this section of the handbook we consider briefly the principles behind these effects and then review the relevant literature on point defects and defect complexes in silicon, in germanium, and in silicon– germanium. We consider the electronic properties of the defects and in particular their position in the bandgap and as a consequence the likely effects on the electrical behavior of devices. The recent literature on diffusion in SiGe and strained Si is reviewed and the effects of point defects on diffusion are 2.6-107 © 2006 by Taylor & Francis Group, LLC

2.6-108

The Silicon Heterostructure Handbook

considered along with the impact of strain on diffusivities of the common dopants. Finally we look at the significance of dislocations in relation to device performance. Much of our understanding of ion implantation defects in silicon and their annealing kinetics is based on studies of electron-irradiated silicon. A high-energy electron will displace an atom in the semiconductor matrix to produce a vacancy and an interstitial as a Frenkel pair. The interstitial is quite mobile and diffuses either to react with a vacancy or substitutional impurities or to add to the surface of the crystal. The remaining vacancies pair with impurities in the immediate vicinity of the displacement or with themselves to form divacancies. The most common reaction products in Si and SiGe are the vacancy–oxygen pair and the divacancy. However there are very substantial differences between the point defects introduced by electron damage and the defects commonly seen in ion-implanted semiconductors. As the mass and energy of the implanted species increases, a more complex population of defects is created. There is clear evidence that this is due to clusters of interstitials or vacancies depending on the depth below the surface relative to the implant range. Many of the vacancies and interstitials recombine to reconstitute the lattice, others react with each other to form clusters of vacancies or clusters of interstitials. Such clusters result in relatively stable entities, which may dissociate during the annealing process used to activate the implanted dopants. The released point defects can result in substantial changes in the diffusivity of the dopants. By far the best known example is the enhancement of boron diffusivity in silicon by excess of self-interstitials in which the diffusivity is increased by several orders of magnitude. The generation of intrinsic defects is very nonuniform throughout the ion path, with the majority of defects created near the end of range. Redistribution of the defects at the implant temperature results in a vacancy-rich region near the surface and an interstitial-rich region just beyond the concentration peak of the implanted species. On annealing, particularly under oxidizing conditions where the surface cannot act as a sink for the interstitials, extrinsic stacking faults with their bounding Frank partial dislocation loops can be formed at the end of the implant range. These accommodate the excess of selfinterstitials locally as an extra plane of atoms. Some of the defects react with impurities (dopants, carbon, oxygen, and hydrogen) during the annealing process. However the majority of these defects can be removed from the active region of the device provided the device design will withstand a sufficient thermal budget. In the next section we examine the populations of defect complexes that evolve and their position in the bandgap. This is an issue of crucial importance in relation to device-significant properties. Figure 2.6.1 shows the conceptual behavior of such defect levels in terms of their behavior as generation, recombination, or trapping centers. Process (A) is the dominant mechanism affecting the generation lifetime. It is a very important process in memory applications particularly DRAM but can also be a major contributor to CMOS quiescent current. In Si and SiGe, process (D) is the dominant mechanism

Conduction band en

Cn en

(A)

Cn

(B) (D)

(C) ep ep

Cp Cp

Valence band

FIGURE 2.6.1 The classic Shockley–Hall–Read representation of (A) a generation center, (B) an electron trap, (C) a hole trap, and (D) a recombination center.

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-109

in defining the recombination lifetime; it is important in bipolar devices and can have a defining influence on the base transport factor and hence the gain in some transistor structures. The trapping processes (B) and (C) are potential sources of noise. In practice the noise frequency is low and in general trapping processes are regarded as contributors to 1/f noise and in consequence are of most significance in analog circuits, particularly RF mixers. If such centers are present in very high concentrations, the charge they store can shift the operating point of devices, either slowly with time or after overload conditions.

2.6.2 Intrinsic Defects and Their Interactions with Impurities in Crystalline Si and Ge The Lattice Vacancy and Vacancy–Impurity Complexes in Si The isolated lattice vacancy in Si has been identified by electron paramagnetic resonance (EPR) in both its paramagnetic single positive (Vþ) and negative (V
) charge states after in situ electron irradiation at cryogenic temperatures (4.2 to 20.4 K) [1, 2]. It was found that the vacancy can take on five different charge states in the silicon band gap: (þþ), (þ), (0), (
), and (

). The information available on the electronic and structural properties of the vacancy is summarized in Table 2.6.1. The EPR spectra of the isolated vacancy disappear after a 15-min annealing at 70 K in n-type Si, 150 K in p-type, and 200 K in high-resistivity material [1, 2]. The disappearance is argued to be related to the long-range diffusion of the vacancy, and the difference in the annealing temperatures is caused by the different values of the activation energy for the vacancy migration in different charge states. The activation energies for migration were determined as 0.18 + 0.02 eV for V

, 0.45 + 0.04 eV for V0, and 0.32 + 0.02 eV for Vþþ [1, 2]. The disappearance of the EPR spectra of the isolated vacancy is accompanied by the appearance of other EPR signals, which are identified as due to vacancies paired with other defects. The Si vacancy forms pairs with group V donor atoms (P, As, Sb) as well as with oxygen, germanium, tin, and some other impurity atoms [1–5]. The interaction of two vacancies was found to result in the formation of the divacancy. The information available on the electronic properties, symmetry, and thermal stability of some vacancy-related point defects is presented in Table 2.6.1. Important issues to be considered in relation to diffusion problems are equilibrium concentrations of intrinsic defects at high temperatures. The equilibrium concentration of a point-defect species X can be expressed as [6]:    f   Cx DGxf DSx
DHxf ¼ Qx exp exp ¼ Qx exp
Cs kT k kT where DG xf, DHxf, and DS xf are, respectively, Gibbs free energy, the enthalpy, and the entropy changes related to the formation of one defect X. DSxf has a configurational contribution and a vibrational contribution that arises from a change in the lattice vibrational frequency spectrum in the vicinity of X: DSxf ¼ DSxf ,c þ DSxf ,v The term Qx is the number of equivalent, distinguishable configurations that X can take (per lattice site); for a given lattice site, at most, one of the Qx configurations that are associated with it can be occupied at any time. Cs is the number of available lattice sites in the crystal (i.e., number of substitutional sites, tetrahedral interstitial sites, etc.). It should be mentioned that there are no experiments where equilibrium concentrations of vacancies or interstitials in Si have been measured definitely. Estimates of the vacancy formation enthalpy based on experimental studies gave the values in the range of 2 to 3.2 eV [4, 7], while the values obtained from theoretical calculations are higher, 3.5 to 3.7 eV [8, 9].

© 2006 by Taylor & Francis Group, LLC

2.6-110

The Silicon Heterostructure Handbook

TABLE 2.6.1 Charge States in the Gap, Symmetry, Position of Energy Levels, and Temperature Ranges of Annealing Out for the Most Abundant Vacancy-Related Defects in Si (from Refs. [2, 3] unless indicated) (Question Marks Indicate the Data that Are Doubtful)

Defect

Charge States

Vacancy

Vacancy—oxygen Vacancy—phosphorus Vacancy—antimony Vacancy—germanium

Divacancy

Vacancy—boron Vacancy—aluminum




0 þ þþ – 0 – 0
0

0 þ þþ


0 þ 0 þ
0

Configuration (Point-Group Symmetry) At Low Temperatures C2v C2v D2d D2d Td C2v C2v — C2h — C2h — —

D3d C2h C2h C2h C1h — C3v —

Energy Levels E(

/
)  Ec
0.17 eV E(
/0) ¼ Ec
0.57 eVa (?) E(0/þ) ¼ Evþ0.05 eV E(þ/þþ) ¼ Evþ0.13 eV

Annealing Out Temperature Ranges (8C) (15–30 min Isochronal) (
225) to (
175) (
75) to (
25)

E(
/0) ¼ Ec
0.17 eV

(
125) to (
75) 325–375

E(
/0) ¼ Ec
0.43 eV

100–175

E(
/0) ¼ Ec
0.44 eV

175–225

E(

/
) ¼ Ec
0.29 eVb (?) —

(
75) to (
25)

E(

/
) ¼ Ec
0.24 eV E(
/0) ¼ Ec
0.43 eV E(0/þ) ¼ Evþ0.20 eV

225–300

—

(
25) to 25

— 225–275

a

From PM Fahey, PB Griffin, and JD Plummer. Point defects and dopant diffusion in silicon. Reviews of Modern Physics 61:289–388, 1989. With permission. b From CV Budtz-Jorgensen, P Kringhoj, A Nylandsted Larsen, and NV Abrosimov. Deep-level transient spectroscopy of the Ge-vacancy pair in Ge-doped n-type silicon. Physical Review B 58:1110–1113, 1998. With permission.

The Lattice Vacancy and Vacancy–Impurity Complexes in Ge In contrast to the silicon case, reliable information available on the properties of the lattice vacancy and vacancy–impurity complexes in crystalline Ge is rather limited. According to recent theoretical calculations [10, 11], the structure and electronic properties of the vacancy in Ge are similar to those of the vacancy in Si: the vacancy in Ge is present as five charge states: (þþ), (þ), (0), (
), and (

). However, the magnitudes and energies of Jahn–Teller distortions were found to be smaller for the vacancy in Ge compared to Si. Comparison with the results for silicon showed that the vacancy formation energies in germanium (from 1.7 to about 2.5 eV) are significantly smaller than in silicon, for all charge states, which makes the vacancy much more important for diffusion in Ge than in Si [10]. Very little information on the positions of energy levels of the isolated vacancy and activation energies for the vacancy migration in Ge is available. However, it was suggested recently on the basis of perturbed angular correlation (PAC) spectroscopy measurements that the (
/0) energy level of the Ge vacancy should be at about Ev þ (0.2 + 0.04) eV [12]. A PAC signal, which was assigned to a complex of a 111In atom with a vacancy nearby, appeared upon annealing at temperatures around 200 K

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-111

in Ge samples subjected to electron irradiation at 77 K. It was proposed that this process is related to the long-range migration of neutral vacancies, and the activation energy for the V0 diffusion was estimated as 0.6 + 0.1 eV [12]. Regarding the vacancy diffusivity in Ge, there is another study [13], the results of which look inconsistent with the results obtained from PAC measurements. It was found by Whan [13] that in oxygen-rich Ge samples, which were electron-irradiated at 25 K, oxygenrelated LVM lines emerged upon annealing in the temperature range 45 to 80 K. These lines were associated with vacancy–oxygen complexes, and the above observation was considered as an evidence for the vacancy diffusion in Ge at low (50 K) temperatures. It might be possible, however, that the vacancy diffusion occurred in different charge states in PAC [12] and infrared (IR) absorption [13] measurements. As in the case of silicon, there are some strong indications that the vacancy in Ge can interact with oxygen and group V donor atoms (P, As, Sb, Bi) with the formation of complexes stable at room temperature. It was shown recently in a combined deep-level transient spectroscopy (DLTS) and IR absorption spectroscopy study that the vacancy–oxygen complex in Ge can exist in three charge states: (

), (
), and (0), with the corresponding energy levels at about E(

/
) ¼ Ec
0.21 eV and E(
/0) ¼ Ev þ 0.27 eV [14, 15]. Strong arguments were presented recently that the Sb–V vacancy in Ge introduces two acceptor levels in the gap at about E(

/
) ¼ Ec
0.20 eV and E(
/0) ¼ Ev þ 0.30 eV [16, 17]. The Sb–V complex in Ge annealed out in the temperature range 140 to 1808C [16, 17].

The Silicon Interstitial and Interstitial-Related Interactions in Si In contrast to the isolated vacancy, the isolated self-interstitial has not been observed directly either in p-type or n-type Si after low-temperature electron irradiation, and the structure and electronic properties of the Si self-interstitial are not known definitely [3]. In p-type Si after low temperature irradiation, EPR signals due to defects which were identified as interstitials trapped at impurities were observed and the same concentration as isolated vacancies. It is argued that the isolated interstitial atoms must be highly mobile in p-type material, even at 4.2 K. There is also strong evidence for lowtemperature (<175 K) long-range migration of Si self-interstitials in n-type Si. Si self-interstitials were found to interact effectively with group III acceptor atoms (B, Al) and substitutional carbon atoms [3]. Information available on electronic properties and thermal stability of the first generation trapped interstitials (Ali Bi, Ci) is given in Table 2.6.2. It was found that these defects can, in turn, migrate over long distances and form pairs with other defects. Table 2.6.2 shows information on the properties of some of these second generation interstitial defects. The values of formation enthalpy of the Si self-interstitial estimated on the basis of some experimental studies are in the range of 3.2–3.8 eV [4, 21]. These values are close to those obtained from theoretical calculations, 3.2–3.7 eV [8, 9].

The Germanium Interstitial and Interstitial-Related Interactions in Ge Reliable information available on the properties of the Ge self-interstitial and its interaction with impurities in crystalline germanium is rather limited. It was found in a recent theoretical study that the Ge interstitial could be an amphoteric defect with an acceptor and a donor level in the gap [22]. For all the charge states the h1 1 0i-split dumbbell configuration was found to be the energetically favored one. The formation energy for the neutral Ge interstitial (2.3 eV) was found to be significantly lower than the corresponding value for Si (3.2 eV) according to the calculations [22]. It was suggested in a recent study based on PAC measurements that Ge self-interstitial has an energy level at about Ec
0.04 eV and is mobile, either in neutral or in singly positively charged state, at temperatures above 220 K [12]. The activation energy for the diffusion was estimated as 0.6 + 0.1 eV.

© 2006 by Taylor & Francis Group, LLC

2.6-112

The Silicon Heterostructure Handbook

TABLE 2.6.2 Charge States in the Gap, Position of Energy Levels, and Temperature Ranges of Annealing Out for the Most Abundant Interstitial-Related Defects in Si Defect

Ali

Bi

Ci

Bi–Oi Ci–Oi Ci–Cs

Charge States

0 þ þþ
0 þ
0 þ þ þþ 0 þ
0 þ

Energy Levels

— E(þ/þþ) ¼ Evþ0.17 eV

Annealing Out Temperature Ranges (8C) (15–30 min Isochronal) — 175–225a —

E(
/0) ¼ Ec
0.37 eV E(0/þ) ¼ Ec
0.13 eV (
25) to 25a E(
/0) ¼ Ec
0.10 eV E(0/þ) ¼ Evþ0.28 eV

50–100

E(þ/þþ) ¼ Ec
0.27 eVb (?) E(0/þ) ¼ Evþ0.35 eV

150–200 350–400

E(
/0) ¼ Ec
0.16 eV E(0/þ) ¼ Evþ0.09 eVc

225–275

a

Annealing out of Bi and Ali is free-carrier injection dependent, much faster upon injection conditions; see Refs. [3, 18]. b From PM Money, LI Cheng, M Su¨li, JD Gerson, and JW Corbett. Defect energy levels in boron-doped silicon irradiated with 1-MeV electrons. Physical Review B 15: 3836–3843, 1977. With permission. c The Ci–Cs is a bistable defect; see Ref. [20] for the details of its electronic structure. Source: From GD Watkins. Vacancies and interstitials and their interactions with impurities in c-Si. Properties of Crystalline Silicon (EMIS Data Review Series No. 20), R. Hull (ed.), INSPEC, London, 1999, chapter 11.1, pp. 643–652. With permission.) (Question Marks Indicate The Data that Are Doubtful)

2.6.3 Effects of SiGe Alloy Composition and Strain on Defect Characteristics Effect of Alloy Composition on the Formation Energies of Intrinsic Defects in SiGe The effect of SiGe alloy composition on the formation energy of vacancies has been studied by ab initio calculations in Refs. [23–25]. There was a consensus that the formation energy of a vacancy in Si1
xGex alloys drops by about 0.2 to 0.25 eV for each Ge atom surrounding the vacancy. The energy of the system with a vacancy was found to drop by 0.04 eV for every second nearest-neighbor Ge atom to the vacancy [25]. There are no reliable data on the effect of SiGe alloy composition on the self-interstitial formation energy.

Effect of Alloy Composition on Electronic Properties of Defects in SiGe Electronic properties of defects in SiGe alloys have been considered recently in Ref. [26]. It was argued that there are three types of behavior a defect may exhibit in the Si1
xGex alloys. First, the core of the defect might be occupied with Ge atoms and consequently the properties of the center are quite different from those of the defect in pure Si. Second, the change in the lattice parameter can cause the vibrational modes or energy levels to shift often in a linear way for dilute concentrations of Ge, and third, the presence of Ge atoms affect the conduction and valence bands in a way beyond the change in bond length and this has an influence on the lattice parameter and other properties. It is often difficult to distinguish these three effects in the alloy experimentally, but the recently developed technique of Laplace deep-level transient spectroscopy (LDLTS) [27] has enabled them to be separated

© 2006 by Taylor & Francis Group, LLC

2.6-113

Defects and Diffusion in SiGe and Strained Si

in some cases and so used to study the local environment of defects [26, 28]. As an example, Figure 2.6.2 shows results of a study of the siting of Au in SiGe. The populations could be quantified and so it was possible to state that gold has a strong preference to site in the vicinity of germanium [28]. Each of the three above mentioned effects might cause changes in diffusivity of defects and binding energies of complexes.

Effect of Strain on Defect Characteristics

Laplace DLTS amplitude

The application of uniaxial or biaxial stress to a semiconductor changes the equilibrium population of interstitials and vacancies. These effects are significant enough to change diffusion coefficients [29] as will be discussed later. Stress modifies other important parameters, such as the formation of interstitial dislocation loops after implantation and the behavior of implantation-induced point defects. The effect of strain on point defects is to lift the degeneracy so that the electronic behavior is different in different directions. This can be observed as a splitting of the properties in techniques with sufficient resolution; classically this has been done in optical absorption, electron spin resonance, and photoluminescence. Unfortunately, these techniques cannot be used on thin layers, but the application of LDLTS [27] allows the direct measurements of electronic properties and the observation of defect motion in thin epitaxial layers under uniaxial stress. An example is given in Figure 2.6.3 for the divacancy [30]. In this experiment, compressive stress is applied to the sample during measurements and the splitting can be observed as a function of stress. Combined with heating, the same technique can be used to study the motion of impurities in strained silicon. In this case, the impurity is aligned at a temperature above that used for the measurement and then cooled to the measurement temperature. The motion can be observed as a function of annealing and activation energies for the process extracted in the usual way. This motion, on an atomic scale, is at the heart of diffusion mechanisms and these novel techniques for observing and quantifying it have the potential to give us a much deeper understanding of the mechanisms involved than the traditional top–down approach and these mechanisms are normally the basis of diffusion studies in more conventional systems.

SiGe: Au 5% Ge at T = 248 K 0

Si

Ge 1 2 1

10 100 1000 Emission rate (s−1)

FIGURE 2.6.2 Electron emission from gold in Si0.95Ge0.05 with a flat diagram representation of first and second nearest neighboring atoms. The labelling on the peaks represents emission from gold with 0, 1, or 2 Ge atoms in the first nearest-neighbor position. (Adapted from L Dobaczewski et al. Physical Review Letters 83: 4582–4585, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

FIGURE 2.6.3 The effect of uniaxial stress on the dominant ion implantation defect in silicon. The stress lifts degeneracy and shifts in the electron binding energy are observed as line splitting. (Adapted from L Dobaczewski et al. Physical Review B 65: 113203-1 to 113203-4, 2002. With permission.)

2.6-114

The Silicon Heterostructure Handbook

2.6.4 Specific Defects in SiGe Shallow Dopants Phosphorus donors have been studied in Si-rich Si1
xGex alloys (0  x  0.27) by means of IR absorption [31]. A weak shift of the activation energy with germanium content was found: E(A1) ¼ (45.5
26x) meV. This was explained by multivalley effective mass theory with a phenomenological central cell potential, which does not depend on alloy composition within the investigated range. The experiments showed that P atoms are distributed at random in the alloy and that their positions are uncorrelated to those of the Ge atoms. Boron–germanium pairs were detected in Si-rich Si1
xGex alloys (0  x  0.075) by means of b-nuclear magnetic resonance (NMR) technique [32]. It was found that the binding energy of the B–Ge pair is low and the probability of the formation of the complex matches with statistical expectations.

Radiation (Implantation)-Induced Defects Vacancy-Related defects The effect of SiGe alloy composition on the electronic properties and thermal stability of vacancy–donor (P, Sb) atom pairs was studied by means of DLTS in strain-relaxed Si1
xGex samples (0  x  0.25), which were grown by the molecular beam epitaxy (MBE) technique [33]. It was found that the activation enthalpy of electron ionization from the single acceptor level of the Sb–V pair increases from 0.41 to 0.51 eV with the increase in Ge content [33]. Recent positron annihilation spectroscopy study showed that Ge atoms are effective sinks for mobile phosphorus–vacancy pairs in strained Si-rich SiGe samples [34]. The V–P–Ge complex was found to anneal out at about 2008C. The 508C higher annealing temperature of the V–P–Ge complex corresponds to about 0.1 to 0.2 eV larger binding energy than that of the V–P pair [34]. Electronic properties of vacancy–oxygen complexes in SiGe alloys were investigated recently in a combined DLTS and ab initio modeling study [26]. Bulk unstrained Czochralski-grown SiGe samples irradiated with electrons were studied. At least three configurations of the VO centers were identified in SiGe alloys. The most stable configuration consists of a Si–O–Si unit and a Ge–Si reconstructed bond in a vacancy. This configuration was found to be about 0.2 eV more stable than separated VO and Ges defects and possesses an acceptor level, which is about 25 meV deeper compared to the level of the VO center without a Ge atom in a nearest-neighbor site. The increase of the ionization enthalpy of the VO complexes with the increase in Ge content in Si1
xGex crystals (the rate of the increase was determined to be about 0.55x eV) was associated with changes in the average Si–Si bond length [26]. The energy levels of the divacancy have been studied in epitaxially grown, strain-relaxed Si1
xGex as a function of x for 0  x 0.5, using DLTS on particle-irradiated pþn and nþp diodes [35]. The two acceptor levels situated in the upper half of the bandgap in Si (see Table 2.6.1) were found to move gradually deeper into the gap with increasing x and the single-acceptor level crosses the midgap for x  0.25, from then on the change of energy changes slope with x . The donor level in the lower half of the bandgap becomes gradually more shallow, pinned to the conduction band. The annealing temperature of the divacancy was found to be independent of composition in the investigated composition range [35]. Interstitial-Related defects DLTS has been used to study electronic properties and annealing behavior of Ci and CiCS defects, created by proton or electron irradiation in strain-relaxed, epitaxial Si1
xGex of 0.005  x  0.5 [36, 37]. It was shown that neither the acceptor levels of Ci and CiCS nor the donor levels of the Ci center are pinned to any of the band edges when the composition of the Si1
xGex was varied. The electron ionization enthalpies of the acceptor levels were found to increase with a rate dDH/dx  0.3 eV/x . The two levels of the Ci defect

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-115

remained at an energy of 0.8 eV separation from each other, independent of composition. The migration enthalpy of Ci was found to be independent of composition (DHm  0.75 eV) in the investigated composition range, 0  x  0.15. The experimentally observed increased stability of Ci with increasing x was argued to be due to a dramatic decrease of the entropy of migration of the Ci defect. It was argued that the entropy is a crucial parameter when discussing dynamic effects in disordered materials [37]. Electronic properties of the Ci–Oi complex were investigated recently in bulk unstrained Czochralskigrown Si1
xGex samples irradiated with electrons. The enthalpy of hole ionization for the single donor level of the complex relative to the valence band edge, DHp, was found to decrease with a rate d(DHp)/dx ¼
0.96 eV upon increase in Ge content [38]. The level is not pinned to the conduction band edge or to the valence band edge.

Metallic Impurities DLTS and high-resolution LDLTS techniques have been also used to study effects of SiGe alloy composition and strain on the electronic properties of 3d transition metal (Fe, Ti, Cr, Ni) and 5d noble metal (Au, Pt) impurities [39–43]. It was found that, as a rule, in strain-relaxed Si1
xGex alloys metal-related energy levels in the lower part of the bandgap move towards the valence band edge with increasing Ge content [39–43]. For the metal-related energy levels in the upper part of the gap both the increase and decrease in activation energies for ionization relative to the conduction band edge were observed upon the increase in Ge content [39–42]. Activation energies of ionization of both electron and hole traps related to metallic impurities were found to increase with the increase of strain in SiGe alloys [41]. The strain dependence was described in terms of the deep state uniaxial and hydrostatic deformation potentials. The difference between the deep state activation energies in Si and Si1
xGex did not agree with the independently determined Si–Si1
xGex band offsets [41, 42]. This demonstrated that the concept of 3d state as an independent, internal reference level, well established for III–V and II–VI compounds, fails in the case of group IV semiconductors [41, 42].

2.6.5 Diffusion The General Picture Diffusion of the common dopants (boron, phosphorous, arsenic, and antimony) in silicon–germanium alloys is inherently more complex than in the elemental semiconductors. In general, diffusion proceeds via the interaction of the dopant species with point defects. In this case these are predominantly the silicon and germanium interstitials and vacancies. An example of the significance of the importance of intrinsic defects is the diffusion of boron in silicon. There have been numerous studies of the release of interstitials from clusters of silicon atoms formed during ion implantation [44, 45]. The dissociation of these clusters during annealing is the basis of enhanced diffusion with diffusivity increases of several orders of magnitude. This has proved to be an immense problem in producing silicon devices with small feature sizes. In contrast species such as antimony, in which diffusion is mediated by vacancies, exhibit a reduced diffusivity in the presence of excess of interstitials. In the alloy the presence of two species results in parallel mechanisms for diffusion. In the general case a classical Arrhenius dependence of the diffusivity D on the temperature T is observed and so we can express the vacancy and interstitial contributions separately: D¼

D0I

 I  V
Ea
Ea V exp þ D0 exp kT kT

The activation energies are each derived from two components namely the energy required to form the intrinsic defect and the migration energy. In principle both of these components might be expected to

© 2006 by Taylor & Francis Group, LLC

2.6-116

The Silicon Heterostructure Handbook

depend on composition of the alloy. For example, the energy required to form a vacancy will depend on the local environment, i.e., how many germanium atoms occupy the four first nearest-neighbor sites. According to the dominant mechanism the diffusion of a particular species is referred to as being interstitially mediated or vacancy mediated. However, another major difference is the presence of strain, which, among other things, alters the equilibrium concentration of intrinsic defects. It is now generally accepted that the formation energy of the self-interstitial increases with increasing compressive strain and decreases with increasing tensile strain. Strain is present in most SiGe systems of technological interest and in general the strained layers are rather thin bounded by heterojunctions or surfaces. The surfaces and interfaces perturb the vacancy and interstitial populations. In the case of the surface the presence of oxide introduces additional interstitials while a nitrided surface will introduce excess vacancies. This is well documented for the case of silicon but has not been studied in the same detail for germanium or germaniumrich alloys. In consequence it is very important to deconvolute the effects of alloy composition from that of strain and the effects of interface proximity. Attempts have been made to do this by modeling [46]. Experimentally the simultaneous presence of strain and alloy effects makes quantifying diffusivity in SiGe extremely difficult with many experimental pitfalls. In consequence there are considerable differences in the literature in absolute values. However, it is possible to measure diffusivity in unstrained SiGe although it is important that the unstrained state is not achieved through relaxation via dislocation formation. This is because the presence of these extended defects at diffusion temperatures modulates the intrinsic defect population and introduces localized strain. In this review, we have focussed on studies of single-crystal material with low dislocation density, ignoring some of the older work on polycrystalline or highly dislocated material. For dilute alloys of Si1
xGex (x > 0.9 or x < 0.1) bulk Czochralski-grown material can be grown [47] but for 0.1 x  0.9 virtual substrate layers must be used [48]. Separation of the effects on diffusivity of strain from other parameters must be achieved if SiGe process models are to have general applicability. A further complication is self-diffusion. Interdiffusion is enhanced by strain and in thin layers it may be the dominant mechanism for strain relaxation rather than dislocation formation. Such diffusion tends to reduce the germanium concentration in the germanium-rich region of the heterostructure and vice versa, so introducing uncertainty into both the strain and composition in such experiments. However, self-diffusion also gives us insight into the mechanisms of diffusion in SiGe.

Self-Diffusion in Unstrained Si1
xGex It is generally accepted that the diffusion of most species in Ge is mediated by vacancies and this is true of self-diffusion. However in silicon Ge diffusion depends on both vacancies and interstitials. In the alloy the interstitially mediated diffusion of Ge in Si1
xGex is significant in the range 0 < x < 0.25 and although there are far fewer data this is probably true of Si diffusion as well. Most recent self-diffusion experiments have been carried out by the introduction of an isotopically enriched region either during growth or by implantation. Considerable care needs to be taken when using implantation as this will perturb the equilibrium concentration of intrinsic defects. The behavior of Ge diffusion in relaxed material is seen clearly in Figure 2.6.4 taken from Laitinen et al. [49]. The diffusivity D at a specific temperature is given from the data by  
Ea D ¼ D0 exp kT In the diagram the activation energy Ea is presented as an enthalpy H. The diagram includes some data from Strohm et al. [50] and Hettich et al. [51]. Strohm’s and Zangenberg’s [52] data are quantified in Table 2.6.3 which also includes a result (x ¼ 0.8) from Laitinen. The change of behavior at x  0.25 is very pronounced and reflects the transition from vacancy-mediated diffusion in the germanium-

© 2006 by Taylor & Francis Group, LLC

2.6-117

Defects and Diffusion in SiGe and Strained Si

5.5

H (eV)

10−2

D0(x)

4.5

10−3

4.0

10−4

H(x)

3.5 3.0 0.00

0.25

0.50

D 0 (m2S−1)

10−1

5.0

0.75

1.00

10−5

x

FIGURE 2.6.4 Self-diffusion enthalpies H (filled symbols) and pre-exponential factors D0 (open symbols) of diffusion coefficients in SiGe as functions of the Ge content x (circles: 71Ge in SiGe epilayers [50]; diamonds: 71Ge in bulk Si [51]; downtriangles: 71Ge in Si0:20Ge0:80 epilayers and in bulk Ge; uptriangles: 31Si in Si0:20Ge0:80 epilayers). (Reprinted with permission from Laitinen et al. Physical Review Letters 89, 085902 (2002). Copyright 2002 by the American Physical Society.)

TABLE 2.6.3 Activation Energies (Ea) and Pre-Exponential Factors (D0) for Self-Diffusion of Ge in Si1
xGex Alloys of Composition x Si1
xGex Composition x

VPE SiGea,b Implanted 71Ge Ea (eV)

0 (Si) 0.05 0.10 0.2 0.25 0.3 0.4 0.43 0.50 0.8 0.95 1 (Ge)

4.97 4.9 4.7 4.1

MBE SiGec Grown in 72Ge Spike

D0 (cm2/sec)

Ea (eV)

D0 (cm2/sec)

2500 4000 400

4.65

310

4.66 4.00

870 6.6

3.82 3.72

4.7 4.2

3.23

0.11

33

4.0

29

3.48 3.3 3.09

81 100 13.6

a

From A Strohm, T Voss, W Frank, J Ra¨isa¨nen, and M Dietrich. Self-diffusion of 71Ge in Si–Ge. Physica B 308–310: 542–545, 2001. With permission. b ¨ ysto¨, From P Laitinen, A Strohm, J Huikari, A Nieminen, T Voss, C Grodon, I Riihima¨ki, M Kummer, J A P Dendooven, J. Ra¨isa¨nen, W Frank, and ISOLDE Collaboration. Self-diffusion of 31Si and 71Ge in relaxed Si0:20Ge0:80 layers. Physical Review Letters 89: 085902-1 to 085902-4, 2002. With permission. c From N Zangenberg, J Lundsgaard Hansen, J Fage-Pedersen, and A Nylandsted Larsen. Ge self-diffusion in epitaxial Si1
xGex layers. Physical Review Letters 87:125901, 2001. With permission.

rich material to interstitially dominated mediation in pure silicon. A more detailed study by Strohm et al. [53] reports a very similar trend but puts the transition from interstitial dominance to vacancy dominance at x  0.35 and details a comprehensive analysis of the relative contributions. However, in terms of absolute values, there is a clear systematic behavior reflected in all the published data showing increased self-diffusivity of Ge with increasing Ge content. The data on self-diffusion of Si in SiGe are very limited but values very similar to those of Ge have been reported in relaxed Si0.2Ge0.8 and silicon [49, 53]. The enthalpy values are the sum of the energy of formation of the vacancy and the energy required for its migration. Venezuela et al. have calculated the formation energies of vacancies in Si0.5Ge0.5 using

© 2006 by Taylor & Francis Group, LLC

2.6-118

The Silicon Heterostructure Handbook

first-principle methods [24]. They find a strong dependence of the formation energy on the configuration of the first nearest-neighbor atoms. This varies linearly from 2 to 3 eV as the number of nearestneighbor Ge atoms varies from 4 to 0. Ramanarayanan et al. Have undertaken ab initio calculations of the vacancy migration energy [25]. However as yet these calculations are quite a long way from providing a comprehensive explanation of the experimental observations in relaxed material.

Dopant Diffusion in Unstrained SiGe Table 2.6.4 provides data on the diffusion mechanism of a number of species in silicon and germanium by indicating whether diffusion is mediated by interstitials or vacancies. This is important as it enables us to decide whether diffusivity will be enhanced or retarded under implant conditions and to predict the effects of strain [54]. We will review the published data on the common dopant species. Arsenic A systematic study of arsenic diffusion in relaxed SiGe across the entire composition range has been undertaken by Laitinen et al. [55] as detailed in Table 2.6.5. Radioactive isotopes (73As and 72As) were introduced by implantation into 1 mm-thick relaxed Si1
xGex epilayers grown by low-energy plasma enhanced chemical vapor deposition (LEPECVD) on graded buffer layers. The density of the threading dislocations was estimated to be about 106 cm
2. As stated previously self-diffusion in Si1
xGex for x > 0.35 is vacancy dominated. Although as shown in Table 2.6.4 diffusion of As in Si is mediated predominantly by interstitials in germanium-rich alloys it is considered to proceed via vacancies. When the arsenic activation energies are compared with Ge self-diffusion values for SiGe, their dependence on the SiGe composition is very similar and it seems likely that the decrease in activation energy as a function of x results from the decrease in vacancy formation energy. The activation energy values for arsenic diffusion are 0.5 eV lower than for self-diffusion. It is postulated that this may be due to the arsenic migrating via a vacancy–arsenic complex [55].

TABLE 2.6.4 Role of Vacancies and Interstitials in Promoting Diffusion in Silicon and Germanium Migrating Species

Silicon Matrix

Germanium Matrix

Boron Phosphorous Arsenic Antimony Silicon Germanium

Interstitial Interstitial Interstitial Vacancy Mixed Mixed

Vacancy? Vacancy Vacancy Vacancy Vacancy Vacancy

TABLE 2.6.5 Activation Energies (Ea) and Pre-Exponential factors (D0) of the As Diffusion Coefficients as a Function of Si1
xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated from Ea and D0 (Extrapolated Data are Shown in Italics) Si1
xGex Composition x 0 0.20 0.35 0.50 0.65 0.80 1.00

Temperature Range (8C)

Ea (eV)

D0 (cm2/sec)

D8508C (cm2/sec)

882–1120 882–1120 812–1050 750–1020 675–870 696–925 490–600

3.81 3.83 3.68 3.47 3.16 2.97 2.42

4.3 30 23 18 16 11 5.8

2.2 10
19 1.9 10
16 7 10
16 4.8 10
15 4.3 10
15 5.2 10
13 8 10
11

Source : From P Laitinen, I Riihima¨ki, J. Ra¨isa¨nen, and ISOLDE Collaboration. Arsenic diffusion in relaxed Si1
xGex. Physical Review B 68: 155209-1 to 155209-6, 2003. With permission.

© 2006 by Taylor & Francis Group, LLC

2.6-119

Defects and Diffusion in SiGe and Strained Si

Eguchi et al. [56] have separated the transient diffusion effects following implantation from the equilibrium behavior in relaxed SiGe. They find, as above, that increased germanium content increases the equilibrium diffusivity but observe a decrease in transient diffusion effects with increasing germanium content. Antimony Antimony is the only dopant which diffuses in both Si and Ge via a mechanism that is mediated predominantly by vacancies. In silicon the diffusion mechanism is via the vacancy Sb pair (the E center) discussed previously in Section 2.6.2. Larsen and Kringhøj [57] have studied the diffusion of antimony in relaxed Si1
xGex layers grown by molecular beam epitaxy for 0 < x < 0.5. The diffusivity of antimony was found to increase with the Ge alloy content. The activation energies for diffusion were found to decrease with increasing germanium content. A summary of their results is given in Table 2.6.6. Antimony exhibits a particularly strong dependence of diffusivity on concentration. In germanium Boltaks [58] reports a change of Ea from 1.69 to 2.13 eV with an increase in Sb concentration from 1015 to 1018 cm
3 and a corresponding increase in D0 from 2.710
3 to 0.35 cm2/sec. In Table 2.6.6 Chui’s [59] value for [Sbmax] ¼ 61019 cm
3 is included for pure Ge which enables comparison with Larsen et al., who have used quite high concentrations of [Sbmax] in their experiments (1019 cm
3). These data represent much lower diffusivities than have been reported by Dan et al. [60] who have used point-defect injection from surface oxidation or nitridation to introduce excess of interstitials or vacancies, respectively. This has confirmed that Sb diffusion is vacancy-mediated in Si and Si0.9Ge0.1. However, lower Sb concentrations were used [Sbmax] ¼ 31018 cm
3 and the SiGe layer used by Dan was compressively strained, which would reduce the formation energy of the vacancy as will be discussed in Section 2.6.5.5. The combination of these two effects probably accounts for the differences in the reported diffusivities. Phosphorus Table 2.6.7 presents the results of Zangenberg et al. [61] and data on pure germanium [59, 62]. Here the activation energy of the diffusivity in Si is rather low compared to the generally accepted values. The authors attribute this to non-Arrhenius behavior as their measurements have been made at relatively low temperatures. However, the diffusion coefficient (as distinct from the individual values of Ea and Do) calculated from the data agrees with the literature below 9008C. The conclusion is similar to that of Eguchi et al. [63], i.e., that the presence of Ge enhances the diffusion coefficient of phosphorus. Boron The case of boron is quite complicated. As already discussed the diffusivity of boron is very sensitive to the presence of excess of interstitials and so issues of ion implantation damage and surface generation of interstitials (e.g., by annealing in an oxidizing atmosphere) create variables which confuse both researchers and process engineers. However, there are other variables. The boron interstitial exists in both neutral and positive charge state. This is believed to have an effect on the diffusivity at low temperatures where the intrinsic carrier concentration is less than the extrinsic hole concentration

TABLE 2.6.6 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Sb Diffusion Coefficients as a Function of Si1
xGex Composition x Si1
xGex Composition x 0 (Si) 0.1 0.2 0.3 0.5 1 (Ge)

Ea (eV)

D0 (cm2/sec)

D8508C (cm2/sec)

4.06 4.07 4.07 3.89 3.63 2.28

0.2 0.4 1.3 0.8 4.2 0.12

1.210
19 2.210
19 7.110
19 2.810
18 2.110
16 7.110
12

Source : Ref. [57] with the exception of the Ge data, which are from Ref. [59].

© 2006 by Taylor & Francis Group, LLC

2.6-120

The Silicon Heterostructure Handbook

TABLE 2.6.7 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Phosphorus Diffusion Coefficients as a Function of Si1
xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated from Ea and D0 (an Extrapolated Figure is Shown in Italics) Si1
xGex Composition x 0 0.07 0.12 0.24 0.4 1 (Ref. [63]) 1 (Ref. [60])

Temperature range (8C)

D0 (cm2/sec)

Ea (eV)

D8508C (cm2/sec)

825–900 825–900 800–900 800–900 800–900 560–850 650 þ model

2.010
3 1.810
1 1.110
1 1.7103 1.7102 2.5 4.410
2

2.80 3.24 3.11 4.01 3.83 2.48 2.07

5.510
16 5.210
16 1.110
15 1.710
15 1.110
15 1.810
11 2.210
11

Source : Ref. [61] with the exception of the Ge data, which are from Refs. [59, 62].

(ni < p). The small size of the boron atom compared to silicon and germanium introduces lattice relaxation effects, which have an impact on transit paths in SiGe and favor the formation of complexes. Cowern et al. [64] have proposed a mechanism by which oxidation-enhanced diffusion occurs via the formation of boron–interstitial complexes. There is a substantial literature on boron diffusion in Si and SiGe but unfortunately there are significant discrepancies in values of activation energies and prefactors. However when this is translated into diffusion coefficients around the temperatures at which the measurements were undertaken the discrepancies are much less pronounced. It is not really clear, as a generality, whether this is due to fitting Arrhenius behavior over a limited temperature range or more fundamental issues associated with the entropy term as exemplified by the Meyer–Neldel rule [65]. Zangenberg et al. [61] have measured diffusion in Si1
xGex for 0 < x < 0.4 in relaxed MBE material at temperatures in the range 8008C to 9008C. These results are shown in Table 2.6.8 together with a diffusivity result for pure Ge from Uppal et al. [66]. Perhaps the most noteable result is that the diffusion coefficient shows almost no change across the entire composition range of SiGe. Uppal’s result has led to speculation that the longstanding assumption that boron diffusion in Ge is vacancy mediated may not be correct. However Uppal et al. used experimental conditions that injected large concentrations of interstitials, which would be expected to suppress vacancy mediated diffusion. This discrepancy may result from conditions that were very different from previous experiments, which gave much higher diffusivities [62]. Recent first-principle calculations [67] appear to support Uppal’s interpretation but further experimental work is needed to resolve this important issue particularly in the Ge-rich SiGe alloys.

The Impact of Strain and Interfaces on Diffusivity The application of hydrostatic pressure or stress (uniaxial or biaxial) to a semiconductor changes the equilibrium population of interstitials and vacancies. Free energy calculations for the hydrostatic pressure case indicate that the formation energy of the self-interstitial increases with increasing compressive strain and decreases with increasing tensile strain. The formation energy of the vacancy decreases with increasing compressive strain and is almost independent of tensile strain [68]. Aziz [53] and Zhao et al. [69] have considered the hydrostatic case theoretically and experimentally and the relationship between hydrostatic, biaxial, and uniaxial stress in relation to point-defect generation. In the strained Si and SiGe cases, it is obviously biaxial stress that is technologically important and is significant enough to change self-diffusion coefficients and the diffusivity of common impurities under normal process conditions. Zangenberg et al. [52] have measured the effect of strain on self-diffusion (Ge in Si0.9Ge0.1). Their work showed a decrease in diffusion coefficient and an increase in activation energy on going from compressive to relaxed to tensile strain. A compressive strain of 0.21% (corresponding to an

© 2006 by Taylor & Francis Group, LLC

2.6-121

Defects and Diffusion in SiGe and Strained Si

TABLE 2.6.8 Activation Energies (Ea) and Pre-Exponential Factors (D0) of the Boron Diffusion Coefficients as a Function of Si1
xGex Composition x. Values of Diffusion Coefficient at 8508C are Calculated From Ea and D0 Si1
xGex composition x 0 0.01 0.12 0.24 1

Temperature range (8C)

D0 (cm2/sec)

Ea (eV)

D8508C (cm2/sec)

800–900 800–925 800–925 800–925 850

3.410
4 3.410
2 2.410
1 5.710
2 —

2.68 3.13 3.30 3.18 —

3.210
16 3.110
16 3.810
16 3.110
16 1.310
16

a

Source: Ref. [61] with the exception of the Ge data, which are from Ref. [64].

in-plane stress of 0.4 GPa) produced an increase in diffusivity by a factor of 1.8 at 10008C while the same tensile stress reduced the diffusivity by about 20%. Earlier results from Cowern et al. [70] show changes in the same sense but of considerably greater magnitude. However, there is a fundamental difference between the experiments in that Cowern et al. measured the diffusion from a Si1
xGex layer with 0.1< x < 0.3 into Si, while Zangenberg et al. used a substitution of 72Ge for the natural Ge in the epilayer. In this latter experiment the diffusion of the germanium within the SiGe produced no change in composition and hence no stress relief. In Cowern’s case the interdiffusion is driven by strain relaxation, which is probably favored kinetically over dislocation growth as the relaxation mechanism. Work by Zangenberg et al. on boron in strained Si0.88Ge0.12 showed a reduction (by a factor of 2) in the diffusion coefficient with compressive strain of 0.21% and a very slight reduction with a similar value of tensile strain. In the case of silicon a factor of 2 increase of boron diffusivity was seen in tensile strained material compared to unstrained silicon [60]. Earlier work by Moriya et al. [71] and by Kuo et al. [72] also showed a retarded B diffusion in compressively stressed SiGe but the separation of the strain effects from the role of germanium was not clear. However, subsequent work discussed above [61] seems to indicate that the chemical effect is small in the case of boron and the dominant effect is strain. Paine et al. [73] have measured the diffusion of boron in compressively strained Si1
xGex layers over the entire composition range but again their results convolute the effects of strain and composition. Over the range 0 < x < 0.5 the diffusivity decreases by almost an order of magnitude with increasing germanium content but then in the germanium-rich region the diffusivity was observed to increase with increasing Ge concentration. Unlike boron in which diffusion is mediated by interstitials the diffusion of antimony is mediated by vacancies; as a consequence the expectation is that compressive stress will enhance the diffusivity due to the reduced energy of formation of the vacancy while tensile stress will have little effect. Kringhøj et al. [29] have studied Sb diffusion under both compressive and tensile stress in Si and Si0.91Ge0.09 and indeed diffusivity is enhanced by compressive stress and retarded by tensile stress. In real devices the issue of composition change is almost always convoluted with strain but in addition interfaces are present. We have already referred to the studies of Cowern et al. [70] where the interdiffusion across a heterojunction was driven by strain relaxation. More recently Lever et al. [74] have studied diffusion across interfaces. The test structures used were grown on Si substrates by LPCVD and consisted of a boron-doped silicon layer sandwiched between two dilute undoped Si1
xGex layers with x ¼ 0.1 or 0.03. After annealing at 8508C the boron profile was determined by SIMS. In all cases there was a clear accumulation of boron in the SiGe layers, which was attributed to a preferential siting of the boron with Ge as a first nearest neighbor. This confirms earlier work by Hu et al. [75] in which experimental results were obtained on the segregation coefficients of boron, phosphorus, and arsenic in Si–(GexSi1
x) heterostructures. It was found that boron tended to segregate into the germanium-rich region, while phosphorus and arsenic tend to segregate away from it. Within experimental error, the diffusivities were not appreciably affected.

© 2006 by Taylor & Francis Group, LLC

2.6-122

The Silicon Heterostructure Handbook

2.6.6 Dislocations The only issue we consider here is the electrical behavior of dislocations although of course they can have a significant effect in device processing as diffusion pipes with resultant shorts across junctions. It is well established that dislocations in Si and in SiGe have levels in the bandgap [76, 77] and so it is apparent there are two key questions to address; firstly the position of the levels in the gap and secondly whether the concentration is sufficient to affect device performance. Dislocations introduce an ensemble of electronic levels into the gap, which can appear as a continuum or mini band of states. The electronic behavior is distinctly different to that of point defects, which, in general, have well-defined discrete energy levels. A very important issue in assessing the significance of dislocations is the role of decoration. The energy state associated with the undecorated dislocation is relatively shallow, typically 120 meV, but as impurities are drawn into the region of the strain field the level moves towards mid-gap [78]. This is very significant as the mid-gap states are extremely effective generation centers while the shallower ‘clean’ state is ineffective in this role. This work has been done mostly on Frank partial dislocations bounding stacking faults but dislocations with larger Burgers vectors behave similarly. In these experiments extremely small levels of ‘decoration’ with transition metals were used. These are well below those detectable in transmission electron microscopy (TEM) and probably typical of levels found in ‘adequate’ fabs in the late 1980s (a few ppb averaged over the layer volume). The behavior with different metals is remarkably similar provided they can diffuse to the defect. However, as the concentration of impurity is increased, metals which precipitate (e.g., copper) produce electrically inert objects which draw the impurity away from dislocations with small Burgers vectors and the state moves away from mid-gap, making it less effective as a generation center. There is also evidence from scanning electron microscopy studies using electron beam induced currents and from luminescence mapping that decorated dislocations are also much more important as recombination centers than clean dislocations [79]. In the limit a dislocation can trap one charge at each atomic plane it threads through but experimental observations indicate that on average the concentration of charge traps is much lower. This gives us a basis for calculating the effects of dislocations on devices assuming a worst-case scenario in which the decoration is such as to move the level to mid-gap. A generation state is only active in the depletion region so if we know the depletion width we can calculate the leakage current produced by one dislocation. For the purpose of this calculation we will assume a device operating temperature of 708C and transistors typical of the 90 nm node in the International Technology Roadmap for Semiconductors (ITRS). At this node the physical gate length is 37 nm, the junction depth 33 nm and Vdd 1 V. The worst-case leakage current associated with a single dislocation is 200 pA. The value is essentially the same for a threading dislocation or a misfit dislocation. This is dramatically different from measurements on devices with wide depletion regions (e.g., power devices where leakage currents as high as 1 mA /dislocation have been reported) [80]. The reason is due to the size of the device and the length of dislocation which can be accommodated in the depletion region. The probability of finding more than one dislocation in a 35-nm device is extremely remote so the question is will our technology accept a leakage current of 200 pA? The design rules for the 90-nm CMOS mode accommodate 20 nA /mm and so it seems that even this worst-case scenario is acceptable for conventional CMOS although the requirements for some memory devices are more stringent. The case of bipolar transistors can be considered very simply. The leakage considerations are very similar to those discussed above. In relation to the effects of dislocations on gain (recombination), the effects are negligible. Beyond the 180-nm node the base width in both hetero- and homojunction transistors is sufficiently small for us to be able to neglect the role of base recombination in the transistor gain.

2.6.7 Summary In this section of the handbook we have tried to give an overview of defects and diffusion in SiGe. It is clear that in the last few years very substantial progress has been made towards resolving one of the

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-123

major problems that plagued early work, namely, separating the issues associated with strain from the chemical effects associated with the presence of two species in the host matrix. There is now a very substantial and reliable literature on defects in silicon and in dilute Si1
xGex (i.e., where x < 0.3). However recent work has caused us to doubt the validity of some of the previously accepted work on germanium. Very little experimental data exist on defects or on diffusion in the germanium-rich alloys (x > 0.5) and extrapolation from x < 0.3 is not feasible because of changes in intrinsic defect mechanisms at around x ¼ 0.25. Interpolation between x ¼ 0.3 and x ¼ 1 is dubious partly for the same reason but also because of doubts regarding the pure germanium data. It is evident that much more work is required if we are to have a sufficiently rigorous understanding of defects and defect reactions to develop reliable process models for devices containing pure germanium or germanium-rich layers.

Acknowledgments We are grateful to our colleagues for valuable discussions and their contribution to this work. In particular we thank A.N. Larsen, K. Bonde Nielsen, L. Dobaczeweski, G. Davies, A.F.W. Willoughby, J.M. Bonar, L.I. Murin, J.L. Lindstro¨m, A. Mesli, and N.V. Abrosimov. We would also like to thank W. Frank and A. Strohm for providing data on self-diffusion.

References 1. GD Watkins. EPR studies of the lattice vacancy and low-temperature damage processes in silicon. Lattice Defects in Semiconductors 1974, edited by FA Huntley. Inst. Phys. Conf. Ser. No 23, IOP, Bristol, 1975, pp 1–22. 2. GD Watkins. The lattice vacancy in silicon. Deep Centers in Semiconductors, ST Pantelides (ed.). Gordon and Breach, New York, 1986, chapter 3, pp 147–183. 3. GD Watkins. Vacancies and interstitials and their interactions with impurities in c-Si. Properties of Crystalline Silicon (EMIS Data Review Series No. 20), R. Hull (ed.), INSPEC, London, 1999, chapter 11.1, pp. 643–652. 4. PM Fahey, PB Griffin, and JD Plummer. Point defects and dopant diffusion in silicon. Reviews of Modern Physics 61: 289–388, 1989. 5. CV Budtz-Jorgensen, P Kringhøj, A Nylandsted Larsen, and NV Abrosimov. Deep-level transient spectroscopy of the Ge-vacancy pair in Ge-doped n-type silicon. Physical Review B 58: 1110–1113, 1998. 6. M Lannoo and J Bourgoin. Point Defects in Semiconductors I: Theoretical Aspects. Springer Series in Solid State Sciences No 22, Springer, New York, 1981. 7. S Dannefaer, P Mascher, and D Kerr. Monovacancy formation enthalpy in silicon. Physical Review Letters 56: 2195–2198, 1986. 8. JS Nelson, PA Schultz, and AF Wright. Valence and atomic size-dependent exchange barriers in vacancy-mediated dopant diffusion. Applied Physics Letters 73: 247–249, 1998. 9. J Xie and SP Chen. Diffusion and clustering in heavily arsenic-doped silicon: discrepancies and explanation. Physical Review Letters 83: 1795–1798, 1999. 10. A Fazzio, A Janotti, AJR da Silva, and R Mota. Microscopic picture of the single vacancy in germanium. Physical Review B 61: R2401–R2404, 2000. ¨ gu¨t and R Chelikowsky. Ab initio investigation of point defects in bulk Si and Ge using a cluster 11. S O method. Physical Review B 64: 245206-1 to 245206-11, 2001. 12. H Haesslein, R Sielemann, and C Zistl. Vacancies and self-interstitials in germanium observed by perturbed angular correlation spectroscopy. Physical Review Letters 80: 2626–2629, 1998. 13. RE Whan. Investigations of oxygen-defect interactions between 25 and 700 K in irradiated germanium. Physical Review 140: A690–A698, 1965.

© 2006 by Taylor & Francis Group, LLC

2.6-124

The Silicon Heterostructure Handbook

14. VP Markevich, ID Hawkins, AR Peaker, VV Litvinov, LI Murin, L. Dobaczewski, and JL Lindstro¨m. Electronic properties of vacancy–oxygen complex in Ge crystals. Applied Physics Letters 81: 1821– 1823, 2002. 15. VP Markevich, VV Litvinov, l Dobaczewski, JL Lindstro¨m, LI Murin, and AR Peaker. Radiationinduced defects and their transformations in oxygen-rich germanium crystals. Physica Status Solidi (c) 0: 702–706, 2003. 16. J Fage-Pedersen, A Mesli, and A Nylandsted Larsen. Irradiation-induced defects in Ge studied by transient spectroscopies. Physical Review B 62: 10116–10125, 2000. 17. VP Markevich, AR Peaker, VV Litvinov, VV Emtsev, and LI Murin. Electronic properties of antimony–vacancy complex in Ge crystals. Journal of Applied Physics 95: 4078–4083, 2004. 18. JR Troxell, AP Chatterjee, GD Watkins, and LC Kimerling. Recombination-enhanced migration of interstitial aluminum in silicon. Physical Review B 19: 5336–5348, 1979. 19. PM Money, LI Cheng, M Su¨li, JD Gerson, and JW Corbett. Defect energy levels in boron-doped silicon irradiated with 1-MeV electrons. Physical Review B 15: 3836–3843, 1977. 20. LW Song, XD Zhan, BW Benson, and GD Watkins. Bistable interstitial-carbon–substitutionalcarbon pair in silicon. Physical Review B 42: 5765–5783, 1990. 21. H Bracht, NA Stolwijk, and H Mehrer. Properties of intrinsic point defects in silicon determined by zinc diffusion experiments under nonequilibrium conditions. Physical Review B 52: 16542–16560, 1995. 22. AJR da Silva, A Janotti, A Fazzio, RJ Baierle, and R Mota. Self-interstitial defect in germanium. Physical Review B 62: 9903–9906, 2000. 23. J Lento, M Pesola, J-L Moros, and RM Nieminen. Vacancies in SiGe: Jahn–Teller distortion and spin effects. Applied Physics Letters 77: 232–234, 2000. 24. P Venezuela, GM Dalpian, AJR da Silva, and A Fazzio. Vacancy-mediated diffusion in disordered alloys: Ge self-diffusion in Si1
xGex . Physical Review B 65: 193306-1 to 193306-4, 2002. 25. P Ramanarayanan, K. Cho, and BM Clemens. Effect of composition on vacancy mediated diffusion in random binary alloys: first principles study of the Si1
xGex system. Journal of Applied Physics 94: 174–185, 2003. ¨ berg, PR Briddon, LI Murin, 26. VP Markevich, AR Peaker, J Coutinho, R Jones, VJB Torres, S O L Dobachewski, and NV Abrosimov. Structure and properties of vacancy–oxygen complexes in Si1
xGex alloys. Physical Review B 69: 125218-1 to 125218-11, 2004. 27. L Dobaczewski, P Kaczor, ID Hawkins, and AR Peaker. Laplace transform deep-level transient spectroscopic studies of defects in semiconductors. Journal of Applied Physics 76: 194–198, 1994. 28. L Dobaczewski, K Goscinski, K Bonde Nielsen, A Nylandsted Larsen, J Lundsgaard Hansen, and AR Peaker. Alloy splitting of gold and platinum acceptor levels in SiGes. Physical Review Letters 83: 4582–4585, 1999. 29. P Kringhøj, A Nylandsted Larsen, and Yu Shiryaev. Diffusion of Sb in strained and relaxed Si and SiGe. Physical Review Letters 76: 3372–3375, 1996. 30. L Dobaczewski, K Goscinski, ZR Zytkiewicz, K Bonde Nielsen, L Rubaldo, O Andersen, and AR Peaker. Piezoscopic deep-level transient spectroscopy studies of the silicon divacancy. Physical Review B 65: 113203-1 to 113203-4, 2002. 31. R Kru¨ssmann, H Vollmer, and R Labusch. The activation energy of phosphorus donors in siliconrich silicon–germanium alloys. Physica Status Solidi (b) 118: 275–282, 1983. 32. J Hattendorf, W-D Zeitz, W Schro¨der, and NV Abrosimov. On the formation of boron–germanium pairs in silicon–germanium mixed crystals. Physica B 340–342: 858–862, 2003. 33. P Kringhøj and A Nylandsted Larsen. Irradiation-induced defect states in epitaxial n-type Si1
xGex alloy layers. Physical Review B 52: 16333–16336, 1995. 34. S-L Sihto, J Slotte, J Lento, K Saarinen, EV Monakhov, AYu Kuznetsov, and BG Svensson. Vacancy– phosphorus complexes in strained Si1
xGex: structure and stability. Physical Review B 68: 115307-1 to 115307-10, 2003.

© 2006 by Taylor & Francis Group, LLC

Defects and Diffusion in SiGe and Strained Si

2.6-125

35. H av Skardi, A Bro Hansen, A Mesli, and A Nylandsted Larsen, The divacancy in particleirradiated, strain-relaxed SiGe. Nuclear Instruments and Methods in Physics Research B 186: 195– 200, 2002. 36. TP Leevard Pedersen, A Nylandsted Larsen, and A Mesli. Carbon-related defects in protonirradiated, n-type epitaxial Si1
xGex . Applied Physics Letters 75: 4085–4087, 1999. 37. A Nylandsted Larsen, A Bro Hansen, D Reitze, J-J Goubet, and J Fage-Pedersen. Interstitial-carbon defects in Si1
xGex . Physical Review B 64: 233202-1 to 233202-4, 2001. 38. VP Markevich, AR Peaker, LI Murin, and NV Abrosimov. Oxygen-related radiation-induced defects in SiGe alloys. Journal of Physics: Condensed Matter 15: S2835–S2842, 2003. 39. F Nikolajsen, P Kringhoj, and A Nylandsted Larsen. Substitutional gold in Si1
xGex. Applied Physics Letters 69: 1743–1745, 1996. 40. A Mesli, P Kringhoj, and A Nylandsted Larsen. Pinning behaviour of gold-related levels in Si using Si1
xGex alloy layers. Physical Review B 56: 13202–13217, 1997. 41. K Nauka and TI Kamins. Deep state defects in strained and relaxed epitaxial Si1
xGex on Si introduced by 3d transition metal and 5d noble metal impurities. Physica B 273–274: 603–607, 1999. 42. K Goscinski, L Dobaczewski, K Bonde Nielsen, A Nylandsted Larsen, and AR Peaker. Highresolution deep-level transient spectroscopy studies of gold and platinum acceptor states in diluted SiGe alloys. Physical Review B 63: 235309-1 to 235309-10, 2001. 43. A Mesli, B Vileno, C Eckert, A Slaoui, C Pedersen, A Nylandsted Larsen, and NV Abrosimov. Iron in relaxed Si1
xGex alloy: band gap related levels, diffusion, and alloying effects. Physical Review B 66: 045206-1 to 045206-12, 2002. 44. NEB Cowern, GFA van de Walle, PC Zalm, and DJ Oostra. Reactions of point defects and dopant atoms in silicon. Physical Review Letters 69: 116–119, 1992. 45. DJ Eaglesham, PA Stolk, H-J Gossmann, and JM Poate. Implantation and transient B diffusion in Si: the source of the interstitials. Applied Physics Letters 65: 2305, 1994. 46. A Pakfar. Dopant diffusion in SiGe: modeling stress and Ge chemical effects. Materials Science and Engineering B89: 225–228, 2002. 47. NV Abrosimov, SN Rossolenko, V Alex, A Gerhardt, and W Shro¨der. Single crystal growth of Si1
xGex by the Czochralski technique. Journal of Crystal Growth 166: 657, 1996. 48. A Nylandsted Larsen. Growth and process-induced defects in SiGe-based heterostructures. Diffusion and Defect Data Part B (Solid State Phenomena) 69–70: 43–45, 1999. ¨ ysto¨, 49. P Laitinen, A Strohm, J Huikari, A Nieminen, T Voss, C Grodon, I Riihima¨ki, M Kummer, J A 31 71 P Dendooven, J. Ra¨isa¨nen, W Frank, and ISOLDE Collaboration. Self-diffusion of Si and Ge in relaxed Si0:20Ge0:80 layers. Physical Review Letters 89: 085902-1 to 085902-4, 2002. 50. A Strohm, T Voss, W Frank, J Ra¨isa¨nen, and M Dietrich. Self-diffusion of 71Ge in Si–Ge, Physica B 308–310: 542–545, 2001. 51. G Hettich, H Mehrer, and K Maier. Tracer diffusion of 71Ge and 31Si in intrinsic and doped silicon. Institute of Physics Conference Series 46: 500–504, 1979. 52. N Zangenberg, J Lundsgaard Hansen, J Fage-Pedersen, and A Nylandsted Larsen. Ge self-diffusion in epitaxial Si1
xGex layers. Physical Review Letters 87: 125901, 2001. 53. A Strohm, T Voss, W Frank, P Laitinen and J Ra¨isa¨nen. Self-diffusion of 71Ge and 31Si in Si–Ge. Zeitschrift fu¨r Metallkunde 93: 737–744, 2002. 54. MJ Aziz. Thermodynamics of diffusion under pressure and stress: relation to point defect mechanisms. Applied Physics Letters 70: 2810–2812, 1997. 55. P Laitinen, I Riihima¨ki, J Ra¨isa¨nen, and ISOLDE Collaboration. Arsenic diffusion in relaxed Si1
xGex. Physical Review B 68: 155209-1 to 155209-6, 2003. 56. S Eguchi, CN Chleirigh, OO Olubuyide, and JL Hoyt. Germanium-concentration dependence of arsenic diffusion in silicon germanium alloys. Applied Physics Letters 84: 368–370, 2004. 57. A Nylandsted Larsen and P Kringhøj. Diffusion of Sb in relaxed Si1
xGex. Applied Physics Letters 68: 2684–2686, 1996.

© 2006 by Taylor & Francis Group, LLC

2.6-126

The Silicon Heterostructure Handbook

58. BI Boltaks. Diffusion in Semiconductors. Infosearch Ltd., London, 1963, p. 190. 59. Chi On Chui, K Gopalakrishnan, PB Griffin, JD Plummer, and KC Saraswat. Activation and diffusion studies of ion-implanted p and n dopants in germanium. Applied Physics Letters 83: 3275–3277, 2003. 60. Aihua Dan, AFW Willoughby, JM Bonar, BM Mcgregor, MG Dowsett, and RJH Morris. Antimony diffusion in silicon gemanium alloys under point defect injection. International Journal of Modern Physics B 16: 4195–4198, 2002. 61. N Zangenberg, J Fage-Pedersen, J Lundsgaard Hansen, and A Nylandsted Larsen. Boron and phosphorus diffusion in strained and relaxed Si and SiGe. Journal of Applied Physics 94: 3883–3890, 2003. 62. WC Dunlap Jr. Diffusion of impurities in germanium. Physical Review 94: 1531–1540, 1954. 63. S Eguchi, JL Hoyt, CW Leitz, and EA Fitzgerald. Comparison of arsenic and phosphorus diffusion behavior in silicon–germanium alloys. Applied Physics Letters 80: 1743–1745, 2002. 64. NEB Cowern, KTF Janssen, GFA van de Walle, and DJ Gravesteijn. Impurity diffusion via an intermediate species: the B–Si system. Physical Review Letters 65: 2434–2437, 1990. 65. NR Zangenberg and A Nylandsted Larsen, The Meyer–Neldel rule for diffusion in Si and SiGe. Physica B 340–342: 780–783, 2003. 66. S Uppal, AFW Willoughby, JM Bonar, AGR Evans, NEB Cowern, R Morris, and MG Dowsett. Diffusion of ion-implanted boron in germanium. Journal of Applied Physics 90: 4293–4295, 2001. 67. P Delugas and V Fiorentini. Energetics of transient enhanced diffusion of boron in Ge and SiGe. Physical Review B 69: 085203-1 to 085203-5, 2004. 68. A Antonelli and J Bernholc. Pressure effects on self-diffusion in silicon. Physical Review B 40: 10643– 10646, 1989. 69. Y Zhao, MJ Aziza, H-J Gossmann, S Mitha, and D Schiferl. Activation volume for boron diffusion in silicon and implications for strained films. Applied Physics Letters 74: 31–33, 1999. 70. NEB Cowern, PC Zalm, P van der Sluis, DJ Gravesteijn, and WB de Boer. Diffusion in strained Si(Ge). Physical Review Letters 72: 2585–2588, 1994. 71. N Moriya, LC Feldman, HS Luftman, CA King, J Bevk, and B Freer. Boron diffusion in strained Si1
xGex epitaxial layers. Physical Review Letters 71: 883–886, 1993. 72. P Kuo, JL Hoyt, JF Gibbons, JE Turner, RD Jacowitz, and TI Kamins. Comparison of boron diffusion in Si and strained Si1
xGex epitaxial layers. Applied Physics Letters 62: 612–614, 1993. 73. ADN Paine, AFW Willoughby, and JM Bonar. Point defect redistribution in Si1
xGex alloys. Journal of Material Science: Materials in Electronics 10: 339–343, 1999. 74. RF Lever, JM Bonar, and AFW Willoughby. Boron diffusion across silicon–silicon germanium boundaries. Journal of Applied Physics 83: 1988–1994, 1998. 75. SM Hu, DC Ahlgren, PA Ronsheim, JO Chu. Experimental study of diffusion and segregation in a Si–(GexSi1
x) heterostructure. Physical Review Letters 67: 1450–1453, 1991. 76. P Omling, ER Weber, L Montelius, HM Alexander, and J Michel. Electrical properties of dislocations and point defects in plastically deformed silicon. Physical Review B 32: 6571–6581, 1988. 77. PN Grillot, SA Ringel, EA Fitzgerald, GP Watson, and YH Xie. Electron trapping kinetics at dislocations in relaxed Ge0.3Si0.7/Si heterostructures. Journal of Applied Physics 77: 3248–3256, 1995. 78. A Berg, I Brough, JH Evans, G Lorimer, and AR Peaker. Recombination–generation behaviour of decorated defects in silicon. Semiconductor Science and Technology 7: 263–268, 1992. 79. V Higgs and M Kittler. Investigation of the recombination activity of misfit dislocations in Si /SiGe epilayers by cathodoluminescence imaging and the electron beam induced current technique. Applied Physics Letters 63: 2085–2087, 1993. 80. BO Kolbesen, W Bergholz, H Cerva, F Gelschorf, H Wendt, and G Zoth. Effects of extended lattice defects on silicon semiconductor devices. Structure and Properties of Dislocations in Semiconductors 1989. Proceedings of the Sixth International Symposium, 1989, Inst. Phys. Conf. Ser. 104: 421–430, 1990.

© 2006 by Taylor & Francis Group, LLC

2.7 Stability Constraints in SiGe Epitaxy 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6

Armin Fischer

2.7.7

Innovations for High Performance Microelectronics (IHP)

2.7.8

Introduction............................................................... 2.7-127 Image-Force Method for Strained Layer Relaxation................................................................... 2.7-128 Surface Relaxation Stress .......................................... 2.7-130 Interaction between Internal Stress and External Stress............................................................ 2.7-132 Critical Thickness and Film Stress of SiGe/Si Layers ............................................................ 2.7-133 Plastic Deformation and Work Hardening in SiGe/Si ................................................................... 2.7-135 Force Balance Model for Buried SiGe Strained Layers........................................................... 2.7-136 Summary .................................................................... 2.7-139

2.7.1 Introduction The growth of coherent thin layers on rigid crystalline substrates is possible when biaxial compressive or tensile strain in the layer accommodates the lattice mismatch between the film and substrate material. When the stored strain energy exceeds a certain threshold, the heterostructure becomes metastable and the film strain may give way to misfit dislocations. The basic energetic and kinetic parameters describing mismatch accommodation by elastic strain and misfit dislocation in metastable heterostructures appear to be well described by the framework of Matthews and Blakeslee [1–3] and Dodson and Tsao [4, 5]. However, it is evident that they cannot adequately explain the point of strain relief onset via plastic flow and the work hardening behavior of strained layers at the end of thermal relaxation process. This stems from ignoring the effects of elastic surface relaxation on the film lattice cells and the elastic interaction between straight misfit dislocations within the film–substrate interface. The first includes the problem of developing a relationship between the equilibrium critical thickness at which dislocations form and the bulk lattice mismatch [6]. The latter involves balancing the force required to move misfit dislocations against the internal elastic stress field due to dislocation–dislocation interactions [7]. Finally, suffice it to say that classical equilibrium and kinetic models for strained layer case do not imply rigorously the conditions of equilibrium at the boundary. In this chapter we present a modified Volterra approach in equilibrium theory for strain relaxation in metastable heteroepitaxial semiconductor structures, which includes the surface effects on mismatch accommodation by tetragonal distortion of the cubic lattice cells and the elastic interaction between straight misfit dislocations. Because of the mathematical complexities involved in a proper atomistic description of the competing forces, the subject is not treated here in a Frenkel–Kontorowa model or its approximations. The principle of our theoretical method is straightforward. The free-surface boundary conditions are satisfied by placing an image dislocation outside the crystal so that its stress 2.7-127 © 2006 by Taylor & Francis Group, LLC

2.7-128

The Silicon Heterostructure Handbook

field cancels that of the real misfit dislocation at the surface. We will discuss the effect of the Airy stress function that removes the fictitious shear and normal stresses at the crystal surface and thus makes the crystal stress-free. We show that this image-force method provides an equilibrium theory that correctly predicts experimentally observed values of critical layer thickness. To demonstrate the physical significance of the present approach in equilibrium theory for strained layer relaxation, we have calculated the equilibrium critical thickness and Ge content via coherency strain of SiGe/Si strained layer structures and compared our results to those predicted by using relaxation models based on the absence of surface relaxation effects and elastically noninteracting dislocations. Furthermore, by considering the exact solution for the elastic interaction of real and image dislocations, our equilibrium model can completely describe the strain relief via lattice distortion, plastic flow, and work hardening in lattice-mismatched epilayers. We show that our Volterra dislocation model is also appropriate when the film thickness is smaller than the misfit dislocation spacing. It is pointed out that the elastic coherency stress of the strained material is really affected by a large surface relaxation stress. This is essential for experimental determination of the Ge content of extremely thin films as a function of the tetragonal distortion of the cubic lattice cells. The equilibrium theory is also used to define the degree of strain relaxation and to predict the incomplete strain relief at the end of thermal relaxation process of metastable SiGe/Si heterostructures. We consider here only the thermodynamic equilibrium and homogeneous deformations of strained layer structures, recognizing that kinematic factors can influence the attainment of the equilibrium state of strain. In the final portion of the chapter we treat the case of Si-capped SiGe epilayer on Si substrate in some detail to expand the basic equilibrium theory for strained layer relaxation to such a Si /SiGe/Si geometry with two adjacent interfaces and a free surface at the top of the heteroepitaxial stack.

2.7.2 Image-Force Method for Strained Layer Relaxation In thermodynamic equilibrium, misfit dislocations appear at the interface of a strained layer heterostructure when the strained layer is thick enough that it is energetically favorable for the mismatch to be accommodated by a combination of elastic strain and interfacial misfit dislocations rather than by elastic strain alone [8]. This equilibrium critical thickness hcrit has been calculated and discussed by many authors in the continuum picture as well as through phenomenological description of dislocation dynamics [1, 3, 5, 9–14]. However, there have been many reports (e.g., in Refs. [11, 14–16]) of experimental determinations of hcrit, indicating that coherence apparently persists to thicknesses much greater than that predicted by classical equilibrium theories. The semiempirical kinetic model of Dodson and Tsao [4, 5] is more appropriate to describe the latter stages of relaxation, where the effective stress is decreasing due to a reduction in misfit strain produced by the high dislocation density. For the case of sufficiently low dislocation content in the strained layer near the point of strain relief onset, this model reduces to the equilibrium form of Matthews and Blakeslee [1, 3]. Thus the challenge remains to develop a predictive model appropriate for strained layer relaxation [17]. To introduce an appropriate continuum model, we begin by analyzing the conditions under which the strained layer relaxation should occur in metastable heterostructures, and then we modify the governing models to account for the discrepancies mentioned above. In a finite body, boundary conditions at the surface must be satisfied. For example, no forces can act on a free surface. The image-force method provides a powerful tool to solve such problems in the continuum theory of elasticity [18]. Let us now consider the schematic illustration in Figure 2.7.1. For the strained layer case, the free-surface boundary conditions are satisfied by placing an image dislocation outside the crystal such that its stress field cancels that of the real interfacial misfit dislocation at the surface. The condition is fulfilled if the selfstress of an image misfit dislocation of equal strength and opposite sign at a position 2h along the strained interface normal is superposed on the self-stress of the real primary dislocation. In general, the complete stress distribution for a mixed dislocation is given by the superposition of the stress fields of the real dislocation, the image dislocation, and a stress term derived from the Airy stress function that makes the surface traction-free. In our case of a mixed dislocation in a coaxial cylinder with its line

© 2006 by Taylor & Francis Group, LLC

2.7-129

Stability Constraints in SiGe Epitaxy

Image dislocation

h Free surface R

h

Strained layer Interface Substrate

Real primary dislocation

Real secondary dislocation p

FIGURE 2.7.1 Schematic illustration of the configuration of real and image misfit dislocations in a strained heteroepitaxial structure. The modulus of complex dislocation semispacing jRj is indicated. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

parallel to the surface, the image construction gives the dominant part of the shear stress component. Since the corresponding stress function term exerts no force component along the strained interface normal, the shear stress of the dislocation construction is approximately obtained from the shear stress of the image dislocation alone. Notice that only shear stresses in the slip system produce glide forces on a dislocation. In the continuum picture, the presence of dislocations causes strains around the line and, as a response to these, stresses as known from conventional elasticity theory. These stresses are defined by the contact forces transmitted through internal area elements. We speak of self-stresses to distinguish them from the applied misfit stresses. In linear approximation, the Volterra expression for the shear self-stress ss of a mixed straight dislocation due to its line tension in a region bounded by a coaxial cylinder of radius R is ss ¼


 Gb(1
n cos2 u) aR ln
1 , 4p(1
n)R cos f b

(2:7:1)

where G is the anisotropic shear modulus in the h1 1 0i direction of the (0 0 1) plane of the epilayer material, n is its Poisson ratio, b is the magnitude of the Burgers vector, u is the angle between the dislocation Burgers vector and its line direction, f is the angle between the slip plane and the strained interface normal, and a is a factor that accounts for the energy in the dislocation core where linear elasticity does not apply. a is generally taken to be in the range from 1 to 4 for covalently bonded semiconductor materials [18]. Because of the logarithmic dependence and the R >> b Volterra regime, the elastic self-stress is insensitive to the precise value of a. We set a/2.7 ¼ 1. Here ss is considered to act on the plane containing the dislocation line direction and the interface normal. So, referred to the slip plane surface, the shear component of the self-stress of a straight dislocation ts is given by ts ¼ cos f ss. For our case, an interfacial 608-type misfit dislocation on the slip plane causes resolved shear stress, i.e.,  n Gb 1
R 4 ts ¼ ln , 4p(1
n)R cos f b

© 2006 by Taylor & Francis Group, LLC

(2:7:2)

2.7-130

The Silicon Heterostructure Handbook

where the ratio G /cos f is the isotropic shear modulus in the {1 1 1} slip planes. Thus, in this case the quantity bts is an image force given by the simple image construction. Under these conditions the attraction of the real primary dislocation toward the surface is obtained from the stress of the image dislocation alone. So far we have considered the image-force and shear self-stress problems for a misfit dislocation in a metastable heterostructure. As shown in Figure 2.7.1, imagine now a real secondary dislocation of equal strength and sign lying parallel to the real primary dislocation at a distance of p and moving continuously towards the primary dislocation. For further deformation under the driving force produced by the external misfit stress, it is necessary that the moving misfit dislocation overcomes the resistance caused by superposed shear self-stress field of the image dislocation and the real primary dislocation bounded by a virtual cylinder of radius R ¼ h. Note that at larger distances from the real primary dislocation the image stresses largely cancel the dislocation stresses. Now for the elastic shear stress field extension of the real interfacial misfit dislocations lying parallel to another, a reasonable approximation would be to take roughly one-half the distance p between dislocations for R in Equation (2.7.2) (see Ref. [18]). However, in this case the quantity bts is a real repulsive force that drives the real primary dislocation in its slip plane toward the surface. According to the Green function method for the elastic displacements u(R) / b/R2 and the principle of superposition of displacement fields [18], we now combine the imaginary, i.e., fictitious, and the real free-surface term of the shear self-stress of a misfit dislocation, i.e., h and p/2, respectively, and get a complex dislocation semispacing R as the first-order solution. Its modulus jRj ¼ Rh,p is given by 1 1 4 2 ¼ h2 þ p2 , Rh;p

(2:7:3)

where h is the thickness of the epilayer and the subscripts h and p stand for the fictitious and the real component, respectively. We can say that the modulus of complex dislocation semispacing Rh,p is an approximate solution for the stress-free boundary associated with the presence of two free surfaces. The relationship represented by Equation (2.7.3) is plotted in Figure 2.7.2 for different layer thicknesses h. The pursual of Figure 2.7.2 shows some interesting relationships. For dislocation spacings p greater than 5h, the modulus of complex dislocation semispacing as a measure of the extension of the elastically strained continuum about a misfit dislocation is dominated by its fictitious term, i.e., by the layer thickness h. In this case, Equation (2.7.3) reduces to Rh,p  h. If p diminishes continuously, then the effect of the real term on Rh,p increases slowly. When the dislocation spacing reaches the value p  2h, the fictitious and the real free-surface terms make the same contribution to the modulus of complex dislocation semispacing. Below p  h /5, as the real misfit dislocations approach one another, the effect of the fictitious component vanishes and Rh,p does not depend on h. Replacing R with Rh,p in Equation (2.7.2), the shear component of the total self-stress created by present dislocation content in a finite body becomes finally  n Gb 1
Rh;p 4 ln : ts ¼ 4p(1
n)Rh;p cos f b

(2:7:4)

We notice that, up until now, we have considered a type of plane strain deformation under shear stresses, in which the body undergoes only changes of shape, but no changes of volume. Now let us consider the effect of the Airy stress function, which removes the fictitious tangential and radial normal stresses at the cylinder surface and thus changes the volume of the epilayer.

2.7.3 Surface Relaxation Stress In the case of the normal self-stress components of 608 misfit dislocations the above solution is inadequate and large additional stresses must be superposed. For such dislocations the normal selfstress components given by the simple image construction do not vanish at the free surface. The

© 2006 by Taylor & Francis Group, LLC

2.7-131

Stability Constraints in SiGe Epitaxy

Modulus of complex dislocation semispacing, Rh,p (Å)

1000 900Å

900 800 700

700Å

600 500Å

500 400

350Å 300 200

200Å

100 0 100

1⫻103

1⫻104

1⫻105

Dislocation spacing, p (Å)

FIGURE 2.7.2 Plot of the calculated modulus of complex dislocation semispacing jRj ¼ Rh,p as a function of misfit dislocation spacing p for strained layer thicknesses h ¼ 200, 350, 500, 700, and 900 A˚. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

procedure for solving this case is the same as that outlined above: first to superpose the simple image and then to devise a stress function that cancels the remaining forces acting at the free surface and thus satisfy the boundary conditions. Hirth and Lothe [18] have given the explicit solution of the Airy stress function for a pure edge dislocation in a cylinder parallel to a free surface. In analogy to the edge dislocation case, the first-order solution for a straight 608 misfit dislocation gives the normal self-stress components sf,t and sf,r that remove the fictitious plane strain and make the crystal stress-free:  n
 Gb 1
3h b2 4 sf ;t ¼
, 2p(1
n) cos f h2 h3  n
 Gb 1
h b2 4 , þ sf ;r ¼ 2p(1
n) cos f h2 h3

(2:7:5a)

(2:7:5b)

where h is the distance from the interface in direction to the crystal surface. These tangential and radial stress terms are in fact the external state of stress that gives rise to the image dislocation construction, which in turn creates the state of tension within the epilayer. Then, according to the generalized Hooke’s law, the normal stress sf,n acting perpendicular to the slip plane is given by the combined effect of the tangential sf,t and radial sf,r stress components on the slip plane. Therefore, from Equations (2.7.5a) and (2.7.5b) we can write the relation

sf ;n

© 2006 by Taylor & Francis Group, LLC

 n b 1
1 þ 2n h 4 ¼ : 2G(1 þ n) (1
2n)(1 þ n) 2p(1
n) cos f h2

(2:7:6)

2.7-132

The Silicon Heterostructure Handbook

Here 2G(1þn) is Young’s modulus of the epilayer. sf,n creates a state of tension between the slip planes of the epilayer. We call the normal stress sf,n the surface relaxation stress. A transformation of this normal stress into the interface plane with the tensile axis normal to the dislocation line gives the state of inplane tension within the epilayer. In these coordinates, Equation (2.7.6) yields the in-plane surface relaxation stress sf. We get sf ¼ 2 cos lsf,ncos f/cos2 f where l is the angle between the Burgers vector and the direction in the interface, normal to the dislocation line. For typical values of n from 0.26 to 0.28, the quantity (1 þ 2n)(1 – n/4)/p(1 – 2n)(1 þ n)cos2 f varies from 1.1 to 1.2, close to unity. Thus the result for the in-plane surface relaxation stress becomes approximately sf ¼

2G(1 þ n) h b cos l 2 : 1
n h

(2:7:7)

In words, the in-plane surface relaxation stress decreases linearly from its maximum value at the crystal surface h ¼ h to zero at the interface h ¼ 0, whereas the strength of surface relaxation effects on the strained layer structure is related to the reciprocal of the square of the layer thickness h. Obviously, it is a remarkable result with regard to our considerations of the lattice-mismatch accommodation. When these effects are ignored and a coherency strain calculation is carried out, one obtains a spurious result, leading to an erroneous strain that acts on a misfit dislocation — image dislocation pair for its generation. In addition, these effects should play a role in the lattice resistance to plastic flow of the material. For practical purposes, a reasonable approximation would be to take an average value sfav for sf (h), i.e., sav f ¼

1 h

Z

h

0

sf ðhÞdh ¼

2G(1 þ n) b cos l : 1
n 2h

(2:7:8)

Notice once again that G is the anisotropic shear modulus in the h1 1 0i direction of the (0 0 1) plane of the epilayer. Furthermore, we have measured the effect of the elastic surface relaxation on the strained layer heterostructure directly. The results are presented in Section 2.7.5.

2.7.4 Interaction between Internal Stress and External Stress For a complete description of the equilibrium state of stress in lattice-mismatched epilayers, we should now consider the resolved shear stress t that acts on the slip system as a consequence of an externally applied misfit stress. In an initially misfit dislocation-free substrate–epilayer system, the in-plane misfit strain is given by (al – as)/as, where a denotes the bulk lattice parameter and the subscripts ‘s’ and ‘l’ refer to the substrate and the layer, respectively. When the elastic strain is partially relieved by a single array of misfit dislocations created at the interface, the residual in-plane strain becomes « ¼ [(al
as)/as]
(b cos l/p), where the term b cos l/p represents the strain relief via plastic flow [19]. Here p is the average distance between the dislocations. Hence it follows that the lattice-mismatch accommodation would occur without in-plane tension within the epilayer caused by the surface relaxation stress. In other words, as explained above, for the case where p > h/5, the heterostructure is not tractionfree, because normal stress components acting on the crystal surface are not taken into account. To overcome this difficulty we will now substitute the modulus of complex dislocation semispacing Rh,p for p/ 2 in the residual in-plane strain expression above. So the true residual in-plane strain becomes « ¼ [(al
as)/as]
[b cos l/ (2Rh,p)], where the h term accounts for the purely elastic surface relaxation and the p term for plastic flow. In this case, the resolved shear stress t acting on the slip system on a misfit dislocation is given by t ¼ cos l cos f

© 2006 by Taylor & Francis Group, LLC


 2G(1 þ n) a1
as b cos l :
(1
n) cos f 2Rh;p as

(2:7:9)

Stability Constraints in SiGe Epitaxy

2.7-133

Thus the surface relaxation stress term is implied in the expression for the resolved shear stress that produced the driving force for plastic flow of the crystal. Note that the ratio G/cos f is the isotropic shear modulus in the {1 1 1} slip planes. As we have previously argued, a finite heterostructure is subjected to point and lattice-mismatch forces. The stresses and strains caused by such internal and external sources of stress can be superposed. We should now consider the resolved shear stress that acts on the slip system as a consequence of the externally applied stress and the elastic shear stress field due to dislocation–dislocation interactions. As shown above, during misfit strain relief via plastic flow, an intrinsic elastic stress field is built up. For further deformation, the moving misfit dislocations have to overcome the resistance caused by this stress field. Consequently, the dislocation shear self-stress field is in the direction opposite the applied misfit stress. The excess resolved shear stress required to produce plastic flow will then be given by the difference between the two stress components. Equations (2.7.4) and (2.7.9) yield texc ¼ t
ts, where the second term also accounts for work hardening of the material. Combining the two terms, we obtain an expression for the excess resolved shear stress: t exc ¼ cos l cos f


 2G(1 þ n) a1
as b cos l
(1 þ b) ; (1
n) cos f 2Rh;p as

(2:7:10)

with b¼

Rh;p 1
(n=4) ln : 4p cos2 l cos f(1 þ n) b

Here the quantity [bcosl/(2Rh,p)]b corresponds to the decrease in active shear stress through elastic interaction between dislocations depending on the current misfit dislocation density of the crystal. As a final topic, a few words on the expression for the excess resolved shear stress are appropriate. This is a convenient expression. The applications are numerous: problems of elastic strain retained by the epilayer, equilibrium critical thickness of a SiGe layer on Si substrate, initial and residual in-plane strain, film stress, work hardening of the material, degree of elastic and plastic strain relaxation, and misfit dislocation density reached at the equilibrium strain state, for example. Some of the applications are discussed in the following sections.

2.7.5 Critical Thickness and Film Stress of SiGe/Si Layers To demonstrate the physical significance of the present approach in equilibrium theory for strained layer relaxation proposed here, we have calculated the equilibrium critical thickness of Si1
xGex /Si strained layer structures as a function of the fractional atomic Ge content x. We have compared our results with those predicted by classical relaxation models, which do not include surface relaxation effects and dislocation–dislocation interactions. Taking the in-plane misfit strain [(al
as)/as] ¼ 0.0418x , Equations (2.7.3) and (2.7.10) and the equilibrium conditions for the point of strain relief onset via plastic flow, i.e., texc ¼ 0 and p ! 1, lead to the following expression for the critical strained layer thickness hcrit: 2 3 n 1
b cos l 4 h crit 4 5: ln 1þ x¼ 0:0836hcrit 4p cos2 l cos f(1 þ n) b

(2:7:11)

In the absence of surface relaxation forces, the equilibrium critical thickness of a single strained epilayer upon a substrate of different lattice parameter according to Matthews and Blakeslee is given by the formulation reported in Ref. [1]. Inserting appropriate material parameters in Equation (2.7.11) and in the Matthews–Blakeslee formulation, cos l ¼ 0.5, cos f ¼ 0.816, n ¼ 0.36 (in the (1 1 1) plane) [21],

© 2006 by Taylor & Francis Group, LLC

2.7-134

The Silicon Heterostructure Handbook

and b ¼ 3.84 A˚ for growth on the (0 0 1) surface, the equilibrium critical thickness calculated for the two different models is plotted in Figure 2.7.3. It is seen, at first glance, that our values of hcrit represented by Equation (2.7.11) are much larger than the values calculated using equation of Matthews and Blakeslee. Moreover, for a fractional atomic Ge content x greater than 0.5, the Matthews–Blakeslee formulation does not provide any value for hcrit. Additionally, we have compared our theoretical results with the published experimental data [14, 15] of hcrit obtained from Si1
xGex /Si structures, grown by molecular beam epitaxy (MBE) at a growth temperature of 7508C. For each composition, there is good agreement between our theoretical results and experimental data reported. For example, for x ¼ 0.25, hcrit was found to be approximately 200 A˚. As seen in Figure 2.7.3, for this case, our analysis yields the value of 200 A˚. The Matthews–Blakeslee model predicts only an equilibrium critical thickness value of 60 A˚. So far, we have been considering the equilibrium critical thickness of a coherently strained structure. Let us now consider film stresses for elastically strained Si1–xGex /Si layers. For the pseudomorphically strained layer case, where p ! 1, according to the previous equation (2.7.9), the in-plane film stress s becomes
 2G(1 þ n) b cos l 0:0418x
: s¼ (1
n) 2h

(2:7:12)

This equation can then be used to predict the stress response to a strain increment, which is related to the volume change of the layer. The first term on the right-hand side corresponds to a volume expansion due to Ge incorporation and the second one to a volume contraction via surface relaxation. Thus the residual in-plane strain is given by « ¼ 0.0418x
(b cos l/2h). Figure 2.7.4 shows a plot of s versus h for x ¼ 0.3, n ¼ 0.28 (in the (1 0 0) plane) [21], and G ¼ 51 GPa. This relationship between coherency stress and surface relaxation stress has also been studied experimentally. The in-plane epitaxial film stress s as a function of layer thickness was measured by a thin-film stress measuring apparatus, which

x = 0.3 2.5 In-plane misfit stress

2.1 Stress (GPa)

Equilibrium critical thickness, hcrit (Å)

103

100

1.7 1.3 In-plane film stress σ

F MB

10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Ge content, x

FIGURE 2.7.3 Comparison of predicted equilibrium critical thickness hcrit for relaxation models based on a nonstress-free body (MB, Matthews–Blakeslee) and a stress-free body (F, this study) as a function of Ge content x. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

0.9 0.5 100

200 300 400 500 SiGe layer thickness, h (Å)

600

FIGURE 2.7.4 Theoretical (solid line) and experimental (?) in-plane epitaxial film stress s as a function of thickness h for as-grown SiGe/Si. The in-plane misfit stress (elastic coherency stress) corresponding to a strain of 0.0418x is also shown. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54: 8761–8768, 1996. With permission.)

2.7-135

Stability Constraints in SiGe Epitaxy

measures the changes in the radius of curvature of a substrate created by deposition of a stressed thin film on its surface. Our experimental data are also shown in Figure 2.7.4. To our knowledge, such measurements of surface relaxation stresses have not been reported previously. It is seen that there is good agreement between our theoretical results and experimental data. This tells us that the elastic coherency stress of the strained material in the plane of the surface is really affected by a large surface relaxation stress.

2.7.6 Plastic Deformation and Work Hardening in SiGe/Si SiGe/Si structures may be grown to substantially greater thickness than our equilibrium critical thickness predictions, before misfit dislocation nucleation and propagation are observed. The heterostructure becomes metastable during growth because texc > 0. This metastable growth regime is concerned with the initial period of creep of diamond structure materials, in which marked plastic deformation under static load does not start abruptly. In our case of strained layer relaxation, such an initial period is characterized by an incubation time encouraged by lower growth temperature and lattice mismatch. The initial creep period is finally terminated by the onset of in-plane strain relief via plastic flow. The ramifications of our model for plastic flow and work hardening in Si1
xGex /Si strained layer structures will now be discussed. According to Equation (2.7.9), the in-plane film stress s becomes s¼


 2G(1 þ n) b cos l : 0:0418x
(1
n) 2Rh;p

(2:7:13)

Putting the values of the material parameters into Equations (2.7.4), (2.7.10), and (2.7.13), assuming a metastable epilayer with x ¼ 0.3 and h ¼ 500 A˚, and recalling Equation (2.7.3), we can evaluate the variation in excess resolved shear stress texc acting on the slip system and in-plane epitaxial film stress s for the complete thermal relaxation process. At the beginning of deformation, where p ! 1, texc ¼ 0.7 GPa and s ¼ 1.9 GPa, as illustrated in Figure 2.7.5. During plastic flow via misfit dislocation generation and propagation, texc and s diminish continuously and then remain unchanged at zero and 1.15 GPa, respectively, whereas the shear self-stress component ts rises to its maximum value. At this equilibrium deformation stage, the externally applied misfit stress and the shear component of elastic stress field due to dislocation interaction compensate one another and strain relief via plastic flow comes to rest. Thus, as a result of work hardening, the lattice-mismatched epilayer will remain in a certain state of strain at the end of thermal relaxation process, i.e., the strained layer is in a stable state. It should be mentioned here that investigations by Gillard et al. [20] suggest that dislocation blocking plays a certain role in limiting strain relaxation. We believe, as shown in the present and the previous sections, that the creep process in all the stages of strain relaxation in these structures is essentially determined by a purely elastic interaction between dislocations, which leads ultimately to work hardening of the material. Further experiments would be required to assess the relative contribution from blocking mechanism. For homogenous deformation, our equilibrium theory for strained layer relaxation is able to predict the degree of in-plane misfit strain relaxation both at the point of onset of plastic flow and at the point of equilibrium strain state where the plastic flow comes to rest. Returning to Equation (2.7.13), which is the general in-plane film stress equation, we define the degree of strain relaxation g as the relative lattice-mismatch accommodation by elastic surface relaxation and interfacial misfit dislocations compared to mismatch accommodation by the elastic in-plane strain alone. It can be written as the ratio of the in-plane strain relief to the in-plane misfit strain (coherency strain). For Si1
xGex /Si heterostructures, we get g¼

© 2006 by Taylor & Francis Group, LLC

b cos l : 0:0836xRh;p

(2:7:14)

2.7-136

The Silicon Heterostructure Handbook

2

x = 0.3, h = 500 Å

1.75

s

1.25 1

Strain relief via plastic flow

0.75

texc

Equilibrium strain state

Stress (GPa)

1.5

0.5 ts 0.25 0 2500

2000 1500 1000 500 Dislocation spacing, p (Å)

0

FIGURE 2.7.5 Decrease in the in-plane epitaxial film stress s and excess resolved shear stress texc during strain relief via plastic flow as a function of the dislocation spacing p. The shear self-stress component ts, the direction of strain relief via plastic flow, and the equilibrium strain state at the end of the thermal relaxation process are indicated. (From A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. With permission.)

For the point of strain relief onset via plastic flow, where p ! 1, Equation (2.7.14) reduces to gel ¼ bcos l/0.0836xh, which can be a general expression for the degree of elastic strain relief via surface relaxation. gel is a constant for a given metastable or stable SiGe /Si strained layer system. Again, according to Equation (2.7.14), the degree of total strain relaxation gt(0) for the point of equilibrium strain state at the end of thermal relaxation process is given by gt(0) ¼ b cos l/0.0836xRh,p(0), where the subscript p(0) stands for the misfit dislocation spacing reached at the equilibrium deformation stage. In our case, for Si0.7Ge0.3/Si, h ¼ 500 A˚, we get gel ¼ 0.15 and gt(0) ¼ 0.49 with p(0) ¼ 330 A˚. As the corresponding degree of plastic strain relaxation is gpl(0) ¼ gt(0)
gel, we thus have gpl(0) ¼ 0.34. Thus, as stated previously, the lattice-mismatched epilayer remains in a certain state of strain at the end of thermal relaxation process. For the given heterosystem, as a result of work hardening, the residual inplane strain is approximately 51%. Again, an elastic strain of 15% is retained in the epilayer by surface relaxation effects and about 34% of the in-plane strain due to lattice mismatch is relieved via plastic flow. It should be noted that, up to now, neither equilibrium theory was able to predict the correct relaxed strain in heteroepitaxial films.

2.7.7 Force Balance Model for Buried SiGe Strained Layers Up to now, both the classical force balance [1, 3–5, 11, 22, 23)], and energy minimization [15, 24] approaches for the determination of the critical thickness hcrit of a coherently strained layer structure at which dislocations form cannot predict this value for a Si-capped SiGe epilayer on Si substrate. The main difficulties to determine the exact strain relief onset via plastic flow in Si /SiGe/Si multilayer structures frequently arise because the classical theories are insensitive both to the effect of the free surface and the ratio of the stored elastic strain energy in the Si cap layer to that in the buried SiGe layer. Within the classical theoretical framework, it is impossible to decide at which cap layer thickness the plastic relaxation may take place through single misfit dislocation injection at the lower SiGe /Si interface

© 2006 by Taylor & Francis Group, LLC

2.7-137

Stability Constraints in SiGe Epitaxy

or through the generation of misfit dislocation dipoles with segments located at both interfaces. Detailed experimental results of hcrit for different cap layer thicknesses have also not been available. Here we extend the basic image-force equilibrium model for strained layer relaxation explained above to Si/SiGe/Si layers with a free surface at the top of the heteroepitaxial stack. The solution of the force balance problem will be carried out in plane stress [25] assuming equal elastic moduli. Far from any lateral free surface and referred to the slip plane {1 1 1} and slip directions h1 1 0i, the state of stress is uniformly biaxial of magnitude t, which is related to the in-plane strain « through t ¼ cos l cos f

2Gð1 þ nÞ «: ð1
nÞ cos f

ð2:7:15Þ

The misfit strain arising from the lattice parameter difference between silicon and germanium in a SiGe epilayer on Si substrate is 0.0418x. In a Si /SiGe /Si heterostructure, the strain that acts on a misfit dislocation–image dislocation pair for its generation is given by [26] « ¼ 0:0418x


b cos l ; 2(h þ H)

(2:7:16)

where h and H are the thicknesses of the buried SiGe layer and the Si cap layer, respectively. This relation includes the surface relaxation effects on the strained layer stack and makes the crystal stress-free at the surface to satisfy the boundary conditions [17, 18]. Counteracting the shear stress component t are the dislocation self-stress terms [11, 26]. These are associated with the strain energy required to create straight misfit dislocation segments at interfaces and the dislocation–dislocation interaction energy between the two parallel segments. The self-stress of a strain-relaxing 608 misfit dislocation on the slip plane of the lower SiGe/Si interface is

t SiGe

 n Gb 1
hþH 4 ln ; ¼ 4p(1
n)h cos f b

(2:7:17:1)

where h þ H is the outer cutoff distance of the interfacial dislocation, a measure of the energy stored in the elastic stress field of the misfit dislocation. Note that the strain energy can be regarded as either the work done on a radial cylinder cut surface in creating the dislocation or, equivalently, by Stoke’s theorem, the stored elastic strain energy in a coaxial cylinder containing the dislocation. Then, the selfstress of a misfit dislocation on the slip plane of the upper Si /SiGe interface is of the form  n Gb 1
H 4 ln ; t Si ¼ 4p(1
n)h cos f b

(2:7:17:2)

where, in this case, H is the outer cutoff distance of the strain-relaxing interfacial dislocation, identical to the cap layer thickness. The attraction of the dipole segments of equal strength and opposite sign lying on adjacent interface planes is given by a stress term connected with a negative dislocation–dislocation interaction energy between the two parallel segments [18, 27]:

t Si=SiGe

 n Gb 1
hþH 4 ln : ¼
4p(1
n)h cos f h

(2:7:17:3)

where the negative interaction energy represents the decrease in free energy of the crystal when the dipole segments of opposite sign are brought together from a distance of h þ H to a separation h. Since the free energy change is a state function, it is independent of the path taken.

© 2006 by Taylor & Francis Group, LLC

2.7-138

The Silicon Heterostructure Handbook

Now consider the ratio of the stored misfit strain in the Si cap layer to that in the buried SiGe layer of a coherent Si /SiGe/Si system to find a measure for the stored elastic strain energy in the layers to drive misfit dislocation generation. This ratio is also a measure for the different frequency of the occurrence of misfit dislocations at the heterointerfaces. The total misfit strain «t in a Si-capped SiGe epilayer with an average value of the fractional atomic Ge content xh /(h þ H) (see Equation (2.7.11)) is given by «t ¼ 0:042x

h : hþH

(2:7:18:1)

Taking only the misfit strain «b in the buried SiGe layer, Equation (2.7.18.1) leads for H ¼ 0 to the wellknown expression «b ¼ 0:042x:

(2:7:18:2)

The misfit strain «c in the Si cap layer will then be given by the difference between the two strain components «t and «b . Thus we have finally «c ¼
0:042x

H : hþH

(2:7:18:3)

This shows that, if the buried SiGe layer incorporates the nucleation energy for one misfit dislocation, the Si cap layer holds energy only for H /(hþH) misfit dislocations. This energy density factor, denoted by d can vary from zero for a capless structure up to 1 for an infinitely thick Si cap layer. In the latter case, only misfit dislocation dipoles occur during strained layer relaxation. Note that, up to now, no equilibrium or energy minimization model takes into account the stored elastic strain energy in the Si cap layer. The excess resolved shear stress texc driving the bending of threading dislocations to form single and / or double misfit dislocation segments will then be given by the difference between the external stress t [Equations (2.7.15) and (2.7.16)] and the internal stress components tSiGe, tSi, tSi–Ge [Equations (2.7.17.1)–(2.7.17.3)]. Including the energy density factor d (from Equations (2.7.18.1)–(2.7.18.3)), we have texc ¼ t
tSiGe
dtSi
dtSi–SiGe. Taking the equilibrium condition for the point of strain relief onset via plastic flow, i.e., texc ¼ 0, this force balance approach leads to the following implicit expression for the critical strained layer thickness hcrit as a function of the Ge content x and the cap layer thickness H: 2 3 n
 1
b cos l 4 hcrit hcrit þ H H hcrit þ H 5 4 þ d ln
d ln þ ln x¼ 0:0836hcrit hcrit þ H 4p cos2 l cos f(1 þ n) b b hcrit with d ¼

(2:7:19)

H : hcrit þ H

This formulation gives a generalized statement of the balance between external and internal forces acting at planar Si /SiGe /Si structures. It is a measure of the transition from the thermodynamically stable to the metastable state of the strained layer system. Finally, it is worth considering the transition thickness for loss of coherency in uncapped SiGe heterostructures. For H ¼ 0, we easily obtain the solution for the critical thickness of a SiGe /Si layer substrate system given by Equation (2.7.11). Inserting appropriate material parameters given above in Equation (2.7.19) the equilibrium critical thickness hcrit calculated for the Si cap layer thicknesses H ¼ 0, 500 A˚, and 1000 A˚ is plotted versus Ge content of the SiGe layer in Figure 2.7.6. Our experimental data obtained from MBE [26, 28] and chemical vapor deposition (CVD) epitaxy [26, 29] are also shown. The agreement between calculated and measured values is evident.

© 2006 by Taylor & Francis Group, LLC

2.7-139

Stability Constraints in SiGe Epitaxy

750 H = 1000 Å

H = 500 Å H = 0

Equilibrium critical thickness, hcrit (Å)

650

550

Area with misfit dislocations

450

350

250

150 0.05

Area without misfit dislocations

0.1

0.15

0.2

0.25

Ge content (x)

FIGURE 2.7.6 Theoretical values (solid lines) and experimental measurements (symbols) of the equilibrium critical thickness hcrit as a function of fractional atomic Ge content x for different Si cap layer thicknesses H. The open data points correspond to structures that maintained coherency; the filled data points correspond to structures that became partially incoherent. The x-ray measuring accuracies are Dh, DH ¼ 10 A˚, and Dx ¼ 0.005. For comparison, the predicted equilibrium critical thickness for relaxation models based on a nonstress-free body (From JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations. Journal of Crystal Growth 27:118–125, 1974; JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: III. Preparation of almost perfect multilayers. Journal of Crystal Growth 32:265–273, 1976) is shown by the dotted line for uncapped SiGe/Si heterostructures. (From A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. Solid-State Electronics 44:869–873, 2000. With permission.)

2.7.8 Summary In this chapter I have attempted to provide a physical basis for a different approach in equilibrium theory for strain relaxation in metastable heteroepitaxial semiconductor structures. This approach includes the surface relaxation effects on the strained layer structure and the elastic interaction between straight misfit dislocations. The main purpose of this work was to develop a straightforward treatment, valid in linear elasticity, for the relatively complicated case of deformation of a finite body containing internal stresses and subjected to lattice-mismatch forces. The model we have outlined yields an expression in terms of the excess resolved shear stress for strained layer relaxation, so that the elastic strain retained by the epilayer, the equilibrium critical thickness of the strained layer, the initial and residual in-plane strain, the film stress, work hardening effects on the material, the degree of strain relaxation, and the misfit dislocation density, reached at the equilibrium strain state, can be predicted. I believe that the image-force method proposed here provides an equilibrium theory that correctly predicts the coherency and relaxation behavior of SiGe/Si and Si /SiGe/Si heterostructures. Finally, this more refined model yields better agreement between computed and measured values, and provides a consistent picture of the complex mechanism for strain relief and defect propagation in a strained layer on a lattice-mismatched substrate.

© 2006 by Taylor & Francis Group, LLC

2.7-140

The Silicon Heterostructure Handbook

References 1. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations. Journal of Crystal Growth 27:118–125, 1974. 2. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: II. Dislocation pile-ups, threading dislocations, slip lines and cracks. Journal of Crystal Growth 29:273–280, 1975. 3. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: III. Preparation of almost perfect multilayers. Journal of Crystal Growth 32:265–273, 1976. 4. BW Dodson and JY Tsao. Relaxation of strained-layer semiconductor structures via plastic flow. Applied Physics Letters 51:1325–1327, 1987. 5. BW Dodson and JY Tsao. Erratum: relaxation of strained-layer semiconductor structures via plastic flow. Applied Physics Letters 52:852, 1988. 6. E Kasper and HJ Herzog. Elastic strain and misfit dislocation density in Si0.92Ge0.08 films on silicon substrates. Thin Solid Films 44:357–370, 1977. 7. A Fischer and H Richter. On plastic flow and work hardening in strained layer heterostructures. Applied Physics Letters 64:1218–1220, 1994. 8. GC Osbourn. Strained-layer superlattices: a brief review. IEEE Journal Quantum Electronics QE22:1677–1681, 1986. 9. DC Houghton. Misfit dislocation dynamics in Si1–xGex /(100)Si: Uncapped alloy layers, buried strained layers, and multiple quantum wells. Applied Physics Letters 57:1434–1436, 1990. 10. DC Houghton. Nucleation rate and glide velocity of misfit dislocations in Si1–xGex /(100) Si heterostructures. Applied Physics Letters 57:2124–2126, 1990. 11. DC Houghton. Strain relaxation kinetics in Si1–xGex /Si heterostructures. Journal of Applied Physics 70:2136–2151, 1991. 12. R Hull, JC Bean, DJ Werder, and RE Leibenguth. Activation barriers to strain relaxation in latticemismatched epitaxy. Physical Review B 40:1681–1684, 1989. 13. R Hull. Equilibrium theories of misfit dislocation networks in the SiGe /Si system. In: E Kasper (ed.), Properties of Strained and Relaxed Silicon Germanium. London: Inspec, 1995. 14. E Kasper. Strained layer superlattices. In: EE Mendez and K von Klitzing (eds), Physics and Applications of Quantum Wells and Superlattices. New York: Plenum Press, 1987. 15. R People and JC Bean. Calculation of critical layer thickness versus lattice mismatch for GexSi1–x /Si strained layer heterostructures. Applied Physics Letters 47: 322–324, 1985. 16. BA Fox and WA Jesser. The effect of frictional stress on the calculation of critical thickness in epitaxy. Journal Applied Physics 68:2801–2808, 1990. 17. A Fischer, H Ku¨hne, M Eichler, F Holla¨nder, and H Richter. Strain and surface phenomena in SiGe structures. Physical Review B 54:8761–8768, 1996. 18. JP Hirth and J Lothe. Theory of Dislocations. New York: McGraw-Hill, 1968. 19. JR Willis, SC Jain, and R Bullough. Work hardening and strain relaxation in strained-layer buffers. Applied Physics Letters 59:920–922, 1991. 20. VT Gillard, WD Nix, and LB Freund. Role of dislocation blocking in limiting strain relaxation in heteroepitaxial films. Journal of Applied Physics 76:7280–7287, 1994. 21. JJ Wortmann and RA Evans. Young’s modulus, shear modulus, and Poisson’s ratio in silicon and germanium. Journal of Applied Physics 36:153–156, 1965. 22. CG Tuppen and CJ Gibbings. A quantitative analysis of strain relaxation by misfit dislocation glide in Si1–xGex /Si heterostructures. Journal of Applied Physics 68:1526–1534, 1990. 23. R Hull, JC Bean, D Bahnck, LJ Peticolas Jr, and KT Short. Interpretation of dislocation propagation velocities in strained GexSi1–x /Si(100) heterostructures by the diffusive kink pair model. Journal of Applied Physics 70:2052–2065, 1991. 24. JH van der Merwe. Structure of epitaxial crystal interfaces. Surface Science 31:198–228, 1972. 25. SP Timoshenko and NJ Goodier. Theory of Elasticity. New York: McGraw-Hill, 1982.

© 2006 by Taylor & Francis Group, LLC

Stability Constraints in SiGe Epitaxy

2.7-141

26. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 27. FRN Nabarro. The mathematical theory of stationary dislocations. Advances in Physics 1:269–394, 1952. 28. H-J Osten, HP Zeindl, and E Bugiel. Considerations about the critical thickness for pseudomorphic Si1–xGex growth on Si(001). Journal of Crystal Growth 143:194–199, 1994. 29. B Tillack, HH Richter, G Ritter, A Wolff, G Morgenstern, and C Eggs. Monitoring of deposition and dry etching of Si /SiGe multiple stacks. Journal Vacuum Science Technology B 14:102–105, 1996.

© 2006 by Taylor & Francis Group, LLC

2.8 Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys 2.8.1 2.8.2 2.8.3

Introduction............................................................... 2.8-143 Strain and its Impact on Energy Bands .................. 2.8-143 Measurements of Energy Band Lineups.................. 2.8-147 The Strained Si/Strained Si1
yGey/Relaxed Si1
xGex System . The Si/SiC System

Judy L. Hoyt Massachusetts Institute of Technology

2.8.4 2.8.5

Introduction to Transport Properties...................... 2.8-152 Summary .................................................................... 2.8-153

2.8.1 Introduction Knowledge of the basic electronic properties of silicon-based heterostructures is essential to understand their applications. This chapter is a review of the electronic properties of strained SiGe, strained Si on relaxed SiGe, and a brief introduction to strained Si1
yCy /Si heterostructures. Because the energy band lineups are critical in determining the types of applications of these materials, the emphasis here is on reviewing theoretical and experimental determinations of the energy band lineups (Sections 2.8.2 and 2.8.3). Section 2.8.4 introduces transport properties in such materials, with an eye towards field-effect transistor (FET) applications, though readers are referred to other chapters of this volume for details on transport and FET applications.

2.8.2 Strain and its Impact on Energy Bands Figure 2.8.1(a) schematically illustrates the relaxed, or equilibrium lattice structures for Si, random Si1
xGex alloys, and Ge. The equilibrium lattice parameters a0 for Si and Ge are 5.431 and 5.646 A˚, respectively [1]. This corresponds to a lattice mismatch to Si m ¼ 100 

a0 (alloy)
a0 (Si) a0 (Si)

equal to approximately 4.1% (for pure Ge). When an alloy is formed of Si and Ge the equilibrium lattice parameter can roughly be linearly interpolated between a0 for Si and Ge, though there is a slight negative deviation from Vegard’s law [1]. Figure 2.8.1(b) illustrates the case of pseudomorphic epitaxial growth in which the in-plane lattice parameter of the epitaxial layer compresses or stretches in order to match that of the substrate, and the out-of-plane parameter is elongated or compressed accordingly. Thus, when strained SiGe is grown pseudomorphically on relaxed Si (left-hand side of Figure 2.8.1(b)), the layer experiences in-plane biaxial compression. Conversely, when a thin layer of strained Si is grown on 2.8-143 © 2006 by Taylor & Francis Group, LLC

2.8-144

The Silicon Heterostructure Handbook

(a) Relaxed (equilibrium) lattices

a0

Si

Ge

Si1−xGex

(b) Pseudomorphic growth

Biaxial compression

Biaxial tension

FIGURE 2.8.1 Schematic illustration of the lattice structures for (a) relaxed Si, Si1
xGex, and Ge, and (b) pseudomorphic epitaxial layers of strained SiGe on Si in biaxial compression (left-hand side), and of strained Si on relaxed SiGe in biaxial tension (right-hand side). The symbol a0 refers to the equilibrium lattice parameter of the material.

relaxed SiGe (right-hand side of the figure), the Si experiences biaxial tensile stress. As will be discussed below, the energy band lineups are quite different in these two cases, and determine, to a large extent, the device applications relevant for the two materials structures. Perfect pseudomorphic growth is only possible up to a certain strained layer thickness, above which misfit dislocations form and the strain begins to relax, as discussed elsewhere in this handbook. Si and Ge are completely miscible and the full range of alloy compositions can be grown in single crystal form. This is not true of Si and C, though it is possible to grow alloys of Si1
yCy with up to 2 at.% C in substitutional lattice sites. The lattice mismatch between Si and Si0.5C0.5 is
20%, much larger than that between Si and Si0.5Ge0.5 (þ2%). Si1
yCy layers containing up to a few percent C can be grown pseudomorphically on Si, with the Si1
yCy layer experiencing biaxial tensile stress, analogous to the case of strained Si on relaxed SiGe. Growth of Si1
yCy is discussed elsewhere in this handbook. Perhaps the most well-known electronic property of SiGe alloys is the reduction in the indirect energy bandgap compared to that of Si as Ge is added to the alloy. Figure 2.8.2 shows the energy bandgap difference, DEg ¼ Eg(SiGe)
Eg(Si) between SiGe alloys and Si as a function of the Ge percentage in the alloy. The upper curve corresponds to the data for unstrained or relaxed alloys, measured by Braunstein et al. by optical absorption at 300 K [2]. The conduction band minimum is along the D direction in the Brillion zone for alloy compositions up to roughly 85% Ge [2]. For higher Ge contents, where the magnitude of the bandgap difference increases rapidly with Ge composition, the conduction band minimum appears along the L direction, similar to that for pure Ge. The remainder of the data in Figure 2.8.2 corresponds to DEg for strained SiGe grown on relaxed Si. As shown in the figure, DEg as determined from photocurrent measurements by Lang et al. [3], and extracted from heterojunction bipolar transistors (HBTs) by King et al. [4], is in reasonable agreement with theoretical predictions by People [5]. It is clear that strain makes a large contribution to the bandgap reduction in SiGe. This is true in general in silicon-based heterostructures, where the strain splitting of degeneracies at the band edges tends to close the bandgap relative to the unstrained state, as discussed below. Note that the electron affinity of relaxed SiGe alloys is not well documented in the literature. Morar et al. employed electron-energy-loss

© 2006 by Taylor & Francis Group, LLC

2.8-145

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

Energy bandgap difference Eg(SiGe) − Eg(Si)(eV)

0 Unstrained (Braunstein et al., 300 K)

−0.1 −0.2 −0.3

HBT (King et al., ~ 300K )

−0.4

Strained SiGe on Si Photocurrent (Lang et al., 90 K)

−0.5 −0.6

Calculation (People)

0

20

40

60

80

100

Ge percentage (%)

FIGURE 2.8.2 The energy bandgap difference, DEg ¼ Eg(SiGe)
Eg(Si) between SiGe alloys and Si as a function of the Ge percentage in the alloy. The upper curve is for unstrained alloys, measured by Braunstein et al. by optical absorption at  300 K [2]. The remainder of the data corresponds to DEg for strained SiGe grown on relaxed Si, including photocurrent measurements by Lang et al. (?) [3], and heterojunction bipolar transistors (HBTs) by King et al. (~) [4]. The hatched region represents the range of theoretical predictions due to uncertainties in the values of the deformation potentials [5]. (From C.A. King, J.L. Hoyt, and J.F. Gibbons. Bandgap and transport properties of Si1
xGex by analysis of nearly ideal Si /Si1
xGex /Si heterojunction bipolar transistors. IEEE Trans. Elec. Dev. 36:2093– 2104, 1989. With permission.)

spectroscopy to extract the variation in the conduction band minimum for a range of relaxed SiGe alloy compositions [6], which gives some indication of electron affinity variation. In many applications, it is assumed that the conduction bands of relaxed Si and relaxed SiGe are closely aligned. Figure 2.8.3 illustrates the energy band lineups for some important silicon heterostructures, including (a) compressively strained SiGe on relaxed Si and (b) strained Si grown on relaxed SiGe. The band alignment for strained SiGe on Si (a) is such that almost all of the bandgap difference appears in the valence band [7]. This material is thus ideally suited for the fabrication of npn Si /SiGe/Si heterojunction bipolar transistors, as well as for applications such as p-channel FETs where confinement of holes in the SiGe layer is desired. Strained Si on relaxed SiGe results in a Type II alignment, with electrons preferentially populating the strained Si layers and holes the SiGe layers (Figure 2.8.3(b)). In the figure, DEs represents the strain-induced energy splitting of the conduction band minimum, where the sixfold degenerate conduction band at the D point splits into a set of twofold (D2) and fourfold (D4) degenerate valleys. The constant energy surfaces corresponding to these valleys are shown in Figure 2.8.3(c). DEs is directly proportional to the lattice distortion, and can be calculated from deformation potential theory [8, 9]. It can be shown that DEs corresponds to roughly 67 meV/10% Ge in the substrate, for strained Si on relaxed SiGe, and approximately 66 meV/1% C for strained Si1
yCy on cubic Si [10], as illustrated in Figure 2.8.3(d). The strain-induced splitting of the conduction band degeneracy for strained Si on relaxed SiGe leads to a configuration that is particularly favorable to inplane electron transport [11, 12]. In this case, electrons preferentially occupy the lower-energy D2 conduction band, which has a smaller in-plane effective transport mass than for the case of unstrained Si, where the in-plane effective mass is calculated by averaging over all six valleys. In addition to this effect, intervalley scattering is suppressed by the conduction band energy splitting. These effects contribute to the enhanced electron mobility in strained Si that is being leveraged in CMOS circuits, as discussed in Chapter 5 of this handbook.

© 2006 by Taylor & Francis Group, LLC

2.8-146

The Silicon Heterostructure Handbook

(a) ∆ES

D2

(b)

D4

∆ES ~ 67 mev/ 10%Ge EC

D6

Strained Si1−xGex

D4

D6

D2 Strained Si

Cubic Si

Cubic Si1−x Gex HH & LH

(c)

D4

(d) ∆ES = 66 meV /1%C

[0 0 1]

D6 D2

EC

C ubic Si

S trained Si1−y Cy ∆4Valleys

EV

EV

HH & LH ∆2Valleys

EC

[0 1 0] HH & LH

[1 0 0]

EV

FIGURE 2.8.3 Energy band lineups for various silicon heterostructures, including (a) compressively strained SiGe on relaxed Si and (b) strained Si grown on relaxed SiGe. The heavy solid lines indicate the band edges. DEs represents the strain-induced energy splitting of the conduction band minimum. The conduction band constant energy surfaces are shown in (c), and the band lineup for strained Si1
yCy on cubic (relaxed) Si is illustrated in (d).

(a) Tensile stress EC

D4

D6

D2 EV

LH & HH

LH

EC EV

HH Relaxed

Hydrostatic stress

Biaxial stress

D2 EC

D6

D4 HH

EV

LH & HH

EC EV

LH

(b) Compressive stress

FIGURE 2.8.4 Schematic illustration of the effects of hydrostatic and biaxial stress on the energy bands in Si for (a) tensile and (b) compressive stress.

Biaxial strain can be decomposed into a hydrostatic contribution (equal dilation in all three directions) plus uniaxial strain in the direction normal to epitaxial growth. The hydrostatic component leads to an energy band shift (and change of the bandgap) while the uniaxial component results in a splitting of the conduction and valence band edge degeneracies. Figure 2.8.4 shows schematically the effects of hydrostatic and biaxial stress on the energy bands in Si for both (a) tensile and (b) compressive stress. For example, biaxial tensile stress (a) corresponds to hydrostatic tension combined with uniaxial compression in the z-direction. For this case, a uniform hydrostatic stretching of the lattice shifts the conduction and valence band edges to lower energies relative to their equilibrium positions, while the uniaxial contribution induces a splitting that does not affect the average band energy. The D2 and D4 bands move in opposite directions and the D2 level moves by twice the amount as the D4 level. One can

© 2006 by Taylor & Francis Group, LLC

2.8-147

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

also see from the figure that in the absence of other (e.g., chemical) effects, biaxial tension favors the introduction of a conduction band offset while biaxial compression tends to produce a valence band offset. This is due to the particular way in which hydrostatic and uniaxial stress affect the bands. Strain effects are only part of the story of the energy band lineup at a heterointerface. Another effect comes from the chemical difference between the two semiconductor materials. Van de Walle and Martin were the first to discuss both the chemical and strain effects on the band alignment, and presented a methodology for calculating the valence band offsets in the Si /Ge system for various strain states [13]. Figure 2.8.5 shows the energy bands as calculated by Van de Walle for both strained SiGe on cubic Si (biaxial compression) and strained SiGe on cubic Ge (biaxial tension). For thorough theoretical reviews of the calculation of energy band lineups and the impact of stress on the band offsets, the reader is referred to Refs. [13–16]. Rieger and Vogl [15] and Schaffler [16] calculated and plotted the theoretical conduction and valence band offsets for a Si1
yGey strained layer on a Si1
xGex substrate.

2.8.3 Measurements of Energy Band Lineups For compressively strained SiGe on cubic Si with Ge contents below 50% it is reasonably well established that the conduction band offset is less than 20 meV. In fact, rigorous studies using photoluminescence suggest that the Si and strained SiGe conduction bands are very close to each other for a Ge composition of 30% [17]. In the case of strained Si /strained SiGe/relaxed SiGe heterostructures, the uncertainty in the theoretical values of the band lineups can be as high as +100 meV, particularly for higher Ge contents, which is too large for device applications. For example, in heterojunction bipolar transistor applications, the collector current varies exponentially with the band offset DEg /kT, and in FETs the threshold voltage is often proportional to an energy band offset in the heterostructure. Hence, accurate determination of

Strained Si1−xGex grown on cubic Si (0 0 1)

Strained Si1−xGex on cubic Ge (0 0 1)

2.0

2.0 Conduction bands

L

L D4 Conduction bands

Energy (eV)

D2 1.17 1.0 0.84

D4

1.0

Eg (Si1−x Gex)

0.74 D2

Valence bands

0.0

0.0 0 Si

0.5 Ge fraction (x)

1 Ge

0 Si

Valence bands

0.5 Ge fraction (x)

1 Ge

FIGURE 2.8.5 Energy bands as calculated by Van de Walle and Martin [13] for both strained SiGe on cubic Si (biaxial compression) and strained SiGe on cubic Ge (biaxial tension). The three strain-split valence bands represent the heavy hole, light hole, and split-off hole bands. The dashed lines represent the weighted average positions of the conduction and valence bands before the uniaxial strain splitting is taken into account. It should be noted that the data of Braunstein et al. [2] were used to place the weighted average conduction band relative to the valence bands. (From G.G. Van de Walle and R.M. Martin. Theoretical calculations of heterojunction discontinuities in the Si /Ge system. Phys. Rev. B 34: 5621–5634, 1986. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-148

The Silicon Heterostructure Handbook

such quantities is required. The following sections discuss measurements of the energy band lineups in silicon heterostructures.

The Strained Si/Strained Si1
yGey/Relaxed Si1
xGex System There are a number of methods used for estimating energy band offsets at semiconductor heterojunctions, including methods such as photoluminescence and x-ray photoelectron spectroscopy (XPS). XPS generally has error bars on the order of 0.1 eV, too large for electronic device applications. Electrical techniques such as admittance spectroscopy and capacitance voltage profiling of reverse-biased Schottky diodes are popular methods [18, 19], though care must be taken as both techniques can be influenced by the presence of deep levels within the depletion region or interface states that can impact the magnitude of the extracted energy band offset. A variation on the Schottky diode methods that is particularly useful for thin heterostructures of interest in FETs is the MOS capacitance–voltage (C–V ) method, as applied to MOS capacitors or MOSFETs [20–22]. By simulating and fitting the measured gate-to-channel capacitance characteristics of strained Si MOSFETs, Welser was able to extract values for the conduction and valance band offsets, DEc and DEv , for strained Si /relaxed SiGe heterojunctions [21]. These results are illustrated in Figure 2.8.6. As shown in the figure, there is generally good agreement between the magnitude of the extracted band offsets (symbols) and the theoretical calculations (lines). The bandgap of strained Si can be estimated by

∆EC (eV)

0.30

0.20

(a) Measurements by J. Welser

0.10 Calculated People and Bean (APL 48(8),1986) 0.00 0.30

∆EV (eV)

(b)

0.20

0.10

0.00 0.00

Calculated Van de Walle and Martin (PR B 34(8), 1986) 0.10

0.20 Ge fraction (x)

0.30

0.40

FIGURE 2.8.6 Conduction (a) and valence (b) band offsets for strained Si/relaxed SiGe heterojunctions determined by Welser [21]. Solid symbols are experimentally extracted from modeling of C–V characteristics measured for strained Si MOSFETs. The band alignment is as shown in Figure 2.8.3(b). (From J.J. Welser. The application of strained Si /relaxed-Silicon germanium heterostructures to metal-oxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-149

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

combining these data with the measured data for the bandgap of relaxed SiGe from Braunstein, according to Eg(strained Si) ¼ Eg(relaxed SiGe)
DEc þ DEv. Figure 2.8.7 illustrates the resulting estimate of the strained Si bandgap as a function of the Ge fraction of the SiGe substrate. The results are in good agreement with the calculations from People and Bean [7]. Note that the error bars in the figure represent the uncertainty in the fitting as opposed to an absolute error. The impact of uncertainties in the strain-induced density of states and quantum corrections on such analysis is discussed in more detail below in the analysis of dual-channel structures. A particularly exciting heterostructure for MOSFET applications is the dual-channel structure [23, 24] shown schematically in Figure 2.8.8. This structure has a top strained Si layer that forms a high-mobility electron channel and a slightly buried, strained high-Ge-content SiGe channel that serves as a high-hole mobility channel. The high Ge content in the buried layer is made possible in part by the relaxed SiGe layer that reduces the overall mismatch. It has been demonstrated that both high electron and hole mobility enhancements can be achieved simultaneously in dual-channel structures [25]. It is critical to know the energy band offsets in such structures in order to predict hole confinement, mobility, and device properties such as threshold voltage and subthreshold slope. The valence band offset, DEv , between the strained Si and strained SiGe layers is particularly important. For the purpose of extracting this energy band offset, p-type heterostructures shown schematically in Figure 2.8.8 have been fabricated [26]. Figure 2.8.9(a) illustrates the energy band diagram for these MOS capacitors at flatband (solid lines) and negative bias (dashed lines). Under increasing negative bias it is clear that holes first accumulate in the buried SiGe well and then at the oxide-strained Si interface. The resulting C
V curves of these MOS capacitors are illustrated in Figure 2.8.9(b). The plot is divided into three regions: inversion on the surface oxide–silicon interface (gate voltages greater than zero) with electrons in the strained Si layer, accumulation of holes in the SiGe well, and accumulation of holes at the oxide–silicon interface. The width of the characteristic plateau region is indicative of the valence band offset, DEv , as shown in the figure. This feature is utilized in order to extract the valence band offset. One-dimensional simulations have been performed to fit the experimental data using the Dessis device simulator [27]. Quantum effects are taken into account in the simulation using the density

1.20 1.15

Calculated People and Bean (1986)

Eg (eV)

1.10 1.05 1.00 0.95 0.90 0.00

Relaxed Strained Si Si1−xGex Eg Bandgap of strained Si on relaxed Si1−x Gex 0.10

0.20 Ge fraction (x)

0.30

0.40

FIGURE 2.8.7 The bandgap energy of strained Si on relaxed SiGe as determined by Welser [21], by combining the data in Figure 2.8.6 with the data for the bandgap of relaxed SiGe from Braunstein et al. [2], according to Eg(strained Si) ¼ Eg(relaxed SiGe)
DEc þ DEv. (From J.J. Welser. The application of strained Si /relaxed-silicon germanium heterostructures to metal-oxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-150

The Silicon Heterostructure Handbook

TiN gate Gate oxide ~ 4 nm p Si (strained) ~ 7 nm

∆EC

∆EV

p Si1−y Gey (Strained) ~ 12 nm p Si1−x Gex (Relaxed) ~ 500 nm p graded Si1−x Gex p+ Si substrate EV

EC

FIGURE 2.8.8 Schematic illustration of an MOS capacitor formed on a dual-channel heterostructure, and associated energy band diagram. This structure has a top strained Si layer that serves as a high-mobility electron channel and a slightly buried, strained high-Ge-content SiGe layer that serves as an enhanced hole mobility channel. Flatband High bias

(a)

EC EF ∆EV

1

EV

(b)

Normalized capacitance (C/Cox)

COX

100 kHz 300 K TSi

0.8

0.6

C⬘OX ∆EV

0.4

0.2

Accumulation Si−oxide interface

0 −4

−3

Cmin

SiGe well Inversion −2 −1 0 Gate voltage (V)

1

2

FIGURE 2.8.9 (a) Energy band diagram at flatband (solid lines) and negative gate bias (dashed lines), and (b) C
V data for a dual-channel MOS capacitor shown schematically in Figure 2.8.8, with y ¼ 0.6 and x ¼ 0.3. The plateau feature in the C
V characteristics, observed when holes accumulate in the SiGe well, is related to the magnitude of the valence band offset DEv. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1
yGey on relaxed Si1
xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

© 2006 by Taylor & Francis Group, LLC

2.8-151

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

∆EV −20 meV

4 ⫻10−10

Tox = 4.6 nm TSi = 6.6 nm

Capacitance (F)

Na = 1016 cm−3 Area = 250 µm2 −10

3 ⫻10

∆EV +20 meV

2 ⫻10−10

1 ⫻10−10 −2.5

Measured data Simulation ∆EV = 435 meV Simulation ∆EV = 435 ± 20 meV −2

−1.5 −1 −0.5 Gate voltage (V)

0

0.5

FIGURE 2.8.10 Measured (symbols) and simulated (lines) C–V characteristics for an MOS structure containing strained Si/strained Si0.4Ge0.6 on a relaxed Si0.7Ge0.3 substrate. The dashed lines show simulations for DE v ¼ 435 + 20 meV. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1
yGey on relaxed Si1
xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

gradient quantum correction model. Figure 2.8.10 compares measured (symbols) and simulated (lines) C–V characteristics for a structure consisting of strained Si /strained Si0.4Ge0.6 on a relaxed Si0.7Ge0.3 substrate. The dashed lines show simulations for DEv ¼ 435 + 20 meV, illustrating that the quality of the fit is very sensitive to small changes in the valence band offset. It has been found that the C–V simulations are sensitive to the values used for the effective valence band density of states Nv in the strained Si. Note that this density of states decreases with increasing strain and Ge content due to the splitting and deformation of the valence bands. Use of the theoretical values for Nv for strained Si produces a much better fit to the C–V data in the portion of the curve corresponding to the population of the strained Si valence bands [26]. Analysis indicates that for this sample, a 15 meV difference in the extracted value of DEv can result from the use of the unstrained values of the density of states in place of the strained values. It is thus important to use a self-consistent parameter set including both Nv and DE v when modeling dual-channel MOSFETs. Figure 2.8.11 illustrates the extracted DE v for strained Si /strained Si1
yGey on relaxed Si1
xGex heterostructures as a function of the compositions x and y. The valence band offset increases with both composition and strain in the Si1
yGey layer. Linear fits to the data yield an average slope of roughly 100 meV/10% Ge in the strained Si1
yGey layer. This follows the theoretical trend, which displays a slope of  75 meV/10% Ge.

The Si/Si1
yCy System Figure 2.8.3(d) illustrates the band lineup for strained Si1
yCy grown on Si, for C compositions less than 2 at.%. Such Si1
yCy layers are strained in biaxial tension. The situation is complementary to that of strained SiGe grown on Si, and the Si1
yCy /Si band lineup, with a conduction band offset and little valence band offset is ideal for the fabrication of pnp Si /Si1
yCy /Si HBTs [28]. Theoretical predictions of conduction band offsets have been reported to accompany the addition of C to Si [29], and there has been some controversy concerning the presence of large conduction band offsets in the SiGeC/Si system [22, 30–32]. The estimated conduction band offset between strained Si1
yCy and Si is approximately 65 meV/at.% C. A combination of MOS C–V analysis to extract DEc, similar to that employed above, and

© 2006 by Taylor & Francis Group, LLC

2.8-152

The Silicon Heterostructure Handbook

600

Valence band offset (meV)

500

400

Bulk Si substrate

300

200

0.40 Substrate Ge (x) 100

0.31 0.19

0 0

0.2 0.4 0.6 0.8 Ge Fraction y in strained Si1−yGey Layer

FIGURE 2.8.11 Extracted DE v for strained Si/strained Si1
yGey on relaxed Si1
xGex heterostructures as determined by fitting MOS C
V analysis. Theoretical values for the effective density of states in strained Si and strained Si1
yGey were used in the extractions. (From C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1
yGey on relaxed Si1
xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004–7, pp. 99–109, 2004. Pennington, N.J. With permission.)

temperature-dependent measurements of the collector current in pnp Si /Si1
yCy /Si HBTs to extract DEg, indicates that for strained Si1
yCy on Si, most of the band offset is in the conduction band [33]. These results are summarized in Figure 2.8.12. Note that when plotted as a function of the magnitude of the lattice mismatch to silicon (upper x-axis in the figure), the magnitude of the bandgap offset per percent mismatch for strained Si1
yCy on Si is close to that for strained SiGe on Si.

2.8.4 Introduction to Transport Properties Although minority carrier diffusion in SiGe has been studied for modeling of npn Si /SiGe HBTs [35–37], the greatest excitement exists today for understanding transport in strained Si and strained SiGe layers for high-speed FET applications, including digital CMOS. For the Si conduction band, it has already been mentioned that the biaxial tensile strain-induced splitting of the degeneracies at the D point is beneficial to in-plane electron transport. There is little deformation of the Si conduction band ellipsoids themselves, but energy shifting and repopulation of the valleys in k-space [15]. The resulting enhancement in electron mobility by a factor of  1.8 has been the subject of investigation for CMOS applications [38] as discussed elsewhere in this volume. Although models have been used to explain the measured strain dependence of peak electron mobility enhancements in strained Si /relaxed SiGe n-MOSFETs [12], ab initio calculations have not been able to account for the enhanced electron mobilities in strained Si n-MOSFETs measured at high vertical electric fields [39], and further work aimed at understanding these effects is required. In addition to the shifts in band edge positions, the shape of the energy bands can change under strain and alloying effects. The valence band is considerably more complex than the conduction band, undergoing warping, splitting, and deformation with strain. Reviews of calculations of the valence band structure in strained SiGe can be found in Refs. [40–43]. To first order as the valence bands split the mass of the uppermost band near k ¼ 0 is reduced, and this is associated with an enhanced in-plane hole mobility in biaxial tensile-strained Si on relaxed SiGe [44]. Recent three-dimensional calculations

© 2006 by Taylor & Francis Group, LLC

2.8-153

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

Magnitude lattice mismatch to Si (%) 0

0.2

0.4

0.6

0.8

0

Band offset (meV)

Fit to HBT data ∆Eg (Si0.9Ge0.1)

−40

Fit to MOS-CV data

−80

∆Ec : MOS CV(Ref. 22) ∆Ec : MOS CV(Ref. 34) ∆Eg : HBT's (No BGN correction) ∆Eg : HBT's (BGN correction)

−120

0

0.5

1 1.5 Substitutional C (at.%)

2

FIGURE 2.8.12 Summary of band offsets for strained Si1
yCy on Si heterojunctions. The solid line is a fit to the DEg values extracted from pnp HBTs. (From D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Novel epitaxial p-Si /n-Si1
yCy / p-Si heterojunction bipolar transistors. Technical Digest of International Electron Devices Meeting 2000, pp. 749– 752. With permission.) The dashed line is a fit to the DEc values extracted from MOS C
V analysis. The estimated conduction band offset between strained Si1
yCy and Si is approximately 65 meV/at.% C. The bandgap offset DEg for Si0.9Ge0.1/Si (mismatch ¼ 0.4%) is shown (6) for reference. (From D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Effect of band alignment and density of states on the collector current in p-Si /n-Si1
yCy /p-Si HBTs. IEEE Trans. Elec. Dev. 50:425–432, 2003. With permission.)

of the Si band structure under ‘‘uniaxial’’ compressive stress indicate a complex behavior that enhances the hole mobility for transport in the direction of compression [45]. The addition of Ge to SiGe leads to a more Ge-like valence band with a higher curvature and reduced effective mass, as well as to strainenhanced mobilities for pseudomorphic growth. Hole mobilities increase dramatically for strained SiGe with Ge contents above 50%. The highest mobilities in the silicon heterostructure system have been obtained for high-Ge-content strained Si1
yGey or strained Ge grown on relaxed Si1
xGex layers with y > x [46].

2.8.5 Summary There has been considerable progress in the understanding of the band structure and basic electronic properties of silicon heterostructures over the years. Strain plays a critical role in determining the energy band structure and the lineup of the bands at strained SiGe/Si and strained Si /SiGe heterojunctions. Research continues in this area as interest in the use of strained Si and SiGe in FET applications grows. More experimental and theoretical work is needed to formulate an accurate picture of transport in strained Si and strained SiGe heterostructures, particularly in inversion layers where electric field quantization is also important, and this is currently an exciting area of investigation.

Acknowledgments I am indebted to a number of talented people with whom I have worked in the area of silicon heterostructures, and whose efforts are represented in this chapter. In particular I would like to thank past collaborators including James Gibbons, Clifford King, Jeff Welser, Kern Rim, Shinichi Takagi, and Dinkar Singh, as well as present collaborators, especially Cait Ni Chleirigh, Oluwamuyiwa Olubuyide, Dimitri Antoniadis, and Eugene Fitzgerald.

© 2006 by Taylor & Francis Group, LLC

2.8-154

The Silicon Heterostructure Handbook

References 1. R.W. Olesinski and G.J. Abbaschian. Bull. Alloy Phase Diagrams 5:180, 1984. 2. R. Braunstein, A.R. Moore, and F. Herman. Intrinsic optical absorption in germanium–silicon alloys. Phys. Rev. 109:695–710, 1958. 3. D.V. Lang, R. People, J.C. Bean, and A.M. Sergent. Measurement of the band gap of Si1
xGex /Si strained-layer heterostructures. Appl. Phys. Lett. 47:1333–1335, 1985. 4. C.A. King, J.L. Hoyt, and J.F. Gibbons. Bandgap and transport properties of Si1
xGex by analysis of nearly ideal Si/Si1
xGex /Si heterojunction bipolar transistors. IEEE Trans. Elec. Dev. 36:2093–2104, 1989. 5. R. People. Indirect band gap of coherently strained GexSi1
x bulk alloys on (0 0 1) silicon substrates. Phys. Rev. B 32:1405–1408, 1985. 6. J.F. Morar, P.E. Batson, and J. Tersoff. Heterojunction band lineups in Si–Ge alloys using spatially resolved electron-energy-loss spectroscopy. Phys. Rev. B 47:4107–4110, 1993. 7. R. People and J.C. Bean. Band alignments of coherently strained GexSi1
x /Si heterostructures on (0 0 1) Gey Si1
y substrates. Appl. Phys. Lett. 48:538–540, 1986. 8. C. Herring and E. Vogt. Phys. Rev. 101:944, 1956. 9. I. Balslev. Phys. Rev. 143:636, 1966. 10. J.L. Hoyt. Substitutional carbon incorporation and electronic characterization of Si1
yCy /Si and SiGeC/Si heterojunctions, in Silicon–Germanium Carbon Alloys: Growth, Properties and Applications, Taylor and Francis, New York, 2002, pp. 59–89. 11. T. Vogelsang and K.R. Hofmann. Electron transport in strained Si layers on Si1
xGex substrates. Appl. Phys. Lett. 63:185–187, 1993. 12. S. Takagi, J.L. Hoyt, J. Welser, and J.F. Gibbons. Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 80:1567–1577, 1996. 13. G.G. Van de Walle and R.M. Martin. Theoretical calculations of heterojunction discontinuities in the Si /Ge system. Phys. Rev. B 34:5621–5634, 1986. 14. R. People. Physics and applications of Gex Si1
x /Si strained layer heterostructures. IEEE J. Quantum Electronics 22:1696–1710, 1986. 15. M.M. Rieger and P. Vogl, Electronic-band parameters in strained Si1
xGex alloys on Si1
yGey substrates. Phys. Rev. B 48:14276–14287, 1993. 16. F. Schaffler, High-mobility Si and Ge structures. Semicond. Sci. Technol. 12:1515–1549, 1997. 17. M.L.W. Thewalt, D.A. Harrison, C.F. Reinhart, J.A. Wolk, and H. Lafontaine. Type II band alignment in Si1
xGex /Si(0 0 1) quantum wells: the ubiquitous type I luminescence results from band bending. Phys. Rev. Lett. 79:269–272, 1997. 18. R.E. Cavicchi, D.V. Lang, D. Gershoni, A.M. Sergent, J.M. Vandenberg, S.N.G. Chu, and M.B. Panish. Admittance spectroscopy measurement of band offsets in strained layers of InxGa1
x As grown on InP. Appl. Phys. Lett. 54:739–741, 1989. 19. H. Kroemer, W.-Y. Chen, J.S. Harris Jr. and D.D. Edwall. Measurement of isotype heterojunction barriers by C–V profiling. Appl. Phys. Lett. 36:295–297, 1979. 20. S.P. Voinigescu, K. Iniewski, R. Lisak, C.A.T. Salama, J.P. Noel, and D.C. Houghton. New technique for characterization of Si /SiGe layers using heterostructure MOS capacitors. Solid-State Electron. 37:1491, 1994. 21. J.J. Welser. The application of strained Si /relaxed-silicon germanium heterostructures to metaloxide-semiconductor field-effect transistors. Ph.D. Thesis. Stanford, 1994. 22. D.V. Singh, K. Rim, T.O. Mitchell, J.L. Hoyt, and J.F. Gibbons. Measurement of the conduction band offsets in Si /Si1
x
yGexCy and Si /Si1
yCy heterostructures using metal-oxide-semiconductor capacitors. J. Appl. Phys. 85:978–984, 1999. 23. C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Hole mobility enhancements in strained Si /Si1
yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1
xGex (x < y). Appl. Phys. Lett. 79:4246–4248, 2001.

© 2006 by Taylor & Francis Group, LLC

Electronic Properties of Strained Si/SiGe and Si1
yCy Alloys

2.8-155

24. C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, and E.A. Fitzgerald. Channel engineering of SiGe-based heterostructures for high mobility MOSFETs, in Materials Issues in Novel Si-Based Technology. Symposium (Materials Research Society Symposium Proceedings) Vol. 686:113–118, 2002. 25. J. Jung, M.L. Lee, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis. Implementation of both high-hole and electron mobility in strained Si /strained Si1
yGey on relaxed Si1
xGex / (x < y). IEEE Electron Dev. Lett. 24:460–462, 2003. 26. C. Ni Chleirigh, C. Jungemann, J. Jung, O.O. Olubuyide, and J.L. Hoyt. Extraction of band offsets in strained Si /strained Si1
yGey on relaxed Si1
xGex dual-channel enhanced mobility structures. Proceedings of the ECS Symposium on SiGe: Materials, Processing and Devices, October 2004, PV 2004 –7, pp. 99–109, 2004. Pennington, N.J. 27. Dessis: Comprehensive semiconductor device simulator, Integrated Systems Engineering AG, Switzerland, http://www/ise.com. 28. D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Novel epitaxial p-Si /n-Si1
yCy /p-Si heterojunction bipolar transistors. Technical Digest of International Electron Devices Meeting 2000, pp. 749–752. 29. A.A. Demkov and O.F. Sankey. Theoretical investigation of random Si–C alloys. Phys. Rev. B 48: 2207–2214, 1993. 30. B.L. Stein, E.T. Yu, E.T. Croke, A.T. Hunger, B. Laursen, A.E. Bair, J.W. Mayer, and C.C. Ahn. Band offsets in Si /Si1
x
yGexCy heterojunctions measured by admittance spectroscopy. Appl. Phys. Lett. 70:3413–3415, 1997. 31. B.L. Stein, E.T. Yu, E.T. Croke, A.T. Hunger, B. Laursen, A.E. Bair, J.W. Mayer, and C.C. Ahn. Measurement of band offsets in Si /Si1
xGex and Si /Si1
x
yGexCy heterojunctions. J. Vac. Sci. Technol. B15:1108–1111, 1997. 32. D.V. Singh, K. Rim, T.O. Mitchell, J.L. Hoyt, and J.F. Gibbons. Admittance spectroscopy analysis of the conduction band offsets in Si /Si1
x
yGexCy and Si /Si1
yCy heterostructures. J. Appl. Phys. 85:985–993, 1999. 33. D.V. Singh, J.L. Hoyt, and J.F. Gibbons. Effect of band alignment and density of states on the collector current in p-Si /n-Si1
yCy /p-Si HBTs. IEEE Trans. Elec. Dev. 50:425–432, 2003. 34. K. Rim, T.O. Mitchell, D.V. Singh, J.L. Hoyt, J.F. Gibbons, and G. Fountain. Metal-oxide semiconductor-capacitance–voltage characteristics and band offsets for Si /Si1
yCy/Si heterostructures. Appl. Phys. Lett. 72: 2286–2288, 1998. 35. J. Poortmans, M. Caymax, A. Van Ammel, M. Libezny, and J. Nijs. Study of the transversal electron mobility in heterojunction bipolar transistors with strained Si1
xGex-base. Semiconductor Heterostructures for Photonic and Electronic Applications Symposium, 1993, pp. 409–414. 36. A. Gruhle, A. Schuppen, H. Kibbel, and U. Konig. Minority carrier mobility and density of states in SiGe HBTs determined by a new method. Compound Semiconductors 1994. Proceedings of the Twenty-First International Symposium, 1995, pp. 253–258. 37. T. Ghani. Characterization of Minority Carrier Transport and Heavy Doping Effects in n-Si /p-SiGe/ n-Si Heterojunction Bipolar Transistors, Ph.D. Thesis, Stanford University, 1994. 38. J.L. Hoyt, H.M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E.A. Fitzgerald, and D.A. Antoniadis. Strained Silicon MOSFET Technology. Tech. Digest IEEE International Electron Devices Meeting, Dec. 2002, pp. 23–26, and references therein. 39. M.V. Fischetti, F. Gamiz, and W. Hansch. On the enhanced electron mobility in strained-silicon inversion layers. J. Appl. Phys. 92:7320–7324, 2002. 40. J.M. Hinckley and J. Singh. Hole transport theory in pseudomorphic SiGe alloys grown on Si(001) substrates. Phys. Rev. B 41:2912–2926, 1990. 41. M.V. Fischetti and S.E. Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys. 80:2234–2252, 1996. 42. T. Manku and A. Nathan, Energy-band structure for strained p-type SiGe. Phys. Rev. B 43: 12634– 12637, 1991.

© 2006 by Taylor & Francis Group, LLC

2.8-156

The Silicon Heterostructure Handbook

43. T. Manku and A. Nathan. Valence energy-band structure for strained group-IV semiconductors. J. Appl. Phys. 73:1205–1213, 1993. 44. D.K. Nayak and S.K. Chun. Low-field hole mobility of strained Si on (001) SiGe substrate. Appl. Phys. Lett. 64:2514–2516, 1994. 45. M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, and K. Zawadzki. Understanding Stress Enhanced Performance in Intel 90 nm CMOS Technology, Proceedings of IEEE Symposium on VLSI Technology, 2004, pp. 118–119. 46. M.L. Lee and E.A. Fitzgerald. Optimized strained Si /strained Ge dual-channel heterostructures for high mobility p- and n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting 2003, pp. 433–436.

© 2006 by Taylor & Francis Group, LLC

2.9 Carbon Doping of SiGe

H. Jo¨rg Osten University of Hanover

2.9.1 Introduction............................................................ 2.9-157 2.9.2 Basic Considerations .............................................. 2.9-157 2.9.3 Growth of C-Containing Alloys ............................ 2.9-158 2.9.4 Control of Dopant Diffusion by Adding Carbon ....................................................... 2.9-160 2.9.5 Strain Manipulation in Si1
x
yGexCy Layers ....... 2.9-162 2.9.6 Microscopic Structure of SiGeC Layers................ 2.9-163 2.9.7 Strain-Stabilized Layers with High C Concentration ......................................................... 2.9-163 2.9.8 Thermal Stability .................................................... 2.9-164 2.9.9 Impact of Carbon on Electrical Layer Properties ................................................................ 2.9-164 2.9.10 Summary ................................................................. 2.9-165

2.9.1 Introduction Silicon is the most important semiconductor material in the microelectronic industry. There have been several attempts to increase the material variety that is compatible with Si technologies. Silicon– germanium alloys and heterojunctions will extend the performance of future Si-based devices. However, the Si1
xGex on Si(0 0 1) system exhibits severe limitations. Examples include the existence of a critical thickness for perfect pseudomorphic growth, which depends on the amount of germanium (the introduced strain). In addition, the main band offset between Si and strained SiGe is located in the valence band, that is, this system is much better suited for hole channel than for electron channel devices. Recently, it was shown that Si1
yCy and Si1
x
yGexCy layers can also be grown pseudomorphically on Si(0 0 1). This new material might alleviate some of the limitations of SiGe on Si(0 0 1). Research on highly supersaturated, C-containing alloys on silicon substrates started only a few years ago. Meanwhile, knowledge has been accumulated on growth, strain manipulation, thermal stability, and carbon effects on band structure and charge carrier transport [1–3]. Low carbon concentrations can also be used to control diffusion of dopants without affecting strain and band alignment. This unique property has already found its first device application, the SiGe:C heterojunction bipolar transistor (HBT) [4].

2.9.2 Basic Considerations Epitaxial growth of C-containing Si1
yCy or Si1
x
yGexCy alloys is more complex than SiGe growth. Several additional problems have to be addressed [5, 6]: Unlike to the Si /Ge system, silicon and carbon are not miscible. According to the binary Si

C phase diagram, stoichiometric SiC (silicon carbide) is 2.9-157 © 2006 by Taylor & Francis Group, LLC

2.9-158

The Silicon Heterostructure Handbook

the only stable compound. Any alloy with a smaller C concentration is thermodynamically metastable. Such alloy layers can be achieved by kinetically dominated growth methods, like molecular beam epitaxy (MBE) [5, 6], various kinds of chemical vapor deposition (CVD) at relatively low temperatures [7], or solid-phase epitaxy (SPE). The SPE approach is based on recrystallization of amorphous mixtures of Si / Ge /C obtained mainly by ion implantation with well-defined temperature profiles [8, 9]. All of these methods generally work under far from thermodynamic equilibrium conditions, allowing a kinetic stabilization of metastable phases. Although the bulk solubility of carbon in silicon is small (3  1017 atoms/cm3 at the melting point of Si [10]), epitaxial layers with more than 1% C can be fabricated. Once deposited as a random alloy at low temperatures (500–7008C), the Si1
yCy appears to be able to withstand anneals up to significantly higher temperatures (up to 9008C) [11, 12]. Contrary to the Si /Ge alloy, carbon in silicon can easily form interstitial defect complexes. Thus, one of the most crucial questions is the relationship between substitutional and interstitial carbon incorporation, which has a large impact on the electrical properties of these layers. Substitutionally incorporated C atoms allow strain manipulation, including the growth of strain-compensated or inversely
C system is the extreme mismatch of the strained Si1
x
yGexCy layers. The striking feature of the Si
Si

Si and Si

C bond lengths. Disordered alloys will exhibit large local strain. Local ordering will occur due to atomic size differences.

2.9.3 Growth of C-Containing Alloys Any alloy with a substitutional C concentration above the bulk solubility limit is thermodynamically metastable. In equilibrium, the solid solubility of a substitutional C impurity (i.e., the value of y for Si1
yCy) is given by: y ¼ exp[
(E
m)/kT ], where E is the energy of a substitutional C atom in Si, m the chemical potential, and k the Boltzmann constant. The concentration of C is limited by the formation of SiC precipitates, which prevents m from rising higher than the value corresponding to a SiC reservoir [13]. However, during growth it is not the equilibrium bulk solubility that is important but rather a ‘‘surface solubility.’’ The increased solubility results from two factors [13]: First, the presence of a surface breaks the bulk symmetry and therefore creates sites for adatoms that are energetically nonequivalent to bulk sites. The stress associated with the atomic size mismatch between C and Si is partially relieved and the energy of the substitutional C decreases smoothly as it approaches the surface. Second, there is a stress field near the surface, associated with the atomic reconstruction there [14]. The coupling of the carbon stress to this spatially varying surface stress substantially lowers the carbon energy on certain sites. For a (21) reconstructed Si(0 0 1) surface there are two nonequivalent sites: One lies beneath the surface dimer (a site), and the other site lies between the dimers (b site). As discussed by Kelires and Tersoff [14], the a sites are under compressive stress. Thus, they are favorable sites for a smaller atom such as C. The adatoms are rapidly buried on subsurface sites, which serve like a sink, and thus immobilized. The high carbon density near the surface is frozen in as the crystal grows, permitting the growth of a highly supersaturated solid-solution, e.g., high carbon concentrations in silicon or silicon–germanium. Tersoff used an empirical many-body potential to model the interaction between atoms in the Si1
yCy system [13]. Including also the surface reconstruction, he found an enhancement of 104 over equilibrium bulk solubility. Thus, the surface solubility of carbon can easily be in the percentage range. The lowest-energy position of carbon in Si is found to be the substitutional site. In addition, the observed activation energy for the diffusion of substitutional carbon (3 eV) is quite large [7]. This is the origin for the achieved stability of these metastable alloys. Carbon precipitation is a rare process that has been reported to occur only in the presence of a supersaturation of silicon self-interstitials or oxygen [15]. The mechanism described here has another possible consequence, in addition to enhanced solubility. If the C atoms have sufficient mobility within the first layers, they will lie only on sites beneath the dimers, with negligible occupancy of the other sites. This ordering should not be lost as the layers are buried deeper, if the C is immobile in deeper layers. First indications of local ordering in Si1
yCy layers have been observed [16, 17].

© 2006 by Taylor & Francis Group, LLC

2.9-159

Carbon Doping of SiGe

Substrate C concentration

The carbon substitutionality (nS /n0) is strongly influenced by the growth conditions, such as temperature and the Si growth rate. Similar trends were observed for MBE and CVD growth [18–21]. All authors found a significant decrease of the substitutional carbon concentration with increasing growth temperature or decreasing growth rate. Osten et al. [18] proposed the following simple model: If the temperature is high enough for Si epitaxy, one can assume that all arriving C adatoms are rapidly incorporated in positions beneath the Si dimers. When another Si adatom arrives above a surface position filled with a C atom, either (i) it migrates further on the surface, or (ii) it binds to the carbon (‘‘freezing in’’ of the C atom on lattice position), or (iii) it kicks the C atom out of a lattice position, forming a Si

C interstitial complex or a C

C dimer on the surface. The substitutional versus interstitial carbon concentration is therefore primarily controlled by process (iii), i.e., by all parameters affecting the formation of the interstitial defect complexes [22]. Desorption processes are likely excluded for the used growth temperatures. Recently, Kelires and Kaxiras [23] reported atomistic calculations of the surface structure of Si with substitutional carbon atoms. One of their important results is that the lowest energy configuration involves the C atoms in the very top layer of the Si(0 0 1) surface, forming dimers in the (2  1) reconstruction. The authors suggest that the strong preference of C to remain on the surface is due to the bond between the two threefold coordinated C atoms (similar to the Si surface atoms forming dimers). The ability of C to form double bonds makes this a low-energy structure. This has important consequences. It implies that if C atoms have a chance to form C

C dimers upon arrival on the Si(0 0 1) surface, their subsequent incorporation in the growing film will be limited. The formation of such dimers depends on several factors, including the frequency of surface hops (i.e., the growth temperature), the time before further deposition immobilizes the atoms (i.e., the growth rate), and the probability of finding another C atom (i.e., the total carbon concentration). In addition, some carbon evaporation sources deliver larger C fragments. Therefore, we have to assume different incorporation kinetics for different C sources. Osten et al. [22] extended their model for the incorporation of substitutional C during epitaxial growth as a function of various parameters. Based on that model one should expect for a certain Si growth rate and C flux the behavior illustrated schematically in Figure 2.9.1. Generally, we can distinguish three different regions (labeled A to C in Figure 2.9.1). In the first region, we have complete substitutional incorporation, independent of the growth temperature. For the highest temperatures in this region, we might find a slight decrease in the substitutional carbon concentration (ns) with increasing temperature. This behavior is similar to the one reported by Zerlauth et al. [20]. In the middle region (B), we observe a relatively strong decrease of ns with increasing growth temperature, similar to the results reported in Refs. [18, 19]. For even higher growth temperatures (region C), almost no substitutional carbon incorporation should be possible. If the substrate temperature is too high, a metastable regime no longer exists, and some deterioration in crystal quality (like a transition to 3D growth or a mixed alloy carbide phase) occurs. The observed behavior can be described using the growth rate r (limiting the time available for defect formation), the total carbon concentration

A

B

C

Temperature

FIGURE 2.9.1 Schematic representation of substitutional carbon incorporation in Si1
yCy layers as a function of growth temperature for given and constant Si and C fluxes. Three distinct regions are marked.

© 2006 by Taylor & Francis Group, LLC

2.9-160

The Silicon Heterostructure Handbook

n0, the growth temperature T, and an energy barrier Ec. Any incorporated C atom has to overcome this barrier to form an interstitial C-containing defect complex. The frequency of defect formation k is given by: k ¼ k0 exp(
Ec /kT ). Based on all available data it seems reasonable to postulate that the energy barrier is lowered by the presence of surface strain, that is, Ec decreases with increasing n0. This behavior can be modeled by a first-order exponential decay, leading to a value of Ec for n0 approaching zero which is close to the barrier obtained for the diffusion of substitutional carbon in bulk silicon with very low carbon concentrations [7]. For the low carbon concentrations used to control dopant diffusion, the energy barrier is still large enough to suppress any defect formation within the temperature window for epitaxial growth. Thus, low carbon concentrations will be predominantly incorporated substitutionally. The preexponential frequency factor k0 decreases over several orders of magnitude with increasing n0. This factor mainly describes the ability of adatoms to migrate on the surface. Thus, the presence of carbon on the surface appears to reduce surface diffusion significantly. Extrapolating to n0 ¼ 0, k 0(0) is in the same order of magnitude typically assumed for surface migration of adatoms on an unperturbed Si surface. There is another interesting consequence arising from the decrease of Ec and k0 with increasing C concentration, namely that the fraction of substitutionally incorporated carbon atoms decreases with increasing n0. This leads to a saturation limit, i.e., any further increase in the carbon flux leads mainly to an increase in the number of interstitial defects, with the amount of substitutionally incorporated carbon remaining constant [22]. This behavior supports the often postulated existence of a limit for substitutional carbon incorporation [1]. This limit depends, of course, on the specific growth conditions and the specific carbon source. So far, we discussed the incorporation of C into silicon. Liu and Osten [24] extended the investigations to substitutional C incorporation during MBE growth of Si1
x
yGexCy alloys. The strain introduced by the incorporation of C and Ge makes these processes even more complicated. They showed that the substitutional C incorporation can be dominated by the Ge or C concentration, depending on the total C concentration range. At low total C concentration, the Ge impact is insignificant; increasing total C concentration leads to less substitutional C incorporation efficiency. At high n0, the impact of C concentration becomes marginal, and the presence of Ge inhibits the substitutional C incorporation. The very low substitutional C incorporation during Ge1
yCy growth even at an extremely low growth temperature of 2008C (reported recently in Ref. [25]) is consistent with this prediction.

2.9.4 Control of Dopant Diffusion by Adding Carbon The amount of carbon discussed in this chapter is in the order of dopant concentrations. To distinguish these materials from the Si1
yCy or Si1
x
yGexCy systems discussed so far, we will use the same notation as for dopants, that is Si:C or SiGe:C. The carbon concentration is too low to affect significantly band alignment and strain of the epitaxially grown Si:C or SiGe:C layers. However, the used carbon concentration in the range of 1020 cm
3 is still orders of magnitude higher than the solid solubility limit, i.e., we have to consider metastable systems with carbon supersaturation. A major challenge for the fabrication of ultrasmall devices for next silicon technology generations is the control of steep dopant profiles. In this context, it is tempting to apply supersaturated carbon as a diffusion-controlling agent in silicon. The fundamental question for applications of C-rich Si in devices is whether electronic device parameters are affected by possible C-related defects. Recently, Gossmann et al. [26] have announced the realization of MOSFET with reduced reverse short-channel effect due to suppressed transient diffusion in C-rich silicon. Little increase in leakage current was reported for devices with carbon. Successful applications of C-rich layers were reported for SiGe HBT [27, 28]. The IHP group has demonstrated that transistors with excellent static and dynamic parameters can be fabricated with epitaxial SiGe:C layers [29, 30]. The main result of this investigation was that carbon supersaturation can preserve steep boron doping profiles without degrading fundamental transistor parameters. The diffusion coefficient of B in Si is reduced by more than one order of magnitude when the concentration of substitutional C is elevated to about 1020 cm
3 [31]. Furthermore, transientenhanced diffusion (TED) of B is strongly suppressed in C-rich Si [32].

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-161

In the following, we will describe the physical mechanism for suppressed boron diffusion in C-rich Si and SiGe (below 0.2% carbon) based on an undersaturation of Si self-interstitials [31, 33, 34]. Diffusion of dopants as well as Si self-diffusion, and diffusion of Ge and C in Si are mediated by point defects, i.e., vacancies and self-interstitials. It is generally accepted that both vacancy and interstitial mechanisms contribute to atomic transport in Si while the direct exchange mechanism of nearest-neighbor atoms plays a negligible role. The effect of C on B diffusion can be explained by coupled diffusion of B and point defects in Si. Diffusion of C out of C-rich regions causes an undersaturation of Si self-interstitials in the C-rich region, which in turn results in suppressed diffusion of boron. Pronounced non-Fickian diffusion behavior was found experimentally for buried carbon with concentrations well above its solid solubility [34]. The basic mechanism for nonequilibrium point defect densities due to C outdiffusion is as follows [1, 31]. Depending on growth conditions, carbon can be mainly substitutionally dissolved in Si. Diffusion of C in Si is via a substitutional–interstitial mechanism. Immobile substitutional carbon atoms (Cs) are transformed into mobile interstitial carbon (Ci) through the kick-out reaction with Si self-interstitials (I ): Cs þ I $ Ci. In addition, interstitial C can be formed in the dissociative Frank–Turnbull reaction, Cs $ Ci þ V, where V is a vacancy. In order to conserve the total number of atoms the flux of interstitial C atoms out of the C-rich region has to be balanced by a flux of Si self-interstitials into this region or a flux of vacancies outwards. The individual fluxes are determined by the products of the diffusion coefficient D and the concentration C, which are all known. For C concentrations CC > 1018 cm
3, the transport coefficient of C may exceed the corresponding transport coefficients of Si self-interstitials and vacancies: DCCC > DICIeq and DCCC > DVCVeq, where CIeq and CVeq are the equilibrium concentrations of Si self-interstitials and vacancies, respectively. Consequently, outdiffusion of supersaturated C from C-rich regions becomes limited by the compensating fluxes of Si point defects, which leads to an undersaturation of self-interstitials and a supersaturation of vacancies in the C-rich region. In Figure 2.9.2 measured C profiles in Si are compared with model calculation [34]. A 50-nm thick box-shaped C profile was grown using MBE and annealed in pure nitrogen atmosphere. Diffusionlimited rates were assumed for the two reactions described above and for Frenkel-pair generation. For the kick-out reaction, local equilibrium is established for typical point defect parameters. In contrast, the concentration of vacancies in the C-rich region is sensitive to the rate of the Frank–Turnbull reaction. Ru¨cker et al. [34] fitted only the reaction rate to the measured diffusion profile of C. From this simulation, he found also a significant vacancy supersaturation. The point defect distribution after annealing resulting from the calculation is also shown in Figure 2.9.2. In the C-rich region, there is a significant reduction in the interstitial density accompanied by an increase in the vacancy density. This has consequences for all dopants diffusing via point defects. Boron diffusion in Si is via an interstitial mechanism. The effective diffusion coefficient of B is proportional to the normalized concentration of self-interstitials. Accordingly, interstitial undersaturation results in suppressed diffusion of B. Also the diffusion of phosphorous will be strongly reduced. On the contrary, the diffusion of dopants, which are diffusing by a vacancy mechanism (like As or Sb), will be enhanced due to carbon incorporation [34]. TED during the first annealing step after ion implantation accounts for a substantial fraction of dopant redistribution during device processing. The source of TED is an enhanced density of Si selfinterstitials. In a subsequent publication, Ru¨cker et al. [35] have extended this physical model to TED, i.e., nonequilibrium distribution of Si self-interstitials. The authors could show that the same mechanism holds also for TED. The effect of C on diffusion of donors and acceptors can correctly be described by a physically based model for coupled diffusion of C and Si point defects. In the simulation, they have used the ‘‘þ1’’ model for implantation damage and coupled diffusion of C and Si point defects. Reduced diffusion of B in SiGe and the effect of the electric field due to hole confinement in SiGe were also included. The simulation reveals the strong suppression of TED in the C-containing structure. Again, the density of excess interstitials is reduced in the SiGe:C layer due to C outdiffusion. The quality of epitaxial layers for electronic device application can also be evaluated by studying the carrier generation lifetime in MOS-like structures [36]. For LPCVD grown SiGe:C layer stacks similar to that used for HBT application lifetimes above 1 ms were measured, i.e., values that are sufficient for

© 2006 by Taylor & Francis Group, LLC

2.9-162

1019

Carbon (cm−3)

The Silicon Heterostructure Handbook

Annealed

1018 as-grown Simulated

Norm. point defect conc.

10 Vacancies 1

0.1 Interstitials 0.0

0.2

0.4 0.6 Depth (µm)

0.8

1.0

FIGURE 2.9.2 Diffusion profiles of buried carbon layers annealed in nitrogen atmosphere (9008C/45 min). SIMS profiles of as-grown ( ) and annealed ( ) samples are shown in the upper panel together with results of model calculation. The corresponding normalized point defect densities are shown in the lower panel.

successful application of those layers in high-performance devices with low noise. Recently, Heinemann et al. [37] could show that the electron mobility in the p-type base of npn bipolar transistors is not reduced by the incorporation of low C concentrations. They reported about a comparative analysis of vertical minority carrier transport in experimentally realized HBTs with Si, Si1
xGex (x ¼ 7.5%), and Si1
yCy (y ¼ 0.2% or 1%) base layers. To overcome drawbacks of the simple transit time analysis, they used 2D device simulations to obtain an improved understanding of the measured high-frequency parameters. Taking into account the real doping profiles and device structures, and using a calibrated parameter set for strained SiGe, the simulation results for the Si, Si1
xGex, and Si1
yCy (y ¼ 0.2%) base layer transistors reproduce very well the measured transit times (assuming the Si data for the electron mobility) in the heteroepiaxial base layers. In the case of higher carbon concentration (y ¼ 1%), the electron mobility is reduced by a factor of two.

2.9.5 Strain Manipulation in Si1
x
yGexCy Layers Adding a constituent with a covalent radius much smaller than that of silicon to a layer containing the larger Ge (rSi ¼ 1.17 A˚, rGe ¼ 1.22 A˚, but rC ¼ 0.77 A˚) opens the possibility to manipulate the strain. It was shown that it is possible to form an ‘‘inversely distorted’’ SiGe cell, i.e., a cell that is tetragonally distorted due to tensile stress instead of the usual compressive stress by adding some carbon [16]. Using simple linear extrapolations between the different lattice constants and the appropriate relative concentration (Vegard’s law for a ternary system), we can estimate the effective lattice constant in the Si1
x
yGexCy system as a(x,y) ¼ (1
x
y)aSiþxaGeþyaC. The linear approximation (between Si, Ge, and diamond) for the average lattice constants results in a Ge:C ratio of 8.2 for complete strain compensation. Ab initio calculations predict values larger than 10 (see for example Ref. [38]). Diamond seems not to be the best choice for interpolating lattice parameter in Si1
x
yGexCy . Osten et al. [16] proposed a linear interpolation between the lattice constants of Si, Ge, and b-SiC: aSiGeC ¼ (1
x
2y)aSiþxaGeþ2yaSiC, which is illustrated in Figure 2.9.3. This approach yields that the

© 2006 by Taylor & Francis Group, LLC

2.9-163

Compressive

Carbon Doping of SiGe

Lattice mismatch

40 % Ge 30 % Ge 20 % Ge

Tensile

10 % Ge 0 % Ge 0

1 2 C concentration (%)

3

FIGURE 2.9.3 Estimated strain reduction in SiGe layers due to the presence of carbon (ternary Vegard’s law).

compressing strain of 9.4 % Ge can be fully compensated by 1% C, i.e., strain compensation occurs for a Ge:C ratio of 9.4. Kelires [39] has calculated the lattice constant of Si1
yCy . He predicted some small bowing effects, which were also found experimentally by Berti et al. [40]. We define an ‘‘effective lattice mismatch’’ as mfeff ¼ [a(x,y)
aSi]/aSi. This quantity is directly accessible by x-ray diffraction. A positive mfeff stands for a compressively strained material, mfeff <0 indicates tensile strain, and mfeff ¼ 0 represents a fully strain-compensated Si1
x
yGexCy alloy. Such a layer should have on an average scale the cubic silicon structure.

2.9.6 Microscopic Structure of SiGeC Layers The microscopic structure of a fully strain-compensated Si1
x
yGexCy layer has been investigated in detail in Ref. [41]. The Si

C bonds are stretched by about 7% with respect to the bond length in cubic silicon carbide, whereas the C atoms mainly strain the Si

Si bond in their neighborhood, with more distant Si

Si bonds less affected. Although the average lattice constant of the strain-compensated Si1
x
yGexCy layer is the same as that of pure silicon, the alloy contains large internal (microscopic) strain. Calculations support the picture of only partial relaxation of the Si

Si and Ge

Ge bonds towards a common bond length. The Si

C and Si

Ge bonds in strain-compensated Si1
x
yGexCy are strongly stretched. The calculated 7% stretching of the Si

C in strain-compensated Si1
x
yGexCy corresponds to 35% relaxation towards the average bond length of the alloy (predicted by Vegard’s law). The observed dependence of Raman spectra on local strain and composition of Si1
x
yGexCy layers can be explained by the model calculations [41].

2.9.7 Strain-Stabilized Layers with High C Concentration By combining theoretical and experimental results for local Si

C phonon modes in dilute Si1
yCy alloys, information concerning the short-range order was obtained [42]. Calculations using an anharmonic Keating model predict satellite peaks near the vibrational frequency of an isolated C impurity, associated with second-, third-, etc., nearest-neighbor C

C pairs. By comparing theoretical spectra with those obtained by Raman and infrared absorption spectroscopies, it was concluded that the probability for a third-nearest-neighbor coordination of the C atoms is considerably above that for a purely random alloy. Maximizing the number of third-nearest neighbors leads to a Si1
yCy system with y  20%. Recently, Ru¨cker et al. [43] investigated the possible existence of such highly concentrated Si1
yCy layers embedded in silicon. They demonstrated that Si1
yCy layers with y  20% can be grown pseudomorphically on a Si(0 0 1) substrate despite the large difference of the C and Si lattice constants. Such structures could only exist due to strain stabilization. It has been observed previously that semiconductor structures, which are not found in the bulk phase diagram, can be stabilized by the

© 2006 by Taylor & Francis Group, LLC

2.9-164

The Silicon Heterostructure Handbook

substrate-imposed strain in pseudomorphic epitaxial growth. The energy Eepi of an epitaxially confined structure can be decomposed as Eepi ¼ Eequib þ Estrain, where Eequib is the energy at the unconstrained equilibrium lattice constant and Estrain is the work needed to strain the material to match the Si substrate. An epitaxially stabilized structure X occurs when Eepi(X) lies below that of the most stable bulk phase X0 [here, Eepi(b-SiC)]. Detailed structural investigations of such strain-stabilized Si1
yCy layers with y  20 % were presented by Ruvimov et al. [44].

2.9.8 Thermal Stability Si1
xGex alloys cannot be grown epitaxially on Si or Ge substrates without introducing large amounts of strain. Strain-relief occurs usually by plastic flow, i.e., by injection and propagation of misfit dislocations (see Chapter 2.7). Si1
xGex alloys can be grown to much larger thickness than predicted by mechanical equilibrium theory. These layers become metastable. A later temperature treatment, as typical for further Si technological steps, causes also the strain-relieving formation of extended misfit dislocations. Therefore, the inherent strain limits the compatibility of heteroepitaxial SiGe systems to common Si technologies due to its lower thermal stability. In addition, the formation of extended misfit dislocations always changes the in-plane lattice constant (loss of pseudomorphy), enabling the construction of virtual substrates with a lattice constant differing from silicon. The temperature stability of tensile-strained Si1
yCy layers was investigated during and after postgrowth annealing [11, 12, 45–47]. Despite the tensile strain in a 100-nm thick layer and the high carbon supersaturation, the samples were stable up to 8508C [12]. Beyond this temperature range, the substitutional carbon content started to decrease exponentially during isothermal annealing. From the temperature–time behavior of the measured changes in lattice spacing, Fischer et al. [12] extracted activation energy for that process of 3.2 eV. However, the layers remain always pseudomorphically to the Si substrate, i.e., they preserve the Si in-plane lattice constants. Although the number of possible nucleation centers for dislocation generation was quite high, no relaxation by the formation of extended misfit dislocation networks was detected [12, 47]. The observed relaxation effect can be explained by precipitation of carbon or nucleation and diffusion-limited growth of SiC nanocrystals. Contrary to the mechanism of strain relief in Si1
xGex , in comparably strained Si1
yCy epilayers, the main high-temperature process is precipitation, which does not alter the in-plane lattice constant. Thus, relaxed Si1
yCy layers are not suitable as virtual substrates with a smaller in-plane lattice constant as silicon. Similar results were obtained for the thermal stability of compressive strained Si1
x
y GexCy alloys [48, 49]. Carbon incorporation changes the thermal stability of SiGe layers significantly. As for pseudomorphic Si1
yCy layers, plastic relaxation is suppressed by the dislocation pinning effect of C, leading to an increase in thermal stability of strained metastable Si1
x
y GexCy alloys compared to strain-equivalent Si1
xGex layers. Recently, the growth of a relaxed, only 1-mm thick, stepwise graded buffer based on a combination of Si1
xGex and Si1
x
y GexCy with a low threading dislocation density was demonstrated [50]. For the nonoptimized buffer growth the authors found a threading dislocation density below 105 cm
2. A stepped Si1
x Gex buffer with the identical thickness and strain profile grown with the same temperature ramp yield a threading dislocation density above 107 cm
2. This buffer concept relies on the retardation of dislocation glide in Si1
x
y GexCy relative to strain-equivalent Si1
xGex on silicon. Due to the very strong local strain fields around the individual carbon atoms, dislocation glide requires a higher energy in Si1
x
y GexCy than in undisturbed, strain-equivalent Si1
xGex on silicon [51, 52]. This indicates that the addition of carbon might be a promising way for new relaxed buffer concepts with low threading dislocation densities.

2.9.9 Impact of Carbon on Electrical Layer Properties Assuming an average band structure for Si1
x
y GexCy alloys, Soref [53] has suggested an empirical interpolation between Si, Ge, and diamond for the bandgap. This technique results in an increase in the fundamental gap of Si1
y Cy layers with increasing y. Alternatively, Demkov and Sankey [54] have

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-165

modeled Si1
yCy alloys with supercells with random occupation of the lattice sites according to the alloy composition. They found that the fundamental gap is reduced when a few percent of carbon are added to the silicon lattice. Photoluminescence measurements on tensile-strained Si1
yCy layers yield a reduction in the fundamental gap, with the main offset occurring in the conduction band [55]. From these experimental results, we can state that the virtual crystal approximation is not able to describe the changes in band structure for Si1
yCy and Si1
x
y GexCy alloys correctly. Also the carbon effects cannot be reduced to changes in strain only as proposed earlier by Powell et al. [56]. To describe adequately the observed energy shifts for pseudomorphic C-containing layers, we have to consider at least straininduced effects and effects due to alloying [57, 58]. Extensive calculations including all contributions lead to the following conclusions for ternary alloys [58]: In tensile strained Si1
yCy , the fundamental bandgap is reduced, with the main offset occurring in the conduction band. This makes Si1
yCy layers particularly suitable for electron confinement. The tensile strain lifts the sixfold degeneracy in the conduction band. Thus, the bandgap is determined by the separation between the light hole and the lowered twofold degenerate valley D(2). The energy splitting in the strained alloys transfers electrons from the upper to the lower valleys, which have a smaller effective mass in the plane. In addition, the energy splitting reduces intervalley scattering between twofold and fourfold degenerate valleys. Analogous to strained silicon, both effects should lead to an increase of in-plane electron mobility for low C contents in Si1
yCy . However, most available experimental data do not support these predictions, presumably due to scattering by interstitial C-containing defects. For samples with identical lattice distortion due to misfit strain and hence band alignment, Osten et al. [59] found differences in electron mobility of nearly a factor of two due to the different concentrations of interstitial carbon. Electron transport characteristics have been studied experimentally and theoretically using Monte Carlo (MC) simulations [60–62]. The authors found that the dependence of mobility on C content depends critically on the (unknown) value for the alloy scattering potential. For small alloy scattering potentials the authors found the following behavior for the electron mobility as a function of C concentration: With increasing carbon content the mobility first increases up to a maximum of approximately twice the value for silicon. Further increase in C content leads to a decrease in the mobility, which can be lower than the mobility in silicon, depending on the assumed scattering potential. Assuming a larger scattering potential, MC simulations yield a monotonic decrease in electron mobility with increasing carbon content due to the dominance of alloy scattering over the strain-induced mobility gain. Brunner et al. [63] reported that the mobility enhancement induced by strain is larger than the degradation caused by alloy scattering, leading to electron mobility values above the appropriate Si values, especially at low temperatures. Recently, pMOSFETs using tensile-strained Si1
yCy channel layers on Si substrates have been shown to provide mobility enhancement over Si epitaxial channel layers and Si bulk devices [64]. These layers did not exhibit the defects typically associated with a relaxed SiGe buffer structure. Furthermore, pMOSFET devices fabricated on these alloy layers demonstrate enhanced hole mobility over Si epi control and Si bulk. However, increased amounts of C may result in degraded device performance. Therefore, when fabricating such devices, a balance must be struck to minimize C-induced interface charges and alloy scattering rate. The bandgap for the ternary alloys is always smaller than that of silicon, independent of strain state (Figure 2.9.4). The addition of C (Ge) into compressive strained Si1
xGex (tensile-strained Si1
yCy) leads to a smaller reduction in bandgap narrowing than an equivalent strain reduction in the binary alloy (lower Ge or C content, respectively). The band gap of a fully strain-compensated Si1
x
y GexCy is a linear function of Ge (or C) concentration. Those layers are strain-free, i.e., there are no thickness limitations due to relaxation. This opens a new way for bandgap engineering of a material on Si(0 0 1) that is macroscopically strain-free.

2.9.10 Summary We have briefly reviewed the basic growth issues and some mechanical and electrical material properties of Si1
yCy and Si1
x
y GexCy layers grown pseudomorphically on Si(0 0 1). This new material promises

© 2006 by Taylor & Francis Group, LLC

2.9-166

The Silicon Heterostructure Handbook

1.2

1.2

Si

y

1.0

1.1

1−

C 1− y

Si

Bandgap (eV)

1.1

xG

1% C

10% Ge

e

x

1.0 2% C

20% Ge

0.9

0.9 3% C

30% Ge

0.8

0.8 −1.0

−0.5 0.0 0.5 Effective lattice mismatch (%)

1.0

FIGURE 2.9.4 Bandgap narrowing for ternary Si1
x
y GexCy alloys, strained on Si(0 0 1) as a function of lattice mismatch. Both binary alloys (tensile strained Si1
yCy and compressive strained Si1
xGex) are shown as references.

to alleviate some of the constraints of strained Si1
xGex , and open new possibilities for device applications of heteroepitaxial Si-based systems. The incorporation of carbon can be used (i) to improve SiGe layer properties, (ii) to obtain layers with new properties, and (iii) to control dopant diffusion in microelectronic devices.

Acknowlegdments The author would like to thank D. Bolze, E. Bugiel, B. Dietrich, K.E. Ehwald, D. Endisch, G.G. Fischer, P. Gaworzewski, J. Griesche, B. Heinemann, M.C. Kim, W. Kissinger, D. Knoll, D. Kru¨ger, G. Lippert, J.P. Liu, M. Methfessel, K. Pressel, H. Ru¨cker, S. Scalese, R. Sorge, H.J. Thieme, B. Tillack, M. Weidner, and P. Zaumseil for their contributions to the research reviewed in this chapter.

References 1. ST Pantelides and S Zollner (Eds). Silicon–Germanium Carbon Alloys, Growth Properties and Application. New York: Taylor and Francis, 2002. 2. HJ Osten. Carbon-Containing Layers on Silicon. Zu¨rich: Transtech Publications, 1999. 3. E Kasper and K. Lyutovich (Eds). Properties of Silicon Germanium and SiGe:Carbon. London: EMIS Data reviews Series No 24, 2000. 4. KE Ehwald, D Knoll, B Heinemann, KChang, J Kirchgessner, R Mauntel, Ik-Sung Lim, J Steele, B Tillack, A Wolff, K Blum, W Winkler, M Pierschel, F Herzel, U Jagdhold, P Schley, R Barth, and HJ Osten. Modular integration of high-performance SiGe:C-HBTs in a deep submicron, epi-free CMOS process. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1999, pp. 561–564. 5. AR Powell, K Eberl, BA Ek, and SS Iyer. Si1
x
y GexCy growth and properties of ternary systems. J. Crystal Growth 127: 425–429, 1993. 6. HJ Osten. Supersaturated carbon in silicon and silicon germanium alloys. Mater. Sci. Eng. B 36: 268– 274, 1996. 7. JL Regolini, F Gisbert, G Dolino, and P Boucaud. Growth and characterization of strain compensated Si1
x
y GexCy epitaxial layers. Mater. Lett. 18: 57–60, 1993. 8. S Im, J Washburn, R Gronsky, NW Cheung, KM Yu, and JW Ager. Optimization of Ge/C ratio for compensation of misfit strain in solid phase epitaxial growth of SiGe layers. Appl. Phys. Lett. 63: 2682–2684, 1993. 9. JW Strane, HJ Stein, SR Lee, BL Doyle, ST Picraux, and JW Mayer. Metastable SiGeC formation by solid phase epitaxy. Appl. Phys. Lett. 63: 2786–2788, 1993.

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-167

10. G Davis, RC Newman. Carbon in monocrystalline silicon, in TS Moss (ed.), Handbook of Semiconductors, Vol. 3, Amsterdam: Elsevier Science, 1994. 11. MS Goorsky, SS Iyer, K Eberl, FK LeGouech, J Angilello, and F Cardonne. Thermal stability of Si1
xCx /Si strained layer superlattices. Appl. Phys. Lett. 60: 2758–2761, 1992. 12. GG Fischer, P Zaumseil, E Bugiel, and HJ Osten. High temperature behaviour of strained Si1-yCy /Si heterostructures. J. Appl. Phys. 77: 1934–1937, 1995. 13. J Tersoff. Enhanced solubility of impurities and enhanced diffusion near crystal surfaces. Phys. Rev. Lett. 74: 5080–5083, 1995. 14. PC Kelires and J Tersoff. Equilibrium alloy properties by direct simulation: oscillatory segregation at the Si–Ge(100) 2x1 surface. Phys. Rev. Lett. 63: 1164–1167, 1989. 15. WJ Taylor, TY Tan, and U Goesele. Carbon precipitation in silicon: why is it so difficult? Appl. Phys. Lett. 62: 3336–3338, 1993. 16. HJ Osten, E Bugiel, and P Zaumseil. The growth of an inverse tetragonal distorted SiGe layer on Si(001) by adding small amounts of carbon. Appl. Phys. Lett. 64: 3440–3443, 1994. 17. K Pressel, B Dietrich, H Ru¨cker, M Methfessel, and HJ Osten. Optical investigations of Si1
yCy alloys. Mater. Sci. Eng. B 36: 167–170, 1996. 18. HJ Osten, M Kim, K Pressel, and P Zaumseil. Substitutional versus interstitial carbon incorporation during pseudomorphic growth of S1
yCy on Si(001). J. Appl. Phys. 80: 6711–6715, 1996. 19. MW Dashiell, LV Kulik, D Hits, J Kolodzey, and G Watson. Carbon incorporation in S1
yCy alloys grown by MBE using a single-graphite source. Appl. Phys. Lett. 72: 833–835, 1998. 20. S Zerlauth, H Seyringer, C Penn, and F. Scha¨ffler. Growth conditions for complete substitutional carbon incorporation into layers grown by molecular beam epitaxy. Appl. Phys. Lett. 71: 3826–3828, 1997. 21. TO Mitchell, JL Hoyt, and JF Gibbons. Substitutional carbon incorporation in epitaxial S1
yCy layers grown by chemical vapor deposition. Appl. Phys. Lett. 71: 1688–1691, 1997. 22. HJ Osten, J Griesche, and S Scalese. Substitutional carbon incorporation in epitaxial Si1
yCy alloys on Si(001) grown by molecular beam epitaxy. Appl. Phys. Lett. 74: 836–838, 1999. 23. PC Kelires and E Kaxiras. Substitutional carbon impurities in thin silicon films: equilibrium structure and properties. J. Vac. Sci. Technol. B 16: 1687–1691, 1998. 24. JP Liu and HJ Osten. Substitutional carbon incorporation during Si1
x
y Gex Cy growth on Si(100) by molecular beam epitaxy: dependence on germanium and carbon concentration. Appl. Phys. Lett. 76: 3546–3548, 2000. 25. R Duschl, OG Schmidt, W Winter, K Eberl, MW Dashiell, J Kolodzey, NY Jin-Phillipp, and F Phillipp. Growth and thermal stability of pseudomorphic Ge1
y Cy /Ge superlattices on Ge(0 0 1). Appl. Phys. Lett. 74: 1150–1152, 1999. 26. HJ Gossmann, C Rafferty, G Hobler, H Vuong, D Jacobson, and M Frei. Suppression of reverse short channel effect by a buried carbon layer. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1998, pp. 725–728. 27. HJ Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe HBT performance and process margins. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1997, pp. 803–806. 28. LD Lanzerotti, JC Sturm, E Stach, R Hull, T Buyuklimanli, and C Magee. Suppression of boron transient enhanced diffusion in SiGe heterojunction bipolar transistors by carbon incorporation. Appl. Phys. Lett. 70: 3125–3127, 1997. 29. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillack, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si /SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1998, pp. 703–806. 30. H. Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, HE Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Device Meeting, Washington, 2003, pp. 121–124.

© 2006 by Taylor & Francis Group, LLC

2.9-168

The Silicon Heterostructure Handbook

31. H Ru¨cker, B Heinemann, W Ro¨pke, R Kurps, D Kru¨ger, G Lippert, and HJ Osten. Suppressed Diffusion of boron and carbon in carbon-rich Silicon. Appl. Phys. Lett. 73: 1682–1684, 1998. 32. PA Stolk, DJ Eaglesham, HJ Gossmann, and JM Poate. Carbon incorporation in silicon for suppressing interstitial-enhanced boron diffusion. Appl. Phys. Lett. 66: 1370–1372, 1995. 33. R Scholz, U Go¨sele, JY Huh, and TY Tan. Carbon-induced undersaturation of silicon self-interstitials. Appl. Phys. Lett. 72: 200–202, 1998. 34. H Ru¨cker, B Heinemann, D Bolze, D Knoll, D Kru¨ger, R Kurps, HJ Osten, P Schley, B Tillack, and P Zaumseil. Dopant diffusion in C-doped Si and SiGe: physical model and experimental verification. Technical Digest of the IEEE International Electron Device Meeting, Washington, 1999, pp. 345–348. 35. H Ru¨cker, B Heinemann, D Bolze, R Kurps, D Kru¨ger, G Lippert, and HJ Osten. The impact of supersaturated carbon on transient enhanced diffusion. Appl. Phys. Lett. 74: 3377–3379, 1999. 36. HJ Osten, G Lippert, P Gaworzewski, and R Sorge. Impact of low carbon concentrations on the electrical properties of highly boron doped SiGe layers. Appl. Phys. Lett. 71: 1522–1524, 1997. 37. B Heinemann, D Knoll, GG Fischer, P Schley, and HJ Osten. Comparative analysis of minority carrier transport in npn bipolar transistors with Si, Si1
xGex , and Si1
yCy base layers. Thin Solid Films 369: 347–351, 2000. 38. W Windl, OF Sankey, and J Mene´ndez. Theory of strain and electronic structure of Si1
yCy and Si1
x
yGexCy alloys. Phys. Rev. B 57: 2431–2442, 1998. 39. PC Kelires. Monte Carlo studies of ternary semiconductor alloys: application to the Si1
x
yGex Cy system. Phys. Rev. Lett. 75: 1114–1117, 1995. 40. M Berti, D De Salvator, AV Drigo, F Romanato, J Stangl, S Zerlauth, F Scha¨ffler, and G Bauer. Lattice parameter in Si1
yCy epilayers: deviation from Vegard’s rule. Appl. Phys. Lett. 72: 1602–1604, 1998. 41. B Dietrich, HJ Osten, H Ru¨cker, M Methfessel, and P Zaumseil. Lattice distortion in a strain compensated Si1
x
yGexCy layer on silicon. Phys. Rev. B 49: 17185–17190, 1994. 42. H Ru¨cker, M Methfessel, B Dietrich, K Pressel, and HJ Osten. Phonons as a probe of short-range order in Si1
yCy alloys. Phys. Rev. B 53: 1302–1309, 1996. 43. H Ru¨cker, M Methfessel, E Bugiel, and HJ Osten. Strain-stabilized highly-concentrated pseudomorphic Si1
yCy layers in Si. Phys. Rev. Lett. 72: 3578–3581, 1994. 44. S Ruvimov, E Bugiel, and HJ Osten. Structural characterization of SinC d-layers embedded in a silicon matrix. J. Appl. Phys. 78: 2323–2327, 1995. 45. AR Powell, FK LeGoues, and SS Iyer. Formation of b-SiC nanocrystals by the relaxation of Si1
yCy random alloy layers. Appl. Phys. Lett. 64: 324–326, 1994. 46. AR Powell, K Eberl, FK Legoues, and BA Ek. Stability of strained Si1
yCy random alloy layers. J. Vac. Sci Technol. B 11: 1064–1068, 1993. 47. HJ Osten, D Endisch, E Bugiel, B Dietrich, GG Fischer, M Kim, D Kru¨ger, and P Zaumseil. Strain relaxation in tensile strained Si1
yCy layers on Si(0 0 1). Semicond. Sci. Tech. 11: 1678–1687, 1996. 48. P Warren, J Mi, F Overney, and M Dutoit. Thermal stability of Si /Si1
x
y GexCy /Si heterostructures grown by rapid thermal chemical vapor deposition. J. Crystal Growth 157: 414 – 419, 1995. 49. P Zaumseil, GG Fischer, K Brunner, and K Eberl. Comparison of the thermal stability of Si0.603Ge0.397/Si and Si0.597Ge0.391C0.012/Si superlattice structures. J. Appl. Phys. 81: 6134–6140, 1997. 50. HJ Osten and E Bugiel. Relaxed Si1
xGex /Si1
x
y GexCy buffer structures with low threading dislocation density. Appl. Phys. Lett. 70: 2813–2815, 1997. 51. E Bugiel, S Ruvimov, and HJ Osten. TEM characterization of Si1
x
y GexCy and Si1
yCy layers grown with molecular beam epitaxy on (0 0 1)Si substrates. Int. Phys. Conf. Ser. 146: 301– 306, 1995. 52. HJ Osten and J Klatt. In situ monitoring of strain relaxation during antimony-mediated growth of Ge and Ge1
yCy layers on Si(001) using refection high energy electron diffraction. Appl. Phys. Lett. 65: 630–632, 1994. 53. RA Soref. Optical band gap of the ternary semiconductor Si1
x
y GexCy . J. Appl. Phys. 70: 2470– 2472, 1991.

© 2006 by Taylor & Francis Group, LLC

Carbon Doping of SiGe

2.9-169

54. AA Demkov and OF Sankey. Theoretical investigation of random Si–C alloy. Phys. Rev. B 48: 2207– 2214, 1993. 55. K Brunner, K Eberl, and W Winter. Near-band-edge photoluminescence from pseudomorphic Si1
yCy quantum well structures. Phys. Rev. Lett. 76: 303–306, 1996. 56. AR Powell, K Eberl, BA Ek, and SS Iyer. Si1
x
yGexCy growth and properties of ternary systems. J. Crystal Growth 127: 425–429, 1993. 57. S Zollner. Theory of optical interband transitions in strained Si1
yCy grown pseudomorphically on Si(001). J. Appl. Phys. 78: 5209–5211, 1995. 58. HJ Osten. Band gap changes and band offsets for ternary Si1
x
yGexCy alloys on Si(0 0 1). J. Appl. Phys. 84: 2716–2721, 1998. 59. HJ Osten, J Griesche, P Gaworzewski, and KD Bolze. Influence of interstitial carbon defects on electron transport in strained Si1
yCy layers on Si(0 0 1). Appl. Phys. Lett. 76: 200–202, 2000. 60. HJ Osten and P Gaworszewski. Charge transport in strained Si1
yCy and Si1
x
yGexCy alloys on silicon. J. Appl. Phys. 82: 4977–4981, 1997. 61. M Ershov and V Ryzhii. Monte Carlo study of electron transport in strained silicon–carbon alloy. J. Appl. Phys. 76: 1924–1926, 1994. 62. P Dollfus, S Galdin, P Hesto, and HJ Osten. Band offsets and electron transport calculation for strained Si1
x
yGexCy /Si heterostructures. J. Mater. Sci.: Mater. Electron. 12: 245–248, 2001. 63. K Brunner, W Winter, K Eberl, NY Jin-Phillip, and F Phillip. Fabrication and band alignment of pseudomorphic Si1
yCy , Si1
x
yGexCy and coupled Si1
yCy /Si1
x
yGexCy quantum well structures on Si substrates. J. Crystal Growth 175/176: 451–458, 1997. 64. E Quinones, SK Ray, KC Liu, and S Banerjee. Enhanced mobility pMOSFETs using tensile-strained Si1
yCy layers. IEEE Electron. Device Lett. 20: 338–340, 1999.

© 2006 by Taylor & Francis Group, LLC

2.10 Contact Metallization on Silicon– Germanium

C. K. Maiti Indian Institute of Technology Kharagpur

2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7

Introduction........................................................... 2.10-171 Contact Metallization: Current Status................. 2.10-172 Contact Metallization: Challenges ....................... 2.10-173 Poly-SiGe Gate Technology .................................. 2.10-175 Silicidation of SiGe................................................ 2.10-175 Silicidation of SiGeC............................................. 2.10-181 Summary ................................................................ 2.10-181

2.10.1 Introduction During the last 40 years, Si-based complementary metal oxide semiconductor (CMOS) technology has emerged as the most predominant technology for the microelectronics industry. The success of the technology has largely been due to technological innovations that enabled continuous scaling of device dimensions, which have resulted in improvements in both device performance and packing density. However, this trend cannot continue indefinitely and we are approaching the fundamental limits of Si technology. To overcome the fundamental limits of Si, still maintaining compatibility with the conventional Si processing, several new materials such as strained-SiGe, strained-Si, and silicon–germanium– carbon (SiGeC) are currently being considered. Acceptance of a new material in CMOS technology requires a detailed understanding of the consequences, if incorporated. Currently, self-aligned silicide technology is being used to form the source and drain regions to reduce the RC delay, increase driving current, and enhance the performance of deep submicron CMOS devices. In CMOS technologies, among many other metals, Ti, Co, Ni, Pt, and Pd have been studied in detail for silicidation. The reader may refer to an excellent recent review by Zhang and Ostling [1]. Properties of some commonly used metals and their silicides for salicide applications in Si CMOS technology are shown in Table 2.10.1 and Table 2.10.2, respectively. According to the International Technology Roadmap for Semiconductors (ITRS) 2003 [2], the device scaling and increased functionality is expected to continue at least until 2016, when the minimum feature size is projected to be 22 nm. Currently one of the key challenges in device scaling is to develop new contact technologies for the MOSFETs as the source/drain (S/D) parasitic series resistance is becoming a significant fraction of the channel resistance. The ITRS roadmap predicts the requirements for source/drain contact regions as: (i) junction depth/sheet resistance (<100 ohm/sq. for 30 nm junctions), (ii) ultralow resistivity contacts (1.5
108 ohm-cm2), (iii) excellent reverse leakage characteristics (less than 1% of the Ioff ), and (iv) integration compatibility with high-k gate dielectrics using the conventional CMOS process flow.

2.10-171 © 2006 by Taylor & Francis Group, LLC

2.10-172

The Silicon Heterostructure Handbook

TABLE 2.10.1

Properties of Some Commonly Used Metals for Silicide Applications in Si CMOS Technology

Melting Point (8C)

Resistivity (mV-cm)

Schottky Barrier (eV) (on n-Si)

Reaction Temperature to Si (8C)

Thermal Stability on SiO2 (8C)

W TiN Ta Mo Ti Al

3387 2950 2996 2610 1675 660

6–15 50–200 15–20 6–15 45–50 3–4

0.65–0.7 0.45–0.5 0.55–0.6 0.6–0.7 0.5–0.55 0.65–0.75

600–700 450–500 450–500 400–700 400–500 250

1000 900 700 900

TABLE 2.10.2

Properties of Commonly Used Silicides for Salicide Applications

Formation temperature (8C) Silicide per nm of metal Silicon consumption per nm of silicide Resistivity (mV-cm) Barrier height on n-Si (eV)

26 Q & Silicide thickness (nm)

TiSi2

CoSi2

NiSi

PtSi

750–900 2.3 0.904 13–20 0.61

550–900 2.6 1.03 14–20 0.65

350–750 1.8 0.82 14–20 0.67

350–750 1.3 0.7 28–35 0.87

Silicide thickness (R) Max. silicon consumption (Q)

24

450

18

22

16

20

14

18 16

12

R

14 12

10

Q

10

8

8

6

6 5

10

15

20 25 30 35 Gate length (nm)

40

45

50

Contact silicide sheet resistance (Ohms/sq)

Metal

FIGURE 2.10.1 The predicted silicon consumption, silicide thickness, and the silicide sheet resistance values by ITRS-2003 are plotted as a function of gate length.

In addition to providing a low contact resistivity, future contact materials should satisfy several criteria, such as the formation of ultrathin silicide contacts, low silicide resistivity, and minimum temperature required to reach the low resistivity phase. Junction depth scaling requires that the thickness of the silicide be also scaled accordingly to reduce the silicon consumption and preserve the integrity of the junction. The trend can be seen in Figure 2.10.1, which shows the ITRS 2003 predictions for junction depth, silicide thickness, and silicide sheet resistance for future CMOS technology nodes.

2.10.2

Contact Metallization: Current Status

Recently, there have been concerns related to the increase of TiSi2 film resistivity on submicron gate lines due to the retarded phase transition from the high-resistivity C49 phase to the low-resistivity C54 phase

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-173

[3, 4]. Ni–silicide has been proposed as a potential candidate for advanced CMOS Si technology because Ni consumes less silicon (important for applications on ultrathin Si layers) [5], and has less risk of spiking in ultrashallow junctions. NiSi is used not only in CMOS but also in bipolar technology as the contact material because of its superior properties. NiSi does not show adverse line-width dependence of sheet resistance, which is often a big problem in TiSi2 and sometimes in CoSi2. Silicon consumption during the silicidation is the smallest among the Ti, Co, and Ni [6]. As such NiSi or nickel monosilicide are chosen as the gate, source, and drain contact material. The sheet resistance of the narrow line was found to even decrease because of the edge effect specific to NiSi [7], which is suitable for ultrashallow S/D junction formation for scaled CMOS. The mechanical stress of the NiSi film on silicon substrate is also the smallest. Contact resistance to p-type silicon, which was a problem for TiSi2, is the smallest due to its lowest barrier height, and that to n-type silicon was found to be also small [8]. Bridging failure between the gate electrode and source/drain hardly occurs for the NiSi silicide due to its reaction mechanism. On the other hand, major concern for NiSi salicide is its low heat resistance. In fact, the maximum allowable process temperature after the salicidation is around 700–7508C. In addition, NiSi can be formed by one-step annealing at low temperature (400–6008C) without any agglomeration and shows a lower resistivity and junction leakage. Aggressive scaling of the channel length and gate oxide thickness in a MOSFET leads to several problems, such as excessive tunneling current through the gate dielectric (100 A /cm2), which limits the scaling of gate oxide thickness around 12–14 A˚, polysilicon (poly-Si) gate depletion which increases the equivalent SiO2 thickness by about 3 A˚, high gate resistance, gate tunneling leakage current, and boron penetration into the channel region. Metal gate technology not only eliminates the gate depletion and boron penetration problems, but also greatly reduces the gate sheet resistance, particularly of interest in ac performance. Replacement of polysilicon gate electrodes in MOSFETs with metal thus promises many advantages. An approach analogous to the established dual poly-Si gate technology (dual metal) is desirable. The major challenge is to find two metals with suitable work functions and a way to integrate them in a CMOS process. Alternative gate dielectrics such as HfO2, ZrO2, Ta2O5, and Si3N4 are being investigated for scaling gate dielectric thickness below 20 A˚ when direct tunneling current through SiO2 may be too high for acceptable standby power consumption. Currently, the silicon nitride/oxynitride dielectric stack is in use due to its compatibility with CMOS processes. Therefore, a process that combines the advantages of dual metal gate and the high-k gate dielectric would be an attractive technology option for scaling the conventional MOSFET structures below 0.1 mm (beyond 65-nm technology node). For future technology nodes, junction formation at low temperatures is also a key necessity since high-k gate dielectrics of interest cannot withstand typical annealing temperatures used to remove implantation damage and activate the dopants.

2.10.3 Contact Metallization: Challenges While the dual metal contact approach appears to be promising at a first glance, integration of two different self-aligned silicide processes is likely to be quite challenging. Furthermore, Fermi level pinning will most likely restrict the benefits of using materials with different work functions. Thus, there is an urgent need to develop new source/drain junction and contact technologies that limit the parasitic series resistance to a fraction of the MOSFET channel resistance (see Figure 2.10.2), and requires fundamentally new approaches. Of particular interest is the smaller bandgap of Si1xGex, resulting in a smaller metal–semiconductor barrier height, which is a key advantage in reducing the contact resistivity of a metal–semiconductor contact. Interest in Si1xGex alloys for performance enhancement of MOSFETs has been escalating in recent years as well [9]. Epitaxially grown Si1xGex layers on Si, under compression, display an enhanced effective hole mobility compared to bulk-Si. This hole mobility enhancement offers a superior channel properties compared to the conventional Si channel in a MOSFET. The SiGe alloys may be incorporated in a MOSFET to enhance the device performance as: (a) compressively strained channel, (b) relaxed

© 2006 by Taylor & Francis Group, LLC

2.10-174

The Silicon Heterostructure Handbook

Poly-Si gate

Source

P+

Drain

P+ SiGe layer under compression n-type Si substrate

(a)

Rcontact

Rchannel Rextension

Rspreading

(b)

FIGURE 2.10.2 (a) Presence of Si1xGex alloy layer in different parts of a heterostructure MOSFET and (b) cross section of a MOS transistor illustrating the parasitic series resistance components.

virtual substrate for tensile strained-Si, (c) tunable work function in the gate, and (d) low-resistivity source/drain extension. Presence of Si1xGex alloys in different structural forms in the various parts of a MOSFET is shown in Figure 2.10.2. SiGe is advantageous because it can be selectively deposited as well as selectively etched compared to Si. In order to realize the improvements in electron mobility and a usable conduction band offset, it is necessary for the film to be in biaxial tension. Instead of growing a thin Si1xGex layer on Si, a thin epitaxial layer of Si grown on a thick relaxed Si1xGex buffer layer can serve this requirement. Due to the lattice mismatch, the thin Si layer is in biaxial tension and exhibits an enhancement in both electron and hole mobilities, making it useful for both n- and p-MOSFETs. It also shows fairly large band offsets (on the order of 100 meV or more) in both valence and conduction bands relative to the relaxed Si1xGex on which it is grown. This allows the tailoring of the band structure to confine both holes and electrons. Strained-Si /SiGe heterolayers on Si wafers are currently being explored as a channel material for high performance heterostructure MOSFETs [10]. Developing robust technology for forming good metal(M)/SiGe source/drain contact regions and ultimately developing a metal silicidation process for application in future strained-Si and SiGe-channel hetero-FETs with high performance is of technological interest. Several new S/D technology using Si1xGex for future CMOS technology nodes have been proposed [11, 12]. However, applying the conventional self-aligned silicide process to the strained-Si and SiGe MOSFETs is not straightforward due to the following reasons: 1. The strained-Si film is too thin to accommodate the conventional silicide. For example, if cobalt or nickel is used to make the silicide, then the Si film must be thicker than about 25 nm to accommodate the silicide. 2. The pseudomorphic strained-Si layer cannot be made thicker than 20 nm as the critical thickness depends upon the composition of the substrate, such as the mole fraction of Ge in the relaxed layer. 3. Since the strained-Si film is not thick enough to supply enough silicon to form the silicide, the silicide will consume some of the underlying SiGe buffer.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-175

The conventional approach in the Si CMOS technology to the abovementioned problems is to make the silicon thicker in the source and drain regions prior to applying the salicide process. But the addition of Si must be selective, and should be limited only to the source and drain regions, which may be obtained by a selective deposition. Selective epitaxy is usually preferred to deposit Si only to the source, drain, and gate regions. Recently, a new self-aligned salicide process that does not require an increase in the thermal budget (high temperature) and is applicable to strained-Si /SiGe materials involving Ni, has been proposed [13].

2.10.4 Poly-SiGe Gate Technology The fabrication of Si1xGex channel MOSFETs [14] always leads to the presence of Si1xGex in the source/ drain regions (see Figure 2.10.2). Perhaps the most important advantage of using Si1xGex instead of Si as a junction material is that Si1xGex provides a promising solution to the contact resistance challenge by raising the possible active doping concentration and lowering the contact barrier height [11, 15–19]. A poly-SiGe gate technology offers several advantages over conventional gate (poly-Si) conductors. First, poly-SiGe gate conductors require a relatively low-temperature rapid thermal anneal (RTA) to activate the dopants such as boron and phosphorous in the gate conductor. A low-temperature RTA facilitates the formation of ultrashallow source/drain junctions and the formation of ultratight pocket regions. Second, poly-SiGe gate conductors effectively suppress boron penetration into a gate conductor heavily doped with phosphorous. Third, poly-SiGe gate conductors can be utilized to adjust the threshold voltage of the transistor. The bandgap of Si1xGex lies between 0.67 eV (bandgap of Ge) and 1.12 eV (bandgap of Si) depending on the amount of Ge and the amount of strain in the lattice. The work function of a transistor is related to the concentration of Ge in the poly-SiGe gate conductor. This aspect is particularly advantageous in integrated circuits having transistors with several threshold voltage levels. Poly-Si1xGex gate technology offers a reduction in gate depletion compared to poly-Si as well. Bang et al. [20] have reported sheet resistance, Hall mobility, and effective carrier concentration as a function of annealing parameters for boron and phosphorus ion implanted films of poly-Si, Si0.75Ge0.25 and Si0.50Ge0.50. The films were ion implanted with boron or phosphorus at dosages between 5
1014 and 4
1015 cm2 and then thermally annealed between 5508C and 6508C from 0.25 to 120 min. The solid solubility of the most common dopants, such as B, P, and As is much higher in Si than in Ge. Boron-doped films showed decreasing minimum sheet resistance with increasing Ge mole fraction while phosphorus-doped films exhibited the reverse trend. However, the solubility of B in Si1xGex is found to drop when increasing the Ge fraction [21]. Supersaturation doping of Si1xGex with B is possible with the in situ doping technique using Si-, Ge-, and B-source gases simultaneously. For strained Si1xGex, alloying with B up to 10 at.%, due to strain compensation effect [22, 23], has been demonstrated by Gannavaram and Ozturk to yield extremely low specific resistivity and contact resistivity values [11] of 0.2-mV-cm and 1.5
108 cm2, respectively.

2.10.5 Silicidation of SiGe In order to form contacts to source /drain junctions formed by the selective Si1xGex technology, a selfaligned contact process needs to be developed. Fortunately, Si1xGex alloys react with common silicide metals to form germanosilicides with properties much like those of silicides. To form these germanosilicide contacts, a good understanding of the metal /Si1xGex ternary solid-phase reactions is necessary. It is important to identify the most promising germanosilicides as self-aligned contacts to source/drain junctions formed by the selective Si1xGex technology. Towards this end, many research groups have made significant contributions towards the understanding of silicide formation of various metals in strained-SiGe and strained-Si layers. Results of studies of interaction between Si1xGex and other transition metals than Ti, Co, and Ni, such as Pd [24, 25], Pt [26–29], Fe [30], Mo [31], W [32], and Zr [33–39] are available in the literature, but they will not be discussed in order to keep our focus on

© 2006 by Taylor & Francis Group, LLC

2.10-176

The Silicon Heterostructure Handbook

contact metallization using the SALICIDE technique in CMOS technology. Experimental SiGe germanosilicide results on Ti [40–45], Co [43, 46–50], and Ni [51–56] have been reported. It is important to note that the majority of the published work on metal /Si1xGex solid-phase reactions involve undoped Si1xGex layers. For applications in strained-Si and SiGe, NiSi is chosen because Ni reacts with both strained-Si and SiGe and forms low sheet resistance silicide and germanosilicide in the source /drain area [54]. To study the solid-state interactions between Ti, Co, or Ni and Si1xGex, the relevant phase diagrams are important. The available thermochemical data indicate that the germanides are less stable than their corresponding silicides with the same atomic composition but by replacing Ge with Si, as the heats of formation (enthalpy) or Gibbs free energies are lower (less negative) for the germanides. An approximate ternary phase diagram depicting the composition domains directly concerning the formation of NiSi1xGex as well as its interaction with Si1xGex is shown in Figure 2.10.3. The formation of germanides or germanosilicides tends to occur at a lower temperature than the formation of the silicides. The required experimental thermochemical data for the different phases involved in the pseudophase diagram were obtained from Ref. [55]. The pseudophase diagram shows that Ni, Si, Ge, NiSi, and NiGe surround the triangle. The existence and orientation of the tie lines provide the necessary information about the formation of Ni(Si,Ge) during low-temperature silicidation. A comparative study on Ni and Co reacting with single-crystal Si0.3Ge0.7 also shows a clear advantage with Ni because a continuous NiSi1xGex layer was found, yielding the desired low-resistivity contact [57]. Figure 2.10.4 indicates that the processing window for CoSi2 and TiSi2 as 800–8508C. At low annealing temperatures, cobalt yielded a very high sheet resistance, presumably due to the formation of Co(Si1yGey) and retarded the formation of low resistive CoSi2 phase. Because Ge atom hinders the transformation of Co(Si1yGey) structure to its lowest resistive Co-silicide phase CoSi2 which forms at a high temperature, 9008C, and the germanosilicide layer shows severe agglomeration. But Ni is also found to be suitable in metal–semiconductor contact formation as its lowest resistive phase is attainable below 7008C as shown in Figure 2.10.4. Figure 2.10.5(a) and (b) shows the SEM micrographs of the Ni-silicided films annealed at 5008C and 6008C for 60 s, respectively. The SEM micrographs show that the surface of the silicided film is still relatively smooth and the grain boundaries are not very prominent. Size of the grains gradually increases with increasing annealing temperature. It has been observed that agglomeration starts to take place above 7008C annealing and it results in a very abrupt increase in the sheet resistance [54, 56].

Sheet resistance (Ω/ )

103

Ni 600⬚C

NiSi

NiGe

Si

Co-germanosilicide Ti-germanosilicide

NiSi

Ni-germanosilicide

102

101

Ge

FIGURE 2.10.3 Pseudophase diagrams of the Ni–Si–Ge ternary system at 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48: 1391–1399, 2004.)

© 2006 by Taylor & Francis Group, LLC

CoSi2 TiSi2

400

500 600 700 800 Annealing temperature (⬚C)

900

FIGURE 2.10.4 Variation of sheet resistance as a function of annealing temperature. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

2.10-177

Contact Metallization on Silicon–Germanium

(a) 5008C

Acc V 9mol Magn 001 WD 5.00kV 3.0 30000x TLD 4.8 sg5

500 nm

(b) 6008C

Acc V 9mol Magn 001 WD 5.00kV 3.0 50000x TLD 4.8 sg5

500 nm

FIGURE 2.10.5 SEM micrographs of Ni-germanosilicided/Si1xGex film annealed at (a) 5008C and (b) 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

The XTEM micrographs of Ni-silicided Si1xGex films annealed at 5008C and 6008C, for 60 s are shown in Figure 2.10.6(a) and (b), respectively. The grain formation generally starts by grain boundary grooving and the atoms diffuse away from the highly curved grain boundaries. It is evident that Ge with higher diffusion coefficient in germanosilicide may out-diffuse into the grain boundaries and form a Ge-rich Si1xGex grain with an increase in the annealing temperature. At 5008C, a layer of relatively uniform NiSi0.75Ge0.25, with a thickness of about 80+10 nm, was found. However, a very small amount of Ge-rich Si1xGex grains was detected, in between the Ni(Si0.75Ge0.25) grains. Similar results were also obtained for a

© 2006 by Taylor & Francis Group, LLC

2.10-178

The Silicon Heterostructure Handbook

(a) 5008C

50 nm

SiGe

Ni(SiGe)

(b) 6008C

50 nm

SiGe

Ni(SiGe)

FIGURE 2.10.6 XTEM micrographs of the Ni-germanosilicided/Si1xGex films annealed at (a) 5008C and (b) 6008C. (After AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.)

lower anneal temperature (3008C) except that the NiSi0.75Ge0.25 was relatively uniform without the presence of any Ge-rich Si1xGex grains. At 6008C anneal temperature, Ge out-diffuses from the Ni(Si0.75Ge0.25) grain and penetrates into the grain boundaries and reacts with both Si and Ge. The distribution and thickness of such germanosilicide grains increase with the increase in annealing temperature. Due to thermal agglomeration, germanosilicide grains lose their columnar structure at the surface and at the interface of silicide–substrate. However, it is clear from the TEM images that the silicide / Si1xGex interface remains smooth within the annealing temperature range of 300–6008C [52, 58, 59]. Aldrich et al. [41, 42] have studied the Ti/Si1xGex system, and found that C49 and C54 Ti/Si1yGey phases are formed with the Ge concentration of the Si1xGex substrate (when x < 0.40). At higher annealing temperatures, the Ge concentration in the germanosilicide decreases and a Ge-rich Si1zGez

© 2006 by Taylor & Francis Group, LLC

2.10-179

Contact Metallization on Silicon–Germanium TABLE 2.10.3

Lattice Structure and Lattice Constants for Ni and Pt Silicide and Germanide

NiSi NiGe PtSi PtGe PdSi

Lattice Structure

a (A˚)

b (A˚)

c (A˚)

Orthorhombic Orthorhombic Orthorhombic Orthorhombic Orthorhombic

5.233 5.381 5.595 5.719 5.599

3.258 3.428 3.603 3.697 3.381

5.659 5.811 5.932 6.084 6.133

alloy precipitates along the grain boundaries, while germanium segregates out of the germanosilicide lattice, and is replaced by Si from the alloy. Lattice structure and lattice constants for Ni and Pt silicide and germanide are shown in Table 2.10.3. Formation of Ni2Si causes an intrinsic compressive stress [60] in agreement with the expectation of a volumetric expansion at the Ni2Si–Si interface. Forces caused by the formation of NiSi are difficult to understand due to the presence of two reaction interfaces. The force changes during the silicide formation and was modeled by Zhang and d’Heurle [61]. However, when the Ni films are subjected to prolonged isothermal annealing, stresses that developed during silicide formation gradually relax. Metal silicides and silicides /germanides have the drawback of less thermal stability and the consumption of silicon/germanium; while the latter is less of a problem for raised source/drains, scaling of vertical dimensions is never the less hampered. Studies on the effect of Ge concentration in relaxed Si1xGex on Ni silicidation process for different annealing temperatures have revealed that ternary compounds always form, and at the same time, Ge segregation has been observed when annealing temperature is above 4008C. Ge segregation with strain relaxation of the underlying Si1xGex, which commonly appears in the metal /Si1xGex reactions using conventional annealing techniques, was effectively suppressed using pulsed laser annealing for Co [50] and Ni [51–53]. Due to rapid melt and solidification processes in laser annealing, the microstructure of the germanosilicide formed by pulsed laser annealing has been shown to be superior. The segregated germanium atoms can react with Si atoms and result in a Ge-rich Si1xGex alloy adjacent to the germanosilicide. Therefore, the solid-phase reactions between metals and Si1xGex can, in general, be characterized as [42]: 1. germanosilicide formation at lower temperatures; and 2. germanosilicide formation accompanied with germanium loss at higher temperatures. The two cases can be described with the following equations: M þ Si1x Gex ! My (Si1x Gex )1y My (Si1x Gex )1y þ Si1x Gex ! My (Si1w Gew )1y þ (Si1z Gez ) (w < x < z) A schematic representation of this reaction sequence is shown in Figure 2.10.7. As shown, Ge loss from the germanosilicide occurs via Ge segregation at the grain boundaries, resulting in the formation of Ge-rich Si1zGez precipitates. The precipitates promote agglomeration and lead to higher sheet resistance due to high resistivity conduction barriers through the germanosilicide [42, 62]. The structure, melting point, typical formation temperature, specific resistivity, and Schottky barrier heights to n-type Si for monosilicides of Ni, Pt, and Pd and monogermanides of Ni and Pt thin films are shown in Table 2.10.4. As Ge segregation will degrade the contact performance, the control of the Ge segregation is crucial. Some reports have shown that the onset temperature for obtaining uniform low-resistivity Ni–SiGe is a strong function of the Ge concentration. In addition, it has further been shown that the RTA technology

© 2006 by Taylor & Francis Group, LLC

2.10-180

The Silicon Heterostructure Handbook

M

M

M

M (a)

Si1−xGex

Si1−xGex

My(Si1−xGex)1−y

Si1−xGex

My(Si1−xGex)1−y (b) Si1−xGex

Ge

Ge

Ge

Ge (c)

Si1−xGex My(Si1−wGew)1−y

Si1−zGez

My(Si1−wGew)1−y (d)

Si1−xGex

FIGURE 2.10.7 Model for the formation of Si1zGez grains between germanosilicide grains: (a) thermal reaction starts initially by the interdiffusion of metal (M), Si, and Ge, (b) formation of M-germanosilicide, (c) segregation of Ge from the germanosilicide grains, and (d) germanosilicide grains become discontinuous due to a rapid growth of Ge-rich grains.

TABLE 2.10.4 Structure, Melting Point, Typical Formation Temperature, Specific Resistivity, and Schottky Barrier Heights to n-type Si for Monosilicides of Ni, Pt, and Pd and Monogermanides of Ni and Pt Thin Films Phase

Melting Point (8C)

Reaction Temperature (8C)

Resistivity (V-cm)

SBH (eV)

NiSi NiGe PtSi PtGe PdSi

980 860 1230 1075 972

250–400 <400 200–540 — 850

14 — 80 — 30

0.65 0.88 — —

has a very narrow process window for different Ge concentrations and may not be a viable manufacturable technology for fabricating uniform Ni–SiGe. In general, due to Ge segregation during germanosilicide formation, agglomeration and strain relaxation of the unreacted Si1xGex film take place. At present, among all the germanosilicides studied, NiSi1xGex has offered the lowest resistivity and is capable of satisfying most of the needs of future CMOS technology. Since NiSi1xGex is a monogermanosilicide, it consumes less of the underlying Si1xGex compared to other digermanosilicides such as those of titanium or zirconium. However, the only concern for Ni germanosilicide appears to be its limited thermal stability. It has been observed that at temperatures equal to or higher than 5008C, Ge out-diffusion from the NiSi1xGex results in formation of Ge-rich Si1zGez precipitates, which could eventually transform into Si1zGez grains, which results in a rough top surface as well as a rough interface, high sheet resistance, and also high junction leakage. A new approach has been proposed to improve the thermal stability of NiSi1xGex. It has been reported that by inserting a thin layer of Pt between Ni and Si1xGex the thermal stability of the germanosilicide can be significantly improved through delaying the transition from NiSi to NiSi2, which is responsible for the increased resistivity and the junction consumption [63–68]. It has also been

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-181

observed that on heavily boron-doped Si1xGex, the sheet resistance of the NiSi1xGex formed with a thin Pt interlayer is more stable than that of NiSi1xGex formed from pure Ni. However, the lowest sheet resistance value achieved using Ni with a thin Pt interlayer is slightly higher than the sheet resistance of the NiSi1xGex achieved using pure Ni. For phosphorus-doped nþ-Si1xGex, Pt incorporation might change the barrier height of the contact and preliminary results on nþ-Si1xGex obtained indicate that the Pt interlayer actually improves the contact resistance for Ni germanosilicide on nþ-Si1xGex while the contact resistance with pure Pt germanosilicide is higher. Incorporation of a small amount of Pt in Ni-Si1xGex via a thin Pt interlayer between Ni and Si1xGex, in general, results in an improved thermal stability of Ni(Pt) germanosilicide.

2.10.6 Silicidation of SiGeC The large mismatch between SiGe alloys and Si leads to severe restrictions in terms of critical thickness and thermal stability. The equilibrium critical thickness of a pseudomorphic SiGe layer depends on the total strain energy in the layer and restricts the applications where high Ge concentrations are needed. Addition of substitutional carbon to a SiGe alloy gives an extra degree of freedom to control the bandgap. Moreover, the strain introduced by the Ge atoms can be compensated by C atoms, which are smaller than Ge and Si atoms, resulting in a critical thickness that can be significantly increased. Aubry-Fortuna et al. [35] have investigated the reactions between Zr and SiGeC alloys using RTA. The interactions of the metal films with the Si1xyGexCy alloys have been investigated by using various analytical tools. The authors concluded that Zr may be a good candidate for contacts on IV–IV alloys in terms of thermal stability. The reaction of Co with epitaxial SiGeC /Si layers has been investigated and compared to the reaction of Co with SiGe /Si layers by Donaton et al. [69]. The sequence of phase formation is the same as the reaction of Co with monocrystalline Si, however, cobalt disilicide is formed at much higher temperatures. The presence of C delays the disilicide formation, as a result of C accumulation at the silicide– substrate interface during the reaction, which blocks the Co diffusion paths. XRD spectra of 17 nm Co on Si0.811Ge0.18C0.009 after annealing for 30 s at different temperatures showed that after 5008C the predominant phase is Co2Si in both cases, although the presence of the monosilicide (CoSi) has been observed. Further annealing at 6008C and 7008C results in a full transformation to CoSi. At 8008C both the mono- and the disilicide phases have been identified, with the CoSi2 peaks being much more intense in the case of the reaction on SiGe than on SiGeC, indicating the presence of a higher fraction of this phase in the former film. It has been observed that the presence of C retards the formation of the disilicide phase. During the reaction, C piles up at the silicide–substrate interface, which is believed to block the Co diffusion paths. The precise role of the C atoms in this retardation is not yet fully understood and is a subject that deserves further investigation. Also, in case of Si1xyGexCy , the presence of substitutional C was found to be effective in reducing strain relaxation during solid-phase reactions to form Ti germanosilicide [44].

2.10.7 Summary One of the key challenges for future CMOS technology is to form source/drain junctions and contacts with very small parasitic series resistance. Germanosilicides of different metals were reviewed with the objective of finding the best germanosilicide candidates for low-resistivity contacts to heavily doped Si1xGex alloys. Formation of germanosilicide of Ti, Co, and Ni contacts to Si1xGex alloys has been discussed in detail. Similar to other germanosilicides, Ni /Si1xGex suffers from Ge out-diffusion. It was found that Ge lost from the Ni /Si1xGex grains formed Ge-rich Si1zGez precipitates accumulating at the germanosilicide grain boundaries. Consequently, the formation temperature of Ni/Si1xGex needs to be kept below 4508C.

© 2006 by Taylor & Francis Group, LLC

2.10-182

The Silicon Heterostructure Handbook

New junction formation technology based on selective deposition of Si1xGex alloys in source/drain regions is needed. Smaller bandgap of Si1xGex and poly-SiGe resulting in a smaller metal–semiconductor barrier height, which reduces the contact resistivity of a metal–semiconductor contact has been described. Ni and Pt germanosilicides are found to be attractive because they form both monogermanosilicides and consume much less Si1xGex than Zr(Si1 xGex)2. A new approach to form ultrathin Ni / Si1xGex layers with enhanced thermal stability by incorporating a thin Pt interlayer between Ni and Si1xGex has also been discussed. There is a growing interest to form strained-Si layers without a thick relaxed Si1xGex buffer. As the MOSFET dimensions are scaled down to tens of nanometers, the composition of the source/drain junctions will most likely have a strong impact on the strain in the channel region. In particular, the impact of Si1xGex junctions on the two sides of a MOSFET channel needs further investigation. However, the Si1xGex junction technology may provide a simple yet powerful means to form strained-Si channels without involving complex and costly fabrication procedures.

References 1. SL Zhang and M Ostling. Metal silicides in CMOS technology: past, present, and future trends. Crit Rev Solid State Materials Sci 28:1–129, 2003. 2. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, San Jose, California, 2003. 3. J Lasy, J Nakos, O Chin, and P Geiss. Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2. IEEE Trans Electron Dev 38:262–269, 1991. 4. H Jeon, CA Sukow, Honecutt, GA Rozgonyi, and RJ Nemanich. Morphology and phase stability of TiSi2 on Si. J Appl Phys 71:4269–4276, 1992. 5. MC Poon, CH Ho, F Deng, SS Lau, and H Wong. Thermal stability of cobalt and nickel silicides. Microelectron Reliab 38:1495–1498, 1998. 6. T Morimoto, HS Momose, T Iinuma, I Kunishima, K Suguro, H Okano, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. A NiSi salicide technology for advanced logic devices. IEEE IEDM Tech Dig 653–656, 1991. 7. T Ohguro, S Nakamura, M Koike, T Morimoto, A Nishiyama, Y Ushiku, T Yoshitomi, M Ono, M Saito, and H Iwai. Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films. IEEE Trans Electron Dev 41:2305–2317, 1994. 8. T Morimoto, T Ohguro, H S Momose, T Iinuma, I Kunishima, K Suguro, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI. IEEE Trans Electron Dev 42:915–922, 1995. 9. CK Maiti and GA Armstrong. Applications of Silicon–Germanium Heterostructure Devices. Bristol: Institute of Physics, 2001. 10. CK Maiti, NB Chakrabarti, and SK Ray. Strained Silicon Heterostructures: Materials and Devices. UK: IEE, 2001. 11. S Gannavaram, N Pesovic, and MC Ozturk. Low temperature (< 8008C) recessed junction selective silicon-germanium source /drain technology for sub-70 nm CMOS. IEEE IEDM Tech Dig 437–440, 2000. 12. MC Ozturk, J Liu, H Mo, and N Pesovic. Advanced Si1xGex source /drain and contact technologies for sub-70 nm CMOS. IEEE IEDM Tech Dig 375–378, 2002. 13. Q Xiang, JS Goo, J Pan, B Yu, S Ahmed, J Zhang, and MR Lin, Strained silicon NMOS with nickel– silicide metal gate. IEEE VLSI Tech Symp Dig 101–102, 2003. 14. SV Vandebroek, E Crabbe, B Meyerson, D Harame, P Restle, J Stork, and J Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Trans Electron Dev 41:94–101, 1994. 15. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. IEEE IEDM Tech Dig 253–256, 1990.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-183

16. TJ King, JR Pfiester, and KC Saraswat. A variable work function polycrystalline Si1xGex gate material for submicrometer CMOS technologies. IEEE Electron Dev Lett 12:533–535, 1991. 17. YV Ponomarev, C Salm, J Schmitz, PH Woerlee, PA Stolk, and DJ Gravesteijn. Gate workfunction engineering using poly-(Si, Ge) for high-performance 0.18 m CMOS technology. IEEE IEDM Tech Dig, 1997, 829–832. 18. PE Hellberg, SL Zhang, HH Radamson, and W Kaplan. Threshold voltage control for pMOSFETs using an undoped epitaxial Si channel and a pþ-SixGe1x gate. Solid-State Electron 44:2085–2088, 2000. 19. WC Lee, B Watson, TJ King, and C Hu. Enhancement of PMOS device performance with poly-SiGe gate. IEEE Electron Dev Lett 20:232–234, 1999. 20. DS Bang, M Cao, A Wang, KC Saraswat, and TJ King. Resistivity of boron and phosphorous doped polycrystalline Si1xGex films. Appl Phys Lett 66:195–197, 1995. 21. PE Hellberg, A Gagnor, SL Zhang, and CS Petersson. Boron doped polycrystalline SixGe1x films: Dopant activation and solid solubility. J Electrochem Soc 144:3968, 1997. 22. B Tillack, P Zaumseil, G Morgenstern, D Kruger, B Dietrich, and G Ritter. Strain compensation in ternary Si1x yGexBy films. J Cryst Growth 157:181-184, 1995. 23. S Gannavaram and MC Ozturk. Ultra-shallow pþ–n junctions for 35–70 nm CMOS using selectively deposited very heavily boron doped silicon-germanium films. ECS Meeting Proc Abs 2000, p. 73. 24. QZ Hong, JG Zhu, and JW Mayer. Solid phase epitaxy of a Ge–Si alloy on [111] Si through a Pd2Si layer. Appl Phys Lett 55:747–749, 1989. 25. A Buxbaum, M Eizenberg, A Raizman, and F Schaffler. Interaction of Pd with strained layers Si1xGex epitaxially grown on Si(100). Jpn J Appl Phys 30:3590–3593, 1991. 26. QZ Hong and JW Mayer. Thermal reactions between Pt thin films and Si1xGex alloys. J Appl Phys 66:611–615, 1989. 27. H Kanaya, Y Cho, F Hasegawa, and E Yamaka. Preferential PtSi formation in thermal reaction between Pt and Si0.80Ge0.20 MBE layers. Jpn J Appl Phys 29:L850–L852, 1990. 28. P Zhong and Y Zheng. Study of Ge movement during thermal reactions between Pt and GeSi /Si heterostructures. Appl Phys Lett 62:3259–3261, 1993. 29. HK Liou, X Wu, U Gennser, VP Kesan, SS Iyer, KN Tu, and ES Yang. Interfacial reactions and Schottky barriers of Pt and Pd on epitaxial Si1xGex alloys. Appl Phys Lett 60:577–579, 1992. 30. H Chen, P Han, XD Huang, LQ Hu, Y Shi, and YD Zheng. Semiconducting Ge–Si–Fe alloy grown on Si(100)substrate by reactive deposition epitaxy. Appl Phys Lett 69:1912–1914, 1996. 31. JS Luo, WT Lin, CY Chang, PS Shih, and TC Chang. Pulsed KrF laser annealing of Mo/Si0.76Ge0.24. Nuclear Inst Meth Phys Res B 169:129–134, 2000. 32. V Aubry, F Meyer, R Laval, C Clerc, P Warren, and D Dutartre. Thermal stability of W on RTCVD Si1xGex films. Appl Surf Sci 73:285–289, 1993. 33. Y Yasuda, O Nakatsuka, and S Zaima. Interfacial reactions of Ti/ and Zr/Si1xGex /Si contacts with rapid thermal annealing. Thin Solid Films 373:73–78, 2000. 34. Z Wang, DB Aldrich, RJ Nemanich, and DE Sayers. Electrical and structural properties of zirconium germanosilicide formed by a bilayer solid state reaction of Zr with strained Si1xGex alloys. J Appl Phys 82:2342–2348, 1997. 35. V Aubry-Fortuna, M Barthula, JL Perrossier, F Meyer, V Demuth, HP Strunk, and O ChiaxPluchery. Contacts on Si1xyGexCy alloys: electrical properties and thermal stability. J Vac Sci Technol B 16:1659–1662, 1998. 36. V Aubry-Fortuna, A Eyal, O Chaix-Pluchery, M Barthula, F Meyer, and M Eizenberg. Thermal stability and electrical properties of Zr/Si1xyGexCy contacts after rapid thermal annealing. Appl Phys Lett 73:1248–1250, 1993. 37. V Aubry-Fortuna, G Tremblay, F Meyer, Y Miron, Y Roichman, M Eizenberg, F Fortuna, U Hormann, and H Strunk. Phase formation and strain relaxation during thermal reaction of Zr and Ti with strained Si1xyGexCy epilayers. J Appl Phys 88:1418–1423, 2000.

© 2006 by Taylor & Francis Group, LLC

2.10-184

The Silicon Heterostructure Handbook

38. V Aubry-Fortuna, O Chaix-Pluchery, F Fortuna, C Hermandez, Y Campidelli, and D Bensahel. Structural properties and stabilities of Zr and Ti germanosilicides formed by rapid thermal annealing. J Appl Phys 91:5468–5473, 2002. 39. V Aubry-Fortuna, M Barthula, F Meyer, A Eyal, C Cytermann, M Eizenberg, and O Chaix-Pluchery. Characterizations of Zr/Si1xyGexCy after rapid thermal annealing. Proc Mater Res Soc 1998, pp. 49– 53, 1998. 40. JB Lai and LJ Chen. Effects of composition on the formation temperatures and electrical resistivities of C54 titanium germanosilicide in Ti–Si1xGex systems. J Appl Phys 86:1340–1345, 1999. 41. DB Aldrich, YL Chen, DE Sayers, RJ Nemanich, SP Ashburn, and MC Ozturk. Effect of composition on phase formation and morphology in Ti–Si1xGex solid phase reactions. J Mater Res 10:2849– 2863, 1995. 42. DB Aldrich, YL Chen, DE Sayers, RJ Nemanich, SP Ashbun, and MC Ozturk. Stability of C54 titanium germanosilicide on a silicon–germanium alloy substrate. J Appl Phys 77:5107–5114, 1995. 43. Z Wang, DB Aldrich, YL Chen, DE Sayers, and RJ Nemanich. Silicide formation and stability of Ti/ SiGe and Co/SiGe. Thin Solid Films 270:555–560, 1995. 44. R Eyal, R Brener, R Beserman, M Eizenberg, Z Atzmon, DJ Smith, and JW Mayer. The effect of carbon on strain relaxation and phase formation in the Ti/Si1xyGexCy /Si contact system. Appl Phys Lett 69:64–66, 1996. 45. JC Huang, JS Luo, WT Lin, CY Chang, and PS Shih. Effects of an interposed Mo layer on the interfacial reactions of Ti/Si0.76Ge0.24 by rapid thermal annealing and pulsed laser annealing. Semicond Sci Technol 15:941–945, 2000. 46. SP Ashburn, MC Ozturk, G Harris, and DM Maher. Phase transitions during solid-phase formation of cobalt germanide by rapid thermal annealing. J Appl Phys 74:4455–4460, 1993. 47. JS Luo, WT Lin, CY Chang, WC Tsai, and SJ Wang. Interfacial reactions of the Co/Si1xGex system. Mater Chem Phys 48:140–144, 1997. 48. O Nur, M Willander, HH Radamson, MR Sardela, Jr., GV Hansson, CS Patersson, and K Maex. Strain characterization of CoSi2 /n-Si0.9Ge0.1 /p-Si heterostructures. Appl Phys Lett 64:440–442, 1994. 49. O Nur, M Willander, L Hultman, HH Radamson, GV Hansson, MR Sardela, and JE Greene. CoSi2 / Si1xGex /Si(0 0 1) heterostructures formed through different reaction routes: silicidation-induced strain relaxation, defect formation and interlayer diffusion. J Appl Phys 78:7063–7069, 1995. 50. JS Luo, YL Hang, WT Lin, CY Chang, and PS Shih. Interfacial reactions of Co/Si0.76Ge0.24 and Co(Si0.76Ge0.24)/Si0.76Ge0.24 by pulsed KrF laser annealing. J Mater Res 14:3433–3438, 1999. 51. JS Luo, WT Lin, CY Chang, PS Shih, and FM Pan. Annealing effects on the interfacial reactions of Ni on Si0.76Ge0.24 and Si1xyGexCy . J Vac Sci Technol A 18:143–148, 2000. 52. JS Luo, WT Lin, CY Chang, and WC Tsai. Pulsed KrF laser annealing of Ni/Si0.76Ge0.24 films. J Appl Phys 82:3621–3623, 1997. 53. JS Luo, WT Lin, CY Change, and WC Tsai. Interfacial reactions of Ni on Si0.76Ge0.24 and Si by pulsed laser annealing. Mater Chem Phys 54:160–163, 1998. 54. HB Zhao, KL Pey, WK Choi, S Chattopadhyay, EA Fitzgerald, DA Antoniadis, and PS Lee. Interfacial reactions of Ni on Si1xGex (x ¼ 0.2,0.3) at low temperature by rapid thermal annealing. J Appl Phys 92:214–217, 2002. 55. T Jarmar, J Seger, F Ericson, D Mangelinck, U Smith, and SL Zhang. Morphological and phase stability of nickel-germanosilicide on Si1xGex under thermal stress. J Appl Phys 92:7193–7199, 2002. 56. KL Pey, WK Choi, S Chattopadhyay, HB Zhao, EA Fitzgerald, DA Antoniadis, and PS Lee. Thermal reaction of nickel and Si0.75Ge0.25 alloy. J Vac Sci Technol A 20:1903–1910, 2002. 57. CY Lin, WJ Chen, CH Lai, A Chin, and J Liu. Formation of Ni germeno-silicide on single crystalline Si0.3Ge0.7/Si. IEEE Electron Dev Lett 23:464–466, 2002. 58. S Zaima, O Nakatsuka, A Sakai, J Murota, and Y Yasuda. Interfacial reaction and electrical properties in Ni /Si and Ni/SiGe(C) contacts. Appl Surf Sci 224:215–221, 2004.

© 2006 by Taylor & Francis Group, LLC

Contact Metallization on Silicon–Germanium

2.10-185

59. V Aubry, OC Pluchery, F Fortuna, C Hernandez, Y Campidelli, and D Bensahel. Structural properties and stability of Zr and Ti germanosilicides formed by rapid thermal annealing. J Appl Phys 91:5468–5473, 2002. 60. CJ Tsai and KH Yu. Stress evolution during isochronal annealing of Ni /Si system. Thin Solid Films 350:91–95, 1999. 61. SL Zhang and FM d’Heurle. Stresses from solid state reactions — a simple model silicides. Thin Solid Films 213:34–39, 1992. 62. KL Pey, S Chattopadhyay, WK Choi, Y Miron, EA Fitzgerald, DA Antoniadis, and T Osipowicz. Stability and composition of Ni-germanosilicided Si1xGex films. J Vac Sci Technol B 22:852–858, 2004. 63. D Manglelinck, JY Dia, JS Pan, and SK Lahiri. Enhancement of thermal stability of NiSi films on (100)Si and (111)Si by Pt addition. Appl Phys Lett 75:1736–1738, 1999. 64. LW Cheng, SL Cheng, LJ Chen, HC Chien, HL Lee, and FM Pan. Formation of Ni silicides on (001) Si with a thin interposing Pt layer. J Vac Sci Technol A 18:1176–1179, 2000. 65. JF Liu, HB Chen, JY Feng, and J Zhu. Improvement of the thermal stability of NiSi films by using a thin Pt interlayer. Appl Phys Lett 77:2177–2179, 2000. 66. DZ Chi, D Mangelinck, SK Lahiri, PS Lee, and KL Pey. Comparative study of current–voltage characteristics of Ni and Ni(Pt)-alloy silicided pþ/n diodes. Appl Phys Lett 78:3256–3258, 2001. 67. JF Liu, JY Feng, and J Zhu. Comparison of the thermal stability of NiSi films in Ni /Pt /(111)Si and Ni/Pt /(100)Si systems. J Appl Phys 90:745–749, 2001. 68. PS Lee, KL Pey, D Mangelinck, J Ding, DZ Chi, and L Chan. New silicidation technology with Ni(Pt) alloy for MOSFETs. IEEE Electron Dev Lett 22:568–570, 2001. 69. RA Donaton, K Maex, A Vantomme, G Langouche, Y Morciaux, AS Amour, and JC Sturm. Co silicide formation on SiGeC /Si and SiGe /Si layers. Appl Phys Lett 70:1266–1268, 1997. 70. AR Saha, S Chattopadhyay, and CK Maiti. Contact metallization on strained-Si. Solid-State Electron 48:1391–1399, 2004.

© 2006 by Taylor & Francis Group, LLC

2.11 Selective Etching Techniques for SiGe/Si 2.11.1 2.11.2

Introduction........................................................... 2.11-187 Process Development for Industrial Applications ........................................................... 2.11-188 Equipment . Influence of the Different Parameters . Process Development . Selective Passivation of Si . Selective Passivation of SiGe . Other Solutions under Consideration

2.11.3

Introduction . Implementation of the SON Process for MOSFET . SON MOSFETs with Metal Gates . SON without Channel Rupture: ‘‘Localized SOI’’ . Implementation of the SON Process to Gate All Around (GAA) MOSFETs . Implementation to Multigate Devices . SON and Microelectromechanical Systems (MEMS)

S. Monfray and T. Skotnicki ST Microelectronics

S. Borel CEA LETI

Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology .............. 2.11-196

2.11.4

Summary ................................................................ 2.11-207

2.11.1 Introduction SiGe alloys are used extensively for their electrical properties (bandgap engineering by adjusting the Ge content, carriers mobility improvement). With the progress in deposition by epitaxial growth, a new application is emerging, based on the crystalline properties of the material. Indeed, from pure Si (x ¼ 0) to pure Ge (x ¼ 1), any Si1
xGex alloy can be deposited on Si with the same crystal structure and the same lattice constant (in the growth plane) as the substrate, provided that it does not exceed the critical thickness for plastic relaxation (Ec). As a consequence, SiGe can be buried between mono-Si layers without modifying their conduction properties. This method is used in several advanced microelectronics architectures that require a thin single-crystal Si-film isolated from the substrate by a cavity: the SiGe layer is used as a sacrificial layer for lateral etching. In this approach, the selectivity is crucial because both similar materials are exposed to the complete etching process whereas only one has to be removed. The objective of this chapter is to describe here the mainstream of the selective SiGe etching and its applications. In particular, we present the Silicon-on-Nothing (SON) process and its possible technological variants within the process of simplification, and improvement of versatility and robustness. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors. 2.11-187 © 2006 by Taylor & Francis Group, LLC

2.11-188

2.11.2

The Silicon Heterostructure Handbook

Process Development for Industrial Applications

Getting some selectivity between SiGe alloys and pure Si is challenging because of the similarity between the two materials. Indeed, they have the same crystal structure (diamond), their lattice constants are not so different (<1% for Ge contents <25%) and their components (Si and Ge) are very close in terms of reactivity to halogen-based chemistries (same external electronic configuration, same kind of volatile etching products). Anyway, it is possible to discriminate between them in highly selective etching processes. In fact, there is no clear explanation about the mechanisms responsible for this selectivity. Neither the strain of SiGe deposited on Si, nor the relative strengths of Si

Si and Si

Ge bonds or electronic effects can explain the high etch rates (ERs) that can be obtained on SiGe as compared to that of pure Si. This section gives a way of obtaining a tunnel by lateral etching of SiGe in a Si/SiGe/Si stack. It details a tool that can be used for this purpose, its functioning, but also a process with its performances and limitations (Figure 2.11.1).

Equipment Shibaura CDE-80 is an industrial tool (Figure 2.11.2) dedicated to chemical dry etching by activated gases, i.e., by neutrals coming from a remote plasma.

SiGe

SiGe

FIGURE 2.11.1 Selective lateral etching of SiGe in a Si/SiGe/Si stack (cross section).

FIGURE 2.11.2 Schematic drawing of CDE-80 etching tool.

© 2006 by Taylor & Francis Group, LLC

2.11-189

Selective Etching Techniques for SiGe/Si

A gas mixture is injected in the etching chamber through a quartz tube (discharge tube) connected to a Teflon tube (transfer tube). The pressure of the system is regulated by an auto pressure controller connected to a dry pump. Then, a plasma is ignited in the discharge tube by using a 2.45 GHz microwave generator. The gas molecules are dissociated and ionized by energetic electrons, leading to several kinds of species. Some of these reactions are given below, as well as examples concerning CF4: .

.

Production of radicals and atoms: AB þ e ! (AB)*

(2:11:1)

CF4 þ e ! (CF4 )*

(AB)* ! A þ B

(2:11:2)

(CF4 )* ! CF3 þ F

Production of electrons and ions by dissociative ionization: AB þ e ! Aþ þ B þ 2e

(2:11:3)

CF4 þ e ! CF3 þ þ F þ 2e

A þ e ! Aþ þ 2e

(2:11:4)

CF3 þ e ! CF3 þ þ 2e

As the plasma is cold and not highly ionized (a < 10
4), ions and electrons are much less numerous than molecules, radicals, and atoms. Moreover, their lifetime is much shorter, so only a few of them reach the Teflon tube: .

Loss of electrons and ions: ABþ þ e ! A þ B

(2:11:5)

CF2 þ þ e ! CF þ F

Neutral species reach the transfer tube and diffuse through it to the etching chamber. They also partially recombine: .

Loss of radicals and atoms: A þ B þ M ! AB þ M

(2:11:6)

CF þ F þ CF4 ! CF2 þ CF4

As a consequence, the etching of the wafer consists of reactions between the material to etch and neutral species remaining from the discharge. It is purely chemical (no ion bombardment), that is why it is isotropic (no favored direction) and potentially selective (no sputtering). The etching is mainly driven by the composition of the gas mixture, but other parameters can be tuned in order to control it.

Influence of the Different Parameters Gas Mixture As mentioned above, this parameter is of primary importance because of the chemical nature of the process. The gases that are used must contain elements which have a spontaneous affinity for the material to etch, and they must form volatile products with it. Silicon and germanium are commonly etched with halogen-based chemistries because of the easy formation of volatile SiX4 and GeX4 (X ¼ F, Cl, Br) in reactive ion etching. In the case of chemical dry etching, there is no ion bombardment to assist the reaction, and all halogens are not of equal efficiency. Fluorine has a spontaneous action on Si or Ge, so fluorinated compounds are the basic gases for Si or SiGe isotropic etching. Other gases may be added in order to modify the level of dissociation/recombination or the passivation layers at the surface of the wafer. For example, a small amount of oxygen contributes to

© 2006 by Taylor & Francis Group, LLC

2.11-190

The Silicon Heterostructure Handbook

the dissociation of CFx by forming CO2 and atomic fluorine, but an excess of O2 leads to a passivating oxide layer that prevents the etching (Figure 2.11.3). Microwave Power The microwave power sets the level of dissociation in the plasma, i.e., the ratio between active species and inert molecules. At low power, the discharge is unstable and the dissociation is poor. The small number of active species make the etch rate quite low. By increasing the power, the production of electrons is increased so the initiation of the discharge and its stability are easier, leading to a greater dissociation (equations (2.11.1) to (2.11.4)). The amount of active species is higher and the etch rate is increased (Figure 2.11.4). Pressure Pressure determines the rate of recombinations between the different species. An increase of the pressure corresponds to a decrease of the mean free path of the species (Figure 2.11.5). They undergo more collisions and may become inert (Equations (2.11.5) and (2.11.6)). The result is a decrease of the etch rate. Temperature During the process, the quartz tube warms up because of energy dissipated by the discharge. For highpower processes, the tube temperature can exceed 1508C after a few minutes. The consequence is an

Maximum dissociation of CFx

Etch rate (mm/min)

5000

SiGe

4000 3000 2000 1000 Si

Passivating Oxide

0 0

50

100

200

300

400

500

Oxygen amount (sscm)

FIGURE 2.11.3

Effect of O2 addition into pure CF4.

SiGe etch rate (Å/min)

25000 20000 15000 10000 5000 0 200

FIGURE 2.11.4

400 600 Microwave power (W)

Effect of the microwave power on SiGe lateral etch rate.

© 2006 by Taylor & Francis Group, LLC

800

2.11-191

Selective Etching Techniques for SiGe/Si

25000 SiGe etch rate (Å/min)

20000 15000 10000 5000 0 300

600

900 Pressure (mT)

1200

1500

150

24500

100

22500 20500

50 18500

ER (Å/min)

T (˚C)

FIGURE 2.11.5 Effect of the pressure on SiGe lateral etch rate.

16500

0 0

100

200

300

400

Seasoning time (s)

FIGURE 2.11.6 Effect of a seasoning on the quartz tube temperature and on SiGe lateral etch rate.

increase of the etch rate due to more dissociation of the gas mixture. But at low power, or for short etching processes, this phenomenon is negligible (Figure 2.11.6). The temperature of the electrostatic chuck (ESC) that holds the wafer may also play an important role in the control of the reactions that take place on it. Indeed, some products are not volatile at low temperature but they can be produced, gasified, and pumped away at higher temperature (e.g., SiF4 is volatile from
868C at 1 atm). In this process, the chuck temperature is water cooled by a chiller between 58C and 258C but its modifications are not easy, so it is kept constant at 108C.

Process Development Method The process used for the realization of a tunnel in a Si/SiGe/Si stack has to etch SiGe with a high selectivity to pure Si. In other words, the ratio between the tunnel depth and the Si loss must be maximized. This ratio is considered as the most representative index for the selectivity (Figure 2.11.7): Selectivity ¼

Tunnel depth Si loss

This complex structure is essential in order to evaluate the selectivity of a lateral etching process because any simplified method would lead to fallacious results (Figure 2.11.8). Actually, both materials must be present simultaneously on the wafer and the distance between them must be as small as possible. For example, the ratio between SiGe and Si etch rate measured on two independent wafers is lower than the tunnel depth/Si loss (Td/Sl) ratio. This suggests that the presence of SiGe has an influence on Si etch rate.

© 2006 by Taylor & Francis Group, LLC

2.11-192

The Silicon Heterostructure Handbook

Ideal process

Real process

Si Nominal height

SiGe

Si loss Tunnel depth

Si

FIGURE 2.11.7 Selectivity characteristics of a tunnel etching process.

(a)

(b)

(c)

(d)

FIGURE 2.11.8 Relevance of the method used to evaluate the selectivity of a lateral etching process. (a) Two independent wafers covered with SiGe or Si; (b) SiGe and Si samples on an inert holder wafer; (c) the same SiGe and Si samples side by side; and (d) patterned wafer with Si/SiGe/Si stack.

Each tested recipe is performed in the same experimental conditions: . . . .

FH wet treatment in order to remove the native oxide on both materials Etching of a patterned wafer with Si/SiGe/Si stack (20% Ge) Stripping in a O2 plasma in order to remove the resist that protects the upper side of Si SEM cross-section observation in order to determine Td and Sl.

It is then possible to compare the values of Td/Sl or the relative positions of each recipe on the graph in Figure 2.11.9. Best Point Many gas mixtures have been tested, using CF4, CH2F2 or Cl2 as the etching gas, adding N2 or O2 in different ratios. Finally, the chemistry that gives the best results is made of pure CF4 (300 sccm). The pressure is set to the maximum value in order to minimize the etch rate (see section on ‘‘Pressure’’) and better control the process. With 300 sccm of gas, the maximum pressure that can be reached is 1500 mT. A consequence of this high pressure is a selectivity improvement, compared with lower pressure recipes. The same behavior is observed with power: at low power, the etch rate decreases (see section on ‘‘Microwave Power’’) and the selectivity between SiGe and Si is improved. A power of 200 W is applied because lower values lead to plasma instability (Table 2.11.1). Performances The graph of Figure 2.11.10, plotted after 60 sec of the process described above, shows a Td/Sl ratio around 40, which means that when a 100 nm-deep tunnel is etched in the SiGe layer, only 2.5 nm of Si are consumed beneath and underneath the entrance of the tunnel.

© 2006 by Taylor & Francis Group, LLC

2.11-193

Selective Etching Techniques for SiGe/Si

Si consumption

SI1 SI2

SI3

Td

Distance to the end of the tunnel

FIGURE 2.11.9 Comparison between different recipes, based on SEM cross-section images. Recipe 2 (dashed line) is more selective than recipe 1 (dashed–dotted line) but less than recipe 3 (dotted line).

TABLE 2.11.1

Process Parameters of the Best Point for Tunnel Etching

CF4 Flow

Pressure

MW Power

ESC Temperature

300 sccm

1500 mT

200 W

108C

Si consumption (nm)

10 8 6 4 2 0 0

50

100 150 200 250 300 Distance to the end of the tunnel (nm)

350

FIGURE 2.11.10 Characterization of the best process for tunnel etching. (a) SEM cross-section micrograph of the tunnel. (b) Si consumption all along the tunnel.

© 2006 by Taylor & Francis Group, LLC

2.11-194

The Silicon Heterostructure Handbook

The following points are to be noted. The Si loss is higher if the material is doped with arsenic. On the contrary, if it is doped with boron, the Si is almost not impacted. As and B do not need to be activated to play their role, which suggests that this phenomenon is not electron-linked. The process is sensitive to the germanium concentration in the alloy. The more Ge it contains, the faster it gets etched by fluorine atoms. A SiGe/Si multistack with Ge contents from 15% up to 30%, exposed to this process, shows the evolution of the etch rate as a function of [Ge] (Figure 2.11.11). The real structure is represented below, after 10 sec of etching. The measurement of the different etch rates may show a nonlinear relationship between [Ge] and SiGe etch rate. But insofar as all tunnels have a different depth, some additional parameters may have to be taken into account, such as the accessibility of the etching species at the end of the tunnel. Limitations As mentioned in ‘‘Method,’’ the presence of SiGe has an influence on Si etch rate since the selectivity obtained with two blanket wafers is very different from that obtained on a patterned wafer with stacked layers. This is a limitation of the process because in almost all industrial applications, it is used for a complete removal of the SiGe sacrificial layer, which means that at the end of the process, there is only silicon on the wafer. At this moment, Si starts to be etched by fluorine species and the benefit of the selectivity may be rapidly lost. The qualitative representations of Si and SiGe etch rate are given in Figure 2.11.13. They show that as long as some SiGe remains, the Si is preserved, but as soon as SiGe has been totally removed from the pattern, the Si etch rate increases.

FIGURE 2.11.11 Structure used to show the impact of the Ge content on the SiGe ER.

FIGURE 2.11.12  30%.

SEM cross-section micrograph of tunnels after etching of a SiGe/Si multistack with 15%  [Ge]

© 2006 by Taylor & Francis Group, LLC

2.11-195

Selective Etching Techniques for SiGe/Si

ER

SiGe

Si No more SiGe

Etching time

FIGURE 2.11.13

Qualitative evolution of Si and SiGe etch rate during the process.

FIGURE 2.11.14

Si loss on small patterns during the etching of large patterns.

A consequence is that the process time must be adjusted in order to minimize the over-etch (necessary in case of bad uniformity of a tool). Another consequence is that large patterns and small patterns cannot be achieved at the same time because large patterns require a longer process time, during which small patterns are over-etched (Figure 2.11.14).

Selective Passivation of Si A possible way of skirting this issue could be the development of a process that passivates Si selectively to SiGe. It would offer a twofold advantage: 1. The entrance of the deep tunnels would be as high as their end (no bevel shape, good integrity of the transistor channel) 2. Small patterns could cohabit with large patterns (no boom in Si etch rate at SiGe disappearance). As silicon oxide is chlorine-resistant whereas germanium oxide is not, a process using O2 and Cl2 may etch oxidized SiGe and stop on oxidized Si.

Selective Passivation of SiGe A process using a mixture of CF4/CH2F2/N2/O2 at high pressure (1500 mT) shows a Si etch rate about 8000 A˚/min and a SiGe etch rate that cannot be measured (Figure 2.11.15). This almost infinite selectivity is due to a passivating layer on SiGe. This process enables the production of tunnels between two SiGe thin layers with no limitation of depth.

© 2006 by Taylor & Francis Group, LLC

2.11-196

The Silicon Heterostructure Handbook

FIGURE 2.11.15 Use of a Si process (infinite selectivity to SiGe) on a Si/SiGe/Si stack.

Other Solutions under Consideration Other kinds of tools, as well as wet approaches, are also tested in order to get a high selectivity between SiGe and Si, but the trends are similar to those obtained on CDE-80 equipment.

2.11.3 Applications of Selective SiGe Etching: Silicon-on-Nothing (SON) Technology Introduction Extremely thin (nanometric) films of monocrystalline silicon on insulator are widely recognized for their potential for end-of-roadmap CMOS transistors [1–7]. Various fabrication technologies (SIMOX, BESOI, Smart Cut, ELTRAN, ELO, etc.) have been developed permitting continuous downscaling of the Si film and the BOX, but the commercial availability of such thin films as 5–15 nm still faces problems of feasibility and dispersions. In contrast with any other SOI technology, in the SON process, the silicon film and buried insulator, both of nanometric scale, are defined by epitaxy on a bulk substrate. Therefore, the SON process opens access to extremely thin films (the silicon channel as well as the BOX) at the same time offering the thickness control as fine as the resolution of the epi process (less than 1 nm). In addition, no more than one (bulk-type) wafer is needed to fabricate the SON layers, in contrast to two wafers in wafer-bonding-type techniques. Successful and highly selective SiGe tunnel etching can be obtained by wet etching using a variety of solvents. Table 2.11.2 summarizes our own experiences with SON-tunnel wet etching. In spite of the

TABLE 2.11.2

Efficiency of SiGe Wet-Etch Solvents Measured in SON Tunnel Lengths

Solution Composition

40 ml HNO3 20 ml H2O2 5 ml HF (5%)

Etch time SON SiGe 50% SON SiGe 30%

© 2006 by Taylor & Francis Group, LLC

1 min 21 nm —

3 min 53 nm <1 nm

10 min — 10 nm

70 ml HNO3

80 ml HNO3

40 ml acetic acide 20 ml HF (5%)

40 ml H2O 10 ml HF (5%)

3 min — 30 nm

3 min — 10 nm

10 min — 70 nm

2.11-197

Selective Etching Techniques for SiGe/Si

good selectivity and etching efficiency obtained with wet-etching, in our experiments a plasma-assisted isotropic dry etching process was used in order to ensure better process reproducibility. As presented in the previous section, a well controlled and reproducible tunnel etching can also be obtained by dry etching. We have used for that a downstream plasma reactor (STRATA from GAZONICS) using NF3, He, and N2. The two important features of this reactor are that: (i) the reactive species are created by plasma and transported to the wafer where the reaction is purely chemical, (ii) the substrates are not biased that practically removes the danger of plasma damage to the wafer. The empty tunnel resulting from this selective etching is the key point for the realization of a thin single-crystal Si film isolated from the substrate by a cavity. Alternatively, we have also used the SHIBAURA reactor using a process very similar to that of STRATA except that CF4 replaces NF3. The first application of the selective SiGe etching was dedicated to the realization of notched gates [8] in order to reduce the source and drain extensions overlap and also to improve the fringing capacitances. In this way, extremely aggressive gates were fabricated within the current state of the art of lithography process, Figure 2.11.16.

Implementation of the SON Process for MOSFET The SON process is very suitable for fabricating thin-film SOI-like devices [9–15]. For this purpose, two selective epitaxial growth (SEG) steps need to be inserted into the conventional CMOS flow just after accomplishing the shallow trench isolation (STI) process. The first SEG step provides a SiGe layer, and the second a Si layer, both layers are grown selectively on active areas (Figure 2.11.17(a)). Next the process comes back to the conventional CMOS flow and runs the usual way up to the step of lowly doped drain (LDD) implants. After the first nitride spacer, a second (TEOS) sacrificial spacer is formed. Then, using the gate and spacers as masks, shallow trenches in active areas are etched to open access to the SiGe layer (Figure 2.11.17(b)) that is selectively etched out (Figure 2.11.17(c)). After this step, the gate stack (polysilicon, gate-oxide and the silicon channel) together with the adjacent spacers is hanging above an empty space — the tunnel remaining after the SiGe etch out. As schematically shown in Figure 2.11.17(d), the stability of the gate stack at this step is due to its bridging across the active area supported by the STI. The tunnel is next cleaned and its inner walls are passivated in an RTO step that is aimed at improving the interface quality. Optionally, this step can be preceded by a sacrificial oxidation aimed at smoothing and removing the inner-tunnel interface.

16 nm 79 nm

Poly-Si 17 nm

Poly-SiGe

16 nm 5 nm

FIGURE 2.11.16 etched gate.

PMOS

TEM cross section of a 16 nm gate length planar CMOS realized with a poly-SiGe selectively

© 2006 by Taylor & Francis Group, LLC

2.11-198

The Silicon Heterostructure Handbook

Si

Gate

Spacer

SiGe

Si SiGe

Si

(a) (b)

Spacer

Selective isotropic removal of SiGe

Gate

STI

Si

(d)

(c) TEOS spacer cleaning

Gate

Selective epitaxial growth

Gate S

Si

Tunnel filled with Dielectric

(e)

D

Si

RTO/HTO

Si3N4

(f)

FIGURE 2.11.17 Key steps of the basic SON process in application to CMOS flow. (a) Selective SiGe/Si epitaxy; (b) standard gate-stack integration and SD etching; (c) SD-etching for the buried SiGe layer access and selective isotropic SiGe removal; (d) after SiGe removal, all the gate stack becomes sustained over the active area; (e) tunnel filling with dielectric and Si-cleaning before selective epi-growth; (f) source and drain area becomes contacted with the conduction channel.

Next, the entire structure is recovered with the first thin layer of deposited dielectric (HTO), sufficiently thin to leave a throughway via the tunnel. The second deposited dielectric (nitride) fulfills completely the tunnel but also recovers all other parts of the structure. Thanks to the dual-dielectric structure, one can, however, etch-back the nitride (everywhere except inside the tunnel) in an anisotropic plasma etch using the HTO layer as an etch-stopper. The remaining HTO oxide is very thin and thus easy to get rid of when cleaning the S/D trenches preparing them for the SEG step. This cleaning step is selective to oxide thus preserving the nitride in the spacers and inside the tunnel. In contrast, the second TEOS spacer is etched out thus exposing the upper part of the extensions to the SEG. The more aggressive is the cleaning, the larger part of the extension is exposed to SEG (Figure 2.11.17(e)). With this double-spacer and dual-dielectric process, wide range of cleaning conditions may be used without jeopardizing either the SEG quality, or the reunification between S/D and the channel. It should be realized that the additional surface of the channel exposed to SEG thanks to the removal of the second TEOS spacer is much larger than the vertical sidewall of the channel. Thanks to this developed exposure surface, the SEG starts not only at the bottom of the S/D trenches but also directly on the exposed parts of the extensions, thus guarantying a reliable reunification (Figure 2.11.17(f)).

© 2006 by Taylor & Francis Group, LLC

2.11-199

Selective Etching Techniques for SiGe/Si

In this way, we can see Figure 2.11.18 in which SON transistors show perfect morphology. On the color map of the entire structure are presented 80 nm transistors with silicon-conduction channel as thin as 20 nm with only 20 nm of buried dielectric. For very thin-film SOI devices the concern is about the bottom interface quality and the crystallinity of the film. The high-resolution TEM cross-section (Figure 2.11.19) made on a finished extremely thin 5 nm-thick SON transistor demonstrates that the bottom interface is almost as smooth as the upper one. This is certainly thanks to the very high SiGe etching selectivity but also due to the fact that the etching is a chemical reaction rather than aggressive ion etching process. This figure also illustrates the perfect monocrystalline structure of the channel (see the lattice regularity). Another major advantage of SON devices is its compatibility with the silicidation process. In general, very thin-film SOI devices need SEG steps to allow S/D silicidation, leading to many issues: charging effects, temperature control on SOI substrates, start on amorphized areas after LDD implant, etc. In the case of SON process, thanks to the continuity between S/D area and the bulk, silicidation can occur without problems. Figure 2.11.20 and Figure 2.11.21 show examples of electrical results obtained on 80 nm NMOS transistors with 30 A˚ of physical oxide thickness and on 38 nm PMOS transistors with 20 A˚ of physical oxide thickness. Concerning the output characteristics, an improvement of as much as 30% at high voltage (Vg
Vth ¼ 1.8 V) (Figure 2.11.20) and as much as 130% at low voltage (Vg
Vth ¼ 0.6 V),

SON MOSFET

80 nm Poly Si SiO2 Si3N4

Si epi Si channel

Tunnel filled with dielectric

FIGURE 2.11.18 FIB/TEM color-map illustrating perfect SON morphology; note the uniform thickness of the buried dielectric and of the Si channel and the comfortable reunification between the channel extremities and the S/D domains.

FIGURE 2.11.19 Magnification (TEM picture) of the buried-dielectric/channel/Gate_ox/poly-gate stack for a very thin Si-film (TSi ¼ 5 nm). Note good quality of bottom and upper tunnel interfaces and perfect crystallinity of the channel.

© 2006 by Taylor & Francis Group, LLC

2.11-200

The Silicon Heterostructure Handbook

Reference SON

Bulk ref. @−12 V

450

+30%

200 + 130%

100 0 0.5

1

1.5

Vdrain (V)

FIGURE 2.11.20 Lin
Id(Vd) of a 80-nm NMOS SON transistor. The drive current is improved by 30% compared to bulk reference. At low Vdd, the improvement reaches 130%.

2

350

1⫻10−4 1⫻10−5

400

300

0 Tsi = 20 nm, TOX = 30Å

1⫻10−3

500

DIBL = 60 mV

300

1⫻10−6 1⫻10−7

250

1⫻10−8

200 150

1⫻10−9

50

1⫻10−10

0 −1.4

−1

−0.6 −0.2 Vg(V)

Idrain (A/µm)

Vg-Vth 700 1.8 V 600 1.5 V 1.2 V 500 0.9 400 0.6 V

Idrain (µA/µm)

Idrain (µA/µm)

800

1⫻10−11 0.2 Tsi = 9 nm, TOX = 20 Å

FIGURE 2.11.21 Lin
Id(Vg) and log-Id(Vg) of our 38 nm PMOS SON device. The architecture shows highresistive SCE properties with only 60 mV of DIBL (pockets implanted). Ioff current is only equal to 100 nA/mm.

has been measured, reflecting large improvement in transconductance (confirmed by direct measurements). 38 nm SON PMOS devices are presented with a 9-nm-thick Si-conduction channel. This architecture leads to a really SCE-resistive device, showing less than 60 mV of DIBL for such an aggressive gate length, (Figure 2.11.21). In absolute numbers, the drain current of those silicided SON pMOSFETs was measured as high as 340 mA/mm at Vg ¼
1.4 V (with a physical oxide thickness of 20 A˚) with only 100 nA/mm Ioff, which is consistent according to the ITRS roadmap. Those performances are really competitive compared to the state of the art for such aggressive gate length, and can be improved by reducing the gate oxide thickness. In fact, for such aggressive gate length, bulk references were showing so high SCE effects that Id(Vg) characteristics demonstrate quasi-short cuts between the extensions. This point shows that the SON architecture is definitely a major advantage for the aggressive ULSI area.

SON MOSFETs with Metal Gates A major issue of very thin FD devices is that Vth decreases with the Si-film thickness (TSi), leading to intolerably high off current. The threshold voltage level of FD devices with thin films becomes consequently a serious issue that needs to be addressed. This is why metal gates may be mandatory for the end-of-the roadmap devices. The use of mid-gap gates allows Vth adjustment with lowly or undoped channels, and may be also useful for polydepletion and gate-resistance reduction. For SON application, the process of totally gates silicidation [16] can be easily applied: The process of the total gate silicidation is the following: (a) the structure is covered with metal capping and (b) RTP is performed for silicide formation down to the gate oxide (Figure 2.11.22 and Figure 2.11.23). SON architecture allows comfortable silicidation thanks to the metallurgical contact between S/D and the bulk. Figure 2.11.22 shows the implementation of the totally silicided gate process to SON devices, with reduced gate height in order to limit silicidation depth in the junctions. SON transistors were fabricated with this process and Figure 2.11.23 shows that the 800 A˚ height gates were totally transformed into CoSi2. Electrical performances are presented as illustration on 55 nm PMOS transistor with 5 nm of conduction-channel thickness on Figure 2.11.24, showing highly SCE-immune devices — only 60 mV

© 2006 by Taylor & Francis Group, LLC

2.11-201

Selective Etching Techniques for SiGe/Si

Gate CoSi2 S CoSi2

D CoSi2

SID implantation Si

FIGURE 2.11.22 Implementation of the total gate silicidation process to SON devices. SON architecture allows total gate silicidation process without creating voids in the Si-film. This is thank to the metallurgical contact between S/D and bulk.

CoSi2 Tox 2nm

Si 5nm

(a)

5 nm Si-channel

BOX 40 nm

(b)

FIGURE 2.11.23 (a) Example of SON transistor with metal gate integration. (b) Plasmon and (c) HRTEM pictures showing the thickness of the Si-channel. Measured TSi ¼ 5 nm, with perfect top and bottom interfaces.

1⫻10−3

0.0003

1⫻10−4 1⫻10−5 1⫻10−6

0.0002 0.00015

1⫻10−7 DIBL = 60m V

1⫻10−8 1⫻10−9

0.0001

0 −1.2 Vd = −0.1 −1.2 V

1⫻10−10

Ioff = 0.1nA

0.00005

−1.8

−0.4 Vg(V)

Idrain (A/µm)

Idrain (A/µm)

0.00025

1⫻10−11 1⫻10−12 0

FIGURE 2.11.24
Lin
Id(Vg) and Iog-Id(Vg) of a 55-nm SON transistor with CoSi2 gate. Data show high SCEresistive devices (DIBL ¼ 60 mV). Due to the Vth shift induced by the mid-gap gate, Ioff is around 0.1 nA/mm. The drive current is over 250 mA/mm at Vd ¼
1.2 V with Tox ¼ 20 A˚ and over 350 mA/mm at Vd ¼
1.4 V.

© 2006 by Taylor & Francis Group, LLC

2.11-202

The Silicon Heterostructure Handbook

of DIBL and a subthreshold slope of 73 mV/dec — in spite of deep S/D junctions. Such results are possible only on SON thanks to its intrinsic strength for SCE/DIBL suppression. Due to the Vth adjustment with mid-gap gate (Vth ¼
0.47 V at
0.1 V), Ioff was reduced to 0.1 nA/mm for 350 mA/ mm of drive current at
1.4 V.

SON without Channel Rupture: ‘‘Localized SOI’’ This process removes the necessity of breaking the continuity between S/D and channel and thereby also that of reunification of these two regions by SEG of silicon. The indispensable access to the SiGe is obtained at the STI edge by means of a slight de-oxidation, or by a slight Si-etching. Thanks to the very high selectivity and sensitivity of the SiGe etching process, this access is sufficient for underetching the entire active area (Figure 2.11.25). The remaining Si-cap layer is then supported by the gate stack that bridges the active area in the perpendicular direction, as in the basic SON process (Figure 2.11.17). In this process, the tunnel is fulfilled in the same time as the spacer stack is deposited (oxide and Si3N4 deposition). During the standard spacers etching step, the nitride layer is kept in the previous tunnel. This very simple process allows us localized SOI-like structures, as we can see in Figure 2.11.26 and Figure 2.11.27, leading to a new way of co-integration of such devices with bulk transistors on the same chip. On the illustration, SOI-like transistors have a silicon-conduction channel thickness of 10 nm isolated from the bulk by a 30 nm buried dielectric layer. It is worth noting that this process is totally compatible with the standard bulk CMOS process and offers new perspective for localized architecture on the chip.

Tunnel etching

Gate

STI

STI

Si-channel

Si

Buried dielectric

Gate

STI

Si-channel

STI Si

FIGURE 2.11.25 Concept of SON process without channel rupture: the buried SiGe layer is etched from STI edges and then the tunnel is fulfilled in the nitride spacers stack realization.

© 2006 by Taylor & Francis Group, LLC

2.11-203

Selective Etching Techniques for SiGe/Si

FPS− Sustained Si-areas

Empty-tunnel

FIGURE 2.11.26 Morphological demonstration of the feasibility of the SON tunnel etching via the STI edges. Active areas are sustained thanks to the gates.

<< Localized-SOI >>

gate

Tunnel filled with dielectric

FIGURE 2.11.27

gate

Si

We have formed localized SOI-like areas. TSi ¼ 10 nm and Tbox is around 30 nm.

Implementation of the SON Process to Gate All Around (GAA) MOSFETs The SON process may also be easily adapted to fabrication of double gate or gate-all-around (GAA) devices. These kind of devices are reputed for their particularly strong immunity to short-channel effects as well as for their augmented transport efficiency. The main problems remaining to be solved are related to: (i) the thickness control of the Si channel, (ii) its surface roughness, and in some realization (wafer bonding) to (iii) a misalignment between the gates. The GAA SON based process, shown in Figure 2.11.28, starts with a SEG of SiGe on STI isolated wafers. The SiGe/Si stack is next patterned by RIE into a strip expanding above the active area (future transistor channel) and overlapping on STI (future S/D). Then, the underlying SiGe is selectively etched out (Figure 2.11.29) as in the conventional SON process, and the entire bridge-like structure is recovered with dielectric (in our case thermal oxidation for ensuring gate-oxide quality). Next, the structure is recovered with poly-silicon that is patterned into a gate in a masked RIE step (Figure 2.11.30). The residuals of polysilicon remaining in the corners under the bridge are neutral for a static operation of the device but contribute to overlap capacitance, thus necessitating as tight design rules as possible to reduce the gate-topoly spacing. The structure is completed by ion-implantation of S/D junctions and extensions (optionally that of S/D after formation of spacers), silicidation and other conventional back-end steps. Note that this process presents at least three important advantages: (i) the SiGe is not subject to any thermal steps (it is etched away just after deposition and channel patterning) thus limiting the danger of relaxation, (ii) the continuity between the channel and the S/D is never broken thus removing all the troubles we had with the reunification of these regions by SEG of Si, and (iii) the S/D junctions lay on

© 2006 by Taylor & Francis Group, LLC

2.11-204

The Silicon Heterostructure Handbook

Si-conduction channel

Si-mono Si poly

Si poly SiGe Si-substrate

FIGURE 2.11.28 Epi stack: selective SiGe and nonselective Si. The channel of the GAA device is defined by photolithography and is followed by a strip patterning.

Si-conduction channel

Si-mono Si poly

Si poly

Si-substrate

FIGURE 2.11.29

Selective removal of the SiGe layer.

GATE SOURCE

DRAIN

n+

n+

Si-substrate

FIGURE 2.11.30

STI

Gate oxidation, poly-Si deposition, and gate patterning.

field oxide (STI), thus promising reduced junction capacitance and leakage. The point still to improve is that the gates are not of the same size even if they are still self-aligned, thus leading to somewhat increased overlap capacitance relevant to the bottom gate. Nonetheless, SON technological steps can be modified in order to combine the bottom gate etching and S/D epitaxy to realize self-aligned top and bottom gate, see Figure 2.11.31. Figure 2.11.32 demonstrates the feasibility of the GAA SON key steps as observed on our experimental samples. Worth noticing is that the nature of the silicon within the bridge-like structure changes from a monocrystal above the active area to polycrystal above the STI. This is not expected to be a problem as

© 2006 by Taylor & Francis Group, LLC

2.11-205

Selective Etching Techniques for SiGe/Si

S

Top gate

D

Silicide STI

FIGURE 2.11.31

Silicide Bottom gate

STI

GAA transistor with top and bottom self-aligned gates.

Silicon bridge

STI

FIGURE 2.11.32

Sustained silicon-conduction channel.

long as the effective channel region is taken in the central, monocrystalline part of the bridge. Note that the bridge-like silicon strip never communicates with the initial Si-substrate. Thanks to that, it can be doped with very high doses and comfortably annealed for efficient dopant activation, without the danger of junction diffusion as in the case of bulk devices. The last photographs (TEM) (Figure 2.11.33 and Figure 2.11.34) show a perpendicular cross-section in the central part of the bridge after reoxidation, polydeposition and gate patterning. The oxide film is pretty conformal all-around the Si strip, and the poly fills the tunnel homogeneously, without voids. Finally, the devices obtained by this process have shown exceptional performances (Figure 2.11.35), with drive current reaching 2000 mA/mm for 283 nA/mm Ioff.

Mono-Si conduction channel

Top Gate Amorphous Si Bottom Gate Gate oxide

FIGURE 2.11.33

In situ doped amorphous Si surrounding the Si-channel.

© 2006 by Taylor & Francis Group, LLC

2.11-206

The Silicon Heterostructure Handbook

Si-conduction film

Top gate

Bottom gate

FIGURE 2.11.34

Gate all around transistor after gate patterning. The measured Si-film thickness is 16 nm.

Lg = 70 nm, TOX = 2 nm, Tsi = 30 nm

Id (A/µm)

1⫻10−3 1⫻10−5

lon = 1954 µA/µm loff = 283.023 nA/µm @Vdd = 1.2 V

1⫻10−7

S = 77 mV DIBL = 70 mV

1⫻10−9 −0.5

0

0.5 Vg (V)

1

FIGURE 2.11.35 Example of Id(Vg) for a 70 nm gate length SON GAA transistor. The measured drive current is the highest ever measured on such devices.

Implementation to Multigate Devices The principle of the SON technology, which consists in a selective etching of SiGe layer, can be extended to the etching of multilayer. In this way, we can imagine structures where several empty tunnels can be performed and filled with gate oxide and poly-Si or metal gates (Figure 2.11.36 and Figure 2.11.37). This opens access to new devices with multiconduction channels, which can considerably boost the drive current for high-performance applications.

SON and Microelectromechanical Systems (MEMS) The fabrication of mono-silicon bridges can be easily adapted to electromechanical micro switch, if the flexure beam can be obtained by selective SiGe etching. This opens new possibilities for such applications, and in particular for the integration of front-end MEMS. Considering the state-of-the-art, the maximal vibration frequencies that can be obtained with flexure beam are in the range of 10 to 100 MHz. With the introduction of monocrystalline beams and very small gap between the detection electrode and the flexure beam, frequencies in the range of several GHz can be reached. The possibilities that are proposed with the SON technology in this domain are also of great interest (see Figure 2.11.38 and Figure 2.11.39).

© 2006 by Taylor & Francis Group, LLC

2.11-207

Selective Etching Techniques for SiGe/Si

FIGURE 2.11.36 Application of SON-GAA technology to multigate devices. The access to the buried SiGe multilayer is performed from the STI area.

Flexure beam

Anchor

Vdc

Vac

FIGURE 2.11.37 The empty tunnels are filled by polySi (or metal) to realize the multigate structure.

Actuation

FIGURE 2.11.38 Electromechanical micro-switch principle: the flexure beam is realized with the SON process, allowing a thin monocrystalline beam.

Mono-Si flexure beam

FIGURE 2.11.39 Example of morphological realization of a thin monocrystalline flexure beam with the SON technology.

2.11.4 Summary The selective Si/SiGe etching has been presented here and extensively detailed in chemical dry etching. This method can be used in several advanced microelectronics architectures that require a thin singlecrystal Si film isolated from the substrate by a cavity: the SiGe layer is used as a sacrificial layer for lateral etching. This approach is demonstrated as a new innovative technique, which is particularly suitable for the realization of localized SOI on bulk using the SON technology. Furthermore, the capability to perform sustained mono-Si areas over an empty cavity opens a wide range of applications for this

© 2006 by Taylor & Francis Group, LLC

2.11-208

The Silicon Heterostructure Handbook

technique, in particular for the realization of double gate devices, MEMs in nanoscale dimensions, new type of nanodetectors and sensors. In conclusion, the selective etching techniques for SiGe can be considered as a fundamental way for new and innovative approaches, demonstrating in this way a large potential for future applications.

Acknowledgments The author would like to thank P. Coronel; D. Chanemougame; D. Dutarte; A. Talbot; S. Harrison; F. Leverd for their contributions.

References 1. Wong, H.-S.P.; Frank, D.J.; Solomon, P.M. Device design considerations for double-gate, groundplane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation, IEDM Tech. Dig., pp. 407–410, 1998. 2. Schulz, T.; Rosner, W.; Risch, L.; Langmann, U. 50nm vertical sidewall transistors with high channel doping concentrations, IEDM Tech. Dig., pp. 61–64, 2000. 3. Ieong, M.; Jones, E.C.; Kanarsky, T.; Ren, Z.; Dokumaci, O.; Roy, R.A.; Shi, L.; Furukawa, T.; Taur, Y.; Miller, R.J.; Wong, H.-S.P. Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric Double-Gate/Ground plane CMOSFETs, IEDM Tech. Dig., pp. 441–444, 2001. 4. Chau, R.; Kavalieros, J.; Doyle, B.; Murthy, A.; Paulsen, N.; Lionberger, D.; Barlage, D.; Arghavani, R.; Roberds, B.; Doczy, M. A 50nm Depleted-Substrate CMOS transistor (DST), IEDM Tech. Dig., pp. 621–624, 2001. 5. Esseni, D.; Mastrapasqua, M.; Fiegna, C.; Celler, G.K.; Selmi, L.; Sangiorgi, E. An experimental study of low field electron mobility in double-gate, ultra-thin SOI MOSFETs, IEDM Tech. Dig., pp. 445–448, 2001. 6. Majima, H.; Saito, Y.; Hiramoto, T. Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs, IEDM Tech. Dig., pp. 733–736, 2001. 7. Balestra, F.; Benachir, M.; Brini, J.; Ghibaudo, G. Analytical models for subthreshold swing and threshold voltage for thin and ultra thin film SOI MOSFETs, IEEE Trans. Electron Devices, Vol. 37, no. 11, pp. 2303–2311, Nov. 1990. 8. Boeuf, F.; Skotnicki, T.; Monfray, S.; Julien, C.; Dutartre, D.; Martins, J.; Mazoyer, P.; Palla, R.; Tavel, B.; Ribot, P.; Sondergard, E.; Sanquer, A. 16 nm planar NMOSFET manufacturable within state-ofthe-art CMOS process thanks to specific design and optimization, IEDM Tech. Dig. Proc., pp. 637– 640, 2001. 9. Jurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Regolini, J.-L.; Morin, C.; Schiltz, A.; Martins, J.; Pantel, R.; Galvier, J. SON (Silicon On Nothing)—a new device architecture for the ULSI Era, Symp. VLSI Tech. Dig., pp. 29–30, 1999. 10. Monfray, S.; Skotnicki, T.; Morand, Y.; Descombes, S.; Talbot, A.; Dutartre, D.; Leverd, F.; Le Friec, Y.; Palla, R.; Pantel, R.; Haond, M.; Nier, M.-E.; Vizioz, C.; Louis, D. Highly-performant 38nm SON (Silicon-On-Nothing) P-MOSFETs with 9nm-thick channels, IEEE SOI Conference Proc., pp. 22–25, 2002. 11. Monfray, S.; Skotnicki, T.; Tavel, B.; Morand, Y.; Descombes, S.; Talbot, A.; Dutartre, D.; Jenny, C.; Mazoyer, P.; Palla, R.; Leverd, F.; Le Friec, Y.; Pantel, R.; Haond, M.; Charbuillet, C.; Vizioz, C.; Louis, D.; Buffet, N. SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) Polysilicon on 5nm-thick Si-films: the simplest way to integration of Metal Gates on thin FD channels, IEDM Tech. Dig. Proc., pp. 263–266, 2002. 12. Skotnicki, T.; Jurczak, M.; Gwoziecki, R.; Lenoble, D.; Ribot, P.; Paoli, M.; Martins, J.; Tormen, B.; Grouillet, A.; Pantel, R.; Galvier, J. Heavily doped and extremely shallow junctions on insulator—by SONCTION (SilicON Cut-off juncTION) process IEDM Tech. Dig., pp. 513–516, 1999.

© 2006 by Taylor & Francis Group, LLC

Selective Etching Techniques for SiGe/Si

2.11-209

13. Monfray, S.; Skotnicki, T.; Morand, Y.; Descombes, S.; Paoli, M.; Ribot, P.; Talbot, A.; Dutartre, D.; Leverd, F.; Lefriec, Y.; Pantel, R.; Haond, M.; Renaud, D.; Nier, M.-E.; Vizioz, C.; Louis, D. First 80nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance, IEDM Tech. Digest Proc., pp. 645–648, 2001. 14. Jurczak, M.; Skotnicki, T.; Paoli, M.; Tormen, B.; Martins, J.; Regolini, J.L.; Dutartre, D.; Ribot, P.; Lenoble, D.; Pantel, R.; Monfray, S. SON (Silicon On Nothing)—an Innovative Process for Advanced CMOS, IEEE Trans. Electron Dev. Vol. 47, Nov. 2000, p. 2179, 2000. 15. T. Skotnicki Silicon On Nothing (SON)—a robust technological platform for ULSI area, ECS Proc., 2001–2003, p. 391. 16. Tavel, B.; Skotnicki, T.; Pares, G.; Carriere, N.; Rivoire, M.; Leverd, F.; Julien, C.; Torres, J.; Pantel, R. Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (2Ohms/square) without metal CMP nor etching, IEDM Tech. Dig., pp. 825–828, 2001.

© 2006 by Taylor & Francis Group, LLC

3 Fabrication of SiGe HBT BiCMOS Technology 3.1

Overview: Fabrication of SiGe HBT BiCMOS Technology J.D. Cressler............ 3.1-213

3.2

Device Structures and BiCMOS Integration Issues D.L. Harame ...................... 3.2-215 Introduction . Types of HBT Structures . BiCMOS Integration Flows . Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes) . Advanced HBT Structures and Scaling Limits . Summary

3.3

SiGe HBTs on CMOS-Compatible SOI J. Cai and T.H. Ning .............................. 3.3-233 The SOI Advantage . Vertical Bipolar Transistors on Thin SOI . Voltage Pinning in a Fully Depleted Collector . Making SiGe HBTs on Thin SOI Substrate . Characteristics of SOI SiGe HBTs . Process Optimization, Device Scaling, and Complimentary Bipolar . Summary

3.4

Passive Components J.N. Burghartz ........................................................................ 3.4-249 Introduction . Resistors and Capacitors . Inductors and Transformers . Transmission Lines . Diodes and Switches . Special Passive Components . Summary

3.5

Industry Examples at State-of-the-Art: IBM A.J. Joseph and J.S. Dunn ............. 3.5-265 Introduction . BiCMOS Process Integration . The SiGe HBT — Key Technology Elements . Electrical Performance . Manufacturability . Summary

3.6

Industry Examples at State-of-the-Art: Jazz P.H.G. Kempf.................................. 3.6-283 Introduction . SiGe Bipolar Transistor . SiGe BiCMOS Process Integration . Process Customization . Summary

3.7

Industry Examples at State-of-the-Art: Hitachi K. Washio.................................. 3.7-295 Introduction . SiGe HBT Technologies . SiGe BiCMOS Technologies . Interconnection and Passive Elements . Summary

3.1-211 © 2006 by Taylor & Francis Group, LLC

3.1-212

The Silicon Heterostructure Handbook

3.8

Industry Examples at State-of-the-Art: Infineon T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck ...................................................... 3.8-307 Introduction . Process Concept . Transistor Fabrication Process . Transistor Results . Additional Devices . Circuit Performance

3.9

Industry Examples at State-of-the-Art: IHP D. Knoll ........................................ 3.9-321 Introduction . History of IHP’s SiGe and SiGe:C HBT Technologies . High-Performance SiGe:C BiCMOS Processes . High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology . Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) . Circuit Applications of IHP’s SiGe:C Technologies . Summary

3.10

Industry Examples at State-of-the-Art: ST A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy ............................................ 3.10-343 Introduction . Device Structures . Doping and Impurity Profiles . BiCMOS Integration Issues . High-Frequency Characteristics . Outlook for the Future

3.11

Industry Examples at State-of-the-Art: TI B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda........................................... 3.11-357 Introduction . Process Integration . Components and their Characteristics . Circuit Application . Summary

3.12

Industry Examples at State-of-the-Art: Philips R. Colclaser and P. Deixler....................................................................................... 3.12-371 Introduction . Historical Background . SiGe in Manufacturing — QUBiC4G . Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X . Summary

© 2006 by Taylor & Francis Group, LLC

3.1 Overview: Fabrication of SiGe HBT BiCMOS Technology

John D. Cressler Georgia Institute of Technology

SiGe HBT BiCMOS technology is the obvious groundbreaker of the Si heterostructures application space and numerous commercial products exist around the world. At present count there are 25 þ SiGe HBT industrial fabrication facilities on line in 2005, and growing steadily. In fact, virtually every major player in the communications electronics market either (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers. Clearly this field is maturing rapidly. Key to this success lies in the successful integration of the SiGe HBT and Si CMOS, with no loss of performance from either device. Chapter 3.2, ‘‘Device Structures and BiCMOS Integration Issues,’’ by D. Harame of IBM Microelectronics, discusses the various nuances of integration of HBTs with CMOS in SiGe fabrication. A recent demonstration of integrating a vertical SiGe HBT on thin film, CMOScompatible SOI substrates has generated considerable interest and is addressed in Chapter 3.3, ‘‘Fabricating SiGe HBTs on CMOS-Compatible SOI,’’ by J. Cai of IBM Research. For mixed-signal circuit applications of SiGe technology, the performance of integrated passive components is often just as important for circuit designers as the transistors, and significant strides have been made in the improvement of passives (and the requisite compact models for them) in recent years, and is reviewed in Chapter 3.4, ‘‘Passive Components,’’ by J.N. Burghartz of Delft University. A novel aspect of this handbook is that it contains numerous ‘‘snapshot’’ views of the industrial ‘‘state-of-the-art’’ for SiGe HBT BiCMOS technology, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global industry. These technology snapshots feature all the leaders of SiGe HBT BiCMOS field, including: Chapter 3.5, ‘‘Industry Examples at State-of-the-Art: IBM,’’ by A. Joseph of IBM; Chapter 3.6, ‘‘Industry Examples at State-of-the-Art: Jazz,’’ by P. Kempf of Jazz Semiconductor; Chapter 3.7, ‘‘Industry Examples at State-of-the-Art: Hitachi,’’ by K. Washio of Hitachi; Chapter 3.8, ‘‘Industry Examples at State-of-the-Art: Infineon,’’ by T. Meister of Infineon; Chapter 3.9, ‘‘Industry Examples at State-of-the-Art: IHP,’’ by D. Knoll of IHP; Chapter 3.10, ‘‘Industry Examples at State-of-the-Art: ST Microelectronics,’’ by A. Chantre of ST Microelectronics; Chapter 3.11, ‘‘Industry Examples at State-of-the-Art: Texas Instruments,’’ by B. El-Kareh of Texas Instruments; and Chapter 3.12, ‘‘Industry Examples at State-of-the-Art: Philips,’’ by R. Colclaser of Philips. In addition to this copious material, and the numerous references contained in each chapter, a number of review articles and books detailing SiGe HBT BiCMOS technology exist, including Refs. [1–11]. 3.1-213 © 2006 by Taylor & Francis Group, LLC

3.1-214

The Silicon Heterostructure Handbook

References 1. JD Cressler, DL Harame, JH Comfort, JMC Stork, BS Meyerson, and TE Tice. Silicon–germanium heterojunction bipolar technology: the next leap in silicon? Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 1994, pp. 24–27. 2. JD Cressler. Re-engineering silicon: Si–Ge heterojunction bipolar technology. IEEE Spectrum 49–55, 1995. 3. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Transactions on Electron Devices 40:455–468, 1995. 4. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Transactions on Electron Devices 40:469–482, 1995. 5. DL Harame. High-performance BiCMOS process integration: trends, issues, and future directions. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1997, pp. 36–43. 6. HJ Osten, D Knoll, B Heinemann, H Rucker, and B Tillack. Carbon-doped SiGe heterojunction bipolar transistors for high-frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 109–116. 7. BS Meyerson. Silicon:germanium-based mixed-signal technology for optimization of wired and wireless telecommunications. IBM Journal of Research and Development 44:391–407, 2000. 8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. R Singh, DL Harame, and MM Oprysko. Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

© 2006 by Taylor & Francis Group, LLC

3.2 Device Structures and BiCMOS Integration 3.2.1 3.2.2

Introduction............................................................... 3.2-215 Types of HBT Structures .......................................... 3.2-215 Bipolar Structure Process Feature Tradeoffs . Bipolar Structure Examples

3.2.3 3.2.4 3.2.5

BiCMOS Integration Flows ...................................... 3.2-223 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes)...................... 3.2-225 Advanced HBT Structures and Scaling Limits ....... 3.2-225

3.2.6

Summary .................................................................... 3.2-229

David L. Harame IBM Microelectronics

THz Performance Possibilities

3.2.1 Introduction SiGe heterojunction bipolar transistors now have performance that rivals the III–Vs and in many cases is superior to them. This technology has grown to be a pervasive technology found in many products, not solely because of the performance, but primarily because it is realized as a BiCMOS technology such that very highly integrated product designs are possible by leveraging a base CMOS technology, which already has existing libraries and intellectual property (IP). Additionally, passives and extensive RF– analog enablement are also added to make custom designs possible that can be merged with the highly integrated digital CMOS section. This combination of the performance of the HBT with all the large digital integration capability is based on having the HBT structure and process fully integrated into the base CMOS process such that it guarantees the compatibility of the HBT and CMOS. This will be the central theme of this section on device structures and BiCMOS integration. The structures will always be seen as within the context of a BiCMOS process. This chapter will begin with a review of the structures that are used in SiGe heterojunction bipolar transistors broadly breaking them up into different types. This will include an extensive section on transistor features, which will emphasize that what the final device looks like is a combination of the bipolar structure and the intended applications. It will then review BiCMOS integration flows followed by a section on the issues in integrating SiGe HBTs into advanced CMOS processes. The chapter will conclude by looking at the performance limits and what very advanced HBT structures might look like.

3.2.2 Types of HBT Structures Bipolar transistor structures can be roughly divided into non-self-aligned and self-aligned structures. A self-aligned transistor structure implies that the extrinsic base region is self-aligned to the emitter opening during the bipolar structure’s fabrication process. Note that this is a fairly limited definition, albeit an important one, considering all of the parts of the final transistor structure. Self-alignment is accomplished by the formation of an outer or inner sidewall, which enables us to make a second broad 3.2-215 © 2006 by Taylor & Francis Group, LLC

3.2-216

The Silicon Heterostructure Handbook

division of structures. Non-self-aligned structures imply that a lithographic alignment tolerance is used for the alignment as opposed to a processing feature during the formation of the structure. Another broad classification seeks to break structures into a combined performance and cost division. This division classes structures into high performance (HP) versus cost performance (CP). The concept is that for the HP set of applications, performance is everything and time to market is critical, making the cost considerations secondary. In contrast, the CP set of applications are commodity cost-sensitive applications where cost is everything and the required peak performance levels are significantly reduced. The CP applications will typically use older lithography generations. Of course, the HP and CP division is much more ambiguously defined when it comes to particular processes, since the features in a process flow are determined by the intended application that may be a mix of requirements. Nevertheless, it is interesting to understand the features and their tradeoffs while arbitrarily assigning them a HP or a CP classification. After the features are discussed, in light of either a HP or CP element, several example NSA and SA processes will be discussed in detail.

Bipolar Structure Process Feature Tradeoffs Some examples of the more typical features and tradeoffs are listed in Table 3.2.1 and several of these examples will be discussed in some detail here, with others addressed throughout this chapter. Issues and limitations of the different features will be discussed in this section. Selection of the starting wafer is a tradeoff. Substrate resistivity has a large impact on microstrip lines and inductors as described in detail by Long and Copeland [1]. Silicon transitions through skin effect, to slow wave, to quasi-TEM propagation modes as the resistivity is changed from low (
0.01 ohm-cm) to high (
50 ohm-cm) resistivity material as shown in Figure 3.2.1. Inductors fabricated on higher resistivity material have higher inductor Q values because of less power dissipation in the substrate [1]. However, high-resistivity wafers may be more susceptible to processing issues (warping during high-thermal steps) and the CMOS may

TABLE 3.2.1 Structural Processing Features of SiGe Heterojunction Bipolar Transistors Process Feature

High Performance

Cost Performance

Wafer Subcollector

High resistivity Nþ subcollector implant followed by n-epitaxy growth. Lowest sheet resistance Deep trench. Best isolation

Same as base CMOS Implanted subcollector without n-epitaxy. Lower cost but higher sheet resistance Junction isolation. Larger transistor layout, less isolation Same as CMOS No additional layers added to the process. Must address all etch steps to not damage the NPN region Nonselective. Structure dependent. Simpler

Transistor isolation Shallow trench NPN protection layer

Epitaxy

Extrinsic base

Same as CMOS Additional layer designed to protect the NPN region during CMOS processing and prior to epi-base. Increases process margin Selective. Structure dependent. Requires close attention to process to maintain high selectivity. Susceptible to nonuniform growth in different areas and density regions Raised extrinsic base. Less like a CMOS transistor. Requires more special steps. Higher performance

Polyemitter

In situ doped. More complex. Fewer small emitter structure issues

Contacts

Separate emitter contact. Structure dependent to make it less susceptible to height differences.

Features are categorized as a high-performance or cost-performance feature.

© 2006 by Taylor & Francis Group, LLC

Implanted extrinsic base. Can be SA or NSA processes. Simplest approach but results in a deeper extrinsic base Implanted emitter. Simpler. May be susceptible to small emitter nonuniform dopant distribution issues CMOS contact. Simpler. With topography differences with CMOS less process margin

3.2-217

Device Structures and BiCMOS Integration

Metal SiO2

1011 SKIN EFFECT

Si

QUASI-TEM

1010

Frequency, in Hz

Electric field distribution

Ground plane Quasi-TEM mode

Digital CMOS

tsi = 350 µm tox = 5 µm

Si bipolar and RF CMOS

tsi = 350 µm tOX = 2 µm

109

tsi = 200 µm tOX = 5 µm 108

Slow-wave

Slow-wave mode 107 10−2

Skin-effect mode

10−1

100

101

102

Silicon resistivity, in Ω-cm

103

Frequency-resistivity mode chart for parallel plate waveguide

FIGURE 3.2.1 Propagation modes in silicon as a function of silicon resistivity and frequency. (J.R. Long, personal communication.)

have significant deltas from the base CMOS latch-up and ESD specifications. A more conservative flow is to select the starting wafer resistivity to be compatible with the base CMOS process or just slightly higher with a typical number around 10 ohm-cm. The formation of the subcollector involves another tradeoff. For the lowest subcollector resistance, a low resistivity buried subcollector is desirable. In this process a high-dose arsenic implant is followed by a long thermal cycle in an oxidizing ambient to drive the arsenic diffusion deep into the wafer and anneal out defects, which is then followed by a thin n-epitaxy layer grown at high temperatures. A buried subcollector process can achieve sheet resistances below 10 ohm/sq. The alternative process is to simply implant the subcollector more like a well implant in CMOS. This has the advantage that it is simpler and allows the starting wafer to be fully compatible with the CMOS process as opposed to adding the n-epitaxy layer to the CMOS regions. The disadvantage is that to avoid defects, the dose and depth of the subcollector implant is significantly less than that of a buried subcollector so that the sheet resistance may be as much as ten times higher than that for a buried subcollector. Reducing sheet resistance and defect density remains a concern for CP sub-collector processes. Transistor isolation is another process feature that is a tradeoff. The best isolation is created by a deep trench (
6.0 mm), which is filled with a thick oxide liner and undoped polysilicon. The transistor-totransistor breakdown voltage may easily exceed 50 V. A simpler process is to use junction isolation taking advantage of other implants in the process. The interesting aspect is that it uses no additional steps but the drawback is much reduced isolation voltages and significantly larger transistor-to-transistor spacing is required. In designs with reduced bipolar transistor count density may not be an important issue and the junction isolation may easily provide adequate isolation. The combination of a deep trench and a buried sub-collector leads to reduced collector capacitance (CSC) and collector resistance (RC) parasitics and therefore the highest fT and fMAX values. The next feature is the NPN protection layer which is a layer used in the Base-after-Gate (BaG) integration flow [2] to protect the NPN regions from CMOS processing damage (Figure 3.2.2). This flow will be discussed in a later section of this article but for the moment all that is needed to know is that after the gate polysilicon is etched away from the active NPN area, the SiGe base is grown over that region of silicon. In modern CMOS processes, the gate oxide continues to shrink and is now on the order of 2.0 nm in 90 nm CMOS. The polysilicon gate etch must stop on that thin layer, but with thin gate oxides the silicon is often damaged. In a CMOS process this region will become heavily doped and

© 2006 by Taylor & Francis Group, LLC

3.2-218

The Silicon Heterostructure Handbook

Bipolar before CMOS (base before gate)

Bipolar after CMOS (base after gate)

Isolation

Isolation

Bipolar

CMOS

CMOS

Bipolar

Contacts and interconnects

Contacts and interconnects

Bipolar during CMOS (base during gate) Isolation

Bipolar and CMOS

Contacts and interconnects

FIGURE 3.2.2 Three simple BiCMOS process flows.

silicides formed so that the condition of the silicon surface is not such an issue. However, in a HBT process in which the intrinsic base is grown over that region, any damage in the underlying silicon will result in defects during epi growth and subsequent poor SiGe HBT yield. This damage can be prevented by adding a dielectric layer to protect the region during the gate etch. The use of this layer is based on a decision to select a larger process margin for a noncritical additional processing step, but it will add additional steps to the process. The next process feature is the SiGe epitaxy process used to grow the base layer. The three most commonly used techniques available to grow the SiGe base layer are MBE, UHV/CVD [3, 4], and APCVD or RPCVD [5, 6]. MBE [7] was used initially but is no longer used in production so we will not focus on it here. The fundamental problem in SiGe epitaxy is the removal of the native oxide layer and each of these three techniques addresses this in different ways. In UHV/CVD epitaxy prior to epitaxial deposition, the wafer is exposed to a HF treatment which removes all of the native oxide and forms a hydrogen-passivated layer that is maintained throughout the epitaxial growth. In APVCVD or RPCVD, the wafer is baked at a high temperature in the presence of a hydrogen flow, which desorbs the oxide layer. Selective deposition is possible with both AP or RPCVD [6] and UHVCVD but UHVCVD is usually used as a nonselective process. A concern with AP or RPCVD selective growth is the sensitivity to local pattern (area) densities, which can affect the growth rate by as much as 50% depending on the conditions [8]. All CVD techniques are capable of in situ doping using phosphorus for n-dopants and boron for p-dopants (boron) and incorporating Ge and carbon [9]. A detailed comparison between UHV/CVD and AP or RPCVD may be found in Ref. [10]. Another interesting feature is that of raised extrinsic base versus a simpler nonraised extrinsic base. A raised extrinsic base is a processing feature that requires a separate deposition of heavily doped material either before or after the intrinsic base layer is formed. The idea was advanced early in the development of epitaxial base development [11–13], and one might also argue that it is a part of the selective epitaxial base structure, which we will go over in detail. The advantages are lower base–collector capacitance and base resistance but at a cost of more complexity than a simple planar ion-implanted extrinsic base structure. This completes the review of features and tradeoffs commonly used in bipolar structures. In the next section we will explore three bipolar structures illustrating the use of these features.

Bipolar Structure Examples This section will focus on three structural examples, which will describe the three basic classes of structures: (1) non-self-aligned epitaxial base transistor, (2) self-aligned epitaxial base transistor with an inner sidewall, and (3) self-aligned using an outside sidewall. We will then look at the impact of advanced CMOS structures and the impact on BiCMOS integration and conclude with a section on advanced bipolar structures within the context of the new CMOS processes.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-219

Non-Self-Aligned Bipolar Transistor Structure This structure is the simplest epitaxial base bipolar structure and usually simpler processes are most widely used. It is often referred to as a quasi-self-aligned transistor structure and is essentially the same structure that has been used widely in implanted base BiCMOS integration processes [14]. An SEM of the structure to be built through a series of cross sections is shown in Figure 3.2.3. The process begins with the formation of the buried layer into a CMOS compatible P substrate by patterning an arsenic implant (Figure 3.2.4(a)). The buried layer implant is followed by a high-temperature anneal in an oxidizing implant to drive the implant deep into the silicon and consume the damaged silicon layer. This is followed by the growth of a very lightly doped n-epitaxial layer, which is traditionally grown at high temperature (Figure 3.2.4(b)). The base CMOS process now begins with the formation of shallow trench by depositing a nitride layer, patterning and etching the nitride and silicon (Figure 3.2.4(c)), followed by a deposition of oxide and planarization (Figure 3.2.4(d)) and subsequent nitride strip. The shallow trench is followed by the ‘‘reach-thru’’ implant, which is a high-dose implant to form a low-resistance-doped region contacting the buried layer from the surface (Figure 3.2.4(e)). Typically this is a high-dose phosphorus implant, which is able to diffuse down to the buried arsenic layer under a moderate heat cycle. This example process has a BaG integration and benefits from the formation of a protect layer. The protect dielectric layer is deposited, patterned, and etched everywhere but over the regions where high-quality single intrinsic base growth is required (Figure 3.2.4(f)). After the CMOS structural process is completed a patterning and etch step remove the bipolar protect layer from the active base region and this same step may serve as an implant block mask for a collector implant to save a masking level (Figure 3.2.4(g)). In the next step the nonselective intrinsic in situ doped SiGe(C) layer is grown (Figure 3.2.4(h)). Single crystal material is grown in the region of exposed silicon and polysilicon over any regions where dielectrics are exposed. The polysilicon growth outside the active region serves as a landing pad for the metal contacts as can be seen in the SEM micrograph in Figure 3.2.3. A high-quality emitter base dielectric is formed by oxidation, which is followed by the deposition of thicker dielectrics. The emitter opening is formed by a patterning and etch step (Figure 3.2.4(i)). The alignment is to the shallow trench level. Next, the emitter polysilicon is deposited, doped, capped with a dielectric layer, patterned and etched (Figure 3.2.4(j)). The alignment of the level is also to the shallow trench level, which makes the alignment second order with respect to the emitter opening. The three sigma total overlay we must allow for is given by OLTotal ¼ WC þ

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi TOL2NP þ TOL2EM þ TOL2NP-ST þ TOL2EM-ST

(3:2:1)

where WC is the worst case overlay of NP-EM allowed by the process, OL are overlays and TOL are tolerances of the process. The extrinsic base is then implanted using the emitter polylayer as a mask for

FIGURE 3.2.3

SEM micrograph of a non-self-aligned SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

3.2-220

(a) Implant subcollector

The Silicon Heterostructure Handbook

(h) After LTE EPI and base dielectric deposition Oxide

(b) Grow n- collector epitaxial layer (i) Define emitter

(c) Define and etch shallow trench

(j) Etch NPN emitter poly and emitter films

(d) After trench planarization and pad nitride strip

(e) Implant NPN reachthrough

(k) Implant extrinsic base

(f) Pattern and etch NPN protect film

(l) Etch NPN base poly

(g) Etch base opening; implant deep pedestal

(m) After TiSix Formation

FIGURE 3.2.4 Fabrication sequence of a simple NSA epitaxial base transistor broken in 13 steps.

© 2006 by Taylor & Francis Group, LLC

3.2-221

Device Structures and BiCMOS Integration

the extrinsic base implant (Figure 3.2.4(k)). The extrinsic base layer is then patterned and etched (Figure 3.2.4(l)). A dielectric deposition and etch forms a sidewall on both the emitter polysilicon and the base polysilicon layer. CMOS implants, an RTA anneal, and Ti silicide formation complete the front end of the line process. Self-Aligned Bipolar Transistor Structure with an Inner Sidewall One of the most common implanted structures used in bipolar technology is the double polysilicon self-aligned (DPSA) implanted transistor structure [15] shown in Figure 3.2.5. This transistor structure has been successfully integrated into many production BiCMOS integration flows. The major drawback of the DPSA structure was the difficulty in maintaining a narrow base with an implanted base process. A suggested process improvement was to incorporate an epitaxial base in place of the implanted base process. The most straightforward way to do this was to substitute an epitaxial growth for the intrinsic base implant just prior to formation of the inner sidewall. A two-step sequence using the same basic structure as the double polysilicon structure is shown in Figure 3.2.6(a) and (b) [16]. This approach was successful in achieving a narrower heavily doped base than an implanted base process, but required higher thermal cycles for the preclean and growth with diffused base limiting the scalabilty of the method. With time, this general approach was significantly improved by adding a pad oxide under the extrinsic base and incorporating a selective SiGe base. The process steps are

Inner sidewalls

P+ polysilicon P+ I/I Intrinsic base

FIGURE 3.2.5

Double polysilicon self-aligned transistor structure.

Selectively grown epitaxial base Dielectric P+ polysilicon P+ ST (a) DPSA after epi base Inner sidewalls

Selectively grown epitaxial base

Dielectric P+ Polysilicon P+ ST Deposited + diffused intrinsic base (b) DPSA after sidewall

FIGURE 3.2.6

Double polysilicon with epitaxial base.

© 2006 by Taylor & Francis Group, LLC

3.2-222

The Silicon Heterostructure Handbook

Dielectric

Pad dielectric

P+ polysilicon Dielectric

ST (a) DPSA with Pad oxide Inner sidewalls

Pad dielectric after HF dip

Dielectric P+ polysilicon Dielectric

ST (b) After SW and HF dip Selective SiGe epitaxial base Dielectric

Voids

P+ polysilicon

ST (c) After selective SiGe epitaxial growth

FIGURE 3.2.7 DPSA with pad oxide and selective SiGe epitaxial base deposition.

shown in Figure 3.2.7(a)–(c). Note that the pad oxide lies under the extrinsic base doped polysilicon, preventing the diffusion of the extrinsic base during the epitaxial base prebake and it restricts the area so that the base–collector capacitance is significantly reduced. A disadvantage of this structure is that the HF dip contributes some variability to the underlap under the Pþ polysilicon — therefore variability in the base resistance, and the structure has significant topography so its narrow emitter effects are a concern. The selective SiGe epitaxial growth is subject to area and local pattern densityloading effects, which can significantly change local growth rate (as much as 50% depending on the conditions) and the wafer emissivity (important for lamp-heated selective SiGe reactors) is dependent on the mask pattern. In spite of these difficulties, the structure does optimize fMAX effectively by greatly decreasing CBC. Self-Aligned Bipolar Transistor Structure with an Outer Sidewall An alternative family of structures to those with an inner sidewall, are those which form the extrinsic base by the use of an outer sidewall on a sacrificial structure (referred to as a pedestal). An advantage of these structures is that the growth and deposition are nonselective and the structures have low topography, the two properties which help with manufacturing control. A process for such a bipolar structure is shown in Figure 3.2.8(a)–(g) [17, 18]. A key aspect of the process is the formation of a pedestal of sacrificial material on which sidewalls are formed to self align the extrinsic base to the emitter opening. The process begins after the nonselective in situ doped SiGe(C) base is grown. A series of films are deposited (Figure 3.2.8(a)) and the top two layers are patterned and etched to form a ‘‘sacrificial pedestal’’ (Figure 3.2.8(b)). A dielectric sidewall is formed on the ‘‘sacrificial pedestal’’ (Figure 3.2.8(c)) and the extrinsic base is implanted (Figure 3.2.8(d)) through the remaining films except where the ‘‘pedestal’’ and sidewall block the implant. The dielectrics are removed leaving

© 2006 by Taylor & Francis Group, LLC

3.2-223

Device Structures and BiCMOS Integration

only the patterned pad nitride and the polysilicon layer exposed on the surface of the wafer. Next, the polysilicon is oxidized everywhere except under the pad nitride. The oxidation of polysilicon is pinned near the LOCOS (Figure 3.2.8(e)) nitride edge due to large compressive stress during field oxidation. The mechanism is the same as that in the well-understood poly-buffered-LOCOS (PBL) approach to forming a field oxide [19]. Next, the PBL nitride pad and underlying polysilicon are stripped and the remaining dielectric etched (Figure 3.2.8(f)) followed by the deposition, doping, patterning, and etching of the emitter polysilicon (Figure 3.2.8(g)). This completes the bipolar process-specific portion of the fabrication sequence, silicidation of the extrinsic base polysilicon and collector contact and contacts using the CMOS portions of the process. An SEM of a 0.18 mm SiGe HBT fabricated with this process is shown in Figure 3.2.9 [20].

3.2.3 BiCMOS Integration Flows The previous section gave a detailed process description of three different bipolar structures. Each of these structures can be fabricated together with CMOS in a BiCMOS process. The objective of BiCMOS process integration is to create a final process with CMOS characteristics unchanged from the original CMOS only process and bipolar performance matching the bipolar only process. BiCMOS process integration flows separate out into three cases, which are shown in Figure 3.2.2. The first process flow is that of base-beforegate (BbG). In this case, the bipolar is structurally formed completely before the CMOS and then covered up or protected during the CMOS processing. The disadvantage of this flow is that the thermal cycles of CMOS are much higher than the bipolar and therefore would tend to diffuse and widen the intrinsic base profile. The second technique is Base after Gate (BaG) [2]. In this approach the CMOS is completely

Dielectric

Polysilicon

Nitride

Dielectric

Nonselective SiGe epitaxial base

ST

(a) Nonselective SiGe epitaxial base and layer depositions Polysilicon

Dielectric Nitride

Patterned and etched sacrificial-emitter-pedestal

Nonselective SiGe base

ST (b) Pattern and etch a sacrificial-emitter-pedestal using the top two layers Outer sidewalls

Nonselective SiGe base

ST (c) Deposit dielectric and etch back to form an outer sidewall on the sacrificial-emitter-pedestal

FIGURE 3.2.8 Self-aligned SiGe epitaxial base bipolar structure using an outer sidewall to self-align the extrinsic base. (Continued)

© 2006 by Taylor & Francis Group, LLC

3.2-224

The Silicon Heterostructure Handbook

Extrinsic base implant

Nonselective SiGe base

P+

P+ ST

(d) Extrinsic implant using boron which is self aligned to the emitter opening by the outer sidewall Oxide Nonselective SiGe base

P+

P+ ST

(e) Oxidation of the sacrificial polysilicon layer exposed in the field area but not underneath the nitride using the LOCOS effect, i.e., the polysilicon underneath the pad nitride is not oxidized Emitter Opening Nonselective SiGe base

P+

P+ ST

(f) Uncover emitter opening by selective removal of the nitride, polysilicon, and finally bottom dielectric layer. Note P+ implant is self-aligned to the emitter opening Emitter Polysilicon N+ Nonselective SiGe base

P+

P+ ST

(g) Emitter-polysilicon deposition, doping, and patterning. Note that with lower topography there is reduced narrow emitter effects.

FIGURE 3.2.8 (Continued )

Collector

Base

Emitter SiGe Base

N+ subcollector

FIGURE 3.2.9 SEM micrograph of a 0.18 mm SiGe BiCMOS HBT.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-225

formed and then covered up for protection during the bipolar processing and therefore the higher thermal cycles of the CMOS are completed prior to the deposition of the intrinsic base and the formation of the bipolar structure. This is the dominant integration technique in modern BiCMOS technologies. The last integration flow is base during gate. In this approach the bipolar and CMOS layers and thermal cycles are shared [17, 18]. This approach was practiced in the 0.5 mm lithographic generation [21] but as CMOS became more complex there was a need to decouple the thermal cycles.

3.2.4 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes) There are many challenges in integrating a SiGe HBT into an advanced CMOS process and this section will discuss some of these after first reviewing some key aspects about advanced CMOS processes. To improve the performance of CMOS generation to generation a selective scaling methodology is used. In selective scaling, the gate length is aggressively scaled with reduced scaling of the oxide thickness and power supply voltage [22]. However, in 65 nm and beyond even selective scaling is challenged as standby power and dynamic power become equivalent and FET performance is not dramatically increasing. The new approach requires a combination of material and structural innovation as well as a scaling algorithm. These innovations have led to the introduction of strain to increase electron and hole mobilities [23–25] and novel structures like FINFETS [26]. Both strain and structural innovations (e.g. FINFETS) have been implemented on SOI and in bulk silicon. The incorporation of one or more of these approaches in a BiCMOS process will complicate integration of the SiGe HBT and modify the SiGe HBT device performance. Two commonly used approaches to introduce strain to improve FET mobility are SiGe buffer layers and post-FET structure film depositions. Buffer layers will have a drastic effect on process integration with CMOS [27], especially if the bipolar is fabricated in these strained Si and relaxed Si1x Gex layers. Given the high defect densities that currently exist in these films, there will be a major impact on transistor yield. There are limited available publications on this interesting question so it is bound to be a major research topic in the future. Less drastic process alternatives to introduce strain is through the use of a tensile nitride deposition after the completion of the front-end processing and just prior to interconnect formation [25]. Liu has published the effects of compressive and tensile strain (
0.28%) on SiGe HBT and Si BJT controls. Compressive strain showed an increase in IC and current gain (þ4%) while tensile strain showed a decrease (4% to 6%) in IC and current gain [28] although this has not been studied in depth. The effects were indeed found to be minor for DC characteristics. Additionally, FinFETs and double-gate structures introduce a novel way to fabricate CMOS devices, which may well be used in future CMOS technologies. In a BaG BiCMOS integration flow FINFET processes will probably not have an impact on the Bipolar formation as far as thermal cycles are concerned, but may introduce integration difficulties due to the extreme topography of these structures. SOI technology has also emerged as an important technology for high-speed processing and it is interesting to see the possibilities of integrating HBTs with SOI. Most approaches to integrate bipolar with the SOI have centered on creating lateral [29, 30] or novel vertical bipolar structures to take advantage of the SOI technology features or more conservative approaches, which utilized thicker silicon on SOI than is available in conventional logic SOI technologies [31]. Cai successfully integrated a SiGe HBT on SOI [32] and achieved an fT and fMAX of 70 GHz at a 20 V substrate bias. At 0 substrate bias the fT and fMAX was 30 and 45 GHz, respectively. Integration of HBTs with SOI is promising but much work remains to be done.

3.2.5 Advanced HBT Structures and Scaling Limits Scaling in bipolar technologies involves a combination of vertical and lateral scaling. In vertical scaling the total transit time is reduced by reducing each of the component transit times. The expression for the

© 2006 by Taylor & Francis Group, LLC

3.2-226

The Silicon Heterostructure Handbook

total transit time is given in Equation (3.2.2) to Equation (3.2.4). In the case of graded SiGe base HBTs, the base is scaled by shrinking the base width WB and increasing the slope of the Ge across the base, which often includes increasing the peak Ge% [33]. If all doped regions are thinned the transit times may decrease but the RC time constants will increase due to increased resistances. Therefore, innovation is required with vertical scaling to simultaneously reduce the thicknesses in the structure, area of the capacitances, and resistances

tEC

1 ¼ tEC ¼ tC þ tB þ t CSCL 2pfT    2  kT kT WB WB WCSCL þ ¼ CEB þ þ RC þ RE CCB þ g þ qIC qIC Dn VEXIT 2nSAT   kT kt DE g¼ 1 [1  e g;GeðgradeÞ=kT ] DEg;GeðgradeÞ DEg;GeðgradeÞ

(3:2:2) (3:2:3) (3:2:4)

In the case of the in situ doped SiGe base the introduction of carbon and the retarding effects on boron diffusion from high-concentration Ge have enabled the sheet resistance of the intrinsic base layer to decrease generation to generation. Fortunately, the epitaxial technology is very advanced today and it is routine to deposit and control very thin SiGe(C) layers. To achieve a higher fT value it is apparent from Equation (3.2.3) that the charging current (IC) must be increased, which means that the Kirk effect must be pushed out to higher current densities. This is accomplished by increasing the collector dopant concentration, usually by an increase in the siliconimplanted collector or SIC, which increases IC and decreases both RC and WCSCL. However, increasing the SIC implant causes more lateral and vertical diffusion, which increases the base–collector capacitance (CCB). The base–collector capacitance is an important term in advanced structures and it indicates an interaction of lateral and vertical scaling that must be carefully controlled to improve the fMAX as well as fT. A schematic cross section of an idealized bipolar shown in Figure 3.2.10 illustrates some of the key parasitics that may be reduced by lateral scaling. To first order, lateral scaling is shrinking all the dimensions and overlaps, which will significantly improve the capacitances and resistances by minimizing

RBSP

RBSU

R BSX RBSSL

Emitter polysilicon C BENP CBEP

CCBOL

CBEA CCBI

Pedestal (SIC)

Base polysilicon Shallow trench

CCBX CCBPB

Subcollector

FIGURE 3.2.10

Cross section through an idealized bipolar transistor showing the key later parasitics.

© 2006 by Taylor & Francis Group, LLC

3.2-227

Device Structures and BiCMOS Integration

the area and distances that current must flow through resistive layers. There are cases in which the shrinking dimensions may cause increased parasitics. For instance, decreasing the trench width increases the perimeter collector to substrate capacitance. Therefore, this dimension is not scaled generation to generation. In another case, decreasing the distance between the SIC implant and the extrinsic base implant will increase the overlap and increase the overlap capacitance CCBOL (see Figure 3.2.10). This component can be a large part of the delay so it must be decreased. The only way to do this is by structural innovation that has resulted in raised extrinsic base structures in which the implant into the silicon is removed to greatly decease the diffusion into the SIC layer (Figure 3.2.11) [33].

THz Performance Possibilities Having reviewed vertical and lateral scaling let us consider what type of future structures would be required to achieve an fT of 1 THz (total transit time < 160 fsec or <40 fsec for tE, tB, tC, tCSCL, respectively). An important assumption is that parasitics, which can be addressed by geometrical scaling, will not be dominant delay components because they can be reduced with clever structural innovations and lithography shrinks. Solutions to THz performance will be found by using the scaling methodology discussed above and methodically addressing each delay component. The emitter delay (tE) component given by Equation (3.2.5) can be addressed by aggressively scaling the emitter area, i.e., emitter width, and therefore CBE. This component will not be a dominant delay component since the emitter width can be relatively easily scaled [34, 35]. Concerns exist about the high current densities but by scaling the shrinkage of the emitter width to 1/(peak fT current density) many of these concerns are mitigated [36]. The base delay (tB) component can be addressed by continuing to shrink the vertical profile using a

Overlap N+ Poly

W Stud contact

Silicide SiGe

N+

DT

STI

SIC

STI

DT

N+ Subcollector P substrate

WE Shallow junction

Raised extrinsic base

STI N+

SIC

N+ Subcollector DT P substrate

FIGURE 3.2.11 Selective scaling in bipolar transistors.

© 2006 by Taylor & Francis Group, LLC

DT

3.2-228

The Silicon Heterostructure Handbook

combination of reduced thermal cycle and increased Ge and C content. Base transit time is limited by transit across the neutral base and the ability of carriers to exit the base at the base–collector space charge region [37]. A graph of these two components versus base width shown in Figure 3.2.12 indicates that at a neutral base width of
80 nm the transit time is less than 40 fsec. Because of the atomic layer control that SiGe epitaxy has [38], achieving neutral base widths of 8 nm is possible. The collector delay (tC) component, given by Equation (3.2.7), is the most complex and will be very challenging. Assuming we can use geometry, and clever structural device design, the CBC term can be reduced by scaling the active collector–base capacitance area and using structures like the raised extrinsic base to reduce the collector– base capacitance per unit area. The most critical area is the overlap between the extrinsic base diffusion and the SIC collector implant. Typically for vertical scaling, the collector doping is increased which increases the current (IC) and pushes out the Kirk effect. This also reduces RC. Structural innovation will also have to occur to continue reducing the emitter and collector resistance. These are difficult challenges but may be possible. And finally the last term to consider is the transit time through the collector–base space charge region given by Equation (3.2.8). This delay component is becoming a significant impediment to vertical scaling. The high-field mobility is a material property and not easily influenced by the process. Therefore, unless there are dramatic changes with a migration to new materials constants this may prove to be the limit to performance kT CBE q IC  2  kT Wb Wb þ tB ¼ DEGe Dn nexit   kT t C ¼ RE þ RC þ CBC qIC tE ¼

t CSCL ¼

tB = ∆Eg,Ge kT

2 T 2b kT − T b kT D n ∆EGe D n ∆EGe

Dn ≈ 10

>5

cm2

s−1

nexit ≈

2

(3:2:6) (3:2:7)

WCSCL 2nSAT

1−e−∆EGe /kT

1.0⫻107

(3:2:5)

cm

+

(3:2:8)

Tb nexit

kT ∆E Ge

1−e−∆EGe /kT t B ≈ kT ∆E Ge

s−1

T b2 Dn

+

300 Total

Delay Time (fsec)

250

Correction 200

Diffusion

150 100 50 0 0

50

100

150

200

250

Neutral Base Width (Angstroms)

FIGURE 3.2.12

Base transit delay time components as a function of neutral base width.

© 2006 by Taylor & Francis Group, LLC

300

Tb nexit

Device Structures and BiCMOS Integration

3.2-229

3.2.6 Summary There are many interesting bipolar structures that can be classed into three groups, non-self-aligned, self-aligned using an inner sidewall technique, and self-aligned using an outer sidewall. The BaG process integration flow is the most commonly used approach since it decouples the CMOS and bipolar thermal cycles. A challenge for the future will be the integration into advanced CMOS processes, which use mobility enhancement by strain techniques. SiGe HBTs will continue to improve in performance moving closer to 1 THz peak fT values. To achieve these values substantial material modifications of the SiGe HBTs and significant structural innovation will be required.

Acknowledgment The author would like to thank all the individuals at IBM who have contributed to SiGe HBT technology to make this work possible, as well as A. Joseph, J.-S. Rieh, J. Johnson, G. Freeman, and J. Dunn, for many helpful discussions about this work.

References 1. JR Long and MA Copeland. The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. IEEE J Solid-State Circ 32(3):357–369, 1997. 2. SA St. Onge, DL Harame, JS Dunn, S Subbanna, DC Ahlgren, G Freeman, B Jagannathan, J Jeng, K Schonenberg, K Stein, R Groves, D Coolbaugh, N Feilchenfeld, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, and S Johns. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm LEFF CMOS. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. 3. BS Meyerson, F Himpsel, and KJ Uram. Bistable conditions for low temperature silicon epitaxy. Appl Phys Lett 57:1034–1036, 1990. 4. BS Meyerson. Low temperature silicon epitaxy by ultra-high vacuum/chemical vapor deposition. Appl Phys Lett 48:797–799, 1986. 5. D Dutarte. RTCVD growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 6. WB De Boer, D Terpstra, and JGM Van Berkum. Selective versus non-selective growth of Si and SiGe. Mater Sci Eng 67:46–52, 1999. 7. E Kasper. MBE growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 8. P Magnee. SiGe:C HBT device technology: what is the big deal? Short Course Notes of the IEEE Bipolar BiCMOS Circuits and Technology Meeting, Toulouse, 2003. 9. J Osten. Carbon doping of SiGe. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 10. T Adam. UHV/CVD. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 11. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base pnp transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 12. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JY-C Sun, GJ Scilla, J Warnock, BJ Ginsberg, KA Jenkins, K-Y Toh, DL Harame, and S Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300.

© 2006 by Taylor & Francis Group, LLC

3.2-230

The Silicon Heterostructure Handbook

13. E Ganin, TC Chen, JMC Stork, BS Meyerson, JD Cressler, G Scilla, J Warnock, DL Harame, GL Patton, and TH Ning. Epitaxial-base double-poly self-aligned bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 603–606. 14. ED Johnson, TB Hook, JE Bertsch, Y Taur, CL Chen, HJ Shin, S Ramaswamy, A Edenfeld, and C Alcorn. A high-performance 0.5-mm BiCMOS technology with 3.3-V CMOS devices. Digest of Technical Papers VLSI Technology Symposium, Kyoto, 1990, pp. 89–90. 15. JD Warnock. Silicon bipolar device structures for digital applications: technology trends and future directions. IEEE Trans Electron Dev 42(3):382–383, 1995. 16. JN Burghartz, BJ Ginsberg, SR Mader, T-C Chen, and DL Harame. Selective epitaxial base transistor (SEBT). IEEE Electron Dev Lett 9(5):259–262, 1988. 17. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Trans Electron Dev 40:455– 468, 1995. 18. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Trans Electron Dev 40:455–468, 1995. 19. SA Jang, C-S Han, Y-B Kim, and I-S Yeo. The role of polysilicon in the suppression of Bird’s beak in poly-buffered LOCOS. IEEE Trans Electron Dev 46(2):433–436, 1999. 20. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 21. DL Harame, EF Crabbe, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, JC Malinowski, AJ Dally, S Ratanaphanyarat, MJ Saccamango, W Rausch, J Cotte, C Chu, and JMC Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 22. DJ Frank, RH Dennard, E Nowak, PM Solomon, Y Taur, and H-SP Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288, 2001. 23. K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, P Ronsheim, M Ieong, A Grill, and H-SP Wong. Strained Si NMOSFETs for high performance CMOS technology. Technical Digest of the VLSI Technology Symposium, 2001, pp. 59–60. 24. S Takagi, T Mizuno, T Tezuka, N Sugiyama, T Numata, K Usuda, Y Moriyama, S Nahaharai, J Koga, A Tanabe, N Hirashita, T Irisawa, and T Maeda. Strained — Si/SiGe — On Insultator CMOS Technology as a platform of device performance boosters, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 61–76. 25. T Ghani, M Armstrong, C Auth, M D Giles, K Mistry, A Murthy, L Shifren, S Thompson, and M Bohr. Uniaxial-strained Silicon CMOS Devices for High Performance Logic Nanotechnology, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 681–700. 26. EJ Nowak, I Aller, T Ludwig, K Keunwoo, RV Joshi, C-T Chuang, K Bernstein, and R Puri. Turning silicon on its edge. IEEE Circuits Dev Mag 20(1):20–31, 2004. 27. JL Hoyt, HM Nayfeh, S Eguchi, I Aberg, G Xia, T Drake, EA Fitzgerald, and DA Antoniadis. Strained Silicon MOSFET Technology. Technical Digest of the Electron Devices Meeting, Washington, 2002, pp. 23–26. 28. CW Liu, S Maikap, MH Liao, and F Yuan. BiCMOS devices under mechanical strain, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 437–438.

© 2006 by Taylor & Francis Group, LLC

Device Structures and BiCMOS Integration

3.2-231

29. H Nii, T Yamada, K Inoh, T Shino, S Kawanaka, M Yoshimi, and Y Katsumata. A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications. IEEE Trans Electron Dev 47(7):1536–1541, 2000. 30. GG Shahidi, DD Tang, B Davari, Y Taur, P McFarland, K Jenkins, D Danner, M Rodriguez, A Megdanis, E Petrillo, M Polcari, and TH Ning. A novel high-performance lateral bipolar on SOI. Technical Digest of the 1991 Electron Devices Meeting, San Fancisco, 1991, pp. 663–666. 31. T Arnborg and A Litwin. Analysis of new high-voltage bipolar silicon-on-insulator transistor with fully depleted collector. IEEE Trans Electron Dev 42(1):172–177, 1995. 32. J Cai, M Kumar, M Steigerwalt, H Ho, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the 2003 BCTM, Toulouse, 2003, pp. 215–218. 33. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, AD Stricker, DC Ahlgren, and S Subbanna. Transistor design and application considerations for >200-GHz SiGe HBTs. IEEE Trans Electron Dev 50(3):645–655, 2003. 34. G Freeman, J-S Rieh, B Jagannathan, Y Zhijian, F Guarin, and A Joseph. Device scaling and application trends for over 200 GHz SiGe HBTs. Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers 2003 Topical Meeting on Silicon Heterostructures, 2003, pp. 6–9. 35. B Jagannathan, M Meghelli, K Chan, J-S Rieh, K Schonenberg, D Ahlgren, S Subbanna, and G Freeman. 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Dev Lett 24(5):324–326, 2003. 36. J-S Rieh, KM Watson, F Guarin, Y Zhijian, P-C Wang, AJ Joseph, G Freeman, and S Subbanna. Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density. IEEE Trans Dev Mater Reliab 3(2):31–38, 2003. 37. MJW Rodwell, T Mathew, D Scott, D Mensa, Q Lee, J Guthrie, Y Betser, SC Martin, RP Smith, S Jaganathan, S Krishnan, SI Long, R Pullela, B Agarwal, U Bhattacharya, L Samoska, and M Dahlstrom. Submicron sealing of HBTs, IEEE Trans Electron Dev 48 (11): 2606–2604, 2001. 38. B Tillack, Y Yamamoto, and J Murota. Atomic Level Control of SiGe Epitaxy and Doping, Proceedings of the 206th Electrochemical Society, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 803–814.

© 2006 by Taylor & Francis Group, LLC

3.3 SiGe HBTs on CMOSCompatible SOI 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6

Jin Cai and Tak H. Ning IBM, T. J. Watson Research Center

3.3.7

The SOI Advantage ................................................... 3.3-233 Vertical Bipolar Transistors on Thin SOI................ 3.3-234 Voltage Pinning in a Fully Depleted Collector ....... 3.3-235 Making SiGe HBTs on Thin SOI Substrate ............ 3.3-238 Characteristics of SOI SiGe HBTs............................ 3.3-240 Process Optimization, Device Scaling, and Complimentary Bipolar .................................... 3.3-244 Summary .................................................................... 3.3-245

3.3.1 The SOI Advantage Silicon-on-insulator (SOI) technology has matured over the past 15 years to become production-worthy for advanced CMOS manufacturing [1], for applications ranging from high-end servers like IBM’s PowerPC and AMD’s Opteron to ultralow-power systems like Seiko and Oki’s chips for watches. Conventional silicon VLSI processing is based on bulk silicon substrates. When CMOS transistors are built into a thin silicon film of the order of 0.1 mm on top of an insulating silicon dioxide layer, the source and drain junction capacitance is greatly reduced. As a result, SOI CMOS circuits switch faster and use less power than conventional bulk CMOS. The power-delay advantage obtained from substrate material innovation has become particularly important as conventional CMOS scaling is reaching its limit. BiCMOS is the preferred technology platform for many wireless and communication applications, which need both RF/analog functions from bipolar transistors and low-power digital functions from CMOS transistors. From a mixed-signal system perspective, SOI is attractive due to the insulating nature of the substrate, which can provide RF noise isolation between digital and RF/analog components, particularly when a thick insulator or high-resistivity substrate is used [2], or when substrate engineering is applied [3]. The reduction of substrate loss also enables fully integrated high quality-factor passive elements for communication systems [2]. The challenge for SOI BiCMOS integration arises from a fundamental device architectural difference between bipolar and CMOS. Unlike CMOS transistors where current flows in a superficial silicon layer from source to drain, in high-speed vertical bipolar transistors including all SiGe HBTs, electrons flow vertically from the emitter on the top to the collector on the bottom. In order to have low resistance access to the collector from a contact electrode on the top, a subcollector layer on the order of 1 to 2 mm thick with heavy doping is needed underneath the collector, which makes it too thick to build on thin silicon film SOI. Past approaches to SOI BiCMOS integration either used a thick silicon layer on a bonded SOI substrate to accommodate the vertical bipolar transistors, or used lateral bipolar transistors on thin silicon film SOI. In the thick SOI case, the CMOS transistors have the same source and drain junction capacitances as those on a conventional bulk substrate and thus have no power-delay advantage. Digital BiCMOS technology on 1 to 1.5 mm silicon film SOI was developed for soft-error immune 3.3-233 © 2006 by Taylor & Francis Group, LLC

3.3-234

The Silicon Heterostructure Handbook

processors [4, 5]. More recently, a SiGe HBT–CMOS technology on 1 mm silicon film SOI was developed for RF and mixed-signal applications, featuring integrated high-Q inductors [2]. For such thick-silicon SOI BiCMOS, deep trenches are employed to isolate the bipolar transistors from the bulk-like CMOS devices. The lateral SOI bipolar has limited speed due to base width control and is not compatible with SiGe epitaxy. It is noteworthy that process innovations to minimize the base width and base resistance have kept improving the speed of lateral SOI bipolar transistors over the years [6–8]. With fT up to 20 GHz, it still cannot compete with vertical bipolar transistors (not to mention SiGe HBTs) in terms of performance, but it may provide a low-cost solution for mobile wireless communications due to a simpler and more CMOS-compatible manufacturing process [7]. Recently, a novel vertical bipolar transistor suitable for integration on CMOS-compatible SOI was proposed and npn transistors with SiGe base were demonstrated on 0.12 mm SOI [9–12]. The remainder of this chapter is dedicated to the concept, manufacturing process, electrical characteristics, and future prospects of this new transistor.

3.3.2 Vertical Bipolar Transistors on Thin SOI High-performance vertical bipolar transistors consist of an nþ emitter region, a p-type base region, and an n-type collector region stacked atop one another. The base and emitter regions can be built on top of the SOI substrate by epitaxial growth of a silicon–germanium base layer followed by LPCVD deposition of a polysilicon emitter film, like in most SiGe HBTs. Thus the silicon film of the SOI substrate needs to accommodate only the collector part. In conventional vertical bipolar, typically a thick nþ-type subcollector region and an nþ reachthrough region are used to give a low resistance contact to the collector at the silicon surface. The subcollector is placed deep enough to leave a quasineutral region of n-collector between the subcollector and collector space–charge region (or depletion region), such that the collector–base capacitance is not increased. This conventional collector structure would require an SOI substrate with a silicon film thickness (TSi) of at least 1 mm, as illustrated in Figure 3.3.1(a). The silicon film thickness requirement is greatly relaxed if we omit the thick nþ subcollector layer, as shown in Figure 3.3.1(b). The lower bound of TSi is determined by the depth of the depleted collector region (WC). For a collector doping concentration (NC) of 1017 cm
3 and a reverse collector–base junction bias of 2 V, WC ¼ 0.19 mm, which approaches the range of TSi for SOI CMOS devices. However, the collector current is carried laterally toward the nþ reachthrough in the thin quasineutral layer above the buried oxide, which is very resistive. The collector series resistance from the quasineutral layer is inversely proportional to NC  (TSI
WC) and can be more than 103 times higher than that of a heavily doped 1-mm thick subcollector layer. A more radical reduction of TSi to below collector depletion thickness WC leads to a new vertical bipolar transistor, as shown in Figure 3.3.1(c). The collector underneath the base and above the buried oxide is fully depleted. The fully depleted collector not only eliminates the resistive quasineutral layer but also results in a reduced collector–base junction capacitance (CCB) due to its serial connection with a small capacitance from the thick buried oxide layer. To minimize collector series resistance, the nþ reachthrough should be placed as close as possible to the depleted collector region. However, it is desirable to leave a narrow quasineutral region in-between such that the proximity of nþ reachthrough does not limit CCB or the breakdown voltage of the device. The new device structure in Figure 3.3.1(c) is similar to bending the vertical collector structure in Figure 3.3.1(a) by 908 such that most of the vertical collector stack including the lower part of collector depletion region, the quasineutral collector region, and the nþ subcollector region rest on the side of the upper part of collector depletion region. Under forward active mode, electrons injected from the emitter, instead of flowing vertically down toward the subcollector layer as in a typical vertical bipolar transistor, are guided by the two-dimensional electric field in the collector depletion region and make a turn toward the nþ reachthrough on the side.

© 2006 by Taylor & Francis Group, LLC

3.3-235

SiGe HBTs on CMOS-Compatible SOI

C

B

Reachthrough

n+

B

E

n+

n+

p

p

n TSI > 1 µm

C

E

n

Depleted n collector

TSI

Quasi-neutral n collector

n Buriedoxide oxide buried

Subcollector

n+

n

n+

Substrate of SOI

Buried buriedoxide oxide

(b)

Substrate of SOI

(a)

C

B

E

n+ Reachthrough

TSI < 0.2 µm

n+

p n

n

Depleted n collector Quasi-neutral n collector

Buriedoxide oxide buried Substrate of SOI

(c)

FIGURE 3.3.1 Schematics of npn bipolar transistors on SOI substrate, showing the evolution of collector design that leads to the new transistor. The three cross sections have the same base and emitter layers but different collector layers: (a) the traditional design with nþ subcollector underneath the n-collector, (b) without nþ subcollector, and (c) fully depleted n-collector.

The new device concept overcomes the TSi limit for integrating SiGe HBT with SOI CMOS. For a given TSi that is usually dictated by CMOS scaling requirement, there is an upper limit to the collector doping concentration that satisfies WC ¼ TSi. To maximize the high-frequency performance of the HBT, an NC near this limit can be used to delay the onset of base push-out, or Kirk effect.

3.3.3 Voltage Pinning in a Fully Depleted Collector In this section, a simple one-dimensional theory is used to analyze the onset condition of full collector depletion, as a function of the physical structure (TSi, NC) and bias conditions (VB, VC, and VS for base, collector, and SOI substrate, respectively). The unique characteristic of collector voltage pinning and its consequence on bipolar device operation will be highlighted. For simplicity, consider part of the SiGe HBT structure, with base, collector, nþ reachthrough, and SOI substrate, as illustrated in Figure 3.3.2(a). Due to the symmetry, along the central cut line, the electric field is vertical and the potential distribution can be solved exactly using one-dimensional Poisson’s equation. The problem is simply a p–n diode in series with a MOS capacitor. Figure 3.3.2(b) illustrates the band diagram along the cut line for the case where both the p–n diode and MOS capacitor

© 2006 by Taylor & Francis Group, LLC

3.3-236

The Silicon Heterostructure Handbook

VB

VC

VC p y1

n+

n+

n

y2

TBox

Buried oxide Substrate of SOI

p+

VS

(a)

Base Collector SiO2 Substrate

Base Collector SiO2 Substrate

E

TSI

EC

TSI

TSI VS

VB EV

EMAX

VC Y y1

y2

y1

(b)

y2

(c)

FIGURE 3.3.2 Analysis of collector potential distributions based on depletion approximation. (a) Schematic cross section of part of an SOI bipolar transistor with symmetrically placed nþ reachthough regions; (b) energy band diagram along the central cut line; and (c) electric field distribution along the same cut line.

are reverse-biased (VB < VC, VS < VC), with two distinct depletion regions of width y1 and y2, respectively (y1 þ y2 < TSi). Figure 3.3.2(c) illustrates the electric field distribution along the same cut line. The voltage in the collector quasineutral region follows VC of the nþ reachthough regions. 0 Increase of collector voltage widens both depletion regions and at certain critical voltage VC , the 0 two depletion regions merge. Increase of collector voltage beyond VC no longer influences the vertical 0 field. The potential well along the center line has a fixed depth determined by VC. This is referred 0 to as collector voltage pinning. Away from the centerline, the additional voltage VC –VC increases the lateral field. The critical collector voltage can be solved analytically using depletion approximations for both the p/n diode and the MOS capacitor. For the base–collector diode, assuming one-sided abrupt junction, depletion width y1 is described by VC
VB þ VBI ¼

q NC y12 ; 2«S

(3:3:1)

where VBI is the diode built-in potential. For the MOS capacitor, the depletion width y2 near the buried oxide is described by VS
VC
fMS ¼ VOX þ VSI ¼


qNC y2 q
NC y22 ; 2«S COX

(3:3:2)

where fMS is the work function difference between the pþ substrate of SOI and the n-collector, VOX and VSI are potentials dropped across the buried oxide and the collector depletion region (y2), respectively. 0 The critical collector voltage VC that fully depletes the collector, i.e., y1 þ y2 ¼ TSi, can be solved based on Equations (3.3.1) and (3.3.2):

© 2006 by Taylor & Francis Group, LLC

3.3-237

SiGe HBTs on CMOS-Compatible SOI

VC0 ¼ VB
VBI þ

q q 0 NC (y10 )2  VCM ¼ VB
VBI þ NC TSi2 ; 2«S 2«S

(3:3:3)

0

where y1 is the value of y1 at the onset of full depletion: y10


 1=COX þ 1=(2CS )
(VB
VS þ fMS
VBI )=qNC TSi ; ¼ TSi 1=COX þ 1=CS

(3:3:4)

Saturated collector (VC'<0)

I. Fully depleted collector

VC (V)

1.0

=VS −φm

1.5

VC

T_SI = 120 nm T_BOX = 140 nm NC = 1.5E17/cm3 VB = 0 V

2.0

s

CS ¼ «S/TSi and COX ¼ «OX/TBOX. For thick buried oxide (COX << CS) and low substrate biases (VS  VB), the depletion region due to the MOS capacitor is narrow and y10  TSi. In general, when the MOS capacitor is under flatband condition and the collector is fully depleted from the p/n diode (y10 ¼ TSi), 0 . More negative substrate bias induces the critical collector voltage reaches the maximum value of VCM a depletion region near the buried oxide, which has the effect of lowering the critical collector voltage via a smaller y10 . In the other direction, under more positive substrate bias, the MOS capacitor is under surface accumulation condition, i.e., electrons accumulate near the buried oxide interface. The accumulation layer is linked to the nþ reachthrough regions and acquires the collector potential VC. This breaks the collector voltage pinning. The vertical potential drop again follows the collector voltage. The accumulation layer acts like an ultrathin subcollector, which is shown to significantly enhance the speed of the SOI SiGe HBTs in Section 3.3.5. We call this novel structure with depleted collector directly on accumulated back surface the accumulation-subcollector transistor. For any SOI bipolar structure, there are four distinct types of collectors depending on the bias condition: (i) fully depleted collector; (ii) partially depleted collector with depleted back surface; (iii) partially depleted collector with accumulated back surface, and (iv) depleted collector on accumulated back surface (accumulation subcollector). The bias condition that defines the collector type is shown in Figure 3.3.3 for an SOI bipolar device with TSi ¼ 120 nm, TBOX ¼ 140 nm, NC ¼ 1.5  1017 cm
3, which is used in the experiment described in Section 3.3.4. VB ¼ 0 is the reference voltage. The boundary between regions I and II is described by Equation (3.3.3). The single point that borders all four

IV. Depletedcollector on accu. layer VC = VCM

0.5 VC

C'

=V

0.0 −0.5 −1.0

II. Partially depleted collector (depleted back surface) −4

−2

0 VS (V)

III. Partially depleted collector (accu. back surface)

2

4

FIGURE 3.3.3 The collector characteristic of an SOI bipolar transistor is categorized into four types depending on the collector and SOI substrate bias conditions: (1) fully depleted collector, (2) partially depleted collector with depleted back surface, (3) partially depleted collector with accumulated back surface, and (4) depleted collector on accumulated back interface, or accumulation subcollector.

© 2006 by Taylor & Francis Group, LLC

3.3-238

The Silicon Heterostructure Handbook

regions corresponds to the condition that y10 ¼ TSi in Equation (3.3.4). It is noteworthy that in the fully depleted collector region, reduced vertical potential drop due to the negative substrate bias can lead to effective forward biasing of the B–C junction (VC0 < VB) for an apparent reverse bias condition (VC > VB), as shown by the shaded area. This region gives rise to collector saturation and should be avoided in circuit applications. There is a well-known tradeoff between the speed (fT) and the breakdown voltage (BVCEO) in a traditional bipolar transistor, from the vertical scaling of the collector depletion layer [13]. The voltage swing of a high-speed device is constrained by the breakdown voltage. We can design an SOI bipolar device such that the collector voltage is pinned at a value below the BVCEO of a bulk device with the same collector doping. The SOI device is expected to have improved BVCEO as well as Early voltage VA. Avalanche multiplication and breakdown is sensitive to the maximum electric field (EMAX) near the B–C junction interface. In a bulk device, EMAX increases with collector voltage as a function of pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 0 VC
VB þ VBI , whereas in the fully depleted collector device, it is pinned at (qNC/e S)y1 , independent of collector voltage. Thus avalanche effect progresses more slowly with increasing collector voltage in a fully depleted collector device than a bulk device. Avalanche breakdown is delayed to higher collector voltage in the SOI device where the lateral field becomes large enough to raise EMAX. The depletion width on the base side is determined by EMAX, which does not change with collector voltage in the fully depleted collector device. Therefore, the modulation of quasineutral base width by the collector voltage is much weaker than that of a bulk device, which results in higher VA. In an accumulation-subcollector device (region IV in Figure 3.3.3), the B–C junction reverse bias is dropped over TSi whereas in a bulk device the same reverse bias is dropped over a larger distance, or WC > TSi if collector-doping concentrations are the same. This means higher EMAX and somewhat degraded BVCEO and VA in an accumulation-subcollector device. The difference in the maximum field is SOI Bulk EMAX
EMAX ¼

qNC WC
TSi : «S TSi

(3:3:5)

3.3.4 Making SiGe HBTs on Thin SOI Substrate Figure 3.3.4 shows the process flow diagrams for building npn SiGe HBTs on SOI substrate. The silicon film thickness for SOI CMOS has been scaled down from about 0.2 mm to below 0.1 mm, along with channel length scaling. The new SiGe HBT is expected to be scalable to thinner SOI substrate as will be discussed in Section 3.3.6. In the experiment, we used the same SOI substrate that is used for a 130 nm SOI CMOS technology [14], which has a silicon thickness of 0.12 mm and a buried oxide thickness of 0.14 mm. After shallow-trench isolation, a phosphorus implant is introduced to define the collectordoping concentration in the silicon area. It can be a blanket implant in a bipolar-only process, or a masked implant in a BiCMOS flow. Both a uniform doping profile and a low–high retrograde doping profile were exercised. Then a mask is used for a high-dose phosphorus implant that defines an nþ reachthrough region surrounding the n-type collector in the middle. The mask dimension determines the length of the n-collector, LC, which was varied in the experiment to evaluate its effect on collector resistance and breakdown behaviors. Next, a dielectric stack, followed by a heavily doped pþ polysilicon layer, is deposited over the wafer. The pþ polysilicon will provide low-resistance contact to the base and the dielectric stack is served as an insulator between the pþ polysilicon and the collector. The thickness of the insulator should be optimized as it contributes to parasitic collector–base capacitance. The parasitic CCB could dominate in a fully depleted collector device as the collector–base junction capacitance is minimized. The use of a thicker insulator reduces CCB but creates more topography later in the process that can increase the base resistance. Then a window is etched into the polysilicon and insulator to expose the silicon surface for epitaxial growth of the SiGe base layer. The window size, LB, should be minimized while providing enough room for a defect-free SiGe base region. The SiGe base layer was grown by a nonselective

© 2006 by Taylor & Francis Group, LLC

3.3-239

SiGe HBTs on CMOS-Compatible SOI

n Buried oxide

STI, collector implant

Substrate of SOI

n+

n+

n Buried oxide Substrate of SOI

p+ n+

n+ reachthrough implant p+ n+

n

Dielectric stack, p+ poly

Buried oxide Substrate of SOI

p+ n+

p+

p n

n+

SiGe-base

Buried oxide Substrate of SOI

n+

n+ p+ n+

Dielectric stack, emitter window

p+

p n

n+

Buried oxide

n+ poly emitter

Substrate of SOI

p+ n+

n+ p n

p+ n+

Pattern n+ emitter poly

Buried oxide Substrate of SOI

B p+ n+

E n+ p n

p+

Buried oxide Substrate of SOI

C

Pattern p+ base poly

n+ CoSi, and contact open

FIGURE 3.3.4 An example of process flow to make SiGe HBTs on CMOS-compatible SOI.

© 2006 by Taylor & Francis Group, LLC

3.3-240

The Silicon Heterostructure Handbook

FIGURE 3.3.5 Cross-sectional SEM micrograph of a SiGe HBT on 0.12 mm silicon film SOI.

low-temperature epitaxy (LTE) process using UHV/CVD tools. During the LTE process, polysilicon is grown on the sidewalls of the dielectric window, which provides the link between the SiGe base layer and the overhanging pþ polysilicon layer. Next, a second dielectric stack is deposited which will serve as an insulator between the base and the emitter. An emitter window mask is used to etch an opening in the dielectric stack, and a layer of in situ arsenic-doped polysilicon layer is deposited that becomes the nþ emitter. Due to the two-dimensional electric field in the depleted collector region, the electrons coming down through the middle of the emitter window will have a longer lateral drift path in the depleted collector than those from the edge of the emitter window. The speed of the SOI device is expected to degrade at large emitter width. Simulation results suggest that a good rule of thumb is to keep WE < 2TSi. Two more mask levels are then used to pattern an nþ polysilicon emitter region and a pþ polysilicon base region, respectively. Cobalt silicide is formed over the pþ base and nþ collector reachthrough regions to reduce access resistance to the intrinsic base and collector of the device. Finally, contacts to the nþ emitter, pþ base, and nþ collector reachthrough are etched open. It should be noted that the deep subcollector implantation and drive-in, the n-type epitaxial silicon growth, and the deep-trench isolation process steps associated with fabrication of a conventional vertical bipolar transistor are not needed in fabricating the thin-SOI bipolar. Figure 3.3.5 shows an SEM micrograph of an SOI SiGe HBT, after contacts to the emitter, base, and collector are opened. The mask dimensions of emitter width, LTE window, and collector length are 0.16, 0.5, and 1.2 mm, respectively. The collector-doping profile is uniform, with NC ¼ 1.5  1017 cm
3. Devices with smaller LB and LC designs and different collector-doping profiles were also fabricated.

3.3.5 Characteristics of SOI SiGe HBTs In this section, the electrical characteristics of the manufactured thin-SOI SiGe HBTs will be reviewed, with a focus on the breakdown behavior in the depleted collector SOI device as well as the substrate bias effect on both the DC and AC performance. Figure 3.3.6 shows the Gummel plot and the output IC
VCE characteristics, with substrate bias, VSE (referenced to the emitter voltage), as a parameter that is varied from
5 to 20 V. The Gummel plot shows a peak current gain of over 400. Since the base and emitter process are borrowed from a bulk SiGe technology [15], the current gain is similar to that of the bulk devices. The substrate bias has an effect at emitter–base forward biases higher than 0.9 V. The opposite movement in IB and IC is a signature of collector saturation effect where the forward biasing of collector–base junction reduces IC while contributing to more IB. A positive substrate bias suppresses this saturation effect by increasing the vertical potential drop in the collector that prevents electrons from back injection into the base. The

© 2006 by Taylor & Francis Group, LLC

3.3-241

SiGe HBTs on CMOS-Compatible SOI

0.01 VCB = 0 V 1⫻10−4 IC IC, IB (A)

1⫻10−6 IB 1⫻10−8

VSE= −5 V 0V 5V 20 V

1⫻10−10

1⫻10−12 0.6

0.7

0.8

0.9

(a) 1.0

1.1

VBE (V) 0.25 IB = 0.1 µA/step

IC (mA)

0.20

0.15

0.10

0.05

(b) 0.00 0

1

2

3 VCE (V)

4

5

6

FIGURE 3.3.6 DC characteristics of a 0.16 mm  0.8 mm SOI SiGe HBT under four substrate bias (VSE ¼ VS
VE) conditions:
5 V (dash–dot), 0 (solid), 5 V (dash), and 20 V (dot). (a) Gummel plot and (b) output characteristics.

IC
VCE in Figure 3.3.6(b) shows almost identical turn-on behaviors under zero and positive substrate biases, whereas under the negative substrate bias, it requires higher collector voltage to turn on the device, another manifestation of saturation effect. This is consistent with Figure 3.3.3, which predicts an 0 effectively forward biased B–C junction (VC
VB < 0) when VS
VB <
2 V. As expected from the voltage-pinning effect, BVCEO is the highest at 5.5 V under zero substrate bias. The reduction of BVCEO at VSE ¼ 20 V is due to the accumulation subcollector that breaks the voltage pinning and creates a vertical potential drop of VCB across TSi. In contrast, at VSE ¼ 5 V, avalanche current turns on at the same VCE as the high-positive bias case, but the rate of increase with collector voltage is slower. This can be explained by Figure 3.3.3. Under low-positive VSE, as VCE increases, the collector makes a transition from the one with an accumulation subcollector (region IV) to a fully depleted collector (region I). The transition decouples the collector voltage to the maximum electric field at the B–C junction interface and results in a much slower increase of avalanche current with VCE.

© 2006 by Taylor & Francis Group, LLC

3.3-242

The Silicon Heterostructure Handbook

For the same collector design, BVCEO depends on the current gain (IC/IB) due to the bipolar effect. A more direct examination of avalanche multiplication is through the measurement of the ‘‘M
1’’ factor [16]. In this measurement, a constant forward emitter current (IE) is forced through the device while ramping up the collector voltage. The electron–hole pairs generated by impact ionization in the collector depletion region contribute to an increase in the collector current and a corresponding reduction in the base current (DIC ¼
DIB). The factor ‘‘M
1’’ is extracted as jDIBj/IE. Figure 3.3.7(a) compares the avalanche multiplication in an SOI SiGe HBT to two bulk SiGe HBTs with 90 GHz fT (open symbols) and 50 GHz fT (solid symbols), respectively. In bulk devices, avalanche multiplication has the similar exponential dependence on VCB. The 90 GHz device has an ‘‘M
1,’’ which is about 6 times higher than the 50 GHz device due to heavier collector doping concentration as a part of vertical scaling. The SOI device shows a much weaker dependence of ‘‘M
1’’ on VCB under zero substrate bias, or under positive substrate bias in the high VCB range. This corresponds to the bias conditions for a fully depleted collector. In the open-base configuration, the increase of collector current due to avalanche effect is multiplied by the current gain b of the bipolar transistor. When b(M
1) ¼ 1, the collector current is doubled from its

1

IE = 10 µA Bulk SiGe HBT

Multiplication factor −1

0.1

20V

0.01

5V

1⫻10−3 0V

1⫻10−4

−5V

1⫻10−5 0

1

(a)

2

SOI SiGe HBT 3

4

5

Collector−base reverse bias (V)

M−1 at VCB = 1.5 V (10−3)

5 4

SOI SiGe HBT (increase substrate bias)

3

NC2

2 bulk SiGe HBT (vertical scaling)

1 NC1 0 20

(b)

40

60

80

100

Cut-off frequency (GHz)

FIGURE 3.3.7 Comparison of measured avalanche multiplication factor (M
1) in the collector–base junction between SOI SiGe HBTs and bulk SiGe HBTs. (a) ‘‘M
1’’ as a function of reverse C–B junction bias. (b) Correlation between ‘‘M
1’’ and cutoff frequency, dashed line indicates trend from bulk SiGe HBT technologies.

© 2006 by Taylor & Francis Group, LLC

3.3-243

SiGe HBTs on CMOS-Compatible SOI

low VCB value, which can be used as a measure for device breakdown. The flat portion of the ‘‘M
1’’ data suggests that it is possible to significantly increase the BVCEO of a fully depleted collector device by reducing the current gain from 400 in the experimental hardware to about 100. Under positive substrate bias and in the low VCB range, which corresponds to the accumulation subcollector condition, ‘‘M
1’’ is nearly the same as the 50 GHz bulk device. Under negative substrate bias, the exponential rise of ‘‘M
1’’ suggests that the lateral field dominates avalanche multiplication in the saturated collector region where there is minimum vertical potential drop in the collector. Figure 3.3.7(b) shows that the SOI devices and the bulk devices have a different ‘‘M
1’’ versus fT tradeoff. The peak fT of the SOI devices can be improved by applying positive substrate biases without much increase of avalanche multiplication, while scaling NC in a bulk device results in a steeper penalty in ‘‘M
1,’’ or breakdown voltage. The fT and fMAX characteristics of an SOI SiGe HBT are shown in Figure 3.3.8, along with those of a lateral SOI bipolar device from Ref. [7]. The SiGe HBT shows a 150% to 350% improvement in peak fT, depending on the substrate bias condition. The maximum oscillation frequency, fMAX, on the other pffiffiffiffiffiffiffiffiffiffiffiffiffiffi hand, is less sensitive to the substrate bias. This is expected from the fMAX / fT =CCB dependence. As VSE increases, CCB increases as the collector makes a transition from a fully depleted one to the one with an accumulation subcollector. A 30% increase of fT is observed for a VSE change from 0 to 5 V, while there is minimal change in fMAX. This suggests that CCB increases by 30% due to the presence of an accumulation back surface. To understand the strong dependence of fT on VSE, it is instructive to look at the two-dimensional potential distribution in the collector depletion region. Figure 3.3.9 shows the simulated equipotential contours in the forward active mode with VCB ¼ 1 V and VBE ¼ 0.84 V. The potential VI is referenced to the vacuum level in the emitter. The boundaries of the collector depletion region are defined approximately by VI ¼
4 V at the base side and VI ¼
2.5 V at the nþ reachthrough side. At zero substrate bias (VSE ¼ 0 V) in part (a), the collector is fully depleted under the base and there is little potential drop along the vertical direction. The arrow indicates the electron drift path along the electric field direction. It is mostly lateral with a length of 0.5 mm. At 20 V substrate bias (VSE ¼ 20 V), the potential at the back interface is fixed at VI ¼
2 V, the same potential as the nþ

80 fT

SOI substrate bias

fMAX

20 V

fT, fMAX (GHz)

60

5V Vertical SOI SiGe HBT 40 0V

20

Lateral SOI Bipolar [7] 0 1⫻10−6

1⫻10−5

1⫻10−4

1⫻10−3

Collector current/emitter length (A/µm)

FIGURE 3.3.8 fT and fMAX characteristics of a 0.16 mm  0.8 mm SOI SiGe HBT, with SOI substrate bias as a parameter. The characteristics of a lateral SOI bipolar transistor from Ref. [7] are plotted for comparison.

© 2006 by Taylor & Francis Group, LLC

3.3-244

The Silicon Heterostructure Handbook

VCB = 1 V, VBE = 0.84 V 1.0

1.0

0.8

0.8

−3.5

3 −2.5

3 −2.5

C

0.4

−2.5

−2.5 −5

−3.5

−4.5 −5

−3.5 −3

−4 −3.5

y (µm)

B

0.6

3 −2.5

C

0.4

−2.5

−3

−3.4 −2.5

−2 5 10 14.8

−4.5 −5

−4

E −4 −5.5

−4 −3.5 −3

5 10 14.8

0.2

0.2

S

S

0.0

VSE = 0 V

x (µm)

(a)

VSE = 20 V

x (µm)

1.0

0.9

0.8

0.7

0.6

0.4

0.3

0.2

0.1

0.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.0

0.5

y (µm)

E

B

0.6

(b)

FIGURE 3.3.9 Simulated potential contours in (a) a fully depleted collector device and (b) the same device transformed to an accumulation subcollector device by a 20 V substrate bias. The arrows represent the direction of electron flow in the collector depletion region. Due to symmetry, only half of the device structure is shown.

reachthrough region. The large substrate bias attracts a majority carrier accumulation layer with an electron concentration of (VS
VC
VBI)/qCOX ¼ 2.7  1012 cm
2. The accumulation layer serves as an ultrathin subcollector, which provides a low resistance path to the nþ reachthrough. It also helps to reduce the collector series resistance in the reachthrough region. The electron drift path becomes vertical and much shorter, on the order of the SOI film thickness, or 0.1 mm. The shortened drift path results in a transit time tBC ¼ WdBC/2vSAT reduction of about 2 psec, which accounts for 80% of the fT improvements. The remaining improvement comes from the reduction of collector series resistance from the accumulation subcollector. Similar fT improvement may be obtained at a much lower substrate bias if the buried oxide is scaled down. For future SOI-CMOS technology, the ability to use a back gate voltage to control the CMOS threshold voltage is desirable for compensating chip-to-chip process variations. This can drive the scaling of buried oxide thickness to below 20 nm. On an SOI substrate with relatively thin buried oxide, it would suffice to connect the SOI substrate of the bipolar portion to the supply voltage VCC (3 V) of the analog–RF circuits to get the benefit of an accumulation subcollector. Use of nþ substrate instead of pþ substrate would further lower the required substrate bias by about 1 V. In lieu of an accumulation subcollector, a retrograde collector-doping profile with low concentration near the base and high concentration near the buried oxide can simulate some of the accumulation-subcollector effect, albeit the doping gradient is limited by the diffusion process and is much less ideal. Experimental hardware with a retrograde collector-doping profile measured a 60 GHz fT at zero substrate bias [11]. The ECL ring oscillator operation has been demonstrated using SiGe SOI bipolar transistors, with a minimum delay time of 18 pico-second per stage for a logic swing of 300 mV [11].

3.3.6 Process Optimization, Device Scaling, and Complimentary Bipolar This section will highlight the opportunities for some future work on the SOI SiGe HBTs. First, there are several process development opportunities for enhancing the device speed while maintaining the benefit

© 2006 by Taylor & Francis Group, LLC

3.3-245

SiGe HBTs on CMOS-Compatible SOI TABLE 3.3.1

Lithographical and SOI Thickness Scaling of Vertical SOI Bipolar Transistors Scaling Factor

Parameters

Fully Depleted Collector

WE, LB, LC TSi NC IC/LE WdBC, lateral WdBC, vertical RCLE CCB/LE RCCCB

a b 1/b2 a/b2 a b — — —

Accumulation Subcollector

Partially Depleted Collector

a b 1/b2 a/b2 — b a a/b a2/b

a b 1/b2 a/b2 — b ab a/b a2

of high breakdown voltage, which includes: (1) self-alignment of the LTE window to the nþ reachthrough region; (2) minimizing the ‘‘facet’’ region near the edge of the epitaxial layer such that the LTE window size (LB) can be reduced for the same emitter width; and (3) self-alignment of the emitter opening to the base layer. All these steps would facilitate closer placement of the nþ reachthrough to the center of the device to reduce the lateral drift path in a fully depleted collector. A buffered region of intermediate doping concentration between the nþ reachthrough and the n-collector would also help to reduce the lateral drift path while maintaining the same collector voltage pinning under the base. For SOI-CMOS, the trend in lateral (lithography dimensions) and vertical (TSi) scaling is expected to continue. We will show that the RF performance of the SOI bipolar device will benefit from this scaling trend as well. Table 3.3.1 shows the effect of scaling on the collector depletion layer drift length WdBC and collector delay time RCCCB for three types of collectors: fully depleted, depleted with accumulation subcollector, and partially depleted. Independent lateral and vertical scaling factors, a(<1) and b(<1), respectively, are assumed. A good guideline is to increase the collector doping concentration (NC) by 1/b2, such that the collector depletion width is reduced by the same factor b as TSi. A fully depleted collector remains fully depleted after scaling, with a shorter lateral drift path determined by the lateral scaling factor a. For the accumulation subcollector and partially depleted collector devices, in addition to a reduction in the vertical drift path by b, the collector resistance reduction results in an RC delay time reduction of up to a factor of a2. Thus, even the partially depleted device can be an attractive option after significant reduction in RC delay time. Simulation results suggest at 100 nm emitter width, 200 GHz fT can be achieved on 55 nm SOI substrates using a collector-doping concentration of 2.4  1018 cm3. The guideline for NC scaling will be eventually limited by the base–collector band-to-band tunneling current and the collector breakdown voltage. Though the speed of SOI SiGe HBT will not be as high as the most advanced bulk SiGe HBT, it will be adequate for most of the RF and wireless applications. Compared to bulk SiGe HBTs, the SOI device features a simpler manufacturing process as deep trench isolation and epitaxial collector are not necessary and the deep subcollector is omitted. The full dielectric isolation of each transistor by the shallow-trench and the buried oxide provides a lower cost opportunity to make both vertical npn and vertical pnp bipolar transistors on the same chip, as illustrated in Figure 3.3.10. In bulk technologies, usually only vertical SiGe npn and lateral Si pnp transistors are available, the latter simply as two back-to-back connected p–n diodes that have very low performance. The availability of a high-performance vertical SiGe pnp transistor should provide innovation opportunities in analog circuit design for significant performance improvement and power saving.

3.3.7 Summary We presented a new class of vertical SiGe HBTs that is compatible with SOI-CMOS. The unique feature of collector voltage pinning in thin silicon film was discussed in depth, which gives rise to high breakdown voltage, high early voltage, and low collector capacitance. The SOI device is promising for

© 2006 by Taylor & Francis Group, LLC

3.3-246

The Silicon Heterostructure Handbook

pnp

npn

E

E B p+ n+ p+ C

B C n+ p+ n+ p+

p

p+

n+

n

n+

nMOS

pMOS

G

G

S n+ D D p+ S n+ p n+ p+ n p+

Buried oxide Substrate of SOI FIGURE 3.3.10

Illustration of an SOI complementary bipolar and CMOS technology.

a better fT-BVCEO tradeoff than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of DC and RF characteristics on SOI substrate bias. The relatively low speed of a fully depleted collector device can be significantly enhanced by a positive substrate bias for an accumulation-subcollector operation. The new device is expected to scale well with SOI-CMOS and can enable complementary SOI-BiCMOS with the possibility of a high-performance pnp transistor.

Acknowledgments The authors would like to thank M. Kumar, M. Steigerwalt, H. Ho, A. Ajmera, K. Stein, H. Chen, and M. Khater for process support, Q. Ouyang, P. Oldiges, J. Rieh, and K. Jenkins for simulation and characterization help, and G. Shahidi, W. Haensch, G. Freeman, and D. Ahlgren for management support.

References 1. G.G. Shahidi. SOI technology for the GHz era. IBM J. Res. Develop. 46(2–3), 121–131 (2002). 2. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, K. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180 GHz fMAX 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEDM Tech. Digest, 741–744 (2000). 3. J.N. Burghartz, M. Bartek, B. Rajaei, P.M. Sarro, A. Polyakov, N.P. Pham, E. Boullard, and K.T. Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proc. BCTM, pp. 17–23 (2002). 4. T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Usami, and T. Ikeda. A 27-GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mm2 CMOS cells for ECL-CMOS SRAM applications. IEDM Tech. Digest, 39–42 (1992). 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Konda, S. Konda, Y. Homma, N. Owada, and T. Ikeda. A 0.2 mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. IEDM Tech. Digest, 209–212 (1998). 6. G.G. Shahidi, D.D. Tang, B. Davari, Y. Taur, P. McFarland, K. Jenkins, D. Danner, M. Rodringuez, A. Megdanis, E. Petrillo, M. Polcari, and T.H. Ning. A novel high-performance lateral bipolar on SOI. IEDM Tech. Digest, 663–666 (1991). 7. T. Shino, S. Yoshitmi, H., Nii, S. Kawanaka, K. Inoh, T. Yamada, T. Fuse, Y. Katsumata, M. Yoshimi, S. Watanabe, and J. Matsunaga. Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications. IEEE Trans. Electron Dev. 49(3), 414–421 (2002). 8. H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshomi, and Y. Katsumata. A novel lateral bipolar transistor with 67-GHz fMAX on thin-film SOI for RF analog applications. IEEE Trans. Electron Dev. 47, 1536–1541 (2000).

© 2006 by Taylor & Francis Group, LLC

SiGe HBTs on CMOS-Compatible SOI

3.3-247

9. J. Cai, A. Ajmera, Q. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, and T. Ning. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI. Symp. VLSI Tech. Digest, pp. 172–174 (2002). 10. Q. Ouyang, J. Cai, P. Oldiges, and J. Johnson. A simulation study of thin SOI bipolar transistors with fully or partially depleted collector. BCTM Tech. Digest, 28–31 (2002). 11. J. Cai, M. Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K. Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Oldiges, and T. Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proc. BCTM, pp. 215–218 (2003). 12. L. Geppert. A better bipolar transistor for wireless ICs. IEEE Spectrum, December 2003, p. 20. 13. Y. Taur and T. H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (1998) [chapter 8]. 14. P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L. Lin, R. Mann, E. Meciejewski, S. Narasimha, P. O’Neil, S. Rauch, D. Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt, and T.C. Chen. A high-performance 0.13 mm SOI CMOS technology with Cu interconnects and low-k BEOL dielectrics. Symp. VLSI Tech. Digest, pp.184–186 (2000). 15. G. Freeman, D. Ahlgren, D.R. Greenberg, R. Groves, F. Huang, G. Hugo, B. Jagnnathan, S.J. Jeng, J. Johnson, K. Schonenberg, K. Stein, R. Volant, and S. Sabbanna. A 0.18 mm 90 GHz fT SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications. IEDM Tech. Digest, 569–572 (1999). 16. G. Freeman, J. Rieh, B. Jagannathan, Z. Yang, and F. Guarin. Device scaling and application trends for over 200GHz SiGe HBTs. Proc. International SiGe Technology and Device Meeting, pp. 51–52 (2003).

© 2006 by Taylor & Francis Group, LLC

3.4 Passive Components 3.4.1 3.4.2 3.4.3

Introduction............................................................... 3.4-249 Resistors and Capacitors........................................... 3.4-251 Inductors and Transformers..................................... 3.4-252 Inductors on Silicon Substrates . Integrated Transformers

3.4.4 3.4.5 3.4.6

Transmission Lines .................................................... 3.4-258 Diodes and Switches ................................................. 3.4-258 Special Passive Components..................................... 3.4-259

3.4.7

Summary .................................................................... 3.4-260

Joachim N. Burghartz Delft University of Technology

Emerging Passives . Suppression of Parasitic Effects

3.4.1 Introduction Passive components (e.g., resistors, capacitors, inductors, and transformers) and passive devices (e.g., varactors, Schottky diodes, and pin diodes) are integral parts of the functioning and performance of radio-frequency (RF) building blocks [1]. They are used for impedance matching and transformation, in filters, in resonators, in delay lines and baluns, and for many other purposes. In RF front-end circuits they often outnumber the active device count. Unlike in the past, bipolar/BiCMOS and CMOS technologies for communications are limited today to a large extent by the quality and cost of those passive components and devices. Modern wireless communication products increasingly contain integrated passives, i.e., passive components that are engineered by exploiting the structures and materials of the device integration process itself. This is in contrast to the hybrid RF systems that have been used in RF communications for a long time. The reason behind the trend toward integration is not only cost reduction but also the small inductance (0.5 to 10 nH) and capacitance (100 to 1 pF) values needed in the current RF circuits operating at >>1 GHz. The parasitic inductances, capacitances, and resistances of the interconnects are then becoming comparable in value to those of the passive component itself, thus generally lowering the quality of that component. Also, such interconnects with all associated parasitics have to be carefully considered in the circuit design making that task extremely difficult. Placement of passive components off chip into the package or onto the printed circuit board (PCB) as a coplanar waveguide (CPW), a microstrip, or a discrete element is no longer an option as RFs are >1 GHz. Chip integration of passives, however, raises other concerns [2]. At frequencies in the range of about 900 MHz to 2.4 GHz, the inductance and capacitance values needed are considerably large (e.g., for a 50-V impedance; see Figure 3.4.1), thus occupying excessive chip real estate. Since that chip area is cycled through the entire transistor fabrication process on-chip inductors and capacitors are expensive. The total area taken by the inductors can in some circuits occupy nearly 50% of the total chip area. An option, which is sometimes used at frequencies near 1 GHz, is the simulation of a large capacitance or a large inductance by active circuitry. That technique, however, has the disadvantage that it generally leads to higher power and noise. The task of integrating inductors and capacitors is simpler at elevated RF, at which comparably smaller values of inductance and capacitance are required. Figure 3.4.1 illustrates that near 15 GHz, however, inductance values as low as 0.5 nH are needed to represent a 50-V impedance on 3.4-249 © 2006 by Taylor & Francis Group, LLC

3.4-250

The Silicon Heterostructure Handbook

Too large size!

Too small inductance value! Too long transmission line!

2

10

1.5 l = λ/4

1

1

l (mm)

L (nH); C (pF)

wL = 50 W

0.5 1/wC = 50 W 0.1

0

10

20

30

40

50

0

f (GHz)

FIGURE 3.4.1 Inductance and capacitance values needed to represent a 50 V impedance. Microstrip length required for a l/4 transmission line. (From JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Integrated RF passive components — discrete vs. distributed. Proceedings of the Device Research Conference, 2001, pp. 113– 114. With permission.)

chip. Beyond about that value on-chip inductors face the same virtue as their in-package counterparts did at about 1 GHz, i.e., their inductance becomes comparable to that of the interconnects feeding signals into them. At frequencies >15 GHz one, therefore, would like to use inductors and capacitors in a distributed form, i.e., by using CPWs or microstrips, as one used to do on PCB at low RF. In contrast to the lumped passive elements, which had to be smaller than l/10, such transmission line structures need to have a physical size of at least l/4 [3]. That means that the concerns with the size of the on-chip passive components suddenly become stressed again with that migration from lumped to distributed component design. Only at frequencies >30 GHz RF circuit design based on integrated microstrips or CPWs starts to become economically feasible (Figure 3.4.1). In spite of the simplicity of the illustrations in Figure 3.4.1, it becomes obvious that the frequency range from 15 to 30 GHz requires the RF engineer’s ingenuity to be able to come up with solutions to the integration of passive components [4]. In addition to the issue of chip area, any extra process steps required for the integration of the passive components and devices have to be taken into consideration. In a SiGe fabrication process, preference will likely be given to such passive component and device structures that can be integrated by exclusively using process elements from the bipolar transistor integration process (Table 3.4.1). Since most silicon RF integration schemes today are BiCMOS processes, with the SiGe HBT merged into a logic CMOS

TABLE 3.4.1 Types of Passive Components and Devices Listed with the Device Integration Processes, in which They Most Efficiently Can Be Realized Type of Passive Component

Bipolar

CMOS

Add-On

Resistor Capacitor Varactor Diode RF Switch Inductor Transformer Transmission line Resonator or filter

Polysilicon Interdigitated PN Junction

Implanted MOS MOS

Thin Film MIM MEMS Schottky

© 2006 by Taylor & Francis Group, LLC

PN MOS-FET PIN; MEMS Spiral Shielded Spiral Spiral: stacked; bifilar; nested Microstrip; coplanar waveguide LC; SAW

MEMS; FM Core FM Core Micromachined MEMS; BAW

Passive Components

3.4-251

process, the range of such ‘‘free’’ passive components can greatly be expanded, as Table 3.4.1 shows. Nevertheless, there are special passives that require additional process steps or materials. They are adopted if more economic solutions are not satisfactory to the RF circuit designer or if they are instrumental in overcoming a design bottleneck.

3.4.2 Resistors and Capacitors Resistors and capacitors have been a part of silicon fabrication processes for a long time. Resistors are used in bipolar circuits for dc biasing purposes and metal–oxide–silicon (MOS) capacitors are freely available in CMOS and BiCMOS processes. Resistors can be integrated in three basic forms, i.e., as an implanted or diffused component, as a polysilicon resistor, and as a thin-film metal element (Table 3.4.1). In bipolar processes sheet resistances ranging from 10 to 10,000 V/sq. can be realized by exploiting either the diffused regions (buried layer, intrinsic base) or the polysilicon films (extrinsic base, emitter). In BiCMOS processes, the well and channel stopper diffusions can also be used in order to cover the sheet resistance range from 100 to 1000 V/sq. Implanted and diffused resistors, however, are not well suited for RF circuit design because the junction isolation leads to a considerably large-shunt capacitance that is bias dependent. Polysilicon resistors work better in that respect since they are separated from the silicon substrate by the field oxide, leading to a much smaller shunt capacitance. The sheet resistance of doped polysilicon, however, varies with the polygrain structure and the dopant distribution between grains and grain boundaries. This results in a typically much larger statistical variation of the sheet resistance compared to implanted or diffused resistors [5]. The best results can be achieved with metal thin-film resistors that are imbedded into the multilevel interconnect stack [6] by, however, investing an extra masks layer and additional process steps (Table 3.4.1). The good electrical isolation of poly and metal thin-film resistors from the silicon substrate, however, causes that such resistors are also thermally isolated due to the poor thermal conductivity of the SiO2. A small temperature coefficient is therefore another aspect in selecting the optimum resistor structure for RF applications. Capacitors can be integrated as an interdigitated metal structure, an MOS structure, or a metal– insulator–metal (MIM) structure. The interdigitated capacitor is adopted from III-V monolithic microwave integrated circuit (MMIC) technology, where it is useful since often only one interconnect layer is available. Since this is not an issue in silicon technology and because the capacitance or area is very small in comparison to that of the MOS and the MIM capacitors, the interdigitated capacitor is not used in SiGe MMICs. MOS capacitors have the same disadvantage as the mentioned implanted or diffused resistors, i.e., a considerable portion of the RF signal flows through the silicon substrate. Also, one terminal is built in silicon causing a relatively high series resistance, thus lowering the quality of the RF capacitor. Nevertheless, MOS capacitors have the comparably highest capacitance/area so that they are used in special applications, such as for dc blocking. The most favorable RF capacitor is the MIM structure since both terminals are built in metal and the structure has good oxide isolation from the substrate. A lumped-element model of an MIM capacitor is shown in Figure 3.4.2. The figure-of-merit of an RF capacitor is the quality factor (Q), which is defined as the ratio of the stored and the dissipated energies, i.e., QC ¼
im(Z)/re(Z), with Z the impedance of the component. It is obvious that the Q-factor will become lower as the frequency is increased, because the impedances of the lumped capacitors drop with frequency so that an increasing fraction of the total energy applies to dissipation at the resistors (see Figure 3.4.2). A second concern is self-resonance. The resonance frequency (fSR) is set by the parasitic series inductance LS and (primarily) CP and should be sufficiently larger than the desired operating frequency. Apart from the types and thicknesses of metal and dielectric layers available with a particular fabrication process layout optimization is effective in optimizing for Q and fSR [7]. Figure 3.4.3 illustrates that a finger layout with a high aspect ratio leads to both an increased Q and a higher fSR. A multifinger layout rather than one single finger can be used to best fit the MIM capacitor into the RF circuit layout. Another issue, besides layout optimization, is the accurate compact modeling of the capacitor. Figure 3.4.4 shows an example of the optimum 1.3-pF MIM capacitor layout from Figure 3.4.3, which is well applicable up to 10 GHz. The compact model with parameters shown in the insert of

© 2006 by Taylor & Francis Group, LLC

3.4-252

The Silicon Heterostructure Handbook

CP

P1

LS COx

CB

P2

RS RP

RB

COx RB

CB

Sub*

FIGURE 3.4.2 Compact model of an integrated capacitor. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) 100

MIM Capacitors: Areas from 10⫻194 mm2 to 80⫻24.5 mm2

4 3

80

Finger ratio increase

Q

60 40

2 1

Quality factor

Capacitance (pF)

5

20

C 0

0 0

2

4

6

8

10

Frequency (GHz)

FIGURE 3.4.3 Measured capacitances and quality factors of multifinger MIM capacitors with varied finger aspect ratios. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

Figure 3.4.4 is derived from the general MIM capacitor model in Figure 3.4.2 with simplifications by neglecting RP and CB.

3.4.3 Inductors and Transformers Inductors on Silicon Substrates Design and Compact Modeling Inductors, in contrast to capacitors and resistors, are fairly new passive components in silicon technology. In 1990, Nguyen and Meyer [8] were the first to place a spiral coil (Figure 3.4.5) over a conductive, and thus lossy, silicon substrate. The Q of a spiral inductor (QL ¼ þim(Z)/re(Z)) hardly reached Q ¼ 5 in the early attempts in spite of extensive knowledge in spiral inductor design from III-V MMICs and PCB implementations. As rough guidelines, the ratio of outer (R) to inner (Ri) coil radius should be R/Ri ¼ 5 for a maximum Q value and the maximum radius should not exceed l/60 to avoid distributed effects [3]. The fact that in silicon technology the inductor coil is placed over a conductive substrate is the main cause of the difficulties to reach appropriate Qs. The primary parameter set to define a spiral inductor on silicon (without the underpath) thus includes the conductor width (W) and space (S), the number of turns (N), the coil radius (R), the metal thickness (TM) and resistivity (rM), the thickness (TOx) and permittivity («Ox) of the dielectric layer between coil and silicon, and the resistivity (rSi), permittivity («Si), and thickness (TSi) of the silicon substrate (Figure 3.4.5). In addition, the specifica-

© 2006 by Taylor & Francis Group, LLC

3.4-253

Passive Components

100

10 0.04 nH

MIM-Cap

0.7 Ω

1.37 pF

Capacitance (pF)

6

0.026 pF 15 Ω

60

Sub

40

Q 4

C

2

Quality factor

80

8

20

0

0 2

0

4

6

8

10

Frequency (GHz)

FIGURE 3.4.4 Measured and modeled frequency dependence of capacitance and quality factor of an optimized multifinger MIM capacitor (model with parameters in inset). (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) N rM

eOx TM R TOx

TSi

W

S

rSi, e Si

FIGURE 3.4.5 Cross section of a spiral inductor on silicon, defined by the width (W) and space (S) of the metal conductor, the number of turns (N), the outer radius of the coil (R), the metal resistivity (rM), the metal thickness (TM), the distance of the spiral coil from the silicon substrate (TOx), the oxide permittivity («Ox), the thickness of the silicon substrate (TSi), and the permittivity («Si) and resistivity (rSi) of the silicon. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

tions of the underpath that connects the inner coil terminal to the outside have to be considered, though play a minor role in most designs. The limitation in Q is a result of ohmic losses and parasitic capacitances in the coil and in the substrate, as illustrated in the compact model in Figure 3.4.6. There, the electrical characteristics of the spiral coil are represented by LS*, RS, and CP. The dielectric isolation between coil and substrate is modeled by COx, and the substrate is described by RB and CB. The elements LE, RE, and M are used to illustrate the effect of eddy currents in the substrate, which become noticeable only for a high silicon conductivity. The resistor RSub describes the effect of a planar substrate contact on the inductor characteristics. First, we discuss the situation for RSub ! 1 (no

© 2006 by Taylor & Francis Group, LLC

3.4-254

The Silicon Heterostructure Handbook

CP POut COx RSub CB

PIn

R LS*=LS−M S M

COx

LE−M RE RShield

RB

RB

CB

Sub Sub*

FIGURE 3.4.6 Compact model of an integrated inductor. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.) 25

60 Qmax

sse

rate

15

los

ses

10

f(Qmax)

5

L

10 0 0

Quality factor

bst

il lo

30 20

20 Su

s

40

Co

Inductance (nH)

50

1

2 3 Frequency (GHz)

4

5

0

FIGURE 3.4.7 Inductance and quality factor of an integrated inductor versus frequency. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

substrate contact) and RE ! 1 (no substrate eddy currents, i.e., M ¼ 0; LS* ¼ LS). If a low-frequency bias is applied between the inductor terminals (POut, PIn in Figure 3.4.6) the RF signal primarily passes through the inductance LS and the resistance RS, because the impedance vLS is small and the impedances 1/vCP and 1/vCOx are large. The quality factor increases then as Q ¼ vLS/RS, which is shown in Figure 3.4.7. With increasing frequency a larger fraction of the RF signal passes through the substrate since vLS becomes larger, 1/vCOx becomes smaller, and because COx >> CP (TOx << R). As a result, a maximum Q-factor (Qmax) appears at a particular frequency f (Qmax), as shown in Figure 3.4.7. It is obvious that the inductor design should aim for optimizing Qmax at the operating frequency, i.e., f0 ¼ f (Qmax), through tailoring coil and substrate losses. Furthermore, self-resonance should occur sufficiently above f (Qmax). This can be achieved by preventing from resonance via COx so that the much smaller CP leads to a high fSR, as achieved for the sample 10-nH inductor in Figure 3.4.7. The metal losses in the spiral coil can be lowered by shunting several layers of the multilevel interconnects together to arrive at an effectively thicker conductor, as first shown by Soyuer et al. [9, 10]. Local thickening of the top metal layer is another economic means to reduce the coil losses [11]. Other design concepts address the skin effect that leads to an increased coil resistance at increased frequency. While the skin effect from the magnetic field caused by the current through a conductor itself cannot significantly be reduced, the skin effect from a magnetic field caused by current flow through a neighboring conductor can well be minimized. The latter effect is experienced as crowding of the current to the conductor edges. That means that at high RF a large conductor width (W) may not be

© 2006 by Taylor & Francis Group, LLC

3.4-255

Passive Components

as effective as a sufficient conductor spacing (S). Furthermore, eddy currents can be caused in particular in the inner metal turns so that hollow coils [12] or smaller conductor width at the inner turns [13] can result in reduced losses. The coil design also affects the interturn capacitance (CP1) and the capacitance between spiral coil and underpath (CP2), which both contribute to CP ¼ CP1 þ CP2 that affects the fSR of the inductor. The coil design discussed so far has been restricted to a spiral coil consisting of a continuous metal conductor at the same interconnect layer. By alternating between interconnect layers less current crowding [14] and a higher resonance frequency [15] can be achieved particularly for large inductances. Also, multilayer inductor structures, providing higher inductance/area figures then become feasible [16, 17]. Substrate Effects and Shields The substrate resistivity can have distinct effects on the inductor characteristics, as illustrated in Figure 3.4.8 for a simulated 2-nH inductor, varying only the silicon resistivity. For resistivities above 10 V cm both Qmax and f (Qmax) increase steadily toward higher resistivity. This so-called ‘‘inductor mode’’ of operation relates to what we had discussed above and the sample inductor in Figure 3.4.7. In the range of 0.1 to 10 V cm the component operates in the ‘‘resonator mode’’ because then self-resonance occurs via the substrate, i.e., COx. With COx >> CP, fSR shows a pronounced decay, which causes that fSR >> f (Qmax) is no longer valid and the component operates as a resonator rather than an inductor. That

Resonator mode regime

Eddy current regime

Inductor mode regime

x 5

L (Q max) (nH)

(a)

20

Qmax

10

f(Qmax)

0

0

6

25

5

20

4

fSR

15 L(Q max)

3

10

2

5

1 0 0.001 (b)

fSR (GHz)

Qmax

10

f (Qmax) (GHz)

30

15

0 0.1

10

1000

Silicon resistivity (Ω-cm)

FIGURE 3.4.8 Maximum quality factor (Qmax), frequency at Qmax (f (Qmax)), inductance (L(Qmax)), and resonant frequency (fSR) of an integrated inductor as a function of substrate resistivity with indication of the three characteristic modes of operation. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.4-256

The Silicon Heterostructure Handbook

means, however, that the design direction becomes distinctly different. Now, not an increase but a reduction in substrate resistivity leads to a higher Qmax. The Q of the resonator namely depends on both the qualities of the lossy inductor coil (QL ¼ vLS/RS) and the lossy oxide capacitor (QC ¼ 1/vRBCOx). The QC is increased by lowering the substrate resistivity and thus RB. It can be seen from Figure 3.4.8 that, surprisingly, somewhat higher Qmax values can be achieved in comparison to a 10 V cm substrate resistivity, particularly if eddy currents in the substrate can be suppressed. (Note that these three modes of operation of a spiral coil structure are closely related, but not identical, to the TEM, slow wave, and eddy current modes of a microstrip as described by Hasegawa et al. [18].) While eddy currents cannot, or at least not easily, be suppressed in the low-resistivity silicon, operation in resonator mode with suppressed eddy currents can be enforced by inserting a patterned ground shield in between the spiral coil and the silicon substrate [19]. Figure 3.4.9 shows the Qmax and the fSR of the 2-nH inductor (from Figure 3.4.8) with a patterned ground and the shield resistivity as the only parameter, showing that Qmax can be raised by 50% while sacrificing fSR. The effect of a patterned ground shield can be modeled by the resistor RShield in the compact model of Figure 3.4.6. Inductor Optimization The optimization of inductors on silicon is extensively discussed in a review paper by Burghartz and Rejaei [20]. In Figure 3.4.10, the Qmax values achievable for a wide range of inductances are shown for a conventional Al metallization and substrate resistivity for thick Cu interconnects in combination with high-resistivity silicon (HRS). There is a general trend that large inductance values combine typically with considerably lower Qs than small inductances. This is a result of the larger area needed to accomplish large inductances and the consequently lower impedance of the substrate leakage path (COx, CB, RB in Figure 3.4.6). Another consequence is that with larger inductance values Qmax appears at a lower frequency f (Qmax). This does not appear to be an issue in RF circuit design since at higher frequencies the required inductance values are smaller and the Qs needed are larger. The last feature from Figure 3.4.6 to be discussed is the effect of a substrate contact. Clearly, a uniform ground potential underneath the inductor coil would provide the best possible electrical symmetry of the component, except for the small geometrical asymmetry of the coil itself [21]. In silicon technology, however, only planar substrate contacts can be used to bias the silicon substrate. It has been shown that, if such a planar substrate contact is positioned close to the coil, the inductor would become electrically

40

16 Eddy currents QMax No eddy currents

30 fSR

8

20

4

10

fSR (GHz)

12 Qmax

rSi = 10 Ω-cm

rShield 0 0.0001

0.01

1

100

0 10,000

Shield resistivity (Ω-cm)

FIGURE 3.4.9 Maximum quality factor (Qmax) and resonant frequency (fSR) of an integrated inductor with patterned ground shield as a function of the resistivity of the shield metal. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.4-257

Passive Components

Maximum quality factor

100 SAM

4 µm Cu+ 3 kΩ-cm Si

10

1µm Al+ 5 Ω-cm Si 1 1

10 Inductance (nH)

100

FIGURE 3.4.10 Maximum quality factor (Qmax) versus inductance of spiral inductors built in a conventional aluminum interconnect process or with copper metallization on a high-resistivity silicon substrate. (From JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

asymmetric. The substrate contact thus has to be considered in the circuit layout [22]. Only an RF ground plane underneath the coil can eliminate this asymmetry, provided that the ground plane is spaced away sufficiently to prevent from eddy current effects [23, 24]. That sensitivity of the inductor characteristics to eddy currents in nearby metal features also prevents one from placing other circuit components inside the large spiral coil or from building the coil over other circuitry [25], except if micromachining techniques are adopted (Section 3.4.6). Accurate modeling of the spiral inductor structure is another important task. While the compact model in Figure 3.4.6 is already sufficiently accurate, it has the restriction of being nonpredictive. An extensive review of predictive inductor models [26–29] is included in Ref. [30].

Integrated Transformers Transformers have been used in RF circuits since the early days of telegraphy. Conceptually, a transformer consists of two spiral coils that are brought in close proximity to achieve mutual magnetic coupling. Figure 3.4.11 shows the three generic types of transformers that are conceivable, i.e., the stacked (Finlay) type, the bifilar (Shibata resp. Frlan) type, and the nested coil type [31, 32]. The mutual coupling, which is a first indication of quality of a transformer, is higher for the stacked coils than that of the bifilar structure, which again is higher than that of the nested coils [32]. The strong mutual coupling, however, also results in a large parasitic capacitance between the coils, which affects the bandwidth of the transformer by making the mutual coupling of the coils partly capacitive. The maximum available gain (Gmax), as used for RF transistors [3], is a useful figure-of-merit of a transformer [32], since it is independent of the port impedances. A good transformer should obviously have both high Gmax and large bandwidth. In that respect, the stacked coils provide the best results in comparison, followed by the bifilar and the nested types [33]. Stacked coils also consume minimum chip area but require three interconnect layers instead of two needed to fabricate the other types. Obviously, if capacitive coupling between the coils has a detrimental effect on the transformer Gmax and bandwidth, substrate effects will play a considerable role and will degrade the transformer in both aspects [32]. Substrate effects are minimum for the stacked coil configuration. Interestingly, a patterned metal ground shield can provide a slightly increased Gmax and bandwidth [32]. The bifilar coil type is most suitable for the design of multifilament, balun, and symmetric transformers, as extensively discussed in a review paper by Long [31] and in a book by Niknejad and Meyer [34].

© 2006 by Taylor & Francis Group, LLC

3.4-258

The Silicon Heterostructure Handbook

Bifilar coils (Shibata)

Stacked coils (Finlay)

Nested coils Bifilar coils (Frlan)

FIGURE 3.4.11 Plan view sketches of generic transformer structures. (From JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. With permission.)

3.4.4 Transmission Lines At frequencies beyond about 30 GHz inductances and capacitances have to be integrated as distributed elements (Figure 3.4.1). This requires the fabrication of transmission lines on a lossy silicon substrate either as a CPW or as a microstrip. Both types of lines have been used on PCB or in III–V MMICs. In silicon technology, however, CPWs suffer from considerable losses in the conductive silicon substrate and microstrips are difficult to integrate due to lack of a through-substrate via process in conventional silicon technology. During the past decade these issues have been circumvented and addressed, respectively, by building microstrips in the multilevel interconnects away from the substrate [35] and by fabricating CPWs over HRS [36]. The small vertical spacing of signal and ground planes of microstrips built in the multilevel interconnects leads to a comparably narrow required width of the signal line, thus raising ohmic losses and the overall attenuation of the line. A wider signal line for reduced losses is feasible if the ground plane is integrated into the silicon substrate. This, however, requires micromachining techniques [37] (see also Section 3.4.6). In that case, as for the CPWs, HRS substrates have to be used to suppress the losses in the silicon. Then, particularly for the CPW, the passivation of the silicon near the Si–SiO2 interface is crucial to be able to minimize those losses [38]. The attenuation figures achieved for transmission lines on silicon substrates are in the range of 2 to 5 dB/cm at 10 GHz, depending on the metal type and thickness and on the silicon resistivity. With the passivation the attenuation can be about tenfold improved.

3.4.5 Diodes and Switches There are several types of diodes that can be applied in RF and microwave applications. Varactors are used, for example, in voltage-controlled oscillators (VCO) and can be built as pn-junction [7] and MOScapacitor type components [39]. The pn-junction varactor can directly be derived from the collector– base junction structure of the bipolar transistor. The component can be modeled by using the scheme in Figure 3.4.2. The challenge in integrating a varactor on a silicon substrate is to achieve a maximum capacitance/area with minimum parasitic resistances and inductances of the terminals and the internal metallization, leading to a multifinger structure as the optimum layout of the component [7]. For

© 2006 by Taylor & Francis Group, LLC

3.4-259

Passive Components

60

5 A= 2 ⫻ 15 ⫻ 27.75 µm2

4 Capacitance (pF)

Varactor (pn junction): 50 40

3 30

Bias increase

2

C 20

1

Quality factor

Q

10

0 0

2

4 6 Frequency (GHz)

8

0 10

FIGURE 3.4.12 Measured capacitances and quality factors of multifinger pn-junction MIM capacitors with varied reverse bias. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

varactors used in the 900 MHz to 2.4 GHz range the multifinger design provides Qs in the range of 20 to 50 (Figure 3.4.12), which is quite sufficient considering the limited Qs of the inductors in the LC tank of the VCO. Diodes, more specifically p–i–n diodes, are used in RF switches, particularly the transmit– receive (T–R) switch at the antenna of the RF transceiver [40]. A p–i–n diode works as a bias-controlled resistor with excellent linearity and distortion and has also been applied in microwave circuits to amplitude modulation, attenuation, and signal leveling. In addition to their use in RF switches, they also make excellent phase shifters and limiters [3]. The integration of p–i–n diodes in silicon processes, however, is difficult since they are typically built as vertical devices by exploiting the entire wafer thickness. Therefore, as the MESFET switch in III–V technology, it is possible to consider MOSFET switches in silicon technology, but they have an inferior insertion loss and isolation and they consume more chip area compared to their III–V contenders [41]. The third type of switch device that is considered for silicon technology is the MEMS switch [42], which appears to be only a technological option in applications where the p–i–n and MOS switches cannot meet the required specifications. A third type of diode that is well integratable in silicon technology is the Schottky rectifier, which can reach cutoff frequencies well in excess of 100 GHz [3, 43].

3.4.6 Special Passive Components Emerging Passives With the trend toward fully monolithic RF transceivers novel materials and structures are now introduced to silicon technology. Introducing them as an addition to the core device integration process is a favorable concept for economic reasons [44]. Micromachining and MEMS can be used to greatly increase the quality of passive components [37, 45, 46] or to integrate large components above [46] or below the active devices into the bulk silicon substrate [37]. Micromachining can also be used to establish an RF ground plane in silicon process technology [37] (see ‘‘Substrate Effects and Shields’’). The enhancement in component quality is quite pronounced in mechanical resonators [47], mechanically variable capacitors [48], and RF MEMS switches (Section 3.4.5). Ferromagnetic thin films can be instrumental in reducing the size of inductors and transformers and to realize novel-integrated RF passive components [49, 50]. The integration of bulk-acoustic wave filters

© 2006 by Taylor & Francis Group, LLC

3.4-260

The Silicon Heterostructure Handbook

[51] and tunable passives becomes possible by using ferroelectric thin films on silicon [52]. In this way, other microwave components known from the hybrid technologies may be brought to silicon technology by exploiting integratable ferromagnetic and ferroelectric thin films [49]. On-chip antenna is another passive component that may gain significance in the emerging fields of integrated microwave sensors [53], unobtrusive radio devices [54], and for intrachip [55] and chip–chip signal transmission [56].

Suppression of Parasitic Effects In addition to the desired passive components there are parasitic effects that affect the characteristics of an integrated RF circuit. RF currents through the electrically conducting silicon substrate [37], electromagnetic coupling between integrated inductors and to the package [23, 25], and thermal coupling through the silicon [57] are such parasitic effects that are undesirable since they are difficult to model and are detrimental to the circuit performance. Such parasitic effects, therefore, have to be carefully considered in the circuit layout [58]. Isolation techniques available with conventional silicon process technology, however, are not sufficiently effective at RF and microwaves [59]. Novel structures to block or to ground such crosstalk signals between RF circuit elements are therefore required. Availability of an RF ground plane with a via connection to the wafer frontside is, therefore, a valuable addition to any RF silicon integration process (see also Section 3.4.4) [37]. In addition to the unwanted crosstalk signals to an RF ground, crosstalk can also be lowered to some extent by increasing the silicon substrate resistivity and the spacing between source and drain of the parasitic RF signals. Overly, high substrate resistivity, however, does not provide any benefit as far as the crosstalk goes, since then the substrate characteristics are fully capacitive and in TEM mode [18, 60]. Then, local replacement of the silicon by a low-permittivity material will have the effect of a virtual increase of the length of the crosstalk path. This can, for example, be achieved by etching trenches through the entire substrate [37].

3.4.7 Summary In this chapter, we have given a broad overview of the passive components and devices required for RF silicon integration processes. The discussion has been restricted to passives that are integrated on the chip, but with highlighting the criteria that favor the integration of passive components over off-chip or in-package solutions. The effect of parasitics on the quality and the characteristics of passive components, as well as on the coupling between passives, have been addressed as well. Among the passive components and devices, the spiral inductor on silicon has particularly been highlighted in the discussions, because this component is still fairly new to silicon technology, it limits the performance and power consumption of RF circuits, and it consumes a considerable fraction of the costly chip area. The discussion of other passive components and devices, as well as of parasitic effects, has been kept brief but combined with an extensive reference list. All in all, it can be stated that passive components and devices are an integral, if not dominant, part of monolithic RF silicon technology.

Acknowledgments The author would like to thank his colleagues at the Laboratory of High-Frequency Technology and Components (HiTeC) at DIMES, TU Delft, and his former colleagues at IBM Research and IBM Microelectronics for the many stimulating discussions on aspects of RF silicon technology. This applies particularly to Dr. Behzad Rejaei (HiTeC), Dr. Mehmet Soyuer (IBM), and Dr. Keith Jenkins (IBM).

References 1. LE Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip.’’ IEEE Transactions on Electron Devices 50:683–699, 2003.

© 2006 by Taylor & Francis Group, LLC

Passive Components

3.4-261

2. JN Burghartz. Silicon RF technology — The two generic approaches. Proceedings of the European Solid-State Device Research Conference (ESSDERC), 1997, pp. 143–153. 3. I Bahl and P Barthia. Microwave Solid State Circuit Design. New York, NY: John Wiley & Sons, 1988. 4. JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Integrated RF passive components — discrete vs. distributed. Proceedings of the Device Research Conference, 2001, pp. 113–114. 5. A Schuppen, H Dietrich, S Gerlach, H Hohnemann, J Arndt, U Seller, R Gotzfried, U Erben, and H Schumacher. SiGe-technology and components for mobile communication systems. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1996, pp.130–133. 6. R Henderson, P Zurcher, A Duvallet, C Happ, M Petras, M Raymond, T Remmel, D Roberts, B Steimle, S Straub, T Sparks, M Tarabbia, and M Miller. Tantalum nitride thin film resistors for integration into copper metallization based RF-CMOS and BiCMOS technology platforms. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2001, pp. 71–74. 7. JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. 8. NM Nguyen and RG Meyer. IC-compatible inductors and LC passive filters. IEEE Journal of SolidState Circuits 25:1028–1031, 1990. 9. M Soyuer, JN Burghartz, KA Jenkins, S Ponnapalli, JF Ewen, and WE Pence. Multilevel monolithic inductors in silicon technology. Electronics Letters 31:359–360, 1995. 10. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 11. JN Burghartz and B Rejaei. Saddle add-on metallization for RF-IC technology. IEEE Transactions on Electron Devices 51:460–466, 2004. 12. J Crols, P Kinget, J Craninckx, and M Steyaert. An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz. Digest of Technical Papers of the Symposium on VLSI Circuits, 1996, pp. 28–29. 13. JM Lopez-Villegas, J Samitier, C Cane, and P Losantos. Improvement of the quality factor of RF integrated inductors by layout optimization. Technical Digest of the Radio Frequency Integrated Circuits (RFIC) Symposium, 1998, pp. 169–172. 14. LF Tiemeijer, D Leenaerts, N Pavlovic, and RJ Havens. Record Q spiral inductors in standard CMOS. Technical Digest of the International Electron Devices Meeting (IEDM), 2001, pp. 949–951. 15. HB Erzgra¨ber, M Pierschel, GG Fischer, T Grabolla, and A Wolff. High performance integrated spiral inductors based on a minimum AC difference voltage principle. Digest of Technical Papers of the Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 71–74. 16. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors Using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 17. RB Merrill, TW Lee, Y Hong, R Rasmussen, and LA Moberly. Optimization of high Q integrated inductors for multi-level metal CMOS. Technical Digest of the IEEE International Electron Devices Meeting, 1995, pp. 983–986. 18. H Hasegawa, F Mieko, and Y Hisayoshi. Properties of microstrip line on Si–SiO2 system. IEEE Transactions on Microwave Theory and Techniques 19:869–881, 1971. 19. CP Yue and SS Wong. On-chip spiral inductors with patterned ground shields for Si-based RF ICs. IEEE Journal of Solid-State Circuits 33:743–752, 1998. 20. JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. 21. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. 22. JN Burghartz, AE Ruehli, KA Jenkins, M Soyuer, and D Nguyen-Ngoc. Novel substrate contact structure for high-Q silicon-integrated spiral inductors. Technical Digest of the IEEE International Electron Devices Meeting, 1997, pp. 55–58.

© 2006 by Taylor & Francis Group, LLC

3.4-262

The Silicon Heterostructure Handbook

23. JN Burghartz. Progress in RF inductors on silicon-understanding substrate losses. Technical Digest of the International Electron Devices Meeting, 1998, pp. 523–526. 24. KT Ng, NP Pham, PM Sarro, B Rejaei, and JN Burghartz. Characterization of a bulk-micromachined post-process module for silicon RF technology. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 99–102. 25. JN Burghartz, DC Edelstein, M Soyuer, HA Ainspan, and KA Jenkins. RF circuit design aspects of spiral inductors on silicon. IEEE Journal of Solid-State Circuits 33:2028–2034, 1998. 26. JR Long and MA Copeland. Modeling of monolithic inductors and transformers for silicon RFIC design. In Microwave Symposium Digest (Technologies for Wireless Applications), 1995, pp. 129–134. 27. CP Yue, C Ryu, J Lau, TH Lee, and SS Wong. A physical model for planar spiral inductors on silicon. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1996, pp. 155–158. 28. AM Niknejad and RG Meyer. Analysis, design, and optimization of spiral inductors and transformers for Si RF Ics. IEEE Journal of Solid-State Circuits 33:1470–1481, 1998. 29. B Rejaei, JL Tauritz, and P Snoeij. A predictive model for Si-based circular spiral inductors. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 1998, pp. 148–154. 30. JN Burghartz. Spiral inductors on silicon — Status and trends. International Journal of RF and Microwave Computer-Aided Engineering 8:422–432, 1998. 31. JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. 32. KT Ng, B Rejaei, and JN Burghartz. Substrate effects in monolithic RF transformers. IEEE Transactions on Microwave Theory and Techniques 50:377–383, 2002. 33. KT Ng, B Rejaei, TR deKruiff, M Soyuer, and JN Burghartz. Analysis of generic spiral–coil RF transformers on silicon. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp.103–107. 34. AM Niknejad and RF Meyer. Design, Simulation, and Applications of Inductors and Transformers for Si RF ICs. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2000. 35. DC Laney, LE Larson, P Chan, J Malinowski, D Harame, S Subbanna, R Volant, and M Case. Microwave transformers, inductors and transmission lines implemented in an Si/SiGe HBT process. IEEE Transactions on Microwave Theory and Techniques 49:1507–1510, 2001. 36. HH Meinel. Millimeter-wave technology advances since 1985 and future trends. IEEE Transactions on Microwave Theory and Techniques 39:759–767, 1991. 37. NP Pham, PM Sarro, KT Ng, and JN Burghartz. IC-compatible two-level bulk micromachining process module for RF silicon technology. IEEE Transactions on Electron Devices 48:1756–1764, 2001. 38. B Rong, JN Burghartz, LK Nanver, B Rejaei, and M vanderZwan. Surface-passivated high-resistivity silicon substrates for RFICs. IEEE Electron Device Letters 25:176–178, 2004. 39. WMY Wong, PS Hui, C Zhiheng, S Keqiang, J Lau, and PCH Chan. A wide tuning range gated varactor. IEEE Journal of Solid-State Circuits 35:773–779, 2000. 40. RH Caverly. RF technique for determining ambipolar carrier lifetime in PIN RF switching diodes. Electronics Letters 34:2277–2278, 1998. 41. RH Caverly. Linear and nonlinear characteristics of the silicon CMOS monolithic 50-V microwave and RF control element. IEEE Journal of Solid-State Circuits 34:124–126, 1999. 42. GM Rebeiz. RF MEMS: theory, design, and technology. New York, NY: John Wiley & Sons, 2003. 43. KM Strohm, J Buechler, and E Kasper. SIMMWIC rectennas on high-resistivity silicon and CMOS compatibility. IEEE Transactions on Microwave Theory and Techniques 46:669–676, 1998. 44. JN Burghartz, M Bartek, B Rejaei, PM Sarro, A Polyakov, NP Pham, E Boullaard, and KT Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2002, pp. 17–23.

© 2006 by Taylor & Francis Group, LLC

Passive Components

3.4-263

45. KJ Herrick, JG Yook, and LPB Katehi. Microtechnology in the development of three-dimensional circuits. IEEE Transactions on Microwave Theory and Techniques 46:1832–1844, 1998. 46. JB Yoon, YS Choi, BI Kim Y Eo, and E Yoon. CMOS-compatible surface-micromachined suspendedspiral inductors for multi-GHz silicon RF Ics. Electron Device Letters, IEEE 23:591–593, 2002. 47. JR Clark, WT Hsu, and CT Nguyen. High-Q VHF micromechanical contour-mode disk resonators. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2000, pp. 493–496. 48. M Bakri-Kassem and RR Mansour. Two movable-plate nitride-loaded MEMS variable capacitor. IEEE Transactions on Microwave Theory and Techniques 52:831–837, 2004. 49. B Rejaei, M Vroubel, Y Zhuang, and JN Burghartz. Assessment of ferromagnetic integrated inductors for Si-technology. Digest of Papers of the topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 100–103. 50. MG Allen. MEMS technology for the fabrication of RF magnetic components. IEEE International Magnetics Conference, 2003, pp. FC-05. 51. M Ylilammi, J Ella, M Partanen, and J Kaitila. Thin film bulk acoustic wave filter. IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control 49:535–539, 2002. 52. KA Jose, H Yoon, KJ Vinoy, P Sharma, VK Varadan, and V Varadan. Low voltage tunable capacitors for RF MEM filters and antenna applications. Digest of the International Symposium on Antennas and Propagation, Vol. 3, 2001, pp. 670–673. 53. P Russer. Si and SiGe millimeter-wave integrated circuits. IEEE Transactions on Microwave Theory and Techniques 46:590–603, 1998. 54. E Aarts. Ambient intelligence: A multimedia perspective. IEEE Multimedia 11:12–19, 2004. 55. BA Floyd, H Chih-Ming Hung, KK O. Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE Journal of Solid-State Circuits 37:543–552, 2002. 56. JJ Lin, L Gao, A Sugavanam, X Guo, R Li, JE Brewer, and KK O. Integrated antennas on silicon substrates for communication over free space. IEEE Electron Device Letters 25:196–198, 2004. 57. BM Tenbroek, MSL Lee, W Redman-White, RJT Bunyan, and MJ Uren. Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE Journal of Solid-State Circuits 33:1037– 1046, 1998. 58. T Blalack, Y Leclercq, and CP Yue. On-chip RF isolation techniques. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, 2002, pp. 205–211. 59. KA Joardar. A simple approach to modeling cross-talk in integrated circuits. IEEE Journal of SolidState Circuits 29:1212–1219, 1994. 60. M Pfost, HM Rein, and T Holzwarth. Modeling substrate effects in the design of high-speed Si-bipolar Ics. IEEE Journal of Solid-State Circuits 31:1493–1501, 1996.

© 2006 by Taylor & Francis Group, LLC

3.5 Industry Examples at the State-of-the-Art: IBM

Alvin J. Joseph and James S. Dunn IBM Microelectronics

3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6

Introduction............................................................... 3.5-265 BiCMOS Process Integration ................................... 3.5-265 The SiGe HBT — Key Technology Elements.......... 3.5-269 Electrical Performance .............................................. 3.5-270 Manufacturability ...................................................... 3.5-276 Summary .................................................................... 3.5-280

3.5.1 Introduction The general market acceptance of SiGe BiCMOS technologies can be attributed to the ability to address the product performance at a very competitive cost by integrating high-performance SiGe HBTs, with state-of-the-art CMOS, and high-quality passives. SiGe HBTs have shown to be highly reliable even under extreme stress conditions [1, 2] and give superior yields compared to other compound semiconductor technologies (e.g., GaAs). It is not surprising, therefore, to see SiGe BiCMOS technologies in mass production that range in various applications, such as wireless, storage, and instrumentation [3, 4]. SiGe BiCMOS technologies offer the flexibility to be optimized based on the specific market applications. For example, performance focus applications such as wired, automotive, and instrumentation require ultrahigh-performance SiGe HBTs. Integrating a simplified low-cost SiGe HBT is the focus, however, for consumer applications such as wireless and storage. Therefore, a ‘‘one size fits all’’ approach for technology optimization will not be optimal to address various market segments due to significant tradeoffs one has to make on either performance or cost. The IBM SiGe BiCMOS technology roadmap addresses these wide-ranging applications by offering two flavors of SiGe HBTs. State-of-the-art examples of IBM SiGe BiCMOS technologies at 0.13 mm CMOS node will be discussed in detail in this section. SiGe BiCMOS 8HP is a technology which features a 200/275 GHz (fT/fmax) SiGe HBT with passives and back-end-of-the-line (BEOL) metallurgy tailored for applications in the 77 GHz range. Technology optimization in this case centers around the performance of the SiGe HBT. SiGe BiCMOS 8WL technology features a 100/200 GHz (fT/fmax) SiGe HBT with 0.5 dB minimum noise figure (NFMIN) at 10 GHz with wide range of active and passive devices that support cost-sensitive consumer applications. In this case, the technology optimization focus shifts to reducing process complexity (or cost) while maintaining adequate SiGe HBT performance.

3.5.2 BiCMOS Process Integration The state-of-the-art BiCMOS process integration approach falls into the category of a base-after-gate (BAG) method, where the base of the SiGe HBT is built after the bulk of the CMOS processing is completed 3.5-265 © 2006 by Taylor & Francis Group, LLC

3.5-266

The Silicon Heterostructure Handbook

BiCMOS 8HP 0.13 µm CMOS Backbone

Shallow trench

BiCMOS 8WL

Bipolar

Subcoll., Nepi, Deep Trench

0.13 µm CMOS Backbone

Shallow trench

Coll. reachthru Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

S/D implant, anneal, Resistor salicide block

Base window, collector pedestal, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

Bipolar

Subcollector I/I Base window, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

S/D Implant, anneal, Resistor salicide block Custom trench

Salicide and contacts Salicide and contacts

Metal interconnect Custom analog metals

Metal interconnect

Custom analog metals

FIGURE 3.5.1 Process flow comparing both BiCMOS 8HP and BiCMOS 8WL in a 0.13 mm CMOS backbone.

[5]. This approach is chosen to minimize the thermal budget for the SiGe HBT. Figure 3.5.1 shows the integration flows utilized in the 0.13 mm IBM SiGe BiCMOS processes. Both 8HP and 8WL process flow use the 0.13 mm CMOS backbone with the addition of bipolar and custom BEOL analog metals. Process flows deviate between 8HP and 8WL due to the tradeoff associated with the bipolar performance. The process flow starts with the formation of the NPN subcollector and the appropriate SiGe HBT isolation scheme. For the 200 GHz fT SiGe HBT in 8HP, critical process elements include a very lowresistance buried subcollector, n-type epitaxy formation, collector reach-through, and deep-trench isolation. In contrast, the 100 GHz fT SiGe HBT in 8WL does not require such process components and can be easily replaced by an implanted subcollector. After such processing sequence, the wafer in each case essentially looks like a standard CMOS processed wafer and can be put through the exact same processing sequence without any significant perturbation to the base CMOS process flow. Both BiCMOS flows then proceed with the standard CMOS processing steps: well implants, single and dual gate oxidations, gate poly deposition or pattern or etch, sidewall oxidation, LDD and extension implants, and finishing with the spacer formation. Essentially, bulk of the CMOS processing is completed with only the source–drain implant and activation remaining. There are multiple reasons for postponing the source–drain implants till after the bipolar formation — (a) the phosphorus (n-FET) and boron (pFET) dopants utilized for advanced CMOS tend to diffuse through the gate with additional lowtemperature cycles from the bipolar processing, (b) these implants can be used for the contact regions of parasitic active or passive devices built using bipolar elements, and (c) preserve modularity with the single activation RTA that can activate the CMOS and bipolar emitter. It should be noted that while the ‘‘BAG’’ approach reduces the thermal cycle for SiGe HBTs, it shifts the process challenge to clearing bipolar films from CMOS regions as well as requiring some re-engineering of CMOS well/extension/LDD implants for parametric centering. Prior to moving into the SiGe HBT build, the CMOS regions are protected by an etch stop layer that can later be easily removed. The bipolar module is extensively the same between 8HP and 8WL, with minor differences in the collector tailor implants and SiGe base profile. Structurally, both devices look quite similar and utilize advanced concepts of raised extrinsic base [6, 7] as well as fully realigned in situ doped emitter processing [8, 9] (see Figure 3.5.2). The bipolar module begins by defining a bipolar window opening by etching through a seed polysilicon and dielectric stack. Afterwards, the nonselective epitaxial growth of the

© 2006 by Taylor & Francis Group, LLC

3.5-267

Industry Examples at the State-of-the-Art: IBM

In situ doped emitter

Dielectric Isolation Silicide

Raised extrinsic base Boron-Doped SiGe base Collector Reachthrough plug Trench isolation

SIC collector Subcollector

FIGURE 3.5.2 Cross-sectional diagram of a raised extrinsic base SiGe HBT device.

UHV/CVD SiGe base region is completed. The raised extrinsic base with heavily doped p-type is then introduced. This provides a low-resistance linkup to the intrinsic base as well as much-reduced collector–base capacitance (CCB) for the SiGe HBT. The emitter–base junction is completed by the formation of an emitter opening with inside spacers, and then depositing an in situ doped polysilicon realigned emitter. The emitter polysilicon is then patterned and etched followed by the pattern or etch of the base polysilicon. The process challenge resides in the careful choice of an etch stop CMOS protect layer and the isotropic polysilicon etch that can clear all residual bipolar films from the CMOS gate topography. The CMOS protect layer is then removed for the source–drain implant and activation RTA. In the case of 8WL, prior to salicidation, a custom trench is etched around the NPN to reduce the collector–substrate capacitance. The trench is later filled with the contact dielectric and planarized. This allows minimum perturbation to the BiCMOS flow, while providing significant performance advantage for HBTs with negligible cost addition. The process sequence then moves into cobalt salicidation, contact formation, and BEOL metallization. Figure 3.5.3 shows a top view SEM of a static RAM cell built in 8HP, showing a clean CMOS integration that is possible with the 0.13 mm BiCMOS integration scheme. High-quality passive elements such as precision resistor, MIMcap, inductors, along with varactor, Schottky, and PIN diodes are integrated in a modular fashion to make technology attractive for various applications. Table 3.5.1 shows a comparative look at the various passive elements offered in 8HP and 8WL. Multiple resistors are available that range in sheet resistance, TCR, parasitic capacitance to substrate, and tolerance. For example, low TCR (<100 ppm/8C) and tight tolerance of less than 10% (3s) are achieved by the low-value polyresistor. Optimization of devices such as MIM capacitors and varactors varies from 8HP to 8WL due to the targeted applications. For example, the 8HP varactor is optimized for a Q value of 10 at 77 GHz, while the 8WL varactor is optimized for high-tuning range as well as linearity with Q >100 at 5 GHz. High-density MIM capacitors are required in wireless application to reduce the area consumed by precision capacitors that typically range from 1 to 10 pF. A high-k dielectric MIM capacitor has been developed in 8WL that is capable of 5 f F/mm2 density with high reliability of 10 ppm failure rate at 5 V for a

© 2006 by Taylor & Francis Group, LLC

3.5-268

The Silicon Heterostructure Handbook

Metal-1 Contact

Polygate

FIGURE 3.5.3 Top view scanning electron micrograph of a static RAM built using 0.13 mm groundrules and fully compatible with foundry CMOS integrated in BiCMOS 8HP.

TABLE 3.5.1

Passive Devices Offered in Both 8HP and 8WL Technologies

Resistors Diffused (n-type — ohms/sq.) Poly (p-type — ohms/sq.) Metal (TaN — ohms/sq.) Capacitors Hyper-abrupt varactor (VA ¼ 0 to
3 V) MOS varactor (VG ¼
1 to 1 V) MIMcap (fF/mm2) Decoupling (fF/mm2) Inductor AM with M1 groundplane Dual Cu with M1 groundplane Diodes Schottky barrier (Vf at 100 uA in mV) ESD protection

BiCMOS 8HP

BiCMOS 8WL

8.8, 73 340, 1700 60

73 220, 340, 1700 60

3.6:1 tuning 6:1 tuning 1 11

4:1 tuning 6:1 tuning 5 11

Q ¼ 19; L ¼ 1 nH Q ¼ 22.5; L ¼ 1 nH — Yes

350 Yes

total device area of 106 mm2 at 100 K power-on-hours (see Figure 3.5.4). This MIM capacitor is compatible with both Al and Cu BEOL integration as a modular element and does not require any changes to the standard BEOL processes to achieve high reliability. Due to the high frequency requirements in 8HP, the MIM capacitor is mostly limited by the minimum geometry possible as opposed to density. For example, to get 50 V impedance for applications in 60 to 80 GHz range, the MIM capacitor geometry of approximately 50 mm2 is reasonable to control if a 1.0 f F/mm2 capacitance density is utilized. The requirements for metallization also diverge due to the targeted application space for 8HP and 8WL. Clearly, the lower levels of metal wiring are required for tight-pitch CMOS integration that enables chip size reduction for system-on-chip integration trends observed in wireless applications. Analog metal above the standard CMOS wiring is needed to address several parameters such as inductor Q, transmission line, and wireability. In the case of 8HP, a standard 4-mm thick Al metal wire separated by at least 10 mm from metal-1 supports the 77 GHz transmission lines. This single metal scheme, however, is not optimal for varied wireless applications due to the cost and complexity considerations. In 8WL, therefore, multiple analog metal options are offered to address performance and cost tradeoffs. Figure 3.5.5 compares various options offered in 8WL relative to 8HP and base CMOS technology. Thick single and dual damascene Cu levels with tight pitch are utilized in 8WL to lower the wire and via resistance as well as to reduce the inductor footprint.

© 2006 by Taylor & Francis Group, LLC

3.5-269

Industry Examples at the State-of-the-Art: IBM

100 K µm2 single MIM capacitor

109

100KPOH

108

Time (s) to failure

107 106 105 104 103 102

Fit 1 PPM 10 PPM 100 PPM

101 100

6

8 10 12 Stress voltage (V)

14

16 18 20

FIGURE 3.5.4 A state-of-the-art MIM capacitor built using high-k dielectric with density of 5.0 fF/mm2 and a lifetime of 100K POH at 9.0 V. This device is integrated into the 8WL Cu BEOL metallurgy.

0.13 µm CMOS

8HP

8WL Option 1

8WL Option 2

8WL Option 3

AM

Al

RF/Analog module

EZ Cu

LY

E1

E1 LM

2X 2X 1X 1X 1X 1X

Standard CMOS ASIC Layers

FIGURE 3.5.5 Cross-sectional sketch of the BEOL metals in 0.13 mm BiCMOS technologies relative to the base CMOS configuration. Analog metal modules are kept thick to improve the inductor performance.

3.5.3 The SiGe HBT — Key Technology Elements In this section, we discuss the key process modules that undergo optimization depending on the technology of choice, i.e., 8HP or 8WL. Primarily, we focus on the subcollector, base–emitter regions, and bipolar isolation. In order to attain the lowest collector resistance, high-performance transistors typically employ buried subcollector with an epi growth. In addition, collector epilayer thickness allows one to tune fT as well as

© 2006 by Taylor & Francis Group, LLC

3.5-270

The Silicon Heterostructure Handbook

allow for multiple breakdown voltage devices. This technique is employed in 8HP to achieve 200 GHz fT. For transistors where subcollector resistance is not the performance limiter, one can easily replace with an implanted subcollector, leading to a much simplified processing [10]. The desired subcollector offset, such as that attained by epitaxial layer growth, is set by the implantation depth and reduction to channeling tails. Special process considerations, such as resist profile and postimplant annealing, need to be employed for ensuring manufacturability. By using various layout techniques one can reduce the total collector resistance and improve fT, without compromising on the processing complexity. The best achievable sheet resistances from both these methods differ by at least an order of magnitude, at the expense of complexity or wafer cost. This difference results in an acceptable but modest peak-fT reduction (<15 GHz) that can somewhat be recovered by using specialized collector layouts [11]. Typically, there are multiple variants of SiGe HBTs in any one technology that are attained by optimizing the collector profile. The maximum breakdown voltage SiGe HBT achievable in any technology will be set by the choice of the subcollector. In order to attain high-performance (HP) SiGe HBT one needs to reduce the vertical distance from the subcollector to base profile by adjusting the epi thickness, which limits the achievable breakdown voltage for the high-breakdown (HB) SiGe HBT. In order to increase the breakdown voltage of HB SiGe HBT, particularly used in power amplifiers and storage preamps, one needs to add additional masks to create an independent subcollector. An intermediate or medium performance (MP) SiGe HBT can be achieved by adding an implant mask to form selectively implanted collector (SIC) profile. In the case of SiGe 8WL, this implant is shared with CMOS well implant to obtain a 65 GHz HBT with no added mask cost. The SiGe base profile is engineered with a Ge ramp profile, with Ge peak concentration around 25% to minimize the base transit time. One can engineer the Ge ramp profile to tradeoff between fT (tE / 1/b / 1/Ge-ramp; tB / 1/Ge-ramp), current gain (b), and breakdown voltage (BVCEO / 1/b). For 8HP, the Ge ramp is made steeper than 8WL resulting in b-difference of two times and BVCEO difference of 0.7 V in a HP SiGe HBT. A carbon-doped narrow base boron profile is used in both technologies to minimize the basewidth. The undoped emitter and collector silicon cap thickness are adjusted for both technologies to attain the appropriate emitter–base and collector–base delay times. The extrinsic base link is formed by an in situ doped raised extrinsic base approach that allows one to reduce rbb simultaneously with CCB, and is utilized in both 8HP and 8WL. Polysilicon emitter is yet another module that has seen processing advances in the recent past. As one scales the transistor performance, the increase in emitter resistance (RE) and current gain (b) due to the presence of the emitter poly–Si interfacial oxide becomes unacceptable. Therefore, the advanced state-ofthe-art technologies use in situ doped polysilicon emitters to form a recrystallized mono emitter interface [12]. This method significantly reduces RE, brings b to a useful range, as well as improves fT. Both 8HP and 8WL technologies take advantage of this process element for improved SiGe HBT performance. Bipolar isolation in 8HP is achieved by using both shallow and deep trenches. The shallow-trench process in 8HP and 8WL is similar to the base CMOS process. The deep trench in 8HP is polyfilled and planarized with process commonality maintained to previous generation production SiGe BiCMOS technologies (e.g., 0.18 mm). This deep-trench isolation feature is not only utilized for bipolar collector– substrate capacitance (CCS) reduction, but, also under the passive elements to reduce substrate coupling. The integration of such a deep trench adds more complexity and wafer cost that is not warranted in 8WL. For desired CCS reduction, if one substitutes the deep trench with traditional simple junction isolation the HBT footprint becomes significant. In 8WL, therefore, a custom deep-trench isolation has been employed for HBTs to optimize performance and cost.

3.5.4 Electrical Performance The centerpiece of the BiCMOS technology is the SiGe HBT that enables the frequency performance. SiGe HBTs have shown sevenfold improvement in fT performance since its first introduction in the 0.5 mm production technology (see Figure 3.5.6). Both lateral- and vertical-scaling techniques are

© 2006 by Taylor & Francis Group, LLC

3.5-271

Industry Examples at the State-of-the-Art: IBM

400 Next generation Cutoff frequency (GHz)

350 300 250 0.13 µm

200

0.18 µm

150 100

0.5 & 0.25 µm

50 0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 3.5.6 SiGe HBT performance scaling over multiple technologies.

employed to reduce transit times and parasitics to boost fT/fmax performance. One aspect of the vertical scaling is to reduce base push out by increasing collector-doping concentration. This increases the collector current density required at peak-fT. However, by shrinking the emitter dimension proportionately one can obtain significant improvement in fT at the same collector current or reduce the power level required for the same fT. For example, at 1 mA of collector current, one can achieve an fT of 275 GHz using a 0.11 mm device compared to 43 GHz for a 0.42 mm SiGe HBT. Figure 3.5.7 shows the Gummel characteristics of both HP and HB SiGe HBTs built in 8HP technology. Devices show ideal behavior over several decades of currents, which is clearly reflected in the current gain (see Figure 3.5.8). As expected, the high-injection Ge-induced barrier effects are clearly visible in MP and HB devices due to the lower collector doping and early onset of the Kirk effect compared to high-performance SiGe HBT. It should be noted that the retrograde Ge profiles are designed to minimize the parasitic barriers and allow maximum fT prior to the Kirk effect. The output characteristics for HP, MP, and HB devices in both 8HP and 8WL technologies are shown in Figure 3.5.9 and Figure 3.5.10. High early voltage is attained for all devices over a 1 V voltage swing (VCE). The fT performance of various flavors of SiGe HBTs with minimum emitter width built in 8HP technology is shown in Figure 3.5.11. The fT and fmax are extracted from jh21j and jUj measured at 20 GHz and extrapolated with an ideal slope of 20 dB/decade, respectively. The HP transistor achieves 200 GHz at 5.0 mA of collector current for a 0.12  3 mm2 emitter transistor. With additional collector adjustment masks for the MP and HB transistors one can achieve 115 and 50 GHz, simultaneously on a wafer. The HP device also shows a reasonable fT performance over a wide temperature range (0 to 1258C) as seen in Figure 3.5.12. The peak-fT performance increases from 170 GHz at 1258C to 226 GHz at 08C, with very minor change to the peak-fT current density. One can also observe that the operating collector current reduces by two times at a fixed fT of 120 GHz over 1258C temperature range, primarily due to the temperature dependence of the emitter–base charging time as well as the current gain. In contrast to HBT optimization for peak-fT/fmax performance as in 8HP, the focus shifts to the optimization of power, noise-figure, linearity, breakdown voltage, etc., for the 8WL SiGe HBTs. The key transit time and parasitic reduction elements from the 8HP HBT are shared wherever possible and tradeoffs made on process modules that can lead to significant cost benefits for marginal performance improvement. One example of this study with the collector sinker has shown that the extra collector resistance introduced by replacing the collector reachthrough module in 8HP with available standard CMOS n-type implants reduces the peak-fT by only 3 GHz. This result combined with the subcollector

© 2006 by Taylor & Francis Group, LLC

3.5-272

The Silicon Heterostructure Handbook

1 ⫻ 10−1

Collector and base currents (A)

1 ⫻ 10−2 1⫻

10−3

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

1 ⫻ 10−4 1 ⫻ 10−5 1 ⫻ 10−6 1 ⫻ 10−7 1 ⫻ 10−8 1 ⫻ 10−9 1 ⫻ 10−10

HP HB

1 ⫻ 10−11 1 ⫻ 10−12 0.4

0.5

0.6

0.7

0.8

0.9

1

Base−emitter voltage (V)

FIGURE 3.5.7 Gummel characteristics of BiCMOS 8HP high-performance and high-breakdown SiGe HBTs. 650 600

HP MP HB

550 500 Current gain

450 400 350 300 250 200 150 100 50

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

0 1⫻10−9 1⫻10−8 1⫻10−7 1⫻10−6 1⫻10−5 1⫻10−4 1⫻10−3 1⫻10−2 1⫻10−1 Collector current (A)

FIGURE 3.5.8 Current gain for the three flavors of SiGe HBTs built in BiCMOS 8HP.

optimization data indicates the potential to fabricate very high-performance, state-of-the-art NPN devices, in a low-complexity process. Figure 3.5.13 shows the fT versus IC curves for three different SiGe HBTs fabricated on an 8WL wafer with optimized implanted subcollector process to meet a wide range of breakdown voltage requirements: a HP device with 96 GHz/2.35 V BVCEO, a MP device with 67 GHz/3.1 V BVCEO, and a HB device with 46 GHz/4.7 V BVCEO. These devices have a BVCBO of 10.4, 14, and 18.6 V, respectively. In general, the devices are not operated in the breakdown bias conditions such as BVCBO or BVCEO. However, these conditions represent the extremity of the NPN operation. The general relationship of breakdown voltage and fT for various SiGe HBTs that span several generations of technologies is plotted in Figure 3.5.14.

© 2006 by Taylor & Francis Group, LLC

3.5-273

Industry Examples at the State-of-the-Art: IBM

6⫻10−4 5⫻10−4 Collector current (A)

HP MP HB

BiCMOS 8HP 2 AE = 0.12 ⫻ 3 µm

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100 0

0.5

1

1.5 2 2.5 Collector-emitter voltage (V)

3

3.5

4

FIGURE 3.5.9 Output characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

6⫻10−4 BiCMOS 8WL AE = 0.12 ⫻ 4 µm2

Collector current (A)

5⫻10−4

HP MP HB

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100

0

0.5

1

1.5 2 2.5 3 3.5 Collector-emitter voltage (V)

4

4.5

5

FIGURE 3.5.10 Output characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

This relationship suggests that the operating margin exceeding 5.5 V can be achieved with a 100 GHz SiGe HBT, with the margin dropping only to 3.5 V for a 350 GHz SiGe HBT. The fMAX behavior for HP and HB devices is shown in Figure 3.5.15. The rbb and CCB reduction possible with the raised extrinsic base approach leads to superior fMAX performance for all HBTs, with obvious improvement seen for 8HP devices compared to 8WL over all bias ranges. We expect that the improved fMAX performance will lead to improved NFMIN performance, primarily due to the reduction in rbb. The NFMIN for 8WL shows a comparable performance to 8HP over a wide range of frequencies with 0.23 dB at 2.4 GHz and only upto 1.5 dB at 20 GHz (Figure 3.5.16 and Figure 3.5.17). These performance numbers for 8WL compare favorably with previous generation wireless technologies at 0.5 mm and 0.18 mm nodes (Figure 3.5.18).

© 2006 by Taylor & Francis Group, LLC

3.5-274

Cutoff frequency (GHz)

The Silicon Heterostructure Handbook

220 200 180 160 140 120 100 80 60 40 20 0 0.1

BiCMOS 8HP VCB = 0.5 V

High performance 2 AE = 0.12 ⫻ 3.0 µm

Medium performance 2 A E = 0.12 ⫻ 2.5 µm

High breakdown 2 AE = 0.12 ⫻ 2.5 µm

1 10 Collector current density (mA/mm2)

100

FIGURE 3.5.11 fT characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

240 Cutoff frequency (GHz)

220 200

T = 0⬚C, 25⬚C, 55⬚C, 85⬚C, 125⬚C

180 160 140 120 100 BiCMOS 8HP A E = 0.12 ⫻ 3 µm2 V CB = 0.5 V

80 60 40 1⫻10−4

1⫻10−3 Collector current (A)

1⫻10−2

FIGURE 3.5.12 Temperature dependence of fT for the HP SiGe HBT in BiCMOS 8HP technology.

Cutoff frequency (GHz)

120 100

BiCMOS 8WL AE = 0.12 ⫻ 4 µm2 VCB = 1.0 V

High performance

80 Medium performance

60 40 High breakdown

20 0 0.01

0.1 1 Collector current (mA)

10

FIGURE 3.5.13 fT characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

© 2006 by Taylor & Francis Group, LLC

3.5-275

Industry Examples at the State-of-the-Art: IBM

Peak cutoff frequency (GHz)

400 350 300 250 200 150

BVCBO limited

100

BVCBO limited

50 0 0

10 15 Breakdown voltage (V)

20

25

The general fT and breakdown voltage relationship for various SiGe HBTs. Unilateral maximum power gain frequency (GHz)

FIGURE 3.5.14

5

350 HP HB VCB = 1.0 V

300 250

BiCMOS 8HP

200 150 100 50

BiCMOS 8WL

0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 3.5.15

fMAX characteristics of HP and HB devices built in 8HP and 8WL technologies. 2.5 8HP 8WL

NFmin (dB)

2 20 GHz 1.5 1 10 GHz 0.5 2 GHz 0 0

FIGURE 3.5.16

2

4 6 8 Collector current (mA)

10

12

NFMIN as a function of collector current for HP devices in 8HP and 8WL technologies.

© 2006 by Taylor & Francis Group, LLC

3.5-276

The Silicon Heterostructure Handbook

2.5 8HP 8WL

NFmin (dB)

2 1.5 1 0.5 0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 3.5.17 NFMIN for HP devices built in 8HP and 8WL over a wide range of frequencies.

Minimum noise figure (dB)

3 10 GHz 2.5

5HP: AE = 0.5 ⫻ 20 ⫻ 2 µm2

2 7WL: AE = 0.24 ⫻ 20 ⫻ 2 µm2

1.5 1 0.5

8WL: AE = 0.12 ⫻ 32 µm2

0 0.1

1 Collector current (mA)

10

FIGURE 3.5.18 NFMIN characteristics of 8WL HP device compared to the previous generation wireless technologies at 0.18 and 0.50 mm nodes.

Industry-standard foundry-compatible CMOS devices at 1.2 and 2.5 V are offered in both 8HP and 8WL. In addition to these basic FETs, 8WL includes devices tailored for analog- and mixed-signal applications, such as 3.3 V/5.2 nm gate oxide analog transistors with a gate length of 0.4 mm, zero-VT transistors etc. Triple well nFETs with 2.1 and 5.2 nm gate oxide are also supported in the BiCMOS technologies. RF layouts are developed for the FETs to provide accurate substrate resistance values and wiring parasitics. The 1.2 V/1.5 V 2.1 nm gate oxide logic FETs have gate length of 0.92 mm while the 2.5 V/5.2 nm thick oxide I/O driver FETs have a gate length 0.21 mm. Figure 3.5.19 and Figure 3.5.20 show the VTsat versus Idsat scatter plots demonstrating equivalence of the CMOS parameters in the BiCMOS and 0.13 mm base CMOS technologies.

3.5.5 Manufacturability For a stable manufacturable technology, it is important that the technology demonstrates adequate parametric control as well as yield over large quantities of lots processed over time. In this section, we present some key manufacturability data that provide insight into the state-of-the-art 8HP technology.

© 2006 by Taylor & Francis Group, LLC

3.5-277

Industry Examples at the State-of-the-Art: IBM

600

I d Saturation (mA)

580 560 540 520 500 480 8SF 8HP 8WL 460 440 270

290

310

330 350 370 V t Saturation (mV)

390

410

FIGURE 3.5.19 Thin oxide nFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VT
Idsat relationship.

−130 −140

I d Saturation (mA)

−150 −160 −170 −180 −190 −200

8SF

8HP

8WL

−210 −220 −450

−400

−350 V t Saturation (mV)

−300

−250

FIGURE 3.5.20 Thin oxide pFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VT
Idsat relationship.

Figure 3.5.21 shows the parametric distribution of base–emitter voltage (VBE) measured at 10 mA of emitter current for 0.12  2.5 mm2 HP transistor for a large sample size of lots processed during technology qualification. This normal distribution shows a 0.7% one-sigma variability, signifying good process control for the emitter–base junction depth as well as the base profile including LTE Ge ramp. For the collector–base control, we show in Figure 3.5.22, the histogram of BVCBO measured at 10 mA for a 0.12  2.5 mm2 HP device on a significantly larger sample size of lots. Data indicate that a tight control of the collector–base junction is possible (one-sigma of 1.3%). We expect that the tight control of the CB profile will also improve the avalanche, fT, CCB, and fMAX performance. The AC performance is sampled (five chips per wafer) routinely to understand the stability of peak-fT/ fmax by measuring s-parameters using a 110 GHz HP analyzer. Figure 3.5.23 shows the fT and fMAX over a

© 2006 by Taylor & Francis Group, LLC

3.5-278

The Silicon Heterostructure Handbook

30

N Mean Sigma Minimum 1st Ptile 5th Ptile 10th Ptile 25th Ptile Median 75th Ptile 90th Ptile 95th Ptile 99th Ptile Maximum LSL Target USL % Low % Yield % High Cp Cpk

25

Percent

20

15

10

5

Normal X2

0 700.5

709.5

718.5

727.5

736.5

745.5

677 727.1496 5.297336 705.6565 711.6716 717.5469 720.4985 724.3328 727.4758 730.3022 733.6274 735.5154 739.8247 742.6243 701 726 751 0 100 0 1.573118 1.50078 65.81932

754.5

Test M1 8211 309 TX6 FVEBS 10UA

FIGURE 3.5.21 Histogram of VBE measured on 0.12  2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple lots.

22.5 20.0 17.5 15.0

Percent

4185

N

12.5 10.0 7.5

Mean

5.87393

Sigma

0.078501

Minimum

5.627674

1st Ptile

5.695866

5th Ptile

5.750379

10th Ptile

5.784013

25th Ptile

5.828348

Median

5.869673

75th Ptile

5.912518

90th Ptile

5.963103

95th Ptile

6.01013

99th Ptile

6.122393

Maximum

6.289583

LSL

5.5

Target

5.9

USL

6.3

% Low

5.0

% Yield % High

1.587784

Cpk Normal X2

0 5.475

5.595

5.715

5.835

5.955

6.075

6.195

0 1.698482

Cp

2.5

0 100

2251.166

6.315

Test M1 8211 313 TX6 BVCBO 10UA

FIGURE 3.5.22 Histogram of BVCBO measured on 0.12  2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple wafer-lots.

© 2006 by Taylor & Francis Group, LLC

3.5-279

Industry Examples at the State-of-the-Art: IBM

320 fMAX

305

Cutoff frequency (GHz)

290 275 260 245

BiCMOS 8HP

230

AE = 0.12 ⫻ 3 µm2 VCB = 0.5 V

fT

215 200 185 170 0

Peak-f T and peak-fmax (GHz), min-Rbb (ohms)

FIGURE 3.5.23 wafer-lots.

10

20

30

40 Wafer

50

60

70

80

Frequency performance trend chart for HP transistor in 8HP technology, sampled over multiple

130

fT

120 110 100

fMAX

90 80 70

AE = 0.2 ⫻ 6.4 µm2

60

Vcb = 1.0 V

50

rbb

40 30 20 10 0 0

3

6

9

12

15

18

21 Lots

24

27

30

33

36

39

FIGURE 3.5.24 Frequency performance trend chart for HP transistor in 0.18 mm/120 GHz technology, sampled over multiple lots during past 2 years.

significant quantity of wafers built over time. Clearly, the fT is well controlled and centered around 200 GHz. The average fMAX shows around 280 GHz with a range from 260 to 310 GHz. It should be noted that some of the fMAX variability is due to the extraction error introduced by the sensitivity of the slope in jUj roll-off. A much larger sample size of AC data has been collected over a period of 2 years from the production 120 GHz 0.18 mm SiGe BiCMOS technology as shown in Figure 3.5.24. Data from close to 40 lots sampled over this significant period of production timeframe indicate stability in the AC performance with all lots meeting specifications. Such a performance control in both these highperformance BiCMOS technologies is a testament to the SiGe epi base process control and the LTE tooling capability.

© 2006 by Taylor & Francis Group, LLC

3.5-280

The Silicon Heterostructure Handbook

The yield is routinely measured on every lot for various active devices, contacts, and the BEOL metallurgy. The NPN yield is measured on an array of 2000 transistors connected in parallel, with the combined leakage measurement for EB, CB, and CE junctions performed. The chain is considered to be a fail if any one junction shows a higher than expected leakage. The chain yield for both HP and HB devices in 8HP is shown in Figure 3.5.25. As expected, the HP transistor has lower yield compared to the HB device due to additional processing. The development of SiGe HBT exposed unique NPN CB yield sensitivity due to the interaction of various processing factors, namely, CMOS RIE etch on bipolar regions, SIC implant, and the LTE processing. This process interaction leads to somewhat depressed yield for NPNs, with HP transistors showing more sensitivity to this mechanism. Data suggest that the yield for NPNs can be improved to well above the 90% by eliminating such sensitivities as typically practiced under volume manufacturing by improved defect learning. Figure 3.5.26 represents the CMOS, contact, and BEOL yield for the last 15 lots fabricated in 8HP technology. The CMOS yield is measured as a cumulative effect of shorts measured from gate-to-source– drain and gate-to-gate and gate-to-well. Contact yield is measured by looking at open on a series of 40K contacts. BEOL cumulative yield is measured as metal shorts and via opens for all the levels. Overall, the combined parametric control as well as yields for various elements of the technology indicates the manufacturability of the state-of-the-art SiGe BiCMOS technology.

3.5.6 Summary The state-of-the-art production SiGe BiCMOS technologies at the 0.13 mm lithography node have been presented. The flexibility of SiGe HBT integration is utilized for tailoring BiCMOS technologies for applications that range from performance-hungry automotive radar to low-cost wireless and storage markets. BiCMOS 8HP and 8WL technologies feature multiple SiGe HBTs that tradeoff fT and breakdown voltage, by optimizing the collector profile through implant masks. CMOS and passive elements are also easily integrated with a fully foundry-compatible Cu BEOL wiring. In addition, we have shown manufacturability data for the 200 GHz SiGe BiCMOS technology, indicating that viability of such technologies in the semiconductor marketplace.

100.0 90.0

NPN 2K chain yield (%)

80.0 70.0 60.0 BiCMOS 8HP 50.0

2K Array

40.0 30.0 20.0 HP HB

10.0 0.0 0

5

10

15

20

25

30

35

Wafers

FIGURE 3.5.25 NPN chain yield for HP and HB transistors in 8HP technology, sampled over multiple wafer-lots.

© 2006 by Taylor & Francis Group, LLC

3.5-281

Industry Examples at the State-of-the-Art: IBM

100 90 80

Yield (%)

70 60 50 40 30 20 10 0 1

2

3

4

5

6 CMOS

7

8 Lots

9

Contact

10

11

12

13

14

15

BEOL

FIGURE 3.5.26 Chain yield data for CMOS, contacts, and BEOL elements in 8HP technology.

Acknowledgments We thank the technology development team in Essex Junction, Vermont and East Fishkill, New York, for their dedication in providing RF, Analog, and Mixed-signal technology solutions. In particular, we greatly appreciate the contributions of Louis Lanzerotti, Xuefeng Liu, Qizhi Liu, David Sheridan, Doug Coolbaugh, Robert Rassel, Jim Slinkman, Bradley Orner, Steve St. Onge, Natalie Feilchenfeld, and Jeffrey Johnson toward the success of this work. Finally, we thank the IBM senior management for their support — Bernie Meyerson, David Harame, Dean Herman Jr., Wally Stein (now retired), and John DiToro — in helping to bring the SiGe BiCMOS solution to the marketplace.

References 1. S. Zhang, J.D. Cressler, S. Subbanna, R. Groves, G. Niu, T. Isaacs-Smith, J.R. Williams, H. Bakhru, P.W. Marshall, H.S. Kim, R.A. Reed. An Investigation of Proton Energy Effects in SiGe HBT Technology. IEEE Transactions on Nuclear Science 49(6):3208–3212, 2002. 2. D.C. Ahlgren, M. Gilbert, D. Greenberg, J. Jeng, J. Malinowski, D. Nguyen-Ngoc, K. Schonenberg, K. Stein, R. Groves, K. Walter, G. Hueckel, D. Colavito, G. Freeman, D. Sunderland, D.L. Harame, B. Meyerson. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace. Technical Digest of International Electron Device Meeting 1996, December 1996, pp. 859–862. 3. SiGe Review. http://www.epenet.com/Newsletters%20-%20Features/sigerev.htm. 4. 802.11 PRISM products. http://www.conexant.com/products/entry.jsp?id ¼ 28. 5. D.L. Harame, D.C. Ahlgren, D.D. Coolbaugh, J.S. Dunn, G.G. Freeman, J.D. Gillis, R.A. Groves, G.N. Hendersen, R.A. Johnson, A.J. Joseph, S. Subbanna, A.M. Victor, K.M. Watson, C.S. Webster, P.J. Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2584, 2001. 6. B. Jagannathan, M. Meghelli, K. Chan, Jae-Sung Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna, G. Freeman, 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Device Letters 24:645–655, 2003. 7. B.A. Orner, Q.Z. Liu, B. Rainey, A. Stricker, P. Geiss, P. Gray, M. Zierak, M. Gordon, D. Collins, V. Ramachandran, W. Hodge, C. Willets, A. Joseph, J. Dunn, J.-S. Rieh, S.-J. Jeng, E. Eld, G. Freeman,

© 2006 by Taylor & Francis Group, LLC

3.5-282

8.

9.

10.

11.

12.

The Silicon Heterostructure Handbook

D. Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fMAX) SiGe HBT. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2003, pp. 203–206. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinares, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharro, J.L. Regolini, G. Vincent, A. Chantre. A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices 46:1525–1531, 1999. A. Joseph, P. Geiss, X. Liu, J. Johnson, K. Schonenberg, A. Chakravarti, D. Ahlgren, J. Dunn. Emitter resistance improvement in SiGe HBTs. Proceedings of the First International SiGe Technology and Device Meeting, January 2003, pp. 223–224. N. Feilchenfeld, L. Lanzerotti, D. Sheridan, R. Wuthrich, P. Geiss, D. Coolbaugh, P. Gray, J. He, P. Demag, J. Greco, T. Larsen, V. Patel, M. Zierak, W. Hodge, J. Rascoe, J. Trappasso, B. Orner, A. Norris, D. Hershberger, B. Voegeli, S. Voldman, R. Rassel, V. Ramachandiran, M. Gautsch, E. Eshun, R. Hussain, D. Jordan, S. St Onge, J. Dunn. High performance low complexity 0.18 mm SiGe BiCMOS technology for wireless circuit applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2002, pp. 197–200. L. Lanzerotti, N. Feilchenfeld, D. Coolbaugh, J. Slinkman, P. Gray, D. Sheridan, J. Higgins, W. Hodge, M. Gordon, T. Larsen, M. Gautsch, P. Lindgren, R. Murty, J. Rascoe, K. Watson, T. Stamper, E. Eshun, J. He, K. Downes, R. Rassel, J. Greco, B. Labelle, S. Sweeney, K. Stein, R. Bolam, K. Vaed, B. Omer, A. Joseph, S. St Onge, J. Dunn. A cost performance 0.13 mm SiGe BiCMOS technology for wireless and mixed signal applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2004, pp. 13–14, 237–240. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, R. Beerkens, N. Zerounian, F. Aniel, A. Chantre. 230 GHz self aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, October 2004, pp. 13–14, 225–228.

© 2006 by Taylor & Francis Group, LLC

3.6 Industry Examples at the State-of-the-Art: Jazz 3.6.1 3.6.2

Introduction............................................................... 3.6-283 SiGe Bipolar Transistor............................................. 3.6-284 Fully Self-Aligned Device Structure . SiGe npn Performance . Vertical Scaling . Lateral Scaling

3.6.3

SiGe BiCMOS Process Integration .......................... 3.6-289 Integration Sequence . CMOS Thermal Budget . SiGe npn Manufacturability

3.6.4

Wireless Technology . High Data Rate and High-Frequency Technology

Paul H.G. Kempf Jazz Semiconductor

Process Customization.............................................. 3.6-291

3.6.5

Summary .................................................................... 3.6-293

3.6.1 Introduction The roots of most commercial silicon germanium (SiGe) BiCMOS processes lie in a tradition of bipolar technology developed relatively slowly over multiple generations. Historical progress of traditional bipolar technology was quickly outpaced by CMOS processes in the 1990s with ever-shrinking linewidths in state-of-the-art CMOS fabs. A step-up to 200 mm wafers for BiCMOS technology created a gap between older generation bipolar technologies, which were optimized at a time when the addition of CMOS compromised bipolar performance, and the new generation of BiCMOS technologies that took full advantage of the tool capabilities in an advanced CMOS fab [1, 2]. Improved capabilities included better control of thermal steps due to vertical furnaces, new temperature monitoring schemes for rapid thermal annealing, higher selectivity etches for silicon, oxide and nitride, in-line SEM metrology for monitoring of critical structures, and tighter photomask alignment tolerances. Along with this fundamentally improved equipment capability came the development of sophisticated factory automation that made it possible to run multiple process technologies with an increasing number of photomask layers at consistently high fab yield. In this new environment, the bipolar transistor was able to realize the full benefit of the addition of silicon germanium to the base structure because lateral scaling reduced performance-limiting parasitic capacitance and resistance, while thermal budget control enabled manufacturable ultra-shallow junctions that were needed for vertical scaling in high-speed bipolar transistors. Acceleration of the performance curve for SiGe bipolar transistors has once again placed the bipolar device as the highest speed transistor available on silicon [3]. This background explains the foundation of Jazz Semiconductor’s SiGe BiCMOS technology, which was released to production as a high-performance upgrade to a 0.35-mm silicon BiCMOS process in the year 2000 (named SiGe60), and later advanced to an ultra-high-performance bipolar module, with fT 3.6-283 © 2006 by Taylor & Francis Group, LLC

3.6-284

The Silicon Heterostructure Handbook

and fmax greater than 155 GHz, integrated with standard 0.18-mm CMOS (named SiGe120). As an example of state-of-the-art production technology, this chapter will focus on the unique optimization of the bipolar structure in a 0.18-mm process, provide a summary of its performance characteristics for different device optimizations up to an fT of 200 GHz, discuss BiCMOS integration challenges for 0.18 and 0.13-mm, and detail some of the customization requirements that are an important aspect of overall technology capability.

3.6.2 SiGe Bipolar Transistor The first choice that must be made when considering transistor architecture is the overall performance level that needs to be met, which is largely fixed by the set of addressable applications for the technology. A dilemma arises when the end-market for a technology is evolving as quickly as the technology. For example, the wireless world was recently focused on up to 2 GHz carrier frequencies, but has since opened up 5 to 60 GHz as a range of interest for high-speed data and other applications. Development of a transistor capable of addressing a wide range of high-speed applications leads to a device design that does not trade off key parameters for one another.

Fully Self-Aligned Device Structure Rather than extending the quasi-self-aligned bipolar structure from the first generation of Jazz SiGe BiCMOS technology to smaller geometries, compromising base link resistance, emitter width, overlap capacitances, and other parameters, a choice was made to create a new self-aligned bipolar device with balanced performance characteristics and physical attributes that would be compatible with supporting a large variety of products integrated with 0.18-mm CMOS technology and below (Figure 3.6.1a). Key attributes include low resistance buried layer and substrate epitaxy for collector formation, deep trench

Self-aligned extrinsic base

Final emitter Collector Base Self-aligned base implant

Direct-patterned Sacrificial emitter Blanket SiGe

Buried layer

Deep trench isolation

Intrinsic Link SiGe base base (a)

(b)

Normalized Rb

3 2.5 2 1.5

SA

1

QSA

0.5 0 0 0.1 0.2 0.3 Effective base link width (microns) (c)

FIGURE 3.6.1 (a) Schematic cross section of the self-aligned SiGe npn transistor. (b) Sacrificial emitter masks the extrinsic base implant. (c) Simulated base resistance at peak fT for self-aligned (SA) versus quasi-self-aligned (QSA) emitter. Error bars show 3-sigma variation.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-285

isolation, near-planar SiGe epi to polysilicon transition, selective collector implants, scalable emitter width with self-aligned base link implants, low-resistance in-situ doped emitter, and conventional cobalt silicidation [4, 5]. The process flow begins with the formation of the buried layer by a high-dose implant and growth of an epitaxial layer. This approach is chosen over use of a high-energy implant to minimize collector resistance and maintain high fT at the low Vce typically employed in small-signal, high-speed applications. It also allows for a wide range of breakdown voltages (BVceo) on the same wafer, which is achieved with different doping levels of the selectively implanted collector (SIC). An optional deep trench is also used to reduce collector–substrate capacitance (Ccs), an important factor in reducing switching delay. The trench is filled with an oxide liner and a polysilicon plug. An oxide-filled shallow trench is also formed, providing a planar surface on which to build the emitter–base structure of the npn bipolar transistor. A blanket SiGe deposition was chosen to support scalable transistor geometries for a wide range of active device area to total wafer area ratios, which is an important capability for a foundry technology that must achieve predictable device performance for a wide variety of circuit layouts. The temperature uniformity that can be achieved across the wafer is superior in the case of a blanket process where similar film stacks are present everywhere during SiGe epi growth. For the base of the drift-field SiGe bipolar transistor, germanium is ramped from 0% near the base–emitter junction to approximately 30% near the collector–base junction, and a very narrow spike of boron is included in the growth sequence. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implants (Figure 3.6.1b), which enable independent optimization of extrinsic base resistance while maintaining a planar base structure that minimizes link resistance effects between the intrinsic epitaxial base and the extrinsic polycrystalline base contact. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimensions of the sacrificial emitter exactly define the final emitter dimensions. This is in contrast to inside spacer techniques that show greater emitter width variation due to the reduced photo and etch resolution of a slot versus a bar, and on the spacer width variation determined by film thickness and etch uniformity (Figure 3.6.1c). Also, this technique results in a self-aligned emitter–base without selective epitaxy, versus the approach used in Ref. [6]. Outside spacers on the emitter poly are necessary for selfalignment of the final extrinsic base used for low base contact resistance and for the prevention of a silicide short between emitter and base polysilicon layers. The subsequent cobalt silicide formation, contact etch, and oxide chemical mechanical polish (CMP) are the same as a standard CMOS process. Achieving extremely low emitter resistance is critical in order to achieve high-speed performance and can be especially limiting for emitter areas that can be as small as 0.2
0.7 mm2 in 0.18-mm technology. Components of the emitter resistance include the emitter to silicon interface, the polysilicon resistivity (dependent on grain structure and dopant activation), the cobalt silicide to polysilicon interface, and the standard contact and metal components. The completed device has a small footprint and a planar intrinsic to extrinsic base transition that enables the high performance of the SiGe npn transistor.

SiGe npn Performance Effective optimization of the SiGe npn transistor results in a device with a wide range of applicability. The scalable architecture is used to build production devices with fT of 38, 78 and 155 GHz with nominal BVceo of 6, 3.5 and 2.2 V, respectively. Changes to the collector doping profile and reduced base width extend the same approach to a technology with fT and fmax greater than 200 GHz [7] while maintaining a BVceo of 2.0 V. As shown in Figure 3.6.2, the gains in the performance of the higher breakdown voltage bipolar devices in each technology have been tracking the high-speed transistor, demonstrating that improvements in the intrinsic device structure have played a significant role in overall SiGe npn performance. While achieving peak fT at modest current density is important for small-signal highspeed circuits, minimum noise figure and low power performance are critical for many RF applications. Benefits derived from low parasitic resistance and capacitance of the Jazz 0.18-mm SiGe bipolar transistor are evident in Figure 3.6.3 relative to the Jazz 0.35-mm SiGe BiCMOS technology that uses

© 2006 by Taylor & Francis Group, LLC

3.6-286

The Silicon Heterostructure Handbook

1000 BC35 SiGe60

f T (GHz)

SiGe90/120 SiGe200

100

10 1

2

3

4 BVceo (V)

5

6

7

FIGURE 3.6.2 fT versus typical BVceo for four generations of Jazz BiCMOS.

200 175

Vce=1 V

SiGe200

fT (GHz)

150

SiGe120

125 100 SiGe90

75

SiGe60

50 25

BC35

0 0.01

0.1

1

10

I C (mA) for minimum We and Le = 1 µm

FIGURE 3.6.3 Higher fT performance at low and high current ranges for 0.18-mm SiGe BiCMOS processes (SiGe90/120/200) versus 0.35-mm (SiGe60, BC35).

a quasi-self-aligned emitter. A large reduction in current required to meet RF circuit specifications, realized over a wide range of frequencies, has been published in various circuit-related studies [8–11]. Performance gains can be attributed to both the vertical and lateral scaling properties of the SiGe bipolar transistor.

Vertical Scaling Vertical scaling has been the traditional advantage of bipolar transistors over n-type MOS transistors due to the better control of vertical profiles versus lateral dimensions. This inherent fT advantage still holds true for advanced npn SiGe bipolar devices versus nanometer gate length CMOS. Optimization of fT is dependent upon a number of factors, as represented by the following analytical model that has proven effective at predicting peak fT of the Jazz bipolar devices:

© 2006 by Taylor & Francis Group, LLC

3.6-287

Industry Examples at the State-of-the-Art: Jazz

1=(2pf T ) ¼ (R e þ kT =(qIc ))(Cbe þ Cbc ) þ Wb2 =(2D b ) þ Wc =(2Vs ) þ Rc Cbc

(3:6:1)

where R e is the emitter series resistance, Ic the collector current, Cbe and Cbc the respective junction capacitances, Wb the base width, Db the electron diffusivity in the base, Wc the collector depletion region, Vs the saturated electron velocity, and Rc the collector resistance. Elements from Equation (3.6.1) can be calculated as a function of process parameters to help analyze trends in the bipolar performance. One method of increasing fT is to increase the collector doping concentration, which moves the Kirk effect to higher collector current density and results in higher peak fT. As shown in Figure 3.6.4, both experimental results as well as predictions from Equation (3.6.1) indicate that this technique is effective at lowering collector doping concentrations, but the benefits saturate at higher doping concentrations due to limitations of Re and Cbc at higher collector current. To achieve higher fT, therefore, Re or Wb must be reduced. Further reduction of base width, Wb, for these high-performance transistors has negative implications on the manufacturability and defect levels for the bipolar device, so reduction of emitter resistance is a more attractive optimization for high fT. Figure 3.6.4 shows that Re does not significantly affect fT at lower collector doping concentrations or lower Ic, and that Re does significantly affect fT at higher collector doping concentrations or higher Ic. Based on this analysis, a strong reduction in emitter resistance, coupled with a small re-optimization in the collector dose, has been used to increase the fT of the SiGe transistor without significantly reducing the base width. A peak fT of 205 GHz is reached for a production device with BVceo of 2.0 V, resulting in an fT
BVceo product of 410 GHz-V.

Lateral Scaling For a given vertical scaling of the SiGe bipolar transistor, the fmax, or similarly the unilateral gain, can be improved with lateral scaling that reduces base-to-collector capacitance and the intrinsic base resistance. Reduction of base resistance also results in lower minimum noise figure, which is beneficial for lownoise amplification of RF signals. Lateral scaling of the active transistor area introduces a challenge in process integration of a nonselective SiGe epitaxial module in order to avoid facet growth at the isolation edge. Optimization for high fmax can be accomplished with a focus on reduction of the total base– collector capacitance (Cbc) and also depends on the emitter integration already discussed for fT optimization, as well as minimizing the extrinsic base resistance or base link, which dominates the total of the extrinsic and intrinsic components of base resistance.

225

0.5 ⫻ Re

200

Re

Peak fT (GHz)

175 2.0 ⫻ Re

150 125 100 75 50 25 0 0

1 2 3 Normalized collector doping

4

FIGURE 3.6.4 Calculated (lines) and measured peak fT as a function of collector doping and emitter resistance.

© 2006 by Taylor & Francis Group, LLC

3.6-288

The Silicon Heterostructure Handbook

For any given emitter integration, a compromise exists between fT and fmax as the collector design becomes more aggressive. The relationship for fmax with dependence on fT can be expressed as the following:

fmax

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi fT ¼ 8pRb Cbc

(3:6:2)

The increased collector doping shifts the Kirk effect to higher current and enables higher fT, but also increases Cbc and degrades fmax. The total Cbc is made up of two basic components: the intrinsic is determined by the collector design to achieve target fT; the parasitic extrinsic components, such as the junction from the pþ extrinsic base to the SIC and also to the nþ buried layer, can be reduced by scaling active area to lower Cbc and improve fmax. Scaling of the base–collector area can be represented by the design rule for active overplot of the emitter, as shown in Figure 3.6.5a for two different collector 22

SIC1 SIC2

21 20

SIC1

C bc (fF)

19 18 17

SIC2 = 0.8 ⫻ SIC1 Average doping level

16 15 14 13 0.15

(a)

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

Emitter active overplot (µm)

35

DR A DR B

Unilateral gain (db)

30

25

20

15

10

5

0 1⫻109

(b)

1⫻1010

1⫻1011

Frequency (Hz)

FIGURE 3.6.5 (a) Base–collector capacitance Cbc as a function of the active overplot of the emitter opening for two collector-doping levels. (b) Improvement in unilateral gain with reduced emitter active overplot.

© 2006 by Taylor & Francis Group, LLC

3.6-289

Industry Examples at the State-of-the-Art: Jazz

designs, one more highly doped at the base–collector junction, and the other more moderately doped. With smaller active sizing (i.e., smaller active overplot of emitter), there is a linear reduction of Cbc that is due to a lower coupling of the peripheral extrinsic component to the nþ buried layer. Since the magnitude of the reduction is dependent on the initial doping level, lateral scaling results in more significant Cbc reduction when a more aggressive, highly doped collector profile is used. Since the physical effect of this design rule is to reduce the length of the electrical connection to the intrinsic transistor, the total resistance would be expected to decrease for a given base resistance. This is not the case for the Jazz 0.18-mm SiGe bipolar transistor due to slow SiGe epi growth planes, dominated by a h3 1 1i type, that are less favorable for carrier transport and effectively reduce the active sizing from the original lithographic definition. Small changes to the optimization of the SiGe epi recipe and the integration process module limit facet growth and result in simultaneous Cbc and Rb reduction for the Jazz 200 GHz SiGe process (named SiGe200). The resultant fmax gains are significant, and reach beyond 200 GHz (Figure 3.6.5b). Intrinsic base resistance is lowered with reduced emitter width, and parasitic collector–base capacitance is lowered through reduction of the active base area. The resulting transistor has fT greater than 200 GHz (magnitude of H21) and fmax greater than 200 GHz (unilateral gain) for an emitter width of 0.15-mm.

3.6.3 SiGe BiCMOS Process Integration CMOS and bipolar performance targets within a BiCMOS technology should be considered simultaneously for a range of applications. Maintaining a significant gap between the fT of the n-type MOS transistor and the high-speed npn bipolar, as defined by fT versus line width in Figure 3.6.6, has broadened the application space for each process generation. Since the bipolar transistor is what defines the unique capability of SiGe BiCMOS, a number of process variants include the same self-aligned npn architecture with 0.25, 0.18, or 0.13-mm MOS transistors.

200 SiGe BiCMOS NPN

fT (GHz)

100 80 60

Si BiCMOS NPN

40 CMOS NFET

20

10 0.5

0.35

0.25

0.18 0.15

0.13

Technology (µm)

FIGURE 3.6.6 Performance curve as a function of process generation for production CMOS, BiCMOS, and SiGe BiCMOS technologies.

© 2006 by Taylor & Francis Group, LLC

3.6-290

The Silicon Heterostructure Handbook

Integration Sequence After buried layers are formed in bipolar collector regions, an epitaxially grown n-type silicon layer becomes the starting substrate for the n- and p-type MOS transistors. Standard well implant doses have been slightly adjusted versus the bulk CMOS process for the presence of the lightly doped n-type layer. An oxide-filled shallow trench is created and dual-gate oxides are grown in support of both 1.8 and 3.3 V MOS transistors. After gate formation and patterned opening of the bipolar base regions, the bipolar is integrated by first depositing a blanket SiGe layer using a single-wafer rapid thermal chemical vapor deposition (RT-CVD) reactor. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implant. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimension of the sacrificial emitter exactly defines the final emitter dimension. A collector implant differentiates the fT and BVceo of the three available npn transistors. Several dry etch steps are used to pattern the emitter poly and remove bipolar-related layers from the CMOS regions of the wafer. Next, the CMOS devices are completed with formation of side-wall spacers, implantation of source and drain, final implant activation and cobalt silicidation, all of which are shared with the SiGe bipolar device. Back-end options include three to six layers of metal with a 1 to 4 fF/mm2 MIM capacitor, a 25 ohm/sq metal resistor and up to a 5.2-mm-thick top metal layer and a 3-mm thick top dielectric layer to realize high-quality inductors. These results have been achieved with integrated 1.8/3.3 V dual-gate CMOS. Full digital library compatibility is maintained for 0.18-mm CMOS performance with the integration of the bipolar device. Idsat of the 1.8 V transistors is 600 and 255 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively. Options for a natural Vt MOS transistor and triple-well isolation are included in this modular technology. Compatibility with 0.13-mm dual-gate 1.2/3.3 V CMOS has also been demonstrated, as shown in the typical output curves in Figure 3.6.7. Idsat of the 1.2 V transistors is 500 and 215 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively.

CMOS Thermal Budget As CMOS is scaled, thermal budget constraints of advanced bipolar devices and CMOS devices diverge, leading to more difficult integration. The CMOS gate, re-oxidation, LDD, and pocket implants are included prior to SiGe epi deposition then the source–drain implants and final anneal are implemented after the SiGe bipolar transistor is completely formed. This limits the exposure of the SiGe transistor to CMOS-related thermal budget from the gate and re-oxidation cycles, which is key for technologies

1⫻10−3

Vd = 1.2 V

1⫻10−4 1⫻10−5

Vd = 0.1 V

Ids (A)

1⫻10−6 1⫻10−7 1⫻10−8

NFET

PFET

1⫻10−9

Lmin = 0.13 µm

1⫻10−10 1⫻10−11 1⫻10−12 1⫻10−13 −1.5

−0.5

0.5

1.5

V gs (V)

FIGURE 3.6.7 Subthreshold characteristics of generic 0.13-mm gate length CMOS integrated with a SiGe npn transistor (fT and fmax >200 GHz).

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-291

having a boron-doped silicon or silicon germanium base where the final base width was largely determined by subsequent thermal budget. The situation is different for a carbon-doped SiGe base profile since the use of carbon co-doping to arrest boron diffusion provides a level of independence from any subsequent thermal budget without compromising bipolar performance. However, while the design of the bipolar is less constrained, the CMOS is now limited by the thermal budget bake used to condition the surface prior to SiGe deposition. The optimization of thermal budget must strike a balance between CMOS performance and bipolar yield. Incomplete surface conditioning results in epi defectivity. This process is thermally activated with an activation energy of approximately 1.1 eV. As the footprint of the bipolar is reduced, some reduction in thermal budget will be possible. For example, shrinking the device area by half but keeping defectivity constant could allow nearly a 1008C reduction in bake temperature. Improvements of ex-situ wet processes and in-situ techniques for pre-cleaning and a reduction in active area due to lateral scaling can make it easier to integrate advanced SiGe devices with scaled CMOS.

SiGe npn Manufacturability A key to manufacturability of SiGe technology is the reuse of high-volume CMOS infrastructure. The maturity of process equipment, the high level of factory automation for recipe download and wafer handling, the yield management discipline, and the mechanisms for continuous improvement make it possible to deliver high-quality wafers in complex process technologies. For similar process complexity, as measured by the number of critical photomask layers or the number of process steps, the manufacturing cost and fab yield is comparable regardless of the technology specifics. It is the commitment to establishing process modules that are within the capability of the equipment set that makes it possible to deliver SiGe technology that is as repeatable and cost-effective as mainstream CMOS. RT-CVD has become the most commonly used process for silicon germanium epitaxy due to the commonality of equipment platforms with other production silicon technologies, and the advantages of single-wafer tools for small lot processes in the high mix manufacturing environment typical of many fabs. Single-wafer RT-CVD tools are used for process recipes such as epitaxial silicon growth on silicon substrates, deposition of heavily doped polycrystalline films, and selective silicon-raised source–drain structures. High-quality SiGe epitaxy required the addition of appropriate gas lines, procedures for minimizing oxygen and carbon contamination, and a redesigned wafer susceptor to achieve production worthy results. Focused efforts on both ex-situ and in-situ pre-clean capabilities were necessary to migrate from initial device level results to attainment of low defect density and high yield for typical levels of BiCMOS integration. Though usually limited to approximately 10,000 bipolar transistors and 250,000 CMOS gates for the integration of many analog/RF functions, the 0.18-mm technology must support upwards of 30,000 bipolar transistors and 1.5 million CMOS gates for practical designs. The ability to perform in-line measurement of SiGe epi thickness, germanium content, and boron doping level is required to establish typical production control charts. Spectroscopic ellipsometry can be used on production wafers to monitor SiGe epi thickness, as shown in Figure 3.6.8a. Demonstrated control of 1.64% 1-sigma variation provides feedback on the epi process. Measurement of poly thickness and in-line sheet resistance closes the loop for day-to-day SiGe manufacturing. Process variation related to the emitter formation, such as emitter pre-clean, in-situ poly doping, and final rapid thermal anneal, adds to the SiGe bipolar variability. Control of all of these parameters translates into resistances and vertical doping profiles that determine the range of bipolar fT, which is shown in Figure 3.6.8b to be 2.5% 1-sigma for over 40 production lots of a technology with mean fT greater than 155 GHz.

3.6.4 Process Customization In a technology landscape where standardization is accepted as the most straightforward route to economies of scale, the modularity of Jazz technology stands as an example of mass customization.

© 2006 by Taylor & Francis Group, LLC

3.6-292

The Silicon Heterostructure Handbook

SiGe Epi thickness (Angstroms)

460

USL

450 440 430 Epi in-line measurement

420 410

LSL

400 0

10

20

(a)

30

40

Sampled lots

240

fT fmax (GHz)

220 220 180 160 140

fT fmax

120 100 0 (b)

10

20

30

40

Sampled lots

FIGURE 3.6.8 (a) In-line measurement of SiGe epi thickness for a 40 lot sample of 0.18-mm production wafers. (b) Control of process parameters related to bipolar performance is indicated by small fT and fmax variation for a sample of production lots.

This approach requires rethinking all elements of technology delivery: process development, design kits, design libraries, and manufacturing control systems.

Wireless Technology Wireless applications require high-performance bipolar transistors with high-quality passives, and CMOS density suitable for moderate levels of mixed-signal and logic integration. As the integration of multistandard and multifunction devices in analog/RF subsystems is addressed, higher voltage CMOS and bipolar device options are added to enable integration of power management and power amplification functions. This is achieved in a wireless focused version of the Jazz 0.18-mm SiGe BiCMOS (SiGe90) process by adding modules that meet RF subsystem requirements, such as high-Q capacitors, inductors, and varactors that enable improved RF performance and reduced die size. For handset transceivers, 1.8 V CMOS is not generally required as large digital blocks are often placed on a separate base-band chip. Thus, a single-gate 3.3 V MOS transistor option is available in SiGe90 to reduce mask count and cost. Deep-trench isolation can be removed as most RF blocks (outside of possibly the prescaler) make use of larger devices that do not benefit as much from use of deep trench and are not as sensitive to collector–substrate capacitance. Also, a transistor with 155 GHz peak fT is not relevant for 2–5 GHz applications that typically operate at lower current densities. Because of low parasitics, the higher BVceo devices still maintain a high fmax and provide very good noise and low-current performance. Three different top via and thick metal module options are available for usage depending on the cost, integration level, and inductor performance requirements. A module with 3-mm deep top via and

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Jazz

3.6-293

5.2-mm thick aluminum offers a significant enhancement in inductor performance or reduction in inductor area for the same level of performance. A 1 kOhm/sq p-type poly resistor provides footprint and matching suitable for 2 to 6 GHz RF circuit design. Upgrade of the MIM capacitor to 2.0 fF/-mm2, or 4.0 fF/mm2 in its stacked topology, reduces capacitor area by using a scaled version of a nitride dielectric.

High Data Rate and High-Frequency Technology To enable implementation of circuits with data rates above 10 Gb/sec or frequencies up to 60 GHz, a fully featured version of the Jazz 0.18-mm SiGe BiCMOS process, SiGe120, is offered. The device set includes dual-gate 1.8/3.3 V CMOS and three SiGe npn transistors with fT of 155/78/38 GHz, four layers of standard metalization for dense digital logic and embedded SRAM, low-capacitance thin film metal resistors for high-frequency operation, a linear MIM capacitor with high Q, and two thick layers of aluminum (1.5 and 3.0-mm) for implementation of transmission lines and inductors. The addition of a higher performance SiGe npn transistor module with peak fT over 200 GHz (SiGe200), and higher fT and fmax over a large range of collector current, enables lower power circuits for networking applications, emerging wireless data standards from 20 to 60 GHz, and even collision-avoidance radar above 60 GHz for automobiles.

3.6.5 Summary Adding new features that build on established technology has resulted in a family of processes that offer a combination of active devices, passive components, and interconnect schemes specifically optimized for different types of products. In the mobile phone, extending the voltage capability of the transistor to 5 to 8 V to meet the requirements of RF power control, power management, and low drop out regulation enables higher levels of analog and RF product integration. High-density passives to scale down capacitor and inductor area can be more important to the reduction of die size than the scaling of digital blocks. Use of only the necessary process modules reduces overall manufacturing complexity, and ultimately cost of a design for a specific market segment. This specialty roadmap for analog and RF functional scaling will repeat with the maturation of subsequent generations of CMOS technology. There will be less emphasis on linewidth reduction and more effort related to the reuse of advanced CMOS process equipment for new materials and structures that advance the functional scaling of highly integrated mixed-signal, analog, and RF products.

Acknowledgments The author would like to thank the entire Jazz Semiconductor team for their technology development efforts, as well Marco Racanelli and Greg U’Ren for their direct contributions to this manuscript.

References 1. M Racanelli, Z Zhang, J Zheng, A Kar-Roy, P Joshi, A Kalburge, L Nathawad, M Todd, C Ukah, C Hu, C Compton, K Schuegraf, P Ye, R Dowlatshahi, G Jolly, and P Kempf. BC35: a 0.35 mm, 30 GHz, Production RF BiCMOS Technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 125–128. 2. A Chantre, M Marty, JL Regolini, M Mouis, J de Pontcharra, D Dutartre, C Morin, D Gloria, S Jouan, R Pantel, M Laurens, and A Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–100. 3. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freemen, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest International Electron Devices Meeting, San Francisco, 2002, pp. 771–774.

© 2006 by Taylor & Francis Group, LLC

3.6-294

The Silicon Heterostructure Handbook

4. M Racanelli and P Kempf. SiGe BiCMOS technology for communication systems. Extended Abstracts of the International Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 286–287. 5. M Racanelli, K Schuegraf, A Kalburge, A Kar-Roy, B Shen, C Hu, D Chapek, D Howard, D Quon, F Wang, G U’Ren, L Lao, H Tu, J Zheng, J Zhang, K Bell, K Yin, P Joshi, S Akhtar, S Vo, T Lee, W Shi, and P Kempf. Ultra high speed SiGe npn for advanced BiCMOS technology, International Electron Devices Meeting Washington, 2001, pp. 01-337–15.3.4. 6. K Oda, E Ohue, I Suzumura, R Hayami, A Kodama, I Shimamoto, and K Washio. Self-aligned selective-epitaxial-growth Si1xy GexCy HBT technology featuring 170-GHz fmax. International Electron Devices Meeting, Washington, 2001, pp. 2–5. 7. M Racanelli and P Kempf. SiGe BiCMOS technology for communication products, Custom Integrated Circuits Conference, San Jose, 2003, pp. 331–334. 8. M Kamat, P Ye, Y He, B Agarwal, P Good, S Lloyd, and A Loke. High performance low current CDMA receiver front end using 0.18-mm SiGe BiCMOS. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 23–26. 9. P Ma, M Racanelli, J Zheng, and M Knight. A 1.4 mA and 3 mW, SiGe90, BiFET low noise amplifier for wireless portable applications. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 237–240. 10. P Ye, B Agarwal, M Reddy, L Li, J Cheng, PC Mudge, E McCarthy, and SL Lloyd. High performance circuits in 0.18-mm SiGe BiCMOS process for wireless applications. IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 329–332. 11. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. 25th GaAs IC Symposium, San Diego, 2003, pp. 183–186.

© 2006 by Taylor & Francis Group, LLC

3.7 Industry Examples at the State-of-the-Art: Hitachi

Katsuyoshi Washio Hitachi Ltd.

3.7.1 3.7.2 3.7.3 3.7.4 3.7.5

Introduction............................................................... 3.7-295 SiGe HBT Technologies ............................................ 3.7-296 SiGe BiCMOS Technologies ..................................... 3.7-300 Interconnection and Passive Elements .................... 3.7-303 Summary .................................................................... 3.7-305

3.7.1 Introduction High-speed monolithic integrated circuits (ICs) and large-scale ICs (LSIs) are the key components for multigigabit data communication systems and wide-bandwidth radio communication systems. Such systems include backbone networks, intercity communication networks, local area networks, and Ethernet for data communications, and microwave and millimeter-wave mobile networks, fixed wireless access, and intelligent transport systems for radio communications. To meet the growing demand for such systems, both high-speed digital operation with sophisticated functions and high-frequency analog operation should be implemented. From this point of view, high-speed SiGe HBT and SiGe HBT with CMOS (BiCMOS) technologies are the most promising candidates to meet these requirements. This is because SiGe HBTs with a sub-5-psec ECL-gate delay and cutoff frequency about 200 GHz have been successfully demonstrated and can be fabricated by the well-established Si process, which is fully compatible with the CMOS process. For the widespread application of these devices in high-speed digital and RF analog ICs/LSIs, SiGe HBTs must be fabricated at a high yield. Moreover, high-quality passive elements, including high-precision resistors, a high-Q varactor, an MIM capacitor, and high-Q inductors, should also be available for integration on a chip. Consequently, technologies for fabricating a self-aligned SiGe HBT by selective epitaxial growth (SEG) and SiGe BiCMOS have been developed. This self-aligned SEG concept can be expected to achieve highspeed and low-power performance as a result of small parasitic resistances and capacitances. A selfaligned SEG SiGe HBT that has shallow-trench and dual-deep-trench isolations (DTIs) and Ti–salicide electrodes was fabricated on a 200-mm wafer line. The fabrication process is almost completely compatible with the 0.2-mm BiCMOS technology that is applied in fabricating fast-cache memory chips. To improve cutoff frequency, maximum oscillation frequency, and ECL-gate delay, optimization of the width of the SiGe SEG layer and the thickness of the Si-cap layer, incorporation of C to suppress B out-diffusion, and application of thin and heavily-boron-doped base have been investigated. In the case of SiGe BiCMOS technology, CMOS devices with gate lengths of 0.25 mm to 80 nm were integrated. For both the SiGe HBT and BiCMOS technologies, a four-level or five-level metal layer structure for interconnection was formed by chemical–mechanical polishing (CMP). Concerning the integration 3.7-295 © 2006 by Taylor & Francis Group, LLC

3.7-296

The Silicon Heterostructure Handbook

of high-quality passive elements, a high-precision poly-Si resistor with a ‘‘quasi-layer-on-layer’’ structure, a high-Q varactor constructed of a SiGe-base and a Si-collector junction, an MIM capacitor formed between the first and second metal layers by plasma SiO2 as an insulator, and a high-Q inductor fabricated by using the fourth metal layer are available for integration on the same chips as active devices.

3.7.2 SiGe HBT Technologies A scanning electron microscopy (SEM) cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT is shown in Figure 3.7.1, including an enlarged view of the active region, the key part of the SiGe HBT [1]. The 0.6-mm-wide Si-cap/SiGe-base multilayer was selectively grown in self-alignment with the 0.2-mmwide emitter by ultrahigh vacuum/chemical vapor deposition (UHV/CVD) [2]. A poly-Si-assisted selfaligned SEG (PASS) structure was applied to provide a good link between the intrinsic SiGe and extrinsic

Base

Emitter

Collector 1st metal

Ti salicide

W 1 µm

Shallow trench Dual deep trench

IDP 0.2 µm Base poly Si

Si/SiGe SEG Poly-SiGe

Buffer poly-Si

FIGURE 3.7.1 An SEM cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT with an enlarged active region, the key part of the SiGe HBT. A 0.6-mm-wide Si-cap/SiGe-base multilayer self-aligned to a 0.2-mm-wide emitter was selectively grown by UHV/CVD. A poly-Si-assisted self-aligned SEG (PASS) structure, shallow-trench and dualdeep-trench isolations, and Ti–salicide electrodes were applied. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Hitachi

3.7-297

poly-Si bases [3, 4]. In the PASS structure, a poly-SiGe base contact was grown, at the same time as the intrinsic SiGe base, around the buffer poly-Si and beneath the extrinsic base poly-Si. This self-aligned active-region structure enabled both low collector capacitance and low base resistance. Furthermore, 0.4-mm-deep shallow-trench isolation (STI) and 0.6-mm-wide 3-mm-DTIs were used to reduce the parasitic capacitances of the collector and substrate, respectively. Ti–salicide layers, with a sheet resistance of 3 V/sq. and contact resistance of about 25 V mm2, were formed on all the electrodes to reduce their parasitic resistances. The process steps in the fabrication of the self-aligned SEG SiGe HBT are explained as follows (Figure 3.7.2). An nþ buried layer (BL) was formed by ion implantation of antimony followed by annealing. A 0.3-mm-thick Si epitaxial layer was then formed. Next, the shallow- and dual-deep-trench grooves for the isolation were formed and filled up with SiO2 by planarization with CMP. Next, the intrinsic region was covered by the three successively deposited films of Si3N4, poly-Si, and SiO2. This multilayer was used to form the PASS structure. An amorphous Si film for the base poly-Si and a thick SiO2 film were then deposited, and a window to the intrinsic region was opened in these films by etching. The first selectively implanted collector (SIC1) region was then formed by phosphorus-ion implantation through the multilayer and into the Si epitaxial layer. After that, the SiO2 film remained on the sidewall of the window after reactive-ion etching (RIE). The Si3N4 film was then deposited, and it remained on the sidewall of the window. At that time, the top film of the multilayer, the Si3N4, was etched. After that, the remaining films of multilayer, poly-Si and SiO2, were selectively etched. The Si3N4 film was then removed from the sidewall, and the window in the Si3N4 film of the multilayer was enlarged by wet side-etching. Next, the Si-cap/SiGe-base multilayer was selectively grown by UHV/CVD using Si2H6, GeH4, and B2H6 source gases at 5508C for the SiGe layer and Si2H6 at 5808C for the Si layer. The SEG layer consisted of a 15-nm-thick Si cap, 20-nm-thick

FIGURE 3.7.2 Process steps for fabricating the self-aligned SEG SiGe HBT. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-298

The Silicon Heterostructure Handbook

Si1
xGex , 40-nm-thick Si0.85Ge0.15, and 10-nm-thick Ge-retrograded (from 15% to 0) Si1
xGex . A 15nm-thick 2  1019 cm
3 boron-doped Si1
xGex layer was formed as the intrinsic base. The poly-SiGe base contact was formed simultaneously with the intrinsic SEG, and this formation was assisted by the middle film of the multilayer, the poly-Si (which was used as a buffer). Next, phosphorus ions were implanted in the lower part of the SEG layer to form the second SIC region (SIC2). Double selective implantations of phosphorous were applied to increase the collector-doping level to about 1  1018 cm
3. Thin SiO2 and in situ phosphorus-doped poly-Si (IDP) layers were deposited, and the IDP film remained on the sidewall of the window. After an emitter area had been opened by wet etching of the thin SiO2, a second IDP layer was deposited. A shallow emitter with a junction depth of about 20 nm was formed by diffusion from the IDP layers into the Si-cap layer at 9008C for 30 sec. Next, Ti–salicide layers on all electrodes of the emitter, base, and collector were formed simultaneously in a self-aligned manner. The SiGe HBT was fabricated on a 200-mm wafer line and the process to fabricate the SiGe HBTs is, with the exception of the SEG, almost the same as the 0.2-mm BiCMOS process [5]. The process is thus completely compatible with BiCMOS technology. The designed profile of the SiGe layer after SEG, featuring dual plateaus with an intermediately Gegraded slope (DPIG), is shown in Figure 3.7.3. The Ge profile of the SiGe layer was designed as follows: two plateaus with Ge contents of 10% (on the surface side) and 15% (on the substrate side), a 5-nm-thick Ge-graded layer between the plateaus, and two Ge-graded layers at the interfaces with the Si-epitaxial and Si-cap layers. This DPIG Ge profile was designed to enable precise controllability of the collector current against deviation in the position of the emitter–base junction. At the end of the process, the base was about 30-nm wide, so the two plateaus and the intermediate Ge-graded layer were located in the base. Note that this layer provided an internal drift field in the conduction band and enabled a short base transit time and a high Early voltage in a similar way to the conventional graded-Ge profile. The emitter–base junction was located at the 10%-Ge plateau, and the thickness of this plateau was sufficient to suppress changes in the effective base Gummel number caused by deviation in the emitter–junction depth. The SiGe HBT, with an emitter area AE of 0.2  2 mm, exhibited good I–V performance with a high current gain of 1400. The ideality factor of the base current IB was 1.10, and the base-recombination current was below 10 pA. The HBT yield, measured from 4000 parallel-connected transistors, was more than 99.9993%. These DC characteristics show that no defects were created in the strained Si/SiGe multilayer during the thermal cycles for the HBT formation. The slope of the Arrhenius plot of the normalized current gain indicates that the Ge-induced bandgap reduction for the strained SiGe base layer

NB = 2
1019 cm−3 w B = 15 nm

B

Ge content (%)

15

Ge2

10

Ge1 SEG I/F

5

0 0

20

40 60 Depth (nm)

80

100

FIGURE 3.7.3 A schematic view of the designed profile, featuring dual plateaus with intermediate Ge-graded slope (DPIG) for the SiGe layer after SEG. Ge1 is the Ge content of the lower plateau and Ge2 is that of the upper plateau. At the end of the process the base was about 30 nm wide, so both plateaus and the intermediate Ge-graded layer were located in the base. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-299

Industry Examples at the State-of-the-Art: Hitachi

was 110 meV, which verifies that there was no relaxation in the SiGe layer. The typical transistor characteristics of a SiGe HBT with an emitter area of 0.2  2 mm are summarized in Table 3.7.1. Figure 3.7.4 shows the dependence of the differential ECL gate-delay time on the switching current as measured from 53-stage ring oscillators with a fan-in and a fan-out of 1 at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The SiGe HBTs have an emitter area of 0.2  2 mm. A minimum ECL-gate delay time of 5.5 psec was measured at a switching current of 2 mA. Analysis of the delay components that made up this delay time showed that the contributions of load resistance, base resistance, forward transit time, and other factors were 1.48, 2.39, 0.93, and 0.70 psec, respectively. The power-delay product of the ECL circuit composed of a SiGe HBTwith an emitter area of 0.2  0.5 mm was low, i.e., 4.4 f J. The fast- and low-power performance of the ECL gate was attributed to the low collector capacitance and the low substrate capacitance enabled by the shallow-trench and dual-DTIs, high fT and fmax of the fully selfaligned SEG SiGe HBT structure, and the low parasitic resistance of the Ti–salicide electrodes. TABLE 3.7.1 Typical SiGe HBT Characteristics with an Emitter Area of 0.2  2 mm 0.2  2 mm2 1400 1.9 V 3.0 V 6.3 V 90 V 3.6 fF 1.8 fF 122 GHz 163 GHz 5.5 ps

Emitter area Current gain BVCEO BVCER BVCBO Base resistance Collector capacitance Substrate capacitance Cutoff frequency Max. oscillation frequency ECL min. gate delay

Source : From K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.

30 Differential ECL gate AE = 0.2
2 µm

53-stage R. O. 10

50 mV/div.

ECL gate delay time (ps)

20

VL = 250 mV

8 500 ps/div. 6 5.5 ps 4 0.3

3 1 Switching current (mA)

10

FIGURE 3.7.4 Dependence of the differential ECL gate-delay time on the switching current as measured from ring oscillators. Each SiGe HBT had an emitter area of 0.2  2 mm and ran at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The fan-in and fan-out were 1. The output waveform of a 53-stage ECL ring oscillator as measured at a switching current of 2 mA is also shown. A minimum ECL gate-delay time of 5.5 psec was measured. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-300

The Silicon Heterostructure Handbook

Optimization of the device structure and the intrinsic impurity profile were investigated [6, 7]. They are related to the collector–base and emitter–base junctions of the self-aligned SEG SiGe HBTs by varying the width of the SiGe SEG layer and the thickness of the Si-cap layer, respectively. The incorporation of carbon to suppress boron out-diffusion of the base was performed [8]. This is effective both to improve high-speed performance and to reduce fluctuations in device performance by alleviating the lattice strain. Furthermore, a thin and heavily-boron-doped base toward a thickness of 1 nm is applied [9]. As a result, a cutoff frequency of 174 GHz, a maximum oscillation frequency of 204 GHz, and an ECL-gate delay of 4.8 psec were obtained. For low-power and high-speed operation, a scaled-down SiGe HBT, structurally optimized for an emitter scaled-down towards 100 nm, was also developed [10].

3.7.3 SiGe BiCMOS Technologies A cross-sectional SEM image of the 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor, and a polySi resistor on an SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm) is shown in Figure 3.7.5 [11]. The SiGe HBT was fabricated in the manner described above. A 4  1019 cm
3 boron-doped 10-nm-thick (as SEG) Si0.95Ge0.05 layer was used as the intrinsic base. A 0.5-mm-wide DTI reaches the buried SiO2. The drawn CMOS gate lengths were 0.25 mm (nMOS) and 0.3 mm (pMOS). The gate electrode was constructed of a layer of 50-nm-thick TiSi2 (formed simultaneously with the other electrodes) stacked on 300-nm-thick nþ-doped poly-Si. The process sequence of SiGe BiCMOS is shown in Figure 3.7.6. The standard steps of the bipolar fabrication process were carried out from the formation of the nþ buried collector layer to the deep trench isolation. A 0.3-mm CMOS process module was then inserted. The thickness of the gate oxide was 6.5 nm. A poly-Si resistor was also formed from nþ-doped gate poly-Si for low sheet resistance (LR). After CMOS formation, the process sequence returns to continue with the bipolar process sequence. During the fabrication of self-aligned SEG SiGe HBTs, the CMOS and poly-Si resistor areas are covered by SiO2. A poly-Si layer was deposited and patterned. Boron and germanium ions were then implanted

M4 (3µm)

M3 MIM-C M2 M1

via TiSi2 poly Si-R

SiO2 (0.3 µm)

SiGe HBT

HRS (1 kΩcm)

nMOS

pMOS

5 µm

FIGURE 3.7.5 Cross-sectional SEM image of a 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor (drawn gate lengths were 0.25 mm for nMOS and 0.3 mm for pMOS), and a poly-Si resistor on a 200-mm SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm). A four-level metal (M1–M4) layer structure was used for interconnection. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-301

Industry Examples at the State-of-the-Art: Hitachi

SiGe HBT n+ buried collector (Sb+) n− epitaxial growth (0.3 µm) Shallow (0.35 µm) trench isolation Collector plug Deep (1µm) trench isolation MR & HR poly-Si (w/ Ge I/I) Base poly-Si (0.2 µm) Emitter window & SIC1 SiGe SEG & SIC2 Emitter poly-Si (in-situ P-doped)

CMOS n & p well I/I Gate poly-Si (LR) PTS I/I & LDD n & p S/D I/I

Ti-salicide Contact & W plug 1st metal & via MIM capacitor 2nd to 4th metal

FIGURE 3.7.6 Process sequence for 0.2-mm SOI/HRS SEG SiGe HBT/CMOS. A 0.3-mm CMOS process module was inserted after formation of the trench isolations. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

to form pþ poly-Si resistors for medium (MR) and high (HR) sheet resistances. After the deposition of oxide, a 0.2-mm-thick poly-Si layer was formed for the base electrode. Phosphorous ions were implanted after the emitter window opening to form SIC1 and after the SiGe SEG to form SIC2. This can provide optimized collector profiles for both high-speed and high-voltage HBTs. The formation of the emitter poly-Si electrode is followed by the process sequence of an interconnection process module. Numbers of masks used were ten for the SiGe HBTs, ten for the CMOS transistors, and three for the poly-Si resistors. The effectiveness of the DPIG Ge profile was confirmed by the dependence of the current gain on Ge1, the Ge content of the lower plateau. As a result, even for HBTs with various Ge2 (the Ge content of the upper plateau) in the range from 7.5% to 15%, the collector current was well controlled by Ge1 and was independent of Ge2. This indicates that the collector current is mainly determined by the bandgap narrowing of the lower plateau. Therefore, the lower plateau suppresses the change in the effective base Gummel number, which occurs with the conventional graded-Ge profile because of the fluctuation in the emitter–junction depth. Good I–V performance, with a current gain of about 300, is confirmed in the Gummel plots for single and 104 parallel-connected HBTs with an emitter area AE of 0.2  1 mm. The averaged forward base tunneling current was about 2 pA/HBT. The respective ideality factors of the collector current IC and base current IB were 1.007 and 1.075. The current gain was higher than 100 in the zlow-collector-current region up to 1 nA. The HBT yield, as measured from sets of 104 HBTs connected in parallel, was about 99.9997%, which means the defect density was about 2000 defects/cm2 under the assumption of a relaxed-limited yield. This means that the limit on the number of HBTs that may be integrated is about 105. The reliability under the forward- and reverse-bias stressing was investigated and compared with manufactural Si BJTs with guaranteed 10-year operation as a control. No change in the collector and base current were viable at JC up to 60 mA/mm2 under forward-bias stress, and a similar behavior of the base current to that of a Si BJT under reverse-bias stress up to a VEB of 3.5 V were observed. As a result, high reliability of SiGe HBTs was confirmed. The HBT characteristics, breakdown voltage, and high-frequency performance were controlled by the collector sheet concentration NS through the double selective phosphorus implantations in the 0.3-mmthick Si epitaxial layer and in the undoped SiGe. The breakdown voltage BVCEO was 2.5 V for the HSHBT and 3.9 V for the HV-HBT. The high Early voltage VA of more than 100 V for both HBTs indicates that the collector current was determined by the drift field created by the bandgap grading. The dependence of the cutoff frequency fT and maximum oscillation frequency fmax on the collector current

© 2006 by Taylor & Francis Group, LLC

3.7-302

The Silicon Heterostructure Handbook

for the HS-HBT with an emitter area AE of 0.2  1 mm and the HV-HBT with an AE of 0.2  4 mm are shown in Figure 3.7.7. The peak fT of the HS-HBT with an emitter area AE of 0.2  1 mm and the HVHBT with an AE of 0.2  4 mm were 76 and 47 GHz, respectively. The peak fT for the HV-HBT was about 60% of that for the HS-HBT, and the collector current density at the peak fT for the HV-HBT was about one fourth of that for the HS-HBT. The dependence of the peak fT on BVCEO was also investigated, and their product was about 190 GHz V. The peak fmax for the HS-HBT was 180 GHz and even that for

100 HS-HBT AE = 0.2
1 µm

Cutoff frequency (GHz)

80

60

40 HV-HBT AE = 0.2
4 µm

20

0 0.1

0.3

1

3

Collector current (mA)

(a)

40

150

HS-HBT AE = 0.2
1µm

30

10

10 100 Frequency (GHz)

40

50

0.3

fmax 180 GHz

VCE = 2 V IC = 0.7 mA 1

HV-HBT AE = 0.2
4 µm

U

MSG/ MAG

20

0 100

0 0.1 (b)

MSG/MAG, U (dB)

AE = 0.2
1 µm HS-HBT

1

Collector current (mA)

3

MSG/MAG, U (dB)

Maximum oscillation frequency (GHz)

200

HV-HBT AE = 0.2
4 µm

30

U

20

MSG/ MAG

10

VCE = 2 V IC = 0.7 mA

0 1

fmax 125 GHz

10 100 Frequency (GHz)

FIGURE 3.7.7 Dependence of the cutoff frequencies (a) and maximum oscillation frequencies (b) on collector current for the HS-HBT with an emitter area AE of 0.2  1 mm and the HV-HBT with an AE of 0.2  4 mm. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.7-303

Industry Examples at the State-of-the-Art: Hitachi TABLE 3.7.2 Typical Transistor Parameters for the HS-HBT with an Emitter Area AE of 0.2  1 mm and the HV-HBT with an AE of 0.2  4 mm

WE (mm) LE (mm) hFE n VA (V) BVCEO (V) BVCBO (V) RB (V) RE (V) CJE (fF) CJC (fF) CSUB (fF) fT (GHz) fmax (GHz) min ECL tpd (psec)

HS

HV

0.2 1 300 1.007 >100 2.5 10.0 120 27 3.7 1.9 1.1 76 180 7.8

0.2 4 300 1.007 >100 3.9 11.5 45 9 13.4 3.4 2.2 47 125 –

Source: From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

the HV-HBT was 125 GHz, thanks to both the low collector capacitance, which was a result of the selfaligned SEG structure and optimized collector profile, and the low base resistance. These results indicate that both HBTs are very suitable for high-frequency analog applications. Typical transistor parameters for the HS-HBT with an emitter area AE of 0.2  1 mm and the HV-HBT with an AE of 0.2  4 mm are summarized in Table 3.7.2. Here, CSUB was reduced to about 60% of that without SOI [12]. This is because CSUB is given by the series connection of the depletion capacitance under the nþ buried collector and the capacitance of the buried oxide. To improve the functionality, scaled CMOS with gate lengths of 0.18 mm [13], 0.13 mm [14], and 80 nm [15] in SiGe BiCMOS technologies have been advanced by optimizing process flow and reducing thermal budgets.

3.7.4 Interconnection and Passive Elements A cross-sectional view of the four-level structure of metal layers with an MIM capacitor is also shown in Figure 3.7.5. The structure of metal layers for use in interconnection was fabricated by applying CMP to planarize the tungsten deposited for the 0.5-mm-wide contact plugs and 0.6  0.6-mm via holes and to planarize the plasma–SiO2 interlayer insulators. All of the metal layers were multilayered structures of Al, Ti, and TiN. A concave MIM capacitor with a capacitance of 0.7 fF/mm2 was formed between the first- and second-level metal layers by using a 50-nm-thick layer of plasma SiO2 as an insulator. The third- and fourth-level (3-mm-thick Al) metal layers made up high-Q spiral inductors. Eleven masks were used for the four-level structure of metal layers for interconnection, including the MIM capacitor. Precise resistors were formed from pþ poly-Si, with a ‘‘quasi-layer-on-layer’’ structure fabricated by Ge implantation, for medium and high sheet resistances (MR, HR) in the SiGe BiCMOS. A cross-sectional TEM image of a precise poly-Si resistor is shown in Figure 3.7.8. By using high-dose Ge implantation, roughly the upper half of the poly-Si layer with small grains as deposited (deposition temperature TD was higher than 6008C) became amorphous. It then changed to large-grain poly-Si by recrystallization after annealing. The ‘‘quasi-layer-on-layer’’ structure was thus fabricated. The temperature coefficient TC of resistance for large-grain poly-Si is positive, while that for small-grain poly-Si is negative. Therefore, these opposite characteristics act to cancel out the temperature dependence of the resistance. Further-

© 2006 by Taylor & Francis Group, LLC

3.7-304

The Silicon Heterostructure Handbook

Poly-Si deposition (TD>600C) Small-grain poly-Si

B and Ge I/I (high dose) Amorphous Si Small-grain poly-Si

Annealing (recrystallization)

Positive TC

Large-grain amorphous poly-Si Si Small-grain poly-Si Negative TC

Large grains

Small grains

50 nm FIGURE 3.7.8 Cross-sectional TEM image of a precise poly-Si resistor formed from pþ poly-Si with a ‘‘quasi-layeron-layer’’ structure fabricated by Ge implantation, for both medium sheet resistance (MR) and high sheet resistance (HR) in the SiGe BiCMOS. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

more, this ‘‘quasi-layer-on-layer’’ structure made the precise control of the sheet resistance possible; the sheet resistance was mainly determined by the thickness of the upper large-grain poly-Si layer with low resistivity, and its thickness could be controlled well by the Ge-implantation energy. The parameters of the passive elements are summarized in Table 3.7.3. An ordinary nþ poly-Si resistor, LR (low sheet resistance of 65 V/sq.), had a temperature coefficient of 600 ppm/8C. On the other hand, both types of pþ poly-Si resistors with a ‘‘quasi-layer-on-layer’’ structure, MR (medium sheet resistance of 220 V/sq.) and HR (high sheet resistance of 635 V/sq.), had low temperature coefficients of 330 and 180 ppm/8C, respectively. The MIM capacitor with an area of 50  100 mm and a capacitance of 4.2 pF, which is usually used to stabilize the supply voltage, had an adequate Q of 13 at 10 GHz. In 10 parallel-connected varactors, each with a SiGe-base and Si-collector junction area of 2.3  2.3 mm, the ratio of Cmax to Cmin for VCB of 0 to 3 V was 1.8 and Q was 45 at 10 GHz and a VCB of 1.5 V. This high-Q varactor is applicable to oscillators with a high-purity signal spectrum for use in mobile communications. A three-turn square (132 mm on the outer sides) spiral inductor with a cavity at the center and a line width/line-to-line space of 6/3 mm was formed on a standard low-resistivity substrate (LRS) in the SiGe HBT process. It had L value of 1.36 nH and Q of 8.8 at 5.8 GHz, and L of 1.45 nH and Q of 15.1 at 10 GHz. The octagonal spiral inductor on the SOI/HRS was compared with that on an SOI/LRS. The width and spacing were 9 and 3 mm, respectively. The frequency dependence of the

© 2006 by Taylor & Francis Group, LLC

3.7-305

Industry Examples at the State-of-the-Art: Hitachi TABLE 3.7.3 Resistor

Passive-Element Parameters nþ poly (LR) pþ poly (MR) pþ poly (HR)

Capacitor

MIM

Varactor

MOS SiGe/Si

Inductor

Oct. spiral

65 V/sq. 600 ppm/8C 220 V/sq. 330 ppm/8C 635 V/sq. 180 ppm/8C 0.7 fF/mm2 13 Q(10 GHz) 4.7 fF/mm2 1.8 (Cmax/Cmin) 45 Q(10 GHz) 0.95/19 nH/Q (10 GHz)

Source : From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

inductance was the same on the HRS and LRS; however, Q of the HRS became higher at frequencies above 5 GHz, and Q at 15 GHz on the HRS was about twice that on the LRS. These results indicate that the high-resistivity substrate is effective in reducing conductive loss through the Si substrate in the microwave band. The octagonal spiral inductor on the HRS, with an L value of 0.95 nH, showed a highQ of 19 at 10 GHz.

3.7.5 Summary Self-aligned SiGe HBT and BiCMOS technologies have been developed. A Si-cap/SiGe-base multilayer fabricated by the SEG method was applied to improve both high-speed and low-power performance of the SiGe HBTs. The process is almost completely compatible with well-established Si BiCMOS technology, and the SiGe HBT and BiCMOS were fabricated on a 200-mm wafer line. To meet the demand for the integration of sophisticated functions, high-quality passive elements, including a high-precision poly-Si resistor, a high-Q varactor, an MIM capacitor, and a high-Q spiral inductor, have also been developed.

Acknowledgments The author would like to express his sincere thanks to Dr. A. Anzai, Dr. Y. Hatta, and H. Hosoe at the Hitachi Device Development Center (HDDC), and Dr. O. Kanehisa, Dr. K. Seki, and K. Kimura at the Hitachi Central Research Laboratory (HCRL) for their encouragement. The author would also like to express his sincere thanks to Dr. T. Onai, E. Ohue, K. Oda, Dr. M. Kondo, H. Shimamoto, M. Tanabe, R. Hayami, Dr. Y. Kiyota, I. Suzumura, Dr. M. Miura, A. Kodama at HCRL, and to T. Harada, K. Mikami, T. Hashimoto, S. Wada, T. Tominari, K. Tokunaga at HDDC for their extensive contributions throughout this work.

References 1. K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. A 0.2-mm self-aligned selective-epitaxial-growth SiGe HBT featuring 107-GHz fmax and 6.7-ps ECL. IEEE Trans. Electron Devices 48:1989–1994, 2001. 2. K. Oda, E. Ohue, M. Tanabe, H. Shimamoto, T. Onai, and K. Washio. 130-GHz fT SiGe HBT technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 1997, pp. 791–794.

© 2006 by Taylor & Francis Group, LLC

3.7-306

The Silicon Heterostructure Handbook

3. K. Washio, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, T. Onai, and M. Kondo. A selectiveepitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay. IEEE Trans. Electron Devices 46:1411–1416, 1999. 4. K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Kondo, S. Kondo, Y. Homma, N. Owada, and T. Ikeda. A 0.2-mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 209–212. 6. E. Ohue, R. Hayami, K. Oda, H. Shimamoto, and K. Washio. 5.3-ps ECL and 71-GHz static frequency divider in self-aligned SEG SiGe HBT. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 26–29. 7. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, and H. Shimamoto. Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic Frequency Dividers. IEEE Trans. Electron Devices 49:1755–1760, 2002. 8. K. Oda, E. Ohue, I. Suzumura, R. Hayami, K. Kodama, H. Shimamoto, and K. Washio. Highperformance self-aligned SiGeC HBT with selectively grown Si1
x
yGexCy base by UHV/CVD. IEEE Trans. Electron Devices 50:2213–2220, 2003. 9. T. Tominari, S. Wada, K. Tokunaga, K. Koyu, M. Kubo, T. Udo, M. Seto, K. Ohhata, H. Hosoe, Y. Kiyota, K. Washio, and T. Hashimoto. Study on extremely thin base SiGe:C HBTs featuring sub 5-ps ECL gate delay. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 107–110. 10. K. Washio, E. Ohue, R. Hayami, A. Kodama, H. Shimamoto, M. Miura, K. Oda, I. Suzumura, T. Tominari, and T. Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Trans. Electron Devices 50:2417–2424, 2003. 11. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. 12. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Harada, and M. Kondo. 82GHz dynamic frequency divider in 5.5ps ECL SiGe HBTs. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 210–211. 13. S. Wada, Y. Nonaka, T. Saito, T. Tomonari, K. Koyu, K. Ikeda, K. Sakai, K. Sasahara, K. Watanabe, H. Fujiwara, F. Murata, E. Ohue, Y. Kiyota, H. Shimamoto, K. Washio, R. Takeyari, H. Hosoe, and T. Hashimoto. A manufacturable 0.18-mm SiGe BiCMOS technology for 40-Gb/s optical communication LSIs. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 84–87. 14. T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahara, T. Tomonari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washio, and H. Hosoe. Integration of a 0.13-mm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 779–782. 15. T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, and H. Hosoe. Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 129–132.

© 2006 by Taylor & Francis Group, LLC

3.8 Industry Examples at the State-of-the-Art: Infineon

T.F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck Infineon Technologies AG

3.8.1.

3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6

Introduction............................................................... 3.8-307 Process Concept......................................................... 3.8-308 Transistor Fabrication Process ................................. 3.8-309 Transistor Results ...................................................... 3.8-311 Additional Devices .................................................... 3.8-315 Circuit Performance .................................................. 3.8-316

Introduction

Recent advances [1–7] in state-of-the-art SiGe bipolar and BiCMOS technologies enabled impressive transistor parameters like maximum oscillation frequencies of 285 GHz [1], transit frequencies up to 350 GHz [2] and ring-oscillator gate delay times down to 3.5 psec [5, 7]. Therefore, even very highfrequency applications like wireless LANs at 60 GHz, optical communications at 80 Gbit/sec and automotive radar systems around 77 GHz, which can now only be achieved by expensive III–V technologies, seem to become feasible in a low-cost silicon-based technology in a highly integrated manner. The progress in the high-speed performance of SiGe HBTs has been achieved by impurity profile engineering in the SiGe base for improving forward transit time and base resistance as well as by the development of self-aligned transistor architectures providing low parasitic capacitances and low extrinsic series resistances. The different self-aligned emitter–base configurations, which are used in present state-of-the-art SiGe HBT technologies, are requiring either nonselective epitaxial growth (NSEG) [1, 2, 5] or selective epitaxial growth (SEG) [3, 4, 6, 7] for the integration of the SiGe base. As an example of such an advanced SiGe HBT technology, we describe here Infineon’s high-frequency SiGe bipolar technology. The SiGe technology is based on a double-polysilicon self-aligned (DPSA) transistor configuration, in which the shallow and highly boron-doped SiGe base layer is integrated by means of SEG. The first realizations of such transistors have used epitaxial silicon base layers which have been grown without Ge [8–10]. Because of the superior performance of the SiGe base over the epitaxial Si base, within the next couple of years processes for DPSA HBTs with selectively grown SiGe base layers have been developed [11–14]. Even the first of these DPSA HBTs that were fabricated in 1992 [11] exhibited a maximum oscillation frequency of 50 GHz and a ring oscillator gate delay time of 19 psec, which was state-of-the-art performance at that time. Using the DPSA HBT concept Infineon’s first SiGe bipolar technology, which has been taken into production for the wireless marketplace in the year 1999 [15], exhibited transit and maximum oscillation frequencies of about 75 GHz. In the meantime the transistor performance of DPSA HBTs with a selectively grown SiGe base could be improved considerably, resulting in bipolar and BiCMOS processes with transit and maximum

3.8-307 © 2006 by Taylor & Francis Group, LLC

3.8-308

The Silicon Heterostructure Handbook

oscillation frequencies of 200 GHz or above [3, 4, 6, 7]. These advancements have been achieved for example by improvements in shallow base formation technology, which has resulted in reduced base thickness even for significantly increased base boron doping levels, as well as by minimizing the size of the transistors for commensurate improvements of base resistance, emitter–base capacitance, and base– collector capacitance. In the following we describe the process concept, the fabrication process, and the electrical results of Infineon’s actual high-frequency SiGe bipolar technology. The technology provides a transit frequency of 200 GHz, a maximum oscillation frequency of 275 GHz, and a ring oscillator gate delay time of 3.5 psec [7]. The bipolar technology is presently under investigation for the realization of very demanding high-frequency applications like 77 GHz automotive radar and optical communications up to 80 Gbit/sec.

3.8.2.

Process Concept

A transmission electron microscopy (TEM) cross section of the npn transistor in the SiGe technology is shown in Figure 3.8.1. The transistor has a deep trench/shallow trench isolation which is commonly used in advanced SiGe HBT technologies. The transistor isolation has a completely planar surface topography which is of great advantage for the realization of small feature sizes and small lithographic alignment tolerances in order to minimize the sizes of the transistors. In addition the deep trenches are useful in enabling the realization of high transistor packing densities in circuits and also allow the realization of small subcollector dimensions for achieving low values of the collector–substrate capacitance. The transistor, which is built onto this transistor isolation, has a DPSA emitter–base structure, which uses highly boron-doped and silicided polysilicon layers for contacting the SiGe base of the active transistor. These pþ-polysilicon base electrodes are separated self-aligned by a thin oxide spacer from the heavily arsenic-doped emitter layer. As compared to transistor concepts realizing the separation of the emitter from the extrinsic base regions by a photolithographic alignment step, the self-alignment of the emitter–base structure is very advantageous for achieving low values of base resistance and base– collector capacitance. In our SiGe technology the SiGe base layer is integrated by SEG, which has also allowed the formation of a self-aligned base–collector structure [9–14]. Similar to the other most advanced high-frequency SiGe HBT technologies [1–7], the SiGe base contains a certain amount of carbon for realizing very thin and highly boron-doped base layers with steep doping profile gradients [16, 17]. Another feature of the SiGe technology is the heavily arsenic-doped monocrystalline emitter

FIGURE 3.8.1 TEM cross section of a fabricated transistor.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Infineon

3.8-309

contact [7, 18, 19], which, as compared with conventional polysilicon emitters, reduces the emitter resistance of laterally downscaled transistors considerably. Finally, since in high-frequency SiGe bipolar technologies the SiGe HBTs are operating at high current densities, we use a copper metallization system. In comparison with a conventional aluminum metallization, the copper metallization has the advantage of a significantly improved electromigration hardness and lifetime at high current densities. In the copper metallization, consisting of four metallization layers, also a high-precision TaN resistor, and an MIM capacitor have been integrated [20].

3.8.3 Transistor Fabrication Process After having described the basic process concept, the transistor fabrication sequence is given in this section. The main emitter–base fabrication steps are outlined in Figure 3.8.2. After the fabrication of the deep trench/shallow trench transistor isolation a CVD-oxide layer is deposited. Then the pþ-polysilicon base electrodes, a CVD-oxide layer, and a nitride layer are deposited. The stack made of these three layers is patterned by reactive ion etching (RIE) for forming the emitter window (Figure 3.8.2a). Then a nitride/oxide stack consisting of a 20-nm thick nitride and a 50-nm thick oxide layer is deposited and spacers — made of the material of the nitride/oxide stack — are formed inside the emitter window by RIE (Figure 3.8.2b). Outside the emitter window the nitride/oxide stack is protected during this RIE by resist. Now a phosphorus implantation into the emitter window is done for forming the selectively implanted collector. The collector implantation is automatically self-aligned to the active transistor region and therefore advantageous for realizing low base–collector capacitance. Moreover, since the spacers inside the emitter window significantly reduce the implantation area for collector implantation a reduction of base–collector capacitance of about 20% is observed as compared to a collector implantation through the whole emitter window [6]. Since the collector implantation is performed before SiGe base deposition any broadening of the boron impurity profile in the SiGe base layer due to implantation damage-induced point defects is avoided in this transistor concept. This is different from the transistor concepts using NSEG for base integration. In these transistors, a collector implantation, which is selfaligned to the active transistor region, can be only performed after the SiGe base deposition process. After collector implantation the CVD-oxide layer, which is covering the collector region, is removed by a wet etch in the active transistor region. The wet etch is performed until self-aligned adjusted pþpolysilicon overhangs of about 100 nm over the CVD-oxide layer beneath have been formed (Figure 3.8.2c). During this wet oxide etch, the nitride layer of the nitride/oxide stack serves to protect the isolation regions. Now the SiGe base layer is integrated by SEG. The deposition is performed in a radiation-heated single wafer reactor using a gas mixture of H2, SiH2Cl2, HCl, GeH4, B2H6, and SiH3CH3. The HCl is used for ensuring the selective growth conditions whereas the SiH3CH3 is added to achieve the incorporation of substitutional carbon in the SiGe base [16, 17] during SEG. The growth parameters of the SiGe base deposition process and their optimization for avoiding loading effects and for improving manufacturability are described in detail in Ref. [21]. Under these selective deposition conditions no growth takes place on the transistor and isolation regions which are covered by the nitride layers (Figure 3.8.2c). Monocrystalline growth of the SiGe base occurs only at the opened collector regions and polysilicon growth only at the overhanging parts of the extrinsic base polysilicon electrodes. During the selective base deposition process the intrinsic SiGe base layer, which is growing bottom up on the collector, is connected with the polycrystalline base link region, which is growing top down from the base electrodes. After base deposition the thin nitride spacers and the sacrificial nitride layers on top of the structure are removed in phosphoric acid (Figure 3.8.2d). Then the oxide spacers which serve for the self-aligned separation of the heavily doped emitter layer from the heavily borondoped extrinsic base regions are formed inside the emitter window. Now the heavily arsenic-doped emitter layer is deposited by NSEG in a radiation-heated CVD reactor. After the in situ removal of the native oxide layer on the silicon substrate by a bake in H2 atmosphere,

© 2006 by Taylor & Francis Group, LLC

3.8-310

The Silicon Heterostructure Handbook

CVD-Oxide

Nitride

p+-poly (a) n− CVD-Oxide Nitride/oxide stack

(b)

Nitride/oxide spacer

p+-poly n−

n

Nitride

n−

STI

p+-Poly overhang

p+-poly

p+-poly

(c) n−

n

n−

Monocrystalline SiGe base

STI

Polycrystalline base link

p+-poly

p+-poly P

(d) n

SiGe base

−

n

n+-mono

n−

STI

n+-poly

p+-poly

p+-poly

(e)

P n

−

n

n−

STI

FIGURE 3.8.2 Fabrication steps of emitter–base structure. (a) Formation of emitter window, (b) deposition of nitride/oxide stack, nitride/oxide spacer formation by RIE using a photomask, self-aligned collector implantation, (c) wet oxide etch for self-aligned formation of pþ-polysilicon overhangs, (d) SiGe base deposition by selective epitaxy, removal of nitride spacers, and sacrificial nitride layers by wet etching, and (e) formation of oxide spacers inside the emitter window, fabrication of emitter.

© 2006 by Taylor & Francis Group, LLC

3.8-311

Industry Examples at the State-of-the-Art: Infineon

this deposition is performed in the CVD reactor at a temperature of 5508C using disilane as silicon source and arsine as dopant source. Under these deposition conditions, the 1021 cm
3 arsenic-doped emitter layer grows monocrystalline on the silicon area of the active transistor region and amorphous on the surrounding isolation regions with a high growth rate of about 70 nm/min. After patterning the NSEG grown nþ-emitter layer, a rapid thermal annealing (RTA) step is performed, which diffuses the emitter about 20 nm deep into the underlying silicon cap of the base. During this emitter drivein, the amorphous parts of the nþ-emitter layer become polycrystalline (Figure 3.8.2e). After the emitter drive-in, processing is completed by salicidation of the base electrodes and by forming the copper metallization.

3.8.4 Transistor Results A TEM cross section through the emitter–base configuration of the fabricated transistors is shown in Figure 3.8.3. The mask width of the emitter window is 0.3 mm and the width of the oxide spacers which are used for the self-aligned separation of the emitter from the pþ-polysilicon base electrodes is 80 nm. The resulting effective emitter width is only 0.14 mm. These small values of emitter width are effective for realizing low values of base resistance and emitter–base capacitance. The thin SiGe base layer is confined within the walls defined by the CVD-oxide layer, which lies under the pþ-polysilicon base electrodes. As already described in the fabrication process (Figure 3.8.2c) the overlay between the pþpolysilicon and the CVD-oxide layer below has been adjusted self-aligned to about 100 nm. In the final transistors this results in a self-alignment of the base/collector structure, which means that the size of the contact region between the extrinsic base electrodes and the SiGe base layer is adjusted independently on a photolithographic alignment step. This self-alignment is advantageous for realizing low values of base– collector capacitance. As seen from the micrograph in Figure 3.8.3 the heavily arsenic-doped nþ-emitter layer is monocrystalline in the active transistor region. The monocrystalline emitter has the advantage of the absence of any interfacial oxide layer between the nþ-emitter contact layer and the underlying silicon cap of the base where the active emitter is diffused in. This is different from polysilicon emitter transistors. In such transistors always a thin interfacial oxide layer is located between the nþ-polysilicon and the underlying silicon substrate, which often breaks up during the emitter drive-in [22]. The thickness of such an interfacial oxide layer is difficult to control and significantly affects the emitter resistance and base currents in polysilicon emitter transistors. The replacement of the polysilicon emitter by the monocrystalline emitter contact has therefore improved emitter resistance and manufacturability of our SiGe HBTs considerably. The emitter resistance has been measured on devices with an emitter length of 2.6 mm by using the modified open collector method described in Ref. [23]. Figure 3.8.4 compares the emitter resistances of transistors with monocrystalline and polycrystalline emitter contacts for various

CVD -oxide

p+-poly n+-mono Si

STI SiGe-base

100 nm

FIGURE 3.8.3 0.14 mm.

TEM cross section of the emitter–base complex of a transistor with effective emitter width of

© 2006 by Taylor & Francis Group, LLC

3.8-312

The Silicon Heterostructure Handbook

values of effective emitter widths. In the polysilicon emitter HBTs the thickness of the interfacial oxide layer has been kept as thin as possible. Nevertheless, for an effective emitter width of 0.18 mm the transistors with monocrystalline emitter exhibit an emitter resistance of only 2.6 V, which is more than 50% lower than the emitter resistance of the polysilicon emitter control HBTs. As can be also seen from Figure 3.8.4 this advantage of the transistors with monocrystalline emitter contact increases with decreasing emitter width and becomes most pronounced in devices with very small effective emitter width. Also, since the interfacial oxide in polysilicon emitter HBTs is a dominant 1/f noise source, it has been found in Ref. [18] that a monocrystalline emitter contact is very effective for improving 1/f noise in high-speed SiGe HBTs. The SIMS doping profile of the fabricated transistors is shown in Figure 3.8.5. By the self-aligned collector implantation which has been described in Section 3.8.3, a high collector doping level of 1  1018 cm
3 has been employed for realizing high current-carrying capability of the transistors. In the SiGe base layer a maximum Ge fraction of 25% has been used. The Ge profile has been steeply graded across the base to achieve an accelerating drift field for the electrons to increase the transit frequency. In the base a boron spike with high concentration of 4  1019 cm
3 has been grown to enable the low base sheet resistance of 2.8 kV/sq. At the emitter side the base is lowly doped with a concentration of 1  1018 cm
3 in order to obtain a small emitter–base capacitance. For realizing high transit frequency the

Ω

n+-poly Si emitter n+-mono Si emitter

6

LE = 2.6 µm RE

4

2

0 0.1

0.2

0.3

0.4

WE (µm)

FIGURE 3.8.4 Emitter resistance RE vs. effective emitter width WE. 30 Base

Collector 25

1021 As

Ge 20 15

1019

C

10

B P 1017 0.05

0.10

0.15 Depth (mm)

FIGURE 3.8.5 SIMS doping profile of the fabricated transistors.

© 2006 by Taylor & Francis Group, LLC

0.2

5 0 0.25

Ge (%)

Concentration (cm-3)

Emitter

3.8-313

Industry Examples at the State-of-the-Art: Infineon

thickness of the boron spike must be kept as thin as possible during the processing steps and annealing cycles following SiGe base deposition for transistor fabrication. Therefore, as the incorporation of carbon on substitutional sites with typical concentrations between 1  1019 and 5  1019 cm
3 reduces the diffusion of boron in Si and SiGe layers significantly [16, 17], the region around the boron spike has been carbon doped with a chemical concentration of 3  1019 cm
3. From this chemical carbon concentration, about 80% was found to be substitutional by x-ray diffraction (XRD). This incorporation of substitutional carbon during SiGe base deposition has effectively reduced the broadening of the base boron dopant profile in the processing steps after SEG. In combination with low-temperature processing therefore steep boron doping profiles have been achieved, resulting in a final metallurgical base width of 27 nm. Despite the highly boron-doped and aggressively vertical-scaled SiGe base profile the transfer characteristics of the fabricated transistors are ideal. Figure 3.8.6 shows the typical transfer characteristics of transistors with an effective emitter size of 0.14  2.6 mm2. For a base–emitter voltage of 0.8 V the typical current gain is 250. Also shown in Figure 3.8.6 is the typical transfer characteristic of a transistor array. These transistor arrays are configured with 7000 transistors connected in parallel. The transistor arrays have an emitter area of 7000  0.18  2.6 mm2 and are used for monitoring the transistor yield. As shown in Ref. [7] the typical emitter–base yield of these transistor arrays is near 100% and the collector– emitter yield is about 80%. Figure 3.8.7 shows the common emitter output characteristics of transistors with an emitter area of 0.14  2.6 mm2. The collector–emitter breakdown voltage BVCE0, which is measured with open base is 1.7 V. The high-frequency performance of the SiGe HBTs has been evaluated using S-parameter measurements up to 30 GHz. The transit frequency fT has been extrapolated from the small signal current gain jh21j2 using transistors with an emitter area of 0.14  2.6 mm2. Figure 3.8.8 shows the dependency of transit frequency fT on the collector current IC for different base–collector voltages VBC. The transit frequency reaches its maximum of 200 GHz at VBC ¼ 0 and a collector current density of about 8 mA/mm2. The maximum oscillation frequency fmax has been extrapolated from Mason’s unilateral gain U [24] at 25 GHz with
20 dB/dec role-off. Figure 3.8.9 shows the dependency of the maximum oscillation frequency on collector current. At VBC ¼
1 V the maximum oscillation frequency peaks at 275 GHz. Figure 3.8.10 shows the measured frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG and the unilateral gain U at the bias conditions (VBC ¼
1 V, IC ¼ 3.5 mA) where the maximum oscillation frequency reaches its optimum. The transition from the maximum stable gain MSG to the maximum available gain occurs at a frequency higher than 30 GHz. The high values of fmax originate from the integration of the thin base layer into a self-aligned transistor

10−2

7000 transistor array

IC,IB (A)

10−4 10−6 10−8

single transistor

10−10 10−12 0

0.2

0.4

0.6 0.8 VBE (V)

1

1.2

FIGURE 3.8.6 Transfer characteristics of a transistor with AE ¼ 0.14  2.6 mm2 and a transistor array with AE ¼ 7000  0.18  2.6 mm2.

© 2006 by Taylor & Francis Group, LLC

3.8-314

The Silicon Heterostructure Handbook

4

I B = 0, 5, 10, 15, 20, 25 µA

IC (mA)

3

2

1

BVCE0 = 1.7 V 0 0

0.5

1

1.5 VCE (V)

2

2.5

3

FIGURE 3.8.7 Common emitter output characteristics of transistors with AE ¼ 0.14  2.6 mm2.

250

300

275 GHz

200 GHz

VCB = 1 V fmax (GHz)

f T (GHz)

200 VCB =1 V

150 100 50 0 0.01

200

100 VCB = 0 V VCB = 0 V 0.1 1 10 Collector current (mA)

0 0.01 100

FIGURE 3.8.8 Cut-off frequency fT vs. collector current for transistors with AE ¼ 0.14  2.6 mm2.

0.1 1 10 Collector current (mA)

100

FIGURE 3.8.9 Maximum oscillation frequency fmax vs. collector current for transistors with AE ¼ 0.14  2.6 mm2.

architecture, providing low capacitances and extrinsic series resistances. Furthermore the high fmax values could be achieved by careful optimization of the highly boron-doped base for achieving simultaneously high transit frequency and low base sheet resistance. Table 3.8.1 summarizes the most important transistor parameters. The tradeoffs between these transistor parameters have been optimized for a balanced compromise to enable high-frequency circuit applications. The high values of transit frequency have been combined with a low base resistance RB of 50 V. The open-base collector–emitter breakdown voltage BVCE0 is 1.7 V and the open-emitter collector– base breakdown voltage BVCB0 is 5.8 V. The maximum sustainable operating voltage of a SiGe HBT generally lies between BVCE0 (worst case) and BVCB0 (best case). The values for emitter–base capacitance CEB, base–collector capacitance CBC, and collector–substrate capacitance CCS in Table 3.8.1 refer to unbiased junctions and include the wiring parasitic capacitances up to the first metallization layer. Taking into account the high base and collector doping levels, which have been employed in the

© 2006 by Taylor & Francis Group, LLC

3.8-315

Industry Examples at the State-of-the-Art: Infineon

40 U

Gain (dB)

30 20

VCB = 1 V IC = 3.5 mA

MSG |h21|2

275 GHz

10 190 GHz

0 1

10 100 Frequency (GHz)

1000

FIGURE 3.8.10 Frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG, and the unilateral gain U for transistors with AE ¼ 0.14  2.6 mm2.

TABLE 3.8.1 Device Parameters of the High-Speed npn Transistor with AE ¼ 0.14  2.6 mm2 AE b RBI BVCE0 BVCB0 CEB CBC CCS RB RE fT fmax Gate delay

0.14  2.6 mm2 250 2.8 kV/sq. 1.7 V 5.8 V 6.3 fF 5.5 fF 3.7 fF 50 V 3.5 V 200 GHz 275 GHz 3.5 psec

technology for achieving high transit frequency, high current-carrying capability and low base resistance, the DPSA emitter–base configuration has provided reasonable low values for emitter–base and base–collector capacitances of 6.3 and 5.5 fF, respectively.

3.8.5.

Additional Devices

To enable high-performance circuit applications several additional devices have been added to the highfrequency npn transistor. Table 3.8.2 summarizes all devices which are available in the technology. In addition to the high-frequency npn transistors which have been described before, two other types of npn transistors are offered on the wafers. Table 3.8.3 summarizes the device parameters of the three different npn transistor types. These npn transistors have been optimized for different tradeoffs between transit frequency fT and base–collector breakdown voltage BVCB0. By using additional mask steps in the process flow, the npn transistors differ in the collector implantation doses. As compared to the high-frequency npn1 transistor, the reduction of the collector doping level in the additional npn transistors has resulted in increased base–collector breakdown voltages of 8.3 and 10.5 V, respectively. This is resulting in a transit frequency of 135 GHz for the npn2 transistor and in a transit frequency of 80 GHz for the npn3 transistor. As seen from Table 3.8.2 also three types of resistors and an MIM capacitor are available. The resistors poly R1 and poly R2 are made of the pþ-polysilicon base electrodes but with less boron doping. The two polysilicon resistors have sheet resistances of 150 and 1000 V/sq., respectively. The high-precision TaN

© 2006 by Taylor & Francis Group, LLC

3.8-316

The Silicon Heterostructure Handbook TABLE 3.8.2 Available Devices fT ¼ 200 GHz, BVCB0 ¼ 5.8 V fT ¼ 135 GHz, BVCB0 ¼ 8.3 V fT ¼ 80 GHz, BVCB0 ¼ 10.5 V 150 Ohm/sq. 1000 Ohm/sq. 20 Ohm/sq. 1.4 fF/mm2

npn1 npn2 npn3 Poly R1 Poly R2 TaN R3 MIM

TABLE 3.8.3 Device Parameters of the Three Different npn Transistor Types (AE ¼ 0.14  2.6 mm2)

fT (GHz) fmax (GHz) CBC (fF) BVCE0 (V) BVCB0 (V)

npn1

npn2

npn3

200 275 5.5 1.7 5.8

135 285 4.6 2.0 8.3

80 225 3.6 3.1 10.5

metal resistor and the MIM capacitor are described in more detail in Ref. [20]. The TaN metal resistor is placed between the first and the second copper metallization layer and has a sheet resistance of 20 V/sq. The MIM capacitor has a specific capacitance of 1.4 fF/mm2 and is integrated between the second and third metallization layer. The MIM capacitor uses a 50-nm thick Al2O3 dielectric layer, which has been deposited by atomic layer deposition.

3.8.6.

Circuit Performance

In this section we describe the ring oscillator gate delay performance. Additionally we discuss some of the circuit results which have been achieved in our SiGe bipolar technology. The ring oscillator gate delay performance is a very good figure-of-merit for the digital circuit speed of a bipolar technology since it accounts for the effects of all transistor parameters and local wiring parasitic elements on the performance of a gate. The gate delay of our SiGe technology has been evaluated by ring oscillators using the power-saving current-mode logic (CML) circuit principle. The CML ring oscillators operate with 2.2 V supply voltage and a differential voltage swing of 400 mV. The dependency of the gate delay time on switching current is shown in Figure 3.8.11 for a position in the center of a wafer. A minimum gate

Gate delay (psec)

30

20

10

0 0.1

td = 3.5 ps

1 Igate (mA)

10

FIGURE 3.8.11 CML ring oscillator gate delay vs. current per gate Igate (AE ¼ 0.14  2.6 mm2).

© 2006 by Taylor & Francis Group, LLC

3.8-317

Industry Examples at the State-of-the-Art: Infineon

delay time of 3.5 psec is achieved at a switching current density of 8 mA/mm2. This state-of-the-art result demonstrates the well-balanced compromise between the important device parameters in Table 3.8.1. Figure 3.8.12 shows the distribution of the minimum gate delay time over a wafer. The mean value is 3.63 psec at a standard deviation of only 1.5%. Figure 3.8.13 shows the trend of the minimum gate delay in the wafer center over a lot of 15 wafers. The minimum and maximum values over the lot are 3.49 and 3.59 psec, respectively. These results demonstrate that the technology has the performance, homogeneity, and reproducibility needed for advanced high-quality circuit fabrication. To give an impression of application fields which seem to become feasible with high-speed SiGe technologies, we now briefly summarize the results of some high-frequency circuits, which have been fabricated in our technology. The frequency divider results are shown in Table 3.8.4. The dynamic frequency divider uses the principle of regenerative frequency division and has a divide ratio of 2. The circuit operates with a total supply current of 62 mA up to 110 GHz [25]. The static frequency divider has a divide ratio of 32 and operates up to 86 GHz [25]. This divider is based on the E2CL circuit principle and uses no pretracking technique [26] for further enhancement of operating frequency. Such frequency dividers are key circuit elements in a wide variety of application fields as for example in optical communications and measurement equipment.

[psec]

3.67

3.68

3.75

3.67

3.65

3.62

3.66

3.69

3.67

3.65

3.61

3.54

3.60

3.66

3.71

3.69

3.65

3.58

3.50

3.55

3.63

3.67

3.65

3.59

3.54

3.58

3.65

3.68

3.66

3.60

3.60

3.63

3.62

3.58

3.57

FIGURE 3.8.12 Wafer map of the ring oscillator gate delay at a switching current density jC ¼ 8 mA/mm2 (AE ¼ 0.14  2.6 mm2).

4.0 3.8 Gate 3.6 delay (psec) 3.4 3.2 3.0 0

5

10

15

Wafer

FIGURE 3.8.13 Minimum gate delay over a lot of 15 wafers (AE ¼ 0.14  2.6 mm2, jC ¼ 8 mA/mm2).

© 2006 by Taylor & Francis Group, LLC

3.8-318

The Silicon Heterostructure Handbook TABLE 3.8.4

Frequency Divider Data

Divide ratio Frequency range Supply voltage Supply current

Static Frequency Divider

Dynamic Frequency Divider

32 86.2 GHz
5.0 V 180 mA

2 35–110 GHz
5.0 V 62 mA

Source : From H Knapp et al. 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology. International Microwave Symposium, 2003, pp. 1067–1070. With permission.

TABLE 3.8.5 Data of Lumped-Element Broadband Amplifier

Frequency range Gain Noise Total Output power Supply voltage Supply current

Broadband Amplifier

VCO with Integrated Buffer

3 dB-bandwidth: 62 GHz 16 dB — —
5.0 V 155 mA

74–80.5 GHz — Phase noise (1 MHz offset): <–95 dBc/Hz >18 dB m
5.5 V 218 mA

Active Mixer 72.3–82.5 GHz >24 dB SSB noise figure: <14 dB —
5.0 V 60 mA

(From W Perndl et al. A 60 GHz broadband amplifier in SiGe bipolar technology. Proceedings BCTM, 293–296, 2004.) VCO with Integrated Output Buffer (From H Li et al. Fully integrated SiGe VCOs with powerful output buffer for 77 GHz automotive radar systems and applications around 100 GHz. Journal of Solid-State Circuits, 263–266, 2004.) and Active Mixer (From W Perndl et al. A low-noise and high-gain double balanced mixer for 77 GHz automotive radar front-end in SiGe bipolar technology. Radio Frequency Integrated Circuits (RFIC) Symposium, 47–50, 2004. With permission.)

The results of a monolithic integrated broadband amplifier [27] are summarized in Table 3.8.5. The broadband amplifier is based on lumped elements and is designed for differential input and output signals. The amplifier has a differential gain of 16 dB, a 3-dB bandwidth of 62 GHz and consumes 155 mA at a supply voltage of
5 V. The clear output eye diagram at a data rate of 80 Gbit/s [27] demonstrates the feasibility of the circuit for optical communications at 80 Gbit/s. To investigate the suitability of high-speed SiGe technologies for automotive radar applications at 77 GHz, we have also fabricated first key building blocks like VCOs and mixers. The results of these circuits are also summarized in Table 3.8.5. The 77-GHz VCO [28] including the resonant circuit and the output buffer has been fully integrated on a single chip (1 mm2). The output buffer has two outputs and has been designed for achieving high output power, which is required in 77-GHz automotive radar applications. The VCO is operating in the frequency range between 74 and 80.5 GHz with a phase noise of
95 dBc/Hz at 1 MHz offset. The total signal power of both buffer outputs is as high as 18 dB m and the total power consumption of the circuit is 1.2 W. The active mixer [29] for down-conversion in Table 3.8.5 consists of a mixer core based on the Gilbert cell and an on-chip balun at the RF input in order to provide a single-ended input. In the frequency range of 72 to 82 GHz the mixer has a gain of more than 24 dB and a single-sideband (SSB) noise less than 14 dB. These results show that demanding application fields like 77-GHz automotive radar which seemed to be reserved for III–V semiconductor technologies in the past, are now feasible in high-speed SiGe bipolar technologies in a highly integrated manner.

References 1. B Jagannathan, M Khater, F Pagette, JS Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, SJ Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, S Subbanna, Self-aligned SiGe npn transistors with 285 GHz fmax and 207 GHz fT in a manufacturable technology. IEEE Electronic Device Letters, 24: 324–326, 2003.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Infineon

3.8-319

2. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, S Subbanna, SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest: 121–124, 2002. 3. T Tominari, S Wada, K Tokunaga, K Koyu, M Kubo, T Udo, M Seto, K Ohhata, H Hosoe, Y Kiyota, K Washio, T Hashimoto, Study on extremely thin base SiGe HBTs featuring sub 5 ps ECL gate delay, Proceedings BCTM: 107–110, 2003. 4. T Hashimoto, Y Nonaka, T Tominari, H Fujiwara, K Tokunaga, M Arai, S Wada, T Udo, M Seto, M Miura, H Shimamoto, K Washio, H Tomioka, Direction to improve SiGe BICMOS technology featuring 200 GHz SiGe HBT and 80nm gate CMOS. IEDM Technical Digest: 129–132, 2003. 5. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Hoppner, D Knoll, K Kopke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, HE Wulf, Y Yamamoto, SiGe:C BiCMOS technology with 3.6 ps gate delay. IEDM Technical Digest: 121–124, 2003. 6. TF Meister, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, A Mitchell, T Bo¨ttner, J Bo¨ck, SiGe bipolar technology with 3.9 ps gate delay. Proceedings BCTM: 103– 106, 2003. 7. J Bo¨ck, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, W Perndl, T Bottner, TF Meister, SiGe bipolar technology for automotive radar applications. Proceedings BCTM: 84–87, 2004. 8. JN Burghartz, BJ Ginsberg, SR Mader, TC Chen, DL Harame, Selective epitaxy base transistor (SEBT), Electron Device Letters, IEEE, 9: 259–261, 1988. 9. F Sato, H Takemura, T Tashiro, H Hirayama, M Hiroi, K Koyama, M Nakamae, A self-aligned selective MBE technology for high-performance bipolar transistors. IEDM Technical Digest: 607– 610, 1990. 10. TF Meister, R Stengl, HW Meul, R Weyl, P Packan, A Felder, H Klose, R Schreiter, J Popp, HM Rein, L Treitinger, Sub-20 ps silicon bipolar technology using selective epitaxial growth, IEDM Technical Digest: 401–404, 1992. 11. F Sato, T Hashimoto, T Tatsumi, H Kitahata, T Tashiro, Sub-20 ps ECL circuits with 50 GHz fmax self-aligned HBTs. IEDM Technical Digest: 397–400, 1992. 12. TF Meister, H Scha¨fer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, H Stolz, S Boguth, J Bo¨ck, SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. IEDM Technical Digest: 739–742, 1995. 13. A Pruijmboom, D Terpstra, CE Timmering, WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, JJEW Hageraats, Selective epitaxial base technology with 14 ps ECL gate delay for low power wide-band communication systems. IEDM Technical Digest: 747–750, 1995. 14. K Washio E Ohue, K Oda, M Tanabe, H Shimamoto, T Onai, A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3 ps ECL-gate delay, IEDM Technical Digest: 795–798, 1997. 15. W Klein, BUH Klepser, 75 GHz Bipolar production technology for the 21st century, Proceedings of the ESSDERC: 88–94, 1999. 16. LD Lanzerotti, JC Sturm, E Stach, R Hull, T Buyuklimanli, C Magee, Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation, Technical Digest IEDM: 249–252, 1996. 17. HJ Osten B Heinemann, D Knoll, G Lippert, H Ru¨cker, Effects of carbon on boron diffusion in SiGe: principles and impact on bipolar devices. Journal of Vacuum Science and Technology B, 16: 1750–1753, 1998. 18. S Jouan, R Planche, H Baudry, P Ribot, JA Chroboczek, D Dutartre, D Gloria, M Laurens, P Llinares, M Marty, A Monroy, C Morin, R Pantel, A Perrotin, J de Pontcharro, JL Regolini, G Vincent, A Chantre, A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices, 46: 1525–1529, 1999. 19. A Joseph, P Geiss, X Liu, J Johnson, K Schonenberg, A Chakravarti, D Ahlgren, J Dunn, Emitter resistance improvement in high-performance SiGe HBTs. Program of ISTDM, in Nagoya, Japan: 53– 54, 2003.

© 2006 by Taylor & Francis Group, LLC

3.8-320

The Silicon Heterostructure Handbook

20. M Schwerd, M Seck, T Huttner, T Bo¨ttner, S Drexl, B Hasler, A Mitchell, H Helneder, H Ko¨rner, V Kubrak, M Schrenk, R Lachner; A manufacturable 0.35 mm 150 GHz fT SiGe:C bipolar RF technology. Proceedings Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: 10– 13, 2003. 21. H Scha¨fer, J Bo¨ck, R Stengl, H Knapp, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, TF Meister, Selective epitaxial growth of SiGe:C for high-speed HBTs. Applied Surface Science, 224: 18– 23, 2004. 22. H Schaber, TF Meister, Technology and physics of polysilicon emitters, Proceedings BCTM: 75–81, 1989. 23. R Gabl; M Reisch, Emitter series resistance from open-collector measurements – influence of the collector region and the parasitic pnp transistor, IEEE Transactions on Electron Devices, 45: 2457– 2465, 1998. 24. JD Cressler and G Niu. Silicon germanium heterojunction bipolar transistors. Artech House, Inc: 162–164, 2003. 25. H Knapp, M Wurzer, TF Meister, K Aufinger, J Bo¨ck, S Boguth, H Scha¨fer, 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology. International Microwave Symposium: 1067–1070, 2003. 26. K Washio, R Hayami, E Ohue, K Oda, M Tanabe, H Shimamoto, M Kondo, 67 GHz static frequency divider using 0:2 mm self-aligned SiGe HBTs. IEEE Radio Frequency Integrated Circuits Symposium: 31–34, 2000. 27. W Perndl; W Wilhelm, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bock, W Simburger, AL Scholtz, A 60 GHz broadband amplifier in SiGe bipolar technology. Proceedings BCTM: 293–296, 2004. 28. H Li, HM Rein, T Suttorp, J Bock, Fully integrated SiGe VCOs with powerful output buffer for 77 GHz automotive radar systems and applications around 100 GHz. Journal of Solid-State Circuits, 39(10): 263–266, 2004. 29. W Perndl, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bo¨ck, W Simbu¨rger, AL Scholtz, A lownoise and high-gain double balanced mixer for 77 GHz automotive radar front-end in SiGe bipolar technology. Radio Frequency Integrated Circuits (RFIC) Symposium: 47–50, 2004.

© 2006 by Taylor & Francis Group, LLC

3.9 Industry Examples at the State-of-the-Art: IHP 3.9.1 3.9.2 3.9.3

Introduction............................................................... 3.9-321 History of IHP’s SiGe and SiGe:C HBT Technologies............................................................... 3.9-322 High-Performance SiGe:C BiCMOS Processes ....... 3.9-323 85 GHz SiGe:C BiCMOS (SGC25A) . 120 GHz SiGe:C BiCMOS (SGC25B) [11, 12] . 200 GHz SiGe:C BiCMOS (SGC25C) [13, 14]

3.9.4 3.9.5 3.9.6

Dieter Knoll IHP

High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology ......................................... 3.9-329 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) ..................... 3.9-332 Circuit Applications of IHP’s SiGe:C Technologies............................................................... 3.9-334 60 GHz Transceiver Circuits . Automotive Radar

3.9.7

Summary .................................................................... 3.9-339

3.9.1 Introduction IHP is an R&D institute mainly financed by the German federal and the Brandenburg state governments. The purpose of IHP’s R&D activities is to create innovative solutions for wireless and broadband communication systems by close cooperative work of competent teams working in the fields of material research, process technology, circuit design, and systems. Cooperation in all these fields with partners from industry, universities, or other R&D institutes is also a common practice. The institute currently operates a 1000 m2 class-1 cleanroom, equipped with a tool set capable for 8-inch Si wafer processing and sub-0.25 mm feature size. In this chapter, we will describe IHP’s modular SiGe:C RF BiCMOS technologies which have been developed to enable the realization of integrated mixed-signal systems-on-a-chip (SoC). These BiCMOS technologies provide several types of SiGe:C HBTs with parameters or features tailored to specific applications, combined with a 0.25 mm CMOS core and a variety of passive elements. We will primarily focus on the fabrication and parameters of the SiGe:C HBT modules, but also give an overview of the further BiCMOS devices. In Section 3.9.2, the history of IHP’s SiGe and SiGe:C HBT technologies is briefly summarized. The following sections (Sections 3.9.3 to 3.9.6) provide a detailed description of the SiGe:C BiCMOS processes presently available at IHP. These processes reflect two different approaches of HBT module development. The first one aims at highest HBT performance for applications such as optical fiber communications with transmission speeds of higher than 40 Gb/sec, very high data rate wireless links in the 60 GHz ISM band, or automotive radar at 77 GHz and beyond. The high-performance HBT modules developed for these applications are described in Section 3.9.3. They offer peak fT and fmax values of up to 3.9-321 © 2006 by Taylor & Francis Group, LLC

3.9-322

The Silicon Heterostructure Handbook

200 and 245 GHz, respectively, and ring oscillator delay times down to 3.6 ps, the lowest value obtained so far in a BiCMOS process. Section 3.9.4 deals with a promising process extension, the common integration of high-speed npn and pnp SiGe:C HBTs in a complementary BiCMOS process. The pnp transistors described show cutoff frequencies which are by a factor of 2 higher than ever-published for a Si-based pnp device. The second approach of IHP’s BiCMOS development aims at cost-sensitive applications, which, however, do not need highest HBT performance. A process, which particularly fulfills the low-cost requirement, is described in Section 3.9.5. In this process, only one mask step is added to the underlying RF CMOS flow to fabricate simultaneously three types of SiGe:C HBTs with BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. Finally, Section 3.9.6 deals with fabricated circuits. Both in-house designers but also many partners and customers from other institutes, companies, or universities made use of industry-standard design kits and took benefit from prototyping and shuttle services offered by IHP for its SiGe:C BiCMOS processes. Here, we focus on some recent results obtained with IHP’s high-performance HBT modules.

3.9.2 History of IHP’s SiGe and SiGe:C HBT Technologies IHP’s activities in the field of SiGe-based device technology began more than 10 years ago with the fabrication of simple double-mesa HBTs with SiGe base layers deposited by MBE or APCVD. These transistors were primarily used to study the particular device properties of HBTs and to learn how these properties can be affected. In the following time, the HBT fabrication process has been continuously improved, also including a change in the SiGe layer deposition process from MBE and APCVD to RTCVD [1]. IHP’s most advanced SiGe HBT technology was a 14-mask RF bipolar process offering three levels of Al and a suite of passive elements [2]. The SiGe HBTs fabricated in this process showed, at 2.7 V BVCEO, peak fT and fmax values of 45 and 60 GHz, respectively, i.e., an RF performance similar to that of IBM’s first generation of SiGe BiCMOS devices [3]. This performance, however, was reached with a much simpler HBT technology that did neither use an epitaxially buried subcollector (EBC), nor deep trench isolation (DTI), nor a self-aligned emitter–base structure. Instead, IHP’s SiGe transistors were fabricated as single-polysilicon transistors with collector wells produced by high-energy P implantation following LOCOS formation. The good RF performance of these devices resulted primarily from a special device construction featuring a minimized spacing between collector contact and internal transistor regions (Figure 3.9.1a). This construction allowed one to reach the low collector resistances necessary for high RF performance, despite the high sheet resistivity of the implanted wells. Moreover, the HBTs took benefit from a progressive SiGe layer structure featuring a half-graded, less than 30-nm

(b)

Salicided collector link

Field oxide Ch. stop

Extr. base implant

SiGe

20

(a)

Polysilicon emitter

Collector well

p-Substrate

[Ge] (%)

Pt silicide

16 12 8 4 0 60 80 100 Depth (nm)

FIGURE 3.9.1 HBT construction (a) and Ge profile (b) (extracted from x-ray measurement), as used in IHP’s first SiGe HBT technology. (From D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Low cost, 50 GHz fmax Si/SiGe heterojunction bipolar transistor technology with epi-free collector wells. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-323

thick Ge profile (Figure 3.9.1b). The Ge profiles used in newer IHP technologies, including the current, most advanced ones, exhibit only minor differences compared to this profile. The primary reason for choosing a relatively simple HBT technology was the aimed modular HBT integration in a state-of-the-art CMOS platform. That seemed to be, at this time, the best way to bring HBTs in the mainstream because allowing the combination of the high RF performance of HBTs with the VLSI capability of digital CMOS. For such a modular HBT integration, we considered single-polysilicon transistors with implanted, epi-free collectors as the most attractive candidates because they can be simply integrated, without altering the CMOS process or process flow, or disturbing the CMOS device characteristics. In the middle of the 1990s, IHP’s material research group began to investigate the properties of C-doped Si and SiGe layers. After learning that even the incorporation of relative low concentrations of C (typically 5
1019 to 1
1020 cm3) can significantly suppress B diffusion in these layers, technology development was focused more and more on HBTs with C-doped SiGe layers, leading to some pioneer results in this field: In 1997, the first SiGe:C transistors with competitive DC and RF parameters were presented [4, 5]. These transistors used MBE-grown SiGe:C base layers. After transferring C-doped Si and SiGe epi-layer deposition to an RTCVD tool, it was shown in detail that C incorporation has no negative effect on ‘impurity-sensitive’ device properties such as leakage currents and yield, low-frequency noise, or base recombination [6, 7]. In 1999, the first SiGe:C BiCMOS process was also presented by IHP [8]. The new SiGe:C HBTs resembled IHP’s C-free SiGe transistors in many features, such as the implanted wells, the LOCOS-based device isolation, the special collector construction, and the singlepolysilicon structure. Besides the C incorporation, they differed from the C-free HBTs primarily in the much higher base B doping, lowering the internal base sheet resistance (RSBi) by more than a factor of 2. Moreover, the low-doped collector (LDC) and emitter (LDE) regions of the SiGe:C HBTs were selectively doped after depositing the SiGe base and a Si cap layer by implantations directly through the emitter window. The SiGe:C devices in IHP’s first BiCMOS process showed peak fT and fmax values of 55 and 90 GHz, respectively, with 3.3 V BVCEO [8], i.e., both the (BVCEO
fT) product and fmax increased by about 50%, in comparison to the C-free transistors presented in Ref. [2]. Clearly, the SiGe:C HBTs took benefit from the C incorporation which effectively suppresses B out-diffusion from a highly doped SiGe layer even under the strong TED impact of the high-dose implant used for doping the external base regions, and the low-dose implants applied for selectively doping the LDE and LDC regions [4, 9]. The reduced B diffusivity in Si:C and SiGe:C layers proved also to be advantageous with respect to a modular BiCMOS process integration. In IHP’s first SiGe:C BiCMOS process, the HBT module was inserted in the CMOS process flow before implantation of the PMOS S/D regions. In this way, the base epitaxy, which needs a high temperature H2-prebake, was prevented from influencing the PMOS parameters. However, the underlying CMOS process did not use a separately implanted drain extension for the PMOS, and a strong RTA had to be applied to drive in the PMOS S/D implant. This anneal was about 708C higher than the RTA of the pure SiGe:C bipolar process [6]. Nevertheless, it could be applied in the BiCMOS flow without degrading the HBT DC and RF characteristics.

3.9.3 High-Performance SiGe:C BiCMOS Processes 85 GHz SiGe:C BiCMOS (SGC25A) In 2000, a 0.25-mm digital CMOS process of an industrial partner was licensed and transferred to IHP’s new cleanroom, which had been completed and equipped some months before. This CMOS process was used as platform for the development of IHP’s second SiGe:C BiCMOS generation. In September 2001, the development was completed with an industry-standard qualification. The new process, called SGC25A, has been running since then as IHP’s BiCMOS ‘work-horse.’ It uses 25 mask steps to fabricate two types of SiGe:C HBTs, in combination with a triple-well, 2.5 V CMOS core. Among the passives are a varactor, polysilicon resistors, and an MIM capacitor. four layers of Al are available, including a 2 mm thick top layer. Table 3.9.1 summarizes the device menu offered by the SGC25A process. Figure 3.9.2

© 2006 by Taylor & Francis Group, LLC

3.9-324

The Silicon Heterostructure Handbook

TABLE 3.9.1 SGC25A HBT Parameters and MOS and Passives Parameters of the SGC Process Family Device

Parameter

Value

Unit

Remark

2

SGC25A HBT Parameters (AE ¼ 0.42
0.84 mm ) Current gain BVEBO

150 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

HBT1

Peak fT / fmax BVCEO BVCBO

60 / 90 3.2 >8

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBT2

Peak fT / fmax BVCEO BVCBO

85 / 100 2.5 >5

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBTs 1 and 2

MOS and Passives Parameters of IHP’s SGC Process Family NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

540 0.4 0.60 0.24

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

230 0.5 0.56 0.245

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

MOS Varactor

Tuning ratio Q factor (@ low/high C)

1:3.4 120/30

Salicide Resistor

Sheet resistance Temperature coefficient

6.6 2900

Vsq ppm/8C

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient

95 450

Vsq ppm/8C

Gate poly (nþ)

Poly-Si Resistor

Sheet resistance Temperature coefficient

350 50

Vsq ppm/8C

HBT base poly

MIM Capacitor

Unit capacitance Voltage coefficient Voltage coefficient Temperature coefficient Breakdown voltage Max. application voltage

1 14 1.6 <10 >30 10

fF/mm2 ppm/V ppm/V2 ppm/8C V V

Quality factors (examples)

4 16

Predefined Inductors

2.5 V
10 V
a

Extrapolation from the IC/AE ¼ (0.3–0.75)mA/mm2 part of the VCE(IC) characteristics.

shows the flow and essential features of the process. The HBT module is integrated after structuring the MOS gates and forming the gate spacers, i.e., in a similar way as described in Refs. [8, 10]. It adds four mask steps (M8–M11) to the underlying RF CMOS baseline and produces a first HBT type featuring 3.2 V BVCEO, and peak fT and fmax values of 60 and 90 GHz, respectively. A fifth additional mask (M4) is used to provide the second HBT type, which combines 2.5 V BVCEO with 85 GHz peak fT and 100 GHz peak fmax. Cross sections of both HBT types are shown in Figure 3.9.3. Note that the SGC25A-HBTs are also fabricated, as IHP’s former devices, with epi-free, implanted wells, and a nonself-aligned emitter– base structure. However, shallow trench isolation was introduced, and higher implantation energies were available. It allowed us to replace our previously used collector construction (Figure 3.9.1a) by a more conventional, planar one. Figure 3.9.4 shows a trend chart of HBT leakage currents demonstrating the high level of SGC25A process maturity.

© 2006 by Taylor & Francis Group, LLC

3.9-325

Industry Examples at the State-of-the-Art: IHP

SGC25A PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA Opening HBT regions + High dose collector implant (M4) MOS well implantations (M5, M6), RTA Gate oxidation, Gate poly deposition Gate etch (M7), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

• • • •

25 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide

HBT MODULES (M4), (M8) − (M11) Deposition of CMOS protection layers (M8): Opening active collector regions + Medium dose collector implant + RTA Non-selective Si/ SiGe:C/ Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch • • • • •

Co salicide Local interconnect (LI) CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

FIGURE 3.9.2 Flow and features of the SGC25A process.

Poly SiGe:C/Si

STI

Polysilicon emitter

HBT1 (a)

SIC SiGe:C

Coll. Well (M8)

Deep n-well (M3)

CMOS protection layer

n+ S/D n-Well

HBT2 (b)

SIC Extr. base Coll. Well (M8)

n+ S/D

High dose collector implant (M4)

FIGURE 3.9.3 Schematic cross sections of the SGC25A HBTs. HBT1 shows 3.2 V BVCEO and 60 GHz fT, while HBT2 combines 2.5 V BVCEO with 85 GHz fT.

The processes SGC25B and SGC25C, described below, are derivatives from SGC25A. They offer a strongly improved HBT performance, while RF CMOS baseline including BEOL, and hence CMOS libraries and passive elements are identical to SGC25A.

120 GHz SiGe:C BiCMOS (SGC25B) [11, 12] SGC25B uses the same HBT integration scheme (Figure 3.9.2) and the same basic HBT construction as SGC25A (Figure 3.9.3b). To get a higher HBT performance than offered by SGC25A, the conditions for the high-dose collector implantation were optimized and the SIC implantation dose was increased.

© 2006 by Taylor & Francis Group, LLC

3.9-326

The Silicon Heterostructure Handbook

AE = 4096⫻(0.42⫻0.84) µm2 log (Ic(A))

−4 −6

IC @VBE = 0.1 V; VCB=1 V

−8

Good device: log IC < −11 Total yield: 92.2%

−10 −12 0

FIGURE 3.9.4

2000

4000 6000 Measuring point

8000

SGC25A trend chart of leakage currents for 4k HBT arrays. 980 wafers from 97 lots were measured.

TABLE 3.9.2

SGC25B HBT Parameters

Parameter

Value

Unit

Remark

SGC25B HBT Parameters (AE ¼ 0.42
0.84 mm2) Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance a

150 120 140 5.9 >2.5 2.3 >4 >40 6.8 4.5 5.6 23 51 150

GHz GHz ps V V V V fF fF fF V V V

@ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VBE ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2) V.

b

Moreover, we reduced some transistor dimensions, such as the active enclosure of the emitter, the overlap of the polysilicon emitter to the emitter window, and the LDE width. Note that the changed SIC conditions are responsible that only one transistor type is available in SGC25B. The parameters of this HBT type are listed in Table 3.9.2, featuring 120 GHz peak fT, 140 GHz peak fmax, and a CML ring oscillator delay time of 5.9 psec.

200 GHz SiGe:C BiCMOS (SGC25C) [13, 14] SGC25C is IHP’s first BiCMOS process which offers bipolar transistors with 200 GHz cutoff frequencies to the design community. Two HBT variants were tested which differ in the emitter–base structure, as shown in Figure 3.9.5. Figure 3.9.6 illustrates both the full SGB25C process flow and the detailed flows for the different HBT modules. The standard HBT variant uses the same single-polysilicon construction as applied in SGC25A/B, featuring an implanted extrinsic base layer (Figure 3.9.5a). This layer is formed on isolator regions during the nonselective epi-process applied to grow the intrinsic SiGe:C base layer and a Si cap. The implantation step for doping the extrinsic base layer is carried out self-aligned to the

© 2006 by Taylor & Francis Group, LLC

3.9-327

Industry Examples at the State-of-the-Art: IHP

(a)

Emitter

Implanted extrinsic base

Collector contact

STI

Heavily doped collector

Emitter

Elevated extrinsic base

STI

(b) Collector contact

STI

Heavily doped collector

STI

FIGURE 3.9.5 Schematic cross sections of the SGC25C standard HBT with implanted extrinsic base (a) and an HBT with elevated extrinsic base (b). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

SGC25C PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA MOS well implantations (M4, M5), RTA Gate oxidation, Gate poly deposition Gate etch (M6), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

ELEVATED EXTRINSIC BASE FORMATION

HBT MODULE (M7) - (M11) Deposition of CMOS protection layers (M7): Opening HBT regions + High dose collector implant + RTA Oxide deposition (M8): Opening active collector regions Si / SiGe:C / Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch

Selective Si epitaxy followed by non-selective HBT base + LDE epitaxy

Sacrificial layer deposition (M9): Opening emitter windows + SIC Forming inside spacers Forming outside spacers + Wet etch sacrificial layer + Selective growth of the B-doped extrinsic base

As doped emitter deposition (M10): Structuring polysilicon emitters (M11): External base structuring Removing protection layers by wet etch

FIGURE 3.9.6 Flow of the SGC25C process with standard HBT module (implanted extrinsic base). The process flow for HBTs with elevated extrinsic base is shown below.

© 2006 by Taylor & Francis Group, LLC

3.9-328

The Silicon Heterostructure Handbook

outer edge of the polysilicon emitter, but not self-aligned to the emitter window. In contrast, the second process variant fabricates transistors with a self-alignment between extrinsic base and emitter window to minimize base resistance (Figure 3.9.5b). This self-alignment is achieved by selectively growing a highly B-doped, elevated extrinsic base layer after structuring the polysilicon emitter. Sacrificial and protection layer depositions as well as spacer processes are applied before, to make possible that this layer growth also occurs in the space between polysilicon emitter and that extrinsic base layer grown already during the nonselective epi-process for base and Si cap formation. Both SGC25C transistor variants reach 200 GHz fT, whereas the HBTs with elevated extrinsic base show fmax values of up to 245 GHz, which is about 50 GHz higher than reached with the implanted version. The strong fT gain, compared to SGC25B, results primarily from a novel collector design, which substantially reduces base–collector charging and transit times. Figure 3.9.6 shows that the SGC25C process flow differs from the SGC25A/B flow in the collector well fabrication. The HBT high-dose collector implantation is now carried out after the gate module. Moreover, conditions for this implantation step were found providing simultaneously a low sheet resistance and a junction depth, which is low enough that the lateral spreading of the highly doped collector wells is confined by the STI side walls. The key new SGC25C device features are the formation of the whole HBT structure in one active area without STI stripe between emitter and collector contacts, the complete lateral enclosure of the highly doped collector wells in the STI side walls, and the self-alignment of the collector contact region to the base poly edge (Figure 3.9.5). This allows us to achieve collector resistances, which are even lower than the emitter resistance. In addition, the new design reduces device dimensions and parasitic capacitances. So, the reduced collector area results in a 50% reduction in the collector– substrate capacitance compared to the SGB25B transistors. Furthermore, since the collector well fabrication is implemented after the critical thermal treatments, this device design allows us to produce extremely steep collector doping profiles and achieves better control of the width of the base–collector space charge regions. Finally, the absence of DTI improves the heat dissipation and reduces the thermal resistance. In addition to the introduction of a new collector design we also optimized the base–collector as well as the emitter–base depletion widths by adjusting the buffer and cap thicknesses of the epi-layer stack in order to maximize fT. Figure 3.9.7 compares the fT vs. IC curves of SGC25B and SGC25C HBTs and illustrates, by a comparison of transit time components, from what the SGC25C performance gain results in detail. Table 3.9.3 summarizes the parameters of the SGC25C HBTs. The standard devices, with implanted extrinsic base, show 200 GHz fT, about 185 GHz fmax, and a minimum CML ring oscillator delay of 4.3 ps. The devices with elevated extrinsic base reach fmax values in excess of 240 GHz and a ring oscillator delay of 3.6 ps (Figure 3.9.8), which is, to our knowledge, the lowest value reached so far in a BiCMOS process.

VCE = 1.5 V

150

SGC25C

100

SGC25B

50 AE = 2⫻(0.21⫻0.84) µm2 0.01

0.1 1 Collector current (mA)

10

Transit time (psec)

Transit frequency (GHz)

1.4 200

1.2

(CBC+CBE)kT/qIC

1.0

CBC(RE+RC)

0.8 0.6 wBC /2vsat

0.4 0.2

tE+tB

0.0 SGC25B

SGC25C

FIGURE 3.9.7 Transit frequency vs. collector current for SGC25B and SGC25C HBTs, and comparison of the transit time components of these transistors.

© 2006 by Taylor & Francis Group, LLC

3.9-329

Industry Examples at the State-of-the-Art: IHP TABLE 3.9.3 SGC25C HBT Parameters

Parameter Emitter dimensions Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

Selectively Grown Elevated Extrinsic Base

Standard: Implanted Extrinsic base

Value

Value

Value

0.175
0.84 300 190 243 3.6 >1.5 1.9 5.1 >40 n.m. 2.4 n.m. 22 21 75

0.21
0.84 300 200 225 3.9 >1.5 1.9 5.0 >40 3.8 2.8 3.0 18 16 85

a

Unit

0.21
0.84 300 202 186 4.3 >1.5 >1.85 4.5 >40 3.8 3.3 3.0 19 16 110

2

mm

GHz GHz ps V V V V fF fF fF V V V

Remark Drawn dimensions @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2)V.

b

7 Gate delay time (ps)

T = 300 K 6

AE = 0.21⫻0.84 µm2

5

∆V = 300 mV VEE = −2.5 V

Impl. extr. base

4 AE = 0.175⫻0.84 µm

2 Elevated extr. base

3 1

10 Current per gate (mA)

FIGURE 3.9.8 CML ring oscillator gate delay vs. current per gate for oscillators with 53 stages. Devices with elevated extrinsic base and different emitter dimensions are compared with the standard SGC25C HBTs (with implanted extrinsic base). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

3.9.4 High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology The availability of both npn- and pnp-type bipolar transistors with matched performance in a complementary BiCMOS process (CBiCMOS) is a promising route to applications simultaneously requiring low voltage, low power, and high speed. IHP has developed a high-speed CBiCMOS process with bipolar parameters summarized in Table 3.9.4 [15]. This process offers pnp SiGe:C HBTs with peak fT/fmax values of 80 GHz/120 GHz (Figure 3.9.9) at 2.6 V BVCEO and a CML ring oscillator delay of 8.9 psec

© 2006 by Taylor & Francis Group, LLC

3.9-330

The Silicon Heterostructure Handbook TABLE 3.9.4

CBiCMOS HBT Parameters (From Ref. [15].) (AE ¼ 0.21
0.84 mm2) npn

pnp

Parameter

Value

Value

Unit

Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCES Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

160 180 185 4.6 >1.5 2.0 5.0 150 4.5 3.6 3.0 19 16 123

180 80 120 8.9 >2.5 2.6 5.5 40 5.3 3.0 4.0 22 50 147

GHz GHz ps V V V V fF fF fF V V V

fT or fmax (GHz)

200 150

Remark @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA @ 10 mA @ 10 mA @ VBE ¼ 0.7 V @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

A E = 2⫻ (0.21⫻0.84) µm2

npn

VCE = 1.5 V pnp-only

100

fmax pnp

50 fT 0

10−4

10−3 Collector current (A)

10−2

FIGURE 3.9.9 Transit frequency (fT) and maximum oscillation frequency (fmax) vs. collector current for pnp and npn HBTs fabricated on the same wafer in the CBiCMOS and for pnp devices from a pnp-only BiCMOS. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

(Table 3.9.4). The simultaneously fabricated npn SiGe:C HBTs show fT/fmax values of 180 GHz/185 GHz, i.e., a performance almost as high as that of the SGC25C process, despite a changed emitter construction and the additional thermal budget within the CBiCMOS process. A pnp-only, reference BiCMOS flow even produced peak fT/fmax values for the pnp devices of 115 GHz/115 GHz (Figure 3.9.9). This pnp RF performance of CBiCMOS and pnp-only BiCMOS surpasses the best reported values of this transistor type substantially. The strong performance gain of the pnp HBTs is mainly due to a highly tuned vertical doping profile, taking full advantage of the reduced P diffusion in the C-doped base [16] combined with the special collector construction of IHP’s 200 GHz npn transistors. This construction allows one to integrate an isolated pnp into a CMOS process easily, while simultaneously minimizing collector resistance and capacitance. CBiCMOS process flow and transistor cross sections are shown in Figure 3.9.10 and Figure 3.9.11. The RF CMOS baseline is the same as used for the SGC (npn-only) process family. Up to the npn base layer epitaxy the process flow is identical to SGC25C. Then, the collector regions of the pnp transistors are

© 2006 by Taylor & Francis Group, LLC

3.9-331

Industry Examples at the State-of-the-Art: IHP

CBiCMOS PROCESS FLOW

Gate etch (M6), Spacer formation BIPOLAR (NPN+PNP) MODULE (M7)-(M16) Deposition of CMOS protection layers (M7): Opening npn regions+ High dose npn collector implant + RTA Oxide deposition (M8): Opening active npn coll. regions npn base epitaxy

NPN

PNP

(M9): Opening pnp regions + High dose pnp collector implant + n-isolation implant + RTA Oxide deposition (M10): Opening active pnp coll. regions pnp base epitaxy (M11): Structuring pnp emitter window etch stop layer + base link implant

(M12): Opening npn em. window + SIC As doped npn emitter deposition (M13): Opening pnp em. window + SIC B doped pnp emitter deposition (M14): Structuring pnp poly emitters (M15): Structuring npn emitter + pnp base poly (M16): Implantation of npn base and pnp collector contacts Removing CMOS protection layers by wet etch S/D implantations (M17, M18) ... Passivation (M30)

FIGURE 3.9.10 Flow of the complementary BiCMOS process.

Base

Emitter

Collector

Base

Emitter

Collector

npn Emitter Poly pnp Base Poly SIC

n+ S/D

High doped collector

SIC

p+

n+ S/D

High doped collector

n-Isolation

n well

FIGURE 3.9.11 Schematic cross section of the npn HBT structure (left) and the pnp HBT structure (right) of the complementary BiCMOS process. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.9-332

The Silicon Heterostructure Handbook

formed in analogy with the npn flow. In addition to the collector well implant, a high-energy implantation is applied for the vertical isolation of the pnp. The pnp epitaxy stack consists of a Si buffer layer, the P-doped SiGe:C layer (30 nm thick), delivering a pinched sheet resistance of about 10 kV/sq, and a Si cap layer. A total of ten mask steps are used for the complementary bipolar module, five for the pnp and four for the npn, and one common mask step for structuring npn emitter poly and pnp base poly. The demonstrated RF performance, the high early voltages (Table 3.9.4) and further results, such as the only weak sensitivity of b and peak fT to the collector bias [15], indicate that valence band barrier effects, a serious problem of pnp HBTs, are largely suppressed before onset of the Kirk effect by a careful profile design at the base–collector junction. A major concern with such heavily doped, rapidly annealed devices, as produced in SGC25C and CBiCMOS is the defect density. The Gummel plots of both npn and pnp 4k HBT arrays, shown in Figure 3.9.12, prove that this problem has been successfully solved for both HBT types.

3.9.5 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) The majority of current BiCMOS applications, in particular in the wireless area, have more modest speed requirements, typically below 100 GHz, but are highly cost-sensitive. Therefore, IHP has developed, in addition to the technologies with high-performance HBTs, a very simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high-volume applications. The technology, called SGB25V, is a 0.25 mm BiCMOS SiGe:C HBT process with only 19 lithographic steps, offering four levels of Al and a full menu of active and passive devices (Table 3.9.5). Three different SiGe:C HBTs can be fabricated simultaneously by adding a single lithography level to the underlying RF CMOS process. These devices offer BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. The further device menu includes 2.5 V VDD MOS transistors for digital applications, an isolated NMOS device, an accumulation type MOS varactor, a junction varactor, three polysilicon resistors with sheet resistances ranging from 6 V/sq. to 2 kV/sq., a 2-mm thick upper Al layer for high-Q inductor fabrication, and a 1 fF/mm2 MIM.

10−1

10−1

10−2 Base, collector current (A)

npn

pnp

10−2

5 arrays AE = 4096⫻ (0.21⫻0.84) µm2

10−3 10−4 10−5

10−3 10−4 10−5

10−6

10−6

10−7

10−7

10−8

VCB = 0 V

10−8

10−9

T = 300 K

10−9

10−10

−0.8

−0.6

−0.4 0.4 0.6 Base−emitter voltage (V)

10−10 0.8

FIGURE 3.9.12 Gummel plots of pnp and npn HBT arrays fabricated in the CBiCMOS flow. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.9-333

Industry Examples at the State-of-the-Art: IHP TABLE 3.9.5

SGB25V HBT, MOS, and Passives Parameters

Device

Parameter

Value

Unit

Remark

2

SGB25V HBT parameters (AE ¼ 0.5
0.9 mm ) Current gain BVEBO

190 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

npn-H

Peak fT/fmax BVCEO BVCES

30 / 70 7 >20

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-S

Peak fT/fmax BVCEO BVCES

50 / 95 4.0 16

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-P

Peak fT/fmax BVCEO BVCES

80 / 95 2.4 7.7

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-H,S,P

SGB25V MOS and Passives Parameters NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

570 3 0.61 0.22

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

290 3 0.51 0.185

mA/mm pA/mm V mm

@ VDS ¼ 2.5V

MOS Varactor

Identical to SGC processes

pþn Varactor

Tuning ratio Q factors (@ low/high C)

1.7:1 35 / 20

Salicide Resistor

Sheet resistance Temperature coefficient

6.8 2950

V/sq. ppm/K

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

310 105 0.64

V/sq ppm/K ppm/K2

Gate poly (pþ) 408C to 1258C

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

2000 2760 6.1

V/sq ppm/K ppm/K2

Low-doped gate poly

MIM Capacitor Inductors

Identical to SGC processes Identical to SGC processes

@ 5 GHz

408C to 1258C

a

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm2 part of the VCE(IC) characteristics.

The CMOS backbone of SGB25V differs from that CMOS baseline used for the SGC25 processes and for a SGB25V pre-production version [17]. The process changes allowed us to release MOS devices with lower leff, and led to a strong yield increase for dense CMOS sections, which use the shorter devices. Moreover, a set of polysilicon resistors is now available, providing a wider range of sheet resistance values compared to the SGC process family. The SGB25V process flow is shown in Figure 3.9.13. HBT fabrication starts after depositing the MOS gates and a Si3N4 protection layer. The single HBT mask is used to remove by RIE the nitride film and the gate material from the HBT regions, and to carry out a chain of P implants. After wet etching the gate oxide, the SiGe:C base and a Si LDE layer are successively grown. L-shaped inside spacers are formed, a SIC implantation is carried out, and an As-doped emitter Si layer is deposited. Then, emitter and base

© 2006 by Taylor & Francis Group, LLC

3.9-334

The Silicon Heterostructure Handbook

SGB25V PROCESS FLOW

Shallow trench etch (M1) and fill Deep n-well implantation (M2), RTA MOS well implantations (M3, M4), RTA Gate oxidation, Gate poly deposition

Gate etch (M6), Spacer formation S/D implantations (M7, M8), RTA Salblock(M9), Co salicide formation Contact (M10), Met-1 (M11) Via-1 (M12), MIM (M13), Met-2 (M14) Via-2 (M15), Met-3 (M16) Via-3 (M17), Met-4 (M18) Passivation (M19)

FIGURE 3.9.13

• • • •

19 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide HBT MODULE (M5)

Nitride layer for CMOS protection (M5): Opening active collector regions + Low dose collector implants Non-selectiveSi/ SiGe:C/ Si epitaxy Forming oxide inside spacers + SIC As doped emitter deposition CMP (Si, SiGe) with stop on nitride Removing nitride layer by wet etch • • • •

Co salicide CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

Flow and features of the SGB25V process.

material are removed by CMP from the Si3N4 layer surface to isolate the emitter from the extrinsic base. After wet etching the nitride film from the gate stack, CMOS device fabrication is continued. The gate structuring process and the PMOS S/D implants are also used to form and dope the HBT extrinsic base regions, respectively. Note that using gate-poly as material for the HBT extrinsic base is not the only advantage of the special HBT integration scheme applied here. It also minimizes the impact of the HBT thermal steps on the MOS characteristics. However, we would not have been able to take advantage of these without doping the HBTs with C. This prevents B out-diffusion from SiGe, and thus HBT parameter degradation, by CMOS thermal steps such as poly-reoxidation and S/D RTA, which are carried out after HBT integration. Figure 3.9.14 shows fT vs. collector current curves for the HBTs simultaneously fabricated in SGB25V. The differences in the fT and BVCEO values are produced by varying the layout for the deep P implant for the CMOS triple-well option, and using the PMOS well implants (Figure 3.9.15). The SGB25V HBT yield (estimated for 4k device arrays) exceeds 90%, matching the numbers obtained with our other BiCMOS processes. VLSI ability of the process is controlled with an 1M SRAM as test vehicle. To study the impact of HBT integration on the yield of this 6-million transistor device, lots were fabricated with and without HBT module. Figure 3.9.16 demonstrates a typical SRAM yield of around 70% for both cases showing that the HBT integration scheme, used for SGB25V, is modular and has no negative impact on the yield of dense CMOS sections. Moreover, it shows that SGB25V guarantees high yield for VLSI CMOS segments necessary for a cost-effective fabrication of RF-SOCs.

3.9.6 Circuit Applications of IHP’s SiGe:C Technologies IHP’s BiCMOS technologies, described in the previous sections, differ in the level of maturity. SGC25A, SGC25B, SGC25C (implanted HBT version), and SGB25V are fully developed and characterized processes which we were able to release for the access of both in-house and external designers. These processes are also offered as EUROPRACTICE platforms. In contrast, the SGC25C version with elevated extrinsic base as well as the CBiCMOS process have pre-production status. Therefore, the access to these processes is presently restricted to in-house designers and a few longtime partners. For IHP’s BiCMOS technologies design kits are available which support a Cadence mixed signal platform. For HBT characterization, the VBIC model is applied [18].

© 2006 by Taylor & Francis Group, LLC

3.9-335

Industry Examples at the State-of-the-Art: IHP

Transit frequency (GHz)

80 70

npn-P

2.4V

60

VCE = 2 V

BVCEO

50 40

4.2 V

npn-S

30 20

npn-H

AE = 10⫻(0.5⫻0.9) µm2

7V

10 0.000

0.005

0.010

0.015

0.020

Collector current (A)

FIGURE 3.9.14 Transit frequency vs. collector current for the three HBT types fabricated in the SGB25V process (npn-P, npn-S, npn-H). The different curves for the same HBT type illustrate the typical scattering across a wafer.

Polysilicon emitter

Gate polysilicon npn-H n+ S/D

SIC

STI

n-Well Coll. well (M5) Poly SiGe:C/Si

Deep n-Well (M2)

SiGe:C base npn-S n+ S/D

SIC Coll. Well

n-Well

Deep n-Well Oxide spacer npn-P SIC Coll. Well

n+ S/D n-Well

Deep n-Well

FIGURE 3.9.15 Schematic cross sections of the three HBT types fabricated in the SGB25V process.

In the following section, we present some recent exemplary circuit results obtained with IHP’s highperformance BiCMOS processes because these technologies enable new product application areas. For demonstration, a series of benchmarking circuits were designed and tested successfully. The main results are summarized in Table 3.9.6. Intended applications are very high data rate wireless links in the 60 GHz ISM band and automotive radar at 77 GHz and beyond.

60 GHz Transceiver Circuits For demonstration of new wireless transmission systems with data rates >150 Mb/sec, key circuit blocks for a 60 GHz transceiver system were designed and fabricated [20, 21]. The proposed transceiver is based

© 2006 by Taylor & Francis Group, LLC

3.9-336

The Silicon Heterostructure Handbook

SRAMs measured on 45 wafer sites

1M SRAM wafer yield (%)

100

BEC = 0 (@2.5 V) 80

60

40

A

B

C

D

E

F G

H

I

J

K

L

BiCMOS lots

CMOS 20

Lot ID (A − L)

FIGURE 3.9.16 Wafer yield of 1M SRAMs with a bit error count (BEC) of zero, fabricated in the SGB25V process (BiCMOS lots) or a flow without the SGB25V HBT module (CMOS lots).

TABLE 3.9.6 Measurement Results of Benchmarking Circuits Fabricated in IHP’s High-Performance BiCMOS Processes Circuit

Parameter

Value

Technology

Ref.

Static frequency divider, 1:2

Maximum input frequency

62 GHz

SGC25B

[19]

Dynamic frequency divider, 1:2

Maximum input frequency

72 GHz

SGC25B

[19]

Low power frequency divider, 1:64, 1 V supply

Maximum input frequency Suppply current

2.4 GHz 0.6 mA

SGC25B SGC25B

[19] [19]

60 GHz LNA

Gain @ 61 GHz

9.6 dB

SGC25C

[20]

LC oscillators

Oscillation frequency

24 GHz 60 GHz 76 GHz 97 GHz 117 GHz

SGC25B SGC25B SGC25B SGC25C SGC25C

[21–23]

Ring oscillators

Gate delay

3.6 ps

SGC25C

[14]

on amplitude shift keying (ASK) modulation principle. The reasons for the selection of this modulation technique are its simplicity, the wide bandwidth of the 61 GHz ISM band, and that there is no need for high-performance A/D converters. The transmit path of the transceiver consists of a 61.25 GHz fundamental mode oscillator, a switch, and a power amplifier. Between the modulator and the power amplifier a filter is inserted to reduce spurs. The receiver path consists of a three-stage, lownoise amplifier (LNA), a mixer, a 56 GHz oscillator, a variable gain amplifier, and an ASK demodulator. One task of the LNA design was to get unconditional stability for both on-wafer measurements and for the use of the amplifier in test board modules together with the other receiver components. Especially the use of bond wires for the connection of the ground potential (and the associated inductance) causes serious stability problems if a single-ended configuration is used. That is why all the stages are designed in differential configuration. The input and output are trafo-coupled. The transformer coupling is useful in two ways. First, it acts as a balun for connection to a singleended antenna. Second, the primary and secondary windings of the transformer are tuned to get a band pass characteristic. With this, an additional input filter in the RX path can be omitted and this function is integrated in the LNA. The single stage of the LNA is a differential stage with inductive load and with matching network at the output. The LNA was measured on wafer with a 110 GHz vector network analyzer. The maximum gain is 9.6 dB. The gain-maximum is reached at 61 GHz, which is

© 2006 by Taylor & Francis Group, LLC

3.9-337

Industry Examples at the State-of-the-Art: IHP

exactly the target frequency of the requested ISM band (Figure 3.9.17). The LNA has a band pass characteristic, resulting from the tuned transformers at input and output. With this characteristic, no additional band pass filter is required.

Automotive Radar High-frequency oscillators are key components in modern low-cost radar systems for automotive and other sensor applications. Most of today’s automotive radar systems utilize the frequency bands at 24 and 77 GHz. For future developments, also higher frequency bands at 94 and 140 GHz are of interest. Reasons for the use of higher frequency bands are the further miniaturization of the radar systems and the better beam-forming prospects due to the shorter wavelength. Several LC oscillators for the different frequency ranges were designed and tested [21–23]. The circuit diagram of the oscillators is shown in Figure 3.9.18. The circuit is a common collector Colpitts oscillator in fully differential implementation. With the symmetric circuit, two advantages are reached: first, it gives reduced signal interference via the silicon substrate and, second, the coupling of the highfrequency energy to subsequent building blocks such as integrated amplifiers or mixers is more effective. 0 0 0 The tank is a symmetric circuit of two inductors L1 and L1 and the MIM capacitors C1, C2, C1 , and C2 . In parallel to the capacitor C1 acts the base–emitter capacitor of the bipolar transistor CBE. For explanation, the tank can be divided into two half circuits separated by the symmetry line shown in Figure 3.9.18. In operation, the oscillator-halves are working in the odd mode, such that the outputs are 1808 out of phase. The nodes of the tank, indicated by the symmetry line, have virtual ground. The oscillation frequency can then be estimated to a first order by the following equation: f ¼ 1=(2p

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L1 {2CBC þ [C2 (CBE þ C1 )=(C1 þ C2 þ CBE )]})

where CBC is the base–collector capacitance of the transistors.

Tank circuit Vctrl L1

L⬘1

C1

C1⬘

C2

Out

C2⬘

10 s21

Gain (dB)

0

Symmetry line

−10 −20 −30

VEE

s12

−40 −50 0

20

40 60 80 Frequency (GHz)

100

120

FIGURE 3.9.17 Gain curves of the 60 GHz LNA.

© 2006 by Taylor & Francis Group, LLC

FIGURE 3.9.18 Circuit diagram of the high-frequency oscillator. (From W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

3.9-338

The Silicon Heterostructure Handbook

The oscillators were characterized using an on-wafer test system with GS probes. For determination of the output spectrum a Rohde & Schwartz spectrum analyzer FSEM30 with a mixer unit FS-Z110 was used. The measurement results of three oscillators are summarized in Table 3.9.7. The supply voltage of these oscillators is 3 V or 4 V. The output power is from 7 dB m (oscillator 1) to 12 dB m per output channel (oscillator 3). The frequency of oscillation can be tuned by applying a tuning voltage at the Vctrl input. For oscillator 2, intended for 94 GHz, the tuning range is from 97.5 to 95.2 GHz for the control voltage changing from 2.4 V to 0. Because the target frequency was not met in this design, a redesign has 0 to be done. The capacitance of C2 and C2 will be reduced by a modest amount to shift the frequency to 94 GHz. Figure 3.9.19 shows the measured output spectrum of oscillator 3, which reaches the highest frequency. The tuning range is from 117.2 to 113.7 GHz. The current consumption is within the range of 10 to 28 mA. Of course, the output power will also undergo a change with varying the current flowing through the oscillator. The maximum measured output power is 12 dB m. Within the tunable frequency

TABLE 3.9.7 Measurement Results of Experimental LC Oscillators Fabricated in IHP’s High-Performance BiCMOS Processes Parameter

Oscillator 1

Oscillator 2

Oscillator 3

Oscillation frequency Supply voltage Supply current Center frequency Tuning range Output power Phase noise at 1 MHz offset Chip size

76 GHz 4.0 V 32 mA 76.1 GHz — 7 dB m 91 dBc/Hz 750
400 mm2

97 GHz 3.0 V 15–37 mA 96.15 GHz 2.3 GHz 11.2 dB m 88 dBc/Hz 750
400 mm2

117 GHz 3.0 V 10–28 mA 115.1 GHz 3.5 GHz 12 dB m — 750
400 mm2

Ref L vl −5 dBm

Marker-12.24 dB m 114.92457381 GHz

−10 −20 −30 −40 −50 −60 −70 −80 Center 114.9312472 GHz

10 MHz/

Span 100 MHz

FIGURE 3.9.19 Spectrum of single-ended output for oscillator 3. The center frequency is 114.3 GHz. (From W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-339

range, the output power is above 20 dB m. The phase noise of oscillators 1 and 2 was measured by using a spectrum analyzer. The phase noise is 91 dB c/Hz and 88 dB c/Hz at 1 MHz offset, respectively.

3.9.7 Summary We have described IHP’s modular SiGe:C RF BiCMOS technologies which provide several types of SiGe:C HBTs, combined with a 0.25 mm CMOS core and state-of-the art passive elements. Highperformance npn HBT modules with up to 200 GHz fT, a complementary HBT module with superior pnp performance, and a low-cost HBT module, providing simultaneously three HBT types, can be fabricated in IHP’s BiCMOS processes. This process menu ideally fulfills the technological requirements for the fabrication of modern fiber and wireless communication systems.

Acknowledgments The author would like to thank all IHP colleagues contributing to the HBT and BiCMOS work through the last years. Special thanks goes to B. Heinemann, K.-E. Ehwald, H. Ru¨cker, B. Tillack, and R. Barth who had the strongest impact in the field of process technology. P. Schley, Ha. Erzgra¨ber, and R. Scholz did great jobs in device measurement and characterization. I am also grateful to F. Fuernhammer and G. Grau (Advico) for the efforts to realize an adequate design environment for IHP’s technologies, and to W. Winkler who strongly supported all technology developments by providing suitable benchmark and verification circuits. Last but not least, the author thanks J. Osten who initiated SiGe:C material research at IHP, and A. Ourmazd for excellent management support and many valuable discussions.

References 1. G Ritter, B Tillack, and D Knoll. Successful preparation of high-frequency HBT by integrated RTCVD processes. MRS Symposium Proceedings, 1995, Vol. 387, Rapid Thermal and Integrated Processing IV, pp. 341–346. 2. D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Low cost, 50 GHz fmax Si/SiGe heterojunction bipolar transistor technology with epi-free collector wells. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. 3. D L Harame, E F Crabbe, J D Cressler, J H Comfort, J Y-C Sun, S R Stiffler, E Kobeda, J N Burghartz, M M Gilbert, J C Malinowski, A J Dally, S Ratanaphanyarat, M J Saccamango, W Rausch, J Cotte, C Chu, and J M C Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 4. B Heinemann, D Knoll, G Fischer, D Kru¨ger, G Lippert, H J Osten, H Ru¨cker, W Ro¨pke, P Schley, and B Tillack. Control of steep boron profiles in Si/SiGe heterojunction bipolar transistors. Proceedings of the European Solid-State Device Research Conference, Stuttgart, 1997, pp. 544–547. 5. H J Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe heterobipolar transistor performance and process margin. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1997, pp. 803–806. 6. D Knoll, B Heinemann, H J Osten, K E Ehwald, B Tillack, P Schley, R Barth, M Matthes, K S Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 7. H J Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116. 8. K E Ehwald, D Knoll, B Heinemann, K Chang, J Kirchgessner, R Mauntel, I S Lim, J Steele, P Schley, B Tillack, A Wolff, K Blum, W Winkler, M Pierschel, U Jagdhold, R Barth, T Grabolla, H J Erzgra¨ber,

© 2006 by Taylor & Francis Group, LLC

3.9-340

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

The Silicon Heterostructure Handbook

B Hunger, and H J Osten. Modular integration of high-performance SiGe:C HBTs in a deep submicron, epi-free CMOS process. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 561–564. D Knoll, B Heinemann, K E Ehwald, G G Fischer, and B Hunger. Emitter scaling of singlepolysilicon SiGe:C HBTs with highly doped base layers. Proceedings of the European Solid-State Device Research Conference, Cork, 2000, pp. 560–563. S A St Onge, D L Harame, J S Dunn, S Subbana, D C Ahlgren, G Freeman, B Jagannathan, S J Jeng, K Schonenburg, K Stein, R Groves, D Coolbaugh, N Feilchenfeldt, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, R Johnson, A Joseph, L Lanzerotti, J Malinowski, B Orner, and M Zierak. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm leff CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. B Heinemann, D Knoll, R Barth, D Bolze, K Blum, J Drews, K E Ehwald, G G Fischer, K Ko¨pke, D Kru¨ger, R Kurps, H Ru¨cker, P Schley, W Winkler, and H E Wulf. Cost-effective high-performance high-voltage SiGe:C HBTs with 100GHz fT and BVCEO
fT products exceeding 220 V GHz. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2001, pp. 348–351. D Knoll, B Heinemann, K E Ehwald, H Ru¨cker, B Tillack, W Winkler, and P Schley. BiCMOS integration of SiGe:C heterojunction bipolar transistors. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 162–166. B Heinemann, H Ru¨cker, R Barth, J Bauer, D Bolze, E Bugiel, J Drews, K E Ehwald, T Grabolla, U Haak, W Ho¨ppner, D Knoll, D Kru¨ger, B Kuck, R Kurps, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, D Wolansky, H E Wulf, Y Yamamoto, and P Zaumseil. Novel collector design for high-speed SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 775–778. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. H Ru¨cker, B Heinemann, D Bolze, D Knoll, D Kru¨ger, R Kurps, H J Osten, P Schley, B Tillack, and P Zaumseil. Dopant diffusion in C-doped Si and SiGe: Physical model and experimental verification. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 345–348. D Knoll, K E Ehwald, B Heinemann, A Fox, K Blum, H Ru¨cker, F Fu¨rnhammer, B Senapati, R Barth, U Haak, W Ho¨ppner, J Drews, R Kurps, S Marschmeyer, H H Richter, T Grabolla, B Kuck, O Fursenko, P Schley, R F Scholz, B Tillack, Y Yamamoto, K Ko¨pke, H E Wulf, D Wolansky, and W Winkler. A flexible, low-cost, high performance SiGe:C BiCMOS process with a one-mask HBT module. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 783–786. B Senapati, R F Scholz, D Knoll, B Heinemann, and A Chakravorti. Application of the VBIC model for SiGe:C heterojunction bipolar transistors. Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, 2004. W Winkler, J Borngra¨ber, B Heinemann, P Weger, and H Gustat. High-performance and low-voltage divider circuits fabricated in SiGe:C HBT technology. Proceedings of the European Solid-State Circuits Conference, Firenze, 2002, pp. 827–830. W Winkler, J. Borngra¨ber, H Gustat, and F Korndo¨rfer. 60 GHz transceiver circuits in SiGe:C BiCMOS technology. Proceedings of the 30th European Solid-State Circuits Conference, Leuven, 2004, pp. 83–86.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: IHP

3.9-341

21. W Winkler, J Borngra¨ber, B Heinemann, and P Weger. 60 GHz and 76 GHz oscillators in 0.25 mm SiGe:C BiCMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, 2003, pp. 454–455. 22. W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. 23. W Winkler and J Borngra¨ber. LC-oscillator for 94 GHz automotive radar system fabricated in SiGe:C BiCMOS technology. Conference Proceedings of the 12th European Gallium Arsenide & other Compound Semiconductors Application Symposium, Amsterdam, 2004, pp. 45–46.

© 2006 by Taylor & Francis Group, LLC

3.10 Industry Examples at the State-of-the-Art: ST A. Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy ST Microelectronics

3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 3.10.6

Introduction........................................................... 3.10-343 Device Structures................................................... 3.10-344 Doping and Impurity Profiles.............................. 3.10-347 BiCMOS Integration Issues .................................. 3.10-348 High-Frequency Characteristics ........................... 3.10-351 Outlook for the Future ......................................... 3.10-353

3.10.1 Introduction The history of SiGe BiCMOS technology development in the ‘‘French silicon valley’’ goes back to the early 1990s [1], when a team of materials researchers at France Telecom CNET Laboratories near Grenoble started investigations in the Si/SiGe system using rapid thermal chemical vapor deposition (RTCVD). Application of this work to the development of heterojunction bipolar transistors (HBTs) soon became a major research theme for the local bipolar device group [2–4]. At the same time, the development of a 0.5-mm single-polysilicon BiCMOS technology was going on in the new 200 mm Crolles plant of STMicroelectronics, a few kilometers away. A joint development work was then initiated between the two teams, with the objective to bring SiGe HBTs into manufacturing when the performance potential of silicon-only bipolar transistors would be fully exhausted [5]. This eventually happened with the 25/40 GHz fT/fmax double-polysilicon self-aligned transistor embedded in the 0.35-mm BiCMOS process. When it was internally demonstrated that much better performance, e.g., 50/70 GHz fT/fmax, could be obtained at the same technology node using a low-complexity SiGe HBT architecture [6], SiGe BiCMOS technology development at ST became a reality. Several SiGe BiCMOS processes, covering the 0.35, 0.25, and 0.13 mm technology nodes, and addressing both wireless and broadband communications applications, have been developed since then, and are now in production or at prototyping level at the Crolles plant. Table 3.10.1 outlines the main technological features of these processes, in terms of device isolation scheme, SiGe epitaxial base process, emitter–base and collector architectures, and emitter material. Main static and dynamic parameters of the high-speed SiGe HBT in these technologies are also summarized. A common feature of all these processes is the use of RTCVD for the growth of the SiGe (or SiGe:C) base. As discussed in Chapter 2.3, RTCVD presents many advantages over competing approaches, and is today the dominant technique for conventional Si epitaxy as well as advanced SiGe processes in the semiconductor industry. Likewise, all technologies rely on a conventional collector structure, consisting of a heavily arsenic-implanted layer buried under lightly doped epitaxial silicon. In contrast with these longstanding technological options, Table 3.10.1 shows that several materials and architecture changes have been brought to the SiGe HBT while moving along the performance path from 45 to 160 GHz fT. The motivations for these structural changes and the accompanying evolutions of transistor doping and impurity profiles are discussed in Sections 3.10.2 and 3.10.3, respectively. Section 3.10.4 addresses some 3.10-343 © 2006 by Taylor & Francis Group, LLC

3.10-344

The Silicon Heterostructure Handbook

TABLE 3.10.1 ST SiGe BiCMOS Technologies: Main Process Features and Device Parameters Technology

BiCMOS6G

BiCMOS7

BiCMOS7RF

BiCMOS9

CMOS node Back-end

0.35 mm Al

0.25 mm Al

0.25 mm Al

0.13 mm Cu

Collector Isolation Base E/B architecture Emitter

BL/epitaxy LOCOS SiGe NSEG QSA single-poly As implant Poly

BL/epitaxy STI/DTI SiGe NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

WE (mm) RpB (kV/sq) Basewidth (nm)

0.4 10 —

0.25 6.5
50

0.25 1 —

0.17 3.6
25

Current gain BVCEO (V) VAF (V) fT (GHz) fmax (GHz) JC (mA/mm2) NFmin @ 2 GHz

100 3.6 60 45 60 1.0 0.8

120 2.6 >50 70 90 3.8 —

200 3.0 >150 60 120 1.8 <0.4

600 1.7 >150 160 160 7.5 —

Applications Status

RF Production

Broadband Production

RF, PA Prototyping

Broadband Prototyping

Refs.

[8]

[9]

[15,16]

[17]

of the issues that have been encountered while integrating these HBTs into the corresponding CMOS flows. Main high-frequency characteristics of the SiGe HBT in the various technologies are reviewed in Section 3.10.5. Finally, Section 3.10.6 concludes the chapter with early results from the development of next generation transistors, targeting 230 GHz cutoff frequencies for the 90-nm technology node.

3.10.2

Device Structures

Figure 3.10.1 displays SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies. The geometrical scale can be inferred from the contact size, i.e., 0.4 mm in (a), 0.25 mm in (b and c) and 0.16 mm in (d). A glance at the pictures shows that, in all technologies, the SiGe base is grown using nonselective epitaxy (NSEG). Compared to the alternative selective deposition process (SEG), this approach presents several advantages [7]: simpler chemistry, larger growth rates (or lower growth temperature), reduced macro- and microloading effects, and improved metrology. Unfortunately, these advantages on the manufacturability side come at the expense of a penalty on the performance side. Indeed, there is no simple way to build a SiGe HBT with fully self-aligned (FSA) emitter–base (E–B) regions on a nonselective base. As briefly discussed in Section 3.10.6, there are only complex solutions to this problem, which (at least partly) outbalance the advantages of NSEG over SEG structures. A pragmatic answer to this manufacturability vs. performance trade-off is provided by the family of quasiself-aligned (QSA) HBT structures implemented in ST SiGe BiCMOS technologies. As shown in Figure 3.10.1(a), a single-polysilicon QSA structure is used in BiCMOS-6G [8], which mainly addresses the RF mobile communications market. In this construction, the poly-SiGe extension of the base formed on the field oxide (here LOCOS) during epitaxy is used as the extrinsic base material. The emitter (width WE ¼ 0.4 mm) is defined by a window opened in a thin deposited nitride/oxide stack. The low topography of the structure enables the use of a conventional arsenic-implanted polysilicon emitter, which is subsequently patterned around the emitter window using a second

© 2006 by Taylor & Francis Group, LLC

3.10-345

Industry Examples at the State-of-the-Art: ST

(a)

(b)

(c)

(d)

FIGURE 3.10.1 SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies: (a) BiCMOS-6G, (b) and (c) BiCMOS-7 and -7RF, (d) BiCMOS-9. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.)

© 2006 by Taylor & Francis Group, LLC

3.10-346

The Silicon Heterostructure Handbook

lithography level. An extrinsic base implant is then performed self-aligned to the polysilicon emitter block (i.e., not to the emitter), followed by dopant activation and salicidation. This single-polysilicon QSA structure is very simple and ideally meets the performance needs of BiCMOS-6G (45/60 GHz fT/fmax). However, several limitations have been foreseen when considering the significantly higher performances (70/90 GHz fT/fmax) targeted for the second generation technology, BiCMOS-7: (i) narrow emitter windows (below 0.3 mm) are difficult to obtain using this process, which penalizes base resistance-related parameters (e.g., fmax, NFmin) and power consumption; (ii) good silicidation of the poly/mono-SiGe/Si boundary region at the edge of the active area is difficult, which penalizes the base access resistance; (iii) point defects injected at the emitter periphery during extrinsic base implantation cause enhanced boron diffusion and base widening [3], which negatively impacts the forward transit time (fT). The double-polysilicon QSA structure developed for BiCMOS-7 successfully addresses all these limitations* [9]. As shown in Fig. 3.10.1b and c, shallow/deep trench isolation (STI/DTI) is used in this technology, which reduces parasitic capacitances and provides a flat topography after SiGe base epitaxy. A conventional double-polysilicon structure is constructed above the base, resulting in the following advantages regarding items (i) to (iii) above: (i) internal spacers reduce the effective emitter width from the emitter window opening, enabling narrow emitters (WE ¼ 0.25 mm) without specific lithography requirements; (ii) extrinsic base silicidation is greatly improved by the availability of a true polysilicon base layer (on top of the poly-SiGe extension of the base), and by the flat topography of the structure at the edges of the base active area; (iii) the extrinsic-to-intrinsic base contact region is formed by the out-diffusion of boron from the base polysilicon layer, avoiding base widening effects related to high-dose implants through the SiGe layer. In order to prevent overetching into the thin epitaxial base during emitter window opening, a polysilicon/oxide pedestal is patterned on the SiGe base prior to base polysilicon deposition, as visible in Figure 3.10.1(c). As a result, emitter and base regions are not self-aligned in this structure either. However, it has been found that a proper overlay strategy with present-day steppers allows enough process margin for the emitter window enclosure by this etch-stop layer, while easily meeting BiCMOS-7 performance targets. A closer look at Figure 3.10.1(c) also reveals a significant difference in the crystalline structure of the emitter, when compared with the first-generation transistor. Indeed, due to the larger topography of the structure at the emitter deposition step, in-situ arsenic-doped polysilicon is used in BiCMOS-7 to avoid emitter perimeter depletion and plug effects. This material is deposited in a commercial singlewafer CVD reactor. Load locks and a very clean ambient eliminate any unwanted oxide layer at the polySi–Si interface, resulting in monocrystalline structure on the active transistor region and in polycrystalline structure on the surrounding isolation regions at the end of the process (Figure 3.10.2). These socalled monoemitters have many advantages over conventional polyemitters [10, 11]: (i) very shallow and uniform E/B junction depths are obtained; (ii) manufacturability issues related to the control and reproducibility of the interfacial oxide layer are suppressed; (ii) emitter resistance and low frequency noise are significantly reduced; (iii) base current is increased, which translates into an improved emitterto-collector breakdown voltage, BVCEO. It should be pointed out that this monocrystalline emitter process was first described in Ref. [12], and is now becoming a standard in the SiGe BiCMOS technology industry. Extension to a SiGe emitter process has also been proposed recently [13]. The range of performances achievable with the double-polysilicon QSA HBT structure has been dramatically extended by introducing SiGe:C base technology [14]. The device used in BiCMOS-7RF, which addresses RF [15] and power amplifier [16] applications, is structurally and geometrically identical to the BiCMOS-7 transistor shown in Figure 3.10.1b and c. Here, carbon doping of SiGe is *It should be pointed out that the latter two effects (ii) and (iii) are minimized in more recent technologies using shallow trench isolation (STI) instead of LOCOS (this reduces the topography of the structure at the edges of the base active area), and carbon-doping of the SiGe base (which suppresses to a large extent transient enhanced diffusion effects caused by the extrinsic base implant).

© 2006 by Taylor & Francis Group, LLC

3.10-347

Industry Examples at the State-of-the-Art: ST

Poly

Epi

SiGe base 60 nm

FIGURE 3.10.2 TEM cross section showing the monocrystalline structure of the emitter in ST BiCMOS-7 technology (similar emitter structure is used in BiCMOS-7RF and -9).

leveraged to improve high-frequency noise figures by enabling much larger integrated base doping concentration. In contrast, the SiGe:C process developed for BiCMOS-9 aims at producing devices with ultrathin bases, in order to comply with the very high cutoff frequencies (160 GHz fT and fmax) required for broadband communications applications [17]. As shown in Figure 3.10.1(d), the transistor structure has been scaled vertically and laterally while moving to 0.13 mm technology node. Vertical scaling was imposed by CMOS compatibility constraints, as discussed in Section 3.10.4. Horizontal scaling, with final emitter widths of
0.17 mm, minimizes the intrinsic component of the base resistance, as well as parasitic elements such as collector resistance and collector/base (C/B) capacitance, which is needed to reach frequency performance targets. Moreover, a reduced emitter stripe width is mandatory to accommodate the increased current density at peak fT in this technology (see Figure 3.10.9).

3.10.3 Doping and Impurity Profiles Transistor doping and impurity profiles have also greatly evolved throughout these developments. The main features of these profiles and the motivations for these evolutions are discussed in this section, with the help of the schematic drawings shown in Figure 3.10.3. BiCMOS-6G and -7, which use a pure SiGe base (i.e., without carbon doping), rely on a ‘‘conventional’’ E/B dopant distribution, where the arsenic profile intercepts the boron profile close to its maximum value (Figure 3.10.3(a)). The doping level there is typically limited to
5  1018 cm3 to avoid tunneling currents and excessive E/B junction capacitance. A two-step germanium profile is used in the base, with larger concentration on the collector side than on the emitter side. This profile serves several purposes and is designed as follows: (i) the Ge content of the lower step sets (to a large extent) the current gain of the transistor; (ii) the flat Ge profile at the E/B junction stabilizes the current gain against fluctuations in the junction depth and improves the reverse Early voltage (as compared to a graded Ge profile); (iii) the larger Ge concentration on the collector side reduces boron diffusion and base widening during processing; (iv) the Ge step in the base creates a pseudoelectric field, which reduces base transit time and improves fT; and (v) the difference in the Ge content between C/B and E/B

© 2006 by Taylor & Francis Group, LLC

3.10-348

The Silicon Heterostructure Handbook

SiGe HBT

Ge B

SiGe:C HBT Ge

As

Concentration

Concentration

As

B

P

P

(a)

Depth

(b)

Depth

FIGURE 3.10.3 Schematic evolution of transistor doping and impurity profiles through ST SiGe BiCMOS technologies: (a) BiCMOS-6G and -7, (b) BiCMOS-7RF (dashed lines), and BiCMOS-9 (solid lines).

junctions increases the forward Early voltage of the transistor. It shoud be pointed out that the whole profile has been scaled down while moving from BiCMOS-6G to -7, in order to comply with the frequency performance increase (final basewidth WB is
50 nm in the latter process). This has been highly facilitated by the introduction of the monoemitter process discussed above. The collector doping, set by a masked implantation prior to SiGe base deposition, has also been adjusted (i.e., increased). No change has been brought to the collector epitaxy thickness. Doping and Ge profiles used in BiCMOS-9 and 7RF SiGe:C technologies are significantly different from the above discussed profiles (Figure 3.10.3(b)). Their main features can be summarized as follows: (i) a bell-shaped boron distribution with peak doping concentration significantly above 1019 cm3 is used in the base, which is made possible by the strong reduction of boron diffusion in SiGe:C [14]; (ii) there is no overlap between arsenic and boron profiles, which keeps E/B junction capacitance low despite the heavy base doping level; (iii) the Ge content is graded across the base on the emitter side, in order to compensate the retarding electric field associated with the retrograde boron profile; (iv) a flat Ge profile is used on the collector side, where an accelerating field is created by the boron distribution itself. Such trapezoidal Ge profile has been found optimum to avoid layer stability issues and high injection induced barrier effects in high-voltage transistors, which can been encountered with triangular Ge profiles. As shown in Figure 3.10.3(b), different optimizations of this generic SiGe:C HBT profile are used in BiCMOS-9 and -7RF. BiCMOS-9 favors a short forward transit time to reach the high fT target. This is obtained using a very thin base (WB
25 nm), a high collector doping, and a thin collector epitaxy. Despite the narrow base, pinched base resistance remains low (RpB
3.6kV/sq.) thanks to the heavy boron doping, enabling simultaneously high fT and fmax in this technology. In contrast, noise figure and analog characteristics are given prior attention in BiCMOS-7RF. To this end, the boron spike width (and the whole SiGe:C stack) has been enlarged, leading to very low base resistance (RpB
1 kV/sq). Also, larger spacing is used between arsenic and boron profiles (through the thickness of the silicon-capping layer), which reduces E/B junction capacitance and improves low current characteristics. The collector structure in this technology is similar to BiCMOS-7. As detailed in Refs. [15, 17], the carbon concentration in both SiGe:C technologies has been carefully optimized to effectively suppress boron diffusion during processing, while avoiding E/B and neutral base recombination effects observed at excessively large carbon contents.

3.10.4

BiCMOS Integration Issues

One major challenge of BiCMOS integration engineers is to design a process flow in such a way that bipolar transistors can be added without disturbing CMOS devices, in order to retain full compatibility

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

3.10-349

with existing logic libraries. This has become increasingly difficult, with the downscaling of CMOS gate lengths and the upscaling of bipolar cutoff frequencies. BiCMOS integration issues are briefly reviewed in this section, with special emphasis on ST’s most challenging technology in this respect, i.e., BiCMOS-9. Generally speaking, the integration of a high-speed HBT within an advanced CMOS technology raises several types of concerns: (i) Thermal cycle issues. The process flow must be designed to avoid substantial CMOS dopant motion due to the addition of the HBT fabrication steps. The hydrogen pre-bake used in RTCVD to clean the base active area prior to SiGe epitaxy is particularly critical in this regard. Symmetrically, high-temperature CMOS processing must be placed prior to the HBT formation to minimize base broadening. It should be pointed out that the use of SiGe:C is very helpful, due to the blocking effect of carbon on the diffusion of boron. Arsenic emitter doping (as opposed to phosphorous) is also favorable, since it is compatible with the final activation anneal of the CMOS process, that the HBT is usually exposed to. (ii) Structural integration issues. The fabrication of the HBT in the presence of CMOS gate topography requires careful choice of integration sequence. Numerous films are deposited during the HBT formation, as illustrated on Figure 3.10.4 which shows the accumulation of some of these films over closely spaced 0.13-mm gates in BiCMOS-9. Subsequent etch steps must isotropically remove these films without leaving unwanted spacers. Another difficulty encountered in the development of BiCMOS-9 is related to the thin photoresists used for critical lithography steps, such as gate patterning. The topography of the adjacent bipolar areas must then be low enough to ensure that sufficient resist be left there to avoid damaging the HBTs while processing CMOS gates. (iii) Back-end compatibility issues. Thin premetal dielectric layers are used in advanced CMOS technologies to reduce the contact hole aspect ratio. This raises concerns in a BiCMOS process, where bipolar transistors are usually higher than CMOS devices, and justifies the significant vertical scaling applied to the double-polysilicon QSA HBT structure while moving to 0.13-mm technology node (see Figure 3.10.1(c and d)). Electromigration issues must also be paid attention in high-speed SiGe BiCMOS technologies, where large current densities (JC) can be attained at peak fT. In BiCMOS-9 where JC
7.5 mA/mm2, full compatibility with the back-end rules of the core CMOS process has been maintained by developing a specific transistor layout, with two rows of contacts (and vias) on emitter and collector regions (see Figure 3.10.1(d)). A generic process flow for ST SiGe BiCMOS technologies is shown in Figure 3.10.5. In all processes, the fabrication starts with buried layer formation on a p-substrate, followed by collector epitaxy. The DTI module is then inserted (except in BiCMOS-6G). Next, the shallow trench module (or LOCOS for BiCMOS-6G) of the CMOS core process is implemented, and the collector reachthrough is formed. At

FIGURE 3.10.4 SEM cross section showing closely spaced 0.13-mm CMOS gates covered by SiGe:C HBT films in ST BiCMOS-9 technology.

© 2006 by Taylor & Francis Group, LLC

3.10-350

The Silicon Heterostructure Handbook

CMOS backbone

Bipolar steps

Shallow trench isolation

Buried layer and collector epitaxy Deep trench isolation Collector reachthrough

Well implants Gate oxide process Poly gate

Extension & S/D implants Activation anneal Salicidation and contacts Metal interconnect

SIC implant Base epitaxy Emitter−base structure

FIGURE 3.10.5 Schematic integration flow for ST SiGe BiCMOS technologies, showing insertion of bipolar modules into the CMOS core process.

FIGURE 3.10.6 Saturation current vs. threshold voltage for 1.2 V low leakage nMOS and pMOS transistors in 0.13 mm pure CMOS and BiCMOS-9 technologies. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and

this stage, the CMOS flow resumes with the formation of wells, gate oxides, and polysilicon gates. Deviations then exist regarding the fabrication of the emitter–base structure of the HBT. In BiCMOS6G, 7, and 7RF, where the main concern was the integrity of the pMOS transistor, the whole E/B module is inserted between extension and source/drain implants, in order to avoid boron penetration through the gate oxide. The situation is more complex in the case of BiCMOS-9, where both CMOS and bipolar devices have become very touchy. A novel integration scheme has been developed for this technology [17], in which E/B fabrication steps are split into two parts, in such a way that all integration issues discussed in concerns (i) and (ii) are solved. Finally, all fabrication sequences are completed by the activation anneal of dopants, salicidation, contact formation, and metallization. Figure 3.10.6 compares 0.13-mm pure CMOS and BiCMOS-9 technologies regarding the saturation current and the threshold voltage of nMOS and pMOS transistors. The results demonstrate the successful integration of the high-speed SiGe:C HBT with the newly developed BiCMOS integration scheme.

© 2006 by Taylor & Francis Group, LLC

3.10-351

Industry Examples at the State-of-the-Art: ST

3.10.5 High-Frequency Characteristics Figure 3.10.7 and Figure 3.10.8 summarize high-frequency figures-of-merit fT vs. BVCEO and fmax vs. fT for the low-voltage SiGe HBT in the various technologies discussed above, and for a high-voltage device obtained in BiCMOS-7RF and -9 by altering the collector doping profile. Shown values of fT and fmax are

A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.) 200

BC6G BC7 150

BC7RF

fT (GHz)

BC9 180

270

BC7RF-HV

100

BC9-HV

50 f T ⫻ BVCEO (GHz-V) 0 0

2

8

6

4 B V CEO (V)

FIGURE 3.10.7 fT vs. BVCEO data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies. Solid lines represent process design contours with constant fTBVCEO product.

200 fmax > fT 150

fmax (GHz)

fmax < fT BC6G

100

BC7 BC7RF 50

BC9 BC7RF-HV BC9-HV

0 0

50

100

150

200

f T(GHz)

FIGURE 3.10.8 fmax vs. fT data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies. © 2006 by Taylor & Francis Group, LLC

3.10-352

The Silicon Heterostructure Handbook

200 BC9 BC6G

150 f T (GHz)

BC7 BC7RF 100

50

0 0.01

0.1

1 JC

10

100

(mA/µm2)

FIGURE 3.10.9 Comparison of fT vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

derived from s-parameter measurements up to 110 GHz. Details on the procedure used to extract fmax from unilateral power gain data may be found in Ref. [17]. The fT vs. BVCEO plot in Figure 3.10.7 shows the classical trade-off between operation speed and breakdown voltage, with fT  BVCEO products close to 180 GHz-V for most devices, except in BiCMOS-9 where this product rises up 270 GHz-V for the high-speed SiGe:C HBT. Figure 3.10.8 shows that fmax/fT ratios larger than unity have been maintained throughout the roadmap, which indicates that process enhancements used to increase fT have not been detrimental to fmax. This holds true for the high-speed HBT in BiCMOS-9, where fT
fmax
160 GHz. This remarkable (and somewhat unexpected) result demonstrates that the combination of the robust double-polysilicon QSA HBT structure with a thin and heavily doped SiGe:C base can provide outstanding frequency performances. The various SiGe technology generations are further compared in Figure 3.10.9 and Figure 3.10.10, which plot the dependencies of fT and fmax on collector current density JC. Here again, a classical trend of increasing current density with peak fT value is observed: from 45 to 160 GHz, approximately eightfold increase in JC at peak fT is obtained. This reflects the delayed onset of Kirk effect at increasing collectordoping concentrations. The benefits of SiGe:C base technology and geometrical scaling for RF and broadband applications are highlighted by the following observations: (i) RF applications. Comparing BiCMOS-7RF and -7 characteristics in Figure 3.10.7 to Figure 3.10.10, one notices a large increase in fmax (from 90 to 120 GHz), despite a 10-GHz decrease in fT linked to a small BVCEO adjust. This results from the drastic reduction of base resistance (pinched base resistance decreases from
6.5 to
1kV/sq) achieved with heavy SiGe:C base doping. As shown in Figure 3.10.11, this translates into excellent HF noise characteristics: NFmin at 2 GHz is lower than 0.4 dB in BiCMOS-7RF, which is twice smaller than in the first RF SiGe process, BiCMOS-6G. Comparing further BiCMOS-6G and -7RF performances in Figure 3.10.10, it is found that fmax has been increased by a factor of
2 for similar current per unit transistor length (i.e., similar JC  WE). This large performance improvement is explained by the combination of the heavily doped SiGe:C base and the reduced emitter width in BiCMOS7RF. As discussed in Ref. [16], the high-voltage SiGe:C HBT also benefits from these features, enabling the integration of power amplifiers with RF functions using this technology. (ii) Broadband applications. Similarly, the introduction of carbon-doped SiGe and the downscaling of emitter widths from 0.25 to 0.17 mm account for the large fmax performance jump (þ60 GHz) between BiCMOS-7 and -9 HBTs (Figure 3.10.10). In this case, the process has

© 2006 by Taylor & Francis Group, LLC

3.10-353

Industry Examples at the State-of-the-Art: ST

1.2

NF min(dB)

1.0

200 BC9 BC6 G

f max (GHz)

150

AE = 6⫻(0.25⫻9.85) µm2 f = 2 GHz VBC = 0 V VBC = −1 V

0.8 0.6 0.4 0.2

BC7

0 0

BC7RF

100

0.005

0.01

0.015

0.02

IC (A) 50

0 0.01

0.1

1

10

100

JC (mA/µm2)

FIGURE 3.10.10 Comparison of fmax vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

FIGURE 3.10.11 Noise figure vs. collector current at 2 GHz for BiCMOS-7RF SiGe:C HBT. (From H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. BiCMOS7RF: a highly manufacturable 0.25 mm BiCMOS RF-applications-dedicated technology using nonselective SiGe:C epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. With permission.)

been designed to provide similar fT enhancement simultaneously. As shown in Figure 3.10.9, the SiGe:C HBT in BiCMOS-9 has about twice the fT of the BiCMOS-7 device at its peak current density of
4 mA/mm2. Alternatively, this approximately twofold higher frequency can be traded for an approximately fivefold reduction in power consumption at the same frequency for applications not requiring the ultimate performance. It should be pointed out that, in addition to these remarkable frequency performances, excellent yield results and process reproducibility have been demonstrated for this technology, as detailed in Ref. [17].

3.10.6 Outlook for the Future In this chapter, the main features of ST 0.35, 0.25, and 0.13 mm SiGe BiCMOS technologies have been reviewed, with emphasis on SiGe HBT structures, profiles, and high frequency characteristics. Further details on these processes, including other available active and passive components, may be found in the literature [8, 15–17]. Circuit applications of these technologies for the mobile communications market are described in Chapter 9.14 of this book. As far as optical communications applications are concerned, available circuit results indicate that the 160 GHz fT/fmax BiCMOS-9 device is able to address the 40 Gb/s market [18, 19]. For more demanding applications, such as 77 GHz automotive radar, higher frequency performances will be required, e.g., >230 GHz fT/fmax. From the past experience in BiCMOS-9 technology optimization, we estimate that the double-polysilicon QSA HBT architecture can be extended over 200 GHz fT, but that aggressive design rules would be needed to reach 230 GHz fmax. Consequently, decision has been made to investigate a FSA HBT structure for 90-nm SiGe BiCMOS generation. As mentioned already, FSA HBT structures using nonselective base epitaxy are not straightforward. They require specific process modules, such as CMP or countermask lithography, which are not easy to implement and to integrate into a BiCMOS flow. For this and other reasons discussed in Refs. [20, 21], the approach used at ST is based on the selective epitaxial base (FSA-SEG) concept, which has the other advantage to be mask-compatible with the QSA-NSEG approach.

© 2006 by Taylor & Francis Group, LLC

3.10-354

FIGURE 3.10.12

The Silicon Heterostructure Handbook

SEM cross section through a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

400

55 K

f max fT, fmax (GHz)

300

fT 300 K

200

100

0 0.1

AE = 0.17⫻3.6 µm2 VC B = 0.5 V 1

10

100

JC (mA/µm2)

FIGURE 3.10.13 High-frequency characteristics at 300 and 55 K of a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

Figure 3.10.12 shows an SEM cross section through a FSA-SEG SiGe:C HBT fabricated using BiCMOS-9 reticles. The main difficulty with the selective epitaxy of SiGe:C is the higher growth temperature compared to nonselective epitaxy, which is detrimental to the carbon incorporation on substitutional sites. However, by proper optimization of the carbon and Ge profiles, this difficulty can be solved, and good process manufacturability and world class device performances (
230 and
350 GHz fT/fmax at room and cryogenic temperatures, respectively) have been demonstrated, such as shown in Figure 3.10.13. It should be pointed out that these performances have been obtained for a device using an arsenic-doped monoemitter and sustaining a high thermal budget, which will facilitate its later integration with 90-nm CMOS.

Acknowledgments The authors are indebted to the many people at ST Microelectronics Crolles involved in the various aspects of this work. In particular, they wish to thank the members of the epitaxy teams of D. Dutartre (C. Fellous, F. Dele´glise, and L. Rubaldo) and D. Bensahel (Y. Campidelli and O. Kermarrec), and of the former CVD group of J.L. Regolini at France Telecom CNET Laboratories, for their contributions to making SiGe BiCMOS technology at ST a success story. The continuous support of B. Sautreuil and M. Roche is also gratefully acknowledged.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: ST

3.10-355

References 1. D. Dutartre, G. Bre´mond, A. Souifi, and T. Benyattou. Excitonic photoluminescence from Si-capped strained Si1–xGex layers. Phys. Rev. B 44:11525–11527, 1991. 2. H. Boussetta, G. Giroult-Matlakowski, B. Le Tron, D. Dutartre, P. Warren, M.J. Bouzid, and A. Chantre. Identification of peripheral base currents in Si or SiGe epitaxial-base single-polysilicon self-aligned bipolar transistors. Proceedings 24th European Solid-State Device Research Conference, Edinburgh, 1994, pp. 63–66. 3. S. Denorme, H. Boussetta, A. Chantre, G. Vincent, and M. Mouis. Demonstration of enhanced base diffusion due to extrinsic base implantations in submicron, polysilicon-emitter, epitaxial base bipolar transistors. Proceedings 25th European Solid-State Device Research Conference, The Hague, 1995, pp. 513–516. 4. B. Le Tron, M.D.R. Hashim, P. Ashburn, M. Mouis, A. Chantre, and G. Vincent. Determination of bandgap narrowing and parasitic energy barriers in SiGe HBTs integrated in a bipolar technology. IEEE Trans. Electron Devices 44:715–722, 1997. 5. E. de Berranger, S. Bodnar, A. Chantre, J. Kirtsch, A. Monroy, M. Laurens, A. Granier, J.L. Regolini, and M. Mouis. Performance improvement in a 200 mm BiCMOS technology by Si/SiGe heterojunction bipolar transistor integration. Proceedings 26th European Solid-State Device Research Conference, Bologna, 1996, pp. 433–436. 6. A. Chantre, M. Marty, J.L. Regolini, M. Mouis, J. de Pontcharra, D. Dutartre, C. Morin, D. Gloria, S. Jouan, R. Pantel, M. Laurens, and A. Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–96. 7. D. Dutartre. Silicon epitaxy: new applications. In Semiconductors and Semimetals, vol. 72. Academic Press, New York, 2001, pp. 397–457. 8. A. Monroy, M. Laurens, M. Marty, D. Dutartre, D. Gloria, J.L. Carbonero, A. Perrotin, M. Roche, and A. Chantre. BiCMOS6G: a high performance 0.35 mm SiGe BiCMOS technology for wireless applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 121–124. 9. H. Baudry, B. Martinet, C. Fellous, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, J. Mourier, G. Troillard, A. Monroy, D. Dutartre, D. Bensahel, G. Vincent, and A. Chantre. High performance 0.25 mm SiGe and SiGe:C HBTs using non selective epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 52–55. 10. S. Jouan, R. Planche, M. Marty, D. Dutartre, J.A. Chroboczek, P. Llinares, H. Baudry, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. In-situ arsenic doped single-crystal emitters for low 1/f noise SiGe HBTs. Proceedings of the 29th European Solid-State Device Research Conference, Leuven, 1999, pp. 336–339. 11. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinare`s, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. A high speed low 1/f noise SiGe HBT technology using epitaxially aligned polysilicon emitters. IEEE Trans. Electron Devices 46:1525–1531, 1999. 12. S. Niel, O. Rozeau, L. Ailloud, C. Hernandez, P. Llinare`s, M. Guillermet, J. Kirtsch, A. Monroy, J. de Pontcharra, G. Auvert, B. Blanchard, M. Mouis, G. Vincent, and A. Chantre. A 54 GHz fmax implanted base 0.35 mm single-polysilicon bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington DC, 1997, pp. 807–810. 13. B. Martinet, F. Romagna, O. Kermarrec, Y. Campidelli, F. Saguin, H. Baudry, M. Marty, D. Dutartre, and A. Chantre. An investigation of the static and dynamic characteristics of high speed SiGe:C HBTs using a poly-SiGe emitter. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2002, pp. 147–150. 14. B. Martinet, H. Baudry, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, T. Schwartzmann, A. Monroy, D. Bensahel, and A. Chantre. 100 GHz SiGe:C HBTs using non selective base

© 2006 by Taylor & Francis Group, LLC

3.10-356

15.

16.

17.

18. 19.

20.

21.

The Silicon Heterostructure Handbook

epitaxy. Proceedings 31st European Solid-State Device Research Conference, Nuremberg, 2001, pp. 97–100. H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. BiCMOS7RF: a highly manufacturable 0.25 mm BiCMOS RF-applications-dedicated technology using nonselective SiGe:C epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. D. Muller, A. Giry, C. Arnaud, C. Arricastres, R. Sommet, B. Szelag, A. Monroy, and D. Pache. LDMOSFET and SiGe:C HBT integrated in a 0.25 mm BiCMOS technology for RF-PA applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 168–171. M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. T.O. Dickson, R. Beerkens, and S.P. Voinigescu. A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic. Proceedings Symposium on VLSI Circuits, Honolulu, 2004, pp. 206–209. S.P.Voinigescu, T.O. Dickson, R. Beerkens, and P. Westergaard. A comparison of Si CMOS, SiGe BiCMOS, and InP HBTs technologies for high-speed and millimeter-wave ICs. Proceedings Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 2004, pp. 111–114. P. Chevalier, C. Fellous, B. Martinet, F. Leverd, F. Saguin, D. Dutartre, and A. Chantre. 180 GHz fT and fmax self-aligned SiGeC HBT using selective epitaxial growth of the base. Proceedings European Solid-State Device Research Conference, Estoril, 2003, pp. 299–302. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, N. Ze´rounian, F. Aniel, and A. Chantre. 230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 225–228.

© 2006 by Taylor & Francis Group, LLC

3.11 Industry Examples at the State-of-the-Art: Texas Instruments Integration of a Complementary-SiGe BiCMOS Process for High-Speed Precision Analog Applications 3.11.1 3.11.2

Introduction........................................................... 3.11-357 Process Integration................................................ 3.11-358 Starting Material . Buried Layers, Collector Epitaxy . Lateral Isolation . Collector Sinkers, CMOS Wells . Base Modules . Emitter Modules . CMOS Module . Capacitors . Resistors

B. El-Kareh, S. Balster, P. Steinmann, and H. Yasuda Texas Instruments

3.11.3

Components and their Characteristics................ 3.11-362 Bipolars . CMOS . Capacitors . Resistors Thermal Resistance

3.11.4 3.11.5

.

Circuit Application................................................ 3.11-366 Summary ................................................................ 3.11-366

3.11.1 Introduction Extensive work has been published on RF SiGe [1–15] and SiGe:C [16–18, 22] npn transistors with impressive cutoff frequencies in the range 40–350 GHz. There are, however, very little data available on SiGe and SiGe:C pnp transistors [19–21]. The design of complementary npn and pnp transistors of high and comparable performance is important to linear analog circuits with symmetrical architectures. In addition, there is a tradeoff between gain (b), transistor breakdown (BVCEO), early voltage (VA), cutoff frequency (fT), and noise that must be met for every application. Finally, there are limitations to the thermal budget that must be considered when integrating SiGe-bipolar, CMOS, and passive components. These considerations were taken into account during the development of a novel, full dielectrically isolated modular complementary-SiGe BiCMOS process that is now in manufacturing for ultrahighspeed precision analog circuits [23]. The availability of SiGe and a controlled emitter interface oxide (IFO) provide added flexibility during the tradeoff. This chapter describes the integration of bipolar, 3.11-357 © 2006 by Taylor & Francis Group, LLC

3.11-358

The Silicon Heterostructure Handbook

CMOS, and passive process modules; their interactions; and integration issues. Active and passive components and their key parameters are then discussed. The chapter concludes with a summary of results obtained on a typical voltage feedback operational amplifier.

3.11.2

Process Integration

This section describes the integration of bipolar, CMOS, and passive process modules and their interactions. Table 3.11.1 summarizes key processing steps. A schematic cross-section of the completed bipolar transistors is shown in Figure 3.11.1 for illustration.

Starting Material The starting material is commercially available silicon on insulator (SOI) wafers with 1.25-mm top silicon and 0.1 to 0.4-mm buried-oxide (BOX) on high-resistivity p-type support wafers. The choice of buried oxide (BOX) thickness is a tradeoff between thermal resistance, maximum applied voltage, parasitic capacitance between collector and support wafer, and cost. For high-voltage applications, the BOX thickness is typically 0.4 mm. It is thinned down to 0.1–0.2 mm wherever applicable to reduce thermal resistance and self-heating, particularly during operation at maximum power. Reducing the BOX thickness, however, increases parasitic capacitance. For a typical p-type support wafer, this increase is particularly significant in pnp structures because of the accumulating applied voltage and workfunction difference between collector and support wafer. Increasing its resistivity to >100 Ohm-cm reduces the impact of thinner BOX on parasitic capacitance and also improves the quality factor of passive components. The latter is especially important in RF applications.

Buried Layers, Collector Epitaxy The n- and p-buried layers (NBL and PBL) are patterned, implanted, and diffused into the top silicon film. The implant and anneal conditions are critical to maintaining low collector resistances while minimizing defect density, surface roughness, and autodoping during epitaxy. An epitaxial film is then deposited. Its minimum thickness is primarily limited by the buried-layer updiffusion, the selectively implanted collector (SIC) and base profiles, and their impact on transistor breakdown. Tighter control of the epitaxial film allows reduction of its nominal thickness, improving fT (mainly the npn fT) while maintaining the minimum transistor breakdown of 5.5 V. For some applica-

TABLE 3.11.1

Key Process Modules

Starting material, SOI wafer Buried layer implants and anneal Collector epitaxy Isolation. Deep- and shallow-trench patterning and fill Collector sinker implants CMOS well implants npn base module pnp base module Precision polysilicon resistor patterning and implant npn emitter module pnp emitter module Patterning of CMOS gate, base, polysilicon resistors, polysilicon capacitor plates Source/drain implant and anneal MIM capacitor module Metal-1 and Metal-2 modules Thin-film resistor module Metal-3 and Metal-4 modules

© 2006 by Taylor & Francis Group, LLC

3.11-359

Industry Examples at the State-of-the-Art: Texas Instruments

17 16

14

5

9

13

3

11

4

2

12

15

5

7

5 4

8

10

3 1

5

6

5 4

Buried oxide PNP

NPN Support wafer

FIGURE 3.11.1 Schematic cross-section of npn and pnp transistors. 1: n-buried layer; 2: p-buried layer; 3: collector epitaxy; 4: deep trench; 5: STI; 6: npn sinker; 7: pnp sinker; 8: npn base; 9: pnp base; 10: npn SIC; 11: pnp SIC; 12: NEMIT POLY; 13: PEMIT POLY; 14: CoSi2; 15: BPSG; 16: contact; 17: first metal (second to fourth metal not shown).

tions, boron is implanted in an intermediate region under the base of the pnp. This allows tailoring the collector profile independently of epitaxial thickness, reducing the collector resistance and improving fT while maintaining low-impact ionization at the collector–base junction.

Lateral Isolation Oxide-filled, deep, and shallow trenches fully encapsulate components. This isolation technique minimizes parasitic capacitances, eliminates latch-up, increases packing density, and allows for separate CMOS body-bias and extensions to high-voltage applications. Deep trenches are first patterned and etched into silicon through a triple oxide–nitride-oxide (ONO) stack of suitable film thickness. After partially filling deep trenches, shallow trenches are patterned, straddling deep trenches, and etched into silicon. A thin oxide liner is grown in both trenches followed by conventional oxide-fill and chemical– mechanical polishing (CMP). The process is optimized to minimize stress [24], and provide a quasiplanar surface for subsequent processing steps.

Collector Sinkers, CMOS Wells Collector sinkers are patterned and implanted to reduce collector resistance. Several factors are considered when defining the sinker dose and energy: the collector resistance, the limited thermal budget, and the sinker surface concentration. The latter is an important factor when constructing a ‘‘highdensity’’ capacitor over an n-type sinker with polysilicon as the second plate and the gate-oxide film as the dielectric. As the surface concentration increases, the oxidation rate increases, reducing the capacitance per unit area. An increase in surface concentration also degrades the dielectric integrity. An advantage of full dielectric isolation over junction isolation is the capability of independently isolating the bottom plate of the polysilicon–oxide–silicon capacitor. After growing 11.5-nm CMOS gate oxide, an intrinsic polysilicon film is deposited that constitutes the first part of the CMOS polysilicon gate. The second part is deposited during the npn base formation.

Base Modules The bipolar base modules begin after the deposition of the CMOS intrinsic gate-polysilicon. The npn base is first patterned by removing the gate-polysilicon and gate oxide from the base region. The SiGe

© 2006 by Taylor & Francis Group, LLC

3.11-360

The Silicon Heterostructure Handbook

npn base is grown epitaxially in the patterned windows and as a polysilicon film over the first intrinsic polysilicon-gate. The film can be in-situ doped or implanted. The base-polysilicon and first gatepolysilicon form the final CMOS gate, capacitor plates, and one of the polysilicon precision resistors. While low in concentration, the presence of Ge in the CMOS gate slightly modifies its bandgap, and hence workfunction [25]. For a specified threshold voltage, a minor re-adjustment in channel profile may become necessary when the npn base Ge concentration is modified. Patterning the pnp base is critical. The npn base polysilicon/epitaxy is first covered with a thin film that will serve as an etch stop in a subsequent step. The pnp base region is patterned through the stack, and a SiGe pnp base epitaxy/polysilicon deposited. Similarly to the npn, the film can be in-situ doped or implanted. A tight control of emitter patterning and film undercut allows the reduction of base dose and energy, and hence of base width, increasing fT without impacting emitter–base leakage. The Ge profile is tailored to maximize VA. The positions of the SiGe/Si transitions strongly impact bipolar parameters. In this process, the pnp early voltage (VA) is dominated by the ratio of Ge concentration at the collector– base junction to that at the emitter–base junction [26, 27]. This limits the flexibility of increasing the Ge concentration at the emitter–base junction to increase gain without seriously impacting VA.

Emitter Modules The key feature of the emitter modules is the npn and pnp interface oxide (IFO) formed at the base surface immediately below the emitter polysilicon. The emitter modules start with a stack of grown/ deposited insulators into which emitter windows are patterned over the base. The thickness and composition of the stack is a tradeoff between patterning control and emitter–base overlap capacitance. The npn emitter openings are first patterned, leaving only a thin oxide film that serves as a screen oxide during the selectively implanted collector (SIC) with the photoresist in place. The SIC profile is tailored to maximize fT while satisfying requirements on impact ionization. A similar process is repeated for pnp emitters and SIC. The most critical step is the emitter surface preparation and interface oxide formation. After removing the thin screen oxide, a controlled IFO is grown over emitters. The interface oxide considerably reduces tunneling of carriers injected from the base into the emitter, resulting in a larger increase in gain and reduction in transistor breakdown voltage. An increase in interface oxide also increases flicker noise. Optimizing the interface oxide thickness offers the flexibility of increasing the gain without degrading the early voltage while minimizing the impact on noise, breakdown, and fT. After depositing a 200-nm polysilicon film over the entire surface, the npn emitters are implanted with arsenic, followed by an anneal step, and the pnp emitters with boron or BF2. The emitter polysilicon is patterned over both transistors.

CMOS Module The CMOS gate-polysilicon, npn base, pnp base, zero-TCR polysilicon resistor, and capacitor plates are patterned simultaneously with focus on controlling the CMOS polysilicon gate-length (LPOLY). A lightly doped drain (LDD) is implanted in NMOS, primarily to ensure adequate channel hot-electron reliability. A nitride film is then deposited, patterned, and directionally etched to form polysilicon-gate sidewall spacers, and also to block silicidation when patterned over selected regions, such as polysilicon resistors. This is followed by conventional masking and implant steps to dope source, drain, gate, and well contacts. The source/drain implants are also introduced into the bipolar base contact regions. Controlling the proximity of base contacts to the corresponding emitters is a critical tradeoff between extrinsic base resistance, VA and transistor breakdown. At close proximity, interactions between dopants can seriously impact the emitter and base profiles in the active region, as also predicted by simulations [28]. The structures are then subjected to a final high-temperature rapid-thermal anneal (RTA). This final anneal is the only high-temperature cycle that the pnp emitter is subjected to.

© 2006 by Taylor & Francis Group, LLC

3.11-361

Industry Examples at the State-of-the-Art: Texas Instruments

Capacitors Precision, MIM A schematic cross-section of the metal–insulator–metal (MIM) capacitor is shown in Figure 3.11.2. The capacitor dielectric is oxide (0.7 fF/mm2) or nitride (2 fF/mm2), depending on application. The dielectric is deposited on silicided polysilicon that acts as the bottom capacitor plate, and then covered by a titanium nitride film that, after patterning, serves as the top capacitor plate. Both plates exhibit metallic behavior. The deposition conditions of oxide dielectric and its interfaces with TiN and CoSi2 are optimized to reduce the trap density within the dielectric and its interfaces, reducing transient shifts in capacitance, an effect that is also known as ‘‘dielectric absorption’’ [29]. Stacked Capacitor A high-density capacitor is formed by stacking the MIM capacitor described in the previous section on a capacitor formed between polysilicon and sinker, whereby the gate oxide acts as the dielectric (Figure 3.11.3). While the voltage coefficient of such a stack is very high compared to that of the MIM capacitor, the capacitance density is increased to near 4.5 fF/mm2 without adding process complexity. Another advantage of the structure is the full isolation of the bottom plate (sinker, well, and buried layer), reducing the parasitic capacitance. When optimizing the sinker profile, it is important to consider the enhanced oxidation rate and oxide integrity as the sinker surface concentration is increased. With this

Capacitor dielectric

TiN, top capacitor plate

Cobalt silicide

Polysilicon

STI

BOX

Support wafer

FIGURE 3.11.2

Illustration of a precision TiN–oxide–polycide capacitor.

Metal

Contact

Gate oxide

Deposited oxide or nitride

TiN (plate 1)

CMOS gate poly (common plate)

STI

STI

N- or P-sinker (plate 2)

DT

DT NBL or PBL Box

Support wafer

FIGURE 3.11.3 Schematic cross-section of the stacked capacitor.

© 2006 by Taylor & Francis Group, LLC

STI

3.11-362

The Silicon Heterostructure Handbook

Oxide

Contacting pad Metal 2 NiCrAl thin flim

VIAI

Metal 1 Silicide

BPSG

Contact

FIGURE 3.11.4

Illustration of thin-film resistor placement. The TFR can also be placed on a planarized surface.

respect, a p-type sinker typically exhibits less enhanced oxidation rate than an n-type sinker, however, at the cost of increased series resistance.

Resistors Three types of precision resistors with sheet resistance ranging from 50 to 320 Ohm/square are available: Polysilicon resistors that are defined during emitter polysilicon patterning, a ‘‘medium-sheet’’ polysilicon resistor tailored to near-zero TCR, and a trimmable thin-film resistor (TFR). Polysilicon Resistors Precision resistors are formed by selectively blocking silicidation of polysilicon. The CMOS polysilicon gate is tailored by selective implantation to 100 Ohm/square and near-zero TCR. The npn and pnp emitter polysilicon films are also utilized to define resistors of near 300 Ohm/square sheet resistance. Silicidation is blocked by patterning the ‘‘sidewall nitride,’’ leaving a patterned nitride film over resistor areas after the directional sidewall etch. Thin-Film Resistor A precision thin-film resistor (TFR) of near 50 Ohm/square is integrated during metallization. The metal modules are standard back-end of the line processes. A laser-trimmable TFR is formed in two masking steps by first depositing an interlevel oxide film, depositing and patterning a thin NiCrAl film, and then patterning contacting pads to the TFR, as shown in Figure 3.11.4.

3.11.3

Components and their Characteristics

The components are optimized for 5 V applications. Their key characteristics are summarized in this section.

Bipolars Bipolar transistors are optimized for 5 V, low base resistance, and high b*VA products while maximizing fT. Key bipolar parameters are given in Table 3.11.2. npn and pnp fT plots are shown in Figure 3.11.5 and Figure 3.11.6. The main contributor to the increase in fT is the reduced base width. Decreasing the IFO thickness considerably suppresses noise, as shown in Figure 3.11.7 where a reduction in flicker noise by approximately one order of magnitude can be seen [30, 31].

© 2006 by Taylor & Francis Group, LLC

3.11-363

Industry Examples at the State-of-the-Art: Texas Instruments TABLE 3.11.2

Nominal npn and pnp Characteristics, AE ¼ 0.4
0.8 mm2 (258C)

Parameter

Unit

npn

pnp

b VA fTmax (VCE ¼ 5 V) fmax (VCE ¼ 3 V) NFmin BVCEO BVCBO BVEBO

V GHz GHz dB V V V

200 95 27 90 0.7 6.0 13 3.5

140 200 27 60 0.9 6.0 13 3.0

30 25

npn 2

f T (GHz)

20

4

3

Vce = 5 V

1

15 10 5 0 100

10,000

1000 JC

(µA/µm2)

FIGURE 3.11.5 npn fT for Vce ¼ 1 to 5 V. AE ¼ 0.4
0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized process.

30 25

pnp 2

f T (GHz)

20

3

4

Vce = 5 V

1

15 10 5 0 100

1000

10,000

Jc (µA/µm2)

FIGURE 3.11.6 process.

pnp fT for Vce ¼ 1 to 5 V. AE ¼ 0.4
0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized

© 2006 by Taylor & Francis Group, LLC

3.11-364

The Silicon Heterostructure Handbook

CMOS Table 3.11.3 summarizes the CMOS parameters. The values are shown for 5 and 3.3 V with reduced channel length. The CMOS performance meets or exceeds stand-alone 5 V CMOS processes, indicating that performance was not significantly sacrificed during integration into a BiCMOS flow.

Capacitors The MIM capacitor is formed between TiN and polysilicon-silicide, both exhibiting metallic characteristics. Key capacitor parameters are given in Table 3.11.4. One important property of precision capacitors is the transient drift caused by traps within the dielectric and at its interfaces. This effect manifests itself as a partial recovery of voltage across the capacitor when the terminals are instantaneously shortened. This drift causes errors in analog applications that are based on charging and discharging capacitors, such as sample-and-hold circuits [29]. Silicon dioxide exhibits lower VCC and dielectric absorption (voltage recovery <50 ppm) than silicon nitride, indicating a lower trap density in SiO2. The stack capacitor is partially formed over an n-sinker surface and hence exhibits higher VCC than the MIM capacitor.

Resistors Three types of precision resistors are available: a thin NiCrAl resistor (TFR), polysilicon resistors that are defined during emitter polysilicon patterning, and a medium-sheet resistor tailored to near-zero TCR. Some properties of the thin-film and polysilicon resistors are given in Table 3.11.5.

TABLE 3.11.3

Nominal CMOS Characteristics (258C)

Parameter

Unit

Drawn L Linear VT IDSAT Max Isub BVDSS Off current

mm V mA/mm mA/mm V pA/mm

TABLE 3.11.4

Capacitor Characteristics (258C)

NMOS, 5 V

NMOS, 3.3 V

PMOS, 5 V

PMOS, 3.3 V

0.6 0.75 520 2.0 12 <1

0.5 0.75 590 0.05 12 <1

0.5 0.80 290 0.08 9 <10

0.45 0.80 300 0.0004 12 <10

Type Dielectric thickness Capacitance per unit area Capacitance to support wafer Linear VCC, 1 MHz Quadratic VCC, 1 MHz Linear TCC Quadratic TCC Dielectric BV at 0.1 nA/mm2 Dielectric absorption, k

TABLE 3.11.5

MIM, SiO2

MIM, Si3N4

Stack SiO2/Si3N4

50 0.70 0.04 4 0.6 10 0.03 >40 <50

30 2.0 0.04 90 50 60 25 >40 1400

30/14 4.5 0.04 3500 500 — — >10 —

Unit nm fF/mm2 fF/mm2 ppm/V ppm/V2 ppm/8C ppm/8C2 V ppm

Resistor Characteristics (258C)

Type Sheet resistance Linear TCC Quadratic TCC

© 2006 by Taylor & Francis Group, LLC

TFR

PPOLY

NPOLY

48 25 0

320 40 0.8

100 100 0.6

Unit Ohm/square ppm/8C ppm/8C2

3.11-365

Industry Examples at the State-of-the-Art: Texas Instruments

10−19

S IB (A2/Hz)

10−20 NPN, ref. 23

10−21

NPN, optimized 10−22 10−23 ~1/f

10−24 10−25 100

FIGURE 3.11.7 reduces noise.

101

103 102 Frequency (Hz)

104

105

Flicker noise comparison of two IFO thicknesses. Decreasing the IFO thickness considerably

Hot spot

Emitter

Deep trench

Top silicon

Buried layer

Box

Heat-flow path

FIGURE 3.11.8 Simplified model to estimate thermal resistance.

Thermal Resistance Figure 3.11.8 is a schematic of the bipolar structure illustrating the major heat dissipation paths. Because the thermal conductance is considerably lower in silicon dioxide than in single-crystal silicon (0.014 W/ cm-K in SiO2 versus 1.47 W/cm-K in Si), the effective thermal resistance is strongly affected by the BOX thickness. The insulator film compositions above the structure limit the heat dissipation upward and toward bond-pads. Lateral heat dissipation is limited by the effective deep trench thickness and sidewall area, and balanced by heat transfer from adjacent structures. A simplified analytical spreading resistance model is developed to approximate the effective thermal resistance for DC conditions. The assumption is made that most of the heat dissipation occurs toward the support wafer of infinite dimensions compared to the size of the structure. The model predicts a reduction in thermal resistance by approximately 50% as the BOX thickness is decreased from 0.4 to 0.145 mm. More accurate 2D thermal simulations are in progress. The impact of reduced BOX thickness on self-heating is experimentally observed by tracing the base– emitter forward voltage as a function of collector reverse voltage for a fixed base current (Figure 3.11.9).

© 2006 by Taylor & Francis Group, LLC

3.11-366

The Silicon Heterostructure Handbook

0.88 0.87

Bulk

0.86

Box: 0.145 µm

V be (V)

0.85 0.84

Box: 0.4 µm

0.83 0.82 0.81 0.80 0.79 0.78 0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Vce (V)

FIGURE 3.11.9 Measurement of Vbe versus Vce at constant collector current showing the impact of BOX thickness on self-heating.

The drop of Vbe with increased power dissipation is a measure of self-heating. An appreciable reduction in self-heating is found when the BOX thickness is reduced from 0.4 to 0.145 mm. Thermal resistance and self-heating are also important considerations for CMOS, passive components, and temperature increase in adjacent structures.

3.11.4

Circuit Application

The process has been used to fabricate a prototype voltage feedback amplifier with characteristics summarized in Table 3.11.6 [32]. A simplified amplifier schematic is shown in Figure 3.11.10. This is a class AB-folded cascode input stage to achieve higher slew rate (lower distortion at higher frequencies) and class AB diamond driver output stage. The improved pnp and npn cutoff frequencies and reduced base resistance and parasitic capacitances increase the frequency of the nondominant poles, allowing a higher small-signal bandwidth (2500 MHz versus 1000 MHz for JI process). The complementary SiGe bipolar technology allows symmetrical architectures with very low distortion. A third-order intermodulation distortion (IMD3) of better than 100 dBc at 60 MHz, 90 dBc at 100 MHz, and 72 dBc at 300 MHz is achieved. These results stem from the complementary SiGe bipolar and the reduction in parasitic capacitances, especially at the high-impedance node of the circuit. Furthermore, the smaller base resistance of the fully dielectrically isolated transistors results in a lower equivalent input noise voltage. Another voltage feedback amplifier implemented on this technology is designed for low noise and included a class AB biased input stage. We p achieved 0.1 dB gain flatness of 500 MHz with an input referred noise of only 1 nV/ Hz in a gain of two. With this process, a unity gain stable general purpose amplifier with 2.6 GHz of bandwidth is achieved for the first time. Such general purpose amplifiers can be used for RF/IF applications with much less power consumption (due to class AB operation) and more flexible external gain setting than currently used class-A RF amplifiers.

3.11.5

Summary

A fully oxide-isolated 5 V complementary-SiGe BiCMOS technology with MIM capacitors and thin-film resistors has been developed for ultrahigh-speed analog applications. The technology provides high

© 2006 by Taylor & Francis Group, LLC

3.11-367

Industry Examples at the State-of-the-Art: Texas Instruments TABLE 3.11.6

Voltage Feedback Amplifier Characteristics

Parameter

Measured

Small-signal bandwidth Gain setting Noise IMD3* at 100 MHz IMD3 at 300MHz

2300 MHz Gain of 5 p 1.9 nV/ Hz 90dBc 72dBc

*IMD3: Third order intermodulation distortion.

VBIAS INP

OUT INN

Class AB Input stage

FIGURE 3.11.10

Folded cascode

Class AB output stage

Voltage feedback amplifier topology.

b*VA and fT*BVCEO npn and pnp transistors with well-matched characteristics. Passive components of very low voltage and temperature coefficients are realized. This process has been used to build an extremely fast voltage feedback amplifier and is now in production for high-speed analog circuits. It is modularly extendable to higher performance or higher voltage applications. By optimizing the npn and pnp emitter interfaces and base profiles in a complementary 5 V SiGe BiCMOS process, a nominal fT of 27 GHz is achieved for both transistors, and the npn noise is reduced by one order of magnitude. In addition, thinning down the SOI BOX thickness reduces the thermal resistance and self-heating, further improving bipolar parameters. Finally, the reduction in dielectric trap density and hence dielectric absorption in precision capacitors extends the applicability of the process.

Acknowledgments We thank the Freising manufacturing, engineering, characterization, and management teams and the Dallas characterization and modeling teams for their relentless support in completing this project.

References 1. JMC Stork, GL Patton, DL Harame, BS Meyerson, SS IYER, E Ganin, and EF Crabbe. SiGe heterojunction bipolar transistors. Symposium on VLSI Technology, Kyoto 1989, pp. 1–4.

© 2006 by Taylor & Francis Group, LLC

3.11-368

The Silicon Heterostructure Handbook

2. TC Chen, E Ganin, H Stork, B Meyerson, JD Cressler, J Warnock, DL Harame, G Patton, GP Li, CT Chuang, and TH Ning. Submicrometer Si and Si–Ge epitaxial-base double-poly self-aligned bipolar transistors. IEEE Trans. Elect. Dev. 38: 941–943, 1991. 3. E Crabbe, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 4. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 79–81. 5. D L Harame, JH Comfort, JD Cressler, EF Crabbe, JYC Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors—Part I: materials, physics and circuits. IEEE Trans. Elect. Dev. 42: 455– 468, 1995. 6. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JYC Sun, G Scilla, J. Warnock, BJ Ginsberg, K Jenkins, KY Toh, DL Harame, and SR Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300. 7. TF Meister, H Schaefer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, M Stolz, S Boguth, and J Boeck. SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 739–742. 8. A Schueppen, U Erben, A Gruhle, H Kibbel, H Schumacher, and U Koening. Enhanced SiGe heterojunction bipolar transistors with 160 GHz–fmax. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 743–746. 9. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Trans. Microwave Theory Tech. 46: 572–589, 1998. 10. M Kondo, K Oda, E Ohue, H Shimamoto, M Tanabe, T Onai, and K Washio. Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems. IEEE Trans. Elect. Dev. 45: 1287–1294, 1998. 11. FS Johnson, J Ai, S Dunn, B El-Kareh, J Erdeljac, S John, K Benaissa, A Bellaour, B Benna, L Hodgson, G Hoffleisch, L Hutter, M Jaumann, R Jumpertz, M mercer, M Nair, J Seitchik, C Shen, M Schiekofer, T Scharnagl, K Schimpf, U Schulz, B Staufer, L Stroth, D Tatman, M Thompson, B Williams, and K Violette. A highly manufacturable 0.25 mm RF technology utilizing a unique SiGe integration. Proceedings of the 1997 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 56–60. 12. J Boeck, H Schaefer, H Knapp, D Zoeschg, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, R Stengl, and TF Meister. Sub 5 ps SiGe bipolar technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 763–766. 13. JS Rieh, B Jaganathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 14. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. Technical Digest of the IEEE GaAs, 2003, pp. 183–186. 15. BA Orner, QZ Liu, B Rainey, A Stricker, P Geis, P gray, M Zierak, M Gordon, D Collins, V Ramachandran, W Hodge, C Willets, A Joseph, J Dunn, JS Rieh, SJ Jeng, E Eld, G Freeman, and D Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fmax) SiGe HBT. Proceedings of the 2003 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 203–206. 16. LD Lanzerotti, A St Amour, CW Liu, and JC Sturm. Si/Si1–x–y/Gex/Cy heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 930–932. 17. HJ Osten, D Knoll, B Heinemann, H Ruecker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the 1999 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 109–116.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Texas Instruments

3.11-369

18. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillak, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 19. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base PNP transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 20. J Warnock, PF Lu, JD Cressler, KA Jenkins, and JYC Sun. 35 GHz/35 PSEC ECL PNP technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 301–304. 21. D Nguyen-Ngoc, DL Harame, JN Burghartz, RC McIntosh, EF Crabbe, JD Warnock, CL Stanis, BS Meyerson, JM Cotte, and JH Comfort. Ion-implanted base SiGe PNP self-aligned SEEW transistors. Proceedings of the 1991 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 75–78. 22. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Grego, U Haak, W Hoeppner, D Knoll, R Kurps, S Marshmeyer, S Orlowski, H Ruecker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 23. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M Waitschull, JW Weijtmans, and C Willis. Proceeding of the BCTM, Toulouse, 2003, pp. 211–214. 24. R Jerome, I Post, K Huffstatter, G Wodek, P Travnicek, and D Williams. The effect of trench processing conditions on complementary analog devices with SOI/trench isolation. Technical Digest of the IEEE Bipolar Circuits and Technology Meeting, 1993, pp. 41–44. 25. T-J King, JR Pfiester, and KC Saraswat. A variable-work-function polycrystalline–Si1–xGex gate material for submicron CMOS technologies. IEEE Electron Dev. Lett., EDL-12: 533, 1991. 26. EJ Prinz and JC Sturm. Analytical Modeling of current-gain — Early voltage products in Si/Si1–x / Gex/Si heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1991, pp. 853–856. 27. JW Slotboom, G Streutker, A Pruijmboom, and D Gravensteijn. Parasitic energy barriers in SiGe HBT’s. IEEE Trans. Elect. Dev. 12: 486–488, 1991. 28. S Denorme, D Mathiot, P Dollfus, and M Mouis. Two-dimensional modeling of the enhanced diffusion in thin base n-p-n bipolar transistors after lateral ion implantation. IEEE Trans. Elect. Dev. 42: 523–527, 1995. 29. C Iorga, Compartmental analysis of dielectric absorption in capacitors. IEEE Trans. Dielectric Electrical Insulation, 7: 187–192, 2000. 30. JD Cressler, E. Zhao, Georgia Institute of Technology, joint project with Texas Instruments. To be published. 31. F Hou, Texas Instruments, Dallas. Private communication. 32. K Hayat-Dawoodi, Texas Instruments, Dallas. Private Communication.

© 2006 by Taylor & Francis Group, LLC

3.12 Industry Examples at the State-of-the-Art: Philips 3.12.1 3.12.2

Introduction........................................................... 3.12-371 Historical Background .......................................... 3.12-371 SiGe Pioneering Phase . QUBiC1 through QUBiC4

3.12.3

SiGe in Manufacturing — QUBiC4G ................. 3.12-373 Process Integration . Electrical Results . HBT Models . Circuit Results

Roy Colclaser and Peter Deixler Philips Semiconductors

3.12.4

Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X .......................................... 3.12-378 Process Integration . Electrical Results

3.12.5

Summary ................................................................ 3.12-384

3.12.1 Introduction Significant increases in the operating frequency range of silicon semiconductor devices over the past decade have made low-cost electronic equipment available to the consumers at spectacular performance levels. The development of techniques to make silicon-based heterojunction bipolar transistors (HBTs) using SiGe and, later, SiGe:C, was responsible for great strides forward in bipolar transistor performance. An important way to use HBTs is to combine them with high-performance CMOS and well-characterized passive components in monolithic integrated circuit processes designated BiCMOS. Philips has manufactured RF BiCMOS products in the QUBiC family since 1989. SiGe HBTs were added to the process in 2002 and SiGe:C HBTs were added in 2004.

3.12.2 Historical Background Philips Electronics is one of the very few manufacturing companies that made the transition from the vacuum tube era to the semiconductor integrated circuits era in the 1960s. Philips Research Laboratories in Eindhoven, the Netherlands, and, more recently, Leuven, Belgium, have made major contributions to the fundamental understanding of semiconductor materials and device physics. Philips Semiconductors manufactures a variety of integrated circuits using bipolar, MOS, and BiCMOS processes. Radio frequency integrated circuits are a major interest at Philips, and SiGe has become an important area for development.

SiGe Pioneering Phase Within Philips, the task of exploring new and exciting fabrication processes and device structures was assigned to Philips Research Laboratories. From 1988 to 2000, process modules were developed using 3.12-371 © 2006 by Taylor & Francis Group, LLC

3.12-372

The Silicon Heterostructure Handbook

low-temperature atmospheric and reduced pressure single-wafer epitaxial reactors for both selective and nonselective (differential) epitaxy of SiGe [1–4]. Selective epitaxy deposits as monocrystalline over exposed areas of single-crystal substrates and does not deposit over dielectric regions. Differential epitaxy is monocrystalline over exposed areas of single-crystal substrates and polycrystalline over dielectrics and polycrystalline regions. A team of device architects and process integration specialists worked with device physics experts to develop early versions of HBTs based on molecular beam epitaxy, and both selective and nonselective epitaxial growth [5–10]. Outstanding performance in SiGe HBTs was presented at IEDM in 1995 [7]. In parallel, the model development group extended the MEXTRAM bipolar model to include the parameters necessary to describe SiGe HBTs [11–13].

QUBiC1 through QUBiC4 During the same time span, project teams within Philips Semiconductors developed the QUBiC family of processes for the manufacture of silicon BiCMOS integrated circuits [14–17]. This process family is bipolar based with buried n-type and buried p-type layers, vertical npn and lateral pnp transistors, a selection of monocrystalline and polycrystalline silicon resistors, a variety of capacitor types (including metal–insulator–metal, [MIM], in QUBiC4), varicaps, inductors, and compatibility with a corresponding standard family of CMOS from the Philips roadmap. Key characteristics of the basic silicon QUBiC family are summarized in Table 3.12.1. The QUBiC4 [17] process evolved from the previous generations. QUBiC1 [14] utilizes fully recessed LOCOS, a single poly bipolar transistor, and three layers of metal. QUBiC2 [15] uses a modified LOCOS, a single poly bipolar transistor, and three layers of metal. The architecture of QUBiC3 [16] is a major change, using conventional LOCOS, separating CMOS and bipolar processing, adding a thick, fourth layer of metal for inductors, and introducing a double poly bipolar transistor with L-shaped oxide or nitride spacers to define the width of the emitter. The base in this device is implanted before the spacers are formed, and the emitter is diffused from polycrystalline silicon that is implanted with arsenic. The major changes for QUBiC4 are associated with isolation. The 0.25 mm CMOS process uses shallowtrench isolation (STI), and this is combined with deep-trench isolation (DTI) to reduce the parasitic capacitances and improve the RF isolation. The npn transistor is modified to use in situ arsenic-doped polycrystalline silicon. A 3 mm thick fifth layer of metal is added to the process to improve the inductors and provide more flexibility for interconnect. The features of this process include a variety of polycrystalline and monocrystalline silicon resistors with sheet resistances ranging from 25 to 2000 ohms/sq., poly–mono capacitors, poly–poly capacitors, and metal–insulator–metal capacitors, lateral pnp bipolar transistors, and varactors using either junctions or MOS capacitors.

TABLE 3.12.1 The QUBiC Family of Silicon BiCMOS Manufacturing Technologies Technology

QUBiC1

QUBiC2

QUBiC3

QUBiC4

Lithography (mm) npn fT (GHz) npn fmax (GHz) Substrate isolation CMOS Leff (mm) Metal layers

1.0 13

0.7 20

Fully recessed LOCOS 0.78 3

Partly recessed LOCOS 0.70 3

0.5 30 60 LOCOS 0.42 4

0.25 37 90 STI/DTI 0.14 5/6

Source : From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE. With permission.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Philips

3.12-373

3.12.3 SiGe in Manufacturing — QUBiC4G The development of QUBiC4 was well under way when it was decided to introduce a silicon–germanium heterojunction bipolar npn transistor (SiGeHBT) with QUBiC4 as a starting platform. A crossfunctional team was assembled from the research laboratories, product groups, and the manufacturing facilities to implement this development. We were able to reuse much of the work that had already been completed for QUBiC4 in the new project, which was designated QUBiC4G [18]. Many of the process modules could be transferred in total from QUBiC4, a few of the modules required small modifications, and some modules had to be developed specifically for the new process. We selected an architecture that enabled the use of the same set of design rules and layouts for essentially all the important devices, which meant that the databases for mask generation for the large arrays of test structures did not have to be altered. We were able to use algorithms to generate the mask layers in QUBiC4G that were different from those used for QUBiC4 without having to redesign the test structures. In fact, we are able to use the same physical masks for many of the layers, allowing us to mix QUBiC4 and QUBiC4G designs on the same multiproject tape-outs. This is a very cost-effective way to evaluate new test structures at the same time as new product designs. All the outstanding passive components that had been developed for QUBiC4 were easily transferred to QUBiC4G. The only major difference in design rules was due to a request from the design community to increase the thickness of the fourth metal layer from 1 to 2 mm so that lowresistivity orthogonal transmission lines could be implemented in the process.

Process Integration After formation of both n- and p-type buried layers beneath the thin collector epitaxial layer, we apply STI and DTI to significantly reduce the parasitic capacitance. We then complete the standard CMOS integration. The windows defining the active bipolar areas are etched, followed by the implanting of the subcollector doping profile. The high breakdown voltage device is obtained by selectively masking some of the collector implants. Extensive process and device simulations were used to guide the collector and base profile optimization and reduce the number of development cycles. The subcollector implants in QUBiC4 are self-aligned to the emitter opening. In QUBiC4G, we chose to do the subcollector implants before deposition of the base SiGe layer due to the possibility of implant damage to the base layer. At this point, in the process, the base layer of the HBT is deposited using reduced-pressure lowtemperature nonselective epitaxial growth in an ASM CVD reactor. The highly doped boron layer is embedded in a stepped germanium profile without intentional grading [10]. The base layer is monocrystalline over the exposed single-crystal silicon and polycrystalline over the regions that were covered with various dielectric materials. In QUBiC4, the boron-doped base region is implanted into the collector epitaxial layer through an opening in the base polycrystalline silicon and is self-aligned to the opening for the formation of the emitter. In QUBiC4G, the boron-doped portion of the base layer extends across the entire extent of the base, allowing for the formation of low resistance contacts to the extrinsic base region. The emitter in QUBiC4G is formed using a different procedure from QUBiC4 as well. A dielectric layer is deposited over the base layer and patterned, using deep-ultraviolet lithography and an advanced overlay feedback system. This layer serves as an etch stop during the reactive ion etching for the emitter opening to prevent etch damage to the base layer. At this point in the process, we form a similar type of double poly structure with L-shaped inside spacers as in QUBiC4 [16, 17]. The technology features in situ arsenic-doped polycrystalline silicon emitters. The mesa-like topography of the HBT structure (Figure 3.12.1) ensures that the silicide of the base poly and the intrinsic SiGe base are laterally at the same level. Combined with tight alignment, this guarantees that the etch-stop layer does not block the shortest current path from the active base via the highly boron-doped SiGe layer to the silicide of the base electrode. This results in a low base-link resistance and, therefore, low noise figure and high fmax.

© 2006 by Taylor & Francis Group, LLC

3.12-374

The Silicon Heterostructure Handbook

FIGURE 3.12.1 The SiGe-HBT combines robust nonselective epitaxial growth with a double-poly structure and deep- and shallow-trench isolation for high performance in a process based on 0.25 mm lithography. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The PMOS source–drain extensions are implanted just before the emitter drive-in anneal. This avoids PMOS degradation during the hydrogen bake cycle before the SiGe layer deposition. The NMOS characteristics are not affected by the limited bipolar thermal cycles due to the SiGe layer deposition and the in situ doped emitter polycrystalline silicon. A tungsten liner is used under each of the first three aluminum–copper layers to enhance the electromigration performance of the interconnect structures. This liner is necessary because of the higher current densities associated with peak fT for the HBT as compared to the npn device in the QUBiC4 process. The top two aluminum–copper metal layers are 2- and 3-mm thick, respectively. These low-resistance interconnect layers facilitate the fabrication of high quality-factor inductors and orthogonal transmission lines. A high-density metal–insulator–metal capacitor is located between the top two metal layers. The back-end structures are planarized using chemical–mechanical polishing and highdensity plasma dielectric layers.

Electrical Results Defining optimum performance parameters for a BiCMOS process is not a straightforward task. The art of device design is an exercise in compromise. A particular parameter may be dominant in one circuit application and superfluous in another. We worked closely with our product design teams to tailor the HBT performance to satisfy the needs for their applications. For instance, there are different requirements for HBTs that are optimized for current mode logic as compared to those optimized for analog RF power amplifiers.

© 2006 by Taylor & Francis Group, LLC

3.12-375

Industry Examples at the State-of-the-Art: Philips

1⫻100

250

1⫻10−2

200

hFE

150

1⫻10−6 100

1⫻10−8

50

1⫻10−10

Aem = 0.3⫻20.1 µm2

1⫻10−12

0 0.4

(a)

0.6 0.8 VBE (V)

1.0

IC,IB (A)

1⫻10−1

1⫻10−4 IC,IB (A)

1⫻101

1⫻10−3 1⫻10−5 Aem = 1000⫻0.3⫻0.9 µm2

1⫻10−7 0.4 (b)

0.6 0.8 VBE (V)

FIGURE 3.12.2 (a) Gummel plot of a standard HBT with Aem ¼ 0.3
20.1 mm2 (symbols are measured data and solid lines are simulated using a Mextram model) and (b) Gummel plot of an array of 1000 standard HBTs with Aem ¼ 0.3
0.9 mm2. Both the individual device and the array have near-ideal slopes for the base and collector currents. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The Gummel plots in Figure 3.12.2 show a comparison of a 0.3
20.1 mm2 standard HBT to a typical multiemitter array with 1000 0.3
0.9 mm2 transistors in parallel. Both the collector currents and base currents are near-ideal down to low base–emitter biases. The output characteristics shown in Figure 3.12.3 exhibit very high Early voltages (>200 V). The standard HBT has a BVCEO of 2.7 V when measured at VBE ¼ 0.65 V, well within the ideal base current regime and before the onset of high injection effects. BVCEO is maintained above the 2.5 V supply voltage set by the digital CMOS logic. The resulting unconditional circuit stability enables circuit design without concerns about breakdown phenomena during power supply transients. The technology also offers HV npn HBTs with a 3.9 V BVCEO for circuit applications where an increased power supply voltage is required. This device type has excellent RF characteristics with fT of 50 GHz and fmax of 110 GHz and complements the standard device with fT of 70 GHz and fmax of 100 GHz. The RF results are shown in Figure 3.12.4 and Figure 3.12.5. The measured RF characteristics have near-ideal slopes and high power gains. The fmax values are derived by extrapolation from the measured slopes, which, due to the low CCS and high Rsub, are observed to be always near 20 dB/decade. The minimum-sized HBT (Aem ¼ 0.25 mm2) draws less than 0.6 mA collector current at peak fT ¼ 70 GHz (as shown in Figure 3.12.4). On this small device, the deep-trench substrate isolation scheme with the low doping level in the substrate reduces the collector–substrate capacitance to less than 2 fF. As seen from Figure 3.12.3, even the deep-trench isolated HBTs biased near peak fT do not show significant self-heating effects. Basing the process integration on the proven QUBiC4 integration scheme allowed us to preserve characteristics of the 0.25 mm CMOS in QUBiC4G. With only minor implant adjustments, all the QUBiC4G CMOS parameters are closely matched to the parent CMOS technology. This ensures full compatibility with the standard CMOS library. The full suite of passive elements was also carried over from QUBiC4 [17]. The MIM capacitor from this process has a 5 fF/mm2 density based on a Ta2O5 dielectric layer. Only one masking step is added for this component. Two polycrystalline silicon capacitors types are also available. Five resistor types are included in the component list. Other features include varactor diodes, a lateral pnp transistor, and RFCMOS. Spiral inductors with quality factors above 20 at 20 GHz can be fabricated in the 3-mm thick top metal layer. Multilayer inductors using the top two metal layers can also be designed.

© 2006 by Taylor & Francis Group, LLC

3.12-376

The Silicon Heterostructure Handbook

60 50

∆IB = 40 nA

IC (µA)

40 30 20 10 IB = 40 nA 0 (a)

0

0.5

1

1.5

2

2.5

VCE (V) 30

IC (µA)

20 ∆IB = ⫻2

10

IB = 25 µA

0 (b)

0

0.5

1

1.5

2

2.5

VCE (V)

FIGURE 3.12.3 Output characteristics for the standard HBT (Aem ¼ 0.3
20.1 mm2) at T ¼ 258C biased at low power (a) and near peak fT (b). BVCEO is 2.7 V and VA exceeds 200 V. The solid lines are from Mextram 504 model simulations. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

Independent high-performance transmission lines can be realized using the two thick top metal layers. This enables the formation of transmission line grids such as those required for the cross-point switch matrix in one of our first products [18, 20].

HBT Models By the time the actual development of the QUBiC4G technology was started, there was already a product group ready to start designing. We provided the initial models for the project by doing a process

© 2006 by Taylor & Francis Group, LLC

3.12-377

Industry Examples at the State-of-the-Art: Philips

80 70

f T [GHz]

60

Std-HBT, BVceo = 2.7 V HV-HBT, BVceo = 3.9 V

50 40 30 20 10 0 0.01

Aem = 0.3⫻20 µm2 VCB = 1 V 0.1

1

10

Jc (mA/µm2)

FIGURE 3.12.4 Transition frequency as a function of collector current density for the standard and high-voltage HBTs (effective emitter width is 0.3 mm). (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

simulation using TSUPREM4 with the USIT applications module and a device simulation using MEDICI with the HBT module [19]. The first set of Mextram [13] models was made available by placing the QUBiC4G intrinsic transistor in a framework based on measurements of the extrinsic parameters of QUBiC4 transistors. These models were sufficient for the designers to get started, and the first models based on measurements of QUBiC4G material were available before the design was taped out for mask making. The first models were used for circuit prototyping, providing valuable input for the HBT development. In Figure 3.12.2 and Figure 3.12.3, the excellent agreement between electrical measurements and the silicon-based scalable Mextram 504 simulations is demonstrated.

Circuit Results 12.5 Gb/sec Asynchronous Cross-Point Switch The first product designed in QUBiC4G is a 20
20 cross-point switch [20] operating at 12.5 Gb/ sec with a peak-to-peak input swing of 100 mV and peak-to-peak output swing of 600 mV. This product has unicast, multicast, and broadcast switching capabilities used for routing data in optical networks. It utilizes the high-speed and low-noise performance of the inherently matched QUBiC4G technology to maintain highly symmetrical rise and fall times and to reduce jitter to less than 2 psec per switching operation. These switches can be cascaded without the need to insert clock–data recovery and retiming logic. The product operates from a 2.5 V supply and consumes less than 4 W. The die area is 36 mm2. LC-VCOs Fully integrated voltage-controlled oscillators based on varactors and spiral inductors have been fabricated in the QUBiC4G process. The measured output spectrum of a 20 GHz LC-VCO [21] is shown in Figure 3.12.6. The center frequency of this circuit is tunable from 19.8 to 22.7 GHz within a 3 V control range. A measured phase noise of 103 dB c/Hz at 2 MHz from the carrier frequency is achieved. A 35.2 to 37.6 GHz LC-VCO [22] has also been demonstrated.

© 2006 by Taylor & Francis Group, LLC

3.12-378

The Silicon Heterostructure Handbook

60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

Std-HBT Aem = 0.3⫻20.1

0 1⫻108

1⫻109

1⫻1010

1⫻1011

f (Hz)

(a)

60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

HV-HBT Aem = 0.3⫻20.1

0 1⫻108 (b)

1⫻109

1⫻1010

1⫻1011

f (Hz)

FIGURE 3.12.5 Measured AC-gains at VCB ¼ 1 V, biased at peak fT, as a function of frequency for (a) the standard HBT and (b) the high-voltage HBT. The fmax values of 100 GHz for the standard device and 110 GHz for the highvoltage device are derived by extrapolation with the measured slope. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

3.12.4 Upgrade to SiGe:C and Monocrystalline Emitters — QUBiC4X The consumer-oriented microwave applications in the 8 to 30 GHz regime require even more RF capabilities than those provided by the QUBiC4G technology. Using the same basic QUBiC4 BiCMOS platform, we are able to substantially improve the RF performance by incorporating a vertically scaled, carbon-enhanced SiGe base, deposited with nonselective epitaxy. We have also replaced the polycrystalline silicon emitter by an epitaxially grown monocrystalline silicon emitter, with significantly lower emitter access resistance. The new process is called QUBiC4X [23]. This technology offers, on the same chip, npns optimized for either ultrahigh speed or high-voltage robustness. Both devices show near-ideal device characteristics combined with excellent RF and low power performance. We also offer a process derivative for power and analog application, featuring dedicated very-high breakdown SiGe:C power transistors.

© 2006 by Taylor & Francis Group, LLC

3.12-379

Industry Examples at the State-of-the-Art: Philips

10: 33: 14 JUL 17, 2002 hp REF −10 . 0 dB m

MKR 19.832233 GHz −19.30 dB m

# AT 0 dB

PEAK LOG 10 dB/

Center 19.832228 GHz

WA SB SC FS CORR

Center 19.832228 GHz #RES BW 30 KHz

#VBW 300 Hz

Span 2. 000 MHz SWP 667 msec

FIGURE 3.12.6 Measured output spectrum of a 20 GHz voltage-controlled oscillator at Vtune ¼ 0.5 V implemented in QUBiC4G. (From H Veenstra and E van der Heijden. A 19–23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE.)

We elected to stay with the same CMOS for this process development because it satisfies the needs of our product portfolio. The CMOS part of the process flow is relatively independent of the bipolar part, so it would be possible to migrate to more advanced CMOS in the future. We have added the capability to make depletion-mode MOS devices and isolated NMOS transistors to this process flow. RF-CMOS models have been added to the library. The on-chip passive components have also been enhanced for QUBiC4X and characterized over the anticipated frequency range. A SiCr thin-film resistor has been added in the back-end part of the flow and there are now seven silicon resistor styles. The titanium silicide has been replaced by cobalt silicide. New models have also been developed for the inductors [24].

Process Integration The QUBiC4X process is based on the established QUBiC4G technology described in the previous section. The significant process changes are associated with the npn HBT. Carbon has been added to the base layer. The carefully tailored carbon profile enables a thinner base with both a significantly higher boron and germanium content, while maintaining ideal base currents. Base resistance is minimized while ensuring sufficient current gain and good high-frequency noise. The extrinsic base is diffused from the boron-doped base polycrystalline silicon into the SiGe film. This procedure preserves HBT doping profile integrity and minimizes the extrinsic collector junction depth. The parasitic collector–base capacitance and the base-access resistance are both low as a result of this approach. The emitter structure, as in QUBiC4G, is based on L-shaped spacers. The upward expanding emitter electrode width [25] minimizes the emitter resistance on the smallest allowed geometries. This enables us to aggressively scale emitter sizes without any degradation in transition frequency. We have moved

© 2006 by Taylor & Francis Group, LLC

3.12-380

The Silicon Heterostructure Handbook

beyond emitters with amorphous silicon and epitaxially aligned polycrystalline silicon to a defect-free epitaxially grown arsenic-doped monocrystalline silicon emitter. This structure is shown in Figure 3.12.7. Optimized silane-based deposition chemistry, pressure, and temperature in the ASM Epsilon CVD reactor enable growth rates approaching the typical throughput of in situ arsenic-doped polycrystalline silicon emitters. By using an optimized clean in combination with a vacuum load lock, hightemperature hydrogen prebakes are not necessary. We use 0.18-mm lithography for the bipolar and CMOS steps that require tight overlay and line width manufacturing control. We decrease the minimum effective emitter stripe width and place dual rows of contacts at the collector and emitter to ensure reliable npn operation near peak transition frequency. The bipolar modules are combined with the CMOS steps in the same manner as QUBiC4G. The gate patterning and cobalt silicide modules from a 0.18 mm CMOS technology have been introduced. This results in a significant enhancement of the RF CMOS performance and tighter process control. The final rapid thermal anneal has been adjusted to a high-temperature spike to mitigate the traditional thermal budget mismatch between SiGe-HBTs and CMOS. We simultaneously achieve good MOS gate–source–drain activation, MOS transistor matching, minimized npn total base-resistance, and shallow or steep emitter diffusion, aided by the limited diffusivity of the arsenic in the monocrystalline silicon emitter.

FIGURE 3.12.7 The QUBiC4X HBT combines a nonselective epitaxial SiGe:C base, an epitaxially grown monocrystalline silicon emitter and a double-polycrystalline silicon structure for minimized parasitics and high performance. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-381

Industry Examples at the State-of-the-Art: Philips

The back-end integration is tailored to the specific needs of mixed-signal and radio frequency designs. It is based on the QUBiC4G technology, with three layers of thin aluminum–copper with tungsten under-liners and two layers of thick aluminum–copper. We have added a silicon–chromium thin-film resistor with low parasitic capacitance and excellent temperature stability.

Electrical Results The diverse portfolio of highly integrated RF and mixed-signal products demands considerable flexibility of BiCMOS technologies over a wide range of frequencies and voltages. We developed a balanced set of high-speed or high-voltage active devices and well-characterized passive components that will enable the designers to explore the considerable potential of SiGe:C BiCMOS technologies for monolithic microwave applications. A Gummel plot and output characteristics of a 0.15
20.1 mm2 standard SiGe:C npn HBT are shown in Figure 3.12.8. Both IC and IB are nearly ideal over several orders of magnitude of current while the Early voltage exceeds 50 V. The standard HBT has a collector–emitter breakdown voltage of 2.0 V, measured at VBE ¼ 0.65 V, which is well within the ideal base-current regime and before

1⫻100

IC,I B (A)

1⫻10−2 1⫻10−4 1⫻10−6 1⫻10−8 Aem = 0.15⫻20.1µm2

1⫻10−10 0.4

0.8

0.6

1.0

VBE (V)

(a)

IC, (mA)

1.0

0.5

∆/B =230nA

0.0 0 (b)

0.5

1 VCE (V)

1.5

2

FIGURE 3.12.8 The Gummel plot (a) and output characteristics (b) of a standard HBTwith Aem ¼ 0.15
20.1 mm2, showing near-ideal device characteristics. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-382

The Silicon Heterostructure Handbook

1

gm/(q.Ic/kT )

0.8

0.6

0.4 2 Monoemitter: RE = 2.5 Ω µm Polyemitter: RE = 20 Ω µm2

0.2

Identical collector architecture and grown SiGe:C base 0 1⫻10−4

1⫻10−3

1⫻10−2

Jc (A/µm2)

FIGURE 3.12.9 The epitaxially grown monocrystalline silicon emitter and optimized HBT doping profiles boost the transconductance to increase drive capability, especially near peak fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/ 140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

the onset of high injection effects. The epitaxially grown monocrystalline silicon emitter has an emitter resistivity of 2.5 ohm mm2. This provides a significant boost in the available transconductance per unit current (as shown in Figure 3.12.9). The transition frequency for the standard HBT is 131 GHz at a relatively low collector current density of 4.4 mA/mm2 (Figure 3.12.10). The maximum frequency of oscillation for this transistor exceeds 140 GHz. The RF minimum noise figure and associated gain are shown in Figure 3.12.11. These properties are useful for low-noise amplifiers operating at high frequencies. The output power specifications for many microwave applications require voltage swings in excess of 5 V, demanding devices with high breakdown voltages. Our technology offers a high-voltage HBT with BVCBO ¼ 13 V. The transition frequency for this device is 60 GHz at 1.1 mA/mm2 with BVCEO exceeding 3.2 V and fmax of 120 GHz. The combination of high-performance standard HBTs and high-voltage HBTs will enable the monolithic integration of high-speed circuitry and powerful antenna driver blocks. To successfully address some new applications [26] it is necessary to develop SiGe:C HBTs with even higher breakdown characteristics. We have demonstrated a customized very-high-breakdown version of QUBiC4X targeted for power amplifiers with 5 V power supplies and BiCMOS protection circuitry. The SiGe:C PA transistors have been optimized for high-temperature stability of transition frequency, minimized emitter–base capacitance for increased transition frequency at low currents and high collector–base breakdown voltages. The fT
BVCEO and fT
BVCBO products are outstanding and exceed 245 and 842 GHz V, respectively. We achieve 88% power-added efficiency with a 20 dB power gain at 1.8 GHz with 3.3 V supply voltage [27]. This combination of high-voltage ruggedness, device speed, and power performance, integrated in BiCMOS, illustrates the potential of silicon-based high-end power amplifiers. The characteristics of the SiGe:C HBT styles available in the QUBiC4X technologies are compared to those in QUBiC4 and QUBiC4G in Table 3.12.2.

© 2006 by Taylor & Francis Group, LLC

3.12-383

Industry Examples at the State-of-the-Art: Philips

160 Vbc = −0.5 V

140

Vbc = 0.0 V Vbc = 0.2 V

120

fT (GHz)

100

80

60

40

20

fT and fmax are derived by extrapolation from 50 GHz Aem = 0.15⫻20.3 µm2

0 0.0001

0.001 Jc (A/µm2)

0.01

2.5

2.5

2.0

2.0

1.5

1.5

1.0

1.0 NFMIN (dB) 0.5

0.5 0.0

Gass (dB)

Fmin (dB)

FIGURE 3.12.10 The transition frequency as a function of collector current density for the QUBiC4X standard HBT. Only VBE ¼ 0.81 V and IC ¼ 4 mA/mm2 are required to reach 130 GHz fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

Aem = 0.15⫻20.3 µm2 0

Gass (dB)

5 10 15 Frequency (GHz)

0.0 20

FIGURE 3.12.11 The NFMIN and associated gain for the QUBiC4X standard HBT is 0.4 dB at 2 GHz and 1.1 dB at 10 GHz. This is a result of the minimized parasitic capacitances and access resistances. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

© 2006 by Taylor & Francis Group, LLC

3.12-384

The Silicon Heterostructure Handbook

TABLE 3.12.2 Electrical Results Obtained for the Standard HBT, the High-Voltage HBT and the Power Amp HBT (at Room Temperature for Aem ¼ 0.15
20.1 mm2) from the QUBiC4X Process Options [23] as Compared to the Standard and High-Voltage Devices from QUBiC4 [17] and QUBiC4G Parameters

QUBiC4 [17]

fT at VCB ¼ 0.5 fmax IC at peak fT hfe BVCEO BVCBO VA Rpinch REAE CCB/AE CCS/PCollector NFMIN at 2 GHz NFMIN at 10 GHz

QUBiC4G [18]

QUBiC4X [23]

Units

Std BT

HV BT

Std HBT

HV HBT

Std HBT

HV HBT

PA HBT

37 90 0.75 150 3.8 16 27 12 22 2.7 1.5

28 70 0.5 140 5.9 18 50 12 22 2.1 1.5

67 90 1.65 300 2.5 10.0 150 4 22 4.0 2.1

50 90 0.83 300 3.6 14.0 220 4 22 3.3 2.1

131 138 4.4 600 2.0 9.0 50 2.8 2.5 7.0 0.22 0.4 1.1

60 120 1.1 600 3.1 13.0 80 2.8 2.5 3.2 0.22

51 115 0.8 160 4.8 16.5 >250 3.2 20 3.0 0.22

GHz GHz mA/mm2 — V V V kohm/sq. ohm mm2 fF/mm2 fF/mm dB dB

Source : From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.

3.12.5

Summary

Philips has a long history in bipolar-based BiCMOS for RF applications. The QUBiC family has evolved through the years with a suite of well-characterized passive components that provide the designers with all they need to make fully integrated products for the consumer market. When a SiGe HBT replaced the silicon bipolar npn in QUBiC4G, a new frequency range was added to the process capabilities. The enhancement of this HBT by the addition of carbon to the HBT in QUBiC4X opens another set of applications to the silicon-based BiCMOS product arena. The remarkable improvements in SiGe:C HBTs make it possible to manufacture products at low cost that previously could only be made using III–V compound semiconductors. Modeling of both active and passive components had to keep pace with these developments in the technology, making it possible to supply the designers with the tools that are needed to make leading edge designs when the technologies are available.

Acknowledgments The authors acknowledge the teamwork within the Philips organization that made it possible for the development of the QUBiC family of process technologies and the incorporation of SiGe and SiGe:C HBTs in production. We thank the teams at Philips Research in Eindhoven and Leuven, Philips Semiconductors Technology Development in Sunnyvale, Albuquerque, Fishkill, San Jose, Nijmegen, Caen and Crolles, and Philips Semiconductors Product Design in Caen, Nijmegen, and San Jose, for all their efforts on these projects.

References 1. WB de Boer and DJ Meyer. Low-temperature chemical vapor deposition of epitaxial Si and SiGe layers at atmospheric pressure. Applied Physics Letters 58:1286–1288, 1991. 2. WB de Boer, D Terpstra, and JGM van Berkum. Selective versus non-selective growth of Si and SiGe. Materials Science and Engineering B 67:46–52, 1999.

© 2006 by Taylor & Francis Group, LLC

Industry Examples at the State-of-the-Art: Philips

3.12-385

3. WB de Boer and D Terpstra. Emissivity effects in low-temperature epitaxial growth of Si and SiGe. Proceedings ECS Spring Meeting, Seattle, 1999, pp. 309–318(99–10). 4. E Aksen, WB de Boer, and D Terpstra. Emissivity effects in differential epitaxial growth (DEG). Proceedings ECS Spring Meeting, Washington, 2001, Abstract No. 558(2001–1). 5. A Pruijmboom, JW Slotboom, DJ Gravesteijn, CW Fredriksz, AA van Gorkum, RA van de Heuvel, JML van Rooij-Mulder, G. Streutker, and GFA van de Walle. Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy. Electron Device Letters 12:357–359, 1991. 6. JW Slotboom, GFA Streutker, and A Pruijmboom. Parasitic energy barriers in SiGe HBTs. Electron Device Letters 12:486–488, 1991. 7. A Pruijmboom, D Terpstra, CE Timmering. WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, and JJEW Hageraats. Selective-epitaxial base technology with 14 ps ECL-gate delay, for low power wide-band communication systems. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 747–750. 8. RJE Hueting, JW Slotboom, A Pruijmboom, WB de Boer, CE Timmering, and NEB Cowern. On the optimization of SiGe-base bipolar transistors. IEEE Transactions on Electron Devices 43:1518–1524, 1996. 9. MS Peter, JW Slotboom, and D Terpstra. Impact ionization and neutral base recombination in SiGe HBTs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2000, pp. 126–129. 10. P Deixler, HGA Huizing, JJTM Donkers, JH Klootwijk, D Hartskeerl, WB de Boer, RJ Havens, R van der Toorn, JCJ Paasschens, WJ Kloosterman, JGM van Berkum, D Terpstra, and JW Slotboom. Explorations for high performance SiGe-heterojunction bipolar transistor integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 30–33. 11. JCJ Paasschens, WJ Kloosterman, and RJ Havens. Modeling two SiGe HBT specific features for circuit simulation. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 38–41. 12. JCJ Paasschens, WJ Kloosterman, RJ Havens, and HC de Graaff. Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. IEEE Journal of Solid-State Circuits 36:1390–1398, 2001. 13. Mextram Models, Level 504. www.semiconductors.philips.com/Philips_Models/bipolar/mextram/ index.html. 14. JL de Jong, R Lane, B van Schravendijk, and G Conner. Single polycrystalline silicon layer advanced super high-speed BiCMOS technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1989, pp. 182–185. 15. B van Schravendijk, JL de Jong, P van Wijnen, and G Conner. QUBiC2: BiCMOS technology for 17 GHz bipolar and 0.5 mm CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 158–161. 16. A Pruijmboom, D Szmyd, R Brock, R Wall, N Morris, K Fong, and F Jovenin. QUBiC3: A 0.5 mm BiCMOS production technology, with fT ¼ 30 GHz, fmax ¼ 60 GHz and high-quality passive components for wireless telecommunication applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 120–123. 17. D Szmyd, R Brock, N Bell, S Harker, G Patrizi, J Fraser, and R Dondero. QUBiC4: a silicon RFBiCMOS technology for wireless communication ICs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 60–63. 18. P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE. 19. Synopsis markets TSUPREM4 and MEDICI. www.synopsis.com.

© 2006 by Taylor & Francis Group, LLC

3.12-386

The Silicon Heterostructure Handbook

20. H Veenstra, P Barre, E van der Heijden, D van Goor, N Lecacheur, B Fahs, G Gloaguen, S Clamagirand, and O Burg. A 20-input 20-output 12.5 Gb/s SiGe cross-point switch with less than 2 ps RMS jitter. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2003, pp. 174–176. 21. H Veenstra and E van der Heijden. A 19–23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE. 22. H Veenstra and E van der Heijden. A 35.2–37.6 GHz LC VCO in a 70/100 GHz fT/fmax SiGe Technology. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2004. 23. P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE. 24. LF Tiemeijer, RJ Havens, R de Kort, Y Bouttement, P Deixler, and M Ryczek. Predictive spiral inductor compact model for frequency and time domain. Technical Digest of the International Electron Devices Meeting, Washington, 2003, pp. 875–878. 25. K Washio, E Ohue, R Hayami, A Kodama, H Shimamoto, M Miura, K Oda, I Suzumara, T Tominari, and T Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Transactions on Electron Devices 50:2417–2424, 2003. 26. K Nellis and P Zampardi. A comparison of bipolar technologies for linear handset power amplifier applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 3–6. 27. DMH Hartskeerl, HGA Huizing, P Deixler, W van Noort, and PHC Magnee. High performance SiGeC HBT integrated into a 0.25 mm BiCMOS technology featuring record 88% power-added efficiency. International Microwave Symposium, Fort Worth, 2004.

© 2006 by Taylor & Francis Group, LLC

4 SiGe HBTs 4.1

Overview: SiGe HBTs J.D. Cressler........................................................................... 4.1-389

4.2

Device Physics J.D. Cressler ...................................................................................... 4.2-391 Introduction . An Intuitive Picture . Current Gain . Output Conductance . Current Gain — Early Voltage Product . Charge Modulation Effects . AC Figures-of-Merit . Base and Emitter Transit Times . Operating Current Density Versus Speed . Summary

4.3

Second-Order Effects J.D. Cressler ........................................................................... 4.3-411 Introduction . Ge Grading Effect . Neutral Base Recombination . Heterojunction Barrier Effects . Summary

4.4

Low-Frequency Noise G. Niu ................................................................................... 4.4-427 Background . Measurement Methods . Physical Origins . SiGe Profile Impact and Modeling . Oscillator and Synthesizer Phase Noise Issues . Summary

4.5

Broadband Noise D.R. Greenberg............................................................................. 4.5-439 Introduction . HBT Noise Mechanisms and Modeling . Noise Performance Overview and Trends . Device Optimization for Low Noise . Circuit Performance . Summary

4.6

Microscopic Noise Simulation G. Niu .................................................................... 4.6-459 Introduction . Noise Source Density and Noise Propagation . Input Voltage and Current Noise Concentrations . A SiGe HBT Example . Summary

4.7

Linearity G. Niu ......................................................................................................... 4.7-475 Introduction . Basic Concepts . Physical Nonlinearities . Volterra Series Linearity Analysis . Summary

4.8

pnp SiGe HBTs J.D. Cressler ..................................................................................... 4.8-489 Introduction . Simulation of pnp SiGe HBTs . Profile Optimization Issues . Stability Constraints in pnp SiGe HBTs . Summary

4.9

Temperature Effects J.D. Cressler ............................................................................. 4.9-497 Introduction . The Impact of Temperature on Bipolar Transistors . Cryogenic Operation of SiGe HBTs . Design Constraints . Optimization of SiGe HBTs for 77 K . Helium Temperature Operation . High-Temperature Operation . Summary

4.1-387 © 2006 by Taylor & Francis Group, LLC

4.1-388

The Silicon Heterostructure Handbook

4.10

Radiation Effects J.D. Cressler .............................................................................. 4.10-511 Introduction . DC Effects . AC Small-Signal and Noise Effects . Origin of Radiation Hardness . Low-Dose-Rate Effects . SiGe HBT Circuit Tolerance . Single-Event Upset . Summary

4.11

Reliability Issues J.D. Cressler............................................................................... 4.11-525 Introduction . Technology-Driven Reliability and Yield Issues . Conventional Device Degradation Mechanisms . ‘‘Mixed-Mode’’ Stress Effects . Breakdown Voltage Constraints and Operating Point Instabilities . Low-Frequency Noise Variations . Summary

4.12

Self-Heating and Thermal Effects J.-S. Rieh ...................................................... 4.12-539 Introduction . Modeling of Self-Heating . Thermal Resistance Measurement and Trends . Thermal Effects and Device Reliability . Summary

4.13

Device-Level Simulation G. Niu .......................................................................... 4.13-553 Introduction . Semiconductor Equations . Physical Model Selection . Application Issues . Probing Internal Device Operation . Summary

4.14

SiGe HBT Performance Limits G. Freeman, A. Stricker, J.-S. Rieh, and D.R. Greenberg ................................................................................ 4.14-571 Performance . Intrinsic and Extrinsic Partitioning . Intrinsic Device Scaling . Extrinsic Device RC Delays . Practical Limitations . Summary

© 2006 by Taylor & Francis Group, LLC

4.1 Overview: SiGe HBTs

John D. Cressler Georgia Institute of Technology

SiGe HBTs are far and away the most mature Si heterostructure devices and not surprisingly the most completely researched and discussed in the technical literature. That is not to say that we completely understand the SiGe HBT, and new effects and nuances of operation are still being uncovered year-byyear as transistor scaling advances and application targets march steadily upward in frequency and sophistication. There is still much to learn. Nevertheless, a large body of literature on SiGe HBT operation does exist, across an amazingly diverse set of topics, ranging from basic transistor physics, to noise, to radiation effects, to simulation. This section’s comprehensive treatment of SiGe HBTs begins with Chapter 4.2, ‘‘Device Physics,’’ by J.D. Cressler of Georgia Tech., and addresses perturbations to that first-order theory in Chapter 4.3, ‘‘Second-Order Effects,’’ by J.D. Cressler of Georgia Tech. Chapters 4.4 to 4.7 address mixed-signal noise and linearity in SiGe HBTs, including: Chapter 4.4, ‘‘Low-Frequency Noise,’’ by G. Niu of Auburn University; Chapter 4.5, ‘‘Broadband Noise,’’ by D. Greenberg of IBM Microelectronics; Chapter 4.6, ‘‘Microscopic Noise Simulation,’’ by G. Niu of Auburn University; and Chapter 4.7, ‘‘Linearity,’’ by G. Niu of Auburn University. The very recent development of complementary (npn þ pnp) SiGe technologies for high-speed analog circuits makes the discussion in Chapter 4.8, ‘‘pnp SiGe HBTs,’’ by J.D. Cressler of Georgia Tech particularly relevant. Chapter 4.9, ‘‘Temperature Effects,’’ by J.D. Cressler of Georgia Tech addresses the impact of bandgap engineering on device behavior across temperature, as well as the inherent advantages enjoyed by SiGe HBTs for cryogenic electronics. The important and very recently emerging application associated with space-borne electronics operating in a hostile radiation-rich environment are addressed in Chapter 4.10, ‘‘Radiation Effects,’’ by J.D. Cressler of Georgia Tech. Reliability issues, of key importance to the deployment of SiGe HBT circuits and systems, are covered in Chapter 4.11, ‘‘Reliability Issues,’’ by J.D. Cressler of Georgia Tech, and the related and important topic of thermal phenomena are treated in Chapter 4.12, ‘‘Self-Heating and Thermal Effects,’’ by J.-S. Rieh of Korea University. Finally, subtleties associated with device-level (one-dimensional through three-dimensional) simulation of SiGe HBTs is presented in Chapter 4.13, ‘‘Device-Level Simulation,’’ by G. Niu of Auburn University, and this section concludes with a look at the ultimate limits of SiGe HBTs in Chapter 4.14, ‘‘Performance Limits,’’ by G. Freeman of IBM Microelectronics. In addition to this substantial collection of material, and the numerous references contained in each chapter, a number of review articles and books detailing the operation and modeling of SiGe HBTs exist, including Refs. [1–13].

4.1-389 © 2006 by Taylor & Francis Group, LLC

4.1-390

The Silicon Heterostructure Handbook

References 1. SS Iyer, GL Patton, JMC Stork, BS Meyerson, and DL Harame. Heterojunction bipolar transistors using Si–Ge alloys. IEEE Transactions on Electron Devices 36:2043–2064, 1989. 2. GL Patton, JMC Stork, JH Comfort, EF Crabbe´, BS Meyerson, DL Harame, and JY-C Sun. SiGe-base heterojunction bipolar transistors: physics and design issues. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 13–16. 3. C Kermarrec, T Tewksbury, G Dawe, R Baines, B Meyerson, D Harame, and M Gilbert. SiGe HBTs reach the microwave and millimeter-wave frontier. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1994, pp. 155–162. 4. JD Cressler. Re-engineering silicon: Si–Ge heterojunction bipolar technology. IEEE Spectrum, 1995, pp. 49–55. 5. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I — Materials, physics, and circuits. IEEE Transactions on Electron Devices 40:455–468, 1995. 6. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II — Process integration and analog applications. IEEE Transactions on Electron Devices 40:469–482, 1995. 7. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Transactions of Microwave Theory and Techniques 46:572–589, 1998. 8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. JS Yuan. SiGe, GaAs, and InP Heterojunction Bipolar Transistors. New York, NY: John Wiley & Sons, 1999. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 12. R Singh, DL Harame, and MM Oprysko. Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 13. P Ashburn. SiGe Heterojunction Bipolar Transistors. New York, NY: John Wiley & Sons, 2004.

© 2006 by Taylor & Francis Group, LLC

4.2 Device Physics

John D. Cressler Georgia Institute of Technology

4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10

Introduction............................................................. 4.2-391 An Intuitive Picture ................................................ 4.2-391 Current Gain............................................................ 4.2-393 Output Conductance .............................................. 4.2-396 Current Gain — Early Voltage Product ................ 4.2-399 Charge Modulation Effects..................................... 4.2-400 AC Figures-of-Merit................................................ 4.2-402 Base and Emitter Transit Times............................. 4.2-402 Operating Current Density Versus Speed ............. 4.2-406 Summary .................................................................. 4.2-408

4.2.1 Introduction The essential differences between the SiGe HBT and the Si BJT are best illustrated by considering a schematic energy band diagram. For simplicity, we consider an ideal, graded-base SiGe HBT with constant doping in the emitter, base, and collector regions. In such a device construction, the Ge content is linearly graded from 0% near the metallurgical emitter–base (EB) junction to some maximum value of Ge content near the metallurgical collector–base (CB) junction, and then rapidly ramped back down to 0% Ge. The resultant overlaid energy band diagrams for both the SiGe HBT and the Si BJT, biased identically in forward-active mode, are shown in Figure 4.2.1. Observe in Figure 4.2.1 that a Geinduced reduction in base bandgap occurs at the EB edge of the quasi-neutral base (DEg,Ge (x ¼ 0)), and at the CB edge of the quasi-neutral base (DEg,Ge (x ¼ Wb)). This grading of the Ge across the neutral base induces a built-in quasi-drift field ((DEg,Ge (x ¼ Wb)
DEg,Ge(x ¼ 0))/Wb) in the neutral base. In this chapter, we examine the impact of Ge on the dc and ac properties of the transistor — the essential devices physics of the SiGe HBT.

4.2.2 An Intuitive Picture To intuitively understand how these band-edge changes affect the dc operation of the SiGe HBT, first consider the operation of the Si BJT. When VBE is applied to forward bias the EB junction, electrons are injected from the electron-rich emitter into the base across the EB potential barrier (refer to Figure 4.2.1). The injected electrons diffuse across the base, and are swept into the electric field of the CB junction, yielding a useful collector current. At the same time, the applied forward bias on the EB junction produces a back-injection of holes from the base into the emitter. If the emitter region is doped heavily with respect to the base, however, the density of back-injected holes will be small compared to the forward-injected electron density, and hence a finite current gain b / n/p results. As can be seen in Figure 4.2.1, the introduction of Ge into the base region has two tangible dc consequences: (1) the potential barrier to injection of electrons from emitter into the base is decreased. Intuitively, this will yield exponentially more electron injection for the same applied VBE, translating into 4.2-391 © 2006 by Taylor & Francis Group, LLC

4.2-392

The Silicon Heterostructure Handbook

∆E g,Ge (x = 0) ∆E g,Ge (x = W b)

e–

EC

p-SiGe base

n+ Si

h+

emitter EV

Ge n–Si p-Si

collector

FIGURE 4.2.1 Energy band diagram for a Si BJT and a graded-base SiGe HBT, both biased in forward active mode at low injection.

higher collector current, and hence higher current gain, provided the base current remains unchanged. Given that band-edge effects generally couple strongly to transistor properties, we naively expect a strong dependence of JC on Ge content. Of practical consequence, the introduction of Ge effectively decouples the base doping from the current gain, thereby providing device designers with much greater flexibility than in Si BJT design. If, for instance, the intended circuit application does not require high current gain (as a rule of thumb, b ¼ 100 is usually sufficient for most circuits), we can effectively trade the higher gain induced by the Ge band offset for a higher base-doping level, leading to lower net base resistance, and hence better dynamic switching and noise characteristics. (2) The presence of a finite Ge content in the CB junction will positively influence the output conductance of the transistor, yielding higher Early voltage. While it is more difficult to physically visualize why this is the case, in essence, the smaller base bandgap near the CB junction effectively weights the base profile (through the integral of intrinsic carrier density across the base), such that the backside depletion of the neutral base with increasing applied VCB (Early effect) is suppressed compared to a comparably doped Si BJT. This translates into a higher Early voltage compared to a Si BJT. To intuitively understand how these band-edge changes affect the ac operation of the SiGe HBT, first consider the dynamic operation of the Si BJT. Electrons injected from the emitter into the base region must diffuse across the base (for constant doping), and are then swept into the electric field of the CB junction, yielding a useful (time-dependent) collector current. The time it takes for the electrons to traverse the base (base transit time) is significant, and typically is the limiting transit time that determines the overall transistor ac performance (e.g., peak fT). At the same time, the applied forward bias on the EB junction dynamically produces a back-injection of holes from the base into the emitter. For fixed collector bias current, this dynamic storage of holes in the emitter (emitter charge storage delay time) is reciprocally related to the ac current gain of the transistor (bac). As can be seen in Figure 4.2.1, the introduction of Ge into the base region has an important ac consequence, since the Ge-gradient-induced drift field across the neutral base is aligned in a direction (from collector to emitter) such that it will accelerate the injected minority electrons across the base. We are thus able to add a large drift field component to the electron transport, effectively speeding up the diffusive transport of the minority carriers and thereby decreasing the base transit time. Even though the band offsets in SiGe HBTs are typically small by III–V technology standards, the Ge grading

© 2006 by Taylor & Francis Group, LLC

4.2-393

Device Physics

over the short distance of the neutral base can translate into large electric fields. For instance, a linearly graded Ge profile with a modest peak Ge content of 10%, graded over a 50-nm neutral base width, yields 75 mV/50 nm ¼ 15 kV/cm electric field, sufficient to accelerate the electrons to near saturation velocity (ns ’ 1  107 cm/sec). Because the base transit time typically limits the frequency response of a Si BJT, we would expect that the frequency response should be significantly improved by introducing this Ge-induced drift field. In addition, we know that the Ge-induced band offset at the EB junction will exponentially enhance the collector current density (and thus b) of a SiGe HBT compared to a comparably constructed Si BJT. Since the emitter charge storage delay time is reciprocally related to b, we would also expect the frequency response to a SiGe HBT to benefit from this added emitter charge storage delay time advantage.

4.2.3 Current Gain To understand the inner workings of the SiGe HBT, we must first formally relate the changes in the collector current density and hence current gain to the physical variables of this problem. It is also instructive to carefully compare the differences between a comparably constructed SiGe HBT and a Si BJT. In the present analysis, the SiGe HBT and Si BJT are taken to be of identical geometry, and it is assumed that the emitter, base, and collector-doping profiles of the two devices are identical, apart from the Ge in the base of the SiGe HBT. For simplicity, a Ge profile that is linearly graded from the EB to the CB junction is assumed (as depicted in Figure 4.2.2). The resultant expressions can be applied to a wide variety of practical SiGe profile designs, ranging from constant (box) Ge profiles, to triangular (linearly graded) Ge profiles, and including the intermediate case of the Ge trapezoid (a combination of box and linearly graded profiles) [2]. Unless otherwise stated, this analysis assumes standard lowinjection conditions, negligible bulk and surface recombination, Boltzmann statistics, and holds for npn SiGe HBTs. The theoretical consequences of the Ge-induced bandgap changes to JC can be derived in closed form

(x) ¼ Nab ¼ constant) by considering the generalized for a constant base-doping profile (pb(x) ¼ Nab Moll–Ross collector current density relation (refer to Appendices A.2 and A.3), which holds for low injection in the presence of both nonuniform base doping and nonuniform base bandgap at fixed VBE and temperature (T ) [3]

Ge

Space charge n+

Wb

0 E

n−

p

B

x C

FIGURE 4.2.2 Schematic base doping and Ge profiles in a linearly graded SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

4.2-394

The Silicon Heterostructure Handbook

q(eqVBE =kT
1) , J C ¼ ð Wb pb (x)dx 2 0 Dnb (x)nib (x)

(4:2:1)

where x ¼ 0 and x ¼ Wb are the neutral base boundary values on the EB and CB sides of the base, respectively. In this case, the base doping is constant, but both nib and Dnb are position-dependent; the former through the Ge-induced band offset, and the latter due to the influence of the (positiondependent) Ge profile on the electron mobility (Dnb ¼ kT/qmnb ¼ f(Ge)). Note that JC depends only on the Ge-induced changes in the base bandgap. In general, the intrinsic carrier density in the SiGe HBT can be written as n2ib (x) ¼ (NC NV )SiGe (x)e
Egb (x)=kT ,

(4:2:2)

where (NCNV)SiGe accounts for the (position-dependent) Ge-induced changes associated with both the conduction and valence band effective density-of-states. In Equation (4.2.2), the SiGe base bandgap can be broken into its various contributions (as depicted in Figure 4.2.3). app is the heavyIn Figure 4.2.3, Egbo is the Si bandgap under low-doping (1.12 eV at 300 K), DEgb doping-induced apparent bandgap narrowing in the base region, DEg,Ge(0) is the Ge-induced band offset at x ¼ 0, and DEg,Ge(Wb) is the Ge-induced band offset at x ¼ Wb. We can thus write Egb(x) as app Egb (x) ¼ Egbo
DEgb þ [DEg;Ge (0)
DEg;Ge (Wb )]

x
DEg;Ge (0): Wb

(4:2:3)

Substitution of Equation (4.2.3) into Equation (4.2.2) gives n2ib (x) ¼ gn2io e

app DEgb =kT [DEg;Ge (Wb )
DEg;Ge (0)]x=(Wb kT) DEg;Ge (0)=kT

e

e

,

(4:2:4)

where we have made use of the fact that for Si, we can define a low-doping intrinsic carrier density for Si as n2io ¼ NC NV e
Ego =kT ,

(4:2:5)

and we have defined an ‘‘effective density-of-states ratio’’ between SiGe and Si according to [4] g¼

(NC NV )SiGe < 1: (NC NV )Si

(4:2:6)

∆E app gb

Egb (x)

Egbo ∆Eg, Ge (0)

∆Eg,Ge (W b)

n+ 0

FIGURE 4.2.3

n−

p Wb

Schematic base bandgap in a linearly graded SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

x

4.2-395

Device Physics

Equation (4.2.4) can be inserted into the generalized Moll–Ross relation (4.2.1) to obtain app

~ nb (eqVBE =kT
1)~ qD gn2io eDEgb =kT eDEg;Ge (0)=kT J C ¼
ð Wb , Nab e
[DEg;Ge (Wb )
DEg;Ge (0)](x=Wb kT ) dx

ð4:2:7)

0

˜ nb and g~ to be position-averaged quantities across the base profile, according to where we have defined D ð Wb ~ nb ¼ ð D Wb 0

dx 2 (x) n 0 ib : dx Dnb (x)n2ib (x)

(4:2:8)

Using standard integration techniques, and defining DEg;Ge (grade) ¼ DEg;Ge (Wb )
DEg;Ge (0),

(4:2:9)

we get app

JC;SiGe ¼

~ nb (eqVBE =kT
1)~ qD gn2io eDEgb =kT eDEg;Ge (0)=kT n o:
Wb kT Nab
DEg;Ge (grade)=kT 1
e DEg;Ge (grade)

(4:2:10)

Finally, by defining a minority electron diffusivity ratio between SiGe and Si as h ~¼

~ nb )SiGe (D , (Dnb )Si

(4:2:11)

we obtain the final expression for JC,SiGe [2, 5] JC;SiGe


 app ~h ~DEg;Ge (grade)=kTeDEg;Ge (0)=kT qDnb qVBE =kT 2 DEgb =kT g ¼
(e
1)nio e : Nab Wb 1
e
DEg;Ge (grade)=kT

(4:2:12)

Within the confines of our assumptions stated above, this can be considered an exact result. As expected from our intuitive discussion of the band diagram, observe that JC in a SiGe HBT depends exponentially on the EB boundary value of the Ge-induced band offset, and is linearly proportional to the Ge-induced bandgap grading factor. Given the nature of an exponential dependence, it is obvious that strong enhancement in JC for fixed VBE can be obtained for small amounts of introduced Ge, and that the ability to engineer the device characteristics to obtain a desired current gain is easily accomplished. Note as well that the thermal energy (kT ) resides in the denominator of the Ge-induced band offsets. This is again expected from a simple consideration of how band-edge effects generally couple to the device transport equations. The inherent temperature dependence in SiGe HBTs will be revisited in detail in Chapter 4.9 [6]. If we consider a comparably constructed SiGe HBT and Si BJT with identical emitter contact technology, and further assume that the Ge profile on the EB side of the neutral base does not extend into the emitter enough to change the base current density, our experimental expectations are that for a comparably constructed SiGe HBT and Si BJT, the JB should be comparable between the two devices, while JC at fixed VBE should be enhanced for the SiGe HBT. Figure 4.2.4 confirms this expectation experimentally. In this case, we note that the ratio of the current gain between an identically constructed SiGe HBT and a Si BJT can be written as

© 2006 by Taylor & Francis Group, LLC

4.2-396

The Silicon Heterostructure Handbook

Collector and base currents (A)

10–2 AE = 0.8 ⫻ 2.5 µm2 RBI = 5−8kΩ/ 10–4

VCB = 0.0 V

SiGe HBT

Si BJT

10–6

IC

IB

4.51⫻ 10–8

10–10 0.4

0.5

0.6 0.7 0.8 Emitter−base voltage (V)

0.9

1.0

FIGURE 4.2.4 Comparison of current–voltage characteristics of a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

bSiGe JC;SiGe ffi , bSi JC;Si

(4:2:13)

and thus we can define a SiGe current gain enhancement factor as 
 g~h ~DEg;Ge (grade)=kTeDEg;Ge (0)=kT bSiGe   J ¼ : bSi VBE 1
e
DEg;Ge (grade)=kT

(4:2:14)

Typical experimental results for J are shown for a comparably constructed SiGe HBT and Si BJT in Figure 4.2.5. Based on the analysis above, we can make several observations regarding the effects of Ge on the collector current and hence current gain of a SiGe HBT: .

.

.

.

The presence of any Ge, in whatever shape, in the base of a bipolar transistor will enhance JC at fixed VBE (hence b) over a comparably constructed Si BJT. The JC enhancement depends exponentially on the EB boundary value of Ge-induced band offset, and linearly on the Ge grading across the base. This observed dependence will play a role in understanding the best approach to profile optimization. In light of that, for two Ge profiles of constant stability, a box Ge profile is better for current gain enhancement than a triangular Ge profile, everything else being equal. The Ge-induced JC enhancement is thermally activated (exponentially dependent on reciprocal temperature), and thus cooling will produce a strong magnification of the enhancement.

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1].

4.2.4 Output Conductance The dynamic output conductance (@IC/@VCE at fixed VBE) of a transistor is a critical design parameter for many analog circuits. Intuitively, from the transistor output characteristics, we would like the output current to be independent of the output voltage, and thus ideally have zero output conductance (infinite output resistance). In practice, of course, this is never the case. As we increase VCB, we deplete the neutral base from the backside, thus moving the neutral base boundary value (x ¼ Wb) inward. Since

© 2006 by Taylor & Francis Group, LLC

4.2-397

Device Physics

Temperature (K) 300

200

130

100

77

100 AE = 0.8⫻2.5 µm2

b (SiGe)/b (Si)

VCB = 0.0 V IC = 30.0 µA data Theoretical 10

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.5 Measured and calculated current gain ratio as a function of reciprocal temperature for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

Wb determines the minority carrier density on the CB side of the neutral base, the slope of the minority electron profile, and hence the collector current, necessarily rises [7]. Thus, for finite base doping, IC must increase as VCB increases, giving a finite output conductance. This mechanism is known as the ‘‘Early effect,’’ and for experimental convenience, we define the Early voltage (VA) as (

( )
1  )
1  @JC  @JC  @Wb VA ¼ JC (0)
VBE ’ JC (0) , @VCB VBE @Wb VBE @VCB

(4:2:15)

where JC(0) ¼ JC (VCB ¼ 0 V). The Early voltage is a simple and convenient measure of the change in output conductance with changing VCB. Simultaneously maintaining high current gain, high frequency response, and high VA is particularly challenging in a Si BJT. For a Si BJT, we can use Equation (4.2.1) together with Equation (4.2.15) to obtain ð Wb VA;Si ¼

pb (x)dx Q (0)
¼ b , @Wb Ccb pb (Wb ) @VCB 0

(4:2:16)

where Qb(0) is the total base charge at VCB ¼ 0 V, Ccb is the collector–base depletion capacitance, and we have assumed that VBE is negligible compared to VCB. Note that Ccb is dependent on both the ionized þ þ

) and the ionized base doping (Nab ). To estimate the sensitivity of VA on Ndc and Nab , collector doping (Ndc we can consider a Si BJT with constant base and collector-doping profiles. In this case, we can write (

VA;Si

 )
1 @Wb  ¼
Wb (0) , @VCB VBE

(4:2:17)

where Wb(0) is the neutral base width at VCB ¼ 0 V. The dependence of Wb on voltage and doping can be obtained from [8]

© 2006 by Taylor & Francis Group, LLC

4.2-398

The Silicon Heterostructure Handbook

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi s 
ffi þ Ndc 2« (fbi þ VCB ) Wb ’ Wm
,
(N
þ N þ ) q Nab ab dc

(4:2:18)

where Wm is the metallurgical base width, and fbi is the CB junction built-in voltage. Using Equation
, increasing (4.2.17) and Equation (4.2.18) we can calculate VA as a function of doping. Cleary, if we fix Nab þ degrades VA, physically because the amount of backside neutral base depletion per unit bias is Ndc þ
, increasing Nab rapidly increases VA, which enhanced for a higher collector doping. If we instead fix Ndc makes intuitive sense given that the base is much more difficult to deplete as the base doping increases, everything else being equal. In real Si BJT designs, a given device generally has a specified collector-toemitter breakdown voltage (BVCEO) determined by the circuit requirements. To first order, this BVCEO sets the collector-doping level. While this may appear to favor achieving a high VA, we must recall that the current gain is reciprocally related to the integrated base charge (refer to Equation (4.2.1)).
to improve VA results in a strong decrease in b. In addition, for a Si BJT, for a fixed Hence, increasing Nab
will degrade the cutoff frequency of the transistor (due to the reduction in the base width, increasing Nab þ to buy back the ac minority electron mobility). We might imagine that we can then increase Ndc performance lost, this in turn degrades VA. This ‘‘catch-22’’ represents a fundamental problem in Si BJT design: it is inherently difficult to simultaneously obtain high VA, high b, and high fT. In practice one must then find some compromise design for VA, b, and fT, and in the process the performance capabilities of a given analog circuit suffer. Intuitively, this Si BJT design constraint occurs because b and VA are both coupled to the base-doping profile. The introduction of Ge into the base region of a Si BJT can favorably alter this constraint by effectively decoupling b and VA from the base-doping profile. To formally obtain VA in a SiGe HBT, we begin by combining Equation (4.2.1) with Equation (4.2.15) to obtain [9] pb (xÞdx 2 D nb (x)nib (x) 0 ¼
ð Wb , @ pb (x)dx @VCB 0 Dnb (x)n2ib (x)


VA;SiGe

ð Wb

(4:2:19)

from which we can write VA;SiGe ¼


 ð
Dnb (Wb )n2ib (Wb ) Wb pb (x)dx @Wb
1 : 2 pb (Wb ) @VCB 0 Dnb (x)nib (x)

(4:2:20)

Comparing Equation (4.2.16) and Equation (4.2.20) we can see that the fundamental difference between 2 VA in a SiGe HBT and a Si BJT arises from the variation of nib as a function of position (the variation of Wb with VCB is, to first order, similar between SiGe and Si devices). Observe that if nib is positionindependent (i.e., for a box Ge profile), then Equation (4.2.20) collapses to Equation (4.2.16) and there is no VA enhancement due to Ge (albeit there will obviously still be a strong b enhancement). On the other hand, if nib is position-dependent (i.e., in a linearly graded Ge profile), VA will depend exponentially on the difference in bandgap between x ¼ Wb and that region in the base where nib is smallest. That is, the base profile is effectively ‘‘weighted’’ by the increasing Ge content on the collector side of the neutral base, making it harder to deplete the neutral base for a given applied VCB, all else being equal, effectively increasing the Early voltage of the transistor. For a linearly graded Ge profile, we can use Equation (4.2.4) and Equation (4.2.20) to obtain the ratio of VA between a comparably constructed SiGe HBT and Si BJT (Q) to be [10]   
DEg;Ge (grade)=kT VA;SiGe  DEg;Ge (grade)=kT 1
e : Q’e VA;Si VBE DEg;Ge (grade)=kT

© 2006 by Taylor & Francis Group, LLC

(4:2:21)

4.2-399

Device Physics

Temperature (K) 300

200

130

100

77

10 AE = 0.8⫻2.5 µm2 Forced–VBE

VA (SiGe)/VA (Si)

7

IC = 30.0 µA data Theoretical

5

3 2

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.6 Measured and calculated Early voltage ratio as a function of reciprocal temperature for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

The important result is that the VA ratio between a SiGe HBT and a Si BJT is an exponential function of Ge-induced bandgap grading across the neutral base. Typical experimental results for Q are shown for a comparably constructed SiGe HBT and Si BJT in Figure 4.2.6.

4.2.5 Current Gain — Early Voltage Product In light of the discussion above regarding the inherent difficulties in obtaining high VA simultaneously with high b, one conventionally defines a figure-of-merit for analog circuit design: the so-called ‘‘bVA’’ product. In a conventional Si BJT, a comparison of Equation (4.2.1) and Equation (4.2.16) shows that bVA is to first-order independent of the base profile, and is thus not favorably impacted by conventional technology scaling, as for instance, the transistor frequency response would be. For a SiGe HBT, however, both b and VA are decoupled from the base profile, and can be independently tuned by changing the Ge profile shape. By combining Equation (4.2.14) and Equation (4.2.21) we find that the ratio of bVA between a comparably constructed SiGe HBT and Si BJT can be written as [9] bVA;SiGe ¼ g~h ~eDEg;Ge (0)=kT eDEg;Ge (grade)=kT : bVA;Si

(4:2:22)

Typical experimental results for the bVA ratio for a comparably constructed SiGe HBT and Si BJT are shown in Figure 4.2.7. Observe that bVA is a thermally activated function of both the Ge-induced band offset at the EB junction and the Ge-induced grading across the neutral base. As can be seen in Figure 4.2.7, bVA in a SiGe HBT is significantly improved over a comparably designed Si BJT, regardless of the Ge profile shape chosen, although the triangular Ge profile remains the profile shape of choice for both VA and bVA optimization. Due to their thermally activated nature, both VA and bVA are strongly enhanced with cooling, yielding enormous values (bVA > 104) at 77 K for a 10% Ge triangular profile [10]. Based on the analysis above, we can make several observations regarding the effects of Ge on both the Early voltage and current gain — Early voltage product in SiGe HBTs:

© 2006 by Taylor & Francis Group, LLC

4.2-400

The Silicon Heterostructure Handbook

Temperature (K) 300

bVA (SiGe)/bVA (Si)

1000

200

130

100

77

AE = 0.8⫻2.5 µm2 IC = 30.0 µA data Theoretical

100

10

1 3.0

5.0

7.0 9.0 1000/T (K–1)

11.0

13.0

FIGURE 4.2.7 Measured and calculated ratio of the current gain–Early voltage product ratio as a function of reciprocal temperature for a comparably doped SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon– Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

.

.

Unlike for JC, only the presence of a larger Ge content at the CB side of the neutral base than at the EB side of the neutral base (i.e., finite Ge grading) will enhance VA at fixed VBE over a comparably constructed Si BJT. This VA enhancement depends exponentially on the Ge grading across the base. This observed dependence will play a role in understanding the best approach to profile optimization, generally favoring strongly graded (triangular) profiles. In light of this, for two Ge profiles of constant stability, a triangular Ge profile is better for Early voltage enhancement than a box Ge profile is, everything else being equal. The Ge-induced VA enhancement is thermally activated (exponentially dependent on reciprocal temperature), and thus cooling will produce a strong magnification of the enhancement. Given that b and VA have the exact opposite dependence on Ge grading and EB Ge offset, the bVA product in a SiGe HBT enjoys an ideal win–win scenario. Putting any Ge into the base region of a device will exponentially enhance this key analog figure-of-merit, a highly favorable scenario given the discussion above of inherent difficulties of achieving high bVA in a Si BJT. A reasonable compromise Ge profile design that balances the dc optimization needs of b, VA, and bVA would be a Ge trapezoid, with a small (e.g., 3% to 4%) Ge content at the EB junction, and a larger (e.g., 10% to 15%) Ge content at the CB junction (i.e., finite Ge grading).

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1].

4.2.6 Charge Modulation Effects At a deep level, transistor action, be it for a bipolar or field-effect transistor, is physically realized by voltage modulation of the charges inside the transistor, that in turn leads to voltage modulation of the output current. The voltage modulation of the charges results in a capacitive current, which increases with frequency. The bandwidth of the transistor is thus ultimately limited by various charge-storage effects in both the intrinsic and extrinsic device structure. Exact analysis of charge-storage effects requires the solution of semiconductor transport equations in the frequency domain. In practice, charge-storage effects are often taken into account by assuming that the charge distributions instantly follow the changes of terminal voltages under dynamic operation (i.e., a ‘‘quasi-static’’ assumption).

© 2006 by Taylor & Francis Group, LLC

4.2-401

Device Physics

The first charge modulation effect in a SiGe HBT is the modulation of space charges associated with the EB and CB junctions. Voltage changes across the EB and CB junctions lead to changes of the space–charge (depletion) layer thicknesses and hence the total space charge. The capacitive behavior is similar to that of a parallel plate capacitor, because the changes in charge occur at the opposing faces of the space charge layer (which is depleted of carriers under reverse bias) to neutral region transition boundaries. The resulting capacitances are referred to as EB and CB ‘‘depletion’’ capacitances. Under high-injection conditions, the modulation of charges inside the space charge layer becomes significant. The resulting capacitance is referred to as the ‘‘transition’’ capacitance, and is important for the EB junction since it is forward biased. Under low-injection conditions, the CB capacitance is similar to that of a reverse biased pn junction, and is a function of the CB biasing voltage. At high injection, however, even in forward-active mode, the CB capacitance is also a function of the collector current, because of charge compensation by mobile carriers as well as base push-out at very high injection levels. The second charge modulation effect is due to injected minority carriers in the neutral base and emitter regions. To maintain charge neutrality, an equal amount of excess majority carriers are induced by the injected minority carriers. Both minority and majority carriers respond to EB voltage changes, effectively producing an EB capacitance. This capacitance is historically referred to as ‘‘diffusion’’ capacitance, because it is associated with minority carrier diffusion in an ideal bipolar transistor with uniform base doping. What is essential in order to achieve transistor action is modulation of the output current by an input voltage. The modulation of charge is just a means of modulating the current, and must be minimized in order to maintain ideal transistor action at high frequencies. For instance, a large EB diffusion capacitance causes a large input current, which increases with frequency, thus decreasing current gain at higher frequencies. At a fundamental level, for a given output current modulation, a decreased amount of charge modulation is desired in order to achieve higher operating frequency. A natural figure-of-merit for the efficiency of transistor action is the ratio of total charge modulation to the output current modulation t ec ¼

@Qn , @IC

(4:2:23)

which has dimensions of time and is thus called ‘‘transit time.’’ Here, Qn refers to the integral electron charge across the whole device, and can be broken down into various components for regional analysis. The partial derivative in Equation (4.2.23) indicates that there is modulation of both charge and current, and is thus necessary. A popular but incorrect definition of transit time leaves out the derivatives in Equation (4.2.23), and instead uses the simple ratio of charge to collector current [1]. The problem with this common formulation can be immediately deduced if we consider the resultant tec of an npn bipolar transistor, where Qn is dominated by the total number of emitter dopants. The use of tec ¼ Qn/IC thus leads to an incorrect transit time definition, since it produces a transit time that is independent of the base profile design, and is clearly non-physical. Equation (4.2.23) can be rewritten using the input voltage as an intermediate variable tec ¼

@Qn =@VBE gm ¼ , @IC =@VBE Ci

(4:2:24)

where Ci is the total input capacitance, and gm is the transconductance. Ci can be divided into two components Cbe ¼ @Qn/@VBE and Cbc ¼ @Qn/@VBC. The transit times related to the neutral base and neutral emitter charge modulation are the base transit time and the emitter transit time, respectively. The base charge modulation required to produce a given amount of output current modulation can be decreased by introducing a drift field via Ge grading, thereby reducing the base transit time and extending transistor functionality to much higher frequencies. This Ge-grading-induced reduction in

© 2006 by Taylor & Francis Group, LLC

4.2-402

The Silicon Heterostructure Handbook

charge modulation is the fundamental reason why SiGe HBTs have better frequency response than Si BJTs. Ge grading is simply a convenient means by which we reduce the charge modulation.

4.2.7 AC Figures-of-Merit For low injection, a key SiGe HBT ac figure-of-merit, the unity-gain cutoff frequency ( fT), can be written generally as fT ¼

 
1 1 1 kT WCB ¼ (Cte þ Ctc ) þ t b þ t e þ þ rc Ctc , 2ptec 2p qIC 2vsat

(4:2:25)

where gm ¼ qIC/kT is the intrinsic transconductance at low injection (gm ¼ @IC/@VBE), Cte and Ctc are the EB and CB depletion capacitances, tb is the base transit time, te is the emitter charge storage delay time, Wcb is the CB space–charge region width, vsat is the saturation velocity, and rc is the dynamic collector resistance. Physically, fT is the common-emitter, unity-gain cutoff frequency (h21 ¼ 1), and is conveniently measured using S-parameter techniques. A formal derivation is given in Ref. [1]. In Equation (4.2.25), tec is the total emitter-to-collector delay time, and sets the ultimate limit of the switching speed of a bipolar transistor. Thus, we see that for fixed bias current, improvements in tb and te due to the presence of SiGe will directly translate into an enhanced fT and fmax of the transistor at fixed bias current. In terms of transistor power gain (i.e., using the transistor to drive a ‘‘load’’), one defines the ‘‘maximum oscillation frequency’’ figure-of-merit ( fmax) by [11]

fmax

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi fT ¼ , 8pCbc rb

(4:2:26)

where rb is the small-signal base resistance, and Cbc is the total collector–base capacitance. A derivation of fmax, together with relevant assumptions and discussion, can be found in Ref. [1]. Physically, fmax is the common-emitter, unity power gain frequency, and can also be measured using S-parameter techniques. Clearly, fmax represents a ‘‘higher-order’’ (and therefore potentially more relevant to actual circuit applications) figure-of-merit than fT, since the power gain depends not only on the intrinsic transistor performance (i.e., the device transit times), but also on the device parasitics associated with the process technology and its structural implementation. A larger fT, a smaller rb, and a smaller Cbc are clearly desired for increasing the maximum power gain and circuit operating frequency. Typical fmax data using the various definitions of power gain (i.e., U, MAG, MSG) for a second-generation SiGe HBT biased near peak fT (120 GHz in this case) are shown in Figure 4.2.8.

4.2.8 Base and Emitter Transit Times To understand the dynamic response of the SiGe HBT, and the role Ge plays in transistor frequency response, we must formally relate the changes in the base transit time and emitter transit time to the physical variables of this problem. It is also instructive to carefully compare the differences between a comparably constructed SiGe HBT and a Si BJT. In the present analysis, the SiGe HBT and the Si BJT are taken to be of identical geometry, and it is assumed that the emitter, base, and collector-doping profiles of the two devices are identical, apart from the Ge in the base of the SiGe HBT. The theoretical consequences of the Ge-induced bandgap changes to the base transit time (tb) can be

(x) ¼ Nab ¼ constant) by derived in closed-form for a constant base-doping profile (pb(x) ¼ Nab considering the generalized Moll–Ross transit time relation, which holds for low injection in the presence of both non-uniform base doping and non-uniform base bandgap at fixed VBE and T [3]

© 2006 by Taylor & Francis Group, LLC

4.2-403

Device Physics

Cutoff frequency (GHz)

60 50 SiGe HBT

40

5.0⫻

1.7⫻

30 20

AE = 0.5⫻2.5 µm2 RBI = 5–8 kΩ/ VCB = 1.0 V

Si BJT 10 0 0.1

0.2

0.3 0.5 1.0 Collector current (mA)

2.0

3.0

FIGURE 4.2.8 Measured comparison of unity gain cutoff frequency fT as a function of bias current for a comparably constructed SiGe HBT and Si BJT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

tb ¼

ð Wb 0

n2ib (x) pb (x)

ð Wb 0

 pb (y)dy dx: Dnb (y)n2ib (y)

(4:2:27)

We can insert Equation (4.2.3) into Equation (4.2.2) to obtain Equation (4.2.4), and substitute Equation (4.2.4) into Equation (4.2.27) to obtain tb;SiGe ¼

ð Wb 0

n2ib (x)
Nab


ð Wb z

 
Nab 1
DEgbapp =kT
DEg;Ge (0)=kT
DEg;Ge (grade)y=Wb kT e e e dy dx: Dnb gn2io

(4:2:28)

Performing the first integration step yields tb;SiGe ¼

ð Wb 0

( ) h i
app n2ib (x)
Nab Wb kT
DEgb =kT
DEg;Ge (0)=kT
DEg;Ge (grade)=kT
DEg;Ge (grade)x=Wb kT e e  e
e dx
~ nb g~n2 DEg;Ge (grade) Nab D io (4:2:29)

where we have accounted for the position dependence in both the mobility and the density-of-states product. Substitution of n2ib from Equation (4.2.4) into Equation (4.2.29) and multiplying through gives ( t b;SiGe ¼

)ð i Wb h Wb kT g~n2io DEg;Ge (grade)x=Wb kT
DEg;Ge (grade)=kT 1
e e dx; ~ nb g~n2io DEg;Ge (grade) 0 D

(4:2:30)

which can be integrated and evaluated to obtain, finally [2,5] t b;SiGe ¼


h i Wb2 kT kT 1
1
e
DEg;Ge (grade)=kT : ~ nb DEg;Ge (grade) DEg;Ge (grade) D

(4:2:31)

As expected, we see that the base transit time in a SiGe HBT depends reciprocally on the amount of Ge-induced bandgap grading across the neutral base (i.e., for fixed base width, the band-edge-induced drift field). It is instructive to compare tb in a SiGe HBTwith that of a comparably designed Si BJT. In the case of a Si BJT (trivially derived from Equation (4.2.27) for constant base doping and bandgap), we know that

© 2006 by Taylor & Francis Group, LLC

4.2-404

The Silicon Heterostructure Handbook

t b;Si ¼

Wb2 , 2Dnb

(4:2:32)

and hence can write
h i t b;SiGe 2 kT kT 1
1
e
DEg;Ge (grade)=kT , ¼ h ~ DEg;Ge (grade) DEg;Ge (grade) t b;Si

(4:2:33)

where we have used the ratio of electron diffusivities between SiGe and Si (Equation (4.2.11)). Within the confines of our assumptions stated above, this can be considered an exact result. Figure 4.2.9 shows the theoretical calcuations based on this equation. As expected from our intuitive discussion of the band diagram, observe that tb and hence fT in a SiGe HBT depend reciprocally on the Ge-induced bandgap grading factor, and hence for finite Ge grading across the neutral base, tb is less than unity, and thus we expect enhancement in fT for a SiGe HBT compared to a comparably constructed Si BJT. Figure 4.2.10 confirms this expectation experimentally. Based on the analysis above, we can make several observations regarding the effects of Ge on the frequency response of a SiGe HBT: .

For fixed bias current, the presence of Ge in the base region of a bipolar transistor affects its frequency response through the base and emitter transit times.

50 MAG MSG Mason′s U (MUG) Potentially Unstable (K<1 )

MAG, MSG and Mason's U (dB)

40

Unconditionally Stable (K>1)

Mason′s U

30 MSG

20

10 −20 dB/decade

−20 dB/decade fitting

MAG

MUG

f max = 113.4 GHz

0 f MAG = 96.2 GHz max

−10 100

101 Frequency (GHz)

102

FIGURE 4.2.9 Measured MAG, MSG, and Mason’s U versus frequency for a second-generation SiGe HBT biased near peak fT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.2-405

Device Physics

% Ge (grade) 10

8

6

4

2

0

103

1.0 0.8

102 0.6 0.4 101

t b(SiGe) / t b(Si)

b(SiGe) / b(Si)

300 K 77 K

0.2 100

0.0 0

1

2 3 % Ge (x = 0)

4

5

FIGURE 4.2.10 Theoretical calculations of base transit time ratio G as a function of Ge profile shape. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

The fT enhancement for a SiGe HBT over a Si BJT depends reciprocally on the Ge grading across the base. This makes sense intuitively given the effects of the grading-induced drift field for the minority carrier transport. This observed dependence on Ge grading will play a role in understanding the best approach to profile optimization for a given application. For two Ge profiles of constant stability, a triangular Ge profile is better for cutoff frequency enhancement than a box Ge profile is, everything else being equal, provided tb is dominant over te in determining fT. While this is clearly the case in most first-generation SiGe HBTs, it is nonetheless conceivable that for a te-dominated transistor, a more box-like Ge profile, which inherently favors b enhancement and hence te improvement, might be a favored profile design for optimal frequency response. A compromise trapezoidal profile, which generally favors both tb and te improvement, is a logical compromise profile design point. Such tradeoffs are obviously technology generation dependent. Given that fT is improved across the entire useful range of IC, the fT versus power dissipation trade-off offers important opportunities for portable applications, where power minimization is often a premium constraint. The Ge-induced fT enhancement depends strongly on temperature, and for tb and te, is functionally positioned in a manner that will produce a magnification of fT enhancement with cooling, in stark contrast to a Si BJT.

Relevant approximations and solutions for other types of Ge profiles are discussed at length in Ref. [1]. As can be seen in Figure 4.2.10, since fT is increased across a large range of useful collector current, we can potentially gain dramatic savings in power dissipation for fixed frequency operation compared to a Si BJT. This power-for-performance tradeoff can in practice be even more important than the sheer increase in frequency response, particularly for portable applications. In this case, if we decided, for instance, to operate the transistor at a fixed frequency of 30 GHz, we could reduce the supply current by a factor of 5. Note as well, that as for the collector current density expression (Equation (4.2.12)), the thermal energy (kT ) plays a key role in Equation (4.2.31), in this case residing in the numerator, and will thus have important favorable implications for SiGe HBT frequency response at cryogenic temperatures, as will be discussed in detail in Chapter 4.9.

© 2006 by Taylor & Francis Group, LLC

4.2-406

The Silicon Heterostructure Handbook

4.2.9 Operating Current Density Versus Speed The fundamental nature of SiGe HBTs requires the use of high operating current density in order to achieve high speed. The operating current density dependence of fT is best illustrated by examining the inverse of fT [1] 1 Cbe þ Cbc ¼ : 2pfT gm

ð4:2:34)

Since Cbe ¼ gm tf þ Cte, Cbc ¼ Ctc, and gm ¼ qIC/kT, Equation (4.2.34) can be rewritten as 1 kT ¼ tf þ Ct , 2pfT qIC

(4:2:35)

where Ct ¼ Cte þ Ctc. Since both Cte and Ctc are proportional to emitter area, Equation (4.2.35) can be rewritten in terms of the biasing current density JC as 1 kT ¼ tf þ Ct , 2pfT qJC

(4:2:36)

where Ct ¼ Ct/AE is the total EB and CB depletion capacitances per unit emitter area, and JC ¼ IC/AE is the collector operating current density. Thus, the cutoff frequency fT is fundamentally determined by the biasing current density JC, independent of the transistor emitter length. For very low JC, the second term is very large, and fT is very low regardless of the forward transit time tf. With increasing JC, the second term decreases, and eventually becomes smaller than tf. At high JC, however, base push-out (Kirk effect, refer to Chapter 4.3) occurs, and tf itself increases with JC, leading to fT roll-off. A typical fT versus JC characteristic is shown in Figure 4.2.11 for a first-generation SiGe HBT. The values of tf and Ct can be easily extracted from a plot of 1/2pfT versus 1/JC (as shown in Figure 4.2.12). Near the peak fT, the 1/2pfT versus 1/JC curve is nearly linear, indicating that Ct is close to constant for this biasing range at high fT. Thus, Ct can be obtained from the slope, while tf can be determined from the y-axis intercept at infinite current (1/JC ¼ 0). To improve fT in a SiGe HBT, the transit time tf must be decreased by using a combination of vertical profile scaling as well as Ge grading across the base. At the same time, the operating current density JC must be increased in proportion in order to make the second term in Equation (4.2.36) negligible compared to the first term (tf ). That is, the high fT potential of small tf transistors can only be realized by using sufficiently high operating current density. This is a fundamental criterion for high-speed SiGe HBT design. The higher the peak fT, the higher the required operating JC. For instance, the minimum required operating current density has increased from 1.0 mA/mm2 for a first-generation SiGe HBT with 50-GHz peak fT to 10 to 15 mA/mm2 for >200-GHz peak fT third-generation SiGe HBTs. Higher current density operation naturally leads to more severe self-heating effects, which must be appropriately dealt with in compact modeling and circuit design. Electromigration and other reliability constraints (refer to Chapter 4.11) associated with very high JC operation have also produced an increasing need for copper metalization schemes. In order to maintain proper transistor action under high JC conditions, the collector doping must be increased in order to delay the onset of high injection effects. This requisite doping increase obviously reduces the breakdown voltage. At a fundamental level, trade-offs between breakdown voltage and speed are thus inevitable for all bipolar transistors (Si, SiGe, or III–V). Since the collector doping in SiGe HBT is typically realized by self-aligned collector implantation (as opposed to during epi growth in III–V), devices with multiple breakdown voltages (and hence multiple fT) can be trivially obtained in the same fabrication sequence, giving circuit designers added flexibility.

© 2006 by Taylor & Francis Group, LLC

4.2-407

Device Physics

60

f T (GHz)

50 40 High injection

30 20

SiGe Control A E = 0.5⫻2.5 µm2

10 0 0.0

1.0 2.0 J C (mA/µm2)

3.0

FIGURE 4.2.11 Typical measured fT
JC characteristics of a first-generation SiGe HBT. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

16 14

SiGe Control AE = 0.5⫻2.5 µm2

1/2pfT (ps)

12 10 8

C⬘t = slope/Vt = 0.01507 pF/µm2

6 4

tf = 2.9383 ps

2 0

5

10 15 20 1/JC (µm2/mA)

25

30

FIGURE 4.2.12 Illustration of Ct and tf extraction in a SiGe HBT.

Another closely related manifestation of Equation (4.2.36) is that the minimum required JC to realize the full potential of a small tf transistor depends on Ct. Both Cte and Ctc thus must be minimized in the device and are usually addressed via a combination of structural design, ground-rule shrink, and doping profile tailoring via selective collector implantation. This reduction of Ctc is also important for increasing the power gain (i.e., fmax). The record fT in SiGe HBT technology stands at present at 350 GHz [12]. From today’s vantage point, a combined 300þ GHz peak fT/fmax appears to be a very realistic performance goal for fully integrated, commercial SiGe BiCMOS processes (see Chapter 4.14). Clearly, breakdown voltages must decrease as the transistor performance improves. For the case depicted in Figure 4.2.13 [13], the 50, 120, and 210 GHz SiGe HBTs have an associated BVCEO of 3.3, 2.0, and 1.7 V, respectively. Achievable fT  BVCEO products in the 350 to 400 GHz V range are realistic goals. The sub-1.5 V breakdown voltages required to reach 300 GHz should not prove to be a serious limitation for many designs, given that BVCEO does not present a hard boundary above which one cannot bias the transistor. Rather, one simply has to live with base current reversal and potential bias instabilities in this (above-BVCEO) bias domain [14]. In addition, on-wafer breakdown voltage tuning will provide an additional level of flexibility for circuit designs needing larger operating headroom.

© 2006 by Taylor & Francis Group, LLC

4.2-408

The Silicon Heterostructure Handbook

Cutoff frequency (GHz)

250 200

0.12 µm (3rd generation) 0.18 µm (2nd) 0.50 µm (1st)

VCB = 1.0 V

150 10⫻ 100 50 0 0.1

1.0 Collector current (mA)

10.0

FIGURE 4.2.13 Measured cutoff frequency data as a function of bias current for three different SiGe HBT technology generations. (From G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. IEEE Trans. Electron Dev. 50:645–655, 2003. With permission.)

4.2.10

Summary

In this chapter, I have detailed ‘‘first-order’’ device physics of SiGe HBTs, both from a dc and an ac perspective. This theoretical framework, while clearly simplistic in its assumptions, is nonetheless very useful in providing insight into the way that real SiGe HBTs operate, and how they are designed in practice in industry. Chapter 4.3 addresses additional subtle, but important, nuances in the operation of SiGe HBTs.

Acknowledgments I am grateful to G. Niu, A. Joseph, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxialbase transistors — Part I: Materials, physics, and circuits. IEEE Trans. Electron Dev. 42:455–468, 1995. 3. H Kroemer. Two integral relations pertaining to electron transport through a bipolar transistor with a nonuniform energy gap in the base region. Solid-State Electron. 28:1101–1103, 1985. 4. EJ Prinz, PM Garone, PV Schwartz, X Xiao, and JC Sturm. The effect of emitter–base spacers and strain-dependent density-of-states in Si/SiGe/Si heterojunction bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1989, pp. 639–642. 5. SS Iyer, GL Patton, JMC Stork, BS Meyerson, and DL Harame. Heterojunction bipolar transistors using Si–Ge alloys. IEEE Trans. Electron Dev. 36:2043–2064, 1989. 6. JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JY-C. Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part I: Transistor dc design considerations. IEEE Trans. Electron Dev. 40:525–541, 1993. 7. JM Early. Effects of space-charge layer widening in junction transistors. Proc. IRE 40:1401–1406, 1952.

© 2006 by Taylor & Francis Group, LLC

Device Physics

4.2-409

8. DJ Roulston. Bipolar Semiconductor Devices. New York, NY: McGraw-Hill, 1990. 9. EJ Prinz and JC Sturm. Current gain–Early voltage products in heterojunction bipolar transistors with nonuniform base bandgaps. IEEE Electron Dev. Lett. 12:661–663, 1991. 10. AJ Joseph, JD Cressler, and DM Richey. Optimization of Early voltage for cooled SiGe HBT precision current sources. J. Phys. IV 6:125–129, 1995. 11. SJ Mason. Power gain in feedback amplifiers. IRE Trans. Circuit Theory CT-1:20–25, 1954. 12. J-S Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–775. 13. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. Transistor design and application considerations for >200 GHz SiGe HBTs. IEEE Trans. Electron Dev. 50:645–655, 2003. 14. M Rickelt, HM Rein, and E Rose. Influence of impact-ionization-induced instabilities on the maximum usable output voltage of silicon bipolar transistors. IEEE Trans. Electron Dev. 48:774–783, 2001.

© 2006 by Taylor & Francis Group, LLC

4.3 Second-Order Effects

John D. Cressler Georgia Institute of Technology

4.3.1 4.3.2 4.3.3 4.3.4 4.3.5

Introduction............................................................... 4.3-411 Ge Grading Effect...................................................... 4.3-411 Neutral Base Recombination.................................... 4.3-415 Heterojunction Barrier Effects ................................. 4.3-421 Summary .................................................................... 4.3-426

4.3.1 Introduction While second-order deviations from the first-order theory presented in Chapter 4.2 will always exist in SiGe HBTs, their specific impact on actual SiGe HBT devices and circuits is both profile-design and application dependent, and thus they must be carefully appreciated and kept at the back of the mind by designers. We first analyze the so-called ‘‘Ge grading effect’’ associated with the position dependence of the Ge content across the neutral base found in SiGe designs. The influence of Ge grading effect on SiGe HBT properties is physically tied to the movement of emitter–base space–charge edge along the graded Ge profile with increasing base–emitter voltage. This Ge grading effect can present potential problems for circuit designs that require precise knowledge and control over the current dependence of both current gain and base–emitter voltage as a function of temperature. We then discuss the impact of neutral base recombination (NBR) on SiGe HBT operation. A finite trap density necessarily exists in the base region of all bipolar transistors, and while the impact is usually assumed to be negligible in Si BJTs, it can become important in SiGe HBTs, particularly when they are operated across a wide temperature range. NBR can strongly affect the output conductance (Early voltage) of SiGe HBTs, and is strongly dependent on the mode of base drive (i.e., whether the device is voltage- or current-driven), and hence the circuit application. Finally, we address high-injection heterojunction barrier effects (HBE) in SiGe HBTs. Barrier effects associated with the collector–base heterojunction under high current density operation are inherent to SiGe HBTs, and if not carefully controlled, can strongly degrade both dc and ac performance at the large current densities which SiGe HBTs are often operated. We conclude each section with a brief discussion of the implications and potential problems imposed by these design constraints on both device and circuit designers (‘‘the bottom line’’).

4.3.2 Ge Grading Effect To ensure the applicability of SiGe HBTs to precision analog circuits, parameter stability over both temperature and bias clearly must be ensured. Given the bandgap-engineered nature of the SiGe HBT, this can become an issue for concern, particularly for devices with non-constant (graded) Ge content across the neutral base. Even a cursory examination of the bias current dependence of the current gain in a graded-base SiGe HBT as a function of temperature, for instance, shows a profound functional difference from that of a Si BJT (Figure 4.3.1). In particular, for a graded-base SiGe HBT, the current gain peaks at low injection, and degrades significantly before the onset of high-injection effects. This 4.3-411 © 2006 by Taylor & Francis Group, LLC

4.3-412

The Silicon Heterostructure Handbook

250

Current gain

8% Ge Trapezoid A E = 0.8⫻2.5 µm2

90 K 111 K

150

140 K 2.75 mA/µm2

100 300 K 50

0 10−6

10−5

10−4 10−3 Collector current (A)

10−2

FIGURE 4.3.1 SiGe HBT current gain as a function of collector current at various temperatures, illustrating the Ge grading effect. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

E Doping concentration and Ge %

77 K 200

B

C

VBE = 0

VBE > 0

∆Eg,Ge(x) ∆Eg,Ge(0) 0 x xBE,met

xBC,met

FIGURE 4.3.2 Schematic diagram of the base profile of a SiGe HBT, illustrating the physical origin of the Ge grading effect.

medium-injection ‘‘collapse’’ of b is clearly enhanced by cooling, and thus can be logically inferred to be the result of a band-edge phenomenon. To understand the physical origin of this bias-dependent behavior in the current gain in SiGe HBTs, consider Figure 4.3.2, which shows a schematic doping and Ge profile in a graded-base SiGe HBT. As derived in Chapter 4.2, the collector current at any bias of a graded-base SiGe HBT is exponentially dependent upon the amount of Ge at the edge of the emitter–base (EB) space–charge region. Physically, as the collector current density increases, the base–emitter voltage must also increase, and hence from charge balance considerations the EB space–charge width necessarily contracts, thereby reducing the EB boundary value of the amount of Ge (DEg,Ge(0)), and producing a bias and temperature dependence different from that of a Si BJT [2]. Since this Ge grading effect is the physical result of the modulation of the base width with increasing base–emitter voltage (Wb(VBE)), it can be logically associated with the socalled inverse Early effect. The dependence of the collector current density on the Ge profile shape in a SiGe HBT is given approximately by JC;SiGe ’


 app DEg;Ge (grade) DEg;Ge (0)=kT qDnb qVBE =kT 2 DEgb =kT ~ : e (e
1)n e g h ~ io
W Nab kT b

(4:3:1)

The relationship between JC and Ge profile shape in Equation (4.3.1) highlights the dependence of the collector current density on Ge profile design. Since DEg,Ge(0) changes with increasing base–emitter bias, any changes in the amount of Ge seen by the device at that EB boundary will have a large impact due to the exponential relationship. Consequently, the more strongly graded the Ge profile, the more serious Ge grading effect can be expected to be. Given that Ge grading effect in SiGe HBTs impacts the bias-current dependence of the current gain, a logical test-case circuit for examining the circuit-level influence of Ge grading effect is the ubiquitous bandgap reference (BGR) circuit, since its functionality relies heavily on the identical dependence of VBE(IC) on temperature between transistors of differing size. Given two transistors with a (realistic) nonconstant base doping, and biased at the same collector current, two SiGe HBTs with a sufficiently strongly graded Ge profile might be expected to ‘‘feel’’ the Ge ramp effect differently, since the voltageinduced space–charge width changes would differ slightly between the two. The conceivable result would

© 2006 by Taylor & Francis Group, LLC

4.3-413

Second-Order Effects

0.95 Base−emitter voltage (V)

AE = 0.5⫻2.5 µm2 VCB = 1.0 V

0.90

IC = 100 µA 0.85

0.80 Si (EG = 1.1035) 0.75

15% Ge triangle (EG = 1.0927)

200

240

280 320 Temperature (K)

360

FIGURE 4.3.3 Base–emitter voltage as a function of temperature at fixed bias current for a Si BJT and a SiGe HBT. The lines represent a SPICE fit to the data using the EG fitting parameter. (From SL Salmon, JD Cressler, RC Jaeger, and DL Harame. IEEE Trans. Electron Dev. 47:292–298, 2000. With permission.)

be a slight mismatch in VBE over temperature between the two transistors, thereby degrading the output voltage stability of the BGR circuit over temperature [3]. In the context of SiGe HBT-based BGR implementations, it is key that detailed knowledge of the impact of Ge profile shape on the temperature dependence of the base–emitter voltage exists. Clearly, VBE in turn depends on the variation of IC across the desired temperature range of interest (e.g.,
558C (218 K) to 858C (358 K)). As can be observed in Figure 4.3.3, the differences in VBE(T) between a Si BJT and a SiGe HBT are small, but clearly observable, and must be more carefully examined. The Ge grading effect in SiGe HBTs is primarily determined by the ‘‘steepness’’ of the Ge profile through the EB space–charge region, and the magnitude and shape of N
ab (x) at the space–charge to quasineutral base boundary. We can roughly estimate the variation on the SiGe-to-Si current gain ratio (J ¼ bSiGe/bSi) with VBE for varying amounts of Ge grading by considering a linearly graded SiGe HBT with uniform doping levels in the emitter and base regions. From Chapter 4.2, we have 
 g~h ~DEg;Ge (grade)=kT eDEg;Ge (0)=kT bSiGe  ,  J ¼ bSi VBE 1
e
DEg;Ge (grade)=kT

(4:3:2)

from which we can obtain @J ¼ @VBE

(


J fbi;BE
VBE

)


xpE 2Wb0



 DEg;Ge (grade)=kT , 1
e
DEg;Ge (grade)=kT

(4:3:3)

where fbi,BE is the built-in potential of the EB junction, xpE is the EB space–charge width on the base side of the junction, and Wb0 is the neutral base width at zero-bias. As DEg,Ge(grade) gets small (i.e., approaching a Ge box profile), the Ge grading effect becomes negligible, yielding a flat b versus IC characteristic, as in a Si BJT. Equation (4.3.3) also predicts a weaker Ge grading effect in transistors with higher base doping, since xpE becomes negligible with respect to Wb0. However, in practical SiGe HBT base profiles, which typically have a retrograded base doping level in the vicinity of the EB junction to reduce the EB electric field, the Ge grading effect is enhanced, since xpE varies nonlinearly with VBE. Finally, we note that due to the band-edge nature of Ge grading effect, its impact on device performance should be greatly magnified at reduced temperatures.

© 2006 by Taylor & Francis Group, LLC

4.3-414

The Silicon Heterostructure Handbook

To determine the impact of the Ge grading effect on practical BGR circuits, we must recast the SiGe HBT collector current density into the familiar BGR design equation. First, the process-dependent parameters (B) and the Ge profile dependent terms (j) can be lumped together in IC as app

IC (T ) ¼ jBT m e
Eg0 =kT eEgb

=kT qVBE =kT

e

,

(4:3:4)

and rewritten in terms of the base–emitter voltage as VBE ¼


 app Eg0 Egb kT IC : ln
þ q q q jBT m

(4:3:5)

In practice, we can measure the base–emitter voltage at a reference temperature and collector current and solve for the lumped process parameters (B). Inserting the lumped parameters back into the original VBE equation and simplifying yields the desired SiGe HBT result [3] VBE;SiGe ¼

o o T 1n T n app app
DEg;Ge (0)
Eg0
Egb
DEg;Ge (0) þ VBE;R Eg0
Egb q qTR TR
 kT IC kT T ln ln : þ
m q q TR IC;R

(4:3:6)

The effects of Ge on the base–emitter voltage of the transistor can be gleaned directly from this more generalized result. Observe that the effective bandgap at the emitter–base junction is simply the Si result in the presence of doping-induced bandgap narrowing (Eg0
Eapp gb ), minus the bandgap reduction due to the amount of Ge at the EB junction (DEg,Ge(0)). In addition, the shape of VBE versus temperature in a SiGe HBT is changed from that of a Si BJT due to the addition of Ge, as is apparent in the last two terms of the equation. The ratio T/TR enhances this difference between Si BJTs and SiGe HBTs. For temperatures near the reference temperature, the last two terms of Equation (4.3.6) have little effect on VBE(IC,T), but as the temperature decreases, these effects can become more pronounced. Note that the effective bandgap parameters (Eg0
Eapp gb
DEg,Ge(0)) and m correspond to the SPICE modeling parameters EG and XTI, respectively. The amount of curvature in VBE versus temperature is affected by the addition of Ge, as is apparent in the last two terms of Equation (4.3.6). Assuming that the Ge grading (DEg,Ge(grade)) does not change significantly with temperature, the deviation from linearity of VBE versus temperature (i.e., VBE curvature) using Equation (4.3.6) is actually reduced with increasing Ge grading across the base. In the curvature results presented, the deviation from linearity is calculated by drawing a line through the endpoints of VBE across the relevant temperature range, and then subtracting the actual VBE value from the value on the line at each temperature, according to   VBE (TL )
VBE (TH ) (TL
T ) , Dlinearity ðT Þ ¼ VBE (T )
VBE (TL )
TL
TH

(4:3:7)

where in this case TL ¼ 218 K (
558C) and TH ¼ 358 K (858C). While this Ge-grading-induced VBE curvature reduction might naively appear to be a good thing for BGR design, it in fact can worsen the performance of BGR circuits. Figure 4.3.4 shows the theoretical deviation from linearity that results from three different hypothetical Ge profiles: (1) no Ge grading; (2) 8.6% Ge grading; and (3) 18.6% Ge grading. Note that a box-shaped Ge profile (no Ge grading), in which the Ge concentration across the base is finite but constant, will have the same deviation from linearity as a Si BJT. Given sufficient Ge grading, it is clear that differences between Si BJTs and SiGe HBTs should be experimentally observable, and a combination of measurement and modeling results confirm this [1].

© 2006 by Taylor & Francis Group, LLC

4.3-415

Second-Order Effects

0.004 I C = 100 µA

Theoretical

TR = 300 K

∆ from linearity (V)

0.003

0.002

0.001

∆ Eg,Ge(grade) = 0 meV ∆ Eg,Ge(grade) = 65 meV

0.000 200

∆ Eg,Ge(grade) = 140 meV 240

280 320 Temperature (K)

360

FIGURE 4.3.4 Theoretical dependence of the peak VBE deviation from linearity as a function of temperature for various amounts of Ge grading. (From SL Salmon, JD Cressler, RC Jaeger, and DL Harame. IEEE Trans. Electron Dev. 47:292–298, 2000. With permission.)

When discussing any second-order effect in transistors, it is important to clearly understand both its physical origins and its potential implications for both device and circuit designers, so that it can be effectively ‘‘designed around.’’ We can summarize these implications for Ge grading effect as follows: .

.

.

.

.

.

Ge grading effect is likely to be important only in precision analog circuits, not in digital or RF/ microwave circuits. While the BGR circuit is a natural candidate for observing Ge grading effect, any analog circuit that depends strongly on current gain across a wide bias range, or that requires the matching of VBE between multiple devices across both bias and temperature, could be potentially affected. While the Ge grading effect exists only in compositionally graded Ge profiles, these graded profile designs typically achieve the best dc and ac performance, and thus represent the vast majority of commercially relevant SiGe technologies. As such, Ge grading effect should never be discounted. The impact of the Ge grading effect is expected to be highly dependent on the specifics of the Ge profile shape, and thus will vary from technology to technology. BGRs implemented in the firstgeneration SiGe HBT technology containing only modest amounts of Ge generally show little impact of Ge grading effect [4]. Since the seriousness of the Ge grading effect depends on the Ge grading, it is a phenomenon that will generally worsen with technology scaling, since for constant strained layer stability, the peak Ge content in a SiGe HBT (and hence the grading across the neutral base) will naturally rise. This scaling-induced enhancement, however, will be at least partially offset by the natural increase in base doping with scaling. Conventional modeling methodologies employed in Gummel–Poon (SPICE) compact transistor models appear to adequately capture the Ge grading effect. Due to its thermally activated nature, cooling clearly exaggerates Ge grading effect, and thus is potentially important for precision analog circuits required to operate across a very wide temperature range.

4.3.3 Neutral Base Recombination Physically, NBR in bipolar transistors involves the recombination of injected electrons transiting the neutral base with holes, via intermediate trap levels. Physically, NBR removes the desired injected

© 2006 by Taylor & Francis Group, LLC

4.3-416

The Silicon Heterostructure Handbook

electrons from the collector current via recombination (i.e., they do not exit the base), and increases the undesired hole density (required to support the recombination process), thereby degrading the base transport factor. Significant NBR thus leads to an increase in the base current and a simultaneous decrease in the collector current, thereby causing a substantial degradation in the current gain. For fixed trap density, the impact of NBR on transistor characteristics, which is generally considered to be negligible in modern Si BJTs, can be exaggerated due to the presence of an increased total base minority carrier charge concentration (Qnb) that participates with the trap recombination process. Because in a SiGe HBT the Ge-induced base bandgap reduction exponentially increases Qnb compared to that in a comparably constructed Si BJT, one would naively expect that the NBR would be strongly enhanced in a SiGe HBT compared to a Si BJT, even at identical trap base density. This situation is also expected to become especially important as the temperature changes, due to the thermally activated nature of Qnb in a SiGe HBT. It is essential, therefore, to understand the physical mechanism of NBR in SiGe HBTs, its impact on the transistor characteristics, and possible circuit implications. For an npn bipolar transistor with negligible EB space–charge region recombination, IB under arbitrary forward-active bias is the sum of the hole current back-injected into the emitter, the hole current due to impact ionization in the collector–base region, and the NBR current component under discussion. For small values of VCB, the additional hole current due to impact-ionization is negligible and thus IB is dominated by the other two components. As the electron diffusion length (Lnb) gets comparable to the neutral base width (Wb), the NBR component of IB becomes increasingly important. With negligible NBR (the ideal case), IB will be independent of VCB for any given VBE. However, under non-negligible NBR, any change in Wb with respect to Lnb will perturb the NBR component of IB. Thus, an easy way to estimate the impact of NBR in a given transistor is to observe the rate of decrease in IB with respect to varying VCB, at a fixed VBE. The base current in this case can be expressed as the sum of the drift-diffusion component and the NBR component as JB ¼ JB;diff þ Jnbr ¼ Jb0 eqVBE =kT þ Jnbr;0 eqVBE =kT :

(4:3:8)

Here Jb0 is assumed to be independent of VCB, while Jnbr,0 is a function of VCB: Jnbr;0 ðSiÞ ¼


 qDnb n2ib cosh xSi
1 , sinh xSi Nab Lnb

(4:3:9)

where x ¼ Wb/Lnb. Since the diffusion component of IB is independent of VCB, the change in IB with VCB will only be due to the variation in Jnbr through the variations in Wb. Therefore, in general, the input conductance of the transistor (gm) can be written as     @JB  @Jnbr  @Jnbr  @Wb  gm ¼ ¼ ¼ : @VCB VBE @VCB VBE @Wb VBE @VCB VBE

(4:3:10)

We can thus determine the gm in a Si BJT to be gm ðSiÞ ¼


   qDnb n2ib qVBE =kT cosh xSi
1 1 @Wb e : Lnb @VCB Nab Lnb sinh2 xSi

ð4:3:11Þ

A more convenient way to compare the variations in Jnbr between devices and across temperature is to normalize gm to the base current at VCB ¼ 0 V (g 0m ). Therefore, by rewriting Equation (4.3.11) using the expressions for both JC and VA derived in Chapter 4.2, we finally obtain g 0m in a Si BJT

© 2006 by Taylor & Francis Group, LLC

4.3-417

Second-Order Effects

gm0 ðSiÞ ¼

gm (Si)
bSi (VBE ; VCB ¼ 0)x 2Si ( cosh xSi
1)  IB;Si (VBE ; VCB ¼ 0) VA;Si (forced-VBE ) sinh2 xSi

(4:3:12)

where bSi(VBE, VCB ¼ 0) represents the current gain measured at a given VBE and VCB ¼ 0 V and VA,Si(forced-VBE) represents the Early voltage at a fixed VBE. Observe that when xSi is zero (representing the ideal situation in the transistor with no NBR), Equation (4.3.12) predicts that g 0m will be zero, as one would expect. On the other hand, when xSi becomes large (i.e., significant NBR is present), then Equation (4.3.12) yields an increased value of g 0m . The g 0m in a SiGe HBT with a trapezoidal Ge profile is difficult to derive analytically. In order to qualitatively determine the device design parameters that strongly influence g 0m , one can consider a simple box Ge profile. In this case, it is easily shown that g 0m in a SiGe HBT is the same as Equation (4.3.12), except for the differences in b. This is expected, since both Jnbr and b in a SiGe HBT are determined primarily by the amount of Ge-induced bandgap reduction at the EB space–charge edge (i.e., DEg,Ge(0)). In general, however, the NBR current component and hence g 0m will be a function of the amount of Ge introduced into the base region of a SiGe HBT (i.e., EB boundary value as well as Ge grading). In addition, since the SiGe-to-Si Jnbr ratio is effectively amplified by cooling, it is expected that the SiGe-to-Si g 0m ratio will also exponentially increase with decreasing temperature. Figure 4.3.5 compares the variation in the normalized-IB as a function of VCB for both the Si and SiGe transistors at 358 and 200 K, respectively. In this case, the transistors are biased in the low-injection region where their collector and base currents are ideal. One can clearly observe the decrease in IB at low VCB due to the modulation of the NBR current component for both transistors, at 358 and 200 K, respectively. The strong decrease in IB at larger values of VCB is due to an increase in the impactionization base current component. By observing the variation in IB with VCB in the low-VCB range, one can easily conclude that the Si BJT shows a weak NBR component (0.5% decrease in IB), while the SiGe HBT shows not only a larger NBR base current component, but also an increase in the NBR with cooling, as anticipated from theory. It is important to note here that, although the NBR component in the SiGe HBT is clearly larger than that in the Si BJT, the magnitude of the NBR component is nevertheless still quite small (3% of IB at 200 K). The measured g 0m in SiGe HBTs is not only expected to be larger than for a comparably constructed Si BJT, but also thermally activated due to the presence of Ge band-offsets in the base region. Figure 4.3.6 confirms this expectation for both triangular and trapezoidal profile SiGe HBTs. 1.00

IB(VCB = 0.0 V)

IB(VCB)

0.99

T = 200 K T = 358 K VBE = 0.85 V VBE = 0.62 V

0.98 AE = 0.8⫻2.5 µm2

Impact Ionization

0.97

0.96

0.95 0.0

SiGe HBT Si BJT 0.2

0.4 0.6 0.8 Collector−base voltage (V)

1.0

FIGURE 4.3.5 Measured normalized-IB as a function of VCB for a SiGe HBT and a Si BJT, at both 358 and 200 K. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-418

The Silicon Heterostructure Handbook

Temperature (⬚C) 85

gµ⬘(SiGe) / gµ⬘(Si)

15

50

−20

27

SiGe HBT AE = 0.8⫻2.5 µm2 Forced-VBE

10 8 6

−55

Trapezoidal Ge Profile

4 EA ~ 60.0 meV

3 2

Triangular Ge profile

EA ~ 34.0 meV

1 2.5

3.0

3.5

4.0

4.5

5.0

1000/T (K−1)

FIGURE 4.3.6 Measured ratio of gm’ in a SiGe HBT and a Si BJT as a function of reciprocal temperature. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

IC and IB

IC and IB IC1 VCB = 0.0 V

IC0

IC0

VCB = 1.0 V

IB0

IB0

VBE

VBE

VBE0

VBE0

No NBR IC

With NBR VBE0 or IB0

IC1

IC0

IB0

IC

VBE0

IC0 Forced-VBE Forced-IB VCE VBE0

VCE VBE0

FIGURE 4.3.7 Illustration of the effects of NBR on the Gummel and output characteristics of a transistor.

A direct consequence of NBR is a difference in the slope of the common-emitter output characteristics of a transistor depending on whether the device is biased using forced-IB or forced-VBE conditions [1]. This can be explained by comparing the dc characteristics for a transistor under an ideal situation (no NBR) with that in the presence of NBR (see Figure 4.3.7). Without NBR, the increase in IC with VCB is the same whether the transistor is biased under forced-VBE or forced-IB input drive, yielding the same VA for both conditions. In the presence of NBR, however, VA measured using both techniques will differ because of the decrease in IB with VCB. In a forced-IB situation, VBE is allowed to change in such a way as

© 2006 by Taylor & Francis Group, LLC

4.3-419

Second-Order Effects

to maintain constant IB. Due to the fact that IB decreases with increasing VCB in the presence of NBR, VBE is forced to increase so as to maintain constant IB. This small increase in VBE exponentially increases IC, leading to a much smaller VA. In a forced-VBE situation, however, the IC increase is due only to the decrease in Wb for an increase in VCB, as one might expect in the ideal case. Thus, in the presence of NBR, VA(forced-IB) will be smaller than VA(forced-VBE), and the two quantities are related through g 0m , according to Ref. [1]: gm0 

1 1
: VA (forced-VBE ) VA (forced-IB )

(4:3:13)

Since g 0m is small in a well-made Si BJT, the difference between VA(forced-VBE) and VA(forced-IB) is expected to be small. Equation (4.3.13) predicts that in SiGe HBTs, however, the difference between VA(forced-VBE) and VA(forced-IB) will be greater because of the larger g 0m compared to that in a Si BJT. Figure 4.3.8 shows VA obtained for both Si and SiGe transistors using forced-IB and forced-VBE conditions as a function of reciprocal temperature. Observe that the VA in a Si BJT, obtained using both techniques, yields similar results, thus confirming the presence of only a weak NBR component in the base current of these transistors. In the SiGe HBTs, however, we can clearly observe a quasiexponential degradation of VA(forced-IB) compared to a quasi-exponential improvement in VA(forcedVBE) with cooling. While it is the bandgap grading in the SiGe HBT that increases the VA(forced-VBE), it is the amount of DEg,Ge(x ¼ 0) that causes the exponential degradation in VA(forced-IB) with cooling. From these experimental results, it is clear that such a strong temperature and input-bias dependent situation for SiGe HBTs could potentially have important consequences on the performance of SiGe HBT analog circuits that depend critically on the output conductance of the transistor. This anticipated impact on circuit performance is confirmed in Figure 4.3.9, which uses SPICE models designed to properly account for NBR in SiGe HBTs and carefully calibrated to data, to assess the impact of NBR on precision current sources (refer to the discussion in Ref. [1]). The presumption in this section is that significant NBR exists in the SiGe HBTs under consideration.

Temperature (⬚C) 100

85

50

27

−20

−55

70 Early voltage (V)

Forced-VBE 50

30 20

Forced-IB

AE = 0.8⫻2.5 µm2 IC ~ 1.0 µA SiGe HBT Si BJT

10 2.5

3.0

3.5 4.0 1000/T (K–1)

4.5

5.0

FIGURE 4.3.8 Measured Early voltage as a function of reciprocal temperature for a SiGe BJT and a Si BJT, using both forced-IB and forced-VBE techniques. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-420

The Silicon Heterostructure Handbook

Output resistance (Rout in GΩ)

5.5 SiGe HBT AE = 0.8⫻2.5 µm2 SPICE simulation

4.5 3.5 2.5

Default SPICE Cascode CS Wilson CS Iout ~ 1.0 µA

Without NBR

1.5 With NBR 0.5 200

240

280 Temperature (K)

320

360

FIGURE 4.3.9 Comparison of calibrated SPICE modeling results both with NBR and without NBR for the output resistance of both Cascode and Wilson precision current sources as a function of temperature. (From AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. IEEE Trans. Electron Dev. 44:404–413, 1997. With permission.)

In this situation we can say: .

.

.

. .

.

An observable difference between VA(forced-VBE) and VA(forced-IB) will exist in the SiGe HBT, and will be reflected in the output characteristics of the transistor. The measured VA(forced-VBE) value in the presence of NBR will be consistent with simple device theory (Chapter 4.2), but the VA(forced-IB) will be degraded (lower) compared to simple theoretical expectations. This input-drive dependent VA difference will be amplified in the SiGe HBT compared to a comparably constructed Si BJT. That is, Ge-induced bandgap engineering will always act to enhance the effects of NBR. This input-drive dependent VA difference will get larger (worse) as the temperature decreases. Careful two-dimensional simulations can be used to identify the physical location of the traps responsible for the NBR component, and correlated with the fabrication process. Accurate compact modeling of SiGe HBTs for circuit design, which includes NBR can be accomplished using existing Si BJT models, but may require an additional parameter to account for the inherently different temperature dependence in VA between a SiGe HBT and a Si BJT. Such NBR-compatible models can provide a detailed assessment of the role of NBR-induced VA changes on particular circuits.

NBR, while clearly inherent to bipolar transistor operation because finite trap densities necessarily exist in semiconductor crystals, does not necessarily strongly perturb the characteristics of modern SiGe HBTs. The experimental results presented in this chapter show a significant NBR base current component, and thus are instructive for understanding and modeling NBR in SiGe HBTs, but we have also measured devices from the other SiGe technologies which do not show appreciable NBRinduced VA changes. Thus, we do not consider NBR to be a ‘‘show-stopper’’ in SiGe HBTs, but rather something to be carefully monitored and assessed during technology development and qualification. In this case, a simple bench-top measurement of IB(VCB)/IB as a function of VCB at two different temperatures (e.g., 300 and 200 K) provides a simple and powerful tool for accurately assessing the presence of significant NBR in a given SiGe HBT technology generation. If present, appropriate steps can be taken to either try and correct the situation by process modification, or models can be developed which accurately account for the effect, thus ensuring that circuit designs are not negatively impacted.

© 2006 by Taylor & Francis Group, LLC

4.3-421

Second-Order Effects

4.3.4 Heterojunction Barrier Effects In order to achieve maximum performance, SiGe HBTs must be biased at very high collector current densities (typically, above 1.0 mA/mm2 for the first-generation SiGe HBTs). High-injection heterojunction barrier effects (HBE), which occur in all HBTs, can cause severe degradation in key transistor metrics such as, b, gm, VA, fT, and fmax, especially at reduced temperatures. Careful transistor optimization is therefore required to delay the onset of the HBE to well above the current density levels required for normal circuit operation. Since the severity of the HBE is mainly determined by the amount of Geinduced band offset at the SiGe–Si heterointerface and the collector doping level, one needs to carefully design the CB junction of the HBT. In order to delay the onset of Kirk effect and hence HBE, one can easily increase the collector doping level (Ndc). Increasing Ndc, however, decreases fmax and BVCEO due to the increase in CCB and the CB electric field, respectively, presenting serious design constraints. The shape and position of the Ge profile in the CB region of a SiGe are critical in determining the characteristics of the onset of HBE and the rate of degradation in HBT characteristics with increasing JC. While large Ge grading is desirable for increasing VA, fT, and fmax of a SiGe HBT, the increased Ge concentration at the CB junction increases the induced barrier associated with HBE. To reduce the impact of the barrier on device performance, one can either gradually decrease the Ge at the CB region or place the SiGe–Si heterointerface deeper inside the collector region, instead of having an abrupt SiGe–Si transition at the interface. Obviously, these methods lead to an increase in the total Ge content of the film, which imposes film stability (and hence manufacturing) constraints on the fabrication process. These device design trade-offs clearly indicate that there exists no specific design solution to completely eliminate HBE. One can, however, tailor the CB design to suit the application at hand, and offers testament to the versatility that can be achieved with bandgap engineering. In Si BJTs operated under high injection in the collector, there are several phenomena that can cause the collector and base currents to deviate from their ideal low-injection behavior (i.e., IC, IB / eqVBE =KT ), including Kirk effect [7], Webster–Rittner effect, the IR drop associated with the base and emitter resistances, and quasi-saturation due to collector resistance. Among these, Kirk effect (or ‘‘base push-out’’) is usually the most important in practical Si BJTs (and SiGe HBTs). The physical basis of Kirk effect lies in the fact that the increased minority carrier concentration in the CB region, at high injection, is sufficient to compensate for the doping-induced charge in the CB space–charge region, causing the space–charge region to first collapse, and then to be pushed deeper into the collector region as JC (hence nC) rises. The displacement of the CB space–charge region effectively increases the base width, which leads to a decrease in the collector current (JC / 1/Wb), and an increase in the base transit time (tb / 1/W 2b ), thus causing a premature degradation in both b and fT. The value of JC at the onset of Kirk effect (JC,Kirk) can be written generally as ( JC;Kirk  qvs Ndc

) 2«(VCB þ fbi ) : 1þ 2 qNdc Wepi

(4:3:14)

The direct relationship between the onset of Kirk effect and the collector doping level is obvious. To get a feel for the numbers, if we assume realistic values for the uniformly doped collector (e.g., Ndc ¼ 11017 cm
3), and an epi-layer thickness of 0.5 mm, we thus expect from Equation (4.3.14) that the onset of Kirk effect will occur at approximately 1.6 mA/mm2. Since maximum device performance is achieved at large current densities, one usually needs to increase Ndc to provide additional immunity to Kirk effect, thereby increasing the CB electric field, and decreasing the CB breakdown voltage. Thus, a fundamental trade-off exists in Si BJTs between device performance (i.e., peak fT) and maximum operating voltage (i.e., BVCEO), as reflected in the socalled ‘‘Johnson-limit’’ [8].

© 2006 by Taylor & Francis Group, LLC

4.3-422

The Silicon Heterostructure Handbook

Extrinsic transconductance (mS/µm2)

In SiGe HBTs, the transition from a narrow bandgap SiGe base layer to the larger bandgap Si collector layer introduces a valence band offset at the SiGe–Si heterointerface. Since this band offset is masked by the band bending in the CB space–charge region during low-injection operation, it has negligible effect on the device characteristics. At high injection, however, the collapse of original CB electric field at the heterointerface exposes the offset, which opposes hole injection into the collector. The hole pile-up that occurs at the heterointerface induces a conduction band barrier that then opposes the electron flow from base to collector, causing an increase in the stored base charge which results in the sudden decrease in both fT and fmax. The ‘‘pinning’’ of the collector current due to this induced conduction band barrier, and the simultaneous increase in the base current due to valence band offset, causes a rapid degradation in desirable characteristics of the SiGe HBT at a HBE onset current density, and can present serious device and circuit design issues. This effect was first reported in Ref. [9], and later addressed by other authors [10, 11]. In addition, since the transport currents are thermally activated functions of the barrier height, it is expected that the HBE will have a much more pronounced impact at reduced temperatures, raising important questions about operation over a wide temperature range [11]. It is therefore essential that the collector profile and the Ge profile be designed properly to reduce the impact of HBE on circuit performance. To experimentally investigate HBE, first-generation SiGe HBTs with three different Ge profiles were measured (a 15% Ge triangle, a 10% Ge trapezoid, and an 8% Ge trapezoid), along with a comparably designed Si BJT control. The collector profile was identical for all the transistors and was selectively implanted to simultaneously optimize fT (at high JC) while maintaining an acceptable BVCEO of about 3.3 V. The Gummel characteristics of all the transistors are ideal across the measured temperature range of 200 to 358 K. While the SiGe HBTs and Si BJTs have differing current gains, as expected, a normalization of b as a function of JC shows that there is a clear difference in high-injection behavior for the SiGe and Si devices, particularly at reduced temperatures. A sensitive test for clearly observing high-injection HBE in SiGe HBTs is to extract the transconductance (gm) at high JC from the Gummel characteristics, at high and low temperatures. As shown in Figure 4.3.10, a clear dip in the gm at 200 K at JC of about 2.0 mA/mm2 can be clearly seen. By comparing gm and b at JC ¼ 2.0 mA/mm2 between the SiGe HBT and the Si BJT at 358 and 200 K, respectively, one can easily deduce that the differences are associated with the Ge profile, and hence are a signature of high-injection HBE. In addition, Figure 4.3.10 suggests that the trapezoidal Ge profiles show a weaker degradation in gm at 200 K compared to the triangular Ge profile, because of the presence of a smaller Ge band offset in the CB junction (15% Ge versus 8% and 10% Ge, respectively), indicating that the specific design of the Ge profile plays a role, as expected.

40

A E = 0.8⫻2.5 µm2 VCB = 0.0 V

30 200 K 20

10 358 K 0 0.0

1.0

SiGe HBT (15% triangle) SiGe HBT (10% trapezoid) SiGe HBT (8% trapezoid) Si BJT (control) 2.0

3.0

4.0

Collector current density (mA/µm2)

FIGURE 4.3.10 Extrinsic transconductance as a function of collector current density for a Si BJT and three SiGe HBT profiles, at 358 and 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-423

Second-Order Effects

To shed light on both the physics of HBE in SiGe HBTs, as well as to determine the optimum doping and Ge profiles for scaled SiGe HBTs, numerical device simulation is required. Figure 4.3.11 shows the electric field distribution in the base–collector region of both calibrated SiGe and Si transistors at low and high JC. Observe that at low JC, the CB built-in electric field entirely covers the SiGe–Si heterointerface. At high injection (JC ¼ 4.0 mA/mm2, past peak fT), however, the CB space–charge region is pushed deep into the collector region in both transistors due to Kirk effect, and in the SiGe HBT a barrier is formed at the original SiGe–Si heterointerface and can be clearly seen in the high-JC field distribution. Figure 4.3.12 shows the evolution of the induced conduction band barrier to electrons in the SiGe HBT as a function of JC. Clearly, the electron barrier appears only at high injection and this can be correlated with the exposure of the SiGe–Si valence band offset (Figure 4.3.13). In addition, the magnitude of the induced conduction band barrier (fB) gets larger as the device is biased progressively

125

Electric field (kV/cm)

75

25

SCORPIO simulation calibrated profile VCB = 0.0 V T = 200 K JC ~ 4.0 mA/µm2

−25

SiGe HBT Si BJT

JC ~ 0.1 mA/µm2

SiGe Si Base

−75 Collector −125 160

260 360 Depth from emitter contact (nm)

460

FIGURE 4.3.11 Simulated electric field distribution in a Si BJT and SiGe HBT at both low and high current density at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

4.0 mA/µm2

Conduction band edge (eV)

1.10 qΦB 1.00

0.90

0.80

SiGe HBT Si BJT

2.0 mA/µm2

SCORPIO simulation calibrated profile VCB = 0.0 V T = 200 K JC ~ 0.1 mA/µm2

0.70 175

225 275 Depth from emitter contact (nm)

325

FIGURE 4.3.12 Simulated conduction band edge as a function of depth for a Si BJT and SiGe HBT, for various current densities at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.3-424

The Silicon Heterostructure Handbook

–0.00

Valence Band Edge (eV)

SCORPIO simulation –0.05 SiGe HBT Si BJT –0.10

Calibrated profile VCB = 0.0 V T = 200 K

4.0 mA/µm2 2.0 mA/µm2

–0.15 JC ~ 0.1 mA/µm2 –0.20 175

225 275 Depth from emitter contact (nm)

325

FIGURE 4.3.13 Simulated valence band edge as a function of depth for a Si BJT and SiGe HBT, for various current densities at 200 K. (From AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. IEEE Trans. Electron Dev. 46:1347–1356, 1999. With permission.)

into higher injection, while at very large current densities fB eventually saturates. Although fB at a fixed JC decreases with cooling due to the shift in operating point with temperature, its impact will be much greater at low temperatures due to its thermally activated nature as a band-edge phenomenon. The sudden increase in JB accompanying the barrier onset in a SiGe HBT is the result of the accumulation of holes in the base region due to HBE. At low injection, one clearly sees that the hole concentration in the base is unperturbed compared to a Si BJT. At high injection, however, not only is the hole profile pushed out into the collector region (Kirk effect) but also the presence of the barrier increases the hole concentration close to the CB junction. A fundamental trade-off in collector profile design exists between maximizing both BVCEO and fmax in SiGe HBTs. RF and microwave power amplifiers require large BVCEO, and therefore the collector doping must be reduced. Obviously, such a reduction in Ndc will adversely affect the large-signal performance due to the premature onset of HBE. One can also, in principle, ‘‘tune’’ the barrier onset by properly adjusting the Ge retrograde profile shape. A higher Ge grading in the base region of a SiGe HBT provides better high-frequency performance throughout the temperature range. Increasing the Ge grading, however, necessarily increases the Ge content in the CB junction, which leads to a stronger barrier effect at high injection. In order to reduce the impact of barrier effect in such cases, one can either more gradually decrease the Ge or push the Ge deeper into the collector. In either case, however, one is limited by the amount of Ge that can be added because of the stability constraints of the SiGe films. The successful insertion of SiGe HBTs into practical systems requires accurate compact circuit models for design. Because SiGe HBTs are typically modeled using Si BJT-based compact models (e.g., SPGP, VBIC, MEXTRAM, or HICUM), it is important to assess the accuracy of these models for capturing unique device phenomena such as high-injection HBE. In most compact models, the Kirk effect and HBE are lumped into a single function, assuming the Kirk effect and barrier effect occur simultaneously. This assumption, however, is no longer valid when the SiGe–Si heterojunction is located either in the neutral base region or deeper in the epitaxial collector. The latter, for instance, can be true in SiGe HBTs optimized for high breakdown voltage. Compact models can fail in this case to capture the functional form of the fT
JC roll-off in SiGe HBTs (Figure 4.3.14). To accurately capture this phenomenon, a new transit time model that decouples the two effects is needed, and is discussed in detail in Ref. [12]. Due to the presence of SiGe–Si heterojunctions in SiGe HBTs, HBEs are inherent in SiGe HBT design and operation, and thus in some sense can be considered the most serious of the three second-order phenomena considered in this chapter. Given this situation, HBE must always be carefully ‘‘designed

© 2006 by Taylor & Francis Group, LLC

4.3-425

Second-Order Effects

fT (GHz)

20 High–breakdown SiGe HBT VCE = 0.8 V AE = 0.48⫻8.4 µm2 10

Measured data HICUM model VBIC model

0 0.1

1.0

5.0

JC (mA/µm2)

FIGURE 4.3.14 Comparison of measured fT–JC characteristics with the HICUM and VBIC compact models in a high breakdown voltage SiGe HBT. (From Q Liang, JD Cressler, G Niu, RR Murty, K Newton, and DL Harame. IEEE Trans. Electron Dev. 49:1807–1813, 2002. With permission.)

around.’’ This is not overly difficult for low-BVCEO transistors where the collector doping is relatively high, effectively retarding Kirk effect. For applications requiring higher breakdown voltage devices (e.g., power amplifiers), however, care must be taken to ensure that HBE do not adversely impact circuit designs, and that they are accurately modeled. For HBE in SiGe HBTs we can state the following: .

.

.

.

.

.

.

HBEs fall into two general categories: (1) induced barriers due to Ge misplacement; and (2) highinjection-induced barriers. The former can be corrected with proper growth and fabrication techniques, and are thus not inherent to a given SiGe technology. The latter, however, can be considered fundamental to the operation of SiGe HBTs, and must be carefully accounted for and accurately modeled by designers. High-JC HBE causes a rapid degradation in b, gm, and fT once the barrier is induced. The critical onset current density for HBE (JC,barrier) is thus a key device design parameter. HBEs are induced in the conduction band when the hole density in the pushed-out base under high-JC is effectively blocked from moving into the collector by the SiGe–Si heterojunction. Both JC and JB are strongly affected. For low-breakdown voltage devices, HBE and Kirk effect generally occur at similar current densities. In higher breakdown voltage devices, or devices with deep SiGe–Si heterojunctions, however, the two effects can occur at very different current densities, producing unusual structure in the fT –JC characteristics, which first-order compact models do not accurately capture. Changes to the Ge retrograde can be used to effectively retard the onset of HBE, but at the expense of reduced film stability. Changes to the collector doping profile can be used to effectively retard the onset of HBE, but at the expense of increased CB capacitance and reduced breakdown voltage. The impact of HBE on device and circuit performance will rapidly worsen as the temperature decreases, because they are band-edge phenomena.

For any SiGe HBT technology generation, it is a prudent exercise to carefully characterize the transistors and assess the significance of HBE on the overall device response, and determine JC,barrier. This is easily accomplished by plotting linear gm on linear JC at two temperatures (e.g., 300 and 200 K), and this knowledge can then be communicated to circuit designers. If JC,barrier is low enough for practical concerns, then Ge or collector profile modifications can be implemented to alleviate any problems. When moving to a new technology generation with different Ge and doping profiles, HBE should always be revisited.

© 2006 by Taylor & Francis Group, LLC

4.3-426

The Silicon Heterostructure Handbook

4.3.5 Summary Important second-order effects associated with: (1) Ge grading, (2) neutral base recombination, and (3) HBEs will always exist in SiGe HBTs, and their specific impact on actual SiGe HBT device and circuit operation is both profile-design- and application-dependent, and thus must be carefully considered by designers.

Acknowledgments I am grateful to A. Joseph, S. Salmon, Q. Liang, G. Niu, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. EF Crabbe´, JD Cressler, GL Patton, JMC Stork, JH Comfort, and JY-C Sun. Current gain rolloff in graded-base SiGe heterojunction bipolar transistors. IEEE Electron Dev. Lett. 14:193–195, 1993. 3. SL Salmon, JD Cressler, RC Jaeger, and DL Harame. The impact of Ge profile shape on the operation of SiGe HBT precision voltage references. IEEE Trans. Electron Dev. 47:292–298, 2000. 4. HA Ainspan and CS Webster. Measured results on bandgap references in SiGe BiCMOS. Electron. Lett. 34:1441–1442, 1998. 5. AJ Joseph, JD Cressler, RC Jaeger, DM Richey, and DL Harame. Neutral base recombination and its impact on the temperature dependence of Early voltage and current gain — Early voltage product in UHV/CVD SiGe heterojunction bipolar transistors. IEEE Trans. Electron Dev. 44:404–413, 1997. 6. AJ Joseph, JD Cressler, and DM Richey. Optimization of Early voltage for cooled SiGe HBT precision current sources. J. Phys. IV 6:125–130, 1996. 7. CT Kirk. Theory of transistor cutoff frequency falloff at high current densities. IRE Trans. Electron Dev. 3:164–170, 1964. 8. EO Johnson. Physical limitations on frequency and power parameters of transistors. RCA Rev. 163–177, 1965. 9. S Tiwari. A new effect at high currents in heterostructure bipolar transistors. IEEE Electron Dev. Lett. 9:142–144, 1988. 10. PE Cottrell and Z Yu. Velocity saturation in the collector of Si/GexSi1
x HBTs. IEEE Electron Dev. Lett. 11:431–433, 1990. 11. AJ Joseph, JD Cressler, DM Richey, DL Harame, and G Niu. Optimization of SiGe HBTs for operation at high current densities. IEEE Trans. Electron Dev. 46:1347–1356, 1999. 12. Q Liang, JD Cressler, G Niu, RR Murty, K Newton, and DL Harame. A physics-based, high-injection transit-time model applied to barrier effects in SiGe HBTs. IEEE Trans. Electron Dev. 49:1807–1813, 2002.

© 2006 by Taylor & Francis Group, LLC

4.4 Low-Frequency Noise 4.4.1 4.4.2 4.4.3 4.4.4

Background ................................................................ 4.4-427 Measurement Methods ............................................. 4.4-427 Physical Origins ......................................................... 4.4-429 SiGe Profile Impact and Modeling .......................... 4.4-431 1/f Noise KF Factor . Geometry Dependence . 1/f Corner Frequency . Impact of Collector–Base Junction Traps . Technology Scaling

4.4.5

1/f Noise in Oscillators . Phase Noise Implications . Synthesizer Phase Noise and Threshold K

Guofu Niu Auburn University

Oscillator and Synthesizer Phase Noise Issues........ 4.4-435

4.4.6

Summary .................................................................... 4.4-437

4.4.1 Background Because of Si-based processing, the low-frequency noise in SiGe HBTs is comparable to that in Si BJTs, which is typically much better (lower) than in III–V HBTs [1–3]. Of particular importance is the 1/f noise or flicker noise, which dominates at low frequency, and can be upconverted to phase noise in RF oscillators through nonlinear I–V and C–V relationships inherent to the transistor. This results in noise sidebands on the carrier frequency, which fundamentally limits spectral purity. Low-frequency noise is also very important for wireless receivers utilizing zero or very low intermediate frequency (IF) architectures. In this chapter, we will introduce the basics of 1/f noise measurement and modeling in SiGe HBTs, its dependence on technology scaling, implications of SiGe, and upconversion to phase noise. We will introduce a method to determine the maximum tolerable 1/f noise level for a given RF process, which can be used to aid process development, as the reduction of 1/f noise is quite challenging in manufacturing, particularly in scaled technologies with low thermal cycle.

4.4.2 Measurement Methods The major 1/f noise source in SiGe HBTs is in the base current, as it is in typical polysilicon emitter Si BJTs. In an equivalent circuit representation, this is described using a noise current source placed between the internal base and emitter nodes. One can measure this noise current either indirectly through measuring the collector noise voltage or directly through measuring the base noise current. The indirect method is relatively easier to implement in practice, and is illustrated in Figure 4.4.1. The potentiometers PB and PC set the dc bias at the base and collector, respectively. Batteries are the preferred power supplies as they have the least amount of spurious noise. The two large capacitors CB and CC provide dynamic ac grounding. They can be left out for simplicity, but care must be exercised in determining the effective source and load resistances seen by the transistor.

4.4-427 © 2006 by Taylor & Francis Group, LLC

4.4-428

The Silicon Heterostructure Handbook

RB is chosen to be much greater than transistor input impedance rp such that the base noise current flows into the transistor for amplification. The voltage noise at RC is further amplified by a low-noise preamp, and detected by a dynamic signal analyzer (DSA). The base current noise (SIB) is obtained from the measured collector voltage noise SVC as SIB ¼

SVC : (RC b)2

(4:4:1)

Strictly speaking, the small-signal b should be used in Equation (4.4.1). If capacitor CC is not used, the effective dynamic load resistance seen by the collector node is used in place of RC. The base bias resistance RB typically ranges from 50 kV to 10 MV, and the collector sampling resistance RC is on the order of 2 kV. Because of the RB >> rp requirement, very large RB is needed for measurement at low IB values. At low IB, the base current noise can be directly measured using a current amplifier (as shown in Figure 4.4.2). A large bypass capacitance CB short-circuits the noise from the base-biasing network, and creates a low impedance path for the base current 1/f noise. The key is to make sure that the input impedance of the current amplifier is much lower than the transistor input impedance (rp), so that all of

DSA

PB

Voltage amplifier

RB

ib

CB

RC CC

PC

FIGURE 4.4.1 Indirect measurement of 1/f noise.

1 MΩ

PB

CC CB

ib

2

S V = G i SIB DSA

GI :gain amplifier

FIGURE 4.4.2 Direct measurement of 1/f noise.

© 2006 by Taylor & Francis Group, LLC

Current amplifier

PC

4.4-429

Low-Frequency Noise

10−20 10−21 SiGe Control AE = 0.5⫻2.5 µm2 I B = 1 µA

SIB (A2/Hz)

10−22 10−23 1/f

10−24

2qIB

10−25 f C = 2.04 kHz

10−26 10−27 100

FIGURE 4.4.3 IB ¼ 1 mA).

101

102 103 Frequency (Hz)

104

105

A typical low-frequency noise spectrum of a first generation SiGe HBT (AE ¼ 0.5
2.5 mm2, and

the base noise current flows into the current amplifier. The current amplifier output voltage is proportional to the base noise current, and the gain of the current amplifier has units of V/A. Figure 4.4.3 shows a typical low-frequency base current noise spectrum (SIB) for a first-generation SiGe HBT. The noise spectrum shows a clear 1/f component as well as the 2qIB shot noise level. The corner frequency fC is determined from the intercept of the 1/f component and the 2qIB shot noise level. At higher IB values, the 2qIB shot noise level cannot be directly observed for various reasons. The calculated 2qIB value can be used to determine fC in this case.

4.4.3.

Physical Origins

The exact origins of 1/f noise are not well understood. A popular theory, proposed by McWhorter [4], describes 1/f noise as a superposition of individual generation–recombination (g–r) noise. Each interfacial trap generates g–r noise with a Lorentzian-shaped spectral density given by SI;i ¼

Ati , 1 þ (2pf p2i )

(4:4:2)

where A is the magnitude of the g–r noise, and ti is the time constant for the trapping–detrapping process. A large number of these traps and a particular statistical distribution of ti (1/t) give rise to 1/f spectral shape. Figure 4.4.4 shows such an example of Lorentzian spectra (dashed lines), and the superpositioned spectrum, which is approximately 1/f. This model assumes no interaction between trap levels at different energies. If the levels interact with each other, a Lorentzian spectrum instead of 1/f spectrum may be observed [5]. This model is expected to work well in devices with large emitter area, where a large number of traps exist. In small emitter area devices, however, one may expect to observe a Lorentzian shape of behavior. Experimental data support the above trapping origin of 1/f noise in SiGe HBTs [6]. Figure 4.4.5(a) and (b) shows the low-frequency noise spectra measured on SiGe HBTs with small and large emitter areas, 0.24
0.48 mm2 and 0.96
1.6 mm2, respectively. Three samples are measured for each area. The low-frequency noise spectra show a strong deviation from 1/f behavior and a larger statistical scatter in the small devices. The average of all samples, shown as solid lines, shows a close to 1/f frequency dependence.

© 2006 by Taylor & Francis Group, LLC

4.4-430

The Silicon Heterostructure Handbook

Noise spectral density (A2/Hz)

10−21 10−22

1/f

10−23 10−24 10−25 10−26 10−27 100

101

102 103 Frequency (Hz)

104

105

FIGURE 4.4.4 1/f noise as a superposition of Lorentzians. 10−19

SIB

(A2/Hz)

10−20 10−21 10−22 10−23

SiGe HBTIB = 1 µA AE = 0.24⫻0.48 = 0.12 µm2 δ = 0.56

10−24 10−25 100

101

(a)

102

103

104

Frequency (Hz)

10−19

SIB

(A2/Hz)

10−20

SiGe HBTIB = 1 µA AE = 0.96⫻1.6 = 1.54 µm2 δ = 0.18

10−21 10−22 10−23 10−24 10−25 100

(b)

101

102

103

104

Frequency (Hz)

FIGURE 4.4.5 Low-frequency noise spectra in three samples with emitter area of (a) AE ¼ 0.24
0.48 mm2 and (b) AE ¼ 0.96
1.6 mm2.

© 2006 by Taylor & Francis Group, LLC

4.4-431

Low-Frequency Noise

4.4.4 SiGe Profile Impact and Modeling 1/f Noise KF Factor In general, SIB is related to IB by SI B ¼ K F

IBa , f

(4:4:3)

where KF and a correspond to the KF and AF model parameters used in SPICE. a ¼ 1 is often viewed as indication of carrier mobility fluctuations, and a ¼ 2 is often viewed as for carrier number fluctuations [7–13]. The a for typical SiGe HBTs is close to 2, and varies only slightly with SiGe profile and collector doping profile (2 þ 0.2). An often-asked question is whether the introduction of SiGe in transistor base affects the 1/f noise KF factor. Assuming that the 1/f noise is solely a function of the number of minority carriers injected into the emitter, one may expect the same 1/f noise at a given VBE, which means the same IB for a SiGe HBT and its Si counterpart. Thus, the 1/f noise K factor is expected to be the same. This turns out to be true experimentally [14]. Figure 4.4.6 shows the SIB at 10 Hz versus IB for three experimental SiGe HBTs and a comparably fabricated Si BJT. The SiGe HBTs include a 10% peak Ge profile control, a 14% peak Ge low-noise design (LN1), and an 18% peak Ge low-noise design (LN2). The Si BJT is an epi-base device. All the devices were fabricated in the same wafer lot. A constant IC comparison is more meaningful in the context of RFIC design, because many RF figures-of-merit fundamentally depend on IC instead of IB (e.g., fT and fmax). In addition, NFmin, though dependent on IB, is often compared at the same operating IC as well. If we compare SIB at the same IC, however, SIB is significantly lower (better) in SiGe HBTs than in Si BJTs, because of the lower IB (higher b) found in SiGe HBTs, all else being equal. Since SIB / I2C /b2, the SIB for the LN1 and LN2 SiGe HBTs should be naturally lower than for the SiGe control and Si BJT because of their higher b. This is confirmed by the measured data shown in Figure 4.4.7.

Geometry Dependence The 1/f noise amplitude, as measured by the KF factor, scales inversely with the total number of carriers in the noise-generating elements, according to Hooge’s theory [15]. The 1/f noise generated by sources in the EB spacer oxide at the device periphery is inversely proportional to the emitter perimeter PE ¼ WE þ LE, while the 1/f noise generated by sources located at the intrinsic EB interface (i.e., the emitter 10−18

S IB (A2/Hz)

10−19 10−20 10−21

14% α IB2.08 18% α IB2.11 10% α IB2.24 Si α I B2.03 αIB2

10−22

AE = 0.5⫻2.5 µm2 f = 10 Hz VCB = 0 V

10−23 10−24 10−7

10−6 I B (A)

10−5

FIGURE 4.4.6 Measured SIB at 10 Hz as a function of IB for the Si BJT, the SiGe control, and the two low-noise SiGe HBTs.

© 2006 by Taylor & Francis Group, LLC

4.4-432

The Silicon Heterostructure Handbook

10−18 SiGe LN1 a IC2.42 SiGe LN2 a IC2.35 SiGe Control a IC2.45 Si BJT a IC2.19

S IB (A2/Hz)

10−19 10−20 10−21

aIC2

10−22 AE = 0.5⫻2.5 µm2 f = 10 Hz VCB = 0 V

10−23 10−24

10−4

10−3 IC (A)

FIGURE 4.4.7 SiGe HBTs.

Measured SIB at 10 Hz as a function of IC for the Si BJT, the SiGe control, and the two low-noise

polysilicon–silicon interface) across the emitter window is inversely proportional to the emitter area AE ¼ WELE. The KF factor is often examined as a function of the emitter area, the emitter perimeter, or the perimeter-to-area ratio as a means of locating the contributing 1/f noise sources [9–13]. For instance, for fixed frequency, the combination of 1/AE dependence with an IB2 bias dependence for SIB is consistent with a uniform area distribution of noise-generating traps across the emitter region. In practice, caution must be exercised in interpreting PE or AE scaling data, because test devices are often designed with the emitter width equal to the minimum feature size, and with an emitter length much larger than the emitter width. As a result, such data tend to scale with the emitter perimeter and area in a similar manner, making interpretation difficult. A wide distribution of device sizes and PE/AE ratios thus needs to be used when designing test structures for noise-scaling studies in order to make a clear distinction between PE and AE scaling in SiGe HBTs. For all the SiGe HBTs described in ‘‘1/f Noise KF Factor,’’ the 1/f noise KF factor is inversely proportional to AE. Equation (4.4.3) can thus be rewritten as SI B ¼

K IB2 K 1 IC2 ¼ 2 ; AE f b AE f

(4:4:4)

where K is a factor independent of the emitter area and is defined as K ¼ KFAE, where a ¼ 2 is assumed. Equation (4.4.4) is written as a function of IC to facilitate technology comparisons for RFIC circuit design, for reasons discussed above. Because the K factor for low-frequency noise is approximately independent of base profile design, a higher b SiGe HBT has a lower SIB, and hence generates lower phase noise when used in RF amplifiers and oscillators. For a given operating current, a larger device can clearly be used to reduce SIB. This tactic, however, reduces fT because of the lower JC. The maximum device size one can use is usually limited by this fT requirement. Optimum transistor sizing is thus important not only for reducing NFmin, but also for reducing phase noise [14].

1/f Corner Frequency Traditionally, 1/f noise performance is characterized by the corner frequency ( fC) figure-of-merit, defined to be the frequency at which the 1/f noise equals the shot noise level 2qIB. Equating (4.4.4) with 2qIB leads to fC ¼

© 2006 by Taylor & Francis Group, LLC

KIB KJC ; ¼ 2qAE 2qb

(4:4:5)

4.4-433

Low-Frequency Noise

where JC is the collector current density, and b is the dc b. Equation (4.4.5) suggests that fC is proportional to JC and K, and inversely proportional to b. We note that this conclusion differs from that derived in Ref. [16]. The derivation in Ref. [16] showed that fC is independent of bias current density, because a ¼ 1 was assumed (i.e., according to mobility fluctuation theory). This dependence of a, however, is not the case in typical SiGe HBTs, which show an a close to 2. Figure 4.4.8 shows the measured and modeled fC – JC dependence for the devices used here. As expected, fC is the lowest in the two low-noise SiGe HBTs, LN1 and LN2, and highest for the Si BJT. The modeling results calculated using Equation (4.4.5) fit the measured data well.

Impact of Collector–Base Junction Traps A subtle effect in SiGe HBTs is the carrier traps near the SiGe–Si growth interface, which are also referred to as collector–base junction traps, because the SiGe–Si growth interface is right in the collector–base junction depletion layer. These traps contribute to a recombination current in the CB ‘‘depletion’’ layer, which is small in magnitude but strongly modulated by the CB voltage, and is responsible for the output conductance degradation under forced-IB operation [17]. At high injection, when the electron concentration in the CB depletion layer becomes comparable to the depletion charge density, the electrical neutral base pushes out. The CB junction traps are now exposed to a large amount of electrons and holes, resulting in a large amount of recombination current. This effect is particularly severe in highbreakdown voltage (HBV) devices, in which collector doping is high and high injection occurs at lower current densities. A natural question is whether these CB junction traps contribute to low-frequency noise. By comparing the base current and base current noise of standard and HBV devices, it was recently found that these CB junction traps indeed produce additional 1/f noise [18]. Conceptually, one can divide the total 1/f noise in a HBV device into two components, one due to EB junction traps and the other due to CB junction traps. The EB noise component is a function of the emitter injection component of the base current, and the CB noise component is a function of the CB recombination current. Figure 4.4.9 shows the two 1/f noise components as a function of their respective base current components [18]. The EB and CB 1/f noises clearly show different dependences on their respective base current components, indicating that the 1/f noise process at the CB junction traps is different from that in the EB junction. For circuit modeling, however, one may continue to simply model the total base current 1/f noise as a function of the total base current, despite that there are two different 1/f noise processes. An accurate model for the CB junction trap-induced recombination current is necessary and has yet to be developed.

100 SiGe LN1 SiGe LN2 SiGe Control Si BJT

fC (kHz)

80 60 40 20 0 0

0.2

0.4

0.6 0.8 JC (mA/µm2)

1.0

1.2

FIGURE 4.4.8 Measured and modeled fC versus JC for the standard breakdown voltage Si BJT, the SiGe control, and the two low-noise SiGe HBTs.

© 2006 by Taylor & Francis Group, LLC

4.4-434

The Silicon Heterostructure Handbook

Technology Scaling The 1/f noise K factor has recently been found to increase with technology scaling [19, 20]. This is likely associated with the physical changes of the emitter–base junction composition during scaling. With scaling, a narrow and more heavily doped base profile is used, which requires a lower thermal cycle for the bipolar processing. The Ge grading often increases with scaling to create a higher accelerating electric field for minority carriers. The addition of carbon in scaled SiGe HBT technologies, though a small amount for suppressing boron outdiffusion, could inadvertently increase 1/f noise. The increase of the 1/f noise K factor with scaling tends to increase fC,1/f . However, depending on device design, b is often increased with scaling as well, which partially offsets the K factor increase. Figure 4.4.10 shows the measured fC a function of JC for HBTs with peak fT of 50 and 120 GHz. The nature of bipolar transistor operation necessitates a higher operating JC to realize the high-speed potential offered by scaling. A larger JC range is thus used for the 120 GHz HBT. For a given JC , an increase of fC,1/f is observed. At JC ¼ 2.5 mA/mm2, the 120 GHz HBT shows a fC,1/f of 1.6 MHz, which is relatively high compared to a 50 GHz HBT at JC ¼ 1 mA/mm2. Such an increase of 1/f corner frequency, however, does not necessarily cause an increase of the overall oscillator phase noise or the ultimate frequency synthesizer noise, due to different mechanisms of phase noise upconversion for the base current 1/f noise and base current shot noise [20].

SIpe (A2/Hz), SIcbsr (A2/Hz)

10−19 SIcbsr−Icbsr

10−20 10−21

HBV LN1

aCB = 1.92, KFCB = 0.52×10−9

Frequency = 10 Hz SIpe−Ipe

10−22

αEB = 2.06, KFEB = 1.35×10−9

10−23 10−24

10−6

10−5 Ipe (A), Icbsr (A)

FIGURE 4.4.9 SIpe – Ipe and SIcbsr – Icbsr dependencies. Frequency is 10 Hz.

fC,1/f (kHz)

1800

120 GHz HBT 50 GHz HBT

1200

600

0 0

FIGURE 4.4.10 Measured fC,1/f versus JC.

© 2006 by Taylor & Francis Group, LLC

0.5

1.0

1.5 2.0 JC (mA/µm2)

2.5

3.0

4.4-435

Low-Frequency Noise

4.4.5 Oscillator and Synthesizer Phase Noise Issues 1/f Noise in Oscillators So far we have considered 1/f noise measured under a given dc biasing IB. In oscillators, the situation is more complicated as [20]: .

.

The base terminal IB is different from the base–emitter junction transport current IBE, because of the capacitive charging and discharging of the junction capacitances. Only IBE generates noise. The noise generating IBE is ‘‘oscillating’’ by the very nature of oscillation.

Figure 4.4.11 compares the waveforms of the terminal IB and internal noise generating IBE in a 5.5 GHz SiGe HBT oscillator. Also shown is the VBE waveform. Clearly, a large difference exists between IBE and IB. Strictly speaking, one cannot simply determine the 1/f noise for an oscillating transistor from the small signal 1/f noise measurement. Measurement of 1/f noise with a periodic large signal biasing, however, is quite involved, particularly if high frequency is involved. In practice, the amount of 1/f noise for an oscillating transistor is assumed to be the same as the 1/f measured at a dc biasing current identical to the dc component of the oscillating noise generating current IBE. This is implemented in CAD tools such as Agilent ADS.

Phase Noise Implications In oscillators, 1/f noise is upconverted to a 1/f 3 phase noise, while all the white noise (shot noise and thermal resistance noise) are upconverted to 1/f 2 phase noises. Figure 4.4.12 shows simulated phase noise versus offset frequency for two HBTs with 50 and 120 GHz peak fT. With device scaling from 50 to 120 GHz technology, the 1/f 3 component increases by 11.4 dB, in part because of the increasing K factor. The 1/f 2 phase noise resulting from upconversion of white noises, however, improves (decreases) by 7.2 dB with HBT scaling. We now define the corner offset frequency, fC,offset, using the intersect of the 1/f 3 and 1/f 2 phase noises. fC,offset is a direct measure of the importance of the phase noise upconverted from 1/f noise with respect to the phase noise upconverted from the white noise sources. fC,offset is 595.4 Hz and 40.8 kHz for the 50 and 120 GHz technologies (as can be seen from Figure 4.4.13). Note that fC,offset itself does not contain any information on either the 1/f 3 or 1/f 2 phase noise level. A higher fC,offset does not necessarily mean higher phase noise. In this case, the fC,offset for the 120 GHz HBT is nearly 70
higher than for the 50 GHz HBT. The overall effect of scaling on oscillator phase

600 0.95 VBE

IB

200 0.90

IBE

0

VBE (V)

IB, IBE (µA)

400

–200 –400

0.85

50 GHz HBT fo = 5.5 GHz

–600 0

100

200 Time (ps)

300

400

FIGURE 4.4.11 Comparison of terminal IB and internal IBE for a SiGe HBT in a 5.5 GHz oscillator. The internal VBE is shown on the right y-axis.

© 2006 by Taylor & Francis Group, LLC

4.4-436

The Silicon Heterostructure Handbook

60 50 GHz HBT 120 GHz HBT

Phase noise (dBc/Hz)

30 0 −30

fo = 5.5 GHz 1/f 3

−60 −90

1/f 2

−120 −150 100

fc,offset 101

102 103 104 105 Offset frequency (Hz)

106

107

Within loop bandwidth

Outside loop bandwidth

LPLL

LVCO

FIGURE 4.4.12 Phase noise of oscillators designed using HBTs with 50 and 120 GHz peak fT.

1/f 3

Within loop bandwidth

Outside loop bandwidth

1/f 3 f loop = 10×f c,offfset L1/f 3 (f loop) =

1 L 2 (f ) 10 1/f loop VCO phase noise dominated

10⫻

1/f 2

10⫻

f c,offset

f loop

f offset

Reference phase noise dominated

10⫻

f loop

1/f 2

f offset

FIGURE 4.4.13 Illustration of the conversion process of VCO and reference phase noise to frequency synthesizer phase noise and the definition of Kth.

noise is a degradation at offsets below 10 kHz, but an improvement at higher offset frequencies. In a frequency synthesizer, if the loop bandwidth is much greater than 10 kHz, the overall synthesizer phase noise will improve with scaling, despite increased 1/f corner frequency, as the oscillator phase noise below 10 kHz is removed by loop feedback.

Synthesizer Phase Noise and Threshold K In frequency synthesizers, the VCO phase noise within the loop bandwidth is suppressed by the loop feedback mechanism. The out-of-band phase noise of the VCO, however, directly translates into synthesizer out-of-band phase noise. From an application standpoint, if the loop bandwidth is sufficiently higher than the corner offset frequency, the 1/f 3 phase noise can be completely suppressed by loop feedback. The out-of-band noise will then be the 1/f 2 phase noise due to white noises. Using 10


© 2006 by Taylor & Francis Group, LLC

4.4-437

Low-Frequency Noise

103

fc,offset (kHz)

102

50 GHz HBT 120 GHz HBT

f loop = 200 kHz

K 120G f c,offset = 20 kHz

101

100

K 50G

Kth = 2.784 µm2 Kth = 3.73×10−9 µm2

10−1

10−12

10−10

10−8

10−6

10−4

10−2

100

102

K factor (µm2)

FIGURE 4.4.14 fC,offset versus K factor. Kth is determined for a loop bandwidth of 200 kHz. The actual K values are shown as ‘‘*.’’

as a criterion, the 1/f 3 phase noise is only one tenth of the 1/f 2 phase noise at the loop bandwidth offset frequency, for a fC,offset that is one tenth of the loop bandwidth (as shown in Figure 4.4.14). For a given oscillator, fC,offset decreases linearly with K according to the analysis in Section 4.4.4. For a given process and loop bandwidth, a threshold K that makes fC,offset equal to one tenth of the loop bandwidth can be defined. Once K < Kth, the synthesizer phase noise no longer decreases with further decrease of K. One can also view this threshold K as the maximum tolerable K. This is very attractive from a semiconductor technology development standpoint, because the 1/f K factor is sensitive to defect level, and very challenging to minimize. Figure 4.4.14 shows fC,offset versus 1/f noise K factor for two technologies of 50 and 120 GHz peak fT. Assuming a loop bandwidth of 200 kHz, Kth is determined as K at which fC,offset ¼ 20 kHz, such that the 1/f 3 phase noise is only 10% of the 1/f 2 noise at 200 kHz. For the 50 GHz HBT, Kth ¼ 2.748 mm2, and the actual K (2.0
109 mm2) is well below Kth. Thus 1/f noise is not a concern for synthesizer phase noise, since practically all the 1/f 3 phase noise is suppressed by loop feedback, and the in-band noise is limited by reference oscillator. For the 120 GHz HBT, Kth ¼ 3.73
109 mm2, which is slightly smaller than the actual K of 8.6
108 mm2. The combination of decreasing Kth and increasing K with scaling makes 1/f noise an increasingly important concern for phase noise of frequency synthesizers.

4.4.6 Summary In this chapter, we have discussed the measurement, modeling, and system phase noise implications of 1/f noise. The 1/f noise K factor, which measures the amount of base current 1/f noise for a given IB, is shown to be a better measure for phase noise than the traditional 1/f noise corner frequency. SiGe HBTs with high corner frequency can still show excellent phase noise performance when used in oscillators. For a given process, the 1/f K factor only needs to be below a certain threshold, and any further reduction of the K factor does not help in reducing system phase noise. The threshold (Kth) is shown to decrease with scaling. This, together with the increase of K factor with technology scaling, makes 1/f noise an increasingly important concern with further scaling.

Acknowledgments The author would like to thank J. Tang for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ1133.

© 2006 by Taylor & Francis Group, LLC

4.4-438

The Silicon Heterostructure Handbook

References 1. L Vempati, JD Cressler, JA Babcock, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors. IEEE J. Solid-State Circ. 31:1458–1467, 1996. 2. B Van Haaren, M Regis, O Llopis, L Escotte, A Gruhle, C Mahner, R Plana, and J Graffeuil. Lowfrequency noise properties of SiGe HBTs and application to ultra-low phase-noise oscillators. IEEE Trans. Micro. Theory Tech. 46:647–652, 1998. 3. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, GG Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS Technology. IEEE Trans. Electron Dev. 48:2575–2594, 2001. 4. AL McWhorter. 1/f noise and germanium surface properties. Semicond. Surf. Phys. 207, 1980. 5. FN Hooge. 1/f noise sources. IEEE Trans. Electron Dev. 41:1926–1935, 1994. 6. Z Jin, JD Cressler, GF Niu, and AJ Joseph. Impact of geometrical scaling on low-frequency noise in SiGe HBTs. IEEE Trans. Electron Dev. 50:676–682, 2003. 7. LKJ Vandamme. Noise as a diagnostic tool for quality and reliability of electronic devices. IEEE Trans. Electron Dev. 41:2174–2187, 1994. 8. A Mounib, F Balestra, N Mathieu, J Brini, G Ghibaudo, A Chovet, A Chantre, and A Nouailhat. Low-frequency noise sources in polysilicon emitter BJTs: Influence of hot-electron-induced degradation and post-stress recovery. IEEE Trans. Electron Dev. 42:1647–1652, 1995. 9. MJ Deen, J Ilowski, and P Yang. Low frequency noise in polysilicon–emitter bipolar junction transistors. J. Appl. Phys. 77:6278–6285, 1995. 10. M Koolen and JCJ Aerts. The influence of non-ideal base current on 1/f noise behaviour of bipolar transistors. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, September 1990, pp. 232–235. 11. HAW Markus and TGM Kleinpenning. Low-frequency noise in polysilicon emitter bipolar transistors. IEEE Trans. Electron Dev. 42:720–727, 1995. 12. P Llinares, D Celi, and O Roux-dit-Buisson. Dimensional scaling of 1/f noise in the base current of quasi self-aligned polysilicon emitter bipolar junction transistors. J. Appl. Phys. 82:2671–2675, 1997. 13. MJ Deen, SL Rumyantsev, and M Schroter. On the origin of 1/f noise in polysilicon emitter bipolar transistors. J. Appl. Phys. 85:1192–1195, 1999. 14. GF Niu, Z Jin, JD Cressler, R Rapeta, AJ Joseph, and DL Harame. Transistor noise in SiGe HBT RF technology. IEEE J. Solid-State Circ. 36:1424–1427, 2001. 15. A van der Ziel. Noise in Solid State Devices and Circuits. Wiley, New York, 1986. 16. LKJ Vandamme and G Trefan. Review of low-frequency noise in bipolar transistors over the last decade. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, 2001, pp. 68–73. 17. GF Niu, JD Cressler, and AJ Joseph. Quantifying neutral base recombination and the effects of collector–base junction traps in UHV/CVD SiGe HBTs. IEEE Trans. Electron Dev. 45:2499–2503, 1998. 18. J Tang, GF Niu, AJ Joseph, and DL Harame. Impact of collector–base junction traps on low-frequency noise in high breakdown voltage SiGe HBTs. IEEE Trans. Electron Dev. 51:1475–1482, 2004. 19. JA Johansen, Z Jin, JD Cressler, and AJ Joseph. Geometry-dependent low-frequency noise variations in 120 GHz fT/SiGe HBTs. Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 57–59. 20. GF. Niu, J Tang, Z Feng, AJ Joseph, and DL Harame. Scaling and technological limitations of 1/f noise and oscillator phase noise in SiGe HBTs. IEEE Trans. Micro. Theory Tech. 53:506–514, 2005.

© 2006 by Taylor & Francis Group, LLC

4.5 Broadband Noise

David R. Greenberg IBM Thomas J. Watson Research Center

4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6

Introduction............................................................... 4.5-439 HBT Noise Mechanisms and Modeling .................. 4.5-440 Noise Performance Overview and Trends............... 4.5-445 Device Optimization for Low Noise........................ 4.5-450 Circuit Performance .................................................. 4.5-453 Summary .................................................................... 4.5-455

4.5.1 Introduction The ultimate data rate of any communication channel is constrained by the bandwidth and the signalto-noise ratio (SNR) of the channel [1]. As a result, the quantity of noise at any point in a signal chain places a direct limit on how many bits per second can pass through that point for a given bandwidth and power level. In a typical system such as a wireless receiver, noise can be introduced in a variety of ways, including by the active devices (both bipolar and MOS) used to implement the circuits. Noise may be added directly in band with the signal, such as in the case of a low-noise amplifier (LNA) at the front end of a receiver chain or in the baseband amplifier near the end of the chain. In addition, nonlinearities may allow noise to enter the channel band indirectly. For example, transistor noise in a voltage-controlled oscillator (VCO) circuit introduces phase noise in the output sinusoid. When serving as a local oscillator, such a signal passed to a mixer along with the data signal can cause out-of-band (e.g., adjacent channel) energy to fold in-band, contributing interference that degrades channel capacity in a manner analogous to noise. While the effects of noise can be countered by increasing the energy per bit, which translates into signal power for a given bit rate, many applications, particularly portable systems such as cellular phones, GPS receivers, and WLAN-capable PDAs, are constrained in transmitted or received signal power by battery life limits, transmitter–receiver distance, feasible antenna and package size or standards and regulatory requirements. Supply voltage and amplifier gain compression can impose an upper signal power limit as well. Thus, communication system designers seeking an attractive trade-off between throughput, signal power, and bit-error rate demand technologies capable of processing high-frequency signals while introducing as little noise as possible. Both in discrete and integrated form, the SiGe HBT has emerged as an attractive low-noise solution, combining the performance of more expensive devices such as III–V FETs and HBTs with the process control, integration potential, and low cost associated with silicon [2, 3]. The technology has been penetrating the market steadily, beginning with cellular telephony and wireless networking parts built in the 0.5-mm node for the 0.8 to 2.4 GHz range and progressing toward emerging applications such as 77 GHz automotive radar using the 0.13-mm node. At the same time, the SiGe HBT has proven amenable to accurate analysis and modeling, enabling the circuit designer to achieve the cost and time to market advantages of first-pass design success.

4.5-439 © 2006 by Taylor & Francis Group, LLC

4.5-440

The Silicon Heterostructure Handbook

4.5.2 HBT Noise Mechanisms and Modeling The SiGe HBT is a vertical device, with carrier transport confined largely to low-defect bulk material. As a result, high-frequency noise in the device under typical bias conditions is well described by a simple, one-dimensional physical model containing five fundamental noise sources (as illustrated in Figure 4.5.1). In forward bias, a voltage VBE applied across the base–emitter junction creates a net flow of electrons over the junction energy barrier and into the base. For collector–base voltage VCB well below the collector–base breakdown voltage BVCBO, the collector current IC consists primarily of this electron flow. Since electrons arrive at and cross this energy barrier according to a random distribution, IC contains shot noise with noise power described by hinjci2 ¼ 2qICB, where B is the bandwidth over which noise power is measured [4]. Under the same conditions, the base current IB is composed primarily of holes injected from base to emitter and contains shot noise power similarly described by hinjbi2 ¼ 2qIBB. Although involving a common junction, each carrier type moves and crosses the E–B junction independently of the other. Further, the space–charge and neutral–base recombination components that contribute to both IC and IB are quite low in modern, low-defect SiGe HBTs and may typically be neglected except at very low temperatures. As a result, noise components injc and injb are almost entirely statistically uncorrelated [5]. Resistors are another source of thermal noise and all physically realized HBTs contain a resistance RB in series with the base, arising from both the nonzero lateral dimension of the pinched intrinsic base and from the extrinsic layers used to create electrical access and contact to this intrinsic region. The emitter polysilicon contributes a second parasitic series resistance RE. These resistances generate noise components that can be described using noise voltage sources with powers hjvnRBji2 ¼ 4kTRBB and hjvnREji2 ¼ 4kTREB [4]. Although a noise voltage on the emitter terminal adds to both VBE and VCE, IC in a HBT is quite insensitive to VCE and thus the indirect contribution of RE noise to IC via the creation of VCE noise can be neglected. As a result, RB and RE can be combined into a single noise voltage source hjvnRji2 ¼ 4kT(RB þ RE)B
4kTRB for a modern SiGe HBT in which RE  RB. The overall noise voltage contribution from the collector resistance RC is negligible since it is divided by the transistor voltage gain as seen from the vantage point of the other parasitic resistances. At sufficiently high VCB, electrons crossing the space–charge region from base to collector can acquire enough energy to excite a valence electron to the conduction band and create an electron–hole pair. Since the timing of an impact ionization event is statistical in nature, the resulting electrons contribute an additional component noise to IC while the holes add a correlated component to IB. This impact ionization noise is often neglected, but we will later demonstrate its effect on minimum noise figure (Fmin) and describe a device design that reduces this component with few trade-offs [6].

B I/I holes

E

Recombining carriers

B-E injected holes

C

E-B injected electrons I/I electrons

FIGURE 4.5.1 Schematic cross section of an idealized one-dimensional bipolar transistor illustrating the components of current flow which contribute to noise.

© 2006 by Taylor & Francis Group, LLC

4.5-441

Broadband Noise

Relating device-modeling parameters such as RB and device performance metrics such as fT to circuitlevel noise parameters Fmin, Rn, and Gopt is essential for designing and optimizing both the structure and layout of a HBT. One method for doing so is to represent each physical noise source as a component in a small-signal equivalent circuit model and to then use this model to determine each noise parameter [7]. Figure 4.5.2 illustrates a common-emitter equivalent circuit noise model that is simple yet works remarkably well for capturing the essential bias and frequency behaviors of the HBT noise parameters. Collector and base shot noise are represented by noise current sources, while base resistance thermal noise is represented by a noise voltage source. For completeness at high VCB, the impact ionization noise contribution to IC is represented by current source inii. A noisy two-port, such as a HBT, can be represented in an equivalent manner by two noise sources, generally correlated, connected to an ideal, noiseless two-port [8, 9]. Figure 4.5.3 illustrates two possible options for doing so. Representation 1 features noise voltage source vnA and noise current source inA connected to port 1, while Representation 2 drives ports 1 and 2 with noise current sources in1 and in2, respectively. Either representation creates a path for calculating the noise source correlation matrix elements, such as hjvnAji2, hjinAji2, hjvnA inA*ji2, and hjinA vnA*ji2 for Representation 1, in terms of the four noise parameters. Casting these same matrix elements in terms of the equivalent noise circuit model Y-parameters and noise sources, in turn, creates the bridge between the noise and device-modeling parameters [5, 7, 10]. Circuit designers turn first to the minimum noise figure Fmin in evaluating the noise performance of an RF technology. Following the above methodology and employing the equivalent noise circuit model of Figure 4.5.2, Fmin can be expressed in terms of the device-modeling parameters as [5, 7, 10–12]

Fmin

n ffi1þ þ b

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2  2IC f 1 n2 þ (RB þ RE ) 2 þ VT fT b b

(4:5:1)

which, after subtracting 1 from both sides and assuming that (RB þ RE)
RB, 1/b  1 and E–B junction ideality factor n
1, simplifies to sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2  2IC f 1 RB 2 þ Fmin  1 ffi VT fT b

(4:5:2)

This expression reveals exactly which device-modeling parameters are most critical to achieving low minimum noise figure: RB, fT, and b. The relative importance of each parameter is a function of frequency and of bias, which enters into the expression both explicitly as IC and implicitly in the bias dependencies of fT and, to a lesser extent, RB.

inii vnR

(M−1)ic’

Rb

B

vbe rbe injb

cbe

ccb

ic’ = gm vbe

C injc

vnA

Representation 1:

E

FIGURE 4.5.2 Small-signal equivalent circuit model for a bipolar transistor, including the dominant noise sources. Here, the total noise contributions of resistances RB and RE are lumped into RB (see text for additional discussion).

© 2006 by Taylor & Francis Group, LLC

inA

Noiseless HBT

in1

Representation 2: Noiseless HBT

in2

FIGURE 4.5.3 Two common representations of a noisy two-port as an ideal, noiseless two-port connected to two external noise sources.

4.5-442

The Silicon Heterostructure Handbook

Frequency sweeps are important for model assessment and evaluating a device against candidate applications as well as for providing a basis for interpolating or extrapolating to frequencies outside of the measured range. Equation (4.5.2) implies that the frequency dependence of Fmin divides into two regimes, illustrated in the linear-scale (non-dB) graph of (Fmin  1) versus frequency for a (0.12  4)  16 mm2 emitter-area SiGe HBT (200 GHz peak fT) plotted in Figure 4.5.4. For f 2/fT2 << 1/b (equivalently f 2  f 2T /b), frequency and fT drop out and Fmin simplifies to sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2IC Fmin  1 ffi RB VT b

(4:5:3)

In this low-frequency regime, Fmin depends only on RB, IC, and b, with fT not an explicit factor except in defining the boundaries of the regime. Low RB and high b are key to achieving low Fmin in this regime. The frequency dependence here is flat as long as IC is held constant. However, analysis (see below) shows that obtaining strictly optimized Fmin per frequency requires optimizing the bias for each frequency point, leading to Fmin decreasing as the square root of frequency. As frequency passes through the regime boundary, the behavior of Fmin shifts to sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  ffi 2 IC RB 2 Fmin  1 ffi f VT fT

(4:5:4)

In this higher frequency regime (f 2 >> f 2T /b), Fmin rises linearly with frequency, with a slope dependent on RB and fT and with b no longer an important concern. In contrast with the low-frequency regime, a value of IC that minimizes Fmin at one frequency also minimizes Fmin over all frequencies, improving ease of test and increasing the utility of such a sweep in evaluating the device. Low RB remains essential for achieving low Fmin as at lower frequency but high fT now becomes important as well. When designing a low-noise circuit, a circuit designer will typically target an application-specific frequency and examine the bias dependences of the noise parameters in order to select an optimal bias. Although bias current IC appears in Equation (4.5.2) directly, fT contains an implicit IC dependence as well, which may be expressed in reciprocal form as   1 VT (CEB þ CCB ) ¼ 2p þ tF fT IC

(4:5:5)

0.7

Fmin −1 (Linear)

0.6

AE = (0.12⫻4) ⫻ 16 µm2 IC = 20 mA, VCE = 1.2 V

0.5 0.4

f << fT

0.3

β

f >> fT

β

f·

2 VT

RB

IC f T2

Proportional to frequency

0.2 2IC

0.1 0.0

VTb 05

RB

10 15 20 Frequency (GHz)

Flat with frequency 25

30

FIGURE 4.5.4 Fmin  1 (linear scale) versus frequency for a sample 0.13-mm node SiGe HBT, illustrating the characteristic behavior in the low-frequency ( f 2 << fT2/b) and high-frequency ( f 2 >> fT2/b) regimes. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-443

Broadband Noise

where input capacitance (CEB þ CCB) sets the fT versus IC slope at low bias and tF determines the upper limit that would be approached by fT at high IC if there were no high-level injection or Kirk effect. This relationship may be substituted into Equation (4.5.2) to yield an expression containing fully explicit references to IC, which may then be minimized with respect to IC to yield a minimum value of Fmin across all currents (an RB versus IC dependence may be inserted as well for those devices in which RB varies significantly with bias over the current range of interest). At low frequencies in which f 2 << f 2T /b, Equation (4.5.3) suggests that Fmin has no minimum and can be made arbitrarily low simply by reducing IC. The equation contains a hidden dependency on fT, however, in the form of the frequency regime boundary defining where the equation is valid. As a result, Equation (4.5.3) cannot be used directly to explore the Fmin bias dependency at a given low frequency. Rather, this dependency must be determined from Equation (4.5.2) and Equation (4.5.5) minimization, with the final result simplified for the low-frequency regime. In this manner, Fmin is found to have a minimum at a bias of pffiffiffi opt: IC ¼ fVT (CEB þ CCB ) b

(4:5:6)

This minimum depends on the capacitances looking into the base (which determine low-current fT) and on b and is an increasing function of frequency. The actual minimum value of Fmin at this optimal bias is given by

opt: Fmin

pffiffiffi ffi f

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 8p2 RB (CEB þ CCB ) b1=2

(4:5:7)

Figure 4.5.5 illustrates this behavior using a graph of (Fmin  1) versus IC for a (0.2  19.2)  2 mm2 emitter-area device (120 GHz peak fT) at 10 and 15 GHz. Good noise performance in this regime requires low RB, a ubiquitous requirement, as well as high b and good low-current fT optimization (low input capacitance).

1.0 AE = (0.2
19.2)
2 µm2, VC = 1.5 V

Fmin −1 (Linear)

Opt. Fmin ≅

8π2 RB (CEB+CCB)

f.

1

b

2

15 GHz

0.5

10

opt. IC = f . VT (CEB+CCB) b 0.0 0

5

10

15

IC (mA)

FIGURE 4.5.5 Fmin  1 (linear scale) versus IC for a sample 0.18-mm node SiGe HBT illustrating the bias dependencies, lowest Fmin, and noise-optimal IC in the low frequency ( f 2 << fT2/b) regime. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-444

The Silicon Heterostructure Handbook

The bias dependence of Fmin at higher frequencies differs significantly as noted earlier. While the optimal current for lowest Fmin is frequency dependent at low frequencies, Fmin is optimized by a single value of IC for f 2 >> f 2T /b: opt: IC ¼

VT (CEB þ CCB ) tF

(4:5:8)

This bias point is a function of both the input capacitances and the current-independent fT transit time term. Indeed, this optimal IC corresponds to a value of fT equal to one half the limit approached by fT asymptotically at high IC neglecting high-level injection and the Kirk effect. Since peak fT can approach 85% of this limit in an actual SiGe HBT optimized for fT, the optimal noise bias can be well approximated by finding IC corresponding to half of peak fT. The Fmin value at this IC is an increasing function of frequency given by opt: Fmin ffi f  4p

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2RB (CEB þ CCB )t F

(4:5:9)

Figure 4.5.6 illustrates this behavior using a graph of (Fmin  1) versus IC for a (0.2  19.2)  2 mm2 emitter-area device (120 GHz peak fT) at 15 and 20 GHz. Good noise performance in this regime requires low RB and good optimization of both low- and high-current fT (low input capacitance and short transit time tF). b does not affect noise in the higher frequency regime. In each expression for Fmin, a parameter that scales with emitter length LE, such as IC or (CEB þ CCB), appears in product with RB, a parameter that typically scales inversely with LE in device layouts employing a base contact finger on each side of the emitter finger. As a result, Fmin itself is generally insensitive to LE. The analysis used to connect Fmin with device and modeling parameters also yields the remaining three noise parameters, which include the real and imaginary parts of the optimal source impedance as well as the noise resistance Rn. These parameters are key to designing an optimal source match.

1.0 AE = (0.2
19.2)
2 µm2, VC = 1.5 V 2RB (CEB+CCB)τF

Peak

fT

Fmin −1 (Linear)

Opt. Fmin ≅ f . 4p

1/(2ptF) 2

20 GHz 0.5 15 IC Opt. IC =

Vt(CEB+CCB) τF

0.0 0

5

10

15

IC (mA)

FIGURE 4.5.6 Fmin1 (linear scale) versus IC for a sample 0.18-mm node SiGe HBT illustrating the bias dependencies, lowest Fmin, and noise-optimal IC in the high-frequency ( f 2 >> fT2/b) regime. Inset connects noise-optimal IC directly to the fT versus IC behavior (see text for details). (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-445

Broadband Noise

Under the same assumptions used to simplify the expressions for Fmin, Rn may be approximated as Rn ffi VT =2IC þ RB

(4:5:10)

This is merely the sum of the small-signal impedance of the emitter–base diode (as seen from the emitter terminal and assuming IE
IC) and the base resistance. Rn is dominated by the former term at low currents and approaches RB as bias increases. Low values of RB, achieved through either process improvements or through layouts featuring long LE, can result in quite low noise resistances and thus to devices that are very tolerant of mismatch and thus more readily able to achieve circuit noise figures close to Fmin despite process variation. Shifting the real or resistive portion of the optimal source impedance toward the desired system impedance (typically 50 V) is the most challenging aspect of achieving a good match using integrated passives with values of Q that are low compared to discrete off-chip equivalents. This impedance component may, under a wide range of conditions, be simplified to Ropt ffi

2Rn ¼ Fmin  1



 VT 2 þ RB Fmin  1 2IC

(4:5:11)

While Fmin, and thus the second factor in this expression, does not change with emitter finger length LE, both terms in the first factor scale inversely with this dimension, allowing the designer to target a value of Ropt as close to 50 V as is possible within limits set by additional sizing constraints such as available chip area and power budget (impacted by IC).

4.5.3 Noise Performance Overview and Trends Continuous progress in both vertical and lateral scaling as well as innovations in processing and structure have led to a steady increase in the peak fT and fMAX for the highest performance HBT at each SiGe BiCMOS lithography node [2, 3, 13–17, 19–22]. These improvements in fMAX have, in large part, stemmed from the steady reduction in normalized base resistance RB illustrated in Figure 4.5.7 and

400

Raised base

Shared base

Norm. RB (Ω-µm)

350 Normalized by LE (units : Ω-µm)

300 250 200 150 100 50 0 0.0

0.1

0.2 0.3 0.4 Lithography node (µm)

0.5

0.6

FIGURE 4.5.7 RB (normalized to emitter finger length LE) versus technology node for IBM SiGe HBTs, illustrating the improvement with generation from lateral scaling and structural innovation. (From D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.5-446

The Silicon Heterostructure Handbook

achieved through advancements such as the raised extrinsic base structure described elsewhere in this book [2, 3]. The fT and RB trends have reaped parallel rewards in noise performance, driving Fmin down and GA up with each generation. The result is a selection of SiGe BiCMOS technologies available to the circuit designer at a variety of cost-performance points and enabling the feasible use of silicon technology to implement noise-sensitive applications at an increasingly broader range of frequencies. The HBT performance at a given technology node is a function not only of the node, but of deliberate trade-offs designed to satisfy application requirements. A high-performance technology may not only a include a flagship HBT optimized for fT and fMAX but also additional variants trading some peak fT for other properties such as higher breakdown voltage. Furthermore, an entire technology may be tuned for a market niche, such as high-volume consumer wireless applications for which low cost is paramount over maximum performance. Noise performance varies with choice of technology node and application optimization as well (as illustrated in Figure 4.5.8) [13]. The figure plots minimum Fmin (optimized over IC bias) versus frequency for a sampling of high-performance technologies at the 0.5-, 0.18-, and 0.13-mm nodes, together with a cost-reduced variant at the 0.18-mm node. A performance range selected from commercial data sheets for the current industry low-noise favorite, the GaAs PHEMT, is also indicated for reference. With a peak fT of 45 GHz and a normalized base resistance of 400 V mm, the 0.5-mm node maintains Fmin values below 1 dB out to 5 GHz and below 2 dB out to 10 GHz. This level of performance is suitable for receiver front-ends for cost-sensitive, high-volume applications including GSM, CDMA, and 802.11b, as evidenced by the commercial availability of SiGe parts for these markets. At the 0.18-mm node, vertical scaling increases the peak fT of performance-optimized HBTs to 120 GHz while lateral scaling and process optimization reduce normalized RB by 30%, to below 280 V mm. The scaling of both parameters has a direct impact on Fmin, which decreases by more than 1 dB at 10 GHz and by more than 2 dB at 26 GHz [14]. This improvement means that Fmin remains below 1 dB at 12 GHz and below 2 dB at 23 GHz. As a result, the 0.18-mm node can address higher application frequencies while providing for greater digital content integration due to improved digital logic performance and density.

5 AE (µm2) VC (V) _________________ (0.5
20)
2 2.0 (0.2
20)
2 1.5 (0.12
4)
16 1.2

Opt. Fmin (dB)

4

0.5 µm 45 GHz 0.18 µm 60 GHz

3

2

0.18 µm 120 GHz

1

0.13 µm 200 GHz GaAs PHEMT range

0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 4.5.8 HBT noise figure Fmin versus frequency for four SiGe BiCMOS technologies, including three highperformance ( fT emphasized) variants at the 0.5-, 0.18-, and 0.13-mm nodes as well as a cost-reduced (and slightly higher breakdown voltage) variant at the 0.18-mm node. (From D Greenberg. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-447

Although the 0.18-mm node HBT may be tuned for high fT, cellular telephony, and wireless networking applications below 6 GHz may prioritize cost over high-frequency capability, such markets can be addressed through cost-reduced technology variants, which eliminate process steps and retune the collector doping for an application-optimized combination of peak fT and breakdown voltage. Although these modifications reduce peak fT by shifting the onset of the Kirk effect to lower IC, values of fT, and thus of Fmin, at currents below the Kirk effect onset is impacted to a much lower extent. As a result, Fmin for the cost-reduced process suffers only minor degradation (0.1 dB at 5 GHz and 0.5 dB at 26 GHz) compared with that of the high-performance process and still represents a significant advance over the 0.5-mm node. The 0.13-mm node introduces a leap in noise performance, due not only to an increase in fT to over 200 GHz but to a further 68% reduction in normalized RB to 90 V mm as well [2, 3]. This large RB improvement results in part from lateral scaling but stems primarily from a shift to a new HBT design featuring a separate, raised polysilicon layer as the extrinsic base [2]. The use of a separate layer rather than a layer shared with the intrinsic base decouples RB and CCB and allows the introduction of much more extrinsic base doping without increasing CCB and losing gain. As a result, Fmin remains below 0.4 dB beyond 12 GHz and rises to only 1.3 dB at 26.5 GHz [16, 17]. This level of performance falls within the range established using the data sheets for GaAs PHEMTs currently on the commercial market, placing silicon within one generation of this benchmark. Guidelines drawn atop the 0.13 mm data in Figure 4.5.8 highlight the frequency dependencies expected from Equation (4.5.2) and illustrated in Figure 4.5.4. Fmin is flat with frequency in the lowfrequency regime and rises linearly with frequency once f 2 exceeds f 2T /b. The flat region seems absent from the 0.5- and 0.18-mm nodes, but this is due simply to the lower fT of these nodes, which positions the regime boundary below the measured frequency range. The bias dependencies of both Fmin and associated gain GA are critical inputs to the design process. Figure 4.5.9 and Figure 4.5.10 explore the 0.18- and 0.13-mm nodes, plotting both Fmin and GA versus IC in order to compare high-performance (hollow symbols) and cost-reduced (solid symbols) variants from this important perspective [14–17]. As described analytically in Equation (4.5.6) and Equation (4.5.8), Fmin is indeed minimized at a particular bias for any given frequency, with this bias a function of frequency at low frequencies and independent of frequency at higher frequencies. Even at the highest plotted frequency of 25 GHz, this optimal collector bias for lowest Fmin in the 0.18-mm node occurs at only 5 mA, which is a mere 8% of the peak fT current for the illustrated device. This result emphasizes that noise performance is tied to low-current fT and not to peak values. Although Fmin is minimized at a unique current, associated gain rises monotonically with current. This behavior requires that the designer selects an optimal balance between achieving lowest Fmin and higher GA based on the requirements of the application. Reducing cost in the 0.18-mm node increases Fmin somewhat, with this degradation an increasing function of frequency. Since low-current fT is similar between the process variants, most of this difference is due to RB, which benefits from a more complex, self-aligned structure in the highperformance variant. Despite the modestly increased Fmin in the cost-reduced variant, however, GA is actually improved as the result of the reduced collector–base capacitance CCB that arises from reducing the collector doping to achieve higher breakdown voltage. Measuring noise at frequencies beyond 26.5 GHz is challenging and the means to do so may not yet be available on many test benches. The excellent correlation in the HBT between data and analytical prediction for Fmin versus frequency provides a means for accurate extrapolation of the data to frequencies beyond the testing boundaries, however, and thus a means for helping the designer evaluate the suitability of new technologies for emerging applications. As an example, Figure 4.5.11 plots (Fmin  1) versus frequency on a linear scale for a 0.13-mm HBT, with the axis taken out to 80 GHz and with data plotted out to 26 GHz. Fmin rises linearity with frequency above 8 GHz and is well-fit by a line using the least-squares method. The fit line may then be extended with reasonable accuracy for at least 1 to 2 octaves beyond the measured data and the resulting Fmin values expressed in dB form for more familiar reference. This method predicts Fmin values for the 0.13-mm HBT of 3.1 and 3.8 dB at 60

© 2006 by Taylor & Francis Group, LLC

4.5-448

The Silicon Heterostructure Handbook

4 Hollow: high-perf (HP) Solid: cost-reduced (CR) 3

Fmin (dB)

25 GHz 2 15 1

10

0.18 µm SiGe BiCMOS AE = (0.18
20)
2

5

VCE = 1.5/2 V (HP/CR)

0 0

5

10 IC (mA)

15

20

25 5 GHz 20

GA (dB)

10 15 15 10

25

5

0 0

5

10 IC (mA)

15

20

FIGURE 4.5.9 HBT noise figure Fmin and associated gain GA versus IC at 5, 10, 15, and 26 GHz for highperformance and cost-reduced variants of 0.18-mm IBM SiGe BiCMOS technology (AE ¼ 0.18  20  2 mm2). (From DR Greenberg, D Ahlgren, G Freeman, S Subbanna, V Radisic, DS Harvey, C Webster, and L Larson. Digest IEEE MTT-S International Microwave Symposium, Boston, 2000, pp. 9–12; D Greenberg, S Sweeney, C LaMothe, K Jenkins, D Friedman, B Martin Jr, G Freeman, D Ahlgren, S Subbanna, and A Joseph. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 495–498. With permission.)

and 77 GHz, respectively [16, 17]. Such levels of performance are suitable for applications such as 60 GHz wireless LAN and 77 GHz automotive radar, opening a high-frequency regime to silicon that was once the exclusive domain of III–V devices. Recent circuit results verifying these noise figure values appear later in the chapter [40]. It is significantly more difficult to achieve noise figures close to Fmin after integrating a transistor into a circuit such as an LNA than when measuring the discrete device on the test bench. Part of this difficulty stems from the need for high Q passives to achieve the required source impedance match, especially when this match differs significantly from 50 V and resides near the outer edges of the Smith chart.

© 2006 by Taylor & Francis Group, LLC

4.5-449

Broadband Noise

0.13 µm SiGe BiCMOS AE = (0.12
4)
16 µm2 VCE = 1.2 V

2.5 26 GHz

Fmin (dB)

2.0 1.5

15

1.0 0.5 10 0.0 0

5

10

15

20

25

30

25

30

IC (mA) 18 16

10 GHz

14 15

GA (dB)

12 10

26

8 6 4 2 0 0

5

10

15 IC (mA)

20

FIGURE 4.5.10 Noise figure Fmin and associated gain GA versus IC at 10, 15, and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12  4  16 mm2). (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

The challenge is compounded by process variation, which introduces a random degree of mismatch into each sample. The impact of this design challenge is observed most readily when designing with FETs, which suffer from relatively high noise resistance and from largely capacitive optimum source impedances with very high real components. The HBT, however, fares much better in this regard, leading to LNA circuits that approach the measured device Fmin more closely. Figure 4.5.12 and Figure 4.5.13 illustrate the key matching parameters for a (0.2  4)  16 mm2 HBT, plotting Rn versus IC and showing Gopt in Smith chart form at 10, 15, 20, and 26 GHz [16, 17]. The very low RB at this technology node leads to correspondingly low Rn, an order of magnitude lower than observed in FETs at the same node. At the same time, Gopt remains comfortably away from the Smith chart edge, with the real portion of the optimum source impedance remaining within a factor of 5 of 50 V at the chosen device size. In practice, the LE scaling required to design a value of Ropt close to 50 V at a target application frequency is typically well within feasible limits for the SiGe HBT.

© 2006 by Taylor & Francis Group, LLC

4.5-450

The Silicon Heterostructure Handbook

1.6 0.13 µm SiGe BiCMOS

[Fmin −1]

1.4

Est. Fmin = 3.8 dB

AE = (0.12
4)
16 µm2

1.2

IC = 20 mA

1.0

VCE = 1.2 V

3.1 dB

0.8 0.6 Least-squares fit

0.4 0.2 0.0 0

10

20

30 40 50 Frequency (GHz)

60

70

80

FIGURE 4.5.11 Fmin  1 (linear scale) versus frequency for a 0.13-mm IBM SiGe HBT illustrating a means for accurate extrapolation beyond the measured data and indicating Fmin estimates of 3.1 and 3.8 dB at 60 and 77 GHz, respectively. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

Noise resistance, Rn (Ω)

5 4

10 GHz

3

26

0.13 µm SiGe BiCMOS AE = (0.12
4)
16 µm2 VCE = 1.2 V

2 1 0 0

5

10

15 IC (mA)

20

25

30

FIGURE 4.5.12 Noise resistance Rn versus IC at 10 and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12  4  16 mm2). (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

4.5.4 Device Optimization for Low Noise SiGe HBT technologies, designed to suit the widest possible range of applications, are already achieving outstanding levels of noise performance suitable for use to beyond 60 GHz. Still, the relationships between the noise and device parameters explored in Section 4.5.2 suggest the means for optimizing noise performance even further.

© 2006 by Taylor & Francis Group, LLC

4.5-451

Broadband Noise

1.0 0.5

10 GHz

2.0

0.2

5.0

26

0.2

0.5

1.0

2.0

5.0

−5.0

−0.2

−2.0

−0.5 −1.0

FIGURE 4.5.13 Gopt bias traces on a Smith chart at 10 and 26 GHz for a 0.13-mm IBM SiGe HBT (noise-optimized layout with AE ¼ 0.12  4  16 mm2). Position away from chart edge suggests relatively easy matching to 50 V. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

The use conditions for a modern HBT typically fall within the domain of Equation (4.5.9), which relates bias-optimized Fmin to the product of three parameters under the direct control of the device designer. At any given frequency, this Fmin can be improved by reducing RB, (CEB þ CCB) or tF, with each playing an equal role. The impact of RB on Fmin may be isolated empirically by varying the fabrication process so as to alter RB while keeping all other design parameters fixed. Figure 4.5.14 plots Fmin versus frequency for two variants of a 0.13-mm process employing a raised extrinsic base to decouple the trade-off between RB and CCB. Compared with baseline process no. 1, process no. 2 introduces significantly more extrinsic base doping and reduces RB by 40% from 140 to 85 V mm [2, 3]. This lone process improvement drops Fmin by an average of 0.3 to 0.4 dB at frequencies above 8 GHz (below which Fmin becomes too low for clean measurement) [16, 17]. Fmin may also be improved through the independent approach of reducing the several components of transit time, which limit f T at the optimal IC for lowest noise. Since Fmin occurs well below peak f T in a HBT, design choices aimed at peak f T may be traded for improved low-current f T instead. The SiGe composition profile in the base is one such design-tuning knob. In a graded-base HBT design optimized for operation at the higher currents required to reach peak f T, significant SiGe mole fraction is maintained not only through the neutral base, but into the base–collector space–charge region as well, where the composition transitions back to silicon. This positions the barrier from the steep profile retrograde within the space–charge region where it causes minimal carrier pileup and thus minimal performance impact at high IC. Although the total SiGe budget is limited by the maximum strain that can be tolerated in a base of given thickness, a noise-optimized HBT design, freed of the need to operate at high IC, can partition this budget differently and shift SiGe mole fraction from the collector side of the base toward the emitter [18]. As illustrated in the Figure 4.5.15 (inset), this creates a narrower profile, positioning the retrograde barrier closer to the neutral base but allowing for either a larger emitter–base heterojunction or, in the case of a graded-profile design, for a steeper SiGe ramp. A larger emitter–

© 2006 by Taylor & Francis Group, LLC

4.5-452

The Silicon Heterostructure Handbook

2.0 AE = (0.12
4)
16 µm2 VC = 1.2 V Fmin at opt. IC (dB)

1.5 Process #1: Baseline RB

1.0

0.5

Process #2: 40% RB Reduction

0.0 0

5

10 15 20 Frequency (GHz)

25

30

FIGURE 4.5.14 HBT noise figure Fmin (optimized over IC) versus frequency for both baseline and low-RB variants of a 0.13-mm IBM SiGe device (noise-optimized layout with AE ¼ 0.12  4  16 mm2), indicating the improvement possible from a 40% reduction in base resistance. (From DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790; D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. With permission.)

1.2

SiGe%

1.4

Control

NFmin (dB)

1.0 0.8

E-B B-C Vertical Depth

0.6 Optimized 0.4 AE = 0.5
20
2 µm2

0.2

f = 2GHz VCB = 0 V 0.0 1.0

2.0

5.0 IC (mA)

10

20

FIGURE 4.5.15 Fmin versus IC at 2 GHz comparing a graded-base SiGe HBT (AE ¼ 0.5  20  2 mm2) with control SiGe base profile with a noise-optimized device in which the SiGe base profile has been modified as per the inset. (From G Niu, S Zhang, JD Cressler, AJ Joseph, JS Fairbanks, LE Larson, CS Webster, WE Ansley, and DL Harame. IEEE Transactions on Electron Devices 47:2037–2044, 2000. With permission.)

base heterojunction can be leveraged to increase b (reducing Fmin in the low-frequency regime) or to increase intrinsic base doping and thus to decrease RB (reducing Fmin at all frequencies). A steeper SiGe ramp creates a strong quasielectric field for electrons in the base, increasing their speed and decreasing tF . Low-noise profile optimization has indeed been demonstrated. Figure 4.5.15 compares Fmin versus IC at 2 GHz for a standard high-fT (45 GHz) 0.5-mm device with a variant containing a noise-optimized graded SiGe base profile. The optimized profile reduces Fmin by as much as 0.3 dB. The data analysis presented to this point has ignored the effects of impact ionization, a source of noise included in the equivalent circuit model of Figure 4.5.2. This simplification is valid as long as the

© 2006 by Taylor & Francis Group, LLC

4.5-453

Broadband Noise

2.5 1.75 V

2.0

0V

Fmin (dB)

1.5 V

0.5 V

1.25 V

1.5

1.0 15 GHz AE = 0.12
20 µm2

0.5

): VCB = 0, 0.5, 0.75, 1, 1.25, 1.5 and 1.75 V ): VCB = 0, 0.5, 1, 1.25, 1.5, 1.75 and 2 V

HP ( MP ( 0.0 0

1

2

3

4 IC (mA)

5

6

7

8

FIGURE 4.5.16 Fmin versus IC at 15 GHz for two 0.13-mm IBM SiGe HBT devices comparing a high-fT baseline device and a modified-collector variant with reduced impact ionization noise. (From DR Greenberg, S Sweeney, G Freeman, and D Ahlgren. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 113– 116. With permission.)

collector–base and collector–emitter voltages remain well below the respective two-terminal breakdown voltages BVCBO and BVCEO. As breakdown is approached, however, impact ionization can begin to contribute significantly to the noise figure. One goal in optimizing a HBT design for low noise is to suppress this phenomenon and its impact on noise. Reducing the collector doping is one approach to achieving this goal. As discussed in Section 4.5.3, lowering the collector doping decreases peak fT by shifting the onset of the Kirk effect toward lower IC yet has little impact on fT or Fmin prior to this onset. The fT for a device optimized for the least impact ionization noise should therefore peak at a value of IC at or just beyond the bias for best Fmin. Such a design minimizes the collector doping and maximizes the breakdown voltage [6]. Figure 4.5.16 plots Fmin versus IC for both a high-fT (200 GHz) HBT (with a BVCEO of 2 V) and a medium-performance (collector-doping-reduced) variant in the 0.13-mm node, comparing the noise performance as VCB is stepped from 0 to 2 V (i.e., VCE from 0.8 to 2.8 V). A reduced collector doping does create a large VCB dependence to the Kirk effect, requiring a VCB greater than 0.5 V (VCE >1.3 V) to position peak fT current beyond the optimum Fmin bias point. At larger VCB, however, Fmin for the medium-performance device maintains its value with further VCB increases while Fmin in the high-fT device degrades significantly from impact ionization, particularly at higher IC. At a VCB value of 1 V, VCE is approximately 1.8 V and thus below BVCEO. Yet, noise in the highfT HBT has already degraded measurably. By the time VCB reaches 1.75 V, impact ionization in the high-fT HBT is severe and minimum Fmin has increased by over 0.75 dB. The modified device shows no such excess noise contribution at these voltages, however, and actually enjoys improved associated gain from the reduction in CCB resulting from the lower collector doping. Thus, the high-breakdown HBT variant offered in the device libraries of many SiGe technologies, while not providing the highest peak fT, can actually be the preferred choice for low-noise operation at typical supply voltages.

4.5.5 Circuit Performance Device performance on the test bench does not always translate into performance in an integrated circuit. For example, LNA performance can be limited by the performance of available inductors which, due to their finite Q, may not always be able to achieve a noise-optimal match and which contribute noise of their own. The matching characteristics of the SiGe HBT, however, help ease good LNA design

© 2006 by Taylor & Francis Group, LLC

4.5-454

The Silicon Heterostructure Handbook

compared with those of FETs. HBT LNA noise figures, while still higher than those of the discrete device, can nevertheless come quite close. Figure 4.5.17 surveys both noise figure and gain for published or commercially available LNAs built in a variety of technology nodes ranging from 0.5 to 0.13 mm [22–39]. The results at any given node vary greatly due to differences in design priorities and the learning curve associated with design in newly available technologies. However, the bounding limits approach discrete device test bench values and demonstrate the levels of performance possible in silicon over a wide range of frequencies. At the high end of the frequency scale, an LNA noise figure of 3.8 dB has been achieved at 60 GHz, with a corresponding gain of 14.5 dB (including the impact of the bondpads) [40]. This noise figure falls within 0.7 dB of the device Fmin estimated in Figure 4.5.11. A more complete characterization of this result is shown in Figure 4.5.18, which plots the noise figure and gain as a function of frequency and presents a microphotograph of the actual measured chip.

30 25

4 3 Technology Node(µm): 0.13 0.2 0.25 0.35 0.5

2 1 0 10

20

30 40 50 Frequency (GHz)

60

70

Assoc. Gain,GA (dB)

Min. Noise Figure, Fmin (dB)

5

20 15

Technology Node(µm): 0.13 0.2 0.25 0.35 0.5

10 5 0 10

20

30 40 50 60 Frequency (GHz)

70

FIGURE 4.5.17 Noise figure and gain versus frequency for a sampling of published SiGe LNA data, illustrating the attained performance ranges for the 0.5- to 0.13-mm technology nodes. (From Refs. [22–39]. With permission.)

20

10 0.13 µm SiGe BiCMOS 60 GHz LNA

15

6 10 4

Gain (dB)

Noise Figure (dB)

8

5

2

0

0 59

60

61 62 Frequency (GHz)

63

FIGURE 4.5.18 Noise figure and gain versus frequency for a fully integrated 60 GHz LNA (complete chip, including pad parasitics) built in IBM’s 0.13-mm SiGe technology and demonstrating a sub-4 dB noise figure consistent with discrete device data extrapolation. (From S Reynolds, B Floyd, U Pfeiffer, and T Zwick. Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp. 442–443. With permission.)

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-455

4.5.6 Summary Each generation of SiGe HBT technology has leveraged scaling, process, and layout innovations to improve low-noise performance. The key contributors to these advances have been the increase in fT and decrease in RB at low to moderate current levels, factors which dovetail naturally with the drive to increase fMAX. As a result, the 0.5-mm generation has been able to penetrate the wireless telephony and networking markets in the 0.8 to 5.8 GHz bands while the latest 0.13-mm generation has demonstrated sub-4 dB performance in actual circuits in the 60 to 77 GHz regime targeted by emerging multimedia and automotive applications. Designers working on noise-sensitive systems have a choice of technology nodes with which to balance cost against performance and integration density. At the same time, the nature of the HBT as a vertical, bulk transistor has kept the device amenable to the detailed analysis and accurate modeling that has helped speed time to market through a strong record of first-pass design success. A variety of ideas have been proposed for optimizing noise still further, many of which will undoubtedly find their way into the technology as SiGe spreads out into the many untapped market niches.

Acknowledgments This chapter would not have been possible without the outstanding and invaluable contributions toward both test and hardware development by S. Sweeney, S. Parker, G. Freeman, D. Ahlgren, A. Joseph, S. St. Onge, P. Cottrell, J. Dunn, D. Harame, and each of the world-class members of IBM’s SiGe development and enablement teams.

References 1. CE Shannon. A mathematical theory of communication. Bell System Technical Journal 27:379–423, 623–656, 1948. 2. B Jagannathan, M Khater, F Pagette, J-S Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, S-J Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, and S Subbanna. Self-aligned SiGe NPN transistors with 285 GHz fMAX and 207 GHz fT in a manufacturable technology. IEEE Electron Device Letters 23:258–260, 2002. 3. A Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman Jr, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTS — expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–181. 4. W Shockley, JA Copeland, and RP James. Quantum Theory of Atoms, Molecules and the Solid State. New York, NY: Academic Press, 1966, pp. 537–563. 5. G Niu, JD Cressler, S Zhang, WE Ansley, CS Webster, and DL Harame. A unified approach to RF and microwave noise parameter modeling in bipolar transistors. IEEE Transactions on Electron Devices 48:2568–2574, 2001. 6. DR Greenberg, S Sweeney, G Freeman, and D Ahlgren. Low-noise performance near BVCEO in a 200 GHz SiGe technology at different collector design points. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 113–116. 7. SP Voinigescu, MC Maliepaard, JL Showell, GE Babcock, D Marchesan, M Schroter, P Schvan, and DL Harame. A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE Journal of Solid-State Circuits 32:1430–1439, 1997. 8. H Rothe and W Dahlke. Theory of noisy fourpoles. Proceedings of the Institute of Radio Engineers 44:811–818, 1956. 9. HA Haus, WR Atkinson, WH Fonger, WW Mcleod, GM Branch, WA Harris, EK Stodola, WB Davenport Jr, SW Harrison, and TE Talpey. Representation of noise in linear twoports. Proceedings of the Institute of Radio Engineers 48:69–74, 1960.

© 2006 by Taylor & Francis Group, LLC

4.5-456

The Silicon Heterostructure Handbook

10. O Shana’a, I Linscott, and L Tyler. Frequency-scalable SiGe bipolar RF front-end design. IEEE Journal of Solid-State Circuits 36:888–895, 2001. 11. G Niu, WE Ansley, S Zhang, JD Cressler, CS Webster, and RA Groves. Noise parameter optimization of UHV/CVD SiGe HBT’s for RF and microwave applications. IEEE Transactions on Electron Devices 46:1589–1598, 1999. 12. S Zhang, G Niu, JD Cressler, AJ Joseph, G Freeman, and DL Harame. The effects of geometric scaling on the frequency response and noise performance of SiGe HBTs. IEEE Transactions on Electron Devices 49:429–435, 2002. 13. D Greenberg. SiGe HBT Noise Performance. Workshop: High frequency noise in advanced siliconbased devices. IEEE MTT-S International Microwave Symposium, Fort Worth, 2004. 14. DR Greenberg, D Ahlgren, G Freeman, S Subbanna, V Radisic, DS Harvey, C Webster, and L Larson. HBT low noise performance in a 0.18 mm SiGe BiCMOS technology. Digest IEEE MTT-S International Microwave Symposium, Boston, 2000, pp. 9–12. 15. D Greenberg, S Sweeney, C LaMothe, K Jenkins, D Friedman, B Martin Jr, G Freeman, D Ahlgren, S Subbanna, and A Joseph. Noise performance and considerations for integrated RF/analog/mixedsignal design in a high-performance SiGe BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp. 495–498. 16. DR Greenberg, B Jagannathan, S Sweeney, G Freeman, and D Ahlgren. Noise performance of a low base resistance 200 GHz SiGe technology. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 787–790. 17. D Greenberg, S Sweeney, B Jagannathan, G Freeman, and D Ahlgren. Noise performance scaling in high-speed silicon RF technologies. Proceedings of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Grainau, 2003. 18. G Niu, S Zhang, JD Cressler, AJ Joseph, JS Fairbanks, LE Larson, CS Webster, WE Ansley, and DL Harame. Noise modeling and SiGe profile design trade-offs for RF applications. IEEE Transactions on Electron Devices 47:2037–2044, 2000. 19. B Mheen, D Suh, HS Kim, S-Y Lee, CW Park, SH Kim, K-H Shim, and J-Y Kang. RF performance trade-offs of SiGe HBT fabricated by reduced pressure chemical vapor deposition. Digest IEEE MTT-S International Microwave Symposium, Seattle, 2002, pp. 413–416. 20. FS Johnson, J Ai, S Dunn, B El Kareh, J Erdeljac, S John, K Benaissa, A Bellaour, B Benna, L Hodgson, G Hoffleisch, L Hutter, M Jaumann, R Jumpertz, M Mercer, M Nair, J Seitchik, C Shen, M Schiekofer, T Scharnagl, K Schimpf, U Schulz, B Staufer, L Stroth, D Tatman, M Thompson, B Williams, and K Violette. A highly manufacturable 0.25 mm RF technology utilizing a unique SiGe integration. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 56–59. 21. JG Tartarin, R Plana, M Borgarino, H Lafontaine, M Regis, O Llopis, and S Kovacic. Noise properties in SiGe BiCMOS devices. IEEE International Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications, Piscataway, 1999, pp. 131–136. 22. J Bock, TF Meister, H Knapp, D Zoschg, H Schafer, K Aufinger, M Wurzer, S Boguth, M Franosch, R Stengl, R Schreiter, M Rest, and L Treitinger. SiGe bipolar technology for mixed digital and analogue RF applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2000, pp. 745–748. 23. G Schuppener, T Harada, and Y Li. A 23 GHz low-noise amplifier in SiGe heterojunction bipolar technology. Digest IEEE Radio Frequency Integrated Circuits Symposium, Phoenix, 2001, pp. 177–180. 24. T Nakatani, J Itoh, I Imanishi, and O Ishikawa. A wide dynamic range switched-LNA in SiGe BiCMOS. Digest IEEE MTT-S International Microwave Symposium, Phoenix, 2001, pp. 281–284. 25. M Kamat, P Ye, Y He, B Agarwal, P Good, S Lloyd, and A Loke. High performance low current CDMA receiver front end using 0.18 mm SiGe BiCMOS. Digest IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 23–26. 26. A Schmidt and S Catala. A universal dual band LNA implementation in SiGe technology for wireless applications. IEEE Journal of Solid-State Circuits 36:1127–1131, 2001.

© 2006 by Taylor & Francis Group, LLC

Broadband Noise

4.5-457

27. J Lee, G Lee, G Niu, JD Cressler, JH Kim, JC Lee, B Lee, and NY Kim. The design of SiGe HBT LNA for IMT-2000 mobile application. Digest IEEE MTT-S International Microwave Symposium, Seattle, 2002, pp. 1261–1264. 28. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. Digest IEEE GaAs Integrated Circuit Symposium, San Diego, 2003, pp. 183–186. 29. DYC Lie, J Kennedy, D Livezey, B Yang, T Robinson, N Sornin, T Beukema, LE Larson, A Senior, C Saint, J Blonski, N Swanberg, P Pawlowski, D Gonya, X Yuan, and H Zamat. A direct conversion W-CDMA front-end SiGe receiver chip. Digest IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 31–34. 30. G Zhang, A Dengi, and LR Carley. Automatic synthesis of a 2.1 GHz SiGe low noise amplifier. IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 125–128. 31. P-W Lee, H-W Chiu, T-L Hsieh, C-H Shen, G-W Huang, and S-S Lu. A SiGe low noise amplifier for 2.4/5.2/5.7GHz WLAN applications. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2003, pp. 349, 364–365. 32. P Chevalier, F De Pestel, H Ziad, M Fatkhoutdinov, J Ackaert, P Coppens, J Craninckx, S Guncer, A Pontioglu, P Tasci, F Yayil, BS Ergun, AI Kurhan, E Vestiel, E De Backer, J-L Loheac, and M Tack. An industrial 0.35 mm SiGe BiCMOS technology for 5 GHz WLAN featuring an improved selective epitaxial growth process. International Symposium on Electron Devices for Microwave and Optoelectronic Applications, Vienna, 2001, pp. 175–180. 33. B Foley, P Murphy, and A Murphy. A monolithic SiGe 5 GHz low noise amplifier and tuneable image-reject filter for wireless LAN applications. IEEE High Frequency Postgraduate Colloquium, Dublin, 2000, pp. 26–31. 34. E Imbs, I Telliez, S Detout, and Y Imbs. A low-cost-packaged 4.9–6 GHz LNA for WLAN applications. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1569–1572. 35. B Banerjee, B Matinpour, C-H Lee, S Venkataraman, S Chakraborty, and J Laskar. Development of IEEE802.11a WLAN LNA in silicon-based processes. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1573–1576. 36. J Sadowy, I Telliez, J Graffeuil, E Tournier, L Escotte, and R Plana. Low noise, high linearity, wide bandwidth amplifier using a 35 mm SiGe BiCMOS for WLAN applications. Digest IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 217–220. 37. S Chakraborty, SK Reynolds, H Ainspan, and J Laskar. Development of 5.8 GHz SiGe BiCMOS direct conversion receivers. Digest IEEE MTT-S International Microwave Symposium, Philadelphia, 2003, pp. 1551–1554. 38. J Bock, H Schafer, H Knapp, D Zoschg, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, R Stengl, and TF Meister. Sub 5 ps SiGe bipolar technology. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 763–766. 39. Y Li, M Bao, M Ferndahl, and A Cathelin. 23 GHz front-end circuits in SiGe BiCMOS technology. Digest IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 99–102. 40. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz receiver circuits in SiGe bipolar technology. Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp. 442–443.

© 2006 by Taylor & Francis Group, LLC

4.6 Microscopic Noise Simulation 4.6.1 4.6.2

Introduction............................................................... 4.6-459 Noise Source Density and Noise Propagation........ 4.6-460 Noise Source Density . Scalar and Vector Green’s Functions . Green’s Function Evaluation and Boundary Conditions . Noise Concentration

4.6.3 4.6.4

Macroscopic Input Noise . Macroscopic and Microscopic Connections . Input Noise Voltage and Current . NFmin, Yopt, and Rn

Guofu Niu Auburn University

Input Voltage and Current Noise Concentrations .......................................................... 4.6-464 A SiGe HBT Example ............................................... 4.6-465

4.6.5

Summary .................................................................... 4.6-471

4.6.1 Introduction The major noise sources in a bipolar transistor are the base resistance thermal noise, or Johnson noise, the base current shot noise, and the collector current shot noise. The base resistance thermal noise is typically described by a noise voltage with a spectral density of 4kTR, and the shot noise is described by a spectral density of 2qI, with I as the DC base current or collector current. These descriptions are based on macroscopic views. The standard derivation of the magic 2qI shot noise assumes a Poisson stream of an elementary charge q. These charges need to overcome a potential barrier, and thus flow in a completely uncorrelated manner. In a bipolar transistor, the base current shot noise 2qIB results from the flow of base majority holes across the EB junction potential barrier. The reason that IB appears in the base shot noise is that the amount of hole current overcoming the EB barrier is determined by the minority hole current in the emitter, IB. Similarly, the collector current shot noise results from the flow of emitter majority electrons over the EB junction potential barrier, and has a spectral density of 2qIC. Surprisingly, however, both the 4kTR resistor noise and the 2qI shot noise can be attributed to the same physical origin at the microscopic level — the Brownian motion of electrons and holes, also referred to as diffusion noise as the same mechanism is responsible for diffusion. The thermal motion of carriers gives rise to fluctuations of carrier velocities, and hence fluctuations of current densities. The density of such current density fluctuation is 4q2nDn according to microscopic treatment of carrier motion [1, 2]. The current density fluctuation at each location propagates toward device terminals, giving rise to device terminal voltage or current noise. The problem of noise analysis is now equivalent to solving the transfer functions of noise propagation at each location and summing over the whole device space. These transfer functions can be solved analytically for ideal transistor operation with simplified boundary conditions, or numerically for arbitrary device structures, and the latter process is referred to as microscopic noise simulation. 4.6-459 © 2006 by Taylor & Francis Group, LLC

4.6-460

The Silicon Heterostructure Handbook

Various mathematical methods have been developed, all based on the impedance field method developed by Schockley and his colleagues [1] and its various generalizations. A very satisfying early application is the successful derivation of the 4kTR Johnson noise, a macroscopic model result, from the microscopic 4q2nDn noise source density. The impedance field approach is equivalent to the Green’s function based approaches [3], which can be rigorously derived from the general master equation. Efficient numerical algorithms have been developed, which enabled the recent implementation of noise analysis in commercial device simulators, e.g., DESSIS from ISE and Taurus from TMA.

4.6.2 Noise Source Density and Noise Propagation The mathematical development of various microscopic noise simulation methods has been well treated in Refs. [4, 5]. We will focus on the aspects of using noise simulations instead. The key to successful application of microscopic noise simulation is to understand the following three concepts: 1. Noise source density, which is a measure of the local current density noise due to velocity fluctuation. This is a scalar, like the electron density, and is a function of position. 2. Vector noise transfer function, or vector Green’s function, which is the gradient of the scalar Green’s function. This is a vector like the electric field. 3. Scalar Green’s function, or scalar noise transfer function, is a ratio of the transistor terminal noise produced for a unity noise current injection into a location. All the three quantities are functions of location, like electron density n, electric field E, and potential c. We now derive the collector shot noise using ‘‘microscopic’’ theory as an example to illustrate the above concepts [6]. Like any other analytical theories, simplifying assumptions are inevitable to arrive at manageable solutions in our derivation. Many such assumptions can be removed using numerical noise simulation. We will consider one-dimensional, and neglect carrier recombination, which will necessitate including frequency in the small signal diffusion equation, in order to minimize complexity.

Noise Source Density Consider a one-dimensional semiconductor bar as shown in Figure 4.6.1. For purpose of analysis, we divide the bar into small sections. The current density is related to carrier concentration and velocity as Jn ¼
qnv,

(4:6:1)

where n is electron concentration and v is the net velocity. Because of velocity fluctuation, there is random charge transport within an incremental section. This can be equivalently described by

A

∆x x + ∆x

x

∆Jn

FIGURE 4.6.1 Equivalent circuit representation of the current density noise due to velocity fluctuations within an incremental section from x to x þ Dx.

© 2006 by Taylor & Francis Group, LLC

4.6-461

Microscopic Noise Simulation

placing a noise current source across the incremental section. A fundamental result of velocity fluctuation is that the spectrum density of the DJn fluctuation for an incremental section between x and x þ Dx is given by SDJn ¼ Kn

1 : ADx

(4:6:2)

The current density fluctuation increases with decreasing ADx, the volume of the incremental section. Here A is the cross-sectional area of the one-dimensional bar, Dx is the length of the incremental section in question, and Kn is the electron noise source density [1, 2]: Kn ¼ 4q2 nDn ,

(4:6:3)

where n is electron concentration and Dn is electron diffusivity. Equation (4.6.2) and Equation (4.6.3) are physically plausible, and consistent with our physical intuitions that statistical fluctuation increases with decreasing size, increasing diffusivity as well as increasing electron concentration. Now consider the neutral base of an ideal one-dimensional bipolar transistor. The purpose is to solve for the collector current noise resulting from current density fluctuations within all the incremental sections when the base and collector are AC shorted (as shown in Figure 4.6.2(a)).

Scalar and Vector Green’s Functions The first step is to consider the amount of JC noise resulting from the current density noise within (x, x þ Dx), DJn, the spectral density of which is described by Equation (4.6.2). This is equivalent to injecting DJn at x and extracting DJn at x þ Dx (as shown in Figure 4.6.2(b)). If we define the current gain G as the ratio of the DJn observed at Wb to a current excitation at x alone, the net DJn (Wb) can be written as DJn (Wb ) ¼ DJn G(x)
DJn G(x þ Dx) ¼
DJn G 0 Dx

(4:6:4)

Neutral base ∆x x

∆JC x + ∆x

0

Wb ∆Jn (a) Neutral base

∆Jn(0)

∆Jn (Wb)

∆x x + ∆x

x 0

∆Jn

∆Jn

Wb

(b)

FIGURE 4.6.2 (a) Equivalent circuit for the the noise propagation from an incremental section (x , x þ Dx) toward the collector. (b) An alternative equivalent circuit for the noise propagation from an incremental section (x , x þ Dx) toward the collector.

© 2006 by Taylor & Francis Group, LLC

4.6-462

The Silicon Heterostructure Handbook

where G 0  dG(x)/dx is the vector Green’s function. G(x) is the scalar Green’s function. The collector current density noise is essentially DJn(Wb). Thus 2

DSJC ¼ SDJn jG 0 j Dx 2 :

(4:6:5)

Similarly, one can solve for the open-circuit noise voltage with an open-circuit boundary condition. The G(x) will then be the ratio of the voltage output at x ¼ Wb to a current excitation at x , an impedance. The vector defined by G 0 ¼ dG(x)/dx has the meaning of a field defined using the gradient of an impedance function, and is thus called impedance field. The open-circuit voltage and short-circuit current noises are equivalent to each other, similar to the equivalence between Norton and Thevenin equivalent circuits.

Green’s Function Evaluation and Boundary Conditions To evaluate G(x), we evaluate the amount of DJn (Wb) produced by an excitation DJn at x alone (as shown in Figure 4.6.3). At the neutral base boundaries, we assume that the quasi-Fermi levels remain fixed at the levels set by the applied voltages, which implies that the minority carrier concentration changes are zero: Dn(0) ¼ 0,

(4:6:6)

Dn(Wb ) ¼ 0:

(4:6:7)

To avoid confusion, we will use x 0 to denote the distance in the neutral base, and use x to denote the injection point. Assuming constant diffusivity, zero base electric field, zero recombination, the minority electron current in a homogeneous p-type base under small signal excitations can be obtained from linearization of its large signal expression as

∆n x

0

0

Wb

x


∆n (x ) ∆Jn(x
) ∆Jn(Wb)

∆Jn

∆Jn(0)

x
0

x

Wb

Neutral base ∆Jn(Wb)

∆Jn(0) x 0

∆Jn

Wb

FIGURE 4.6.3 Solution of the scalar Green’s function G(x) using an excitation of DJn at x 0 ¼ x.

© 2006 by Taylor & Francis Group, LLC

4.6-463

Microscopic Noise Simulation

DJn (x 0 ) ¼ qDn

dDn(x 0 ) , dx 0

(4:6:8)

DJn (x 0 ) is constant from x 0 ¼ 0 to x as there is no recombination, and must be equal to DJn(0). Using Equation (4.6.6) and integrating Equation (4.6.8) from 0 to x, DJn (0)  (x
0) ¼ qDn ½Dn(x)
0:

(4:6:9)

DJn(0) is now related to Dn(x): DJn (0) ¼

qDn Dn(x) : x

(4:6:10)

Similarly, DJn (x 0 ) is constant from x to Wb, and must be equal to DJn(Wb). Using Equation (4.6.7) and integrating Equation (4.6.8) from x 0 ¼ x to Wb , DJn (Wb )  (Wb
x) ¼ qDn ½0
Dn(x);

(4:6:11)

DJn(Wb) is thus obtained as DJn (Wb ) ¼


qDn Dn(x) : Wb
x

(4:6:12)

A sudden change from DJn (0) to DJn (Wb) occurs at x 0 ¼ x, because of the DJn injection:
DJn ¼ DJn (Wb )
DJn (0) ¼ qDn (
1)Dn(x)

 1 1 þ : Wb
x x

(4:6:13)

Using Equation (4.6.12) and Equation (4.6.13), G(x) is obtained as

DJn (Wb ) G(x) ¼ ¼ DJn

1 x Wb
x : ¼ 1 1 Wb þ Wb
x x

(4:6:14)

We note that G(x) is dimensionless, as it represents a current gain. In this case, G(x) is simply x/Wb. In general, however, G(x) is a frequency-dependent complex number. G 0 is readily evaluated as G 0 (x) ¼

dG(x) 1 ¼ : dx Wb

(4:6:15)

G 0 (x) is position-independent in this case, and therefore, the final noise for each section is determined by the noise source density. Recall that the spectral density of DJn for the incremental section (x, xþDx) is given by Equation (4.6.2), which is rewritten as SDJn ¼ 4q2 Dn n(x)

© 2006 by Taylor & Francis Group, LLC

1 : ADx

(4:6:16)

4.6-464

The Silicon Heterostructure Handbook

Substituting Equation (4.6.16) and Equation (4.6.15) into Equation (4.6.5), DSJC ¼ 4q2 Dn n(x)

1 1 Dx: A Wb2

(4:6:17)

Replacing Dx by dx, and integrating from 0 to Wb, one obtains the total noise SJC as SJ C ¼ ¼

ð Wd dSJC 0 ð Wb

4q2 Dn n(x)

0

1 1 dx A Wb2

ð 1 1 Wb 1 1 n(0) Wb n(x)dx ¼ 4q2 Dn 2 A Wb 0 A Wb2 2 qDn n(0) 1 1 ¼ 2qJC ¼ 2q Wb A A ¼ 4q2 Dn

(4:6:18)

where we used: JC ¼

qDn n(0) , Wb

(4:6:19)

a direct result of linear minority carrier distribution in an ideal bipolar transistor. JC is related to IC by IC ¼ AJC, thus: SIC ¼ A2 SJC ¼ 2qIC :

(4:6:20)

The base current shot noise can be derived in the same manner: SIB ¼ 2qIB :

(4:6:21)

Noise Concentration In practice, one may only be interested in the terminal noise produced by a unit volume at a given location, that is, dSJC/dx in our one-dimensional bipolar example. Just like one can calculate the total number of electrons in the device by integrating electron concentration, one can calculate the total terminal noise current or voltage by integrating the noise concentration. A plot of the noise concentration immediately shows where most of the noise comes from within the physical structure of the device. Obviously, if one desires to understand the details of the noise concentration plot, one would have to examine the noise source density and the Green’s functions.

4.6.3 Input Voltage and Current Noise Concentrations The results of microscopic noise simulation are typically given for either the open-circuit noise voltages or the short-circuit noise currents. However, for noise optimization, the input noise current and voltage for a chain representation are the most convenient, and directly relate to NFmin, Yopt, and Rn. The microscopic noise concentrations for the input noise current, voltage, and their correlation Sia, Sva, and Sia va* facilitate identification of major noise sources within the transistor physical structure, leading to device-level optimization (e.g., doping profile, Ge profile, and device layout) with respect to the noise parameters, and can be obtained as follows [7].

© 2006 by Taylor & Francis Group, LLC

4.6-465

Microscopic Noise Simulation

Consider the transistor as a noisy linear two port. The open-circuit noise voltage parameters are obtained by integrating the ‘‘noise concentration’’ over the device volume Sn ¼

ð CSn dV;

(4:6:22)

V

where n is v1, v2, or v1v*2. For instance CSv 1 is the ‘‘concentration’’ (volume density) of Sv1 , and has a unit of V2/Hz/cm3. CSv 1CSv 2 and CSv * are solved in TCAD tools, including DESSIS and TAURUS [8, 9]. In 1 v2 principle, the boundary conditions can be modified to directly solve for the ‘‘concentration’’ of the chain representation noise parameters Sia, Sva, and Sia va* . This, however, has not been implemented in device simulators. The problem can be circumvented by postprocessing of CSv 1 , CSv 2 , and CSv v* which requires 1 2 no code development by TCAD vendors [7]: "

CSva C Si v * a a

C Sv i * a a C Si a

#

"

CSv1 ¼ T: C Sv * 2v1

# C Sv * 1 v2 T y; C Sv 2

(4:6:23)

where  T¼

1 0


A11 ,
A21

(4:6:24)

where A11 and A21 are elements of the ABCD parameter matrix A. T y is the transposed conjugate of T. Integration of the obtained chain representation noise concentrations CSv a , CSi a , and CSi a v *a over the whole device gives the transistor Sva, Sia, and Sia va* , respectively. Each noise concentration consists of an electron contribution and a hole contribution, which account for electron and hole velocity fluctuations, respectively.

4.6.4 A SiGe HBT Example One major benefit of simulation is that it offers insight into internal device operation, which can be used to develop better compact model. The same principle applies to noise simulation and noise modeling. We now examine the classical bipolar transistor noise model using the simulation results as a reference for a SiGe HBT.

Macroscopic Input Noise Figure 4.6.4(a) and (b) shows the chain representation and an equivalent circuit containing the main macroscopic noise sources, respectively. Through noise-circuit analysis, Sva, Sia, and Sia va* are obtained as [10] Sva ¼

2qIC þ 2qIB rb2 þ 4kTrb , jY21 j2 2qIC , jh21 j2

(4:6:26)

Y11 þ 2qIB rb , jY21 j2

(4:6:27)

Sia ¼ 2qIB þ Sia va* ¼ 2qIC

© 2006 by Taylor & Francis Group, LLC

(4:6:25)

4.6-466

The Silicon Heterostructure Handbook

where h21 ¼ Y21/Y11. The Y parameters are for the whole transistor that includes both rb and the intrinsic transistor.

Macroscopic and Microscopic Connections The 4kTrb terms in the model equations account for velocity fluctuations of holes in the base. One can therefore compare the 4kTrb related terms with the integration of the base hole noise concentration. Similarly, the 2qIB terms account for emitter minority hole velocity fluctuation, and the 2qIC terms account for base minority electron velocity fluctuation [4]. Thus, connections between compact noise model and microscopic noise simulation can be established for Sva, Sia, and Sia va* , as shown in Table 4.6.1. Here the superscripts e and h stand for electron and hole contributions, respectively.

Input Noise Voltage and Current Figure 4.6.5(a) compares the modeled and simulated Sva, Svea , and Svha for JC ¼ 0.05 mA/mm2. Svea dominates over Svha . The model slightly underestimates Svea , and significantly underestimates Svha . The simulated Svea and Svha are both frequency dependent. Despite inaccurate modeling of Svha , the total Sva is well modeled, because of the dominance of Svea . At a higher JC of 0.65 mA/mm2, however, the hole contribution dominates over the electron contribution, as shown in Figure 4.6.5(b). With increasing JC, Svea decreases, while Svha stays about the same. The model underestimates Svha , and overestimates Svea . Observe that the simulated Svha is frequency dependent, while the modeled Svha (4kTrb) is frequency independent. Figure 4.6.6 and Figure 4.6.7 show the electron and hole noise concentration contours at 2 GHz (CSev a and CShv a ) at JC ¼ 0.65 mA/mm2. Both CSev a and CShv a are the highest in the SiGe base, indicating that transistor Sva mainly comes from the SiGe base. This provides guidelines to future noise model

I1

Va

I2 Noiseless two-port

+ V1

Ia

Y

_

I1 +

rb

I2

+

+ 2qIB

V2

V1

_

_

(a)

FIGURE 4.6.4

4kTrb

Intrinsic BJT

2qIC V2 _

(b)

(a) Chain representation of a noisy two-port. (b) The essence of noise modeling used in CAD tools.

TABLE 4.6.1

Connections between Noise Modeling and Simulation Model

Svea

2qIC/jY21j2

Svha

2qIBr2b

Siea

4kTrb 2qIC/jh21j2

Siha Siea va*

2qIB 2qICY11/jY21j2

Siha va*

2qIBrb

© 2006 by Taylor & Francis Group, LLC

Simulation Ð e base CSv a dV Ð h emitter CSv a dV Ð C h dV Ð base Sev a base CSi a dV Ð C h dV Ð emitter e Si a base CSia v * dV a Ð h emitter CSia v * dV a

4.6-467

Microscopic Noise Simulation

1017 Impedance Field Simulation Compact Noise Model

Total

Total (V2/Hz)

(V2/Hz)

1016

S va, S eva, and S hva

S va, S eva, and S hva

Electron contribution

JC = 0.05 mA/µm2

Hole contribution

1017

Hole contribution

Electron contribution

JC = 0.65 mA/µm2 Impedance Field Simulation Compact Noise Model

1018 5

10 15 Freq (GHz)

20

5

10 15 Freq (GHz)

(a)

FIGURE 4.6.5 Sva,

Svea ,

and

Svha

20

(b) 2

versus frequency at (a) JC ¼ 0.05 mA/mm . (b) JC ¼ 0.65 mA/mm2.

−0.1 0 0.1

E

Y (mm)

0.2

B

0.3 SvaConc. (V2/Hz/cm3)

0.4 0.5 0.6

1.13714341E-04 9.18461982E-05 6.99780558E-05 4.81099134E-05 2.62417709E-05 4.37362849E-06

C Electron contribution JC = 0.65 mA/µm2

0.7

1.5

2 X (mm)

FIGURE 4.6.6.

Two-dimensional distribution of CSeva (2 GHz, JC ¼ 0.65 mA/mm2).

development, that is, the transistor noise mainly originates from the EB junction. In the intrinsic base, and along the x-direction, CSev a is uniform, while CShv a is highly nonuniform, and shows a strong ‘‘base noise crowding’’ effect. Figure 4.6.8(a) shows the integrals of CSev a in the base, emitter, collector, and p-substrate, together with the 2qIC related term in the model at JC ¼ 0.65 mA/mm2. The model accounts for only the base contribution, which is reasonable, since the simulated base electron contribution overwhelmingly

© 2006 by Taylor & Francis Group, LLC

4.6-468

The Silicon Heterostructure Handbook −0.1 0 0.1

E

Y (mm)

0.2

B

0.3 SvaConc. (V2/Hz/cm3) 0.4

C

3.13664075E-04 2.53344060E-04 1.93024046E-04 1.32704032E-04 7.23840172E-05 1.20640029E-05

0.5 0.6

Hole contribution Jc = 0.65 mA/µm2

0.7

1.5

2 X (mm)

FIGURE 4.6.7.

Two-dimensional distribution of CShv a (2 GHz, JC ¼ 0.65 mA/mm2).

10−17

10−17

10−18

(V2/Hz)

10−19 Emitter electrons

10−20

10−21 Collector electrons

Base electrons Emitter electrons Collector electrons Substrate electrons 2qIC/IY21I2 0

5

Emitter holes

2qIBrb2 Collector holes

JC = 0.65 mA/µm2 Substrate holes

10−22

10−23

10−26

10−19

10−21

Substrate electrons

10−24

4kTrb

10−20

JC = 0.65 mA/µm2

10−22

Base holes

10−18

2qIC/|Y21|2

Regional contributions of S hva

Regional contributions of S eva

(V2/Hz)

Base electrons

10 Freq (GHz)

15

Base holes Emitter holes Collector holes Substrate holes 4kTrb2 2qIBrb

10−23

10−24

20

0

5

10 Freq (GHz)

(a)

FIGURE 4.6.8 Regional contributions of

© 2006 by Taylor & Francis Group, LLC

(b)

Svea

(a) and

Svha

2

(b) at JC ¼ 0.65 mA/mm .

15

20

4.6-469

Microscopic Noise Simulation

dominates over other electron contributions. The 2qIC description, however, overestimates Svea , and thus a better description is required. Figure 4.6.8(b) shows the integrals of CShv a in the base, emitter, collector, and p-substrate. Also shown are the 2qIB (emitter holes) and 4kTrb (base holes) related terms accounted for in the model. The collector and substrate hole noises are indeed negligible. The noise from the base majority holes dominates over the noise from the emitter minority holes. The base majority hole noise contribution is less than predicted by 4kTrb, and frequency dependent as well. The noise from the emitter minority holes increases with frequency, and is underestimated by 2qIB related term. Figure 4.6.9(a) compares modeled and simulated Sia, Siea , and Siha for JC ¼ 0.05 mA/mm2. Siea decreases with frequency and is slightly underestimated (by the model). Siha increases dramatically with frequency, and is significantly underestimated. At a higher JC of 0.65 mA/mm2, however, the Siea discrepancy between model and simulation becomes much more pronounced (as shown in Figure 4.6.9(b)). Thus, for Sia, 2qIC is not a good description for base minority electron noise. Like for Svha , the frequency dependence for Siha is not accounted for in the model. Siha dominates at lower frequencies, while Siea becomes dominant at higher frequencies. Figure 4.6.10(a) shows the integrals of CSei a in the base, emitter, collector, and p-substrate. JC ¼ 0.65 mA/mm2. The model only accounts for the base electron contribution, a 2qIC/jh21j2 term. Like for other noise parameters, the base minority electron contribution for Siea is poorly modeled by the 2qIC related term. Figure 4.6.10(b) shows the regional contributions of Siha . The model accounts for only the emitter hole contribution through the 2qIB term. Even though the collector and substrate hole contributions are indeed negligible, the base hole contribution is not negligible at higher frequencies. This emitter contribution constitutes the main discrepancy for the total Siha between modeling and simulation, and shows frequency dependence.

Impedance Field Simulation Compact Noise Model

JC = 0.65 mA/µm2

Total

1023

Sia, S eia, and S hia (A2/Hz)

Sia, S eia, and S hia (A2/Hz)

1023

Electron contribution

1024

Total

Hole contribution

1024

1025 JC = 0.05 mA/µm2

Electron contribution

Hole contribution Impedance Field Simulation Compact Noise Model

1026 5

10 15 Freq (GHz) (a)

20

5

10 15 Freq (GHz) (b)

FIGURE 4.6.9 Sia, Siea , and Siha versus frequency at (a) JC ¼ 0.05 mA/mm2. (b) JC ¼ 0.65 mA/mm2.

© 2006 by Taylor & Francis Group, LLC

20

4.6-470

The Silicon Heterostructure Handbook

10−23

10−22 2qIC/|h21|2

10−23

10−24

Emitter holes

Base electrons

10−25 10−26

Regional contributions of S hia (A2/Hz)

Regional contributions of S hia (A2/Hz)

10−24

Emitter electrons

10−27

JC = 0.65 mA/µm2 Collector electrons

10−28

Substrate electrons

10−29

2qIB

10−25 Base holes

10−26

JC = 0.65 mA/µm2

10−27

substrate holes

10−28 Collector holes

10−29

10−30 base electrons emitter electrons collector electrons substrate electrons 2qIC/|h21|2

10−31 10−32

0

5

10 Freq (GHz)

15

base holes emitter holes collector holes substrate holes 2qIB

10−30

20

10−31

0

5

10 Freq (GHz)

(a)

FIGURE 4.6.10.

15

20

(b)

Regional contributions of

Siea

(a) and

Siha

2

(b) at JC ¼ 0.65 mA/mm .

Similar analysis can be performed for Sia va* . The results also show that the noise from the base minority electrons is poorly described by the model. Similar problems exist with 4kTrb description of the base hole noise, and 2qIC description of the base minority electron noise.

NFmin, Yopt, and Rn NFmin, Yopt, and Rn are obtained from Sva, Sia, and Sia va* by [11] qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 Sva Sia
½I(Sia va* )2 þ R(Sia va* ) 5, ¼ 10 log41 þ 2kT 2

NFmin

Yopt

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   I(Sia va* ) 2 R(Sia va* ) Si a ¼
,
j Sva Sva Sva Rn ¼ Sva =4kT :

(4:6:28)

(4:6:29) (4:6:30)

To compare the impact of electron and hole noise on circuit-level noise parameters, we examine NFemin and NFhmin, defined as the NFmin that the transistor would have when only electron velocity or only hole velocity fluctuates, respectively. NFemin is obtained by substituting Svea , Siea , and Siea va* into Equation (4.6.7). NFhmin is obtained similarly. Since NFmin is not a linear function of Sva, Sia, and Sia va* , e is similarly defined and obtained by substituting Svea , Siea , and Siea va* into NFmin 6¼ NFemin þ NFhmin. Y opt e h þ Y opt . Equation (4.6.8). Like NFmin, Yopt 6¼ Y opt

© 2006 by Taylor & Francis Group, LLC

4.6-471

Microscopic Noise Simulation

550

Impedance Field Simulation Compact Noise Model

Impedance Field Simulation Compact Noise Model

6

JC = 0.65 mA/µm2

JC = 0.65 mA/µm2

500

h NFmin, NFmin, and NFmin (dB)

400 350

Rhn

4 NFmin

e

Rn, Rne , and Rnh (Ω)

5

Rn

450

300 250

3

2

200 Rne

150

h NFmin

1 e NFmin

100 5

10 Freq (GHz) (a)

15

20

5

10 Freq (GHz) (b)

15

20

FIGURE 4.6.11 (a) Rn. (b) NFmin. JC ¼ 0.65 mA/mm2.

Figure 4.6.11(a) shows the simulated and modeled Rn, Ren, and Rhn for JC ¼ 0.65 mA/mm2. Figure 4.6.11(b) shows the modeled and simulated NFmin, NFemin, and NFhmin, also for JC ¼ 0.65 mA/mm2. Since Rn ¼ Sva/4kT, which is a linear function, Rn ¼ Ren þ Rhn. The problems with Sva modeling directly translate into Rn inaccuracy. Both NFmin and NFemin are overestimated by the model, and the discrepancies increase dramatically with frequency. NFhmin is poorly modeled. Note that the frequency dependence of NFhmin is not modeled. Figure 4.6.12(a) and (b) shows the real and imaginary parts of Yopt for JC ¼ 0.65 mA/mm2. Neither e h or Y opt is well modeled. The discrepancies increase with frequency. The frequency Yopt nor Y opt h dependence of Y opt is not accounted for by the model. The discrepancies of Rn, NFmin, and Yopt are all fundamentally caused by the inaccurate modeling of Sva, Sia, and Sia va* . In particular, the description of base minority electron noise using 2qIC is clearly responsible for the inaccuracy of the electron contributions, and the description of base majority hole noise using 4kTrb is responsible for the inaccuracy of the hole contributions.

4.6.5 Summary We have presented an overview of the concepts related to microscopic noise analysis. The key concepts involved are the noise source density, and the scalar and vector Green’s functions that describe noise propagation. These concepts are illustrated using analytical treatment of the collector current shot noise. Two-dimensional microscopic noise simulation results on a SiGe HBT are presented, and used to examine the validity of the widely used macroscopic transistor noise model.

© 2006 by Taylor & Francis Group, LLC

4.6-472

The Silicon Heterostructure Handbook

 103 Impedance Field Simulation Compact Noise Model

2

0 h ℑ(Yopt )

JC = 0.65 mA/µm2 e h ℑ(Yopt ), ℑ(Yopt ), and ℑ(Yopt ) (Ω1)

2

ℜ(Yopt)

1.6

h

ℜ(Yopt), ℜ(Yopt), and ℜ(Yopt) (Ω1)

1.8

 104

1.4

e

1.2

1

0.8

h ) ℜ(Yopt

6

8

e

ℑ(Yopt) 10

e

16 10

JC = 0.65 mA/µm2

14

ℜ(Yopt) 5

15

20

Impedance Field Simulation Compact Noise Model 5

Freq (GHz)

10

15

20

Freq (GHz)

(a)

FIGURE 4.6.12.

ℑ(Yopt)

12

0.6

0.4

4

(b) 2

(a) R(Yopt). (b) I(Yopt). JC ¼ 0.65 mA/mm .

Acknowledgments The author would like to thank Y. Cui for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ-1133.

References 1. W Shockley, J Copeland, and R James. The impedance field method of noise calculation in active semiconductor devices. Quantum Theory of Atoms, Molecules, and the Solid-State. Academic Press, New York, 1966, pp. 537–563. 2. A van der Ziel and KM van Vliet. H.f. thermal noise in space-charge limited solid state diodes — II. Solid-State Electron. 11:508–509, 1968. 3. KM van Vliet. General transistor theory of noise in PN junction-like devices — I. Three-dimensional Green’s function formulation. Solid-State Electron. 15:1033–1053, 1972. 4. F Bonani, G Ghione, M Pinto, and R Smith. An efficient approach to noise analysis through multidimensional physics-based models. IEEE Trans. Electron Dev. 45:261–269, 1998. 5. F Bonani and G Ghione. Noise in Semiconductor Devices: Modeling and Simulation. Springer-Verlag, Heidelberg, 2001. 6. GF Niu. Bridging the gap between microscopic and macroscopic theories of noise in bipolar junction transistors. Tech. Digest of IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. pp. 227–230, 2004.

© 2006 by Taylor & Francis Group, LLC

Microscopic Noise Simulation

4.6-473

7. Y Cui, GF Niu, Y Shi, and DL Harame. Spatial distribution of microscopic noise contributions in SiGe HBT. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, April 2003, pp. 170–173. 8. DESSIS device simulator. ISE Integrated Systems Engineering. 9. TAURUS-DEVICE simulator. Synopsys, Inc. 10. Y Cui, GF Niu, and DL Harame. An examination of bipolar transistor noise modeling and noise physics using microscopic noise simulation. Proceedings of the IEEE BCTM, September 2003, pp. 225–228. 11. HA Haus. Representation of noise in linear twoports. Proc. IRE 48:69–74, 1960.

© 2006 by Taylor & Francis Group, LLC

4.7 Linearity 4.7.1 4.7.2 4.7.3 4.7.4

Identifying Dominant Nonlinearity . Collector Current Dependence . Collector Voltage Dependence . Load Dependence and Nonlinearity Cancellation . Linearity Limiting Factors

Guofu Niu Auburn University

Introduction............................................................... 4.7-475 Basic Concepts........................................................... 4.7-476 Physical Nonlinearities.............................................. 4.7-479 Volterra Series Linearity Analysis............................. 4.7-480

4.7.5

Summary .................................................................... 4.7-485

4.7.1 Introduction ‘‘Linearity’’ is the counterpart of ‘‘distortion,’’ or ‘‘nonlinearity,’’ and refers to the ability of a device, circuit, or system to amplify input signals in a linear fashion. SiGe HBTs, like other semiconductor devices, are in general nonlinear elements. Most obviously, the collector current IC depends on the base– emitter voltage VBE exponentially, common to all bipolar transistors. This exponential I–V relation in fact represents the strongest nonlinearity found in nature, and underlies the ‘‘translinear principle,’’ which enables a large variety of linear and nonlinear functions to be realized using bipolar transistors. Despite our intuition, the distortion in translinear circuits is not caused by the exponential IC –VBE relationship, but rather is due to the departure from it, by various means (i.e., series resistance, high-level injection, impact ionization, early effect, and inverse early effect). SiGe HBTs can be used to build both ‘‘nonlinear’’ and ‘‘linear’’ circuits depending on the required application and the circuit topology used. In fact, transistor nonlinearity is both a blessing and a curse. Nonlinearity can be a blessing because we need nonlinearity to realize frequency translation; but can also be a curse, because it creates distortion in the various signals we are interested in preserving, amplifying, or transmitting. For instance, nonlinearity causes intermodulation (IM) of two adjacent strongly interfering signals at the input of a receiver, which can corrupt the nearby (desired) weak signal we are trying to receive. In the transmit path, nonlinearity in power amplifiers clips the large amplitude input, which causes power leaking (and thus interference) to adjacent channels in digitally modulated signals. Perhaps surprisingly, SiGe HBTs exhibit excellent linearity in both small-signal (e.g., LNA) and largesignal (e.g., PA) RF circuits, despite their strong I–V and C–V nonlinearities. Clearly, the overall circuit linearity strongly depends on the interaction (and potential cancellation) between the various I–V and C–V nonlinearities, the linear elements in the device, as well as the source termination, the load termination, and any feedback present, intentional or parasitic. These issues can be best understood using Volterra series [1–3], a powerful formalism for analysis of nonlinear systems. In this chapter, we focus on the intermodulation linearity of SiGe HBTs, a major concern in RF circuits.

4.7-475 © 2006 by Taylor & Francis Group, LLC

4.7-476

The Silicon Heterostructure Handbook

4.7.2 Basic Concepts We first introduce basic nonlinearity concepts using simple power series, which strictly speaking only applies to a memory-less circuit. Under small-signal input, the output voltage y(t) is related to its input voltage x(t) by y(t) ¼ k1 x(t) þ k2 x 2 (t) þ k3 x 3 (t):

(4:7:1)

Consider a two-tone input x(t) ¼ A cos v1t þ A cos v2t. The output has not only harmonics of v1 and v2, but also ‘‘intermodulation products’’ at 2v1
v2 and 2v2
v1. A full expansion of Equation (4.7.1) shows that the output contains signals at v1, v2, 2v1, 2v2, 3v1, 3v2, v1 þ v2, v1
v2, 2v2
v1, 2v2 þ v1, 2v1
v2, and 2v1 þ v2. When v1 and v2 are closely spaced, the third-order intermodulation products at 2v2
v1 and 2v1
v2 are the major concerns, because they are close to v1 and v2, and thus within the amplifier bandwidth. Consider a weak desired signal channel, and two nearby strong interferers at the input. One intermodulation product falls in band, and corrupts the desired component (as illustrated in Figure 4.7.1). The fundamental signal and intermodulation products in the output are given by y(t) ¼


 3k3 A3 3k3 A3 3k3 A3 þ cos v1 t þ    þ cos (2v2
v1 )t k1 A þ 4 2 4 þ    fundamental intermodulation:

(4:7:2)

The ratio of the amplitude of the IM product to the amplitude of the fundamental output is defined as the ‘‘third-order intermodulation distortion’’ (IM3). Neglecting the higher order terms added to k1A, one has IM3 ¼

f1

f2

3k3 A3 4

 k1 A ¼

3 k3 2 A: 4 k1

(4:7:3)

IM3

2f 2−f 1

FIGURE 4.7.1 Illustration of the corruption of desired signals by the intermodulation product of two strong interferers.

© 2006 by Taylor & Francis Group, LLC

4.7-477

Linearity

For small A, the fundamental output at v1 grows linearly with A, while the IM product at 2v2
v1 grows as A3. A 1-dB increase in the input results in a 1-dB increase of fundamental output, but a 3-dB increase of IM product. The extrapolation of the fundamental output and the IM3 versus the input intersect at a given input level, which is defined as the input third-order intercept point (IIP3). IIP3 is obtained from Equation (4.7.3) by letting IM3 ¼ 1 sffiffiffiffiffiffiffiffi 4 k1 : IIP3 ¼ 3 k3

(4:7:4)

IIP3 is a widely used figure-of-merit because it does not depend on the input signal level. Because IM3 grows with A2 (Equation (4.7.3)), IIP3 can be measured at a single input level A0, IIP32 ¼

A20 , IM30

(4:7:5)

where IM30 is the measured relative intermodulation distortion. Note that IIP3 and A0 are voltages, and thus IIP32 and A20 are measures of power. Taking 10 log on both sides, one has 20 log IIP3 ¼ 20 log A0
10 log IM30 :

(4:7:6)

Here, 20 log IIP3 is the power expressed in dB at the intercept point, and 20 log A0 is now the input power level expressed in dB. The reference power level does not enter into the equation. Now Equation (4.7.6) can be rewritten in terms of power 1 PIIP3 ¼ Pin þ ðPo,1st
Po,3rd Þ 2

(4:7:7)

1 POIP3 ¼ Po,1st þ ðPo,1st
Po,3rd Þ: 2

(4:7:8)

and

In practice, IIP3 and OIP3 are used to denote the power at the intercept point. The IP3 data in commercial load-pull systems and CAD tools (e.g., ADS) are defined for each input power level according to the equations above. The following is the sample output of a load-pull measurement on a SiGe HBT amplifier. The two tones are at 2.000 and 2.001 GHz (i.e., 1-MHz spacing).

Pin (dB m)
30.00
29.00
28.00
27.00
26.00
25.00
24.00
23.00
22.00

© 2006 by Taylor & Francis Group, LLC

Pout,1st (dB m)

Gain (dB)

Pout,3rd (dB m)

POIP3 (dB m)


11.72
10.75
9.74
8.74
7.72
6.77
5.74
4.73
3.75

18.28 18.25 18.26 18.26 18.28 18.23 18.26 18.27 18.25


74.48
72.68
69.91
67.24
64.89
62.28
59.57
57.15
54.66

19.65 20.20 20.35 20.51 20.87 20.98 21.18 21.47 21.71

4.7-478

The Silicon Heterostructure Handbook

Frequency Source state Source imp. Load state Load imp. Vc Vb Date Time

2.00 GHz 1; #377 0.20–170.1 1; #550 0.70–14.9 3.001 V 0.816 V April 30, 1998 16:22:43

Figure 4.7.2 shows the measured fundamental and third-order IM product power versus input power data for the above SiGe HBT amplifier, along with gain. The measured slope of the IM product curve deviates from 3:1, because of the ‘‘high’’ input power level used in the measurement. As a result, the IP3 numbers measured at different input powers are different, as can be seen from the data output. One would obtain an OIP3 of 35 dB m by simply extrapolating the linear portions of the measured Pout,1st and Pout,3rd data. The OIP3 based on a theoretical 3:1 slope at Pin ¼
30 dB m is only 20 dB m, however, and therefore, caution must be exercised in interpreting the IP3 numbers. The gain compression at very high input power level can also be clearly seen here. Clearly IIP3 is an important figure-of-merit for front-end RF–microwave low-noise amplifiers, because they must contend with a variety of signals coming from the antenna. The interfering signals are often much stronger than the desired signal, thus generating strong intermodulation products that can corrupt the weak but desired signal. To some extent, IIP3 is a measure of the ability of a handset, for instance, not to ‘‘drop’’ a phone call in a crowded environment. For many LNA applications, IIP3 is just as important (if not more so) as the noise figure. The dc power consumption must also be kept very low because the LNA is likely to be continuously listening for transmitted signals of interest and hence continuously draining power. The power consumption aspect is taken into account by another figure-of-merit, the linearity efficiency, which is defined as IIP3/Pdc, where Pdc is the dc power dissipation. First-generation SiGe HBTs typically exhibit excellent linearity efficiencies above 10, which is competitive with III–V technologies. We note, however, that IIP3/Pdc is not adequate for describing the Class AB operating mode for transistors in the driver and output stage of power amplifiers [4].

40

20

Gain

0 15 −20

Pout,1st

−40 −60 80 −40

Pout,3rd

−30

10

IC = 3 mA VCE = 3 V AE = 0.5⫻20⫻4 µm2 SiGe HBT 2 GHz −20 −10 P in (dBm)

0

Gain (dB)

Pout (dBm)

20

25

5 0 10

FIGURE 4.7.2 A typical Pout versus Pin curve for a first generation SiGe HBT (IC ¼ 3 mA and VCE ¼ 3 V). The input power at the 1-dB compression point is
3 dB m.

© 2006 by Taylor & Francis Group, LLC

4.7-479

Linearity

4.7.3 Physical Nonlinearities The major physical nonlinearities in a SiGe HBT are depicted in Figure 4.7.3, including: 1. ICE, the collector current transported from the emitter, ICE / exp(VBE/VT). 2. IBE, the hole injection current into the emitter. IBE tracks ICE through IBE ¼ ICE/b. 3. ICB, the avalanche multiplication current, and is a strong nonlinear function of both VBE and VCB [5]. The nonlinearity due to ICB can be minimized using a low VCB. 4. CBE, the EB junction capacitance, including the diffusion capacitance and depletion capacitance. CBE tracks ICE at high JC because diffusion charge is in proportion to the transport current ICE. 5. CCB, the CB junction capacitance. CCB is much smaller than CBE, because of reverse bias on the CB junction. The feedback position, however, makes CCB important for circuit linearity. A medium value VCB that makes CCB more linear and keeps the avalanche (breakdown) current ICB small is optimum for linearity [6]. Both the value and the bias dependence of CCB matter for the overall transistor linearity [7]. Among all the nonlinearities, the ICE–VBE nonlinearity often dominates in RF circuits. For relatively weak input signal, the nonlinear ICE–VBE relation can be approximated by a Taylor expansion. A direct consequence of the ICE–VCE nonlinearity is to make the effective transconductance a function of vbe (as opposed to a constant in a linear circuit) 0

gm,eff

1 nonlinear contributions zfflfflfflfflfflfflfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflfflfflfflfflfflfflffl{ B C 2 ic 1 vbe 1 vbe B C ¼ ¼ gm B1 þ þ þ . . .C: 2 @ A 2 Vt 6 Vt vbe

(4:7:9)

Equation (4.7.9) indicates that the nonlinear contributions to gm,eff increase with the voltage drop across the EB junction vbe. In typical bipolar amplifiers, vbe decreases with increasing biasing current, making

(1-XCJC)CBC XCJC CBC

RB

ICB (VBE,VCB)

RC C

IBE(VBE)

CBE

ICE(VBE,VCB)

B

RE CBE - EB capacitance CBC - CB capacitance CCS - CS capacitance

CCS

Substrate ICB - Avalanche multiplication

E

ICE - Transport current IBE - Hole injection into emitter

FIGURE 4.7.3 Nonlinear I–V and C–V relations in a bipolar transistor.

© 2006 by Taylor & Francis Group, LLC

4.7-480

The Silicon Heterostructure Handbook

gm,eff closer to a constant like in a linear circuit. Linearity of bipolar circuits can therefore be improved by increasing the biasing current. The expense is, however, increased power consumption. Parasitic or intentionally used emitter resistance or inductance also helps improving linearity by decreasing vbe through negative feedback. All the capacitances, either internal or external CBE and CCB, help improving linearity through negative feedback at the expense of gain. The nonlinear contributions from various I–V and C–V nonlinearities cancel out each other to certain extent depending on circuit design, which further improves circuit overall linearity. In particular, for bipolar transistors, the exponential I–V and exponential C–V nonlinearities can be engineered to cancel out through tuning of harmonic impedance termination, which can be understood using Volterra series, as described below.

4.7.4 Volterra Series Linearity Analysis We now examine how the physical nonlinearities affect IP3 using Volterra series, a mathematical method of analyzing small-signal distortion. Compared to other distortion analysis methods, Volterra series allows us to easily identify the contribution of various individual nonlinearities, as well as identify the interaction between individual nonlinearities. Volterra series is an extension of the theory of linear systems to weakly nonlinear systems, its essence is summarized as follows: .

.

Volterra series approximate the output of a nonlinear system in a manner similar to the more familiar Taylor series approximation of analytical functions. Similarly, the analysis is applicable only to weak nonlinearities, or small inputs. The response of a nonlinear system to an input x(t) is equal to the sum of the responses of a series of transfer functions of different orders (H1, H2, . . . , Hn) Y ¼ H1 (x) þ H2 (x) þ H3 (x) þ    :

.

(4:7:10)

In the time domain, Hn is described as an impulse response hi(t 1, t 2, . . . , t n). As in linear circuit analysis, frequency-domain representation is more convenient, and thus Hn(s1, . . . , sn), the nthorder transfer function or Volterra kernel in frequency domain, is obtained through a multidimensional Laplace transform of the time-domain impulse response Laplace transform

zfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflffl{ time domain ð þ1 zfflfflfflfflfflfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflfflfflfflfflfflffl{ zfflfflfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflfflfflffl{ ð þ1 Hn (s1 ,    , sn ) ¼  hn (t 1 , t 2 , . . . , t n ) e
(s1 t1 þs2 t2 þþsn tn ) dt 1    dt n : frequency domain


1 . .

.

(4:7:11)


1

Here, Hn takes n frequencies as the input, from s1 ¼ jv1 to sn ¼ jvn. The first-order transfer function or Volterra kernel H1(s) is essentially the transfer function of the small-signal linear circuit at dc bias. Higher order transfer functions represent higher order phenomena. Solving the output of a nonlinear circuit is equivalent to solving the Volterra series H1(s), H2(s1,s2), and H3(s1,s2,s3), . . .

The mathematical derivation of Volterra kernels for nonlinear circuits has been well treated in Refs. [1, 2]. We will focus on its application to calculation of IIP3 in SiGe HBTs. Consider a single transistor amplifier shown in Figure 4.7.4. The first step is to linearize the largesignal equivalent circuit in Figure 4.7.3 at the bias point. The resulting linear circuit is then solved using compacted modified nodal analysis (CMNA) [8]: ~1 (s) ¼ ~ I1 , Y (s)  H

© 2006 by Taylor & Francis Group, LLC

(4:7:12)

4.7-481

Linearity

LL

+ VBE

VCE

RL

Load inductance

CS

−

AC freq 2 AC freq 1

RS

IC

Load resistance

SiGe HBT

FIGURE 4.7.4 Circuit schematic of the single transistor amplifier used.

~ 1(s) is the vector of first-order where Y(s) is the CMNA [8] admittance matrix at frequency s(jv), H ~ Volterra kernel transforms of the node voltages, and I 1 is the vector of the node excitations. The admittance matrix Y and the excitation vector ~ I 1 are obtained by applying the Kirchoff ’s current law at every circuit node. The unknowns are the node voltages. The circuit output and the voltages that ~ 1(s). control nonlinearities can be expressed as a linear combination of the elements of H ~ With H 1(s) solved, we now excite the same circuit using the second-order nonlinear current sources ~ I 2, which are functions of the first-order voltages that control individual nonlinearities, and the secondorder derivatives of all the I–V and C–V nonlinearities. Every nonlinearity in the original circuit corresponds to a nonlinear current source in parallel with the corresponding linearized circuit element. ~ 2(s1,s2): The node voltages under such an excitation are the second-order Volterra kernels H ~2 (s1 ; s2 ) ¼ ~ I2 Y (s1 þ s2 )  H

(4:7:13)

where Y(s1 þ s2) is the same CMNA admittance matrix used in Equation (4.7.12), but evaluated at the frequency s1 þ s2. ~ 3 can be solved as response to excitations In a similar manner, the third-order Volterra kernels H specified in terms of the previously determined first- and second-order kernels: ~2 (s1 , s2 , s3 ) ¼ ~ I3 : Y (s1 þ s2 þ s3 )  H

(4:7:14)

Pout versus Pin, the third-order input intercept (IIP3) at which the first- and third-order signals have ~ 1. IIP3, the input power at which ~ 3 and H equal power, and the (power) gain can then be obtained from H the fundamental output power equals the intermodulation output power, is obtained as [6]: IIP3 ¼

1 jH1 ( jv1 )j , 6RS jH3 ( jv1 , jv1 ,
jv2 )j

(4:7:15)

where RS is the source resistance. IIP3 is often expressed in dB m by IIP3dBm ¼ 10 log10(103IIP3). An inspection of the Volterra series procedure immediately shows that the Volterra kernels are strongly related to the properties of the circuit admittance matrix at various frequencies. For intermodulation (2v1
v2), the circuit admittance matrix at the second harmonic frequency and at very low frequency (v1
v2) are of particular importance. Harmonic tuning and low-frequency ‘‘traps’’ circuit techniques of linearity enhancement [9–11] are based on this concept.

© 2006 by Taylor & Francis Group, LLC

4.7-482

The Silicon Heterostructure Handbook

Identifying Dominant Nonlinearity An unique feature of the Volterra series approach is the ability to identify the dominant physical nonlinearity [2, 6]. This is realized by turning on and off each individual nonlinearity-related nonlinear ~ 3 [6]. An individual IIP3 is thus ~ 2 and H current sources in formulating the excitations for solving H obtained for each nonlinearity. The individual nonlinearity that gives the lowest IIP3 (the worst linearity) is identified as the dominant nonlinearity. We can then calculate the overall IIP3 by including all of the nonlinearities in the calculation of ~ 3. A comparison of the individual IIP3 and the overall IIP3 reveals the interaction ~ 2 and H both H between individual nonlinearities. As shown below, the overall IIP3 obtained by including all of the nonlinearities can be larger (better) than an individual IIP3, implying cancellation between individual nonlinearities [6, 12]. We now consider the Volterra series linearity analysis of a SiGe HBT with 50 GHz peak fT. The frequency is 2 GHz, and the tone spacing is 1 MHz. The SiGe HBT has four AE ¼ 0.5  20 mm2 emitter fingers. IC ¼ 3 mA, VCE ¼ 3 V, RS ¼ 50 V, CS ¼ 300 pF, RL ¼ 186 V, and LL ¼ 9 nH.

Collector Current Dependence Figure 4.7.5 shows the IIP3 and gain as a function of IC up to 60 mA at which fT and fmax peak. The collector biasing voltage is VCE ¼ 3 V. At low IC (<5 mA), the exponential ICE–VBE nonlinearity () yields the lowest individual IIP3, and hence is the dominant factor. For 5 mA < IC <25 mA, the ICB nonlinearity due to avalanche multiplication () dominates. For IC > 25 mA, the CCB nonlinearity due to the CB capacitance ( ) dominates. Interestingly, the overall IIP3 obtained by including all of the nonlinearities is close to the lowest individual IIP3 for all the IC in this case. The closeness indicates a weak interaction between individual nonlinearities. The overall IIP3 increases with IC for IC < 5 mA when the exponential ICE nonlinearity dominates. For IC > 5 mA where the avalanche current (ICB) nonlinearity dominates, the IC dependence of the overall IIP3 is twofold: 4

1. The initial current for avalanche ICE increases with IC. 2. The avalanche multiplication factor (M
1) decreases with IC. The increase of the avalanche IIP3 and hence the overall IIP3 for IC > 17 mA is a result of the decrease of M
1 with increasing JC. For IC > 25 mA, ‘‘the overall IIP3 becomes limited by the CCB nonlinearity, and is approximately independent of IC.’’ The optimum biasing current is therefore IC ¼ 25 mA in this case (VCE ¼ 3 V). The use of a higher IC only increases power consumption, and does not improve

60 I BE I CE CBE CCB CCS I CB

IIP3 (dBm), Gain (dB)

50 40 30 20

all nonlinearities gain

10 0 −10

0

9

17 26 34 43 Collector current (mA)

FIGURE 4.7.5 IIP3 and gain as a function of IC.

© 2006 by Taylor & Francis Group, LLC

51

60

4.7-483

Linearity

linearity. The decrease of M
1 with increasing JC is therefore beneficial to the linearity of these SiGe HBTs. The low-noise biasing JC for this HBT is 0.1 to 0.2 mA/mm2, which corresponds to a IC of 4 to 8 mA in Figure 4.7.5. In this IC range, IIP3 is limited by avalanche multiplication for the circuit configuration in Figure 4.7.4. To further improve IIP3, a lower collector doping is desired, provided that the noise performance is not inadvertently degraded. The noise figure, for instance, is relatively independent of the collector doping as long as Kirk effect does not occur at the JC of interest [13]. Thus, there must exist an optimum collector-doping profile for producing low-noise transistors with the best linearity.

Collector Voltage Dependence An alternative way of reducing avalanche is to decrease the collector biasing voltage, which, however, also reduces the output voltage swing and hence the dynamic range. Another disadvantage from a linearity standpoint is that the CB capacitance nonlinearity is increased. Therefore, one must carefully optimize the collector biasing voltage for optimum IIP3. Figure 4.7.6 shows the overall IIP3 as a function of VCE up to 3.3 V, the BVCEO of the transistor. A peak of IIP3 generally exists as VCE increases. For IC ¼ 10 mA where noise figure is minimum, the optimum biasing VCE is 2.4 V, yielding an IIP3 of 9 dB m. The IIP3 obtained (9 dB m) is 11 dB higher than the IIP3 at VCE ¼ 3 V (
2 dB m), illustrating the importance of biasing in determining linearity of these SiGe HBTs. The biasing current and voltage has significant impact on transistor linearity. Figure 4.7.7 shows the IIP3 as a function of IC for different VCE. At sufficiently high IC, IIP3 approaches a value that depends on VCE. The threshold IC where IIP3 reaches its maximum is higher for a higher VCE. For a given VCE, IC must be above this threshold to achieve good IIP3. On the other hand, the use of an IC well above the threshold does not further increase IIP3, and only increases power consumption. The optimum IC is thus at the threshold value, which is 10 mA for VCE ¼ 2 V. Figure 4.7.8 shows the contours of IIP3 as a function of IC and VCE, which can be used for selection of biasing current and voltage.

Load Dependence and Nonlinearity Cancellation Figure 4.7.9 shows the individual and overall IIP3 as a function of load resistance, together with gain. As expected, the gain varies with load, and peaks when the load is closest to conjugate matching. IIP3, however, is sensitive to load variation. The IIP3 with all nonlinearities (denoted by ) is noticeably !

15

IIP3 (dBm)

10

0

15

IC = 5 mA IC = 10 mA IC = 15 mA IC = 30 mA

−5

−10 1

1.5

2 VCE (V)

FIGURE 4.7.6 IIP3 as a function of VCE for different IC.

© 2006 by Taylor & Francis Group, LLC

2.5

3

4.7-484

The Silicon Heterostructure Handbook

15

10

IIP3 (dBm)

5

0

VCE = 1.5 V VCE = 2.0 V VCE = 2.5 V

−5

VCE = 3.0 V

−10 0

10

20

30 IC (mA)

40

50

60

FIGURE 4.7.7 IIP3 as a function of IC for different VCE.

IIP3 60 55 50 3 45

IC (mA)

40 35 30 9

10

25

0

20

−4

6

15 10 0

5

6

−4 1.2

1.4

−8 1.6

1.8

2

2.2 VCE (V)

FIGURE 4.7.8 Contours of IIP3 in dB m on the IC–VCE plane.

© 2006 by Taylor & Francis Group, LLC

−4

3

2.4

2.6

2.8

3

3.2

4.7-485

Linearity

50

IIP3 (dBm), Gain (dB)

40 I BE I CE CBE CCB CCS I CB

30 20 10 0

all nonlinearities gain

−10 −20

0

100

200 300 Load resistance (Ω)

400

500

FIGURE 4.7.9 IIP3 and gain as a function of load resistance at IC ¼ 13 mA and VCE ¼ 3 V.

higher than the IIP3 with the avalanche current (ICB) nonlinearity alone (denoted by ). The interaction between individual nonlinearities has improved the overall linearity through cancellation. In this case, the two most dominating nonlinearities are the avalanche current ICB nonlinearity and the CCB nonlinearity. The cancellation between the ICB and CCB nonlinearities leads to an overall IIP3 value that is higher (better) than the IIP3 obtained using the ICB nonlinearity alone. The degree of cancellation depends on the biasing, source and load conditions, as expected from the Volterra series theory. Physically, the load dependence of linearity in these HBTs results from the CB feedback [6]. The first kind of such feedback is the CB capacitance CCB, and the second kind is the avalanche multiplication current ICB that flows from the collector to base. Both feedbacks are nonlinear, though the load dependence would still exist for linear CB feedback [7] (for instance, externally connected linear CB capacitance).

Linearity Limiting Factors Figure 4.7.10 shows the dominant nonlinearity factor on the IC–VCE plane. The upper limit of IC is where fT reaches its peak value. Avalanche multiplication and CCB nonlinearities are the dominant factors for most of the bias currents and voltages. Both avalanche multiplication and CCB nonlinearities can be reduced by reducing the collector doping. This, however, conflicts with the need for high collector doping required to suppress Kirk effect and heterojunction barrier effects in SiGe HBTs. Therefore, multiple collector-doping profiles are needed to provide both high fT devices and high IIP3 devices for different stages of the same circuit. Typical SiGe processes offer HBTs with different collector-doping profiles through selective collector implantations. Circuit designs could use the higher breakdown voltage devices when fT is sufficient, which may provide better linearity.

4.7.5 Summary Despite the strong I–V and C –V nonlinearities, SiGe HBTs can be used to design highly linear RF amplifiers. The avalanche multiplication nonlinearity can be minimized by proper choice of biasing current density and voltage. Linearity in general can be improved by increasing the biasing current, and parasitic or intentionally used feedbacks also help improving linearity. All the capacitances, either internal or external CBE and CCB, help improving linearity through negative feedback at the expense of gain. The nonlinear contributions from various I–V and C–V nonlinearities cancel out each other to certain extent, depending on the impedance of the linear circuit admittance matrix at both the

© 2006 by Taylor & Francis Group, LLC

4.7-486

The Silicon Heterostructure Handbook

Dominant nonlinearity 60

50

CCB CB Capacitance

IC (mA)

40

30

ICB Avalanche Multiplication

20

10

ICE−VBE

0 1

1.5

2

2.5

3

3.5

VCE (V)

FIGURE 4.7.10

Dominant nonlinearity factor on the IC–VCE plane.

fundamental and harmonic frequencies, which can be utilized for further linearity improvement, e.g., through harmonic tuning. Both the CCB and ICB (avalanche) nonlinearities depend on the collectordoping profile, which can be optimized for linearity improvement. The higher breakdown voltage lower speed HBTs in commercial SiGe processes can be used in circuit design for linearity leverage.

Acknowledgments The author would like to thank Q. Liang for help in preparation of the manuscript. This work is supported by NSF under ECS-0112923 and ECS-0119623 and SRC under SRC-2001-NJ-937 and SRC-2003-NJ-1133.

References 1. DD Weiner and JE Spina. Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits. Van Nostrand Reinhold, New York, 1980. 2. P Wambacq and W Sansen. Distortion Analysis of Analog Integrated Circuits. Kluwer Academic, Dordrecht, 1998. 3. S Narayanan. Transistor distortion analysis using Volterra series representation. Bell Syst. Tech. J. 46:991–1024, 1967. 4. H Jos. Technology developments driving evolution of cellular phone power amplifiers to integrated RF front-end modules. IEEE J. Solid-State Circ. 36:1382–1389, 2001. 5. GF Niu, JD Cressler, S Zhang, U Gogineni, and DC Ahlgren. Measurement of collector–base junction avalanche multiplication effect in advanced UHV/CVD SiGe HBTs. IEEE Trans. Electron Dev. 46:1007–1015, 1999.

© 2006 by Taylor & Francis Group, LLC

Linearity

4.7-487

6. GF Niu, QQ Liang, JD Cressler, C Webster, and DL Harame. RF linearity characteristics of SiGe HBTs. IEEE Trans. Micro. Theory Tech. 49:1558–1565, 2001. 7. GF Niu, JD Cressler, WE Ansley, CS Webster, R Anna, and N King. Intermodulation characteristics of UHV/CVD SiGe HBTs. Proc. IEEE Bipolar/BiCMOS Circ. Tech. Meeting, 1999, pp. 50–53. 8. G Gielen and W Sansen. Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer Academic, Dordrecht, 1991. 9. V Aparin and LE Larson. Analysis and reduction of cross-modulation distortion in CDMA receivers. IEEE Trans. Micro. Theory Tech. 35:1591–1602, 2003. 10. KL Fong. High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network. IEEE J. Solid-State Circ. 35:1249–1252, 2000. 11. QQ Liang, JM Andrews, JD Cressler, and GF Niu. General Analysis of the impact of harmonic impedance on linearity, with applications to SiGe HBTs. Proc. of IEEE Bipolar/BiCMOS Circ. Tech. Meeting, pp. 48–51, 2004. 12. S Maas, B Nelson, and D Tait. Intermodulation in heterojunction bipolar transistors. IEEE Trans. Micro. Theory Tech. 40:442–448, 1992. 13. GF Niu, WE Ansley, S Zhang, JD Cressler, C Webster, and R Groves. Noise parameter optimization of UHV/CVD SiGe HBTs for RF and microwave applications. IEEE Trans. Electron Dev. 46:1347– 1354, 1999.

© 2006 by Taylor & Francis Group, LLC

4.8 pnp SiGe HBTs

John D. Cressler Georgia Institute of Technology

4.8.1 4.8.2 4.8.3 4.8.4 4.8.5

Introduction............................................................... 4.8-489 Simulation of pnp SiGe HBTs.................................. 4.8-490 Profile Optimization Issues ...................................... 4.8-490 Stability Constraints in pnp SiGe HBTs.................. 4.8-494 Summary .................................................................... 4.8-495

4.8.1 Introduction At present, SiGe technology development is almost exclusively centered on npn SiGe HBTs. For highspeed analog and mixed-signal circuit applications, however, it is well known that a complementary (npn þ pnp) bipolar technology offers significant performance advantages over an npn-only technology [1]. Push–pull circuits, for instance, ideally require a high-speed vertical pnp transistor with comparable performance to the npn transistor [2]. The historical bias in favor of npn Si BJTs is due to the significantly larger minority electron mobility in the p-type base of an npn Si BJT, compared to the lower minority hole mobility in the n-type base of a pnp Si BJT. In addition, the valence band offset in SiGe strained layers is generally more conducive to npn SiGe HBT designs, because it translates into an induced conduction band offset and band grading that greatly enhance minority electron transport in the device, thereby significantly boosting transistor performance over a similarly constructed npn Si BJT. It has been shown that this band alignment is not as restrictive, however, as has been commonly assumed [3]. For a pnp SiGe HBT, on the other hand, the valence band offset directly results in a valence band barrier, even at low injection, which strongly degrades minority hole transport and thus limits the frequency response. Careful optimization to minimize these hole barriers in pnp SiGe HBTs is thus required, and has in fact yielded impressive device performance compared to Si pnp BJTs, as demonstrated in the pioneering work reported in Refs. [4–6]. Very recently, in fact, the first commercial complementary SiGe HBT BiCMOS technologies have been reported, in one case targeting high-speed and high-voltage analog circuit applications [7], and the other demonstrating impressive levels of pnp SiGe HBT performance, in this with a peak fT / fmax of 80/ 120 GHz at a BVCEO of 2.6 V [8]. Details of these impressive complementary SiGe technology demonstrations are given in Chapters 3.9 and 3.11, respectively. An analysis of the inherent profile design differences between npn and pnp SiGe HBTs is relevant in this context of complementary SiGe HBT technologies, as well as meaningful design guidelines for constructing pnp SiGe HBTs. Relevant questions include, for instance: . .

. .

How does SiGe npn and pnp profile design fundamentally differ? Can a single Ge profile design point be used for both npn and pnp transistors, for a given stability constraint? Is a graded-base Ge profile design preferable to a box-shaped Ge profile design for pnp HBTs? How much Ge retrograding in the collector–base junction is required to obtain acceptable SiGe pnp HBT performance?

4.8-489 © 2006 by Taylor & Francis Group, LLC

4.8-490

The Silicon Heterostructure Handbook

These issues are addressed using calibrated device simulations to shed light on the fundamental SiGe profile design differences between npn SiGe HBT and pnp SiGe HBTs that might be encountered, for instance, in developing such a viable complementary SiGe HBT technology [9].

4.8.2 Simulation of pnp SiGe HBTs One-dimensional MEDICI simulations [10] which were used to analyze the differences in intrinsic profile design between pnp and npn transistors are the central focus. To aid in interpretation of the results, simplistic hypothetical npn and pnp SiGe profiles with constant emitter, base, and collector doping, and a Ge content not subject to thermodynamic stability constraints, were initially adopted (Figure 4.8.1). These profile assumptions are clearly nonphysical for real SiGe technologies, but are very useful for comparing npn and pnp devices so that their differences can be more easily discriminated and not masked by doping-gradient-induced phenomena (stability issues will be addressed below). This artificial assumption on constant doping clearly yields ac performance numbers (e.g., fT) that are lower than what would be expected for a real complementary SiGe HBT technology, but relative comparisons between npn and pnp devices are nonetheless valid, and the comparison methodology widely applicable. MEDICI models of the devices were constructed using actual device layouts and measured SIMS data, and careful calibration of MEDICI simulations for both npn and pnp Si BJTs to measured complementary Si BJT hardware was performed. It was found that the default minority hole mobility modeling capability of MEDICI was deficient and tuning was required to obtain reasonable agreement between data and simulation, particularly under high-level injection. The SiGe model parameters determined from earlier calibrations of high-speed npn SiGe HBTs were used [3], and assumed to be the same for both npn and pnp transistors.

4.8.3 Profile Optimization Issues A comparison of the equilibrium conduction and valence band edges for both npn and pnp devices without any Ge retrograding into the collector (i.e., an abrupt transition from the peak Ge content to zero Ge content in the CB junction) is shown in Figure 4.8.2 and Figure 4.8.3 for: (1) a Si BJT; (2) a triangular (linearly graded) Ge profile with a peak Ge content of 10%; and (3) a triangular Ge profile with a peak Ge content of 25%. Observe that while there is no visible conduction band barrier present in the npn HBT, there is an obvious valence band barrier in the pnp HBT, even for low Ge content. This is

1020

30 25

E

Ge

1019

20

1018

15

1017

10

1016 1015 0.0

B

Ge Concentration (%)

Doping concentration (cm−3)

1021

5

C

0 0.2

0.4

0.6

0.8

1.0

Depth (µm)

FIGURE 4.8.1 Hypothetical doping and Ge profiles for both pnp and npn SiGe HBTs. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-491

pnp SiGe HBTs

1.0 Conduction band edge (eV)

Si 0.8

npn SiGe HBT

10% peak 25% peak

0.6

0.4

VBE = 0.0 V V BC = 0.0 V T = 300 K Ge profile

0.2

0.0 0.15

0.20

0.25

0.30

0.35

0.40

Depth (µm)

FIGURE 4.8.2 Valence band edge of an npn SiGe HBT for varying peak Ge content. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

Valence band edge (eV)

0.0 pnp SiGe HBT

−0.2 −0.4 −0.6

V BE = 0.0 V V BC = 0.0 V T = 300 K

Ge profile

10% peak

25% peak −0.8

qF B Si

−1.0 0.15

0.20

0.25

0.30

0.35

0.40

Depth (µm)

FIGURE 4.8.3 Simulated conduction band edge of a pnp SiGe HBT for varying peak Ge content. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

consistent with the fact that there is a valence band offset in strained SiGe on Si (refer to Chapter 4.2), and clearly indicates that pnp SiGe HBT design is inherently more difficult than npn SiGe HBT design. In addition, due to the inherent minority carrier mobility differences between electrons and holes, it is also clear that npn devices will consistently out-perform pnp devices, everything else being equal. Unlike for a well-designed npn SiGe HBT (i.e., Ge outside the neutral base edges), where conduction band barrier effects are uncovered only at high JC under Kirk effect [3] (refer to Chapter 4.3), the valence band barrier in pnp SiGe HBTs is in play even at low injection, and acts to block minority holes transiting the base. This pileup of accumulated holes produces a retarding electric field in the base, which compensates the Ge-grading-induced drift field, dramatically decreasing both JC, b, and fT. This effect worsens as the current density increases, since more hole charge is stored in the base. In this case, the fT of the pnp SiGe HBT is in fact significantly lower than that of the pnp Si BJT. As expected, however, retrograding of the Ge edge into the collector can ‘‘smooth’’ this valence band offset in the pnp

© 2006 by Taylor & Francis Group, LLC

4.8-492

The Silicon Heterostructure Handbook

SiGe HBT, and thus improve this situation dramatically, although at the expense of film stability [4, 5]. For an increase of the Ge retrograde from 0 to 40 nm, the pnp SiGe HBT performance is dramatically improved, yielding roughly a 2
increase in peak fT over the pnp Si BJT performance at equal doping. Figure 4.8.4 and Figure 4.8.5 show the variation in peak fT and b as a function of peak Ge content for both npn and pnp SiGe HBTs for both a 0-nm Ge retrograde and 100-nm Ge retrograde. At 100-nm retrograde, the performance of the pnp SiGe HBT monotonically improves as the Ge content rises, while the maximum useful Ge content is limited to about 10% without retrograding. Figure 4.8.6 indicates that 40–50 nm of Ge retrograding in the pnp SiGe HBT is sufficient to ‘‘smooth’’ the valence band barrier, and this is reflected in Figure 4.8.7, which explicitly shows the dependence of pnp peak fT on Ge retrograde distance, for both triangular and box Ge retrograde profile shapes. Observe that the box Ge retrograde is not effective in improving the pnp SiGe HBT performance, since it does not smooth

50 Peak cutoff frequency (GHz)

Base Collector Ge

40

100 nm retrograde

Retrograde 0 100 nm

30 npn 20

No retrograde

pnp

10 T = 300K 0 0

5

10 15 Peak Ge content (%)

20

25

FIGURE 4.8.4 Simulated peak cutoff frequency as a function of peak Ge content for different Ge retrogrades for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949– 1954, 2000. With permission.)

350 Base Collector

300

JC = 0.1 mA/µm2 Retrograde T = 300K

Ge Current gain

250 0

100 nm

200 100 nm retrograde 150 npn

100

No retrograde pnp

50 0 0

5

10 15 Peak Ge content (%)

20

25

FIGURE 4.8.5 Simulated current gain as a function of peak Ge content for different Ge retrogrades for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-493

pnp SiGe HBTs

−0.4 p+

Ge retrograde p

n

−0.6

25 20

100 nm 50 nm 40 nm

−0.8

−1.0 0.15

0.20

10

30 nm

qF B

10 nm 0 nm 0.25

0.30

0.35

0.40

15

Ge Concentration (%)

Valence band edge (eV)

30 V BE = 0.0 V V BC = 0.0 V T = 300 K

5

0.45

0 0.50

Depth (µm)

FIGURE 4.8.6 Valence band edge of a pnp SiGe HBT as a function of Ge retrograde distance. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

50 Peak cutoff frequency (GHz)

npn 40 Base Collector 30

Box-like extension

Ge

Triangle retrograde

20

0

10

100 nm Peak Ge = 25% V = 1.0 V T = 300 K

pnp

0 0

20

40

60

80

100

Retrograde distance (nm)

FIGURE 4.8.7 Simulated peak cutoff frequency as a function of both Ge retrograde distance and Ge profile shape for both npn and pnp SiGe HBTs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949– 1954, 2000. With permission.)

the Ge barrier, but rather only pushes it deeper into the collector, where it is still felt at the high JC needed to reach peak fT. This box Ge retrograde is also clearly undesirable from a stability standpoint. The effects of Ge retrograding on the npn SiGe HBT performance, on the other hand, are minor, while the film stability is significantly worse due to the additional Ge content. This suggests that using one Ge profile design for both npn and pnp SiGe HBTs is not optimum for high-peak Ge content values. Note that while the peak fT is unchanged with Ge retrograding in the npn SiGe HBT, the fT response above peak fT does not roll off as rapidly due to the high-injection-induced barrier, consistent with the results in Ref. [3] (refer to Chapter 4.3). An examination of the frequency response of the npn and pnp SiGe HBTs as a function of front-side Ge profile shape (in this case, triangle versus box Ge profile, with a fixed retrograde of 100 nm for both) and peak Ge content shows that for the npn SiGe HBT, the base transit time reduction from the Gegrading-induced drift field of the triangle Ge profile shape gives a significant advantage above 10% peak

© 2006 by Taylor & Francis Group, LLC

4.8-494

The Silicon Heterostructure Handbook

Ge, indicating that the npn SiGe HBT is base transit time limited. Interestingly, for the pnp SiGe HBT, however, the differences between the box and triangle Ge profiles are much less pronounced, everything else being equal. The box Ge profile gives a slight advantage at low Ge content due to the low b and hence importance of the emitter transit time (tE / 1/b), but once the b is sufficiently high, the triangle Ge profile dominates at higher peak Ge content, where the base transit time limits the overall response. In both npn and pnp devices, the triangle Ge profile offers better performance and better stability (lessintegrated Ge content), and thus can be considered an optimum shape for both devices. This is even more apparent if we examine the Early voltage of the devices, a key figure-of-merit for complementary analog circuits. In this case, the triangle Ge profile has a clear advantage due to its graded bandgap, as expected, and both npn and pnp transistors show a significant improvement in VA with increasing Ge content.

4.8.4 Stability Constraints in pnp SiGe HBTs The total amount of Ge that can be put into a given SiGe HBT is limited by the thermodynamic stability criterion. Above the critical thickness, the strain in the SiGe film relaxes, generating defects. In general, varying peak Ge content or retrograde distance (i.e., film thickness) moves the profile along different contours in stability space (Figure 4.8.8). Under the SiGe stability constraint, the peak Ge content must be traded off for the Ge retrograde distance in the collector–base junction. Figure 4.8.9 shows that a 11% peak Ge profile with a 25-nm retrograde gives the highest fT for the pnp SiGe HBT at this design point. A similar exercise for the npn SiGe HBT shows that the ac performance is not sensitive to the SiGe profile shapes used, and, hence, without a significant loss of performance, the same Ge profile may in principle be used for both pnp and npn SiGe HBTs. This may be advantageous from a fabrication viewpoint. These results should be valid for current SiGe technology nodes with about 100-nm base width. If the base width is further reduced with technology scaling, the peak Ge content can be obviously increased, while maintaining film stability. The same optimization methodology employed here can be used in that case to determine the best SiGe profile for both devices.

400

Effective thickness (nm)

(1)

300

peak Ge from 8% to 13% (step = 1%)

(2)

(3) peak Ge = 11%

(4)

100 nm E B

25 nm C

200

Retrograde from 0 to 40 nm (step = 10 nm) 100 nm E B

40 nm C

100 0

0.0005

0.001 0.0015 Effective strain

0.002

FIGURE 4.8.8 SiGe stability diagram illustrating the various pnp profile design tradeoffs. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.8-495

pnp SiGe HBTs

20 Base Collector Retrograde

Ge Cuttoff frequency (GHz)

(1) peak Ge = 10% Retro = 39 nm

15

(2) peak Ge = 11% Retro = 25 nm (3) peak Ge = 12.5% Retro = 9 nm (4) peak Ge = 13% Retro = 5 nm

0

pnp

10 SiGe

5

0

Si

10−5

10−4 JC

(A/µm2)

FIGURE 4.8.9 Simulated cutoff frequency as a function of collector current density for pnp SiGe HBTs with different Ge profiles. Refer to Figure 4.4.8 for the exact profile shapes. (From G Zhang, JD Cressler, G Niu, and A Pinto. Solid-State Electronics 44:1949–1954, 2000. With permission.)

4.8.5 Summary In spite of the historical bias in favor of npn SiGe HBTs, complementary (npn þ pnp) SiGe HBT technology has recently emerged as a viable mixed-signal technology. In this chapter, we have examined the fundamental profile design constraints associated with pnp SiGe HBTs, and importantly, how those constraints differ from those faced in conventional npn SiGe HBT design.

Acknowledgments I am grateful to G. Zhang, G. Niu, and D. Harame for their contributions. This work was supported by the GEDC at Georgia Tech and IBM.

References 1. JD Cressler, J Warnock, DL Harame, JN Burghartz, KA Jenkins, and CT Chuang. A high-speed complementary silicon bipolar technology with 12 fJ power-delay product. IEEE Electron Device Letters 14:523–526, 1993. 2. CT Chuang, JD Cressler, and JD Warnock. ac-coupled complementary push-pull ECL circuits with 34 fJ power-delay product. Electronics Letters 29:1938–1939, 1993. 3. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 4. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base pnp transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest of the IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 5. DL Harame, BS Meyerson, EF Crabbe´, JM Cotte, JMC Stork, AC Megdanis, GL Patton, SR Stiffler, JB Johnson, JD Warnock, JH Comfort, and JY-C Sun. 55 GHz polysilicon-emitter graded SiGe-base pnp transistors. Technical Digest of the IEEE Symposium on VLSI Technology, Oiso, Japan, 1991, pp. 71–72.

© 2006 by Taylor & Francis Group, LLC

4.8-496

The Silicon Heterostructure Handbook

6. DL Harame, JH Comfort, EF Crabbe´, JD Cressler, JD Warnock, BS Meyerson, KY-J Hsu, J Cotte, CL Stanis, JMC Stork, JY-C Sun, DA Danner, and PD Agnello. A SiGe-base pnp ECL circuit technology. Technical Digest of the IEEE Symposium on VLSI Technology, Honolulu, 1993, pp. 61–62. 7. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schultz, L Swanson, D Tatman, M Waitschull, J Weijtmans, and C Willis. A 5 V complementary-SiGe BiCMOS technology for high-speed precision circuits. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 211–214. 8. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Hoppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Rucker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high-speed npn and pnp SiGe:C HBTs Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 9. G Zhang, JD Cressler, G Niu, and A Pinto. A comparison of npn and pnp profile design tradeoffs for complementary SiGe HBT technology. Solid-State Electronics 44:1949–1954, 2000. 10. MEDICI. 2-D Semiconductor Device Simulator, Avant!, Fremont, CA, 1997.

© 2006 by Taylor & Francis Group, LLC

4.9 Temperature Effects 4.9.1 4.9.2

John D. Cressler Georgia Institute of Technology

4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8

Introduction............................................................... 4.9-497 The Impact of Temperature on Bipolar Transistors .................................................................. 4.9-497 Cryogenic Operation of SiGe HBTs ........................ 4.9-498 Design Constraints .................................................... 4.9-500 Optimization of SiGe HBTs for 77 K....................... 4.9-501 Helium Temperature Operation .............................. 4.9-506 High-Temperature Operation .................................. 4.9-506 Summary .................................................................... 4.9-509

4.9.1 Introduction Bandgap engineering generally has a positive influence on the low-temperature characteristics of bipolar transistors [1]. SiGe HBTs operate very well, in fact, in the cryogenic environment (e.g., liquid nitrogen temperature ¼ 77.3 K ¼
3208F ¼
1968C), an operational regime traditionally forbidden to Si BJTs. At present, cryogenic electronics represents a small but important niche market, with applications such as high-sensitivity cooled sensors and detectors, semiconductor–superconductor hybrid systems, space electronics, and eventually cryogenically cooled computers systems. While the large power dissipation associated with conventional bipolar digital circuit families such as emittercoupled-logic (ECL) would likely preclude their widespread use in cooling-constrained cryogenic systems, the combination of cooled, low-power, scaled Si CMOS with SiGe HBTs offering excellent frequency response, low-noise performance, radiation hardness, and excellent analog properties represents a unique opportunity for the use of SiGe HBT BiCMOS technology in cryogenic systems. Furthermore, independent of the potential cryogenic applications that may exist for SiGe HBT BiCMOS technology, all electronic systems must successfully operate over an extended temperature range (e.g.,
55 to 1258C to satisfy military specifications and 0 to 858C for most commercial applications), and thus, understanding how Ge-induced bandgap engineering affects SiGe HBT device and circuit operation is important. In this chapter, we address temperature effects in SiGe HBTs, by first reviewing the impact of temperature on bipolar transistor device and circuit operation. We then show how temperature couples to SiGe HBT dc and ac performance, how one optimizes SiGe HBTs specifically for cryogenic operation, and finally consider the operation of SiGe HBTs at elevated temperatures (to 3008C).

4.9.2 The Impact of Temperature on Bipolar Transistors The detrimental effects of cooling on homojunction bipolar transistor operation have been appreciated for many years [2–6]. While the precise dependence of Si BJT properties on cooling can be a strong function of technology generation and profile design, Si BJT device and circuit properties cooled to cryogenic temperatures typically exhibit [7–12]: 4.9-497 © 2006 by Taylor & Francis Group, LLC

4.9-498

.

.

.

. . .

. .

The Silicon Heterostructure Handbook

A modest increase (degradation) in the junction turn-on voltage with decreasing temperature (monotonic). A strong increase (improvement) in the low-injection transconductance with cooling (monotonic). A strong increase (degradation) in the base resistance with cooling (typically, quasi-exponential below about 200 K). A mild decrease (improvement) in parasitic transistor depletion capacitances (monotonic). A strong decrease (degradation) in b with cooling (quasi-exponential). A modest decrease (degradation) in frequency response with cooling, with fT typically degrading more rapidly than fmax with decreasing temperature (monotonic below about 200 K). An increase (degradation) in ECL circuit delay with cooling (monotonic below about 200 K). The noise margin of current-switch-based digital circuits (e.g., ECL) increases (improves) with cooling (monotonic), allowing reduced logic swing operation.

The impact of cooling of Si BJTs is typically largely one of serious device and circuit performance degradations, effectively precluding their use in cryogenic applications. The addition of SiGe to this problem can be used to change this situation dramatically.

4.9.3 Cryogenic Operation of SiGe HBTs Intuitively, we expect that band-edge effects induced by bandgap engineering will generally couple strongly to bipolar transistor properties. This strong coupling is physically the consequence of the fact that the bipolar transistor is a minority carrier device, and hence the terminal currents are proportional to ni02 via the Shockley boundary conditions, with ni02 in turn proportional to the exponential of the bandgap. Hence, changes to the bandgap will couple exponentially to the currents. Furthermore, from very general statistical mechanical considerations, these bandgap changes will inevitably be divided by the thermal energy (kT), such that a reduction in temperature will greatly magnify any bandgap changes. Not surprisingly, then, even a cursory examination of the SiGe HBT device equations suggests that both the dc and ac properties of SiGe HBTs should be favorably affected by cooling [13, 14]. In fact, the thermal energy (kT), in every instance, is arranged in the SiGe HBT equations such that it favorably affects the low-temperature properties of the particular performance metric in question, be it b(T), fT(T ), or VA(T ). The beneficial role of temperature in SiGe HBTs can be used to easily offset the inherent bandgapnarrowing-induced degradation in current gain of a Si BJT to achieve viable dc operation down to 77 K, even for a SiGe HBT that has not been optimized for the cryogenic environment. Figure 4.9.1 shows the evolution of peak current gain as a function of reciprocal temperature from early Si BJT technologies circa 1978 to SiGe technologies circa 1992. Clearly, the addition of Ge-induced bandgap engineering enables functional current gain down at least to 77 K with minimal effort. From a dynamic point of view, the Ge-grading-induced base drift field provides a means to offset the inherent tb degradation associated with cooled Si BJTs, yielding an fT that does not degrade with cooling. Since the reduced thermal cycle nature of epitaxial growth techniques are generally more conducive to maintaining thinner, more heavily doped base profiles than conventional ion-implanted bases used in modern Si BJTs, it is fairly straightforward to control base freeze-out in SiGe HBTs, at least down to 77 K, and hence Rb at cryogenic temperatures can be more easily controlled. If fT and Rb do not degrade significantly with cooling, then achieving respectable circuit performance down to 77 K becomes a reality unknown to Si BJT technologies. Figure 4.9.2 shows the evolution of unloaded ECL gate delay as a function of publication date. As expected, optimized 300-K technology scaling successfully improved circuit speed over time. More surprising, perhaps, is that the rate of improvement in low-temperature performance was significantly faster. The 1991 and 1992 cryogenic data points are for SiGe HBT technologies, and clearly demonstrate that one can no longer out of hand dismiss Si-based bipolar technologies for

© 2006 by Taylor & Francis Group, LLC

4.9-499

Temperature Effects

Temperature (K) 300

Norm. current gain (b/b 300 K)

10

200

150 125

100

77 1992 SiGe

1.0

1990

.10

1987 1984

RBI = 6–8 kΩ/(300 K)

1978

.01 2

4

6

8 10 1000/T (K−1)

12

14

FIGURE 4.9.1 Evolution of current-gain temperature dependence with Si-based bipolar technology generation. The last two generations are SiGe HBT technologies. (From JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JYC Sun. IEEE Trans. Electron Dev. 40:525–541, 1993. With permission.)

Bipolar ECL gate delay (ps)

500 84 K 300 K

200 100 50 20 10 1980

21.9 ps (84 K) 1983

1986 1989 Publication date

1992

1995

FIGURE 4.9.2 Evolution of unloaded ECL gate delay at 310 and 84 K with Si-based bipolar technology generation. The last two generations are SiGe HBT technologies. (From JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JYC Sun. IEEE Trans. Electron Dev. 40:525–541, 1993. With permission.)

the cryogenic applications. SiGe can thus be viewed as an effective means to extend Si-based bipolar technology to the cryogenic environment (with little or no effort). This scenario is particularly appealing if we consider the state-of-the-art SiGe HBT BiCMOS technologies, since Si CMOS also performs well down to 77 K, and provides a major advantage in the reduction in power dissipation, an often serious constraint given the limited efficiency of cryocoolers. While it is unlikely that one would develop SiGe technology explicitly for cryogenic applications, if (as is the case) one could simply take a room temperatureoptimized SiGe technology and operate it at low temperatures without serious modification, that prospect might prove cost-effective. With the present trend toward reduced-temperature operation of CMOSbased high-end servers as a performance and reliability enhancement vehicle (currently at 0 to
408C and going lower), the appeal of SiGe HBT BiCMOS technologies for the cryogenic environment may naturally grow over time, since HBTs can provide numerous advantages over CMOS in analog, RF, heavily loaded digital, and high-speed driver or receiver applications. We first examine the expected theoretical temperature dependence of the important SiGe HBT performance metrics. Compared to a comparably constructed Si BJT, b(T ) in a SiGe HBT should increase exponentially with decreasing temperature, since

© 2006 by Taylor & Francis Group, LLC

4.9-500

The Silicon Heterostructure Handbook


  g~h ~DEg,Ge (grade)=kT eDEg,Ge (0)=kT bSiGe

’ : bSi
VBE 1
e
DEg,Ge (grade)=kT

(4:9:1)

As expected, a quasi-exponential increase in the SiGe-to-Si current gain ratio with decreasing temperature is typically observed experimentally. In addition, VA(T) and bVA(T) in a SiGe HBT should also increase exponentially with decreasing temperature compared to a comparably constructed Si BJT, since
 
DEg,Ge (grade)=kT VA,SiGe

DEg,Ge (grade)=kT 1
e ’e VA,Si
VBE DEg,Ge (grade)=kT

(4:9:2)

bVA,SiGe ¼ g~h ~eDEg,Ge (0)=kT eDEg,Ge (grade)=kT : bVA,Si

(4:9:3)

and

This is again confirmed experimentally. The anticipated temperature dependence of the frequency response of a SiGe HBT can be gleaned from the temperature dependence of the base and emitter transit times,  h i t b,SiGe 2 kT kT
DEg,Ge (grade)=kT ¼ 1
1
e h ~ DEg,Ge (grade) DEg;Ge (grade) t b,Si

(4:9:4)

and t e,SiGe JC,Si 1
e
DEg,Ge (grade)=kT ’ ¼ : DEg,Ge (grade) DEg,Ge (0)=kT t e,Si JC,SiGe e g~h ~ kT

(4:9:5)

Both are favorably influenced by cooling, and thus, we expect that the influence of the graded SiGe base is sufficient to overcome the inherent electron diffusivity degradation on tb with cooling, and this is indeed the experimental case.

4.9.4 Design Constraints While SiGe HBTs designed for room temperature operation function acceptably down to 77 K, secondorder design constraints do, nonetheless, exist, and can impact profile optimization [15, 16]. The first such constraint centers on the base current and its impact on the current gain at low injection. While conventional Shockley–Read–Hall (SRH) recombination exponentially decreases with cooling, thereby effectively eliminating reverse leakage in the collector–base junction, the same is not true of carrier tunneling processes, whether they are band-to-band or trap-assisted. Given that the EB junction of high-speed bipolar transistors (either Si or SiGe) are typically quite heavily doped (often in the vicinity of 1  1018 cm
3), the doping-induced electric field is high, and can result in substantial parasitic tunneling leakage. While this is generally easily designed around in 300-K designs, it is more problematic at low temperatures, given that the collector and base currents decrease strongly at fixed VBE as the temperature drops. In this case, as the base current decreases with cooling, any tunneling-induced leakage will remain roughly constant, hence uncovering a parasitic leakage ‘‘foot’’ on the base current (this effect can be clearly seen in Figure 4.9.3). This parasitic base leakage current can severely limit the current gain at low injection at cryogenic temperatures. Thus, as a rule of thumb, it can be safely stated that the ideality of the base current of a high-performance Si or SiGe bipolar transistor will never improve with cooling. If the base current is ideal (i.e., eqVBE/kT) down to a picoampere at 300 K, it may be ideal only to a nanoampere

© 2006 by Taylor & Francis Group, LLC

4.9-501

Collector and base currents (A)

Temperature Effects

10−2

10−4

1.0 mA/µm2 SiGe HBT "emitter–cap" profile AE = 1.4⫻4.4 µm2 VCB = 0.0 V

10−6

10−8

10−10 0.4

300 K

IC

77 K

5.84 K

IB

0.6

0.8 1.0 Base−emitter voltage (V)

1.2

FIGURE 4.9.3 Gummel characteristics at 300, 77, and 5.84 K for a 77-K optimized emitter-cap SiGe HBT. (From AJ Joseph, JD Cressler, and DM Richey. IEEE Electron Dev. Lett. 16:268–270, 1995. With permission.)

at 77 K. If it is even modestly non-ideal at 300 K, it will be quite leaky at 77 K. How serious a limitation this leakage is depends strongly on the circuit application. In digital logic, for instance, it is not an issue, given that the devices are biased well out of the leakage regime, and b does not strongly couple to circuit speed. For more sensitive analog circuits, however, it can in principle require careful design consideration. As discussed below, one can optimize a SiGe HBT to reduce this leakage effect, a feat much more easily accomplished using epitaxial growth rather than ion-implantation for the base layer formation. More worrisome than the base current at low temperatures, however, is the enhancement of highinjection, heterojunction barrier effects with cooling (refer to Chapter 4.3 for a detailed discussion of barrier effects in SiGe HBTs). Band-edge effects in bipolar transistors generally couple very strongly to the device properties, and barrier effects are no exception. In this case, given that barrier effects necessarily exist in all practical SiGe HBTs, cooling will make the situation decidedly worse. The consequences of barrier effects, as at room temperature, include a premature roll-off in both b and fT at high JC, and a limitation on maximum output current drive. What is different in the context of cryogenic operation, however, is that while a well-designed 300-K SiGe HBT may not show any clear evidence of barrier effect at 300 K, it will certainly show evidence of it at 77 K, and its impact on device performance will be correspondingly worse. That is, the design margin for 77-K operation is in essence narrower, always an undesirable situation. As discussed in Chapter 4.3, the device transconductance is a useful tool for assessing barrier effects in SiGe HBTs. A comparison of gm between comparably designed i–p–i SiGe HBTs and i–p–i Si BJTs clearly shows that while gm at low JC increases with cooling as expected, a dramatic drop in gm at a higher critical current density close to that of Kirk effect can be observed in the SiGe HBT. Fortunately, it is also true that this critical onset current density in fact increases with cooling, consistent with the fact that the saturation velocity rises at low temperatures, thus delaying Kirk effect until higher JC. As discussed below, this result can be traded off to optimize SiGe HBTs for 77 K operation. One would also expect that barrier effect would have a serious impact on transistor dynamic response, given that enhanced charge storage in the base couples strongly to fT. The approaches that can be used to design around barrier effects at cryogenic temperatures are the same as those outlined in Chapter 4.3, albeit with a narrower design margin than at 300 K.

4.9.5 Optimization of SiGe HBTs for 77 K While conventional 300-K SiGe HBT designs will inherently function reasonably well down to 77 K, it remains to be seen whether a SiGe HBT designed specifically for 77 K operation can achieve significantly

© 2006 by Taylor & Francis Group, LLC

4.9-502

The Silicon Heterostructure Handbook

better device and circuit performance at 77 K than it has at 300 K, and what the design issues and tradeoffs faced in achieving this goal would be. To address the explicit optimization of a SiGe HBT for 77 K operation, a new profile design point and fabrication scheme is required [17]. In this case an epitaxial ‘‘emitter-cap’’ layer doped with phosphorus at about 11018 cm
3 was deposited in situ in a UHV/CVD deposition tool on top of the SiGe-base to form the EB junction. This 77-K optimized SiGe HBT will be referred to as an epitaxial ‘‘emitter-cap’’ SiGe HBT [18]. Because EB carrier tunneling processes depend exponentially on the peak junction field, the lightly doped emitter is expected to minimize the parasitic EB tunneling current compared to a conventional ‘‘i–p–i’’ SiGe HBT design. In addition, the increase in carrier saturation velocity with cooling, as well as the presence of velocity overshoot in the CB space–charge region at 77 K, results in an onset current density of base push-out (Kirk effect) that is about 50% larger at 77 K than at 300 K [15]. Thus, compared to a 300-K design, the collector doping level can be decreased in an optimized 77-K profile. In this case, the doping level at the metallurgical CB junction was lowered from 11017 cm
3 for the conventional SiGe HBT design to about 21016 cm
3, and ramped upward toward the subcollector to minimize freeze-out deep in the neutral collector. This 77-K collector profile is used to reduce the parasitic CB capacitance under the constraint that the onset current density of the SiGe–Si heterojunction barrier be above the maximum operating current density of about 1.0 mA/mm2. To ensure a low emitter resistance, a 200-nm in situ doped polysilicon contact was deposited on top of the composite EB profile (n-cap/p-SiGe). Because the arsenic out-diffusion from the heavily doped polysilicon layer is used only to contact the epitaxial phosphorus emitter and does not determine the metallurgical EB junction, only a very short rapid thermal annealing (RTA) step is required to activate and redistribute the emitter dopants, allowing the maintenance of a thin, heavily doped base. A metallurgical emitter-cap thickness of about 10 nm was achieved at the end of processing (estimated by subtracting the arsenic out-diffusion of the emitter poly from the total EB junction depth). The boron doping of the base profile was increased over a more conventional i–p–i SiGe design to improve its base freeze-out properties, and was deposited as a box 10 nm wide by 2.5  1019 cm
3. At the end of processing the metallurgical base was about 75 nm wide with a peak concentration of about 8  1018 cm
3, well above the Mott transition for carrier freeze-out. To minimize minority carrier charge storage in the emitter-cap layer, a large 77 K b is also desirable (te / 1/bac). Therefore, a trapezoidal Ge profile with 3 to 4% Ge at the EB junction (compared to about 0 to 1% for the standard design) and ramping to 8.5% at the CB junction (compared to about 8.5% for the standard design) was used. The resultant emitter-cap Ge profile was about 65 nm thick, and satisfied the thermodynamic stability criteria for UHV/CVD blanket films. This 77-K SiGe design point yields a transistor with reasonably ideal Gummel characteristics at low temperatures, with a maximum output current drive well above 1.0 mA/mm2 at 84 K (Figure 4.9.3). The higher Ge concentration at the EB junction, the beneficial effects of the emitter high–low (nþ/n
cap) junction, and the bandgap narrowing of the heavily doped base, offset the bandgap narrowing of the heavily doped emitter region to yield a peak b that increases quasi-exponentially with cooling from 102 at 310 K to 498 at 84 K (Figure 4.9.4). This large b value at low temperatures serves to minimize the unwanted charge storage associated with the emitter-cap layer as well as to circumvent the degradation of b at medium injection levels due to bias-dependent Ge ramp effects (refer to Chapter 4.3), giving an ideal value of b of 99 at 84 K at a typical circuit operating point of 1.0-mA collector current [18]. An undesirable result of the high b at low temperature, however, is a decrease in the BVCEO from 3.1 V at 310 K to 2.3 V at 84 K, but it remains acceptable for most circuit applications. Depending on circuit requirements at 77 K, the low-temperature current gain can be easily tuned to a desired value. The reduction in overall thermal cycle compared to a conventional design is key to maintaining the abrupt, as-deposited boron base profile, and thus providing immunity to carrier freeze-out at cryogenic temperatures (Rbi only increases from 7.7 to 11.0 kV/sq. between 310 and 84 K). Importantly, this immunity to base freeze-out does not come at the expense of increased EB leakage, as it does, for instance, in a spacer-free SiGe profile with a very heavily doped base [15]. The lower doping level of the emitter-cap layer results in a reverse EB leakage at 1.0 V at 84 K, which is more than 500 times smaller

© 2006 by Taylor & Francis Group, LLC

4.9-503

Temperature Effects

1100

Current gain

880

SiGe HBT ("emitter–cap") AE = 1.4⫻4.4 µm2 VCB = 0.0 V

5.84 K

35 K 660 77 K 440 142 K 220 300 K 0 10−6

10−5

10−4 10−3 Collector current (A)

10−2

FIGURE 4.9.4 Current gain versus bias current as a function of temperature for a 77-K optimized emitter-cap SiGe HBT. (From AJ Joseph, JD Cressler, and DM Richey. IEEE Electron Dev. Lett. 16:268–270, 1995. With permission.) 80

Cutoff frequency (GHz)

AE = 0.7⫻19.4 µm2 VCB = 1.0 V

tEC = 2.3 ps (85 K) tEC = 3.2 ps (300 K)

60 85 K 40

20

300 K

0 1

10 Collector current (mA)

100

FIGURE 4.9.5 Cutoff frequency characteristics at 300 and 85 K for a 77-K optimized emitter-cap SiGe HBT. (From JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. IEEE Electron Dev. Lett. 15:472–474, 1994. With permission.)

than for the conventional SiGe design. The consequence is a much smaller forward tunneling component in the base current (much larger low-current b), a smaller EB capacitance, and an expected improvement in hot-carrier reliability at cryogenic temperatures. As shown in Figure 4.9.5, the transistor cutoff frequency ( fT) rises from 43 to 61 GHz with cooling to 85 K due to the beneficial effects of the Ge-grading-induced drift field. This improvement in fT, coupled to the low total base resistance and slightly decreased CB capacitance, yields an increase in maximum oscillation frequency with cooling as well, from 40 GHz at 310 K to 50 GHz at 84 K. To assess the 77-K circuit capabilities of this technology, unloaded ECL ring oscillators were measured (Figure 4.9.6). Highpower (12.45 mW) ECL circuits switch at a record 21.9 psec at 84 K, 3.5 psec faster than at 310 K. Circuits that were optimized for lower power operation achieve a minimum power-delay product of 61 fJ (41.3 psec at 1.47 mW) at 84 K, and are 9.6 psec faster than at 310 K. These 77-K optimized ECL circuits are expected to exhibit even more dramatic improvements in speed over room-temperature ECL circuits under heavy loading, due to the beneficial effects of cooling on metal interconnect resistance and

© 2006 by Taylor & Francis Group, LLC

4.9-504

The Silicon Heterostructure Handbook

70

ECL gate delay (ps)

60

VL = 500 mV

50

310 K

FI/FO = 1

40

84 K

CW = 6 fF

30 310 K 41.3 ps at 1.47 mW (61 fJ)

84 K

20 21.9 ps AE = 0.52⫻1.52 µm2 AE = 0.72⫻4.42 µm2 10 0.1

0.2

0.3 0.5 0.7 1.0 2 Average switch current (mA)

3

4 5 6

FIGURE 4.9.6 Unloaded ECL gate delay as a function of power at 310 and 84 K. (From JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. IEEE Electron Dev. Lett. 15:472–474, 1994. With permission.)

circuit logic swing [16]. The delay improvement at long interconnect wire lengths can be dramatic (2.7 faster at 84 K than at 300 K at 10 mm wire length), and suggests that SiGe HBT based line-drivers might be attractive for 77-K applications. Recent measurements on non-cryogenically optimized 200 GHz, third-generation SiGe HBTs, show even more impressive performance down to liquid nitrogen temperature [19]. Current–voltage measurements across the 300 to 85 K temperature range were made on SiGe HBTs with an emitter area of 0.12  10.0 mm2. In spite of the high peak base and emitter doping levels associated with these aggressively scaled SiGe HBTs (>1019 cm
3), the base current remains reasonably ideal at 85 K. This is the result of the lightly doped epitaxial spacer layer inserted between the base and emitter regions, and helps limit field-assisted tunneling and recombination at low temperatures. The base and emitter regions in this device are both doped above the Mott-transition, and ensure that carrier freeze-out does not negatively impact the base or emitter resistance below 100 K. This device is capable of very high current density operation (>25 mA/mm2), and thus the high collector doping level effectively limits the impact of heterojunction barrier effects at low temperatures. The current gain increases monotonically with cooling, from 600 at 300 K to 3800 at 85 K (Figure 4.9.7). Two mechanisms are responsible for this improvement with cooling: (1) the (sizable) Ge-induced band offset in this device (exponentially) increases the current gain with cooling, and (2) the heavily doped base region partially offsets the doping-induced bandgap narrowing associated with the emitter region. There is a strong decrease in the current gain above its peak value at 85 K associated with the Ge-grading effect, but the current gain remains above 2000 at 85 K at the current density at which peak fT is reached, effectively minimizing any emitter charge storage at low temperatures. Figure 4.9.7 also shows the extracted peak cutoff frequency versus temperature for the 0.12  10.0 mm2 SiGe HBT. An increase in peak fT from 200 GHz at 300 K to 260 GHz at 85 K is observed. This increase in the peak fT with cooling is proportionately smaller than has been reported in first-generation SiGe HBTs (Figure 4.9.5) operated at 85 K. This is because in the present case, the base and emitter transit times in this 200 GHz device, which are favorably affected by both the Ge-grading and cooling, are already small compared to the collector delay time, and thus their relative influence on the total transit time with cooling is smaller. The extrapolated total emitter-to-collector delay decreases from 0.7 psec at 300 K to 0.6 psec at 150 K and 0.5 psec at 85 K, and the total depletion capacitance of the device decreases with cooling, as expected, since the junction built-in voltages increase with cooling.

© 2006 by Taylor & Francis Group, LLC

4.9-505

Temperature Effects

4000

400

3500

350 Peak current gain

3000 2500

300

2000 250 1500 1000

200

Peak cutoff frequency (GHz)

AE = 0.12 µm⫻10 µm VCE = 1.2 V

500 50

100

150 200 250 Temperature (K)

300

150 350

FIGURE 4.9.7 Peak current gain and peak cutoff frequency as a function of temperature for a third-generation SiGe HBT. (From B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. With permission.)

AE = 0.12 µm⫻10 µm

Minimum noise figure (dB)

85 K

VCE = 1.2 V IC = 12 mA

4

25

20

300 K 15

3

10

2 300 K

Associated gain (dB)

5

5

1 85 K 0 5

10 15 20 Frequency (GHz)

0 25

FIGURE 4.9.8 Minimum noise figure and associated gain as a function of frequency at 300 and 85 K for a third-generation SiGe HBT. (From B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. With permission.)

Figure 4.9.8 shows the measured minimum noise figure (NFmin) and associated gain (Gassoc) as a function of frequency at IC ¼ 12 mA (i.e., at peak fT), for a 0.12  10.0 mm2 SiGe HBT, at both 300 and 85 K. At 85 K, this device achieves a minimum NFmin of about 0.3 dB (with Gassoc ¼ 18 dB) at 14 GHz, and a minimum NFmin of about 0.75 dB (Gassoc ¼ 15 dB) at 20 GHz, record numbers for SiGe HBTs operating at cryogenic temperatures.

© 2006 by Taylor & Francis Group, LLC

4.9-506

The Silicon Heterostructure Handbook

4.9.6 Helium Temperature Operation Long-wavelength infrared focal-plane-arrays (FPA) and certain ultra-low-noise instrumentation amplifiers require transistors that operate down to liquid helium temperature (LHeT ¼ 4.3 K). In addition to evaluating SiGe HBT performance at these potential application temperatures, the below 77-K regime is ideally suited for investigating new device physics phenomena, as well as for testing the validity of conventional theoretical formulations of device operation (e.g., drift-diffusion). This is particularly true for a SiGe HBT, since many of the transistor parameters are thermally activated functions of the Geinduced band offsets, and are expected to change dramatically between 77 and 4 K. For instance, a simple calculation of the intrinsic carrier density, to which the terminal currents are proportional, shows that a nio changes by a factor of e3056 between 77 and 4 K. Initial results on (unoptimized) Si BJTs to 10 K [20] showed transistor functionality but poor performance in the LHeT regime (<10 to 15 K). More recent work [21] on SiGe HBTs optimized for 77-K operation shows more impressive performance results as well as reveals interesting new device physics effects. The emitter-cap SiGe HBT optimized explicitly for 77 K achieved a b of 500, fT of 61 GHz, fmax of 50 GHz, and a minimum ECL gate delay of 21.9 psec at 84 K. In cooling this transistor from 77 K to LHeT, the current gain increases monotonically from 110 at 300 K to 1045 at 5.84 K, although parasitic base current leakage limits the useful operating current to above about 1.0 mA at 5.84 K. Figure 4.9.3 shows the Gummel characteristics of a 1.4  4.4 mm2 emitter-cap SiGe HBT down to 5.84 K, and Figure 4.9.4 shows the current gain as a function of bias current down to 5.84 K. The severity of the base current leakage at low injection, and the Ge-ramp effect at medium injection, limits the current range where one obtains the peak current gain. The aggressive base profile design in
close to 8  1018 cm
3) leads to an Rbi of <18 kV/sq. at the emitter-cap SiGe HBT design (peak Nab 5.84 K, much lower than a more conventional SiGe HBT design. Base freeze-out below 77 K depends very strongly on peak base doping, and must be carefully optimized for LHeT applications. At temperatures as low as 5.84 K, this transistor has a maximum current drive in excess of 1.5 mA/mm2 (limited by quasi-saturation and heterojunction barrier effects), with a peak transconductance of 190 mS. Theoretical calculations based on measured SIMS data were compared to the experimentally observed variation of peak current gain with temperature. Above 77 K, the temperature variation of peak current gain for the SiGe HBT is close to that theoretically expected, while at temperatures below 77 K, the exponential increase in current gain is primarily limited by parasitic base leakage due to fieldenhanced tunneling. In contrast to this strong enhancement of current gain with cooling for the SiGe HBT, the current gain in a Si BJT fabricated with a comparable doping profile is significantly degraded at low temperatures, due to the strong bandgap narrowing in the emitter. A comprehensive discussion of other unique cryogenic phenomena in SiGe HBTs operating in the LHeT environment is presented in Ref. [1].

4.9.7 High-Temperature Operation While it has been demonstrated that SiGe HBTs operate well down to deep cryogenic temperatures, there was historically early concern about their suitability for operation at elevated temperatures. Given that all electronic systems must successfully operate at temperatures considerably above 300 K (e.g., 1258C to satisfy military specifications and 858C for many commercial applications), this is a potentially important issue. Given the narrow bandgap base region of the SiGe HBT compared to a Si BJT, and hence the expected negative temperature coefficient of the current gain (i.e., b decreases as temperature increases), it was often asked whether practical SiGe HBTs would have acceptable values of b at required high-end operational temperatures (e.g., 1258C). That this issue is not a valid concern for circuit designers is clearly demonstrated in Figure 4.9.9, which compares the percent change in peak current gain between 25 and 1258C for a Si BJT and a number or commercially relevant SiGe profiles. There are several important points to glean from these data:

© 2006 by Taylor & Francis Group, LLC

4.9-507

Temperature Effects

+25

Change in b from 25 to 125⬚C (%)

+20

VCB = 1.0 V

+15 +10 +5 0 −5 −10 −15 −20 −25 Si BJT

15%Ge Triangle

8%Ge 10%Ge 14%Ge Trapezoid Trapezoid Low-Noise

Ge profile shape

FIGURE 4.9.9 Percent change in peak current gain between 25 and 1258C for various Ge profiles. (From JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. With permission.)

.

.

.

.

The current gain in SiGe HBTs does indeed have an opposite temperature dependence from that of a Si BJT, as expected from simple theory. These changes in b between 25 and 1258C, however, are modest at best (<25%), and clearly not cause for alarm for any realistic circuit. The negative temperature coefficient of b in SiGe HBTs is tunable, meaning that its temperature behavior between, say, 25 and 1258C can be trivially adjusted to its desired value by changing the Ge profile shape near the EB junction. In the case of the 15% Ge triangle profile, with 0% Ge at the EB junction, b is in fact temperature independent from 25 to 1258C. This points to a major advantage of bandgap engineering. Finally, it is well known that thermal-runaway in high-power Si BJTs is the result of the positive temperature coefficient of b (i.e., as the device heats up due to power dissipation, one gets more bias current since the b increases with temperature, leading to a positive feedback process, and hence thermal collapse). The fact that SiGe HBTs naturally have a negative temperature coefficient for b suggests that this might present interesting opportunities for power amplifiers, since emitter ballasting resistors (which degrade RF gain) could in principle be eliminated.

There is also an emerging interest in the operation of electronic devices above 1258C, for planetary space missions (e.g., Venus), or for on-engine electronics for both the automotive and aerospace sectors to support the ‘‘more-electric-vehicle’’ thrust of the military. In these cases, allowing the requisite electronic components to operate at relatively high temperatures (say 200 to 2508C) presents compelling cost-saving advantages, since the cooling system constraints can be dramatically relaxed. Conventional wisdom dictates that Si-based devices not be considered for these types of high-temperature applications, since Si is a fairly low-bandgap material, and thermal leakage (i.e., Ion/Ioff ratios) depends exponentially on Eg. The fact that SiGe HBTs are capable of operation in such high-temperature environments can be easily demonstrated experimentally (as shown in Figure 4.9.10 and Figure 4.9.11). While performance degradation generally results at high temperatures, in these second-generation SiGe HBTs the peak

© 2006 by Taylor & Francis Group, LLC

4.9-508

The Silicon Heterostructure Handbook

current gain remains above 125 at 3008C and the peak fT/fmax above 90 GHz at 2008C [22]. No serious reliability degradation mechanisms were identified at elevated temperatures. Thus, there is no fundamental reason why SiGe HBTs cannot satisfy this important emerging niche application of hightemperature electronics. 500 High-breakdown High-performance AE = 0.28⫻4.6 µm2 VCB = 0 V

400

Current gain

25⬚C

300 150⬚C 200 300⬚C 100

0 10−12

10−10

10−8 10−6 Collector current (A)

10−4

10−2

FIGURE 4.9.10 Current gain as a function of collector current at various temperatures for both high-performance (low-breakdown) and high-breakdown second-generation SiGe HBTs. (From T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004. With permission.) 150 fT 25⬚C fmax 25⬚C fT 100⬚C fmax 100⬚C fT 200⬚C fmax 200⬚C

fT/ fmax (GHz)

100

High-performance AE = 0.28⫻4.6 µm2 VCB = 1 V

50

0

10−4

10−3 10−2 Collector current (A)

10−1

FIGURE 4.9.11 Cutoff frequency as a function of collector current at various temperatures for a second-generation SiGe HBT. (From T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

Temperature Effects

4.9-509

4.9.8 Summary Bandgap engineering has a positive influence on the low-temperature characteristics of bipolar transistors, enabling conventionally designed SiGe HBTs to operate very well in the cryogenic environment. We have addressed the effects of temperature on SiGe HBT device and circuit operation, by showing how temperature couples to SiGe HBT dc and ac performance, addressing how one optimizes SiGe HBTs specifically for cryogenic operation, and finally by considering the operation of SiGe HBTs at high temperatures. We conclude that the operation of SiGe HBTs at extreme temperatures (both low and high) is a viable path for commercial SiGe technology, and of potential importance for a growing number of niche applications.

Acknowledgments I am grateful to A. Joseph, T. Chen, R. Krithivasan, Y. Lu, D. Richey, B. Banerjee, S. Nuttinck, G. Niu, D. Harame, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by Hypres, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. WL Kauffman and AA Bergh. The temperature dependence of ideal gain in double diffused silicon transistors. IEEE Trans. Electron Dev. 15:732–735, 1968. 3. ES Schlig. Low-temperature operation of Ge picosecond logic circuits. IEEE J. Solid-State Circuits 3:271–276, 1968. 4. D Buhanan. Investigation of current-gain temperature dependence in silicon transistors. IEEE Trans. Electron Dev. 16:117–124, 1969. 5. WP Dumke. Effect of minority carrier trapping on the low-temperature characteristics of Si transistors. IEEE Trans. Electron Dev. 17:388–389, 1970. 6. WP Dumke. The effect of base doping on the performance of Si bipolar transistors at low temperatures. IEEE Trans. Electron Dev. 28:494–500, 1981. 7. JD Cressler, DD Tang, KA Jenkins, GP Li, and ES Yang. On the low-temperature static and dynamic properties of high-performance silicon bipolar transistors. IEEE Trans. Electron Dev. 36:1489–1502, 1989. 8. JD Cressler, DD Tang, KA Jenkins, and GP Li. Low temperature operation of silicon bipolar ECL circuits. Technical Digest of the IEEE International Solid-State Circuits Conference, New York, 1989, pp. 228–229. 9. JMC Stork, DL Harame, BS Meyerson, and TN Nguyen. High performance operation of silicon bipolar transistors at liquid nitrogen temperature. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 405–408. 10. JCS Woo and JD Plummer. Optimization of bipolar transistors for low temperature operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 401–404. 11. K Yano, K Nakazato, M Miyamoto, M Aoki, and K Shimohigashi. A high-current-gain lowtemperature pseudo-HBT utilizing a sidewall base-contact structure (SICOS). IEEE Electron Dev. Lett. 10:452–454, 1989. 12. JD Cressler, TC Chen, JD Warnock, DD Tang, and ES Yang. Scaling the silicon bipolar transistor for sub-100-ps ECL circuit operation at liquid nitrogen temperature. IEEE Trans. Electron Dev. 37:680– 691, 1990. 13. EF Crabbe´, GL Patton, JMC Stork, JH Comfort, and BS Meyerson. The low-temperature operation of Si and SiGe bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20.

© 2006 by Taylor & Francis Group, LLC

4.9-510

The Silicon Heterostructure Handbook

14. JD Cressler, JH Comfort, EF Crabbe´, GL Patton, W Lee, JY-C Sun, JMC Stork, and BS Meyerson. Sub-30-ps ECL circuit operation at liquid-nitrogen temperature using self-aligned epitaxial SiGebase bipolar transistors. IEEE Electron Dev. Lett. 12:166–168, 1991. 15. JD Cressler, JH Comfort, EF Crabbe´, JMC Stork, and JY-C Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part I. Transistor dc design considerations. IEEE Trans. Electron Dev. 40:525–541, 1993. 16. JD Cressler, EF Crabbe´, JH Comfort, JMC Stork, and JY-C Sun. On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications — Part II. Circuit performance issues. IEEE Trans. Electron Dev. 40:542–556, 1993. 17. JH Comfort, EF Crabbe´, JD Cressler, W Lee, JY-C Sun, J Malinowski, M D’Agostino, JN Burghartz, JMC Stork, and BS Meyerson. Single crystal emitter cap for epitaxial Si- and SiGe-base transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 857–860. 18. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter-cap SiGe-base bipolar technology optimized for liquid-nitrogen temperature operation. IEEE Electron Dev. Lett. 15:472–474, 1994. 19. B Banerjee, S Venkataraman, Y Lu, S Nuttinck, D Heo, E Chen, JD Cressler, J Laskar, G Freeman, and D Ahlgren. Cryogenic Performance of a 200 GHz SiGe HBT Technology. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 171–174. 20. AK Kapoor, HK Hingarh, and TS Jayadev. Operation of poly emitter bipolar npn and p-channel JFETs near liquid-helium (10 K) temperature. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1988, pp. 210–214. 21. AJ Joseph, JD Cressler, and DM Richey. Operation of SiGe heterojunction bipolar transistors in the liquid-helium temperature regime. IEEE Electron Dev. Lett. 16:268–270, 1995. 22. T Chen, W-ML Kuo, E Zhao, Q Liang, Z Jin, JD Cressler, and AJ Joseph. On the high-temperature (to 3008C) characteristics of SiGe HBTs. IEEE Trans. Electron Dev. 51:1825–1832, 2004.

© 2006 by Taylor & Francis Group, LLC

4.10 Radiation Effects

John D. Cressler Georgia Institute of Technology

4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 4.10.6 4.10.7 4.10.8

Introduction........................................................... 4.10-511 DC Effects .............................................................. 4.10-511 AC Small-Signal and Noise Effects ...................... 4.10-514 Origin of Radiation Hardness .............................. 4.10-515 Low-Dose-Rate Effects .......................................... 4.10-516 SiGe HBT Circuit Tolerance................................. 4.10-516 Single-Event Upset ................................................ 4.10-517 Summary ................................................................ 4.10-521

4.10.1 Introduction There are currently two recent but rapidly growing thrusts within the space electronics community: (1) the use of commercial-off-the-shelf (COTS) parts whenever possible for space-borne systems as a cost-saving measure; and (2) the use of system-on-a-chip integration to lower chip counts and system costs, as well as simplify packaging and lower total system launch weight. The ‘‘holy-grail’’ in the realm of space electronics can thus be viewed as a conventional terrestrial IC technology with a system-on-achip capability, which is also radiation-hard as fabricated, without requiring any additional process modifications or layout changes. It is within this context that we discuss SiGe HBT BiCMOS technology as potentially such a ‘‘radiation-hard-as-fabricated’’ IC technology with possibly far-ranging implications for the space community. Within the context of existing data for radiation exposure of SiGe HBTs, it is meaningful to distinguish between different SiGe HBT technology nodes, and is loosely defined by the ac performance of the SiGe HBT (e.g., peak fT, which is a very strong function of the vertical profile and hence nicely reflects the degree of sophistication in structural design, lateral dimensional scaling, profile scaling, and net thermal cycle). We thus label a SiGe HBT technology node having a SiGe HBT with a peak fT of roughly 50 GHz as ‘‘first-generation’’ (e.g., SiGe 5HP from IBM [1]), that with a peak fT of roughly 100 GHz as ‘‘secondgeneration’’ (e.g., SiGe 7HP from IBM [2]), that with a peak fT of roughly 200 GHz as ‘‘third-generation’’ (e.g., SiGe 8HP from IBM [3]), and that with a peak fT of roughly 300 GHz as ‘‘fourth-generation’’ (e.g., SiGe 9T from IBM [4]). For brevity, here we only discuss radiation effects in SiGe HBT. For discussion on the impact of radiation on the Si CMOS devices found the SiGe HBT CMOS, the reader is referred to Ref. [5]. More recent results on other commercial SiGe HBT technology platforms (than the IBM results presented here) can be found in Refs. [6, 7].

4.10.2 DC Effects The response of SiGe HBTs to a variety of radiation types has been reported, including gamma rays, neutrons, and protons [8–14]. Since protons induce both ionization and displacement damage, they can be considered the worst case for radiation tolerance. For the following results, relevant proton energy of 63 MeV was used. At proton fluences of 1
1012 p/cm2 and 5
1013 p/cm2, the measured equivalent 4.10-511 © 2006 by Taylor & Francis Group, LLC

4.10-512

The Silicon Heterostructure Handbook

total ionizing dose (TID) was approximately 135 and 6759 krad(Si), respectively, the latter being far larger than most orbital missions require. The typical response of a SiGe HBT to irradiation can be seen in Figure 4.10.1, which shows typical measured Gummel characteristics of a fourth-generation SiGe HBT, both before and after exposure to protons [8–14]. As expected, the base current increases after sufficiently high proton fluence due to the production of generation/recombination (G/R) trapping centers, and hence the current gain of the device degrades. There are two main physical origins of this degradation. The base current density is inversely proportional to the minority carrier lifetime in the emitter, so that a degradation of the hole lifetime will induce an increase in the base current. In addition, ionization damage due to the charged nature of the proton fluence produces interface states and oxide-trapped charges in the spacer layer at the emitter–base junction. These G/R centers also degrade IB, particularly if they are placed inside the EB space–charge region, where they will yield an additional non-ideal base current component (non-kT/q exponential voltage dependence). By analyzing a variety of device geometries, it can be shown that the radiation-induced excess base current is primarily associated with the EB spacer oxide at the periphery of the transistor, as naively expected, and is hence the radiation response is dominated by ionization damage rather than displacement damage. The radiation-induced degradation of the base current and current gain for four generations of SiGe technology are shown in Figure 4.10.2 and Figure 4.10.3. Less than 30% degradation in peak current gain is observed across all four technology nodes, to 1.0 Mrad(Si) equivalent radiation levels, suggesting that SiGe HBTs are robust to TID for typical orbital proton fluences for realistic circuit operating currents above roughly 100 mA without any additional radiation hardening. These results are significantly better than for conventional diffused or even ion-implanted Si BJT technologies (even radiation-hardened ones). Of particular interest is the inference of the spatial location of the proton-induced traps in these devices [10]. The existence of proton-induced traps in the EB space–charge region is clearly demonstrated by the G/R-induced increase in the non-ideal base current component shown in the Gummel

Collector and base current density (A/µm2)

10–1

Forward mode A E = 0.12⫻2.5 µm2 Low breakdown

10–3

VCB = 0 V 300 K

10–5

Pre-radiation 1⫻1012p/cm2 7⫻1012p/cm2 2⫻1013p/cm2 5⫻1013p/cm2 Self-anneal of post 5⫻1013p/cm2

10–7

10–9

10–11 0.4

0.5

0.6

0.7

0.8

0.9

1.0

Base−emitter voltage (V)

FIGURE 4.10.1 Forward-mode Gummel characteristics of a fourth-generation, 350 GHz SiGe HBT, during radiation exposure. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-513

Radiation Effects

I B(post)/I B(pre)

70 60

Forward mode

50

AE = 0.12⫻2.5 µm2(9T)

40

VBE = 0.6 V VCB = 0 V 300 K

30 20 10 0 1⫻1012

5HP (AE = 0.5⫻2.5 µm2) 7HP (AE = 0.16⫻1.6 µm2) 8HP (AE = 0.12⫻10 µm2) 9T Low BVCEO 9T High BVCEO

1⫻1013 Proton fluence

1⫻1014 (p/cm2)

FIGURE 4.10.2 Normalized base current degradation for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

1.1 AE = 0.12⫻2.5 µm2(9T)

1.0

VCB = 0 V 300 K

Peak bpost / bpre

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1⫻1012

5HP (AE = 0.5⫻2.5 µm2) 7HP (AE = 0.16⫻1.6 µm2) 9T Low BVCEO 9T High BVCEO 1⫻1013

1⫻1014

Proton fluence (p/cm2)

FIGURE 4.10.3 Current gain degradation for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-514

The Silicon Heterostructure Handbook

characteristics. The existence of radiation-induced traps in the collector–base space–charge region was verified by measuring the inverse mode Gummel characteristics of the device (emitter and collector leads swapped). In this case the radiation-induced traps in the CB junction now act as G/R centers in the inverse EB junction, with a signature non-kT/q exponential slope. Two-dimensional simulations were calibrated to both measured data for the pre- and post-irradiated devices at a collector–base voltage of 0.0 V. In order to obtain quantitative agreement between the simulated and measured irradiated results, traps must be located uniformly throughout the device, and additional interface traps must be located around the emitter–base spacer oxide edge. Most of the radiationinduced recombination occurs inside the EB space–charge region, leading to a non-ideal base current, as expected.

4.10.3

AC Small-Signal and Noise Effects

To assess the impact of radiation on the ac performance of the transistors, the S-parameters were measured to 40 GHz both before and after proton exposure [15]. From the measured S-parameters, the transistor cutoff frequency as a function of bias current density can be extracted, and is shown for four technology generations in Figure 4.10.4. Only a slight degradation in fT (and fmax) is observed, the latter expected from the minor increase of the base resistance with irradiation, due to either carrier removal, mobility and lifetime changes, or both. The broadband noise performance of SiGe HBTs is critical for space-borne transceivers and communications platforms. As shown in Figure 4.10.5, the minimum noise figure (NFmin) degrades only slightly at 2.0 GHz in a first-generation SiGe HBT after an extreme proton fluence of 5
1013 p/cm2 (from 0.95 dB to a still-excellent value of 1.07 dB, a 12.6% degradation). SiGe HBTs have the desirable feature of low 1/f noise commonly associated with Si bipolar transistors, which is of great importance because upconverted low-frequency noise (phase noise) typically limits the spectral purity of communication systems. Understanding the effects of radiation on 1/f noise in SiGe HBTs thus becomes a crucial issue for space-borne communications electronics. Physically, 1/f noise results from the presence of G/R center traps in the transistors, from which trapping–detrapping

400

Cutoff frequency (GHz)

350 300

VCB = 1.0 (5HP,7HP,8HP) VCB = 0.5 V (9T) 300 K

9T

250 8HP

200 150 100 50 0 0.1

Pre-radiation 7⫻1012p/cm2 5⫻1013p/cm2

7HP 5HP

1.0 10 Collector current density (mA/µm2)

100

FIGURE 4.10.4 Pre- and post-radiation cutoff frequency versus bias current density for first-, second-, third-, and fourth-generation SiGe technology nodes. (From A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.10-515

Radiation Effects

3.5

NFmin (dB)

3.0

f = 10 GHz

2.5

AE = 0.5⫻20⫻2 µm2 VCB = 1 V IC = 2.6 mA

2.0 f = 4 GHz

1.5 1.0

f = 2 GHz 0.5 1012

Pre

1013

1014

Proton radiation fluence (p/cm2)

FIGURE 4.10.5 Extracted minimum noise figure as a function of proton fluence for multiple frequencies for firstgeneration SiGe HBTs. (From S Zhang, G Niu, SD Clark, JD Cressler, and M Palmer. IEEE Trans. Nuclear Sci. 46:1716–1721, 1999. With permission.) 10–19 SiGe HBT Ae = 0.5⫻1 µm2 I B = 4 µA Pre-irradiation 2⫻1013 p/cm2

S IB (A2/Hz)

10–20 10–21 10–22 10–23

∝1/f

10–24

2qIB

10–25 100

101

102

103

104

105

Frequency (Hz)

FIGURE 4.10.6 Input-referred base current low-frequency noise for a first-generation SiGe HBT, before and after irradiation. (From Z Jin, G Niu, JD Cressler, C Marshall, P Marshall, H Kim, R Reed, and D Harame. IEEE Trans. Nuclear Sci. 48:2244–2249, 2001. With permission.)

processes occur while carriers flow inside the device, thus modulating the number of carriers (and hence currents) to produce 1/f noise. The pre-irradiation low-frequency noise spectrum in these SiGe HBTs is typically 1/f, with an IB2 dependence, while SIB
AE is almost independent of AE. The IB2 and 1/AE dependencies of SIB are strong indicators of uniformly distributed noise sources over the entire emitter area. After 2
1013 p/cm2 proton irradiation, the low-frequency noise spectrum in first-generation SiGe HBTs remains 1/f in frequency dependence, and free of G/R (burst) noise, and at roughly the same noise magnitude (i.e., no radiation-induced degradation) (as can be seen in Figure 4.10.6) [16].

4.10.4 Origin of Radiation Hardness We note that careful comparisons between identically fabricated SiGe HBTs and Si BJTs (same device geometry and wafer lot, but without Ge in the base for the epitaxial-base Si BJT) show that the extreme level of total dose tolerance of SiGe HBTs is not per se due to the presence of Ge [10]. That is, the proton response of both the epitaxial base SiGe HBT and Si BJT is nearly identical. We thus attribute the

© 2006 by Taylor & Francis Group, LLC

4.10-516

The Silicon Heterostructure Handbook

observed radiation hardness to the unique and inherent structural features of the device itself, which from a radiation standpoint can be divided into three major aspects: (1) in these epitaxial base structures, the extrinsic base region is very heavily doped (>5
1019 cm3) and located immediately below the emitter–base (EB) spacer oxide region, effectively confining any radiation-induced damage, and its effects on the EB junction; (2) the EB spacer, known to be the most vulnerable damage point in conventional BJT technologies, is thin (<0.20 mm wide) and composed of an oxide–nitride composite, the latter of which is known to produce an increased level of radiation immunity; (3) the active volume of these transistors is very small (emitter stripe width WE ¼ 0.5 mm, and base width Wb < 150 nm), and the emitter, base, and collector doping profiles are quite heavily doped, effectively lessening the impact of displacement damage. We also note that these SiGe HBTs compare very favorably in both performance and radiation hardness with (more expensive) GaAs HBT technologies that are often employed in space applications requiring both very high speed and an extreme level of radiation immunity [17].

4.10.5

Low-Dose-Rate Effects

Within the past few years, a pronounced low-dose-rate sensitivity to gamma irradiation that is not screened by the current test methods for ionizing radiation has been observed in Si bipolar technologies. The enhancement in device and circuit degradation at low gamma dose rates has come to be known as ‘‘enhanced low-dose-rate sensitivity’’ (ELDRS) [18–20]. The ELDRS effect was first reported in 1991, which demonstrated that existing radiation hardness test assurance methodologies were not appropriately considering worst-case conditions. The physical origins underlying ELDRS have been hotly debated for years, and numerous mechanisms proposed. Recent attempts to understand ELDRS include a model suggesting that the lower net radiation-induced trapped charge density at high-dose-rates is a result of a space–charge phenomenon, caused by delocalized hole traps that occur in heavily damaged oxides such as bipolar base oxides. These traps can retain holes on a timescale of seconds to minutes, causing a buildup of positive charge in the oxide bulk during high-dose-rate irradiation. This is in contrast to lowdose-rate irradiation, where the irradiation time is much longer, effectively allowing the holes in the trap centers to be detrapped. Thus, in the high-dose-rate case, the larger total trapped hole density forces holes near the interface to be trapped closer to the interface, where they can be compensated by electrons from the silicon. This lowers the resultant net trapped charge density. To assess ELDRS in first-generation SiGe technology, low-dose-rate (0.1 rad(Si)/sec) and high-doserate (300 rad(Si)/sec) experiments were conducted using Cobalt-60 [21]. As can be seen in Figure 4.10.7, low-dose-rate effects in these first-generation SiGe HBTs were found to be nearly non-existent, in striking contrast to reports of strong ELDRS in conventional Si bipolar technologies. We attribute this observed hardness to ELDRS to the same mechanisms responsible for the overall radiation hardness of the technology, and is likely more structural in nature than due to any unique advantage afforded by the SiGe base. Interestingly, an anomalous decrease in base current was also found in these devices at lowdose-rates, suggesting that a new physical phenomenon is present at low-dose-rates in these devices.

4.10.6

SiGe HBT Circuit Tolerance

For the successful deployment of SiGe technology into space-based systems, circuit-level radiation hardness is clearly more important than device-level hardness. As presented above, the TID device degradation is minor in the bias range of interest to most actual circuits (typically IC > 100 mA). In order to assess the impact of radiation exposure on actual SiGe HBT circuits, we have compared two very important, yet very different circuit types, one heavily used in analog ICs (the bandgap reference circuit), and one heavily used in RFICs (the voltage-controlled oscillator) [22, 23]. Each circuit represents a key building block for realistic SiGe ICs that might be flown in space. Each of these SiGe HBT circuits was designed using fully calibrated SPICE models, layed-out, and then fabricated on the same wafer to facilitate unambiguous comparisons. In addition, because any realistic RF IC must also

© 2006 by Taylor & Francis Group, LLC

4.10-517

Radiation Effects

600

X-ray 25⬚C (Nowlin et al.) Cobalt 25⬚C (Nowlin et al.) X-ray 60⬚C (Nowlin et al.) Cobalt 25⬚C (This Work)

500

∆I B/I B (%)

400 300 200

100 krad (SiO2) VBE = 0.6 V This Work − 0.5⫻2.5 µm2 SiGe HBT Nowlin et al. − 1.5⫻1.5 µm2 Si BJT

100 0 −100 0.1

1

10

100

1000

Dose rate [rad(SiO2)/S]

FIGURE 4.10.7 Normalized base current as a function of gamma radiation dose rate, for both Si BJTs and firstgeneration SiGe HBTs. (From G Banerjee, G Niu, JD Cressler, SD Clark, MJ Palmer, and DC Ahlgren. IEEE Trans. Nuclear Sci. 46:1620–1626, 1999. With permission.)

necessarily include passive elements such as monolithic inductors and capacitors, we have also investigated the effects of proton exposure on an RF LC bandpass filter. As can be seen from the data (Figure 4.10.8), the impact of even extreme proton fluences has minimal effect on either the output voltage or temperature sensitivity of BGRs, the phase noise or tuning range of VCOs or passive elements, and is indicative of the overall robustness of this SiGe technology for analog and RF circuit applications.

4.10.7 Single-Event Upset Clearly, a space-qualified IC technology must demonstrate sufficient SEU immunity to support highspeed circuit applications as well as possess TID tolerance. It is well known that even III–V technologies that have significant TID tolerance often suffer from poor SEU immunity, particularly at high data rates. Recently, high-speed SiGe HBT digital logic circuits were found to be vulnerable to SEU at even low linear energy transfer (LET) values [24–26]. In addition, successfully employed III–V HBT circuit-level hardening schemes using the current-sharing hardening (CSH) technique were found to be ineffective for these SiGe HBT logic circuits (Figure 4.10.9). To understand single-event effects in SiGe HBTs, one must use calibrated two-dimensional or three-dimensional device simulation to assess the charge collection characteristics of SiGe HBTs. These device-level simulation results can then be coupled to circuit-level modeling to better understand circuit-level mitigation approaches. From a device perspective, it is important to first assess the transistor charge collection characteristics as a function of terminal bias, load condition, substrate doping, and ion strike depth [27, 28]. Bias and loading conditions were chosen to mimic representative circuit conditions within an actual ECL/CML digital circuit. Figure 4.10.10 shows the charge collected by the collector versus time for different RC loads. The base and emitter terminals were grounded, the substrate bias was 5.2 V, the collector was connected to ground through an RC load, and the substrate doping was 5
1015 cm3. A uniform LET of 0.1 pC/mm (equivalent to 10 MeV cm2/mg) over 10-mm depth was used, which generates a total charge of 1.0 pC. The results clearly show that charge collection is highly dependent on the transistor load condition (i.e., circuit topology). As the load resistance increases, the collector-collected charge decreases. Note, however, that the emitter-collected charge increases correspondingly. The underlying physics is that more electrons exit through the emitter, instead of the collector. A larger load resistance presents a higher impedance to the electrons at the collector, and thus more electrons exit through the emitter.

© 2006 by Taylor & Francis Group, LLC

4.10-518

The Silicon Heterostructure Handbook

Pre-radiation After 5⫻1013 p/cm2 VCC 3.0 3.0 ICC 0.773 0.767 Bandgap 1.37416 reference Vout at 300 K 1.372096 Stability 81.7 81.2 (−55 to 85⬚C) 5.0 5.0 Frequency Vcc 3.3 3.3 Voltage ICC 22.5 22.5 controlled −5.0 −5.5 Outpout power oscillator −112.5 −111.8 Phase noise Tunning range 4,55−5,452 4,623−5,470 1.9 1.9 Frequency Filter Q 7.6 7.6 (at 3 dB BW) 16.8 16.8 LC bandpass Insertion Loss 2.5 2.5 L filter 7.4 7.4 Inductor Q 6.0 6.0 C 58 58 Capacitor Q SiGe HBT Circuit

Parameters

Units V mA V ppm/⬚C GHz V mA dBm dBc/Hz MHz GHz − dB nH − pF −

FIGURE 4.10.8 Summary of the measured radiation tolerance of some important first-generation SiGe HBT circuits and passives. (From JD Cressler, MC Hamilton, R Krithivasan, H Ainspan, R Groves, G Niu, S Zhang, Z Jin, CJ Marshall, PW Marshall, HS Kim, RA Reed, MJ Palmer, AJ Joseph, and DL Harame. IEEE Trans. Nuclear Sci. 48:2238–2243, 2001. With permission.)

Device cross-section (cm2)

1.0⫻10−3 1.0⫻10−4 1.0⫻10−5 C-12 at 1.6 Gbps F-19 at 1.6 Gbps

1.0⫻10−6

Si-28 at 1.6 Gbps CI-35 at 1.6 Gbps

1.0⫻10−7

Ni-58 at 1.6 Gbps Br-79 at 1.6 Gbps

1.0⫻10−8 1.0⫻10−9 0.0

10.0

20.0 30.0 40.0 50.0 LET (MeV ⫻ cm2/mg)

60.0

70.0

80.0

FIGURE 4.10.9 Experimental SEU cross-section test data on first-generation SiGe HBT shift registers. (From P Marshall, MA Carts, A Campbell, D McMorrow, S Buchner, R Stewart, B Randall, B Gilbert, and R Reed. IEEE Trans. Nuclear Sci. 47:2669–2674, 2000. With permission.)

The collector of the adjacent device only collects a negligible amount of charge, despite the transient current spikes of the strike. Nearly all the electrons deposited are collected by the collector and the emitter, although the partition between emitter and collector collection varies with the load condition. The impact on the SiGe base layer on the charge collection properties is a secondary effect. To better understand circuit-level SEU response, we combined these simulated charge–time profiles with circuit-level modeling in three different SiGe circuit architectures [29]. Circuit A is a

© 2006 by Taylor & Francis Group, LLC

4.10-519

Radiation Effects

Collector-collected charge (pC)

1.2 1.0

VB = 0 V, VE = 0 V VSUB = –5.2 V

R = 1.2 kΩ C = 15 fF R = 10 kΩ C = 2 fF R = 100 kΩ C = 2 fF R = 100 kΩ C = 15 fF

0.8 0.6 0.4 0.2 0.0 0

2

4

6

8

10

Time (ns)

FIGURE 4.10.10 Simulated collector-collected charge versus time for different RC loads. (From G Niu, R Krithivasan, JD Cressler, P Marshall, C Marshall, R Reed, and D Harame. IEEE Trans. Nuclear Sci. 48:1849–1854, 2001. With permission.)

straightforward ECL implementation of the standard rising edge-triggered flip-flop logic. Circuit B is the unhardened version of the D flip-flop used in the shift register results shown in Figure 4.10.9. Circuit B uses fewer transistors and thus less power than circuit A, and is also faster than circuit A, allowing operation at higher clock rates. Because of these advantages, circuit B is very popular in highspeed bipolar digital circuit design. The circuit consists of a master stage and a slave stage. The master stage consists of a pass cell, a storage cell, a clocking stage, and a biasing control. The slave stage has a similar circuit configuration. Circuit C is the current-sharing hardened version of circuit B. (Refer to Ref. [5] for circuit-level schematics for A, B, and C.) The circuit was used as a basic building block of the 32-stage shift-register data shown in Figure 4.10.9. In this case, the current source transistor is divided into five paths, and these paths are maintained separately through the clocking stage and through the pass and storage cells. In essence, the input and output nodes of five copies of the switching circuits, including the controlling switch, clock, master, and storage cells, are connected in parallel. The load resistance is shared by all the current paths. The quasi-three-dimensional simulated SEU-induced transient currents were activated on one of the sensitive transistors in the respective circuits. The SEU currents were activated at 5.46 nsec (within the circuit hold time), immediately after the clock goes from low to high, a sensitive time instant for SEU-induced transient currents to produce an upset at the output. The input data are an alternating ‘‘0’’ and ‘‘1’’ series with a data rate of 2 Gbit/sec. Under these conditions, circuit A shows no upset at all, while circuits B and C show five and three continuous bits of data upset, respectively (Figure 4.10.11). These results suggest that circuit A has the best SEU tolerance, while circuit C, the CSH hardened version, has better SEU tolerance than its unhardened companion version, circuit B. Circuit A, which shows no data upset at a switching current of 1.5 mA, does in fact show an upset when the switching current is lowered to 0.6 mA. This is consistent with our earlier observation that increasing switching current is effective in improving SEU performance for circuit C. The fundamental reason for the observed better SEU tolerance of circuit A than for circuits B and C is that only one of the two outputs of the emitter-coupled pair being hit is affected by the ion-strike SEU current transients. As long as the differential output is above the logic-switching threshold, the output remains unaffected, and no upset occurs. The collector voltage of the switching transistor decreases upon ion strike (compared to without SEU), however, and no upset is observed at the output, simply because the differential output remains above or below the relevant-switching threshold (Figure 4.10.12). These results suggest that circuit-level mitigation techniques can be used in SEU

© 2006 by Taylor & Francis Group, LLC

V1, V2 and clock (V)

4.10-520

The Silicon Heterostructure Handbook

0.2

V1

−0.2 −0.4 3

Data, Q, and clock (V) (V1−V2) and clock (V)

V2

0

4

5

6

7

8

9

10

7

8

9

10

Time (ns) 0.4 0.2 0 −0.2 −0.4 −0.6 3

138 mV

−113 mV 4

5

6 Time (ns)

0.5

No upset

Q

0 −0.5

Data

−1.5

3

Clock

Ion strike at 5.46 ns

−1 4

5

6

7

8

9

10

Time (ns)

V1, V2 and clock (V)

FIGURE 4.10.11 Simulated circuit A output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA. (From G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. With permission.)

V1

0 −0.2 −0.4 3

Data, Q, and clock (V) (V2−V1) and clock (V)

V2

0.2

4

5

6

7

8

9

10

7 Time (ns) Upsets

8

9

10

9

10

Time (ns) 0.4 0.2 0 −0.2 −0.4 −0.6

143 mV

113 mV 3

4

5

6

0.5 Q 0 −0.5

Clock

Ion strike at 5.46 ns

Data

−1 3

4

5

6

7

8

Time (ns)

FIGURE 4.10.12 Simulated circuit B output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA. (From G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. With permission.)

© 2006 by Taylor & Francis Group, LLC

Radiation Effects

4.10-521

hardening of SiGe HBT logic, albeit at some level of additional power dissipation and circuit complexity. A potential SEU-hardening approach has been recently discussed in Ref. [30], but clearly more research is needed in the area of SEU mitigation before widespread deployment of SiGe circuitry in space is attempted.

4.10.8 Summary While ionizing radiation degrades both the dc and ac performance of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. While technology scaling can negatively impact the TID response of the SiGe HBT, it naturally improves the hardness of the CMOS devices, and thus 200 to 300 krad tolerance of the full BiCMOS technology can be achieved without radiation-hardening in second-generation SiGe HBT BiCMOS technology. Taken together, SiGe HBT BiCMOS technology offers many interesting possibilities for SoC applications of space-borne electronic systems.

Acknowledgments I am grateful to A. Sutton, B. Haugerud, Y. Lu, W.-M. Kuo, G. Niu, P. Marshall, R. Reed, C. Marshall, J.-S. Rieh, G. Freeman, D. Ahlgren, L. Cohn, K. LaBel, H. Brandhorst, H. Ainspan, J. Lee, S. Nuttnick, H. Kim, C. Palor, S. Clark, D. Emily, B. Randall, K. Jobe, M. Palmer, A. Joseph, D. Harame, D. Herman, B. Meyerson, and the IBM SiGe team for their contributions. This work was supported by DTRA under the Radiation Hardened Microelectronics Program, NASA-GSFC under the Electronics Radiation Characterization Program, IBM, and the Georgia Electronic Design Center at Georgia Tech.

References 1. DC Ahlgren, G Freeman, S Subbanna, R Groves, D Greenberg, J Malinowski, D Nguyen-Ngoc, SJ Jeng, K Stein, K Schonenberg, D Kiesling, B Martin, S Wu, DL Harame, and BS Meyerson. A SiGe HBT BiCMOS technology for mixed-signal RF applications. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1997, pp. 195–198. 2. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, M Gordon, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC compatible CMOS using copper interconnect. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 3. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 4. J-S Rieh, B Jagannathan, H Chen, K Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency near 300 GHz. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 2002, pp. 771–774. 5. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

© 2006 by Taylor & Francis Group, LLC

4.10-522

The Silicon Heterostructure Handbook

6. J Comeau, A Sutton, B Haugerud, JD Cressler, W-ML Kuo, P Marshall, R Reed, A Karroy, and R Van Art. Proton tolerance of advanced SiGe HBTs fabricated on different substrate materials. 2004 IEEE Nuclear and Space Radiation Effects Conference, Atlanta, to be presented July 2004. 7. E Zhao, A Sutton, B Haugerud, JD Cressler, P Marshall, R Reed, B El-Kareh, and S Balster. The effects of radiation on 1/f noise in complementary (npn þ pnp) SiGe HBTs. 2004 IEEE Nuclear and Space Radiation Effects Conference, Atlanta, to be presented July 2004. 8. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Trans. Nuclear Sci. 42:1558– 1566, 1995. 9. J Roldan, WE Ansley, JD Cressler, SD Clark, and D Nguyen-Ngoc. Neutron radiation tolerance of advanced UHV/CVD SiGe HBTs. IEEE Trans. Nuclear Sci. 44:1965–1973, 1997. 10. J Roldan, G Niu, WE Ansley, JD Cressler, and SD Clark. An investigation of the spatial location of proton-induced traps in SiGe HBTs. IEEE Trans. Nuclear Sci. 45:2424–2430, 1998. 11. JD Cressler, M Hamilton, G Mullinax, Y Li, G Niu, C Marshall, P Marshall, H Kim, M Palmer, A Joseph, and G Freeman. The effects of proton irradiation on the lateral and vertical scaling of UHV/CVD SiGe HBT BiCMOS technology. IEEE Trans. Nuclear Sci. 47:2515–2520, 2000. 12. JD Cressler, R Krithivasan, G Zhang, G Niu, P Marshall, H Kim, R Reed, M Palmer, and A Joseph. An investigation of the origins of the variable proton tolerance in multiple SiGe HBT BiCMOS technology generations. IEEE Trans. Nuclear Sci. 49:3203–3207, 2002. 13. Y Lu, JD Cressler, R Krithivasan, Y Li, RA Reed, PW Marshall, C Polar, G Freeman, and D Ahlgren. Proton tolerance of third-generation, 0.12 mm 185 GHz SiGe HBTs. IEEE Trans. Nuclear Sci. 50:1811–1815, 2003. 14. A Sutton, B Haugerud, Y Lu, W-ML Kuo, JD Cressler, P Marshall, R Reed, J-S Rieh, G Freeman, and D Ahlgren. Proton response of 4th-generation 350 GHz UHV/CVD SiGe HBTs. 2004. IEEE Trans. Nuclear Sci. 51:3736–3742, 2004. 15. S Zhang, G Niu, SD Clark, JD Cressler, and M Palmer. The effects of proton irradiation on the RF performance of SiGe HBTs. IEEE Trans. Nuclear Sci. 46:1716–1721, 1999. 16. Z Jin, G Niu, JD Cressler, C Marshall, P Marshall, H Kim, R Reed, and D Harame. 1/f noise in proton-irradiated SiGe HBTs. IEEE Trans. Nuclear Sci. 48:2244–2249, 2001. 17. S Zhang, G Niu, JD Cressler, SJ Mathew, SD Clark, P Zampardi, and RL Pierson. A comparison of the effects of gamma irradiation on SiGe HBT and GaAs HBT technologies. IEEE Trans. Nuclear Sci. 47:2521–2527, 2000. 18. RL Pease. Total-dose issues for microelectronics in space systems. IEEE Trans. Nuclear Sci. 43:442–452, 1996. 19. EW Enlow, RL Pease, W Combs, RD Schrimpf, and RN Nowlin. Response of advanced bipolar processes to ionizing radiation. IEEE Trans. Nuclear Sci. 38:1342–1351, 1991. 20. DM Fleetwood, SL Kosier, RN Nowlin, RD Schrimpf, RA Reber Jr, M Delaus, PS Winokur, A Wei, WE Combs, and RL Pease. Physical mechanisms contributing to enhanced bipolar gain degradation at low dose rates. IEEE Trans. Nuclear Sci. 41:1871–1883, 1994. 21. G Banerjee, G Niu, JD Cressler, SD Clark, MJ Palmer, and DC Ahlgren. Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors. IEEE Trans. Nuclear Sci. 46:1620–1626, 1999. 22. JD Cressler, MC Hamilton, R Krithivasan, H Ainspan, R Groves, G Niu, S Zhang, Z Jin, CJ Marshall, PW Marshall, HS Kim, RA Reed, MJ Palmer, AJ Joseph, and DL Harame. Proton radiation response of SiGe HBT analog and RF circuits and passives. IEEE Trans. Nuclear Sci. 48:2238–2243, 2001. 23. S Zhang, JD Cressler, G Niu, C Marshall, P Marshall, H Kim, R Reed, M Palmer, A Joseph, and D Harame. The effects of operating bias conditions on the proton tolerance of SiGe HBTs. SolidState Electron. 47:1729–1734, 2003. 24. P Marshall, MA Carts, A Campbell, D McMorrow, S Buchner, R Stewart, B Randall, B Gilbert, and R Reed. Single event effects in circuit hardened SiGe HBT logic at gigabit per second data rates. IEEE Trans. Nuclear Sci. 47:2669–2674, 2000.

© 2006 by Taylor & Francis Group, LLC

Radiation Effects

4.10-523

25. R Reed, P Marshall, H Ainspan, C Marshall, H Kim, JD Cressler, and G Niu. Single event upset test results on an IBM prescalar fabricated in IBM’s 5HP germanium doped silicon process. Proceedings of the IEEE Nuclear and Space Radiation Effects Conference Data Workshop, Vancouver, 2001, pp. 172–176. 26. RA Reed, PW Marshall, J Pickel, MA Carts, T Irwin, G Niu, JD Cressler, R Krithivasan, K Fritz, P Riggs, J Prairie, B Randall, B Gilbert, G Vizkelethy, P Dodd, and K LaBel. Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20 mm silicon germanium heterojunction bipolar transistors and circuits. IEEE Trans. Nuclear Sci. 50:2184–2190, 2003. 27. G Niu, JD Cressler, M Shoga, K Jobe, P Chu, and DL Harame. Simulation of SEE-induced charge collection in UHV/CVD SiGe HBTs. IEEE Trans. Nuclear Sci. 47:2682–2689, 2000. 28. G Niu, R Krithivasan, JD Cressler, P Marshall, C Marshall, R Reed, and D Harame. Modeling of single event effects in circuit-hardened high-speed SiGe HBT logic. IEEE Trans. Nuclear Sci. 48:1849–1854, 2001. 29. G Niu, R Krithivasan, JD Cressler, PA Riggs, BA Randall, P Marshall, and R Reed. A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures. IEEE Trans. Nuclear Sci. 49:3107–3114, 2002. 30. R Krithivasan, G Niu, JD Cressler, SM Currie, KE Fritz, RA Reed, PW Marshall, PA Riggs, BA Randall, and B Gilbert. An SEU hardening approach for high-speed SiGe HBT digital logic. IEEE Trans. Nuclear Sci. 50:2126–2134, 2003.

© 2006 by Taylor & Francis Group, LLC

4.11 Reliability Issues 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5

John D. Cressler Georgia Institute of Technology

4.11.6 4.11.7

Introduction........................................................... 4.11-525 Technology-Driven Reliability and Yield Issues............................................................. 4.11-526 Conventional Device Degradation Mechanisms ........................................................... 4.11-527 ‘‘Mixed-Mode’’ Stress Effects................................ 4.11-528 Breakdown Voltage Constraints and Operating Point Instabilities ................................ 4.11-532 Low-Frequency Noise Variations ......................... 4.11-534 Summary ................................................................ 4.11-536

4.11.1 Introduction Clearly, any new integrated circuit technology (SiGe or otherwise) must be proven to be ‘‘reliable.’’ That is, under typical circuit-operating conditions, the circuits, and importantly, the systems constructed from those circuits, must not wear-out or degrade to a level at which they fail ‘‘in the field’’ over the functional life of the system. In integrated circuit circles, reliability of a given technology begins with assurance of the reliability of the underlying building block devices — the transistors certainly, but also the passive elements such as inductors or capacitors, and the interconnects linking the various elements. In this chapter, we will focus only on the reliability of the transistors; in this case SiGe HBTs. From a transistor perspective, one ensures adequate reliability by subjecting the devices to extreme operating conditions for a given length of time, which, for a bipolar technology, historically encompasses two different operational scenarios: (1) hot carrier (hot electron or hot hole or both) stressing associated with reverse-biasing of the emitter–base (EB) junction, and (2) high forward collector current density (JC) stressing. Both reliability ‘‘modes’’ will generally be conducted under ‘‘accelerated’’ conditions (‘‘over stress’’) consisting of higher VEB and JC than the device would normally encounter during ‘‘typical use’’ circuit conditions, and will likely be performed at either elevated (e.g., 1008C for high JC stressing) or reduced (e.g.,
408C for reverse EB stressing) temperatures to invoke worst-case stress conditions. One then defines the ‘‘reliability’’ of the transistors in terms of the measured change in a given defined device metric after a given amount of time under stress (e.g., the stress time it takes to produce decrease in current gain of 10%). From this time-dependent stress data, which is by definition limited in scope due to practical testing demands, one then typically projects an extrapolated ‘‘lifetime’’ of the technology (e.g., >10 years), a procedure which clearly invokes a number of assumptions. If the projected lifetime greatly exceeds the intended system life of the part, then all is well. In practice, during technology ‘‘qualification’’ various process splits and fabrication cycle variations are often changed to improve this or that reliability metric as needed, until the checkered flag is finally raised. This is standard practice today for bipolar integrated circuit technologies. Interestingly, these basic bipolar reliability stress methodologies have been in place for well over 25 years in basically an unaltered form. Given the present reality that Si-based bipolar device performance has increased dramatically in recent years (largely due to the addition of Ge bandgap engineering), and classical bipolar circuit 4.11-525 © 2006 by Taylor & Francis Group, LLC

4.11-526

The Silicon Heterostructure Handbook

topologies have changed radically during this period from a high-speed digital ECL centric world to a wide variety of mixed-signal circuit types, it is logical to ask whether such reliability methodologies are in fact capturing all possible reliability degradation modes. As will be argued, they are not. For the purposes of this chapter, then, we define the concept of device ‘‘reliability’’ to be much broader than its standard usage in the industry, to include any possible degradation mechanism for any possible mixedsignal circuit application, in any of the various intended circuit application domains [1]. For instance, in addition to classical device reliability mechanisms associated with reverse EB and forward JC stress, new reliability issues for SiGe HBTs include, for instance, the impact of Ge film stability on technology yield, impact-ionization induced ‘‘mixed-mode’’ stress, concerns associated with scaling-induced breakdown voltage compression and operating point instabilities, and geometrical scaling-induced low-frequency noise variations. The impact of ionizing radiation on device and circuit reliability is also important in this context, but is discussed in Chapter 4.10.

4.11.2

Technology-Driven Reliability and Yield Issues

It is obviously key to the viability of SiGe HBT technology that it has a clearly demonstrated reliability and yield that are comparable to or better than existing Si BJT technology. That is, any reliability or yield loss due to the incorporation of strained SiGe films are potential technology ‘‘showstoppers.’’ Although published data on commercial SiGe technologies are sparse, there is no evidence to date that the use of thermodynamically stable SiGe films imposes any such reliability risk. Clearly, this is good news. Interestingly, the reverse-bias EB stress response of SiGe HBTs can actually be substantially better than that for aggressively scaled ion-implanted Si BJTs. This is because the very shallow, low-energy base implants needed to realize high-performance implanted Si BJTs inevitably place the peak of the base doping at the metallurgical EB junction, and thus increase the EB electric field. In contrast, for an epitaxial base device (Si or SiGe), the boron can be placed inside the base region as a boron ‘‘box’’ profile, and while the finite thermal cycle spreads the boron during processing, a boron ‘‘retrograde’’ is naturally produced at the EB junction, thereby lowering the EB electric field. Since hot electron injection under reverse-bias EB stress conditions depends exponentially on the EB electric field [2], a transistor with an epitaxial base will have a fundamental and decided advantage over an implanted base device in terms of reliability. Importantly, however, this boron retrograde at the EB junction itself produces a doping-gradient-induced electric field that retards electron transport through the base under forwardbias, degrading fT. In a SiGe HBT, this doping-induced retarding field is more than compensated by the Ge-induced accelerating field, but in an epi-base Si BJT, a performance penalty is inevitable. Thus, compositionally graded SiGe is clearly desirable for epi-base transistor design in Si technology. High yield on large wafers is key to the cost advantage Si enjoys over its III–V competition, and as in reliability, the presence of a strained SiGe layer must not unfavorably impact device and circuit yield. It does not. CMOS yield in a SiGe HBT BiCMOS technology is typically evaluated using a large embedded static random-access-memory (SRAM) yield monitor (e.g., several hundred kbit). If any of the HBT films or residuals are not properly removed, then this will be reflected in the SRAM yield. Yield values can also be easily compared with CMOS-only processes to gauge the robustness of the CMOS section of the BiCMOS process. Typical yield numbers for the 154 k SRAM in first- and second-generation SiGe technology are well above 75% [3]. SiGe HBT yield is typically quantified using large chains of small transistors wired in parallel. A chain yield ‘‘failure’’ is defined as the intersection of emitter-to-collector shorts (pipes), high EB leakage, or high CB leakage (i.e., any of the three occurrences is defined as a ‘‘bad’’ or ‘‘dead’’ device chain). For instance, 4000 0.42  2.3 mm2 SiGe HBTs is used as a yield monitor in a first generation technology, and typically has greater than 85% to 90% yield. Choice of CMOS integration scheme does not appear to affect this result. Interestingly, the primary yield failure mechanism in both the CMOS and SiGe HBTs is the same, and can be traced to the shallow-trench isolation [3]. By assuming an ideal Poisson distribution relating defect density and emitter area, one can infer the net defect density associated

© 2006 by Taylor & Francis Group, LLC

4.11-527

Reliability Issues

with a given SiGe HBT BiCMOS technology, in this case yielding numbers in the range of 100 to 500 defects/cm2. For orientation, a defect density of 426 defects/cm2 would ideally produce a 60% yield on a integrated circuit containing 100,000 0.5  2.5 mm2 SiGe HBTs, ample transistor count (and yield) to satisfy almost any imaginable mixed-signal application using SiGe technology [3]. The above yield considerations are clearly predicated on the use of thermodynamically stable SiGe films in the SiGe HBT BiCMOS technology. While stability considerations in the SiGe material system are not completely settled, and numerous ‘‘open issues’’ remain (see Ref. [4]), there do exist reasonably accurate simple theories for predicting film stability once film Ge content and dimensions are accurately known [5]. While not often openly discussed in the literature, there is a general consensus in industry that using stable SiGe films is a ‘‘good thing’’ from a yield perspective. The precise coupling of stability to local pattern density as well as local (added) strain associated with say the shallow- or deep-trench isolations, remain largely matters for conjecture, and should be quantified with dedicated research.

4.11.3 Conventional Device Degradation Mechanisms

Collector and base currents (A)

As discussed above, reliability stress and ‘‘burn-in’’ of bipolar transistors historically proceed along two different paths [2–9]: (1) reverse emitter–base (EB) stress, which is used to inject hot electrons (or holes) into the EB spacer oxide, thereby introducing generation/recombination (G/R) center traps which lead to excess non-ideal base current (Figure 4.11.1) and hence current gain degradation (Figure 4.11.2) as well as increased low-frequency noise [7]; and (2) high forward-current density stress, which also results in current gain degradation, but is generally attributed to electromigration-induced changes in the emitter contact, resulting in a decrease in collector current with increasing stress time. Accelerated lifetime testing of SiGe HBTs using reverse-bias EB stress is generally conducted under high reverse EB bias (e.g., 3.0 V) at reduced temperatures (e.g.,
408C), where carrier velocities are higher due to reduced scattering, whereas high forward-current density stress is conducted under a large JC (e.g., three to four times of the JC at peak fT ¼ 3.0–4.0 mA/mm2 for a first-generation SiGe technology) at elevated temperatures (e.g., 1008C), where electromigration is inherently more severe. Typical reverse-bias EB burn-in data from first-generation SiGe HBTs (Figure 4.11.3) show less than 5% change in the current gain after a 500-hour,
408C reverse-bias EB stress at 2.7 V [3]. Comparison of reverse-bias EB stress data of SiGe HBTs having various Ge profile shapes with a comparably constructed epi-base Si BJT control (Figure 4.11.4) suggests that there is no enhanced reliability risk associated with the SiGe layer itself [9].

10−2 10−4 10−6

t = 0 sec t = 1 sec t = 10 sec t = 100 sec t = 1000 sec AE = 0.5⫻2.5 µm2 3 V stress VCB = 0 V

10−8 10−10 0.2

0.4

0.6 0.8 1.0 Base−emitter voltage (V)

1.2

FIGURE 4.11.1 Gummel characteristics of a first-generation SiGe HBT showing the effects of reverse-bias emitter– base stress. Time (t) is measured in seconds. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-528

The Silicon Heterostructure Handbook

120

t = 0 sec t = 1 sec t = 10 sec t = 100 sec t = 1000 sec

Current gain

100 80 60 40

AE = 0.5⫻2.5 µm2 3 V stress

20 0

10−12

10−10

10−8 10−6 Collector current (A)

10−4

10−2

FIGURE 4.11.2 Current gain as a function of bias current of a first-generation SiGe HBT showing the effects of reverse-bias emitter–base stress. Time (t) is measured in seconds. (From U Gogineni, JD Cressler, G Niu, and DL Harame. IEEE Trans. Electron Dev. 47:1440–1448, 2000. With permission.)

Change in current gain (%)

0.0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 0.0

Stress time = 500 h Stress temperature = −40⬚C AE = 0.5⫻2.5 µm2 b measured at IE = 100 µA 0.5

1.0 1.5 2.0 Emitter−base reverse bias (V)

2.5

3.0

FIGURE 4.11.3 Current gain degradation due to reverse emitter–base bias stressing of a first-generation SiGe HBT as a function of stress voltage. (From DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. IEEE Trans. Electron Dev. 48:2575–2594, 2001. With permission.)

Typical high forward-current burn-in data from first-generation SiGe HBTs (Figure 4.11.5) show less than 5% change in the current gain after a 500-hour, 1008C forward-current stress at 1.3 mA/mm2 [3]. Using empirically determined acceleration factors, this result is theoretically equivalent to a more-thanacceptable 10% current gain degradation after 100,000 power-on-hours (POH) under ‘‘normal use’’ conditions (1.25 mA/mm2 at 1008C).

4.11.4

‘‘Mixed-Mode’’ Stress Effects

Optimized transistor scaling leading to such rapid advances in SiGe HBT performance inevitably results in increased current density operation (i.e., the JC at which peak fT is achieved), in the presence of increased impact ionization due to the increased collector doping required to suppress both Kirk effect and high-injection heterojunction barrier effects [4].

© 2006 by Taylor & Francis Group, LLC

4.11-529

Reliability Issues

Avg. decrease in current gain (%)

60 Si BJT (8 samples) 8% SiGe HBT (7 samples) 10% SiGe HBT (4 samples) 15% SiGe HBT (3 samples)

50 40 30

AE = 0.5⫻2.5 µm2 3.0 V stress VBE = 0.7 V 300 K

20 10 0 10−7

10−6

10−5 10−4 Stress charge (C)

10−3

10−2

FIGURE 4.11.4 Percent current gain degradation as a function of injected stress charge for a variety of SiGe profiles and a comparably constructed epi-base Si BJT. (From U Gogineni, JD Cressler, G Niu, and DL Harame. IEEE Trans. Electron Dev. 47:1440–1448, 2000. With permission.)

Change in current gain (%)

0.0 Stress current density = 1.3 mA/µm2 Stress temperature = 100⬚C AE = 0.5⫻2.5 µm2 b measured at IE = 100 µA

−1.0 −2.0 −3.0 −4.0 −5.0 −6.0

0

200

400

600 800 Stress time (h)

1000

1200

FIGURE 4.11.5 Current gain degradation due to forward current density stressing of a first-generation SiGe HBT as a function of stress time. (From DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. IEEE Trans. Electron Dev. 48:2575–2594, 2001. With permission.)

A new reliability damage mechanism in SiGe HBTs was recently reported [10, 11], which was termed ‘‘mixed-mode’’ degradation, since it results from the simultaneous application of high JC and high VCB, and which differs fundamentally from conventional bipolar device reliability damage mechanisms associated with either reverse emitter–base stress [2, 9], or high forward current density stress [13, 14]. (We note parenthetically that the 120 GHz, second-generation SiGe HBTs used in this mixed-mode stress study [12] showed negligible (acceptable) degradation for conventional reverse EB and forward JC stressing.) To carefully control the total injected charge during mixed-mode stressing, a robust time-dependent stress methodology was used which operates the transistor in common-base mode under variable forced IE and VCB conditions. The stress times ranged from 1 msec to 1000 sec, with excellent repeatability. Both forward-mode and inverse-mode (emitter and collector swapped) Gummel characteristics were

© 2006 by Taylor & Francis Group, LLC

4.11-530

The Silicon Heterostructure Handbook

measured at specific (adjustable) time intervals, and the base current degradation determined at VBE ¼ 0.5 V (VCB ¼ 0 V). Typical forward-mode and inverse-mode Gummel characteristics as a function of cumulative stress time are shown in Figure 4.11.6 and Figure 4.11.7 for a JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V mixed-mode stress condition. The mixed-mode stressing produces interface traps and subsequent G/R base current leakage at both the emitter–base spacer (forward-mode), and the shallow-trench edge (inverse-mode), consistent with Ref. [10]. The latter effect is new and unexpected compared to conventional reliability stress modes. The specific JE and VCB dependence of the damage process is shown in Figure 4.11.8 and Figure 4.11.9. Damage thresholds can be observed in second-generation SiGe HBTs at about 25 mA/mm2 (3.0 V), and VCB ¼ 1.0 V (35 mA/mm2).

100

IC and IB (A)

10−2 10−4

AE = 0.2⫻4.0 µm2 JE = 40 mA/µm2, VCB = 3 V T = 300 K

Forward-mode

EB spacer

10−6 10−8

n+poly

Base contact p STI

+ −

n

p−SiGe n damage

10−10

Increasing stress time 0, 1, 10, 100, 800 sec

10−12 0.0

0.2

0.4

0.6

0.8

1.0

VBE (V)

FIGURE 4.11.6 Forward-mode Gummel characteristics showing the base current degradation with increasing mixed-mode stress time (JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V). (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

100

IC and IB (A)

10−2 10−4 10−6 10−8 10−10 10−12 0.0

AE = 0.2⫻4.0 µm2 JE = 40 mA/µm2, VCB = 3 V T = 300 K

Base contact p+ STI

n−

EB spacer n+ poly p−SiGe n

Increasing stress time 0, 1, 10, 100, 800 sec

damage

0.2

Inverse-mode

0.4

0.6

0.8

1.0

VBE (V)

FIGURE 4.11.7 Inverse-mode Gummel characteristics showing the base current degradation with increasing mixed-mode stress time (JE ¼ 40 mA/mm2 and VCB ¼ 3.0 V). (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-531

Reliability Issues

We consistently observed random fluctuations in the base current during stress (both within a single device and device-to-device), which we believe are due to simultaneous creation and annealing of stresscreated interface traps. As argued in Ref. [13], base current fluctuations in the 1 to 100 pA range are quite consistent with reported hot-carrier-generated trap capture cross sections of 10
13 to 10
15 cm
2 for Si–SiO2 interface traps. We have performed poststress annealing studies (at 4008C for 30 min in forming gas), which demonstrate that most of the mixed-mode-induced damage can be annealed, consistent with the known behavior of interface traps. To gain deeper insight into the mixed-mode damage physics, the hot-carrier injection current was simulated under mixed-mode conditions (35 mA/mm2, 3.0 V VCB) using fully calibrated (using SIMS, device layout, and dc and ac data), isothermal two-dimensional MEDICI simulations (with the ‘‘gate

IB post-stress/IB prestress

30.0 JE = 20 mA/µm2 JE = 35 mA/µm2 JE = 40 mA/µm2

25.0 20.0 15.0

AE = 0.2⫻4.0 µm2 VCB = 3 V T = 300 K

10.0 5.0 0.0 10−3

10−2

10−1

100 Time (s)

101

102

103

FIGURE 4.11.8 Base current damage ratio versus stress time for different emitter current densities (VCB ¼ 3.0 V). Poststress data are measured at VBE ¼ 0.5 V and VCB ¼ 0.0 V. (From From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

14.0 VCB = 0V VCB = 1V VCB = 3V

IB post-stress/I B prestress

12.0 10.0 8.0 6.0

AE = 0.2⫻4.0 µm2 JE = 35 mA/µm2 T = 300 K

4.0 2.0 0.0 10−3

10−2

10−1

100 Time (s)

101

102

103

FIGURE 4.11.9 Base current damage ratio versus stress time for different collector–base voltages (JE ¼ 35 mA/ mm2). Poststress data are measured at VBE ¼ 0.5 V and VCB ¼ 0.0 V. (From From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-532

The Silicon Heterostructure Handbook

Norm. injection current

1.0 0.8 Hot carrier

0.6 0.4 Hot carrier

0.2 0.0 0

Extrinsic base contact

0.05 0.1

EB Spacer

n+ Emitter p SiGe n Si

p+ Extrinsic Base

0.15 0.2 0.25 0.3

STI

n− Si

0.35 Depth (µm) 0.4

−0.4

Cross-section Cut

−0.3

−0.2

−0.1

0

0.1

Width (µm)

FIGURE 4.11.10 Simulated distribution of the local hot-carrier current (JE ¼ 35 mA/mm2 and VCB ¼ 3.0 V). The peak injection currents are located at the emitter–base spacer and the shallow-trench isolation edge. (From C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. With permission.)

current analysis’’ module invoked). The local carrier temperatures (electron and hole) were calculated using energy balance. As with the classical ‘‘lucky-electron’’ model [15], the Si–SiO2 interface trap production is correlated with the hot-carrier injection current density [16], and is the product of the local electron current density and the probability that these electrons reach the oxide interface with kinetic energy higher than the interface trap creation activation energy (taken here to be 2.3 eV [16]). Note that the emitter–base spacer (and the shallow-trench isolation edge) are well within a mean-free path length of the (randomly moving) hot carriers generated in the CB junction by impact ionization. Figure 4.11.10 shows the normalized distribution of the simulated local hot-carrier injection current density. For both the emitter–base spacer and shallow-trench damage regions, we find that injection current density is clearly present and dominated by hot electrons (hot holes exist but in smaller numbers), consistent with the data shown in Figure 4.11.6 and Figure 4.11.7. A comparison of these second-generation, 120 GHz SiGe HBT mixed-mode stress results with stress results on more aggressively scaled third-generation 200 GHz SiGe HBTs (peak fT in the 200 GHz devices occurs at a JC of nearly 20 mA/mm2) shows that transistor lateral and vertical scaling appears to improve the mixed-mode damage thresholds at fixed JE and VCB conditions, consistent with observations reported in Refs. [10, 17]. We believe that the observed improvement is likely to be a consequence of the new ‘‘raised extrinsic base’’ structure of the 200 GHz device, which has a reduced level of the impact ionization at the device edge due to its very shallow extrinsic base formation.

4.11.5 Breakdown Voltage Constraints and Operating Point Instabilities Optimized scaling of SiGe HBTs necessarily results in the decrease of maximum operating voltages as the technology evolves. For CMOS technology, the reduction in VDD is driven by hot-carrier reliability constraints. For SiGe HBTs, this voltage reduction has a different physical origin; namely,

© 2006 by Taylor & Francis Group, LLC

4.11-533

Reliability Issues

the increase in impact ionization as the collector doping is increased to support increasingly higher operating current densities. In the case of SiGe HBTs, BVCEO decreases, for instance, from 3.3 to 2.5 to 1.7 V for first-, second-, and third-generation SiGe technology, respectively. Operating voltage compression is rarely a good thing from a circuit design and system performance perspective, except for helping maintain power dissipation as operating frequencies rise. Particularly in high-speed analog and RFIC design, and even in cascoded digital circuits, all application arenas for which bipolar technology is more naturally suited than CMOS, voltage compression can present serious problems for maintaining adequate signal-to-noise ratio, voltage headroom for transistor ‘‘stacking,’’ and loss of efficiency. This voltage compression issue in SiGe HBTs is far more interesting in many ways than it is for CMOS, since the actual maximum operating voltages that the transistor can sustain depends very strongly on how the transistor is driven (i.e., its local circuit environment), and the static as well as dynamic bias currents which it sees as it is operated. This makes for a seriously complicated situation, particularly with regard to predictive modeling and robust reliability testing. The ubiquitous BVCEO of SiGe HBT technologies, for instance, represents the worst-case bias configuration, since it electrically opens the base, thereby providing a (bad) positive feedback path for the impact ionization induced currents originating in the CB junction, leading to premature breakdown. Even in such cases, however, BVCEO is of questionable relevance to real mixed-signal circuit design since all circuits will present a dynamically varying finite impedance between the base and emitter terminals (i.e., if the base is truly open the circuit cannot do very much!). Thus, the maximum sustainable operating voltage on a SiGe HBT generally lies between that of BVCEO (worst case) and the open-emitter collector–base breakdown voltage BVCBO (best case). For instance, in a first-generation SiGe HBT, BVCEO might be 3.3 V, while BVCBO might be 10 V, three times higher. Figure 4.11.11 shows the measured maximum sustainable collector-to-emitter voltage as a function of operating current density for different input bias configurations for a second-generation SiGe HBT with a 2.2 V BVCEO and 7.5 V BVCBO. Observe the substantial (worrisome) structure in these curves. This should give any reliability engineer food for thought; since in principle the operational bias configuration of the transistor is application driven, and can even vary by

Collector current density (mA/µm2)

7.0

SiGe HBT: 120 GHz peak f T AE = 0.2⫻4.0 µm2

6.0 5.0 4.0

common-emitter: forced IB

3.0

common-emitter: forced VBE

2.0

common-base: forced IE 1.0 0.0 0

2

4 6 8 Collector−emitter voltage (V)

10

12

FIGURE 4.11.11 Collector current density as a function of applied collector to emitter voltage for three different transistor drive conditions. The data are for a second-generation 120 GHz peak fT SiGe HBT. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

© 2006 by Taylor & Francis Group, LLC

4.11-534

The Silicon Heterostructure Handbook

10.0 A E = 0.2⫻4.0 µm2 Common-base: forced IE Collector current (mA)

8.0

VBIC model measurement

6.0

4.0

2.0 SiGe HBT: 120 GHz peak fT 0.0 −1

0

1

2 3 4 5 Collector−base voltage (V)

6

7

FIGURE 4.11.12 Common-base output characteristics for forced emitter-current drive showing bias induced instabilities, and a comparison with results from a ‘‘calibrated’’ compact model. (From JD Cressler. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. With permission.)

architecture within the same basic application. Said another way, ensuring reliability of the transistor building block is no solid guarantee of overall circuit and system reliability. Perhaps even more troubling is the fact that very complex operating bias point ‘‘instabilities’’ exist in SiGe HBTs (in all bipolar devices, actually) [18, 19]. Such instabilities are generally believed to be triggered by impact ionization, resulting in so-called ‘‘pinch-in’’ current constriction phenomena, but the simple truth is that they are both highly complex in nature and extremely difficult to both predict and test for. The simple and tempting proclamation of ‘‘do not design your circuits to operate the transistors anywhere near such instabilities,’’ may seem like a safe and reasonable approach, but this stance is increasingly problematic given the ever-shrinking voltage supplies of scaled IC technologies, and the ever-increasing need for circuit designers to maximize both performance and efficiency. In addition, even circuits that are well behaved with respect to such instabilities at dc may be inadvertently forced to dynamically switch through such unstable regimes, with unpredictable consequences. This is particularly true for certain of the myriad classes of amplifiers, for instance. Figure 4.11.12 shows a typical result for a second-generation SiGe HBT operating in forced IE mode. At VCE in the range of 3 V, the output characteristics develop a chaotic-like behavior, the potential circuit implications of which will be frightening to most designers. More alarming perhaps, even well-calibrated compact models cannot capture such instabilities in a robust manner, and hence such effects are effectively not modeled in even mature technology design kits. The open questions from a reliability perspective are: (1) how do we meaningfully test our devices for exposure to such instabilities, and (2) can we predict the results of such behavior on our circuits. These questions remain largely unanswered at present.

4.11.6

Low-Frequency Noise Variations

Low-frequency noise (LFN) is up-converted to phase noise (noisy sidebands on the carrier) through the nonlinearities of transistors, producing a fundamental limit on the achievable spectral purity of communications systems. While LFN is not traditionally considered to be a reliability issue, per se, its importance in mixed-signal circuit design makes it worthy of fresh consideration, within both the context of aggressive geometrical scaling, as well as the addition of SiGe to the problem. One of the unique merits of SiGe HBTs is that they can simultaneously provide very small broadband noise and low

© 2006 by Taylor & Francis Group, LLC

4.11-535

Reliability Issues

1/f noise, giving them a decided advantage over scaled CMOS and III–V devices for high-frequency wireless building blocks limited by phase noise (e.g., oscillators and mixers) [20, 21]. SiGe HBTs are in fact capable of extremely impressive levels of LFN, even when they are aggressively scaled in geometry, vertical profile, and thermal budget to improve the broadband performance. For instance, a 1/f noise corner frequency of 220 Hz (IB ¼ 1 mA) was achieved in a 0.12  0.50 mm2 (drawn) third-generation SiGe HBT with a peak fT of greater than 200 GHz and minimum NFmin of less than 0.5 dB at 10 GHz. This combined low-frequency plus broadband noise performance is superior to any semiconductor device technology, even InP pHEMT technology. This impressive performance noted, we must also point out that an unusual statistical variation (in effect, a device-to-device statistical ‘‘scatter’’) in the LFN spectra of small geometry SiGe HBTs has been recently reported [22]. We view such variations to be inherent reliability concerns, with largely unknown circuit implications, and are generally underappreciated in the reliability community. This LFN statistical variation with size has also been observed in MOSFETs, JFETs, and BJTs in small-sized devices [23–25]. Fundamentally, the noise-generating mechanism inside transistors is generally regarded as a superposition of individual trapping or detrapping processes due to the presence of G/R centers in the device. Each G/R center contributes a Lorentzian-type (1/f 2) noise signature, and given a sufficient number of traps (a statistical ensemble), these Lorentzian processes combine to produce the observed 1/f noise behavior. At sufficiently small device size, however, the total number of traps is small enough that non-1/f behavior, and hence large statistical variations, can be easily observed. Figure 4.11.13 compares a typical family of noise spectra measured on a ‘‘small’’ SiGe HBT, with those measured on a ‘‘large’’ SiGe HBT, at fixed base current density (to allow easy comparison). In these SiGe HBTs, the noise magnitude as a function of bias current (at 10 Hz) for the devices exhibiting ‘‘clean’’ 1/f behavior exhibit a classical IB2 plus 1/AE dependence across the useful bias range, independent of the technology generation, consistent with classical number fluctuation theory [26, 27]. The noise variation in these SiGe HBTs can be quantified using a classical standard deviation approach [22]. Cross-generational noise variation data in SiGe HBT technology are shown in Figure 4.11.14 (the effect is negligible in the first-generation 50 GHz SiGe HBTs due to their larger emitter size)

J B = 14.4 µA/µm2

10−16

Dotted lines: individual devices Solid lines: average

SIB (A2/Hz)

10−18 AE = 0.82⫻3.22 = 2.64 µm2 10−20 1/f 10−22 AE = 0.22⫻0.66 = 0.15 µm2 10−24 100

101

102 Frequency (Hz)

103

104

FIGURE 4.11.13 Base current noise spectra for a ‘‘large’’ area SiGe HBT and a ‘‘small’’ area SiGe HBT showing the large statistical variation from sample-to-sample for small geometry transistors. (From J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington, DC, 2003, pp. 12–13.)

© 2006 by Taylor & Francis Group, LLC

4.11-536

The Silicon Heterostructure Handbook

Variation coefficient (δ)

2.5

2.0

200 GHz fT non-ideal IB 210 GHz fT 350 GHz fT

120 GHz fT 90 GHz fT

1.5

1.0

0.5

0 0.03

0.1

1

3

AE (µm2)

FIGURE 4.11.14 Noise variation coefficient versus emitter area for multiple SiGe HBT technology generations. The base bias current is 1.0 mA. (From J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington DC, 2003, pp. 12–13.)

[28]. Interestingly, observe that the noise variation in the 200 GHz SiGe technology generation shows anomalous scaling behavior below about 0.2 to 0.3 mm2 emitter geometry, below which the noise variation rapidly decreases. Such LFN variations in very small geometry SiGe HBTs can be qualitatively explained by calculations based on the superposition of Lorentzian (1/f 2) G/R traps [22, 23]. Both simple calculations and more sophisticated microscopic noise simulations indicate that as the emitter geometry scales, the device-to-device LFN variation becomes larger due to the decreased number of G/R traps participating in the noise process. Conventional reverse-bias EB stressing, as well as exposure to ionizing radiation, can be used to further probe and understand the origins of this unique scalinginduced reliability issue [22, 29].

4.11.7

Summary

In this chapter, I have attempted to give a new (and hopefully refreshing) perspective on the reliability issues and concerns associated with emerging SiGe HBT technologies, particularly as they are increasingly used in a wide variety of mixed-signal circuit applications. As any honest reliability engineer will admit, the scariest scenarios are those reliability failure mechanisms that may loom beyond the horizon and remain unseen at present, even to the trained eye. While I have managed to address in this chapter the conventional reliability failure mechanisms, as well introduce a number of additional nonstandard reliability issues in SiGe HBTs, which are becoming increasingly important in the emerging mixed-signal application domain, it is impossible, by definition, to anticipate them all. Thermal effects, for instance, which are unavoidable in today’s high-performance technologies operating at very high current levels, will eventually come back to plague us in a major way (they already do). Such thermal issues couple in strong ways to virtually all failure mechanisms in devices, and importantly, are both difficult to measure, and even harder to predictively model. Impact ionization induced bias point instabilities are another concern of increasing importance, which demands attention. Operating voltages necessarily compress with scaling for optimal performance, and what effect such instabilities have on circuit and system-level reliability remains unclear, and hence is worthy of increased focus. We will likely soon reach a point in certain mixed-signal circuits when simply avoiding such operational bias regimes will not be a tractable solution. All of this said, I do not view any of the reliability issues addressed here as ‘‘show-stopping’’ in

© 2006 by Taylor & Francis Group, LLC

Reliability Issues

4.11-537

nature, and as with all reliability concerns, they must be understood, quantified, and then carefully but relentlessly ‘‘designed around.’’

Acknowledgments I am grateful to G. Niu, C. Zhu, Q. Liang, R. Al-Huq, J. Johansen, Z. Jin, T. Chen, U. Gogineni, C. Grens, J. Babcock, A. Joseph, D. Harame, G. Freeman, J.-S. Rieh, D. Ahlgren, F. Guarin, J. Dunn, B. Meyerson, D. Herman, and the IBM SiGe team for their contributions. This work was supported by the Semiconductor Research Corporation, the GEDC at Georgia Tech, and IBM.

References 1. JD Cressler. Emerging SiGe HBT reliability issues for mixed-signal circuit applications. IEEE Trans. Device Mater. Reliab., 4:222–236, 2004. 2. DD Tang and E Hackbarth. Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design. IEEE Trans. Electron Dev. 35:2101–2107, 1988. 3. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD. Gillis, RA Groves, GN Hendersen, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Trans. Electron Dev. 48:2575–2594, 2001. 4. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 5. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. Solid-State Electron. 44:869–873, 2000. 6. A Neugroschel, CT Sah, and MS Carroll. Current–acceleration for rapid time-to-failure determination of bipolar junction transistors under emitter–base reverse-bias stress. IEEE Trans. Electron Dev. 42:1380–1383, 1995. 7. A Neugroschel and CT Sah. Comparison of time-to-failure of GeSi and Si bipolar transistors. IEEE Electron Dev. Lett. 17:211–213, 1996. 8. JA Babcock, JD Cressler, LS Vempati, AJ Joseph, and DL Harame. Correlation of low-frequency noise and emitter–base reverse-bias stress in epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 357–360. 9. U Gogineni, JD Cressler, G Niu, and DL Harame. Hot electron and hot hole degradation of SiGe heterojunction bipolar transistors. IEEE Trans. Electron Dev. 47:1440–1448, 2000. 10. G Zhang, JD Cressler, G Niu, and A Joseph. A new ‘‘mixed-mode’’ reliability degradation mechanism in advanced Si and SiGe bipolar transistors. IEEE Trans. Electron Dev. 49:2151–2156, 2002. 11. C Zhu, Q Liang, R Al-Huq, JD Cressler, A Joseph, J Johansen, T Chen, G Niu, G Freeman, J-S Rieh, and D Ahlgren. An investigation of the damage mechanisms in impact ionization-induced ‘‘mixed-mode’’ reliability stressing of scaled SiGe HBTs. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 185–188. 12. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, M Gordon, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC compatible CMOS using copper interconnect. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 13. RA Wachnik, TJ Bucelot, and GP Li. Degradation of bipolar transistors under high current stress at 300 K. J. Appl. Phys. 63:4734, 1988. 14. MS Carroll, A Neugroschel, and C-T Sah. Degradation of silicon bipolar junction transistors at high forward current density. IEEE Trans. Electron Dev. 44:110, 1997. 15. S Tam, PK Ko, and C Hu. Lucky-electron model of channel hot-electron injection in MOSFET’s. IEEE Trans. Electron Dev. 31:1116, 1984.

© 2006 by Taylor & Francis Group, LLC

4.11-538

The Silicon Heterostructure Handbook

16. D DiMaria and JW Stasiak. Trap creation in silicon dioxide produced by hot electrons. J. Appl. Phys. 65:2342, 1989. 17. Z Yang, F Guarin, E Hostetter, and G Freeman. Avalanche current induced hot carrier degradation in 200 GHz SiGe heterojunction bipolar transistors. Proceedings of the IEEE International Reliability Physics Symposium, 2003, pp. 339–343. 18. M Rickelt, HM Rein, and E Rose. Influence of impact-ionization-induced instabilities on the maximum usable output voltage of silicon bipolar transistors. IEEE Trans. Electron Dev. 48:774– 783, 2001. 19. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, A Stricker, D Ahlgren, and S Subbanna. Transistor design and application considerations for >200 GHz SiGe HBTs. IEEE Trans. Electron Dev. 50:645– 655, 2003. 20. LS Vempati, JD Cressler, JA Babcock, RC Jaeger, and DL Harame. Low-frequency noise in UHV/ CVD epitaxial Si and SiGe bipolar transistors. IEEE J. Solid-State Circ. 31:1458–1467, 1996. 21. R Plana, L Escotte, JP Roux, J Graffeuil, A Gruhle, and H Kibbel. 1/f noise in self-aligned Si/SiGe heterojunction bipolar transistors. IEEE Electron Dev. Lett. 16:58–60, 1995. 22. Z Jin, JD Cressler, G Niu, and A Joseph. Impact of geometrical scaling on low-frequency noise in SiGe HBTs. IEEE Trans. Electron Dev. 50:676–682, 2003. 23. M Sanden, O Marinov, and MJ Deen. A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs. IEEE Trans. Electron Dev. 49:514–520, 2002. 24. P Llinares, D Celi, and O Roux-dit-Buisson. Dimension scaling of 1/f noise in the base current of quasi-self-aligned polysilicon emitter bipolar junction transistors. J. Appl. Phys. 82:2671–2675, 1997. 25. MJ Deen, S Rumysantesev, R Bashir, and R Taylor. Measurements and comparison of low frequency noise in npn and pnp polysilicon emitter bipolar transistors. J. Appl. Phys. 84:625–633, 1998. 26. HAW Markus and TGM Kleinpenning. Low-frequency noise in polysilicon emitter bipolar transistors. IEEE Trans. Electron Dev. 42:720–727, 1995. 27. A Mounib, F Balestra, N Mathieu, J Brini, G Ghibaudo, A Chovet, A Chantre, and A Nouailhat. Low-frequency noise sources in polysilicon emitter BJTs: influence of hot-electron-induced degradation and post-stress recovery. IEEE Trans. Electron Dev. 42:1647–1652, 1995. 28. J Johansen, Z Jin, JD Cressler, Y Cui, G Niu, Q Liang, J-S Rieh, G Freeman, D Ahlgren, and A Joseph. On the scaling limits of low-frequency noise in SiGe HBTs. Proceedings of the IEEE International Semiconductor Device Research Symposium, Washington DC, 2003, pp. 12–13. 29. Z Jin, JA Johansen, JD Cressler, RA Reed, PW Marshall, and AJ Joseph. Using proton irradiation to probe the origins of low-frequency noise variations in SiGe HBTs. IEEE Trans. Nuclear Science, 50:1816–1820, 2003.

© 2006 by Taylor & Francis Group, LLC

4.12 Self-Heating and Thermal Effects 4.12.1 4.12.2

Introduction........................................................... 4.12-539 Modeling of Self-Heating ..................................... 4.12-540 Thermal Resistance Rth . Thermal Capacitance Cth . Thermal Impedance Zth

4.12.3

Thermal Resistance Measurement and Trends ..................................................................... 4.12-543 Measurement of Rth . Rth Trend in SiGe HBTs Device Layout for Reduced Rth

4.12.4

Jae-Sung Rieh Korea University

.

Thermal Effects and Device Reliability ............... 4.12-547 Thermal Runaway . Long-Term Reliability

4.12.5

Summary ................................................................ 4.12-549

4.12.1 Introduction Within semiconductor devices under external bias, the carriers experience successive scatterings while traveling under the influence of an electric field. In most scattering events, they give up kinetic or potential energy they retained, which is converted into various other forms of energy as a result of generating phonons, photons, or electron–hole pairs. Among these energy-conversion modes, the generation of phonons, or the increase of lattice vibration level, is the most frequently encountered mode and results in the generation of heat in the devices. The consequent junction temperature rise, or self-heating, significantly influences device behaviors. It modulates the device operation condition since the characteristics of semiconductors are inherently given as a function of temperature. Device reliability is also affected since the raised temperature promotes most of the long-term degradation mechanisms as well as the catastrophic failures of the devices. Therefore, an accurate characterization of self-heating is critical for the precise prediction of device operation and degradation as well as the prevention of device failures. Historically, self-heating has been a concern mainly for high-power devices in which extensive power consumption results in a great heat generation. However, recent aggressive scalings intended for speed enhancement, which usually accompany a considerable increase in operation current level, have made the self-heating in high-speed devices a major concern. Hence, self-heating has become a generic issue for semiconductor systems in general, and their thermal properties need to be properly analyzed along with the electrical properties. This chapter provides an overview of the issues related to self-heating and thermal effects in SiGe HBTs. As SiGe HBTs are nearly identical to conventional Si BJTs from the thermal point of view, except for a fractional amount of Ge included in the base, the analyses and discussions made in this review are for Si BJTs in general. Although SiGe in the base has a poorer thermal conductivity than Si [1], its impact will not be pronounced since the principal heat source in bipolar transistors is the base–collector space–charge region and most of the generated heat is dissipated downward through the substrate. Section 4.12.2 overviews the modeling of self-heating and its impact on device operation, followed by 4.12-539 © 2006 by Taylor & Francis Group, LLC

4.12-540

The Silicon Heterostructure Handbook

Section 4.12.3 in which thermal resistance measurement methods are introduced along with the trend of the thermal resistance for various SiGe HBT dimensions and structures. In Section 4.12.4, selected reliability issues related to self-heating are discussed.

4.12.2

Modeling of Self-Heating

Thermal Resistance Rth The heat conduction in a homogeneous isotropic solid is described by following time-dependent equation [2]: r2 T ¼

rc @T , k @t

(4:12:1)

where T is temperature, r is density, c is specific heat, k is thermal conductivity, and t is time. With appropriate initial and boundary conditions, the temperature is determined as a function of time and position within the conducting media. The thermal resistance Rth is defined as the ratio of the final value of the temperature at a given position ~ r and the dissipated power (Pdiss) from the heat source: r) ¼ Rth (~

T (~ r , t ¼ 1)
T (~ r , t ¼ 0) DT (~ r) ¼ : Pdiss Pdiss

(4:12:2)

Although Rth is a function of position in general, Rth of a device conventionally refers to the thermal resistance at the region inside the device with the peak temperature, which is called the junction temperature Tj. Hence, following position-independent formula is widely accepted: Tj ¼ Rth Pdiss þ T0 ,

(4:12:3)

where Rth is the thermal resistance of the given device, and T0 is the temperature in the absence of power dissipation, or the ambient temperature. The simplest practical boundary condition for the heat dissipation in a device fabricated on a semiconductor substrate is a hemisphere with an adiabatic surface just above the heat source. Although the introduction of an image heat source above the surface simplifies such boundary condition [3], there exists no closed-form solution for this apparently simple geometry, implying the level of complexity involved in the proper modeling of Rth in practical devices. Joy and Schlig [3] proposed an approximate expression, based on numerical calculations, to best represent Rth for such boundary condition: Rth ¼

1 pffiffiffiffiffiffiffiffi f (L, W , H, D) 2k LW ’

1 pffiffiffiffiffiffiffiffi , 4k LW

(4:12:4a) (4:12:4b)

where f (L, W, H, D) is a function of the dimensions for the heat source: length (L), width (W), height (H), and the distance from the surface (D). For bipolar transistors, in which most of heat is generated within the base–collector space–charge region, the dimensions of this region suitably serve for the estimation when substituted. Equation (