Frequency Synthesizers: From Concept to Product (Artech House Microwave Library)

Frequency Synthesizers Concept to Product

For a complete listing of titles in the Artech House Microwave Library, turn to the back of this book.

Frequency Synthesizers Concept to Product

Alexander Chenakin

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library. Cover design by Vicki Kane

ISBN 13: 978-1-59693-230-2

© 2011 ARTECH HOUSE, INC. 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

To my family

Contents xiii

Preface 1

Parameters and Architectures

1

1.1

Frequency Synthesizer Concept

1

1.2 1.2.1 1.2.2 1.2.3 1.2.4

Main Parameters Frequency and Timing Spectral Purity RF Output Power Other Parameters

3 3 5 12 14

1.3

Form Factors and Applications

14

1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9

Control Interfaces Parallel Interface SPI I2C RS-232 USB GPIB VXI PXI LXI

16 16 17 20 20 20 21 21 22 23

vii

Frequency Synthesizers: Concept to Product

viii

1.4.10

AXIe

24

1.5 1.5.1 1.5.2 1.5.3

Main Architectures Direct Analog Synthesizers Direct Digital Synthesizers Indirect Synthesizers

24 25 31 35

References

38

2

Building Blocks

41

2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5

Oscillators Phase Noise in Microwave Oscillators Resonators Coupling Active Devices Noise Reduction Techniques

41 42 45 53 53 54

2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8

Frequency Multipliers Frequency Multiplication Single-Diode Multipliers Balanced Diode Multipliers Antiparallel Diode Multiplier Digital Logic Multipliers Step-Recovery-Diode Multipliers Varactor Multipliers Transistor Multipliers

58 58 59 60 62 62 63 64 64

2.3 2.3.1 2.3.2

Frequency Dividers Digital Dividers Analog Dividers

64 65 69

2.4 2.4.1 2.4.2 2.4.3 2.4.4

Frequency Mixers Frequency Mixing Harmonic Mixers Image-Reject Mixers IQ-Modulators

69 70 71 72 73

2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5

Phase Detectors Balanced Mixer Sampling Mixer Exclusive-OR Gate Flip-Flop Phase-Frequency Detector

74 74 75 75 76 76

Contents

ix

2.5.6

Integrated PLL Components References

79 82

3

Synthesizer Construction

87

3.1

Transmission Lines and Distributed Elements

87

3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6

Transmission Line Basics Transmission Line Types Microwave Materials Discontinuity Effects Coupling Distributed and Lumped Elements

87 89 92 95 95 96

3.2

Chip-and-Wire Approach

97

3.3

Printed Circuit Board

98

3.4 3.4.1 3.4.2 3.4.3 3.4.4

Packaging Electrical Interface Environmental Protection Shielding Mounting and Heat Sinking References

101 101 103 103 106 107

4

Design Process

109

4.1

Specifications

109

4.2

Block Diagram

110

4.3

Schematic

116

4.4

Board Layout

133

4.5

Assembly

134

4.6

Mechanical Design

135

4.7

Control Software

136

4.8

Troubleshooting

138

4.9

Testing

141

Frequency Synthesizers: Concept to Product

x

4.10

Documentation

145

References

146

5

Improving Performance

149

5.1

Performance Trade-Offs

149

5.2

Fractional-N

151

5.3

Using a DDS

155

5.4

Frequency Offset Schemes

158

5.5

Multiloop Architectures

163

5.6

Frequency Acquisition

164

5.7

Lock Monitoring

169

5.8

Fast-Switching Designs

170

5.9

VCO or YIG?

172

5.10

Reference Generation and Distribution

176

5.11

Filtering Harmonics

177

5.12

Frequency Extension

181

References

184

6

Advanced Functions

187

6.1

Frequency Stability and Synchronization

187

6.2 6.2.1 6.2.2 6.2.3

Frequency Control Blanking Frequency Sweep List Mode

191 191 192 194

6.3 6.3.1 6.3.2 6.3.3 6.3.4

Output Power Control Open-Loop Control Closed-Loop Control Power Equalizer Power Sweep

194 194 196 197 197

Contents

xi

6.3.5

Power Mute

198

6.4 6.4.1 6.4.2 6.4.3 6.4.4

Modulation Pulse Modulation Amplitude Modulation Frequency and Phase Modulation Complex Modulation References

198 198 200 201 204 206

About the Author

207

Index

209

Preface Frequency synthesizers have evolved over time, and this book offers an overview of well-established and recently developed techniques. It is primarily intended for engineers in their first years of practice and serves as a quick and effective guide to mastering professional skills. This book aims to bridge the gap between basic theoretical knowledge and the years of work required to build practical experience. It covers all design aspects including main architectures, key building blocks, and practical circuit implementations. This book is also likely to be helpful to professionals (engineers, researchers, consultants, and marketing and sales specialists), since it is meant to supplement technical articles, application notes, and design recipes in the field of frequency synthesis. This book is divided into six chapters that guide the reader from introductory material to advanced design topics. Chapter 1 provides a brief introduction to the field of frequency synthesis. It starts with general definitions and requirements followed by a review of main synthesizer architectures. Direct analog, direct digital, and indirect techniques are compared in terms of performance, circuit complexity, and cost impact. Chapter 2 continues with a review of key building blocks from the perspective of their practical use in microwave frequency synthesizers. The main focus is on how undesired signals (spurs and phase noise) are generated and then propagate through synthesizer components. Oscillators, frequency multipliers, dividers, mixers, phase detectors, and complex integrated circuits are discussed. The next logical step is to examine how the individual synthesizer components are physically connected together. Chapter 3 focuses on constructional and

xiii

xiv

Frequency Synthesizers: Concept to Product

packaging principles used for building microwave frequency synthesizers. It begins with a brief overview of transmission line theory, types of transmission lines, characteristic impedance, losses, discontinuity and coupling effects, microwave materials, and distributed and lumped elements. Chapter 3 continues with a review of the most popular assembling techniques including hybrid chip-and-wire and printed circuit board approaches. Packaging aspects, including grounding and shielding effects, are also discussed. Chapter 4 moves from general concepts to practical applications. A simple single-loop PLL example is used to demonstrate the most important aspects of the design process from the block diagram to production. The chapter begins by capturing and formulating design goals as formal specifications. A block diagram is created as a high-level pictorial model, which helps the reader to understand the overall design concept. It is transformed into a schematic that shows all individual components and their connections. Component selection and circuit optimization are discussed in detail. The design is laid out and implemented on a printed circuit board. It is discussed how to bring the assembled board to life through step-by-step troubleshooting of its individual blocks. Finally, the circuit is refined, tested, and properly documented. Additional small changes may be required until the design develops into a stable product that can be released to production. The simple single-loop PLL synthesizer scheme analyzed in Chapter 4 exhibits various limitations and trade-offs. Chapter 5 examines various design alternatives to achieve different performance objectives such as fast switching speed, low phase noise, and fine resolution. The design trade-offs are analyzed and complemented with a review of fractional-N, DDS, frequency offset, multiloop, and other schemes. Chapter 5 also covers such important design aspects as initial frequency acquisition, lock monitoring, oscillator selection, harmonic filtering, and frequency extension. The main function of any frequency synthesizer is to deliver a stable and clean signal. However, inside any synthesizer there are many circuits that can carry multiple functions and be reused to increase the functionality without a significant increase in cost. Chapter 6 concludes the book with notes on advanced design options that address frequency synchronization, sophisticated frequency and power control, and various modulation functions. Note that this book serves as a live guide to practical designs rather than acting as a comprehensive handbook. Although basic theoretical background is presented, mathematical treatment is kept at a minimum and left to numerous reference sources readily available. Several topics would require separate texts of their own. Further details can be found in the attached references listed in accordance with the individual chapter topics. Many pertinent sources have been cited; I apologize in advance to anyone who may have been slighted.

Preface

xv

The work presented in this book could not have happened without the help of many people. I express my sincere appreciation to colleagues from Phase Matrix, Inc. as well as other organizations that supported this endeavor. I especially thank Richard Bush, Pete Pragastis, Suresh Ojha, Heather Brown, Ronni Basu, Anthony Estrada, and Doug Padrick for their valuable suggestions that complemented the text. Finally, I would like to thank the Artech House team for their effort in publishing this book.

1 Parameters and Architectures The frequency synthesizer is a key component of virtually any radio-frequency (RF) and microwave test-and-measurement, communication, and monitoring system. It generates a stimulus signal and is used as a local-oscillator (LO) source in a variety of upconversion and downconversion schemes. Synthesizer designs utilize various techniques and are almost as diverse as the number of their applications [1–6]. This chapter provides a brief introduction to the field of frequency synthesis. It starts with general definitions and requirements followed by a review of the main synthesizer architectures. Direct analog, direct digital, and indirect techniques are compared in terms of performance, circuit complexity, and cost impact.

1.1 Frequency Synthesizer Concept A frequency synthesizer is an electronic device that translates one (or more) input base (reference) frequency to a number of output frequencies as illustrated in Figure 1.1. It can be treated as a “black box” containing individual components or building blocks such as voltage-controlled oscillators (VCOs), frequency dividers, multipliers, mixers, and phase detectors, which, when properly connected, perform this translation function. Its structure is defined by a system architecture that describes the organization and relationships among the individual components. Synthesizer architectures can be classified into a few main groups as indicated in Figure 1.2. The direct architectures are intended to create the output

1

2

Frequency Synthesizers: Concept to Product Δf

Frequency synthesizer fREF

Figure 1.1

fMIN

fMAX

Frequency synthesizer concept.

Frequency synthesizers

Indirect

Direct

Analog

Digital

Analog

Digital

Hybrid techniques

Figure 1.2

Frequency synthesizer classes.

signal directly from the available base frequency signals either by manipulating and combining them in the frequency domain (direct analog synthesis) or by constructing the output waveform in the time domain (direct digital synthesis). The indirect methods assume that the output signal is regenerated inside the synthesizer in such a manner that the output frequency relates (e.g., is phase-locked) to the input reference signal. Similarly, indirect synthesis can be accomplished with analog and digital techniques. Indirect synthesizers are also associated with integer and fractional-N phase-lock-loop (PLL) techniques, as will be further discussed in Chapter 5. A practical synthesizer, however, is usually a hybrid design that combines various techniques to achieve specific design goals based on the destination of the product. A good example is a multiloop synthesizer that is essentially a combination of direct analog (frequency mixing) and indirect PLL methods. By combining both technologies, it is possible to take advantage of the best aspects of each. These hybrid solutions, along with their design limitations and trade-offs, are discussed in more detail in Chapter 5.

Parameters and Architectures

3

1.2 Main Parameters An ideal synthesizer is intended to provide a pure sine-wave signal that, in the frequency domain, is represented as a pair of delta functions. Such an ideal signal would appear as a single tone (or, in other words, an indefinitely narrow line) on a spectrum analyzer screen. In reality this line is spread by signal fluctuation effects (referred to as phase noise or jitter); some other signal artifacts (spurs and harmonics) are also present. In the time domain, these artifacts manifest themselves as signal waveform distortion. The quality and usability of synthesized signal are determined by a few key parameters or specifications. The synthesizer’s parameters can be divided into a few groups depicting its frequency and timing (frequency coverage, resolution, accuracy, switching speed), spectral purity (harmonics, spurs, phase noise), and RF output power (output power, control range, step size, accuracy, flatness, impedance, return loss) characteristics, as well as how the synthesizer interfaces with the outside world (control interface, bias, power consumption, and size). 1.2.1

Frequency and Timing

Frequency coverage or range denotes the range of frequencies that can be generated by the synthesizer. It is specified in the units of hertz (megahertz and gigahertz) by indicating the minimum and maximum frequencies generated by the synthesizer. Frequency resolution or step size is the maximum frequency difference between two successive output frequencies indicated in Figure 1.1 as Δf = fn+1 − fn. The frequency coverage and resolution are fundamental synthesizer specifications set by a particular application. Some applications (e.g., test and measurement) require wide bandwidth and fine frequency resolution, while others need a relatively narrowband (10–20%) coverage with a rough step size or just a single fixed frequency. Frequency accuracy indicates the maximum deviation between the synthesizer’s set output frequency and its actual output. Frequency accuracy is normally determined by the reference signal, which can be internal or external to the synthesizer. Frequency synthesizers usually employ a crystal oscillator as an internal reference. The crystal oscillator’s temperature stability and aging are important characteristics that define the synthesizer’s frequency accuracy. Temperature stability denotes the maximum frequency drift over the operating temperature range and is usually expressed in ppm. The term ppm is an acronym for parts per million—a dimensionless coefficient equal to 10−6. For example, the temperature stability of 0.5 ppm for a 100-MHz crystal oscillator means that the oscillator frequency can drift up to 50 Hz (0.5 × 10−6 × 100 × 106 Hz) over the specified operating temperature range.

4

Frequency Synthesizers: Concept to Product

Aging is a change in frequency over time that occurs because of changes in the resonator material or a buildup of foreign material on the crystal. It is also specified in ppm over a certain period of time. Aging leads to a permanent frequency error; thus, it is good practice to use mechanical or electronic frequency adjustment means to compensate for internal reference aging. Switching or tuning speed determines how fast the synthesizer transitions from one desired frequency to another and is defined as time spent by the synthesizer between these two states (thus, the switching time is a more proper term). The definition seems straightforward for a hypothetical dual-frequency synthesizer (shown in Figure 1.3) where the frequency change is performed with an electronic switch. In this case, the switching time is simply a propagation delay inserted by the switch and its control circuit. However, a practical frequency acquisition scenario is usually a more complex process, as illustrated in Figure 1.4 for a PLL synthesizer. Let’s assume that at time t0 we send a command requesting the synthesizer to change its frequency from f1 to f2. Before starting the transition, the synthesizer needs to receive the command (which can be a digital data stream or a single trigger pulse), make all necessary calculations according to the synthesizer’s frequency tuning algorithm, and then program its individual devices (e.g., a programmable frequency divider in the PLL feedback path). Since this process takes a certain amount of time, the frequency transition itself starts at t1. Then the synthesizer’s PLL circuit steers the VCO to the desired frequency by changing the voltage on its tuning port. The process is not instantaneous and is similar to the process of charging a capacitor (that is a part of the PLL filter indeed). Moreover, the VCO can pass on the destination frequency; thus, the PLL has to return the VCO output back by correcting its tuning voltage. Depending on the dynamic characteristics of a particular loop filter, this process also takes time before the PLL brings the VCO output close enough to the desired frequency in order to meet the system requirements (point t2). The total switching time is calculated from the time when the synthesizer receives a command to the time it approaches the desired frequency with a specified accuracy (e.g., ±1 MHz, ±50 kHz, ±0.1 ppm, and so forth). It is also assumed that the synthesizer can jump from any one frequency

F1

F2

Figure 1.3

Switching time is set by a propagation delay inserted by the switch.

Parameters and Architectures

5 ΔF

f

f2

f1 t0

Figure 1.4

t1

t2

t

Frequency acquisition in a PLL synthesizer.

to any other frequency within its operating frequency range (unless otherwise specified). The switching speed is determined by a particular synthesizer scheme and is usually a trade-off between other synthesizer parameters, such as step size, spurs, or phase noise. 1.2.2

Spectral Purity

Harmonics appear in the synthesizer spectrum as integer multiples of the output frequency because of signal distortion in nonlinear components. For example, if the fundamental frequency is represented by f, the frequencies of the harmonics would be represented by 2f, 3f, and so forth. Harmonics are expressed in dBc (decibels relative to the carrier) and represent the power ratio of a harmonic to a carrier signal as shown in Figure 1.5. Harmonics usually do not cause serious problems since they are well separated from the main tone and can be easily filtered out. Moreover, they are often recreated in a nonlinear device (such as a mixer) connected to the synthesizer. The range of −15 to −30 dBc is acceptable

P, dBm ΔP, dBc

f

2f

3f

Figure 1.5 Harmonics appear in the synthesizer spectrum due to signal distortion in nonlinear components.

6

Frequency Synthesizers: Concept to Product

in many cases, although the level should be reduced to −50 dBc or even lower in some harmonic-sensitive applications such as test-and-measurement instruments. For a narrowband synthesizer, this is easily achieved by placing a lowpass filter at the output. A switched filter bank or a tunable filter is required for bandwidths reaching or exceeding an octave. Subharmonics are created at frequencies that are “subharmonically” related to the main signal such as f /2, f /3, and so forth. Propagating through nonlinear components, these signals exhibit their own harmonics. Thus, in a more general case, the subharmonics are considered as products appearing at N/K of the output frequency, where N and K are integers. A typical example that can demonstrate the creation of subharmonics is a frequency doubler, which is often used to extend the synthesizer output frequency range. As a nonlinear device, the doubler generates a number of harmonics of the incoming signal. It usually employs a balanced scheme that intends to suppress odd products as shown in Figure 1.6. Since the second harmonic now becomes the main signal, all the odd products, which are not completely suppressed, do not meet the harmonic relationship with respect to the desired output and are, therefore, treated as subharmonics. Another example is divider leakage, which can be found in PLL circuits as illustrated in Figure 1.7. In this example, the VCO signal at 2 GHz is divided down to 1 GHz by a frequency divider inserted into a PLL feedback path. The divider output is rich in odd harmonics due to the square-wave waveform of the signal produced by the divider. These products can leak back to the VCO output due to insufficient isolation of the feedback path and appear as subharmonics with respect to the VCO’s main signal. Similar to harmonics, subharmonics of a small order (e.g., 1/2 or 3/2) are well separated from the main output and, hence, can be easily filtered. However, high-order products can present a serious problem due to decreasing separation from the main tone. As a common rule, the subharmonics are normally treated as spurious (i.e., nonharmonically related) signals. Spurious signals or spurs are undesired artifacts created by the synthesizer at some discrete frequencies that are not harmonically related to the output signal

12 34

1

12 34

×2

Figure 1.6

A frequency doubler can generate subharmonic products.

Parameters and Architectures

2 4

7

1 2 34

VCO

÷N 1 2 34

Figure 1.7

Another subharmonic example.

ΔP, dBc

f

Figure 1.8

2f

3f

Spurious products are not harmonically related to the output signal.

(Figure 1.8). Spurs can come from different sources such as PLL reference spurs, mixer intermodulation products and LO leakage, some internal auxiliary signals, or even external signals coming through the bias or control interface. Although the spurs seem randomly positioned in the synthesizer spectrum, their location is mostly determined by a particular synthesizer architecture and frequency plan. In contrast to harmonics, the spurs are much more troublesome products that can limit the ability of receiving systems to resolve and process a desired signal. Spurs can sit very close to the main tone and in many cases cannot be filtered. Thus, the spurious level has to be minimized, typically to −60 dBc relative to the main signal, although many applications require bringing this level even lower. This presents a certain design challenge, especially if a small step size is required. A different concern is mechanically induced spurs usually referred to as “microphonics.” These spurs appear due to the sensitivity of certain synthesizer components to external mechanical perturbations and are treated by mechanical (e.g., damping) and electrical (e.g., wideband PLL) means. Phase noise is a measure of the synthesizer’s short-term frequency instability, which manifests itself as random frequency fluctuations around the desired

8

Frequency Synthesizers: Concept to Product

tone. As mentioned earlier, the output of an ideal synthesizer is a pure sine-wave signal with amplitude A0 and frequency ω0 = 2πf0 that is described by VOUT = A0 sin ω0t

(1.1)

However, in reality the output signal demonstrates amplitude and phase variations (Figure 1.9) because of noise fluctuations in the synthesizer’s components, which can be represented as follows: VOUT = ( A0 + a (t )) sin ( ω0t + ϕ (t ))

(1.2)

where a(t) and ϕ(t) are the amplitude and phase fluctuations, respectively. Amplitude noise is rarely as critical as phase noise. The amplitude variations can be easily reduced by balanced mixers, amplifiers in compression, diode limiters, or an automatic level control circuit. Hence, the phase effects generally dominate, reducing (1.2) to VOUT = A0 sin ( ω0t + ϕ (t ))

(1.3)

These phase fluctuation effects result in uncertainty on the signal zerocrossing, which in the time domain is referred as jitter. How do these fluctuations affect the synthesizer output spectrum? Let’s imagine that the phase fluctuations ϕ(t) are caused by an unwanted fixed-frequency signal ωm = 2πfm that modulates the synthesizer output frequency (for example, by approaching and modulating the VCO tuning port) and are expressed as ϕ (t ) = Am sin ωmt

(1.4)

In this case, the output signal can be described by VOUT = A0 sin ( ω0t + Am sin ωmt ) Amplitude variations

Phase variations

t

Figure 1.9

(1.5)

t

The synthesizer output signal exhibits both amplitude and phase variations.

Parameters and Architectures

9

With a well-known trigonometric identity sin(α + β) = sin α cos β + cos α sin β, the expression (1.5) is transformed into VOUT = A0 ⎡⎣sin ω0t cos ( Am sin ωmt ) + cos ω0t sin ( Am sin ωmt )⎤⎦

(1.6)

Assuming that the amplitude of the modulating signal Am is small (we can restrict a large unwanted signal at the most sensitive point in our design, right?), we can simplify corresponding terms of (1.6) to cos ( Am sin ωmt ) ≈ 1

(1.7)

sin ( Am sin ωmt ) ≈ Am sin ωmt

(1.8)

reducing the expression (1.6) to VOUT ≈ A0 ( sin ω0t + Am cos ω0t sin ωmt )

(1.9) 1

Using another elementary trigonometric formula, sin α cos β = [sin (α 2 + β) + sin (α − β)], the expression (1.9) is further modified to A ⎧ ⎫ VOUT ≈ A0 ⎨sin ω0t + m ⎡⎣sin ( ωmt + ω0t ) + sin ( ωmt − ω0t )⎤⎦ ⎬ 2 ⎩ ⎭

(1.10)

and finally

VOUT ≈ A0 sin ω0t +

A0 Am AA sin ( ω0 + ωm ) t − 0 m sin ( ω0 − ωm ) t 2 2

(1.11)

Note that (1.11) has three sinusoidal terms related to ω0, ω0 − ωm, and ω0 + ωm. Thus, in the frequency domain, the output signal is no longer a single spectral line but adds two spurious sidebands equally spaced by fm (below and above the main signal) as shown in Figure 1.10. This is a typical spectrum that represents spurious sidebands caused by a modulating signal of a fixed frequency fm. Obviously, if fm is not a fixed frequency but changes randomly, the sidebands also spread randomly over frequencies both above and below the nominal signal frequency. What spectrum should we observe in this case? To answer this question, let’s imagine that we can take a series of hypothetically instantaneous screenshots of such a fluctuating signal. Intuitively, we can say that in most cases we will

10

Frequency Synthesizers: Concept to Product PLL Spurs dBm 6 GHz 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80

Start: 5.9750 GHz Res BW: 300 Hz

Vid BW: 1 kHz

Stop: 6.0250 GHz Sweep: 200.00s

Figure 1.10 The modulation on a VCO tuning port results in spurious sidebands below and above the main tone.

find the output somewhere close to the desired nominal frequency rather than far away from it. In other words, a “good” synthesizer design generates a signal that contains most of its energy around the nominal frequency as illustrated in Figure 1.11. How can we quantify this intuitive view of the spectral distribution? Obviously, we should do it by measuring the output power at many frequencies away from the nominal frequency and comparing it to the power at the nominal frequency. This leads us to a quantitative definition of the phase noise as the ratio of the noise power found in a 1-Hz bandwidth at a certain frequency offset Δf to the total power at the carrier frequency f0, which can be written as ⎛ Pf1 Hz ⎞ + Δf  = 10 log ⎜ 0 ⎟ ⎝ Pf 0 ⎠

(1.12)

This ratio is normally taken in the logarithmic scale; hence, the phase noise is expressed in units of dBc/Hz (dBc per hertz) at various offsets from the carrier frequency and is usually specified by a table or as a graphic representation. Phase noise is one of the major parameters that ultimately limits the performance of RF and microwave systems. To illustrate this, let’s examine the ability of a microwave receiver to resolve a signal of small amplitude. The receiver is essentially a mixer that converts the signal down and processes it at a lower

Parameters and Architectures

11

P

 1 Hz Δf

f0

Figure 1.11 signal.

f

Phase noise manifests itself as random frequency fluctuations around the output

intermediate frequency (IF). Naturally, the conversion is affected by the quality of the available LO source as illustrated in Figure 1.12. A receiver utilizing an LO source with excessive phase noise (source A) will not be able to detect the signal since it is masked under the phase noise. In order to receive the desired signal, either the transmitter has to provide higher output power, or a better LO source (source B) is required. Therefore, phase noise generated by the frequency synthesizer is a critical parameter that imposes the ultimate limit on the system’s ability to resolve signals of small amplitude. Phase noise minimization is a primary design concern—it demands a specific effort and usually results in a trade-off between other synthesizer parameters. dBm Source A Source B Signal 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 1.12

Start: 9.9990 GHz Res BW: 10 kHz

Vid BW: 100 Hz

Stop: 10.0010 GHz Sweep: 4.00s

Excessive phase noise limits the ability to resolve a signal of small amplitude.

12

1.2.3

Frequency Synthesizers: Concept to Product

RF Output Power

Output power is a measure of the synthesizer output signal strength specified in units of watt or, more frequently, in dBm. The term dBm refers to the ratio in decibels of the measured power referenced to 1 milliwatt. The relationship between these two units is expressed by PdBm = 10 log Pmwatt

(1.13)

The RF output power can vary within a wide range depending on a particular application. A typical scenario assumes the frequency synthesizer as an LO source driving a frequency mixer in a variety of upconversion and downconversion schemes. This normally requires a 10- to 17-dBm output signal, although some applications need more power. A simple synthesizer usually delivers a fixed power level that cannot be changed. More complex designs provide an ability to control the output power in a specified range. In the latter case, the output power control range (i.e., the minimum and maximum values between which power can be set) and the power step size (i.e., the minimum change between two consecutive power settings) are specified as well. Note that output power can differ from its set value. This discrepancy is described by the output power accuracy that defines the absolute maximum variance between programmed and actual (i.e., measured) power values. Output power flatness denotes the difference between the maximum and minimum power values within the operating frequency range as shown in Figure 1.13. The output power usually tends to decrease at higher frequencies because of a “natural” gain roll-off of individual devices in the synthesizer output chain. Sophisticated synthesizer designs include compensation mechanisms using either hardware (e.g., gain equalizers) or software (e.g., power calibration) methods. The output power also varies with temperature change (Figure 1.14) and P

PMAX PMIN

f

Figure 1.13 Output power flatness denotes the difference between the maximum and minimum power values across the operating frequency range.

Parameters and Architectures

13

P T = 0°C C T = 25°C T = 55°C

f

Figure 1.14

Output power variations caused by temperature change.

is specified as a maximum power variation over operating temperature range. These two parameters are often combined together to present the total power variations at all operating conditions. Output impedance is an important characteristic since RF and microwave devices are supposed to be matched with other devices when connected. At microwave frequencies the source and load impedances are normally set to 50 ohms, although some equipment works in other environments (e.g., 75 or 600 ohms). When the source and load impedances are mismatched, some incident power is reflected back. As a result, not all of the available power from the source is delivered to the load. To describe this “loss,” the concept of return loss is introduced as RL = −20 log Γ

(1.14)

where Γ is the voltage reflection coefficient well known from transmission line theory. The return loss is measured in decibels and indicates how close the synthesizer output impedance is to 50 ohms (or another specified value). The best scenario assumes no reflection (i.e., Γ = 0), which corresponds to negligibly small return loss. On the other hand, a return loss of 0 dB corresponds to total reflection when |Γ| = 1 and all incident power is reflected. Alternatively, the output match can be described by the voltage standing wave ratio or VSWR, which relates to the voltage reflection coefficient as

VSWR =

1+ Γ 1− Γ

(1.15)

The VSWR of 2:1 (that roughly corresponds to a −10-dB return loss) is typically an acceptable level for many synthesizer designs. A better match is

14

Frequency Synthesizers: Concept to Product

required for some demanding applications and can be achieved by connecting an attenuator to the synthesizer output as depicted in Figure 1.15. This, however, results in reduced power level. 1.2.4

Other Parameters

Other specifications may include power supply (DC or AC voltage, current, power consumption), mechanical (size, weight, mounting dimensions), and environmental (temperature, humidity, altitude, vibration) characteristics as well as some special features such as dual output (or a number of outputs), various modulation options, and many other functions tailored to specific applications.

1.3 Form Factors and Applications Synthesizers come in a variety of forms ranging from tiny PLL chips and moderate-size modules to bench-top signal generators. Single-chip synthesizers are available in a die form or as surface-mount integrated circuits (ICs). They include key elements (such as RF and reference dividers, phase detector, and lock indicator) that are required to build a simple single-loop PLL synthesizer. More complex ICs include a built-in VCO, multiple PLLs, direct digital synthesizer (DDS), and other valuable components integrated on a single chip. Such ICs are installed on a printed circuit board (PCB) with additional circuitry (e.g., loop filter components) and are used in many applications, including various communication systems, wireless portable devices, FM radio, and TV receivers. They are also utilized as components in more complex, hybrid synthesizer designs. The next level of integration includes PCB-based modules that range from small, surface-mount, “oscillator-like” designs to more complex connectorized assemblies as exhibited in Figure 1.16. The level of complexity varies from simple single-loop PLLs to sophisticated multiloop and DDS-based designs. These are normally installed into larger systems that provide all necessary control functions as well as mechanical support and electrical shielding. Applications include various test-and-measurement, communication, and monitoring systems. Alternatively, such PCB assemblies can be packaged into metal housings and presented as complete, stand-alone synthesizer modules. These can be quite so-

Frequency synthesizer

Figure 1.15

An attenuator at the synthesizer output improves its return loss.

Parameters and Architectures

Figure 1.16

15

A PCB-based synthesizer module. (Courtesy of General Electronic Devices, Inc.)

phisticated designs (such as that shown in Figure 1.17) that include an internal microcontroller to control individual devices inside the synthesizer. Connectorized synthesizer modules (often called “bricks”) can be used to build larger bench-top and rack-mountable signal generators for test-andmeasurement applications. These are fairly complex, system-type instruments (Figure 1.18) complete with an AC power supply, display, and various communication interfaces. They come with high-end technical characteristics, precise calibration, and extended functionality including frequency and power sweep, various modulation modes, built-in modulation sources, and many other functions.

Figure 1.17 The QuickSyn synthesizer module features high performance and extended functionality. (Courtesy of Phase Matrix, Inc.)

16

Frequency Synthesizers: Concept to Product

Figure 1.18 A bench-top signal generator. (Copyright Agilent Technologies, Inc. 2007. Reproduced with permission.)

1.4 Control Interfaces The control interface is an electrical link that provides connection and data exchange between two (or more) devices such as a frequency synthesizer and host controller. There is a large variety of interfaces and data-exchange formats used in frequency synthesizers; the most popular ones are described next. 1.4.1

Parallel Interface

The parallel interface assumes transmitting and receiving control signals over multiple wires at one time. The number of wires heavily depends on the number of functions to be controlled. To illustrate this, let’s come back to the hypothetically simplest dual-frequency synthesizer example shown in Figure 1.3. Only a single control line is required to switch between two frequencies. If we need more output frequencies, more switches and more control lines must be added. Using a binary code, we can control as many as 2n frequencies, where n is the number of control lines (in addition to a ground connection). Alternatively, we can use a binary-coded decimal (BCD) control that is more convenient to set a frequency with decimal digits but requires a higher number of control lines. Besides setting the frequency, we may also need to control output power and other synthesizer functions that require even more control lines. Furthermore, the interface can also include some extra auxiliary signals such as a lock indicator, trigger, and so forth. Hence, the number of control wires grows with the design complexity. The main advantage of the parallel interface is high communication speed since all control signals are sent simultaneously. While data transmission in parallel is very fast, it usually requires a lot of control lines, bulky connectors on

Parameters and Architectures

17

both sides, and a complex, multiwire connecting cable. Nevertheless, the parallel interface can be a good choice in fast-switching designs such as direct analog synthesizers. 1.4.2

SPI

Serial peripheral interface (SPI) is a synchronous serial data link introduced by Motorola, Inc., that offers full duplex communication, relatively high throughput, and flexibility. The idea behind the SPI is to send controlling bits one by one rather than altogether via a single line. Another line is added to receive some information from the device under control. In order to synchronize the data streams, an auxiliary synchronization signal (such as clock pulses) is needed. Finally, we may want to control not one but several devices via the same wires. This is accomplished using an additional auxiliary line that allows the selection of a particular device. Thus, a multidevice, full-duplex interface can be physically constructed with four signal lines as shown in Figure 1.19. The controlling device is called master, and the device under control is called slave. The control lines are asserted to carry the following functions: SCLK

SCLK

MOSI MISO

MOSI MISO

SS

SS

Master

Slave 1

SCLK MOSI MISO SS Slave 2

SCLK MOSI MISO SS Slave N

Figure 1.19 The SPI interface offers full-duplex communication with multiple devices using four signal lines.

18

Frequency Synthesizers: Concept to Product

• Serial clock (SCLK) is used for synchronization of data streams. • Master output, slave input (MOSI) is used to stream data from the master device to the slave. • Master input, slave output (MISO) is used to stream data from the slave device to the master. • Slave select (SS) is used to select a particular slave device. The communication is initiated by the master that sets the SS signal low for a desired slave device (Figure 1.20). If only a single slave device is used in the system, the SS signal is not necessarily required and in many cases may be set to ground. With multiple slave devices, however, an independent SS signal is required from the master for each slave device; thus, only one slave may be chosen at a time. After selecting a slave, the master starts streaming the data through the MOSI line, simultaneously providing clock pulses on the SCLK line. The SCLK is aligned with MOSI in such a way that the slave device processes the data bit by bit with every clock pulse. Other slave devices that have not been chosen disregard the SCLK and MOSI signals. Besides, they must not drive the common MISO line. Most slave devices have an internal switch that disconnects or puts into a high-impedance state their MISO output when the device is not selected, thus allowing multiple devices to share the same line. To better understand the communication process, let’s consider the slave device input as a shift register, which is essentially a cascade of flip-flops, sharing the same clock as shown in Figure 1.21. A signal on the register’s data input line

SS

SCLK

MOSI

MISO

Figure 1.20

SPI communication timing diagram.

Parameters and Architectures DATA IN

CLOCK

D

19

Q

Q0

Q

Q1

Q

QN

CLK

D

CLK

D

CLK

Figure 1.21

A shift register allows converting a serial data stream into a parallel format.

is transferred to the first flip-flop output on the rising (or falling) edge of the clock signal. With the second clock pulse, this signal is further transferred to the output of the second flip-flop, and so forth. Thus, the series of data bits is shifted down and appears on the corresponding flip-flop outputs. In other words, the register converts an input data stream from serial to parallel format. Similarly, a parallel controlling word on the transmitter side can be converted to a serial format and delivered to the receiving device with a minimal number of physical connections between the devices. Although the concept seems straightforward, a number of SPI modifications exist because of the lack of a strict standard. Each device is described by its own specifications including maximum clock rate, timing characteristics, number of bits and their definitions, and polarity of control signals. Moreover, the MOSI and MISO signals are sometimes combined together into a common data line. The MISO signal is often omitted entirely, which allows programming the slave device but not reading information from it. This SPI modification is called “3-Wire” in contrast to the normal four-wire arrangement and is widely used in PLL synthesizer chips. Overall, the SPI interface is extensively used in both IC and module-level synthesizer designs to allow small packages and highly integrated functionality.

20

1.4.3

Frequency Synthesizers: Concept to Product

I2C

The I2C interface was introduced by Philips Semiconductors in the early 1980s. The name I2C translates into “Inter IC,” since the idea was to allow easy communication between components residing on the same circuit board. Currently I2C is not only used within a single board, but also used to connect separate devices using a cable. Each device connected to the bus is software addressable by a unique address. I2C is a multimaster bus, meaning that multiple masters can initiate data transfer over the shared bus. The main advantage of the I2C interface is its simplicity. Only two bidirectional lines (serial data and serial clock) are required for communication. Disadvantages include relatively low communication speeds and the lack of automatic bus configuration. 1.4.4

RS-232

RS-232 is another serial interface that is widely used in computer serial ports. The standard was introduced by the Electrical Industries Association and evolved from serving electromechanical teletypewriters to modern electronic devices and personal computers. While the standard recommends a 25-pin connector, a three-wire arrangement is often used when the full capabilities of RS-232 are not required. In the latter case, communication is established via the transmit data, receive data, and ground pins. RS-232 can be a good choice if the synthesizer needs to be controlled from a personal computer. Its main disadvantage is relatively low speed. As a result, it is being replaced by much faster USB and Ethernet connections. 1.4.5

USB

Universal serial bus (USB) is today’s most popular way of connecting various devices to a personal computer. Compared to RS-232, USB is faster, smaller, and simpler to use. The current USB version 2.0 provides up to 480 Mbit/second of data transfer and will be replaced with an even faster USB 3.0 rated to 5 Gbit/ second. USB also supports plug-and-play connectivity, meaning that devices are detected by the computer’s operating system and configured automatically as soon as they are attached. USB cables can be up to 30 meters long and can also be used to bias relatively low-power devices. These features make USB a very desirable option in the design of frequency synthesizer modules since it allows instant deployment or simply evaluation of a synthesizer using a personal computer as illustrated in Figure 1.22.

Parameters and Architectures

21

Figure 1.22 A USB interface allows instant deployment and evaluation of frequency synthesizer modules. (Courtesy of Phase Matrix, Inc.)

1.4.6

GPIB

General Purpose Interface Bus (GPIB) is a special interface for test-and-measurement applications. It was originally introduced by Hewlett Packard (now Agilent Technologies, Inc.) as an HPIB bus to control measurement instruments. In 1975, the interface was standardized by the Institute of Electrical and Electronics Engineers (IEEE) under the IEEE-488 standard. The GPIB bus has 24 lines: eight signal lines used for data transfer, three lines for handshake, five lines for bus management, and eight lines for ground returns. It allows the connection of multiple off-the-shelf instruments into a complex automated test system (ATE). 1.4.7

VXI

VXI stands for VME Extensions for Instrumentation and is an interface that was introduced in the mid-1980s as an open system platform for synthetic instrumentation. One of the principles behind synthetic instrumentation in general, and VXI in particular, is to offer a cost-efficient modular approach for building complex test-and-measurement equipment. It enables the emulation of various traditional bench-top instruments employed in automatic test systems using a reconfigurable combination of core hardware modules. A VXI instrument includes a chassis (also called mainframe) that contains several spaces (slots) where individual VXI modules can be placed. The mainframe also contains all necessary DC power supplies and provides communication between individual components and a host controller that is usually an external computer. A VXI module (such as a signal generator shown in Figure 1.23) fits into one or more slots in the chassis and connects through a VXI bus

22

Frequency Synthesizers: Concept to Product

Figure 1.23 A VXI signal generator covers the 0.01- to 20-GHz frequency range. (Courtesy of Phase Matrix, Inc.)

that delivers all necessary control and bias lines. The VXI specifications are governed by the VXI Bus Consortium, which was founded in 1987 by a group of interested companies to define mechanical, electrical, and software features of VXI instrumentation. 1.4.8

PXI

PXI stands for PCI Extensions for Instrumentation and is a further enhancement of the synthetic instrumentation concept (PCI stands for peripheral component interconnect). The PXI standard was introduced by National Instruments Corporation in 1997 and is currently governed by the PXI Systems Alliance (PXISA). The alliance includes more than 50 companies chartered to promote the standard, ensure interoperability, and maintain PXI specifications. Similar to VXI, a typical PXI instrument is built using a PXI chassis and a number of individual modules that fit into PXI slots (as shown in Figure 1.24). However, the size of the chassis and the modules is significantly smaller; a typical PXI module measures approximately 4 by 6 inches in dimensions. Moreover, the host computer can be built as a PXI component and plugged into the chassis.

Parameters and Architectures

23

Figure 1.24 A 3- to 9-GHz local oscillator module available in PXI form. (Courtesy of Phase Matrix, Inc.)

Therefore, a whole instrument or even an ATE system can be completed within a single PXI frame. Another distinct advantage is higher communication speed compared to the VXI environment. It should be noted that the PXI chassis backplane uses essentially the same PCI bus used in personal computers. Thus, the development and operation of PXI systems are not much different from that of standard Windows-based applications. A newer PXI Express standard (released in 2005) further increases the available PXI bandwidth by taking advantage of PCI Express technology. Users benefit from significantly increased bandwidth, ensured backward compatibility, and additional timing and synchronization features. 1.4.9

LXI

LXI stands for LAN Extensions for Instrumentation and is another interface for test-and-measurement applications (LAN stands for local area network). It was introduced in 2004 by Agilent Technologies, Inc., and is currently maintained by the LXI Consortium. The LXI concept offers integration advantages of modular instruments without the constraints of card-cage architectures. It is

24

Frequency Synthesizers: Concept to Product

based on a well-established Ethernet protocol that allows connecting individual instruments into a network. LXI can be used at any level of network complexity ranging from a single component and a controlling computer to complex multiinstrument systems operated remotely through the Internet. The LXI standard defines three classes of instruments. The base class C incorporates a Web browser via an Ethernet port as well as an interchangeable virtual instrument (IVI) driver. Class B brings synchronization capability via the IEEE 1588 precision time protocol and also supports peer-to-peer messaging. The IEEE 1588 protocol synchronizes clocks in multiple devices to ensure proper event time stamping and execution of synchronized events. Finally, Class A adds a fast hardware trigger bus, which offers lower-latency synchronization compared to the Class B. 1.4.10 AXIe

AXIe (Advanced TCA Extensions for Instrumentation and test) is a recent addition to the synthetic instrumentation interfaces that supports both PXI and LXI standards (TCA stands for Telecommunications Computing Architecture). It is governed by the AXIe Consortium that was formed in 2009 by Agilent Technologies, Inc., Aeroflex Corporation, and Test Evolution Corporation. AXIe addresses a wide range of ATE systems, rack-and-stack modular, bench-top, and module plug-ins. It offers higher performance per rack inch, greater scalability, more flexibility, and easy integration with various platforms.

1.5 Main Architectures The RF and microwave industry feels constant pressure to deliver higher performance, higher functionality, smaller size, lower power consumption, and lower-cost synthesizer designs. What parameters are the most important? Is there an “ideal” synthesizer design or architecture? Although all synthesizers exhibit significant differences as a result of specific applications, they share basic fundamental design objectives as depicted in Figure 1.25. The ideal synthesizer should be broadband with fine frequency resolution that allows addressing a larger number of potential applications. Aside from frequency coverage and resolution, phase noise and spurs are critical parameters that impose the ultimate limit in the system’s ability to resolve signals of small amplitude. Another key parameter of the synthesizer that impacts overall system performance is frequency switching speed. The time spent by the synthesizer transitioning between frequencies becomes increasingly valuable since it cannot be used for data processing. Modern synthesizers tend to be faster due to the ongoing increase of the data rates of RF and microwave systems. Another challenge is cost reduction. Although it is considered to be a universal, standard requirement, cost reduction drastically

Parameters and Architectures

25

Speed

Spurs

Noise Cost

Coverage

Figure 1.25

Step Size

Synthesizer design challenges.

narrows the designer’s choice since it determines the types of designs that can be utilized. These requirements—wide frequency coverage, small step size, fast switching speed, adequate spectral purity, and low cost—are the key drivers in the development of frequency synthesizers. Synthesizer characteristics depend heavily on a particular architecture. While reviewing traditional frequency synthesizer schemes, we specifically address the technology trend toward increasing the synthesizer tuning speed, improving the spectral purity as well as reducing its complexity and cost. The main architectures along with their characteristics and trade-offs are described next. 1.5.1

Direct Analog Synthesizers

The direct analog synthesizer is one of the most powerful techniques offering excellent switching speed and phase noise performance [3–7]. As the name suggests, the desired signal is created directly (i.e., without regeneration) by mixing base frequencies followed by switched filters as conceptually shown in Figure 1.26. The base frequencies can be obtained from low-frequency (e.g., crystal, SAW) or high-frequency (e.g., CRO, DRO, metal cavity, and sapphire resonator) oscillators by frequency multiplication, division, and/or mixing. The key advantage of the direct analog technique is extremely fast switching speed, ranging from microseconds to nanoseconds. Since direct analog synthesis assumes no closed loops, switching speed is only limited by propagation delays inserted by the switches and their control circuits as well as filter settling. Another distinct advantage is the ability to generate low phase noise due to usage of components with negligibly low residual noise compared to the base frequency sources. Hence, the direct analog synthesizer phase noise mainly depends on the noise of the available fixed-frequency sources and can potentially be very low. The main disadvantage of the indicated topology is limited frequency coverage and step size. In our example, only 18 output frequencies can be generated (even

26

Frequency Synthesizers: Concept to Product

F1 F2 F3

F4 F5 F6

Figure 1.26

Direct analog synthesizer concept.

by utilizing both mixer sidebands). Naturally, this is not enough for a practical design. The number of output frequencies can be increased by using a higher number of base frequencies and/or mixer stages as depicted in Figure 1.27. However, this rapidly increases the design complexity and overall component count. An effective solution is to use a direct digital synthesizer module (Figure 1.28) to increase the minimum step size requirements for the direct analog portion. The frequency resolution can also be improved by repeatedly mixing and dividing the base frequencies as conceptually shown in Figure 1.29. The synthesizer contains a chain of frequency mixer-divider cells that transform an input frequency fi to fi f f f = f 0 + 1 + 22 +  + i i i N N N N i =0

f OUT = ∑

(1.16)

where fi is a frequency driving the corresponding mixer and N is the division coefficient of the utilized frequency dividers. Using proper fixed frequencies and a sufficient number of individual cells, an arbitrarily small step size can be achieved. In general, the frequency division coefficients can also be arbitrary; however, N = 10 is the most commonly used scenario that leads to

f OUT = f 0 +

f1 f f + 2 +  + ii 10 100 10

(1.17)

Figure 1.27

A1

A2

A3

AX

Direct analog synthesizer with extended frequency coverage.

FN

F3

F2

F1

B1

B2

B3

BY

Parameters and Architectures 27

Figure 1.28

A1

A2

A3

AX

Using a DDS module for better frequency resolution.

DDS

B1

B2

B3

BY

28 Frequency Synthesizers: Concept to Product

Parameters and Architectures

29

÷N

fi

÷N

f1

f OUT

÷N

f0

Figure 1.29

Reducing step size by repeatedly mixing and dividing the base frequencies.

The frequencies fi are usually generated from a common reference F0 by utilizing its harmonics F0, 2F0, 3F0, …, 9F0 as shown in Figure 1.30 and can be presented by f i = Ai F0

(1.18)

where Ai is an integer between 1 and 9 that allows rewriting (1.17) to A ⎞ A A ⎛ f OUT = F0 ⎜ A0 + 1 + 2 +  + ii ⎟ ⎝ 10 100 10 ⎠

(1.19)

The decimal coefficients Ai in this formula simply show what harmonic is chosen. Furthermore, the individual mixer-divider cells can be bypassed as depicted in Figure 1.31, which mathematically corresponds to fi = 0 or Ai = 0. Therefore, the output frequency is conveniently represented in a decimal form by setting corresponding digits. Similarly, the synthesizer can be constructed using different frequency division coefficients to represent its output frequency in a binary or any other desired form, or a combination thereof. Moreover, there are numerous further modifications to this scheme that allow simplifying

30

Frequency Synthesizers: Concept to Product Harmonic Generator

F0 F0

X

2F0 3F0

9F0

Figure 1.30

All necessary frequencies are generated from a common reference.

Figure 1.31

An additional through path simplifies frequency setting.

the synthesizer design or improving its technical characteristics. Every design is unique since it is governed by specific requirements as well as available components and their cost. Thus, the designer’s experience and intuition are probably the most important factors in the synthesizer development equation. A serious problem associated with direct analog synthesis is the large amount of mixing products that have to be filtered. These include the undesired mixer sideband, LO leakage, and intermodulation products. Depending on a particular frequency plan, filtering close-in spurs can be a challenging task. Another serious issue is crosscoupling between individual filter channels and whole cascades. Switch isolation is one of the critical parameters that directly affect the synthesizer’s spurious characteristics. Special attention should also be paid to the synthesizer layout and isolation between its individual blocks. These are nontrivial considerations requiring certain design effort and careful frequency planning. Although a large variety of mixing and filtering organization schemes are possible, they tend to be hardware-intensive if a small frequency step and wide coverage are required. Therefore, while direct analog synthesis offers excellent tuning speed and phase-noise characteristics, its usage is limited to applications where fairly high cost can be tolerated. This includes radars, frequency hopping

Parameters and Architectures

31

and antijam communications, high-throughput ATE, medical imaging systems, and other applications that demand speed. 1.5.2

Direct Digital Synthesizers

In contrast to traditional analog concepts, direct digital synthesizers utilize digital signal processing (DSP) to construct an output signal waveform in the time domain piece by piece from a base (clock) signal [3–5, 8]. Although it may seem complex, the concept is fairly simple. To illustrate this, let’s take a shift register and inject a single, logic-high pulse into its input. With every clock cycle, this logic-high signal will travel through the register outputs from top to bottom. Let’s also connect resistors to these outputs to form voltage dividers as shown in Figure 1.32. The voltage at the divider output changes with every clock pulse in accordance with the chosen resistor values. We can adjust the values in such a manner that the voltage steps approximate a desired signal waveform, for example, a sine wave. The synthesized waveform looks “ugly,” meaning that it has a highly contaminated spectrum in the frequency domain. We can slightly improve it by adding a capacitor that smoothes the edges of the voltage steps; however, the signal is still far from perfect. What can be done to improve our simple digital synthesizer? First, we can increase the length of the shift register and use a higher clock frequency to approximate the sine wave in smaller steps. Second, we can use a specialized digital-to-analog converter (DAC) that generates a much more precise voltage than the simple resistor divider, thus, making the output signal closer to the desired waveform. In this case, we need to add some kind of a decoder between the shift register outputs and the DAC address bus to generate proper voltages. This can be easily accomplished with a memory chip. Furthermore, instead of a smoothing capacitor we can use a high-rejection lowpass filter (LPF) to clean up

DATA IN

D

Q0 Q1 Q3

CLOCK

CLK QN

Figure 1.32 A shift register creates voltage steps that approximate a desired signal waveform.

32

Frequency Synthesizers: Concept to Product

the spectrum of the synthesized signal. Another consideration is how to change the output frequency. Of course, it can be changed by simply varying the input clock frequency. However, this method defeats the whole purpose of frequency synthesis, that is, synthesizing many desired (not fixed) frequencies from an available single fixed-frequency reference. Note that we can change the output frequency by using a smaller (or larger) number of voltage steps within the fixed length defined by the register capacity. In other words, the output frequency can be changed by manipulating the number of register bits or their connections. Keeping all these ideas in mind, we can intuitively come to an improved block diagram depicted in Figure 1.33, which is not too different from what is used in real DDS designs. The direct digital synthesizer consists of four main blocks: a phase accumulator, digital look-up table, DAC, and LPF. The phase accumulator is essentially a more sophisticated version of the shift register used in our example. Instead of injecting a single pulse, it allows entering a digital word (code) called phase increment. At each clock pulse the phase accumulator adds (accumulates) the increment to the previously stored digital value that represents an instantaneous digital phase of the generated signal. This digital phase is continually updated until it reaches the capacity of the accumulator. For an N-bit accumulator and the smallest increment of one least significant bit, it will take 2N clock cycles to fill up the accumulator. Then the accumulator resets and the process starts over again. Hence, the lowest generated frequency is given by

f MIN =

f CLK 2N

(1.20)

that also equals the smallest frequency step. With a larger phase increment W, the phase accumulator obviously fills up faster and the DDS output frequency increases to

fCLK

Phase accumulator

Look-up table

f OUT

DAC

Tuning word Figure 1.33

A direct digital synthesizer block diagram.

LPF

Parameters and Architectures f DDS =

W f CLK 2N

33

(1.21)

Therefore, frequency tuning is accomplished by changing the phase increment word. This word defines the DDS output frequency and can be loaded into the accumulator through either a serial or parallel interface. The tuning process has essentially no settling time delays other than what is inserted by the digital interface. The frequency can be changed in very small steps determined by the length of the phase accumulator. For example, assuming that fCLK is 100 MHz and N = 32, we can calculate fMIN to approximately 0.023 Hz. The length of the phase accumulator can be further increased; thus, millihertz or even microhertz steps are easily achievable. The next step is to convert the digital phase value into a digital representation of the signal waveform. This is accomplished with a look-up table. It uses a read-only memory (ROM) to store a digital code that sets a proper address on the DAC’s bus and, consequently, its output voltage. In general, any desired waveform can be created; however, the sine wave is most commonly used. The waveform construction process completes with a lowpass filter required to remove some unwanted spurious components because of the imperfect approximation of the desired waveform. Practical realization of this concept brings further modifications. For example, the length of the phase accumulator, required to achieve the necessary resolution, can exceed practical limits for ROM and DAC devices. Due to the sine function’s symmetry, only one-fourth of the cycle needs to be stored, thus greatly reducing the required memory capacity. Furthermore, the DAC usually utilizes a smaller number of bits available from the phase accumulator. This may seem confusing. How can a 32-bit phase accumulator work with, let’s say, a 12bit DAC? Interestingly, the DAC may use only one (most significant) bit of the phase accumulator. In this case, it produces a signal of rectangular shape; however, the frequency is still set with the same 32-bit resolution. By adding DAC bits, the sine-wave function is better approximated, thus resulting in a cleaner output. This reduction in DAC resolution is called phase truncation and leads to increased spurious levels. The DDS output contains a number of spurious signals (Figure 1.34) as a result of truncation, amplitude quantization, and DAC nonlinearities. However, the most significant ones are aliased images of the output signal that appear on either side of the clock frequency and its multiples because of the sampling nature of digital signal synthesis. From this point of view, the DDS works as a frequency mixer producing spurs at f SPUR = ±n f CLK ± m f DDS

(1.22)

34

Frequency Synthesizers: Concept to Product DDS Spurs dBm 147 MHz 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 1.34

Start: 10.0000 Hz

Stop: 200.0000 MHz

An output spectrum of a direct digital synthesizer.

where n and m are integers. Similar to mixer intermodulation products, these spurs require careful frequency planning since they can be very close to the output signal and, therefore, cannot be filtered. While spur location in the frequency domain can be easily determined, its amplitude is much less predictable. As a general rule, lower-order spurs are the strongest, although fairly high-order spurs can still be harmful and must be taken into account. Typical DDS spurious levels are −50 to −60 dBc for output signal ranges between a few tens to a few hundreds of megahertz. The DDS also provides reasonably low phase noise levels, even showing an improvement over the phase noise of the clock source itself. From the phase noise point of view, the DDS works as a fractional frequency divider with a very fine, variable, frequency division coefficient. Similar to dividers, the noise improvement is described by 20log(FCLK/FDDS ) function and is limited by the residual noise floor. The DDS is currently available as a tiny, yet highly integrated, surfacemount IC that includes the phase accumulator, look-up table, and DAC in a single chip. It needs only a few external components (LPF and bias circuitry) to build a powerful and versatile module. The most valuable DDS feature is its exceptionally fine frequency resolution and fast switching speed comparable to direct analog schemes. The main disadvantages are limited usable bandwidth and relatively poor spurious performance. While a DDS starts working from nearly DC, its highest frequency is limited within one half of the clock frequency according to the sampling theory. It is theoretically possible to use DDS aliased images above the one half of the clock limit; however, the spurious content is

Parameters and Architectures

35

further degraded. As a rule of thumb, the usable DDS bandwidth is limited to about 40% of the clock signal by practical LPF design considerations. Typical clock speeds for today’s commercial DDS ICs are in the range of a few hundred megahertz to a few gigahertz. The DDS technique is widely used to generate arbitrary waveforms at RF frequencies. However, it rarely works alone at microwave frequencies because of the mentioned bandwidth and spurious limitations. Rather DDS is used as a fine-frequency-resolution block in conjunction with direct analog and indirect architectures. Moreover, it is often accompanied by spur-reduction circuits that control spurious emission. These techniques will be further discussed in Chapter 5. Overall, direct digital synthesizers have a tremendous potential for future growth as a result of exceedingly rapid developments in solid-state devices. The extension of DDS usable bandwidth (together with its spurious content reduction) is the key improvement required by industry. 1.5.3

Indirect Synthesizers

Indirect frequency synthesizers use an additional high-frequency oscillator to generate an output signal that is in a certain relationship with the reference signal. Indirect synthesizers are commonly associated with phase-lock-loop techniques, which are extensively used in RF and microwave systems. A typical single-loop PLL synthesizer includes a tunable VCO that generates a signal in a desired frequency range. This signal is fed back to a phase detector through a frequency divider with a variable frequency division ratio N as depicted in Figure 1.35. The other input of the phase detector is a reference signal equal to a desirable step size. The phase detector compares the signals at both inputs and generates an error voltage, which, following filtering and optional amplification, slews the VCO until it acquires the lock frequency given by f OUT = N f PD

f REF

÷R

f PD

LPF

f OUT /N ÷N

Figure 1.35

A PLL synthesizer block diagram.

(1.23)

VCO

f OUT

36

Frequency Synthesizers: Concept to Product

where fPD is the comparison frequency at the phase detector inputs. The frequency tuning is achieved in discrete frequency steps equal to fPD by changing the division coefficient N. The available reference frequency can be divided down by another divider to reduce the step size. If the division coefficient of the reference divider is R, then the output frequency is set by

f OUT =

N f REF R

(1.24)

Although the phase-lock-loop block diagram appears fairly straightforward, its rigorous analysis is not so simple. The PLL is a nonlinear, closed-loop feedback system and is usually analyzed using the Laplace transform as extensively covered in [9–19]. Fortunately, there are a number of programs that can simulate and even synthesize a PLL circuit with desired characteristics. Hence, engineering effort reduces to formulating design goals that require a clear understanding of PLL limitations and trade-offs. A step-by-step review of the design sequence for a simple single-loop PLL example is given in Chapter 4. How does a PLL behave compared to direct analog and direct digital synthesizers? Since the output signal of the PLL synthesizer is generated at microwave frequencies, all spurs associated with the direct architectures are generally absent. The only source of the spurs in the PLL block diagram shown in Figure 1.35 is the reference signal itself. The reference signal and its harmonics modulate the VCO tuning port and create sidebands both above and below the main signal. The loop filter bandwidth has to be significantly lower than fPD (usually 10 times or more) to keep the reference spurs at a reasonable level. However, the loop bandwidth is inversely proportional to the settling time. Thus, achieving fine frequency resolution, low spurs, and fast switching is an arduous task as it means balancing mutually exclusive terms. Another important consideration and design trade-off is phase noise. The noise outside the PLL filter bandwidth is mainly determined by the VCO’s freerunning noise. The phase noise within the loop filter bandwidth is given by  PLL =  ΣPD + 20 log N

(1.25)

where ΣPD is the cumulative phase noise of the reference signal, reference and feedback dividers, phase detector, LPF, and loop amplifier recalculated to the phase detector input (Figure 1.36). In other words, the phase noise generated by PLL components is degraded by large division ratios required to provide a high-frequency output with a fine resolution. Moreover, programmable dividers are usually not available at high frequencies; thus, an additional, fixed-divisioncoefficient divider (called a prescaler) is required. In this case, the total division

Parameters and Architectures

37 VCO

REF

÷R

VCO

LPF

OUT

÷N

+ 20 log N ΣPD

Figure 1.36

PLL noise sources.

ratio will increase by the prescaler division coefficient resulting in further phase noise degradation. At high frequency offsets, the VCO’s free-running noise can be (and normally is) better than the multiplied PLL noise. The optimal phase noise profile is achieved by choosing the loop bandwidth at the cross point of the multiplied PLL noise and VCO free running noise curves as depicted in Figure 1.37. Clearly, by utilizing a low-noise VCO and narrower loop bandwidth, it is possible to mask some excessive PLL noise at high frequency offsets. However,  VCO

OUT

PLL

20 log N  ΣPD

Frequency offset

Figure 1.37

PLL synthesizer output phase noise.

38

Frequency Synthesizers: Concept to Product

this results in slower switching speed. Alternatively, a good PLL design can suppress VCO noise at higher frequency offsets and also provide faster tuning. Overall, the major advantages of the PLL schemes are reduced levels of spurious signals resulting from the lowpass filter action of the loop and much lower level of complexity compared to the direct analog architectures. In fact, all key PLL components can be integrated into a single chip that leads to low-cost, miniature designs. The main disadvantages are slower tuning, limited step size, and considerably higher phase noise. The PLL synthesizer’s characteristics can be improved by a number of techniques (such as fractional-N or frequency conversion within a feedback path), as will be further discussed in Chapter 5.

References [1] Stone, R. R., Jr., “Frequency Synthesizers,” Proc. 21st Annual Symposium on Frequency Control, April 1967, pp. 294–307. [2] Kroupa, V. F., Frequency Synthesis: Theory, Design and Applications, New York: John Wiley & Sons, 1973. [3] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [4] Reinhardt, V., et al., “A Short Survey of Frequency Synthesizer Techniques,” Proc. 40th Annual Symposium on Frequency Control, May 1986, pp. 355–365. [5] Galani, Z., and R. A. Campbell, “An Overview of Frequency Synthesizers for Radars,” IEEE Transactions on Microwave Theory and Techniques, Vol. 39, No. 5, May 1991, pp. 782–790. [6] Chenakin, A., “Frequency Synthesis: Current Solutions and New Trends,” Microwave Journal, May 2007, pp. 256–266. [7] Karlquist, R. K., “A 3 to 30 MHz High-Resolution Synthesizer Consisting of a DDS, Divide-and-Mix Modules, and a M/N Synthesizer,” IEEE Int. Frequency Control Symposium Proc., June 1996, pp. 928–933. [8] Kroupa V. F., (ed.), Direct Digital Frequency Synthesizers, New York: IEEE Press, 1999. [9] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [10] Egan, W. F., Phase-Lock Basics, 2nd ed., New York: John Wiley & Sons, 2007. [11] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [12] Best, R. E., Phase-Locked Loops: Theory, Design, and Applications, New York: McGraw-Hill, 1984. [13] Rohde U. L., Digital PLL Frequency Synthesizers: Theory and Design, Upper Saddle River, NJ: Prentice-Hall, 1983. [14] Rohde, U. L., Microwave and Wireless Synthesizers: Theory and Design, New York: John Wiley & Sons, 1997.

Parameters and Architectures

39

[15] Klapper, J., and J. T. Frankle, Phase-Locked and Frequency-Feedback Systems, New York: Academic Press, 1972. [16] Crawford, J. A., Frequency Synthesizer Design Handbook, Norwood, MA: Artech House, 1994. [17] Crawford, J. A., Advanced Phase-Lock Techniques, Norwood, MA: Artech House, 2008. [18] Kroupa, V. F., Phase Lock Loops and Frequency Synthesis, New York: John Wiley & Sons, 2003. [19] Goldman, S. J., Phase-Locked Loop Engineering Handbook for Integrated Circuits, Norwood, MA: Artech House, 2007.

2 Building Blocks As discussed in Chapter 1, the frequency synthesizer can be thought of as a black box containing the necessary components to translate an input reference signal to a number of output frequencies. The synthesizer’s performance depends heavily on characteristics of individual components used in the design. This chapter continues with a review of key building blocks from the perspective of their practical use in microwave frequency synthesizers. The main focus is on how undesired signals (spurs, phase noise) are generated and then propagate through synthesizer components. Oscillators, frequency multipliers, dividers, mixers, phase detectors, and complex integrated circuits will be discussed.

2.1 Oscillators An oscillator is an electronic device that generates a repetitive electronic signal such as a sine wave. Oscillators are used extensively in many electronic instruments; hence, their parameters and design techniques are well covered in many sources, including [1–50]. Frequency coverage, tuning sensitivity, frequency stability, and output power are important characteristics for a synthesizer designer. However, oscillator phase noise is probably the most important figure of merit since it defines the ultimate performance of a frequency synthesizer. This section briefly summarizes the research and development effort in the area of low-noise signal generation. It discusses a general noise generation mechanism, the influence of individual elements on phase noise behavior as well as various noisereduction techniques.

41

42

2.1.1

Frequency Synthesizers: Concept to Product

Phase Noise in Microwave Oscillators

An oscillator can be looked at as either a feedback or negative resistance circuit. A typical feedback microwave oscillator, shown in Figure 2.1, consists of a passive frequency-determining resonant element and an active device required to compensate for the resonator loss in order to start oscillations. The oscillations are initiated due to small, noisy signal fluctuations occurring in the oscillator components. The active device’s small-signal gain has to be greater than the resonator loss to result in a rapid increase of the output signal. Naturally, some kind of limiting mechanism (such as gain compression) is required to stabilize the output power at a certain level. The gain compression usually occurs in the active device itself because of its natural nonlinear behavior. Thus, at steady state, the gain of the active device becomes equal to the overall loss in the resonator-feedback path that stabilizes the output signal amplitude. The oscillation frequency is determined by the resonator frequency selectivity and phase relationship in the oscillator-feedback path. Therefore, two essential requirements are necessary to realize an oscillator: • Noisy signal fluctuations in oscillator components are required to initiate oscillations. • A limiting, nonlinear mechanism is required to achieve steady-state oscillations. Unfortunately, these vital features of the microwave oscillator eventually result in output spectrum contamination either directly (due to the active device RF noise or resonant-frequency fluctuations) or indirectly (due to the upconversion of the active device’s low-frequency noise in its nonlinearities). In general, oscillator phase noise can be approximated by

Resonator Q

f0 , P G, F

Active device Figure 2.1

Feedback oscillator block diagram.

Building Blocks =∑ n

an a a a = a 0 + 1 + 22 +  + nn fn f f f

43

(2.1)

where f is the offset frequency from the carrier and an are coefficients that define the noise shape for a particular oscillator circuit. In practice, higher-order terms are ignored since they appear at very low frequency offsets (below 1 Hz) and the oscillator noise behavior is usually represented as

⎧⎪GFkT  ≈ 10 log ⎨ ⎪⎩ 2P

⎡⎛ f 0 ⎞ 2 f c ⎛ f 0 ⎞ 2 1 ⎤ ⎫⎪ f × 3 +⎜ × 2 + c + 1⎥ ⎬ ⎢⎜ ⎟ ⎟ f f f ⎝ 2Q ⎠ ⎢⎣⎝ 2Q ⎠ ⎥⎦ ⎪⎭

(2.2)

where G = active device gain F = active device noise factor k = Boltzmann’s constant T = absolute temperature P = RF power applied to the resonator Q = resonator loaded Q-factor f0 = oscillation frequency fc = active device flicker-corner frequency f = offset frequency This expression is a well-known modification of Leeson’s equation [3–6] that depicts the oscillator phase noise behavior in the offset frequency domain. Although the formula defines four basic frequency offset regions, in microwave oscillators the 1/f term is further ignored because of the 1/f 2 noise domination. This leads to the “classical” microwave oscillator phase noise profile shown in Figure 2.2. For offset frequencies higher than the resonator half bandwidth f0/2Q, phase noise is mainly determined by the available RF power level and the active device thermal noise. This region shows a nearly flat response called noise floor. For frequencies between the half bandwidth and flicker-corner frequency fc, phase noise increases at a 20 dB per decade rate. In the last region, where the flicker noise dominates, the phase noise increases at 30 dB per decade. Thus, two important oscillator parameters, namely the resonator half bandwidth f0/2Q and flicker-corner frequency fc, define the shape of the phase noise curve while its magnitude is mainly determined by the GFkT/2P term.

44

Frequency Synthesizers: Concept to Product Phase noise fc , f 0 / 2Q 30 dB/decade

20 dB/decade Noise floor

fc

Figure 2.2

f 0 / 2Q

Frequency offset

Phase noise behavior of a microwave oscillator.

The graph in Figure 2.2 gives a simplified yet very helpful visualization of the phase noise behavior as well as some intuitive ideas on how to reduce its appearance in the oscillator output spectrum. The phase noise can be controlled by reducing the flicker-corner frequency fc and/or the resonator half bandwidth f0/2Q as shown. The flicker-corner frequency is mainly determined by a particular active device and its operating regime while the half bandwidth is set by the frequency resonator and its coupling scheme. Clearly, utilizing low-flicker-noise devices (such as silicon bipolar transistors) and applying a high-Q frequency resonator technology are effective and commonly used ways of cleaning up the oscillator output spectrum. Alternatively, the entire noise curve can be shifted down, as shown in Figure 2.3, by increasing the oscillator signal-to-thermal noise ratio. This can be achieved practically by maintaining a higher power level in front of the resonator and/or reducing the active device noise factor while setting the active device gain to its optimum value (determined by the resonator coupling as will be discussed later). Thus, extracting a higher power from the active device provides a considerable effect—the entire phase noise curve is shifted down, decibel for decibel. However, the output power increase should be implemented very carefully since severe phase noise degradation can occur because of the active device noise elevation at compression. It is preferable to operate the active device in a small-signal, “linear” regime in order to keep its noise characteristics unaffected. This may seem confusing since in order to get steady-state oscillations, a limiting mechanism is required (i.e., something has to be nonlinear). However, “something” does not necessarily mean the active device itself. The limiting mechanism can be effectively spread through oscillator components or even moved from the active device to a less critical (from the noise generation point of view) component. In a more general sense, the main idea here is to reduce the influence of oscillator

Building Blocks

45

Phase noise GFkT 2P

30 dB/decade

20 dB/decade Noise Floor

fc

Figure 2.3

f 0 /2Q

Frequency offset

Another method for phase noise reduction.

nonlinearities on the phase noise generation process that can be achieved with a variety of linearization and noise suppression techniques. In summary, the key principles in designing low-noise microwave oscillators are as follows: • Reducing the oscillator half bandwidth frequency by utilizing a high-Q resonator and optimum coupling scheme; • Reducing the flicker-corner frequency by choosing an appropriate active device and its operating regime; • Increasing the oscillator signal-to-thermal noise ratio by choosing an active device with a low noise figure and maintaining high signal level in front of the resonator; • Preventing the active device noise elevation by optimizing the oscillationlimiting mechanism as well as applying active device linearization and noise-reduction techniques. 2.1.2

Resonators

The frequency resonator element has considerable impact on oscillator phase noise and tuning characteristics. Modern microwave oscillators utilize various resonator technologies, based on electromagnetic, electro-acoustic, and electrooptical principles. 2.1.2.1 Electromagnetic Fixed-Frequency Resonators

An air-filled metal cavity is a typical example of a high-Q electromagnetic resonator, which confines the electromagnetic energy inside a shielded volume. The cavity is usually a cylinder made from a temperature-stable material such as Invar

46

Frequency Synthesizers: Concept to Product

while its internal walls are plated and thoroughly polished to minimize surface resistivity. Since dielectric dissipation and radiation losses are eliminated, the achievable Q is mainly limited by the loss in the metal walls and can be fairly high (10,000–70,000). The all-metal structure also permits increasing signal power levels to maximize the oscillator signal-to-thermal noise ratio. Excellent phase noise of −165 dBc/Hz at 10-kHz offset and the 10-GHz output has been achieved with a 33-dBm signal injected into a metal cavity and applying an advanced interferometer-based noise-suppression technique [7]. In spite of the high achievable Q-factors and excellent power handling capabilities, the impractically large size of cavity resonators restricts their integration with other surfacemount components commonly used in frequency synthesizer designs. Smaller sizes are realizable using dielectric resonators. A dielectric resonator is a cylindrically shaped piece of material (often called a “puck”) that resonates at certain frequencies determined by its geometry. The resonator can be conveniently mounted on an alumina substrate or printed circuit board and coupled to microstrip lines as illustrated in Figure 2.4. Hence, integration with other components is easily achieved. The practical frequency range for dielectric resonators is between 1 and 40 GHz, while their Q-factor typically reduces linearly with increasing frequency. A Q of 10,000 at 4 GHz is an average representative of commonly used materials [8–11]. The phase noise of −110 to −120 dBc/Hz at 100-kHz offset output is a typical number for X-band commercial dielectric resonator oscillators (DROs). Ceramic resonators offer a simple, low-cost solution for frequencies between a few hundred megahertz and a few gigahertz. The resonator is a silverplated length of temperature-stable ceramic, shorted on one end; achievable Qfactors are comparable to dielectric resonator pucks. Their low cost and easy implementation make them an excellent candidate for ceramic resonator oscillators (CROs), which are commercially available up to approximately 10 GHz

Transmission lines Dielectric resonator

Figure 2.4

Dielectric resonator oscillator.

Building Blocks

47

(such as shown in Figure 2.5). CROs exhibit low-noise characteristics (Figure 2.6), while their tuning is limited to a few percents. Much higher Q-factors are possible using sapphire resonators. The resonator is a cylinder made from a monocrystalline Al2O3 material known as sapphire. This material features extremely low dielectric loss at microwave frequencies. The typical Q-factor of a sapphire resonator used in the fundamental TE01δ mode is 40,000 to 50,000. The higher-order, so-called “whispering-gallery” modes are utilized to isolate the electromagnetic energy inside the resonator and, therefore, reduce the influence of the external elements. Q-factors greater than 200,000 at room temperature have been reported [12–16]. 2.1.2.2 Electromagnetic Tunable Resonators

The main disadvantage of the resonators described above is their limited tuning range, since any resonator detuning adversely affects its Q characteristics. Even frequency locking can be a certain challenge for high-Q resonators such as sapphire. Yttrium iron garnet (YIG) resonators are utilized when wideband tuning and high Q-factors are simultaneously required [17–23]. The YIG resonator consists of a small (8–20 mils in diameter) YIG sphere placed between the two poles of a cylindrically reentrant electromagnet and coupled with small wire loops as depicted in Figure 2.7. Frequency tuning is possible since the resonant frequency of the spherical YIG resonator in uniform magnetic field is a function of the magnetic field strength. The basic relationship between the resonant frequency f and magnetic field strength H is given by f = γH where

Figure 2.5 CRO module built on a 0.5 by 0.5 inch PCB and shielded with a metal can. (Courtesy of Z-Communications, Inc.)

48

Figure 2.6

Frequency Synthesizers: Concept to Product

CRO phase noise at 3.25 GHz. (Courtesy of Z-Communications, Inc.)

Electromagnet

Tuning coil YIG sphere

Figure 2.7

YIG resonator construction.

γ = 2.8 MHz/Oe is a physical constant called a gyromagnetic ratio. Thus, the resonant frequency is in direct proportion to the magnetic field, which can be controlled by changing the DC current injected into the electromagnet tuning coil. YIG resonators offer a relatively high Q (greater than 4,000 at 10 GHz),

Building Blocks

49

which linearly increases with frequency. A practical usable frequency range of pure YIG resonators lies between 2 and 50 GHz, similar to the frequency range of dielectric resonators. Lower operating frequencies (a few hundred megahertz) are obtainable by adding special dopes (such as gadolinium), which unfortunately degrades Q-characteristics. The highest boundary is mainly limited by magnet saturation and impractically high power consumption that is caused by the very high current required to generate the necessary magnetic field strength. The unique features of the YIG material have found application in YIGtuned oscillators (YTOs) featuring excellent phase noise performance. Active devices in the negative resistance configuration (Figure 2.8) are used to achieve wideband tuning. Using a silicon bipolar transistor and a composite feedback architecture (double coupling the YIG sphere in a series feedback for higher frequencies and in a parallel feedback for lower frequencies), a tuning range of 2 to 22 GHz has been achieved with a phase noise of better than −120 dBc/Hz at 100-kHz offset at 10 GHz [22]. YIG-tuned oscillators also offer very linear and repeatable tuning characteristics that simplify a synthesizer’s coarse tuning in multiloop PLL designs. The disadvantages are low tuning speed, high power consumption, large footprint, and relatively high cost. DC power consumption can be reduced by using a permanent magnet to boost magnetic field strength. However, permanent magnet bias leads to narrower tuning bandwidths. Besides this, the relatively slow tuning speed remains one of the major drawbacks that restricts the application of YIG-tuned oscillators in fast-switching synthesizer designs. Smaller size and lower-cost characteristics are possible with varactor-tuned oscillators (usually referred to as voltage-controlled oscillators or VCOs) based on either lumped LC or distributed microstrip resonators [24, 25]. Frequency tuning is achieved using varactor diodes, since their capacitance depends on the applied tuning voltage. Unfortunately, the Q-factors of these resonators are not high; typical values are between a few tens to a few hundreds, depending on the particular technology and tuning range. Thus, the free-running noise of the VCO is significantly higher in comparison with YIG-oscillator numbers. Nevertheless, the VCO is an attractive choice in designing a multiloop PLL synthesizer since its noise can be suppressed by utilizing a low-noise, fixed-frequency Active device YIG resonator

Figure 2.8

YIG-tuned oscillator utilizes a negative resistance concept.

50

Frequency Synthesizers: Concept to Product

reference oscillator as well as a very wide loop bandwidth. VCOs are available in different forms operating from low RF to millimeter waves (Figure 2.9). 2.1.2.3 Electro-Acoustic Resonators

A generic electro-acoustic device combines electrical-to-acoustic and backward acoustic-to-electrical signal transducers with a high-Q acoustic resonator as depicted in Figure 2.10. A “classical” representation is the crystal resonator that utilizes the piezoelectric effect in quartz material [26]. Quartz features exceptional stability and has been the industry’s workhorse for embeddable, precise time base for over half a century. It has also demonstrated exceptionally high Q-factors, ranging from 30,000 to more than 1 million and has been widely used in lownoise, time-stable oscillators from low RF to a few hundred megahertz. Temperature is a key parameter that affects the frequency stability and phase noise characteristics of a crystal oscillator. Various techniques are used to control temperature stability. A temperature-compensated crystal oscillator (TCXO) utilizes additional control circuitry to sense the temperature and generate a voltage that corrects oscillator output frequency drift. An oven-controlled crystal oscillator (OCXO), on the other hand, stabilizes the ambient temperature surrounding the crystal. The resonator as well as other oscillator components are confined in a thermally isolated package (called an oven) such as shown in Figure 2.11. The design also includes a temperature sensor and a thermal heater that form a feedback system to control the temperature inside the oven. When an OCXO is turned on, it goes through a warm-up period while the temperature inside the oven stabilizes and remains at a constant level. OCXOs deliver superior frequency stability and phase noise characteristics compared to other crystal oscillator types (as demonstrated in Figure 2.12) and are, therefore, extensively used in high-performance frequency synthesizer designs.

Figure 2.9

Voltage-controlled oscillator in TO-8 package. (Courtesy of Phase Matrix, Inc.)

Building Blocks

51

At higher frequencies surface acoustic wave (SAW) resonators are most commonly used. The SAW resonator structure is deposited onto a low-acousticloss substrate (such as lithium niobate) and exhibits high-Q characteristics at RF and microwave frequencies up to 2 GHz [27, 28]. The film bulk acoustic resonator (FBAR) is another representative of the electro-acoustic resonator family [29]. The resonator is a three-layer structure with the top and bottom electrodes of molybdenum sandwiching a middle layer of aluminum nitride. FBARs are used in the frequency range of a few hundred megahertz to approximately 5 GHz with a typical Q-factor of greater than 500 at 2 GHz. 2.1.2.4 Electro-Optical Resonators

Electro-optical principles are utilized in an optoelectronic oscillator (OEO), which is capable of generating a signal at microwave frequencies [30, 31]. The OEO generic architecture is essentially a transposed gain oscillator that utilizes laser light energy to enable an electro-optical signal conversion. The laser radiation propagates through a modulator and an optical energy storage element (that is a resonator) then is converted to electrical energy with a photodetector, as depicted in Figure 2.13. The electrical signal at the output of the photodetector is amplified, filtered, and fed back to the modulator to close the oscillator feed-

Electrical-to-acoustic signal transducer

Acoustic resonator

Acoustic-to-electrical signal transducer

Figure 2.10

Electro-acoustic resonator concept.

Figure 2.11

Oven-controlled crystal oscillator. (Courtesy of Bliley Technologies, Inc.)

52

Frequency Synthesizers: Concept to Product

Figure 2.12 An OCXO delivers superior phase noise characteristics. (Courtesy of Bliley Technologies, Inc.)

Laser

Electro-optical modulator

Optical resonator

Photo detector

RF output

Figure 2.13

Optoelectronic oscillator block diagram.

back loop. The optical resonator is constructed using a long fiber delay line; the Q-factor is proportional to the ratio of the delay time and line loss. Since fiber lines exhibit fairly low insertion loss (less than a decibel per kilometer), high-Q resonators can be constructed. Further improvements and miniaturization are possible with a microspherical optical resonator that utilizes multiple reflections inside a fused silica sphere [32].

Building Blocks 2.1.3

53

Coupling

Resonator coupling is another important consideration because any coupling mechanism reduces the residual (unloaded) resonator Q-factor to the actual (loaded) value used in phase noise calculations. However, it is a common design mistake to try to achieve high loaded Q values by using a very loosely coupled resonator. Resonator loss is a function of its unloaded and loaded Q-factors and is given by ⎛ ⎜ 1 Loss (dB) = 10 log ⎜ ⎜ 1 − QL ⎜⎝ Q U

⎞ ⎟ ⎟ ⎟ ⎟⎠

2

(2.3)

where QU and QL are the resonator unloaded and loaded Q-factors, respectively. Undercoupling results in increased overall resonator loss requiring an extra amount of gain to compensate it, which, in turn, results in thermal noise increase. Since these two factors work in opposite ways, intuitively, there should be a certain optimum determined by a specific oscillator topology. It can easily be shown [33, 34] that for the simple feedback oscillator discussed previously, the phase noise minimum is achieved when the resonator loaded Q-factor is set to one half of its unloaded value (i.e., QL = 0.5QU ). This corresponds to a 6-dB resonator loss. Other oscillator schemes may require different optimum coupling values depending on specific design goals and trade-offs. Moreover, the coupling structure does not necessarily have to be symmetrical, that is, the two resonator ports may have different coupling coefficients as required by a particular oscillator scheme [35, 36]. For example, a circulator-based oscillator, shown conceptually in Figure 2.14, utilizes a feedback signal reflected from one resonator port, while the second port is used to extract the output frequency. The output frequency can also be extracted from the amplifier output, thus eliminating the need for the second resonator port. No circulator is required in negative resistance designs, which utilize single-port resonators and are commonly used for wideband oscillators such as YIG-tuned oscillators. 2.1.4

Active Devices

Bipolar and field-effect transistors are the most common devices used in microwave oscillators. Transistor gain, maximum oscillation frequency, output power, and noise characteristics are the main parameters affecting oscillator design. These parameters are heavily dependent on a particular solid-state device technology; the most common ones are silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe).

54

Frequency Synthesizers: Concept to Product

Output 2

Output 1

Figure 2.14 port.

A circulator-based oscillator utilizes a feedback signal reflected from a resonator

Silicon-bipolar-junction transistors have dominated the oscillator field up to approximately 20 GHz because of their excellent 1/f noise characteristics. GaAs FET and HEMT devices, on the other hand, have been demonstrated to oscillate at frequencies beyond 100 GHz as fundamental oscillators. Unfortunately, their flicker-corner frequency is also higher compared to the silicon bipolar transistors, which restricts their application in low-noise oscillator designs. In practice, it is more common to achieve millimeter-wave frequencies by using a lower frequency silicon bipolar transistor oscillator, followed by a frequency multiplier and bandpass filter. This arrangement usually results in better phase noise performance, compared to fundamental, GaAs-based oscillators. SiGe is another very promising technology that combines excellent noise characteristics with high oscillation frequencies. 2.1.5

Noise Reduction Techniques

Active device linearization is one of the techniques that help to prevent noise elevation [37–40]. The simplest solution is to avoid or, more precisely, reduce active device compression by implementing another less noisy limiting mechanism. Various techniques (or their combination) can be used, as shown in Figure 2.15. For example, a signal limiter can be placed either before or after the active device, keeping its output well below the compression level. The same function can be achieved with an automatic-level-control (ALC) feedback circuit that detects the active device output and adjusts the overall loop gain with an RF attenuator. The RF signal sampled from the amplifier output can be fed back to, and subtracted from, the RF input signal directly without DC detection as depicted in Figure 2.16. This is essentially a generic feedback concept, which can be implemented in a variety of forms ranging from transistor-level local feedback circuits to more complex system-level solutions. Active device characteristics can also be linearized using a feedforward amplifier approach [41]. The feedforward amplifier employs two cancellation

Building Blocks

Input limiter

Attenuator

55

Output limiter

ALC Figure 2.15

Implementation of limiting mechanism.

−

Figure 2.16

RF feedback concept.

circuits to generate an error signal and subtract it from the main amplifier output as shown in Figure 2.17. By properly balancing amplitude and phase characteristics, it is possible to remove undesired artifact products created by the main amplifier. This approach is widely used to suppress amplifier intermodulation distortion products; moreover, it can be effectively utilized for noise reduction as well. The level of suppression is mainly limited by amplitude and phase balance; typical values are in the 15- to 30-dB range and can be further improved by applying a more sophisticated balance adjustment. Another interesting method (shown conceptually in Figure 2.18) is based on the use of a transposed-gain amplifier [34, 42]. Low-flicker-noise silicon bipolar transistors can be utilized to generate output frequencies greater than their own maximum oscillation frequency. The auxiliary LO noise can be suppressed (to a certain degree, of course) by adjusting the phase delay between the mixer LO ports.

56

Frequency Synthesizers: Concept to Product

Main amplifier

Delay

−

Delay

− Auxiliary amplifier

Figure 2.17

Feedforward concept.

LO

Figure 2.18

Delay

Transposed gain oscillator.

Frequency locking is another powerful approach in constructing low-noise oscillators [43–46]. This approach utilizes a phase detector (usually a balanced mixer) to compare the two signals coming from a VCO directly and through a high-Q resonator used as an external frequency discriminator (Figure 2.19). These two signals are adjusted to be in quadrature to increase the phase detector sensitivity. The phase detector produces a voltage that steers the VCO to suppress its phase noise fluctuations. The noise suppression is limited by the discriminator sensitivity, which heavily depends on the resonator Q-factor. VCO phase noise can be drastically reduced by utilizing a high-Q external resonator, such as a metal cavity or sapphire. However, this circuit exhibits an

Building Blocks

57

VCO

Figure 2.19

Frequency-locked oscillator.

initial frequency-lock acquisition problem caused by the high-Q resonator characteristics. The problem can be elegantly solved by utilizing a common high-Q resonator, which is simultaneously used as both an oscillator resonant element and frequency discriminator (Figure 2.20). A phase noise of −140 dBc/Hz at a 100-kHz offset from a 10-GHz carrier has been achieved using a conventional dielectric resonator with a loaded Q of 1,500 and a FET-based transistor amplifier [46]. The discriminator sensitivity and consequently the phase noise performance can be further improved by putting an additional low-noise amplifier (LNA) in front of the phase detector. However, the incident power coming to the LNA should be kept very low to minimize its flicker noise contribution. This can be achieved by utilizing a near-critical coupling resonator configuration [47] or interferometric signal processing [48, 49]. A phase noise of −150 dBc/Hz at 1-kHz offset and 9-GHz output has been achieved using a whispering-gallerymode sapphire resonator and advanced interferometer-based noise suppression circuit [49]. A pound discriminator is another technique that reduces phase detector DC errors by modulating the VCO with an auxiliary RF generator [50].

ϕ

Figure 2.20

Frequency-locked oscillator with a built-in discriminator.

58

Frequency Synthesizers: Concept to Product

2.2 Frequency Multipliers A frequency multiplier is an electronic device that produces harmonics of the input signal. Frequency multiplication is achieved by introducing a component with nonlinear behavior (for example, a diode or transistor) that distorts a signal waveform and, therefore, generates harmonics [51–54]. Multipliers are used extensively in frequency synthesizers to multiply reference signals or to extend operating frequency range. 2.2.1

Frequency Multiplication

A frequency multiplier is characterized by the output harmonic content versus input frequency and power level. However, the main concern of a synthesizer designer is what happens to phase noise and spurs after passing through a multiplier. To answer this question, let’s examine a nonlinear component that produces an output signal described by VOUT = ∑ knV INn = k1V IN + k2V IN2 + k3V IN3 +  + knV INn n

(2.4)

In general, an infinite number of harmonics are generated. However, for simplicity, let’s consider a frequency doubler described by the k2V IN2 term only. In other words, such a hypothetical component squares the incoming signal. Let’s assume that the incoming signal is a phase-modulated sine wave expressed as V = A0 sin(ω0t + Am sin ωmt). Using the elementary identity sin2 α = (1 − cos 2α)/2 the output signal can be rewritten as

VOUT =

k2 A02 ⎡1 − cos ( 2 ω0t + 2 Am sin ωmt )⎤⎦ 2 ⎣

(2.5)

Ignoring the DC-related term (it can be simply removed with an AC blocking capacitor), we can state that the doubler output contains a signal at 2ω0 modulated at the same ωm rate. Hence, we should still expect two spurious sidebands, equally spaced from the doubled output, as illustrated in Figure 2.21. Note, that the amplitude of the modulating signal in (2.5) doubles, which corresponds to a 6-dB change in power (as the amplitude is given in terms of voltage). Since phase noise has essentially the same phase modulation nature, we should expect the same 6-dB degradation. Our model is very basic, yet quite helpful in understanding the multiplication process. Using more terms from (2.4) brings higher-order harmonics into consideration; however, the idea remains the same. A more rigorous analysis [53] leads to a general conclusion that a times-N multiplier introduces 20logN degradation for both PM spurs and phase noise.

Building Blocks

59

So far, we have considered a purely phase-modulated signal only. However, the input signal can present amplitude variations as well. As discussed earlier, amplitude modulation (AM) effects are often ignored since the AM is greatly attenuated if signal limiting takes place. In the latter case, however, AM-to-PM conversion can affect phase noise performance. The AM noise is first converted into PM noise and then enhanced by 20logN. Moreover, a solid-state device (a diode or transistor) used in a multiplier design also introduces its internal noise that can be upconverted on device nonlinearities and result in further phase noise increase. Thus, the designer’s primary concern is to avoid any extra phase noise degradation above the “natural” 20logN. From this point of view, passive, Schottky-diode-based solutions are generally preferred. 2.2.2

Single-Diode Multipliers

The easiest way to generate harmonics is to use diode nonlinearity to distort a sine-wave signal as shown in Figure 2.22. This circuit is called a half-wave rectifier because it cuts a half of the incoming sine wave. Its design is quite simple and assumes matching the diode impedance with both source and load. The output matching circuit is usually tuned for resonance to accentuate a desired harmonic. Typical conversion loss numbers for a single-diode doubler are in the order of 10 dB. The conversion loss varies as a function of the input power because of

6 dB f

Figure 2.21

2f

Frequency doubling results in 6-dB PM spur degradation.

Matching circuit

Matching circuit & ground return

Figure 2.22 A single-diode half-wave rectifier distorts the incoming sine wave and generates harmonics.

60

Frequency Synthesizers: Concept to Product

the change in diode impedance. The main disadvantages of this scheme are low efficiency and the lack of undesired product suppression. Obviously, the first, fundamental harmonic is the largest since the half-wave pulses still circulate at the same frequency. Although higher-order harmonics are present, the output power declines rapidly with the harmonic number. Therefore, amplification and extensive filtering are required. 2.2.3

Balanced Diode Multipliers

The performance of a single-diode frequency multiplier can be improved by using a balanced configuration. The idea is to suppress the fundamental and other undesired products by out-of-phase cancellation at the output load while combining a desired harmonic in-phase. This can be achieved by adding a signal transformer and another diode to the half-wave rectifier circuit as depicted in Figure. 2.23. The diodes are fed in antiphase; hence, each diode passes an opposite half of the incoming sine wave. Thus, current circulates through the load two times per cycle. The output waveform looks somewhat like a sine wave with twice the frequency of the signal applied to the input. Therefore, we should expect a strong second harmonic with no fundamental signal. Indeed, an ideal scheme outputs even harmonics only while all odd products are suppressed [51]. Although, this circuit works nicely as a doubler, it can also be used as a quadrupler or a higher even-order multiplier. Good odd-harmonic rejection requires that the diodes be balanced or, in other words, respond equally to the positive and negative portions of the input sine wave. A diode pair integrated on the same chip is preferable since the diode characteristics are well matched. In practice, however, no perfect balance can be achieved. Typical fundamental and thirdorder harmonic levels are in the range of −20 to −40 dBc with respect to the output signal as illustrated in Figure 2.24.

Figure 2.23

A balanced doubler is constructed by adding a transformer and another diode.

Building Blocks

Figure 2.24

61

Balanced doubler output spectrum.

Note that the diodes can be connected in antiphase by placing the transformer at the output as shown in Figure 2.25. The circuit behavior is nearly identical. Similar output waveforms can also be obtained with a double-balanced bridge multiplier (Figure 2.26) that requires no ground return, thus eliminating the transformer center point. This configuration is suitable for very broadband operation since it isolates the input and output ports making each easier to match. At microwave frequencies, baluns are used in the place of transformers. The word balun is an acronym for balanced-to-unbalanced converter that converts a single-ended signal to a balanced (differential) one. Baluns can be physically constructed from pieces of transmission lines, which can be conveniently formed on a printed circuit board. The design techniques are well described in [52]. Such balanced multipliers are readily available as low-cost, surface-mount components from Mini-Circuits, Hittite Microwave Corporation, and other manufacturers. Thus, the designer’s effort is reduced to selecting a part with the appropriate characteristics.

Figure 2.25

Another balanced multiplier configuration.

62

2.2.4

Frequency Synthesizers: Concept to Product

Antiparallel Diode Multiplier

The balanced solutions discussed above work nicely to generate even-order harmonics, but what if we need to create an odd-harmonic multiplier, let’s say, a tripler? A simple solution is to use an antiparallel diode pair as shown in Figure 2.27. This circuit can be thought of as a limiter that cuts sine wave edges from both sides, making it closer to a square wave. Fourier analysis reveals that such a signal contains only odd harmonics while even harmonics are suppressed. The level of suppression depends on how the diode characteristics are matched. Obviously, a diode pair integrated on the same chip is a preferable choice. Such a part is readily available in surface-mount packages; thus, a simple tripler can be easily built on a printed circuit board and integrated with other synthesizer components. 2.2.5

Digital Logic Multipliers

As discussed earlier, odd-order frequency multiplication can be accomplished simply by filtering the output of the circuits used to square the sine-wave signal. A good example is a digital logic gate shown in Figure 2.28. This circuit works nicely at low frequencies (depending on a particular logic device family) and provides an output turn-off feature by utilizing an auxiliary gate input. A typical spectrum for a 10-MHz input signal passed through a SN74LVC00A NANDgate is presented in Figure 2.29.

Figure 2.26

A double-balanced doubler utilizes a diode bridge.

Figure 2.27

Frequency tripler built with an antiparallel diode pair.

Building Blocks

Figure 2.28

63

A digital logic gate provides odd-order multiplication functions.

dBm 10 MHz IN 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80

Figure 2.29

2.2.6

Start: 0 Hz Res BW: 10 kHz

Vid BW: 30 kHz

Stop: 100.0000 MHz Sweep: 1.00s

NAND-gate output spectrum for a 10-MHz input frequency.

Step-Recovery-Diode Multipliers

A step-recovery diode (SRD) has long been used to build high-order frequency multipliers. The SRD utilizes capacitive nonlinearity to generate a train of very short pulses that is rich in high-order harmonics. The circuit is called a comb generator and is often used in multiloop synthesizers to generate a high-frequency LO signal with a coarse step size. A fixed-frequency filter or switched filter bank can be placed at the SRD multiplier output to choose a desired harmonic as is often used in direct analog synthesizer designs. Note that although the circuit may seem simple, it can require a lot of effort to optimize and implement properly. Design details are given in [52].

64

2.2.7

Frequency Synthesizers: Concept to Product

Varactor Multipliers

A varactor diode multiplier also relies on capacitive nonlinearity. It provides relatively low conversion loss and excellent phase noise characteristics. However, the varactor multiplier is notoriously narrowband and, similar to the SRD, very sensitive to circuit parameter variations. Under certain conditions it can exhibit a negative resistance and become unstable. For these reasons, the varactor multiplier is rarely used in modern synthesizer designs. 2.2.8

Transistor Multipliers

Transistor multipliers use both bipolar and FET devices. A device is biased in such a manner that it conducts during a portion of the input sine-wave cycle. Similar to diode multipliers, the signal waveform is distorted and harmonics are created. The transistor DC bias is adjusted to accentuate a selected harmonic. A balanced design is also possible as depicted in Figure 2.30. This circuit utilizes two devices that are fed in antiphase and conduct current during a positive and a negative half-cycle, respectively. The circuit delivers two pulses per period of the incoming signal, therefore generating a strong second harmonic. All oddharmonic products should be generally suppressed. The level of suppression depends on the mismatch between individual transistor characteristics. The main advantage of a transistor multiplier is its high efficiency. Nonlinear behavior and signal amplification functions of a transistor are combined to achieve frequency multiplication with minimal conversion loss or even conversion gain. This minimizes the number of additional components (such as amplifiers) required to compensate for signal loss. The main disadvantage is higher noise, which can restrict its application in multiplying a low-noise reference signal.

2.3 Frequency Dividers A frequency divider is an electronic device that produces a signal at 1/N of the input frequency where N is an integer. It works in the exact opposite way that a multiplier does, that is, it brings phase noise and PM-spurious improvement at the same 20logN rate [53–55]. This reduction in noise is ultimately limited

Figure 2.30

Balanced transistor doubler.

Building Blocks

65

by the residual phase noise characteristics of a particular divider. Although both digital and analog implementations are possible, the digital dividers are more versatile and commonly used. They are easily programmable, allowing large and variable division coefficients. Different logic families have different phase noise characteristics as a function of the operating frequencies. The noise in digital dividers is mainly generated in the transition region where the signal crosses the logic threshold. In general, faster logic and larger voltage swings exhibit better phase noise performance; a comparative analysis is given in [56]. Analog dividers offer better phase noise characteristics. They also have the ability to work at very high frequencies and are used in some critical applications. 2.3.1

Digital Dividers

The simplest digital divider is built using a D-type flip-flop as depicted in Figure 2.31. The flip-flop changes its output state with every rising edge of the incoming pulses, thus, providing a divide-by-2 function. Such a divider with a fixed division coefficient is called a prescaler and is available up to a few tens of gigahertz. Ideally, the output of a digital divider has a square-wave waveform that, in the frequency domain, exhibits only odd harmonics. In reality, even products are still present as illustrated in Figure 2.32. Divider harmonics can also be utilized to obtain fraction frequency multiplication or division coefficients (e.g., 3/2, 3/4, 5/4, and so forth), which can be desirable in certain cases. These elementary dividers are cascaded to obtain higher division coefficients. An electronic switch can be added to select a desired division coefficient as depicted in Figure. 2.33. This concept is realized in the UXC20P divider manufactured by Centellax, which operates through 20 GHz providing divideby-2, -4, and -8 functions.

D f IN

Q

f OUT

CLK Q

f IN

f OUT

Figure 2.31

A D-type flip-flop provides a divide-by-2 function.

66

Frequency Synthesizers: Concept to Product dBm Divide-by-2 Fin = 4 GHz 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 2.32

Start: 1.0000 GHz Res BW: 30 kHz

Stop: 11.0000 GHz Sweep: 11.50s

Divider output spectrum.

÷2

Figure 2.33

Vid BW: 100 kHz

÷2

÷2

Divider with a selectable division coefficient.

Other division coefficients are obtainable using a digital counter concept. A counter consists of a chain of flip-flops that are initially preset to a certain state by an external binary word as shown in Figure 2.34. The incoming pulses change the output state of the flip-flops, which is detected by an auxiliary state detector circuit. After counting a certain number of pulses, the circuit generates an output signal and also reloads the flip-flops to their initial state. The number of pulses to be counted during the full cycle depends on the initial, preloaded counter state. Thus, a variable, programmable divider can be realized. This is an important part of any PLL synthesizer since it controls the synthesizer’s output frequency by changing the division coefficient. Programmable dividers are usually implemented with CMOS technology and are readily available to a few hundred megahertz. Adding a high-frequency prescaler in front of the programmable divider extends the operating frequency range. Prescalers normally operate at much higher frequencies since they eliminate all delays involved in frequency presetting. This arrangement, however,

Building Blocks IN D1

CLK

67

Q

DATA PRE

CLK D2

Q

DATA State detector

PRE

CLK DN

OUT

Q

DATA PRE Reload

Figure 2.34

Programmable divider.

increases the synthesizer step size. For example, by adding a prescaler, the output frequency of a single-loop PLL synthesizer will be determined by f OUT = PNf PD

(2.6)

where fPD is the comparison frequency at the phase detector inputs, and P and N are division coefficients of a high-frequency prescaler and programmable divider, respectively. Since P is fixed, frequency tuning is now provided in discrete frequency steps equal to PfPD but not fPD. Decreasing comparison frequency can reduce the step size. However, this results in slower tuning and phase noise degradation. This limitation is overcome by using a dual-modulus prescaler concept depicted in Figure 2.35. A dual-modulus prescaler allows the setting of its division coefficient to have two different values: P or P + 1. It works in conjunction with two low-frequency, programmable dividers (marked as A-counter and B-counter), which are clocked from the same prescaler output. Initially, the prescaler divides by P + 1 until the A-counter counts A pulses and switches the prescaler division ratio to P. The number of input pulses required to reach this state equals

68

Frequency Synthesizers: Concept to Product Prescaler

B-Counter

÷(P+1)/P

÷B Reset

Modulus control

÷A A-Counter

Figure 2.35

Dual-modulus prescaler concept.

(P + 1)A. The B-counter counts B − A more pulses that corresponds to P(B − A) pulses at the prescaler input then generates an output signal. It subsequently reloads both counters to their initial settings and the process starts over. Thus, the overall number of input pulses counted during this full cycle is determined by N = (P + 1) A + P (B − A ) = PB + A

(2.7)

and the PLL tuning formula changes to f OUT = (PB + A ) f PD

(2.8)

Since both A and B are programmable integers, the output frequency can be tuned in steps equal to fPD. Therefore, the dual-modulus concept allows the extending of the operating frequency range without any loss in frequency resolution. However, several limitations are applied. First, A must be less than or equal to B. Otherwise, the B-counter would reset the system before the A-counter changed the prescaler division ratio, which would always be kept at P + 1. Moreover, A must cover the 0 to P − 1 range to ensure continuous integer spacing every time B is incremented. Therefore, we conclude that AMIN = 0, BMIN = AMAX = P − 1 and the minimum division coefficient is determined by N MIN = PBMIN + AMIN = P ( P − 1)

(2.9)

On the other hand, the P value should be kept sufficiently high to ensure proper operation of both counters when the input is at the highest operating frequency. This issue is addressed in multimodulus schemes that utilize a larger number of scaling factors.

Building Blocks 2.3.2

69

Analog Dividers

An analog frequency divider is essentially an oscillator that generates a signal at a subharmonic of the input signal. For example, a varactor diode, used in a negative resistance mode, can accomplish this function [57]. Analog principles are also used in a regenerative frequency divider depicted in Figure 2.36. The regenerative divider forms a feedback system that can oscillate under certain conditions [57–60]. To start oscillation, a signal must be present in the feedback path (e.g., caused by thermal fluctuations) and the loop gain must be greater than unity. The input frequency f is mixed with a feedback signal in a mixer that produces two products at f /2 and 3f /2. A lowpass filter removes the upper sideband to deliver a feedback signal at the right frequency. Assuming that the oscillation conditions have been met, the circuit outputs the signal at f /2, thus working as a frequency halver. Higher division coefficients are attained by inserting a frequency multiplier into the feedback path as illustrated in Figure 2.37. Analog frequency dividers work at a higher operating frequency and also exhibit significantly lower residual phase noise compared to digital dividers. However, they are rarely used because of their narrowband behavior as well as sensitivity to circuit parameters and input signal level.

2.4 Frequency Mixers A frequency mixer is an electronic device that produces signals at the sum and difference of the two input frequencies and their harmonics. Mixers are utilized f

f/2

f/2

f/2

3f /2 f/2

Figure 2.36

Analog regenerative divider block diagram.

f

f /N

f /N

f (2N + 1)/N

f (N + 1)/N

Figure 2.37

×(N + 1)

f /N

Higher division coefficients are attained by adding a frequency multiplier.

70

Frequency Synthesizers: Concept to Product

in direct analog architectures as well as indirect schemes where frequency offsetting (mixing) is involved. Mixers are available in IC form and can also be built from discrete parts. Similar to frequency multipliers, passive (diode-based) solutions are preferable when phase noise is a concern. 2.4.1

Frequency Mixing

The concept of frequency mixing comes from the trigonometric identity sin α sin β = [cos(α − β) − cos(α + β)]/2 and can be mathematically represented by the multiplication of two sine-wave signals V1 = A1 sin ω1t and V2 = A2 sin ω2t as

VOUT =

A1 A2 ⎡cos ( ω1 − ω2 )t − cos ( ω1 + ω2 )t ⎤⎦ 2 ⎣

(2.10)

Frequency mixing occurs due to component nonlinearities and results in two spectral components at the sum and difference of the input frequencies. Since any nonlinear component creates harmonics, the sum and difference products are created at the multiples of the input frequencies as well. Besides this, direct port-to-port signal leakages also take place. Therefore, the mixer output contains the input signals, harmonics, and their multiplication products described by f OUT = ±nf 1 ± mf 2

(2.11)

where n and m are integers. Similar to frequency multipliers, a single Schottkybarrier diode can be used as a nonlinear component to perform frequency mixing. However, a balanced design is always preferable since it allows canceling of certain multiplication products. There is a large variety of mixer designs. The most popular schemes along with corresponding design techniques are presented in [52]. In contrast to frequency dividers and multipliers, an ideal mixer provides a frequency shift without disturbing signal phase-modulated spurious and phase noise characteristics. This can be easily shown by inserting a phase-modulated signal V = A0 sin(ω0t + Am sin ωmt) into (2.10) instead of the plain sine wave. To highlight the fundamental difference between these three devices, a propagation of a phase-modulated signal with a −60-dBc spurious level through a hypothetically ideal multiplier-mixer-divider chain is illustrated in Figure 2.38. As always, practical scenarios are usually more complicated since AM-to-PM conversion and other effects can take place.

Building Blocks −60 dBc

×2

−54 dBc

71 −54 dBc

÷2

−60 dBc

Figure 2.38 Propagation of a phase-modulated signal through a hypothetically ideal multiplier-mixer-divider chain.

2.4.2

Harmonic Mixers

Harmonic mixing is useful when an LO signal needs to be multiplied. In general, according to (2.11), any single-diode mixer can be used as a harmonic mixer. However, the efficiency of such a mixer would not be high since conversion loss increases rapidly with the harmonic number. A clever solution is to combine an SRD multiplier and mixer diodes in a common package as depicted in Figure 2.39. The use of an SRD multiplier provides a much better efficiency compared to a single-diode solution. This solution eliminates the need for a separate multiplier, leading to considerable reduction in synthesizer component count. However, this mixer is very sensitive to circuit parameters—making one work properly is not trivial. Another concern is a reduced signal-to-noise ratio caused by high multiplication factors, which can result in phase noise degradation in some cases. A fundamental mixer driven by a chain of frequency multipliers can still be a better solution. A second harmonic mixer is another useful circuit. It employs an antiparallel diode pair that is connected in series (or parallel) to the incoming RF signal as depicted in Figure 2.40. An LO signal switches a corresponding diode during a negative and a positive half-cycle, respectively. As a result, the diode pair conducts two times per cycle, as a single diode would be driven by a doubled signal. In other words, the second harmonic mixer requires an LO signal at half the frequency compared to a regular, fundamental mixer. A disadvantage is lower conversion loss and worse linearity compared to a fundamental solution.

Figure 2.39

A harmonic mixer IC combines an SRD multiplier with mixer diodes.

72

Frequency Synthesizers: Concept to Product

RF matching circuit

IF matching & ground return

LO matching circuit

Figure 2.40

2.4.3

Second harmonic mixer built with an antiparallel diode pair.

Image-Reject Mixers

In a regular mixer, two different (but spaced equally above and below the LO signal) input RF frequencies may result in the same IF output. An image-reject mixer eliminates this uncertainty by out-of-phase cancellation of an undesired signal sideband (called an image). A generic block diagram of the image-reject mixer is presented in Figure 2.41. It consists of two regular mixers fed with a 90° phase shift between their RF ports. As a result, the IF signals also have a 90° difference; hence, another 90° hybrid is used to combine the IF outputs in phase. Note that another RF sideband flips the phase shift; hence, the IFs are combined out-of phase and cancelled. This scheme can be used in reverse as a single-sideband (SSB) modulator that upconverts an IF signal and rejects an undesired sideband as illustrated in Figure 2.42. To examine this arrangement, let’s assume that the LO and IF signals at the first mixer are described by VLO = ALO sin ωLOt and VIF = AIF sin ωIF t, respectively. Then the second mixer is driven by VLO = ALO cos ωLO t and VIF = AIF cos ωIF t as a result of the 90° phase shift introduced by the LO and IF hybrids. The mixer output signals are determined by

RF

90° hybrid

90° hybrid

IF LO Figure 2.41

Image-reject mixer block diagram.

Building Blocks IF 1

IF

90° hybrid

90° hybrid

73 RF 1

LO 1

RF

LO 2

IF 2

RF 2

LO

Figure 2.42

SSB modulator upconverts an IF signal and rejects an undesired sideband.

V RF 1 = ALO sin ωLO t × AIF sin ωIF t =

V RF 2

ALO AIF 2 = ALO cos ωLO t × AIF cos ωIF t = ALO AIF 2

⎡⎣cos ( ωLO − ωIF )t − cos ( ωLO + ωIF ) t ⎤⎦

(2.12) ⎡⎣cos ( ωLO − ωIF ) t + cos ( ωLO + ωIF ) t ⎤⎦

After combining these two signals, the output will become VOUT = V RF 1 + V RF 2 = ALO AIF cos ( ωLO − ωIF )t

(2.13)

Thus, one (lower) sideband is generated and another one is cancelled. However, the unwanted sideband is never cancelled completely. The level of rejection depends heavily on the phase and amplitude balance. Equalizing the signal paths within 1 dB (amplitude) and 10° (phase) results in approximately a 20-dB sideband rejection, which is considered to be a reasonable number. 2.4.4

IQ-Modulators

Vector modulation (also called IQ-modulation) is widely used in modern digital communication systems. A typical IQ-modulator consists of two identical mixers driven with a 90° phase shift at their LO ports as shown in Figure 2.43. Two separate baseband data signals are applied directly to the IF ports, upconverted, and summed together with no phase shift between them. The resulting output is an IQ-modulated signal at the same carrier frequency as the LO. Similar to the previous case, the quality of the modulated signal depends on both amplitude and phase balance of the I and Q paths.

74

Frequency Synthesizers: Concept to Product I

LO

90° hybrid

RF

Q

Figure 2.43

IQ-modulator block diagram.

2.5 Phase Detectors A phase detector is an electronic device that compares two input signals and generates a voltage representing the phase difference between the signals. The phase detector is the main element of any PLL synthesizer. There are many types of phase detectors [54, 55]; the most popular ones are listed next. 2.5.1

Balanced Mixer

A balanced mixer can be used as a phase detector. As discussed earlier, a frequency mixer generates both the sum and difference frequencies described by (2.10). Assuming that the mixer is driven by two sine-wave signals V1 = A1 sin(ω1t + θ1) and V2 = A2 sin(ω2t + θ2), its output is described by

VOUT =

A1 A2 AA cos ⎡⎣( ω1 − ω2 )t + θ1 − θ 2 ⎤⎦ − 1 2 cos ⎡⎣( ω1 + ω2 ) t + θ1 + θ 2 ⎤⎦ (2.14) 2 2

By putting a lowpass filter at the mixer output, we can remove the sum product and (2.14) reduces to

VOUT =

A1 A2 cos ⎡⎣( ω1 − ω2 )t + θ1 − θ 2 ⎤⎦ 2

(2.15)

Note that when the mixer inputs have the same frequencies, its output provides a DC voltage that is proportional to the phase difference between the input signals. A balanced configuration should be used to minimize an unwanted DC voltage offset that could affect the detector output. Other undesired signals are

Building Blocks f REF

75

VCO

f OUT

f OUT = N f REF

Figure 2.44

A sampling mixer locks a VCO to an integer multiple of a reference signal.

present at twice the reference frequency (that is, the sum component) and the reference frequency itself (because of insufficient port-to-port isolation). The main advantages of such a phase detector are its low residual noise and ability to support a very high reference frequency. The disadvantages are relatively high undesired signals (e.g., reference harmonics as well as a DC offset caused by imperfect balance) and an initial frequency acquisition problem when the PLL is out of lock. An acquisition aid circuit is normally required to presteer a VCO to a frequency where it can be held by the phase detector. 2.5.2

Sampling Mixer

A harmonic (sampling) mixer, which we discussed earlier, can be used as a phase detector as well. It can lock a high-frequency VCO to an integer multiple of a reference (as shown in Figure 2.44), thus eliminating the need for a frequency multiplier or divider. Note, however, that the sampling detector is very sensitive to circuit parameters. It also exhibits elevated noise because of high multiplication factors. Moreover, broadband noise near multiples of the reference frequency is also converted down and appears at the sampler output. Thus, a fundamental balanced mixer driven by a separate multiplier is usually a better choice. The sampling mixer provides no frequency discrimination; thus, a frequency acquisition aid is required. 2.5.3

Exclusive-OR Gate

Digital logic is used extensively for constructing various phase detectors. The simplest solution is based on an exclusive-OR gate as depicted in Figure 2.45. This gate is driven by two square-wave pulse streams coming from the reference and feedback dividers. When the two signals are completely in-phase, the gate outputs zero voltage. When the signals differ by 180°, the gate’s output sets to high. A phase shift between 0° and 180° results in a train of pulses. By smoothing this output with a lowpass filter, we can get a voltage that is proportional to the phase difference between the two signals. The output spectrum of the exclusive-OR gate has no reference component; however, it does have the component at twice the reference frequency.

76

Frequency Synthesizers: Concept to Product

Figure 2.45

An exclusive-OR gate works as a phase detector.

This component has a maximum when the inputs have 90° phase shift, which is usually the operating state for the phase detector. From this point of view, the exclusive-OR gate works similarly compared to a balanced mixer. It has relatively strong spurious output content and has no frequency discrimination. Moreover, for proper operation, it has to be driven by symmetrical signals with a 50% duty cycle. Nevertheless, the exclusive-OR gate can be successfully used in some nondemanding applications (e.g., as a lock-detection circuit). 2.5.4

Flip-Flop

A flip-flop can be also used as a phase detector as illustrated in Figure 2.46. Similar to the exclusive-OR gate, it is driven by pulse streams that set and reset the output. Very short pulses should be used for proper operation. The average voltage at the flip-flop output represents the phase difference between the input signals. The main advantage is the circuit simplicity. No frequency discrimination is provided. 2.5.5

Phase-Frequency Detector

There is a large variety of phase detector schemes constructed with flip-flops. A phase-frequency detector (PFD) is a very popular solution since it provides a frequency-sensitive signal to aid frequency acquisition. The detector consists of a pair of D-type flip-flops as well as an AND-gate connected as shown in Figure 2.47. A time-delay element at the AND-gate output can also be added to remove the output uncertainty (referred to as a dead zone) when the signals are completely in-phase and there is no time separation between them. The PFD has two outputs marked as up and down. The logic high signal at the up-output

Building Blocks

Figure 2.46

77

Flip-flop phase detector.

Vcc D F1

Q

Up

Q

Down

CLK R Vcc D

F2

CLK R

Figure 2.47 A phase-frequency detector provides a frequency-sensitive signal when PLL is out of lock.

commands the VCO to increase its frequency. The logic high signal at the downoutput does the opposite. The lock is achieved when both outputs set to zero. Note that both flip-flops cannot be set to high simultaneously since they would be immediately reset by the AND-gate circuit. The PFD output information is contained in the polarity and widths of the up and down pulses that are combined and averaged with a loop filter shown in Figure 2.48. Alternatively, the outputs can be summed with a charge pump circuit, which is essentially a pair of switched current sources (Figure 2.49).

78

Frequency Synthesizers: Concept to Product Vcc D F1

Q

CLK R

− +

Vcc D F2

Q

CLK R

Figure 2.48

An operational amplifier combines PFD outputs.

V+ Vcc

Current source D

F1

Q

CLK R Vcc D

F2

Q

CLK

Current source

R V-

Figure 2.49

PFD outputs can be summed with a charge pump circuit.

The main advantage of the phase-frequency detector is its ability to sense the frequency, thus eliminating a need for initial frequency acquisition. This is probably the most popular and widely used phase detector. Disadvantages are associated with dead-zone effects and higher residual phase noise in comparison with analog schemes.

Building Blocks 2.5.6

79

Integrated PLL Components

Phase detectors are available as surface-mount ICs and are often combined with other PLL components on the same chip. Analog Devices, Inc., National Semiconductor, Peregrine Semiconductor Corporation, Hittite Microwave Corporation, and other manufacturers provide fully integrated solutions that contain all necessary components required to build a whole synthesizer. A good example is the ADF4106 PLL IC manufactured by Analog Devices, Inc. The part consists of a digital phase-frequency detector with an integrated charge pump, programmable RF and reference dividers, lock detector, and other useful circuits as depicted in Figure 2.50. The reference divider is a 14-bit programmable counter that provides division ratios from 1 to 16,383. The counter divides the input reference signal down to produce a required phase detector comparison frequency (equal to a desired step size). The specified input frequency range is 20 to 300 MHz. It can be extended to lower frequencies by ensuring a sufficient slew rate of the incoming reference signal. This is accomplished practically by placing a sine-to-square wave converter in front of the IC. The RF divider is constructed using the dual-modulus technique discussed above. It includes a dual-modulus prescaler with a selectable modulus of 8/9, 16/17, 32/33, or 64/65. The prescaler works in conjunction with A- and Bcounters to allow a wide range of division ratios. The A-counter is a 6-bit counter that counts between 0 and 63. The B-counter is a 13-bit device that provides division ratios between 3 and 8,191. Keeping in mind that NMIN = P(P − 1) (as required to realize contiguous division ratios) and NMAX = PBMAX + AMAX, the available division ratios are calculated as indicated in Table 2.1. The RF divider input frequency range is specified between 0.5 and 6 GHz. Similar to the reference divider, the operating frequency range can be easily extended down with a sine-to-square wave converter. Higher operating frequencies are available with ADF4107 (7 GHz) and ADF4108 (8 GHz) ICs, which are pin-to-pin compatible devices. Note that the A- and B-counters are CMOS devices specified to work when the prescaler output is 325 MHz or less. The reference and RF divider outputs are routed to the phase detector that produces an output proportional to the phase and frequency difference between the inputs. The maximum allowable comparison frequency is 104 MHz. The phase detector is accompanied by a charge pump. The charge pump current is set by connecting an external resistor and can be further controlled (changed) by software means. Similarly, the phase detector polarity can be programmed if required. Furthermore, the detector also includes a programmable delay element that controls the width of the antibacklash pulse to minimize the dead-zone effects. The ADF4106 IC includes a lock detector that can work in either analog or digital lock detection mode as will be further discussed in Chapter 4. The

Figure 2.50

The ADF4106 PLL IC includes all essential components required to build a frequency synthesizer. (Courtesy of Analog Devices, Inc.)

80 Frequency Synthesizers: Concept to Product

Building Blocks

81

Table 2.1 RF Divider Division Ratios

P/P + 1

NMIN

NMAX

8/9

56

65,591

16/17

240

131,119

32/33

992

262,175

64/65

4,032

524,287

output multiplexer on the ADF4106 allows the user to access various internal points including the lock detector output, RF and reference divider outputs, bias voltage, and ground. A dedicated chip enable pin allows the disabling of all main blocks of the ADF4106 integrated circuit. A logic low signal on this pin powers down the device and puts the charge pump output into a three-state mode. Further details regarding functionality are available in the ADF4106 datasheet [61]. An evaluation board containing the IC and all other parts required to evaluate its functionality and technical characteristics is shown in Figure 2.51. ADF4106 parameters (such as RF and reference divider division coefficients) can be conveniently programmed through a built-in three-wire serial interface (clock, data, and chip select lines). The user can also program charge

Figure 2.51 An evaluation board allows evaluating functionality and technical characteristics of PLL ICs. (Courtesy of Analog Devices, Inc.)

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Frequency Synthesizers: Concept to Product

pump current (to adjust PLL bandwidth), change phase detector polarity (this feature can be very helpful if frequency mixing is employed), monitor frequency lock, or access some internal signals. The IC allows building a simple single-loop PLL synthesizer (by adding an external VCO and loop filter components) or can be used in more complex schemes. A single-loop PLL design example, based on this part, will be reviewed in more detail in Chapter 4.

References [1] Bahl, I., and P. Bhartia, Microwave Solid State Circuit Design, 2nd ed., New York: John Wiley & Sons, 2003. [2] Rohde, U. L., A. K. Poddar, and G. Bock, The Design of Modern Microwave Oscillators for Wireless Applications: Theory and Optimization, New York: John Wiley & Sons, 2005. [3] Leeson, D. B., “A Simple Model of Feedback Oscillator Noise Spectrum,” IEEE Proc. Letters, Vol. 54, February 1966, pp. 329–330. [4] Parzen, B., “Clarification and a Generalized Restatement of Leeson’s Oscillator Noise Model,” IEEE Intl. Frequency Control Symposium Proc., June 1988, pp. 348–351. [5] Nallatamby, J., et al., “Extension of the Leeson Formula to Phase Noise Calculation in Transistor Oscillators with Complex Tanks,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, March 2003, pp. 690–696. [6] Rubiola, E., “The Leeson Effect: Phase Noise in Feedback Oscillators,” IEEE Int. Frequency Control Symposium Tutorial, June 2006. [7] Sen Gupta, A., et al., “High Spectral Purity Microwave Oscillator: Design Using Conventional Air-Dielectric Cavity,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 51, October 2004, pp. 1225–1231. [8] Kajfez, D., and P. Guillon, Dielectric Resonators, Norwood, MA: Artech House, 1986. [9] Khanna, A. P. S., “Review of Dielectric Resonator Oscillator Technology,” IEEE Intl. Frequency Control Symposium Proc., May 1987, pp. 478–486. [10] Loboda, M. J., T. E. Parker, and G. K. Montress, “Frequency Stability of L-Band, Two-Port Dielectric Resonator Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. 35, December 1987, pp. 1334–1339. [11] Khanna, A. P. S., “Microwave Oscillators: The State of the Technology,” Microwave Journal, April 2006, pp. 22–24. [12] McNeilage, C., et al., “A Review of Sapphire Whispering Gallery-Mode Oscillators Including Technical Progress and Future Potential of the Technology,” IEEE Intl. Frequency Control Symposium Proc., August 2004, pp. 210–218. [13] Tobar, M. E., et al., “High-Q Whispering Gallery Traveling Wave Resonators for Oscillator Frequency Stabilization,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 47, March 2000, pp. 421–426.

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[14] Tsarapkin, D. P., and N. A. Shtin, “Whispering Gallery Traveling Wave Interferometer for Low Phase Noise Applications,” IEEE Intl. Frequency Control Symposium Proc., August 2004, pp. 762–765. [15] Tobar, M. E., et al., “Compact, High-Q, Zero Temperature Coefficient, TE011 SapphireRutile Microwave Distributed Bragg Reflector Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 48, May 2001, pp. 821–829. [16] Dick, G. J., and J. Saunders, “Measurement and Analysis of a Microwave Oscillator Stabilized by a Sapphire Dielectric Ring Resonator for Ultra-Low Noise,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37, September 1990, pp. 339–346. [17] Carter, Jr., P. S., “Magnetically-Tunable Microwave Filters Using Single-Crystal YttriumIron-Garnet Resonators,” IRE Transactions on Microwave Theory and Techniques, Vol. 9, May 1961, pp. 252–260. [18] Helszajn, J., YIG Resonators and Filters, New York: John Wiley & Sons, 1985. [19] Heyboer, T. L., and F. E. Emery, “YIG-Tuned GaAs FET Oscillators,” IEEE Intl. Microwave Symposium Dig., June 1976, pp. 48–50. [20] Trew, R. J., “Design Theory for Broad-Band YIG-Tuned FET Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-27, January 1979, pp. 8–14. [21] Papp, J. C., “An 8-18 GHz YIG-Tuned FET Oscillator,” IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-28, July 1980, pp. 762–767. [22] Khanna, A. P. S., and J. Buenrostro, “2-22 GHz Low Phase Noise Silicon Bipolar YIG Tuned Oscillator Using Composite Feedback,” IEEE Int. Microwave Symposium Dig., June 1992, pp. 1297–1299. [23] Zensius, D. P., M. Draher, and N. K. Osbrink, “Device and Construction Refinements Yield First 33 to 50 GHz GaAs FET YTO,” Microwave Journal, June 1986, pp. 153–159. [24] Khanna, A. P. S., et al., “Low Jitter Silicon Bipolar Based VCOs for Applications in High Speed Optical Communication Systems,” IEEE Intl. Microwave Symposium Dig., May 2001, pp. 1567–1570. [25] Rohde, U. L., A. K. Poddar, and K. J. Schoepf, “Cost-Effective VCOs Replace PowerHungry YIGs,” Microwaves & RF, April 2006, pp. 80–87. [26] Kroupa, V. F., “The State of the Art of Flicker Frequency Noise in BAW and SAW Quartz Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, May 1988, pp. 406–420. [27] Driscoll, M. M., “Low-Noise Microwave Signal Generation Using Bulk- and SurfaceAcoustic-Wave Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, May 1988, pp. 426–434. [28] Montress, G. K., et al., “Extremely Low-Phase-Noise SAW Resonators and Oscillators: Design and Performance,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, November 1988, pp. 657–667. [29] Khanna, A. P. S., et al., “A Film Bulk Acoustic Resonator (FBAR) L band Low Noise Oscillator for Digital Communications,” Proc. of 32nd European Microwave Conference, October 2002.

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[30] Yao, S., and L. Maleki, “Characteristics and Performance of a Novel Photonic Oscillator,” IEEE Intl. Frequency Control Symposium Proc., May–June 1995, pp. 161–168. [31] Yao, X. S., and L. Maleki, “Optoelectronic Oscillator for Photonic Systems,” IEEE Journal of Quantum Electronics, Vol. 32, July 1996, pp. 1141–1149. [32] Ilchenko, V. S., “Optical Microsphere Resonators and Laser Frequency Stabilization,” Lasers and Electro-Optics Society Annual Meeting Proc., November 1997, pp. 94–95. [33] Parker, T. E., “Current Developments in SAW Oscillator Stability,” IEEE Intl. Frequency Control Symposium Proc., June 1977, pp. 359–364. [34] Everard, J. K. A., “A Review of Low Noise Oscillator. Theory and Design,” IEEE Intl. Frequency Control Symposium Proc., May 1997, pp. 909–918. [35] Galani, Z., et al., “Analysis and Design of a Single-Resonator GaAs FET Oscillator with Noise Degeneration,” IEEE Transactions on Microwave Theory and Techniques, Vol. 32, December 1984, pp. 1556–1565. [36] Tsarapkin, D. P., “Phase Noise in Microwave Bridge Oscillators,” IEEE Intl. Frequency Control Symposium Proc., August 2005, pp. 534–538. [37] Darwish, A. M., et al., “A New Phase Noise Reduction Technique for MMIC Oscillators,” IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Dig., June 1992, pp. 171–174. [38] Kuleshov, V. N., and T. I. Boldyreva, “l/f AM and PM Noise in Bipolar Transistor Amplifiers: Sources, Ways of Influence, Techniques of Reduction,” IEEE Intl. Frequency Control Symposium Proc., May 1997, pp. 446–455. [39] Rohde, U. L., and A. K. Poddar, “Noise Minimization Techniques for RF and MW Signal Sources,” Microwave Journal, September 2007, pp. 136–162. [40] McNeilage, C., et al., “Review of Feedback and Feedforward Noise Reduction Techniques,” IEEE Int. Frequency Control Symposium Proc., May 1998, pp. 146–155. [41] Black, H. S., “Translating System,” U.S. Patent 1,686,792, October 1928. [42] Everard, J., Fundamentals of RF Circuit Design: with Low Noise Oscillators, New York: John Wiley & Sons, 2001. [43] Walls, F. L., C. M. Felton, and T. D. Martin, “High Spectral Purity X-Band Source,” IEEE Intl. Frequency Control Symposium Proc., May 1990, pp. 542–548. [44] Dick, G. J., “Microwave Oscillators for Superior Short Term Stability and Ultra-Low Phase Noise,” IEEE Intl. Frequency Control Symposium Proc., May 1992, pp. 349–355. [45] Tsarapkin, D. P., “Low Phase Noise Sapphire Disk Dielectric Resonator Oscillator with Combined Stabilization,” IEEE Intl. Frequency Control Symposium Proc., June 1994, pp. 451–458. [46] Bianchini, M. J., et al., “A Single-Resonator GaAs FET Oscillator with Noise Degeneration,” IEEE Int. Microwave Symposium Dig., May–June 1984, pp. 270–273. [47] Santiago, D. G., and G. J. Dick, “Microwave Frequency Discriminator with a Cooled Sapphire Resonator for Ultra-Low Phase Noise,” IEEE Intl. Frequency Control Symposium Proc., May 1992, pp. 176–182.

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[48] Ivanov, E. N., M. E. Tobar, and R. A. Woode, “Microwave Interferometry: Application to Precision Measurements and Noise Reduction Techniques,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 45, November 1998, pp. 1526–1536. [49] Ivanov, E. N., M. E. Tobar, and R. A. Woode, “Applications of Interferometric Signal Processing to Phase-Noise Reduction in Microwave Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. 46, October 1998, pp. 1537–1545. [50] Pound, R. V., “Electronic Frequency Stabilization of Microwave Oscillators,” Review of Scientific Instruments, Vol. 17, November 1946, pp. 490–505. [51] Faber, M. T., J. Chramiec, and M. E. Adamski, Microwave and Millimeter-Wave Diode Frequency Multipliers, Norwood, MA: Artech House, 1995. [52] Maas, S. A., The RF and Microwave Circuit Design Cookbook, Norwood, MA: Artech House, 1998. [53] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [54] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [55] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [56] McClure, M. R., “Residual Phase Noise of Digital Frequency Dividers,” Microwave Journal, March 1992, pp. 124–130. [57] Driscoll, M. M., “Phase Noise Performance of Analog Frequency Dividers,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37, July 1990, pp. 295–301. [58] Harrison, R. G., “Theory of Regenerative Frequency Dividers Using Double-Balanced Mixers,” IEEE Intl. Microwave Symposium Dig., June 1989, pp. 459–462. [59] Rubiola, E., M. Olivier, and J. Groslambert, “Phase Noise in the Regenerative Frequency Dividers,” IEEE Transactions on Instrumentation and Measurement, Vol. 41, June 1992, pp. 353–360. [60] Ferre-Pikal, E. S., and F. L. Walls, “Microwave Regenerative Frequency Dividers with Low Phase Noise,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 46, January 1999, pp. 216–219. [61] Analog Devices, Inc., “PLL Frequency Synthesizer, ADF4106,” Datasheet, www.analog. com.

3 Synthesizer Construction Chapter 2 discussed the individual components that are used in frequency synthesizers. The next logical step is to examine how these components are physically connected together. This chapter focuses on constructional and packaging principles used in building microwave frequency synthesizers. It begins with a brief overview of transmission line theory, types of transmission lines, characteristic impedance, losses, discontinuity and coupling effects, microwave materials, and distributed and lumped elements. It continues with a review of the most popular assembling techniques including hybrid “chip-and-wire” and printed circuit board approaches. Packaging aspects, including grounding and shielding effects, are also discussed.

3.1 Transmission Lines and Distributed Elements At low frequencies, a circuit can be built by simply connecting its individual elements with wires according to a schematic diagram. As frequency increases, however, various undesired effects occur. A key principle in designing RF and microwave circuits is the need to take into account physical dimensions not only for circuit components but also for their interconnections, which are treated as transmission lines. 3.1.1

Transmission Line Basics

A transmission line is a material medium that guides electrical energy from one point to another. The simplest transmission line is a wire (or two wires since a ground path is needed). In circuit theory, such a wire is a simple connection between circuit nodes. However, in reality, any wire has an inductance that is proportional to the wire’s length. Furthermore, there is always a capacitance be87

88

Frequency Synthesizers: Concept to Product

tween the signal wire and the ground. Inductance and capacitance effects can be significant at high frequencies. In general, they also take place at low frequencies and become quite noticeable for a very long wire. The terms “long” or “short” are relative since they depend on the frequency (or the wavelength) of the traveling electrical signal. A transmission line is considered to be electrically long when its physical length becomes comparable to the wavelength of the electrical signal it carries. At high frequencies, even a physically short wire acts as an LC-circuit rather than a simple electrical connection. Moreover, any transmission line introduces losses to the electrical energy that it is supposed to guide. The conductor, forming a transmission line, always has some resistance, which is never equal to zero. Obviously, a portion of the energy is dissipated in the form of heat when the current flows through such a conductor. The transmission line can also radiate some energy into surrounding space that results in transmission power loss. Furthermore, some energy is dissipated in the dielectric material between the signal line and the ground. These losses are modeled by adding a resistance in series with the inductor as well as a shunt conductance across the capacitor as illustrated in Figure 3.1. In reality, the picture is even more complicated as the indicated effects are not concentrated in one physical spot but rather distributed along the entire length of the transmission line. The transmission line is modeled by breaking it into an infinite number of electrically small elementary cells and then cascading them. The values of such elementary components (called distributed constants) are specified per unit length and depend on physical characteristics (e.g., dimensions, dielectric type) of a particular transmission line. Although the distributed constants can be extracted from the line dimensions, a more practical and widely used parameter is characteristic impedance determined by

Z0 =

R + j ωL G + j ωC

(3.1)

The characteristic impedance denotes the ratio of the complex voltage to the complex current of the traveling wave at any point on a matched terminated R

L

G

Figure 3.1

R

C

L

G

C

A transmission line is modeled by cascading an infinite number of elementary cells.

Synthesizer Construction

89

line. From this point of view, the characteristic impedance is somewhat comparable to the resistance in a “regular” DC circuit. The importance of this parameter is the fact that it governs what portion of the energy is delivered to the load and what portion is reflected back to the source. Obviously, a good connection assumes maximum energy transfer with minimal reflections. This is achieved when both source and load are matched, meaning that the load’s impedance is the complex conjugate of the source’s impedance. Note that any electronic device connects to another device through a transmission line that serves as a load for the input device and as a source for the output device, respectively. Thus, the transmission line should be matched with the devices that it connects. Many RF and microwave devices used in frequency synthesizer designs are specified for 50-ohm input and output impedances (although some devices work in other environments, such as 75 or 600 ohms). Hence, a 50-ohm transmission line is a key component of any high-frequency design since it serves as a connection element between individual devices. 3.1.2

Transmission Line Types

Transmission lines can be formed in many different ways—ranging from a twisted pair of wires and coaxial cable to exotic waveguide structures. However, planar transmission lines are the most practical media to interface with surfacemount and chip components used in synthesizer designs. The most popular planar structures are briefly described next. More details on particular transmission lines as well as their design techniques are given in [1–10]. 3.1.2.1 Microstrip Line

A microstrip transmission line is formed with a flat conductive strip on one side of a dielectric material called a substrate. The opposite side of the substrate is covered by metal that serves as a ground. The microstrip is the most popular transmission line and is widely used in both monolithic and hybrid circuits. It can be simply formed on a hard substrate or a soft board by photolithographic processes. If designed properly, the “printed” traces look and act very similar to the “natural” connection lines shown on a schematic diagram. The microstrip environment also allows the mounting of circuit components on the top side of the board, thus simplifying the assembly process. The basic geometry of the microstrip line is shown in Figure 3.2, where W denotes the width of the conductive strip, H is the substrate’s height, ε is the dielectric constant of the substrate, and T is the conductor’s thickness. There are a number of empirical equations for the microstrip line’s characteristic impedance, which is a function of the ratio of the substrate height to the conductor strip width. For example, a 15-mil strip printed on a 15-mil-thick alumina substrate (the dielectric constant of alumina is close to 10) produces approximately

90

Frequency Synthesizers: Concept to Product W

T H

Figure 3.2

ε

Microstrip transmission line.

a 50-ohm characteristic impedance. An alumina substrate of 10-mil thickness requires a 10-mil strip for the same impedance. The impedance also depends heavily on the dielectric constant of the substrate. A higher dielectric constant means higher line capacitance and lower characteristic impedance. For example, in order to realize 50-ohm impedance on an 8-mil soft board with the dielectric constant of 3.38 (RO4003C material manufactured by Rogers Corporation), the line width has to be increased to about 18 mils. The thickness of the metal strip also affects the characteristic impedance. Although the effect is not so pronounced, a greater metal thickness increases the capacitance of the line and therefore reduces its impedance. A metal enclosure in close proximity to the microstrip line has a similar effect (i.e., it lowers the line impedance). A disadvantage of the microstrip line is that it is an open structure and therefore tends to radiate. Hence, circuits that require high isolation (filters, switches, and so forth) have to be properly shielded. Another issue is the dispersion that becomes noticeable at high frequencies. The dispersion manifests itself through signals of different frequencies propagating at slightly different speeds. This may result in asymmetric frequency responses of some distributed structures such as bandpass filters. Microstrip lines also exhibit losses to the propagating signals. For substrates with high dielectric constants, resistive losses in the strip conductor and the ground plane usually dominate over dielectric and radiation losses. The losses in the strip conductor increase with increasing characteristic impedance because of the greater resistance of narrow strips. Surface roughness and skin effect contribute to the conductor losses as well. Skin effect manifests itself as electrical current irregularities inside a metal volume. The effect is characterized by skin depth, which denotes the distance where the electric field reduces to 1/e of its value at the conductor surface. In other words, skin depth indicates how deep the current penetrates into the conductor. The skin depth is inversely proportional to the square root of the operating frequency. At microwave frequencies, the electrical current is mostly concentrated near the conductor surface. There-

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91

fore, proper metallization is vital to control conductive losses. The metallization thickness should be a few times higher than the skin depth to reduce this effect. 3.1.2.2 Stripline

A stripline uses a flat metal strip surrounded by a dielectric between two parallel ground planes as shown in Figure 3.3. It requires three metal layers, which is why it was originally called triplate. Similar to the microstrip, the characteristic impedance of the stripline is mainly determined by the width of the strip, the thickness of the substrate, and its dielectric constant. The structure is often built using a multilayer printed circuit board where the central conductor is sandwiched between two board pieces. The structure can also be made asymmetric if necessary. For example, the central conductor does not need to be equally spaced between the two ground planes. Furthermore, the dielectric materials may be different above and below the central conductor. The stripline exhibits lower radiation as compared to the microstrip line. It also offers excellent isolation since the central strip can be conveniently shielded by putting a few parallel rows of stitching via holes between the ground planes on both sides of the strip. The stripline is widely used to create broadband distributed circuits such as filters and directional couplers. However, in contrast with microstrip, the stripline is not easily integrated with other circuit components. It is mainly used in multilayer boards in conjunction with microstrip lines when it is necessary to route RF signals across each other. 3.1.2.3 Coplanar Waveguide

A coplanar waveguide consists of a conductive strip surrounded by a pair of ground planes as illustrated in Figure 3.4. Both conductor and ground planes are printed on the same surface of the dielectric substrate. The electric field is mainly concentrated not in the dielectric substrate but in the gap between the central strip and the ground planes. As a result, radiation effects are more pronounced compared to those of the microstrip. The structure is often accompanied by another ground plane formed on the opposite side of the substrate as shown in

Figure 3.3

Stripline structure.

92

Frequency Synthesizers: Concept to Product

Figure 3.4 A coplanar waveguide consists of a conductive strip surrounded by a pair of ground planes.

Figure 3.5. The top ground planes are usually connected to the bottom plane with stitching via holes. The coplanar waveguide allows for mounting circuit components on top of the substrate similar to the microstrip line environment. Moreover, mounting of shunt elements is even more convenient since the ground is within close proximity of the signal line. The ground path inductance is usually smaller compared to ground vias required in the microstrip environment. Therefore, the coplanar waveguide is preferable at higher frequencies over the microstrip line. The coplanar waveguide can easily interface with other transmission lines (such as microstrip or coaxial line) as well as with microwave probes. It is a good alternative to the microstrip and is widely used in both monolithic and hybrid circuits. 3.1.2.4 Slotline

A slotline is built as a narrow gap between conductive planes formed on one side of a dielectric substrate as depicted in Figure 3.6. Similar to the coplanar waveguide, it is a convenient medium for mounting shunt elements. Although, it is not as popular as the microstrip or the coplanar waveguide, the slotline is very useful in some applications. An example in Figure 3.7 shows a slotline junction that splits a signal into two branches with exactly a 180° phase shift caused by the inversion of the electric field. This circuit can be conveniently used in a variety of balanced devices such as mixers or frequency multipliers [11]. 3.1.3

Microwave Materials

The main parameters of planar transmission lines depend heavily on substrate material and its metallization. The most popular dielectric materials (divided

Figure 3.5

Coplanar waveguide with ground plane.

Synthesizer Construction

Figure 3.6

A slotline is built as a narrow gap between conductive planes.

Figure 3.7

A slotline splits a signal into two branches with a 180° phase shift.

93

into two main classes: hard substrates and soft boards), along with their physical properties, are listed in Table 3.1. Alumina is the most widely used hard substrate dielectric material, which provides a good balance between physical properties (e.g., reasonably low loss at Table 3.1 Hard Substrate and Soft Board Dielectric Materials Dielectric Constant

Loss Tangent, ×10−4

Alumina

9–10

<1

Fused silica

3.8

<1

Material Hard Substrates

Sapphire

9.4, 11.6

<1

Aluminum nitride

8.6

<10

Beryllium oxide

6.5

<10

4.3–4.8

100–200

Soft Boards FR-4 RT/duroid 5880

2.2

4–9

RO4003C

3.38

21–27

RO4350B

3.48

31–37

94

Frequency Synthesizers: Concept to Product

microwave frequencies, good thermal conductivity, good adhesion with metal layers, and so forth) and cost. Alumina is an extremely hard yet malleable material that can be cut to a desired form. Its adhesion to metal is reasonably strong; thus, conductor layers can be easily deposited and then etched to form a required circuit pattern. Unfortunately, the thermal expansion of alumina is not well matched with common metal materials such as aluminum or brass. Hence, it is preferable to attach the alumina substrate to a piece of metal (called a carrier) fabricated from a special alloy such as Kovar, molybdenum, or tungsten copper. These alloys exhibit thermal expansion properties similar to alumina and minimize the risk of cracking when temperature changes. Fused silica (also called quartz) and sapphire are single-crystal dielectrics that demonstrate low dielectric loss as well as excellent surface smoothness. This results in a lower conductive loss of the metal layers deposited on the substrate. These materials are more expensive and fragile compared to alumina; hence, they are rarely used in conventional designs. Aluminum nitride and beryllium oxide feature exceptional thermal conductivity and are utilized in high power applications where good heat sinking is crucial. In regular microwave circuits, they are less common compared to alumina. Soft boards utilize composite materials, which are fabricated from flexible plastics such as polytetrafluoroethylene (PTFE, also known as Teflon). They are reinforced with ceramic or fiber glass powder to form required physical properties. The soft boards are generally less costly and easier to fabricate compared to hard substrates. They are widely used at RF and microwave frequencies, especially when a large circuit pattern has to be formed. On the other hand, physical dimensions of etched elements (e.g., trace widths, gaps between traces) are less controllable compared to hard substrates. Therefore, creating certain high-frequency components (such as directional couplers and edge-coupled filters) can be challenging. The most common conductive materials utilized to form conductive layers are presented in Table 3.2. Gold metallization is typical for hard substrates while copper coating is standard with soft board materials. The thickness of copper, Table 3.2 Conductive Materials

Material

Electrical Resistivity, nOhm · m

Thermal Thermal Expansion Conductivity, Coefficient, Watts ·m−1 · K−1 μm · m−1 · K−1

Copper

17

400

17

Gold

22

318

14

Silver

16

429

19

Nickel

69

91

13

Synthesizer Construction

95

attached to the soft board, is historically specified in ounces per square foot and usually ranges from 1/4 oz (that corresponds to about 8-micron metal thickness) to 2 oz (70 μm). Thinner metallization allows better control of impedance-sensitive circuits (e.g., filters and directional couplers), while thicker coating is used for high power applications. The copper layer is usually covered by gold during the PCB fabrication process. This technique protects the copper from corroding and consequently reduces conductive loss. Silver is an alternative to gold that offers even less loss. However, it is quite sensitive to how the board is handled. A tiny nickel underlayer is normally placed under the gold layer to ensure good adhesion. While specifying the conductive layer’s thickness, proper attention should be paid to the skin effect. A small thickness of the upper gold layer may lead to microwave current penetration into a higher resistance nickel underlayer that contributes to higher loss. 3.1.4

Discontinuity Effects

A transmission line of proper impedance serves almost as well as an ideal connecting wire on a schematic diagram, but what happens when the transmission line steps in width or interconnects with other elements such as shown in Figure 3.8? An abrupt change in line geometry is called discontinuity. It distorts the uniform electromagnetic field present in the transmission line and generally results in a part of the traveling signal being reflected. A discontinuity essentially forms a parasitic element that affects circuit characteristics and therefore has to be taken into account. Basic discontinuity models (such as a connecting via, step, tee junction, cross, bend, and stub) are included in virtually all modern circuit simulators and are usually quite accurate. It is important to include all significant discontinuities into circuit analysis and choose appropriate models. 3.1.5

Coupling

Another problem that distinguishes transmission lines from ideal connecting wires is coupling. Coupling is the transfer of energy or signal from one circuit

Transmission line

Capacitor

Figure 3.8 An abrupt change in line geometry results in a part of the traveling signal being reflected.

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Frequency Synthesizers: Concept to Product

segment to another. It often occurs between long adjacent traces that run parallel to each other. Coupling is usually an unintended and undesired effect that adversely affects system performance. To minimize coupling, signal traces should be separated as much as possible. Ground strips between signal lines also help reduce coupling. However, coupling is not necessarily always a negative effect. There are a number of useful circuits that utilize coupling. A good example is a directional coupler that is often used in phase-lock-loop synthesizers to sample a signal into the PLL feedback path. A directional coupler is a four-port device that can be conveniently printed on a hard substrate or soft board as depicted in Figure 3.9. An RF signal, generated by a VCO, enters input port 1 and passes through the main line to port 2 with minimal loss, which depends on a coupling coefficient. A small portion of this signal couples into another line that is placed in close proximity and in parallel to the main line. Interestingly, the signal levels appearing on the coupled line ends are not equal. The coupler geometry is chosen in such a way that the majority of the transferred signal reaches port 3, called the coupled port. The signal at another end of the coupled line (port 4) is normally much smaller. This port is called the isolated port and is usually terminated with a 50-ohm resistor. The directional coupler is a fully symmetrical device—it exhibits the same directional features when the signal is applied to a different port. For example, undesired products of PLL dividers and the phase detector enter port 3 and mostly dissipate in the 50-ohm resistor located at port 4. Only a small portion of this signal couples into the upper line and appears at port 1. The coupled signal at port 2 (synthesizer output) is further attenuated by the coupler directivity. 3.1.6

Distributed and Lumped Elements

While drawing a schematic diagram, the elementary circuit components (such as resistors, capacitors, and inductors) are usually treated as ideal or lumped elements. We naturally assume that a resistor always behaves as a resistor at any from VCO

to RF output

1

2

3

4

to PLL

Figure 3.9 surface.

A directional coupler consists of two transmission lines printed on a substrate

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97

frequency regardless of its physical dimensions, where it is connected, and how it is oriented with respect to other components. This model works quite well at low frequencies, where the element dimensions are physically much smaller compared to the signal wavelength. However, as frequency increases, all the above-mentioned factors have to be taken into account. As a result, a “simple” resistor becomes a network formed from ideal lumped elements. Such a complex component is called a distributed element since its inductance, capacitance, and resistance are not concentrated in one spot but are spread through the component geometry. Distributed elements can also be created by forming a proper metal pattern on a substrate surface. These printed components range from a simple transmission line stub used as a tuning element to quite complex structures such as bandpass filters. Basic distributed element models are included with linear circuit simulators. However, complex planar and three-dimensional structures are better treated with electromagnetic simulators, which deal with the circuit geometry and produce much more accurate results compared to simplified lumpedelement models.

3.2 Chip-and-Wire Approach RF and microwave electronic circuits can be built using various techniques. The chip-and-wire approach is suitable for attaching and connecting unpackaged discrete devices or integrated circuits. A hard substrate (such as alumina) is used to create the required microwave structure (e.g., microstrip lines and distributed elements) on the substrate’s top surface while the backside is grounded. The substrate is usually attached to a metal carrier made from a material (such as Kovar, molybdenum, or tungsten copper) that is compatible with the thermal expansion characteristics of the utilized substrate. Kovar is a nickel-cobalt ferrous alloy that offers good characteristics and low cost. Molybdenum and tungsten copper, which is a composition of copper and tungsten particles, are more expensive, but provide better heat removal because of their high thermal conductivity. An unpackaged device called a die is attached directly to the substrate or to the carrier as shown in Figure 3.10. In the latter case, a thin metal sheet called a rib is placed under the die to bring the die and substrate surfaces to the same level. This reduces the length and consequently the inductance of connecting wires. The die can be attached with various techniques such as soldering, adhesive bonding (using an epoxy), or eutectic bonding (heating two materials to form an alloy composition). The attached chip is connected to the conductors printed on the substrate using gold or aluminum wires, called wirebonds. The assembled module (such as that shown in Figure 3.11) is placed into a metal enclosure and connects to other modules or external connectors. The technique

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Frequency Synthesizers: Concept to Product Substrate

Carrier

Die

Wirebond

Rib

Figure 3.10 An unpackaged device and alumina substrates are attached to a metal carrier then connected together with wirebonds.

Figure 3.11 A 2- to 22-GHz attenuator module built with the chip-and-wire technique. (Courtesy of Phase Matrix, Inc.)

offers excellent reliability and a smaller footprint as compared to the same device in a surface-mount package.

3.3 Printed Circuit Board While the chip-and-wire approach is attractive for simple, component-level circuits, the majority of frequency synthesizer designs are built using printed circuit

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boards. The PCB offers a much larger area for creating complex circuits and is also less expensive in high-volume production. A blank soft board material coated with thin copper foil (referred to as a copper-clad board) is utilized to form a required metallization pattern that includes traces, component pads, and ground planes. A typical high-frequency PCB design uses surface-mount components soldered flush to PCB pads. The components and connecting traces are preferably placed on the top of the board, while the bottom layer is used as a ground. This arrangement allows natural 50-ohm microstrip environment similar to hard substrate designs discussed in Section 3.2. The metal layers are traditionally tin-lead coated during the PCB fabrication process. This protects the copper from corrosion and also ensures good adhesion with solder. In highfrequency designs, a gold “flash” coating is preferable since it offers a very flat surface finish. Finally, some applications require RoHS-compliance, which aims to restrict certain dangerous substances such as lead, mercury, and cadmium. The components can also be mounted on both sides of a PCB to utilize the available space more efficiently. A multilayer board is used for more complex designs. Although it is generally more expensive, the multilayer approach offers extra freedom to route a complex circuit by running traces on the inner layers of the board. This is handy in situations where multiple traces have to cross each other. It also leads to more compact designs since the circuit components can be packed more tightly. The multilayer board is constructed as a “sandwich” made from individual boards where each layer is dedicated for specific signals as shown in Figure 3.12. For example, microstrip lines can be printed on the top surface of a relatively thin, high-frequency material (e.g., 8-mil RO4003C), while its backside is used as an RF ground. The bias, control lines, and other auxiliary signals are moved to the inner layers, which are formed on a less expensive, low-frequency material such as FR-4. The bottom side of the board is usually assigned as a DC ground. The board layers may have a different assignment based on particular design needs. More high-frequency pieces can be sandwiched to form a stripline environment inside the board structure required to route RF signals that cross each other. The overall board thickness must provide adequate mechanical strength RF RF Ground Control DC Bias DC Bias DC Ground

Figure 3.12

A multilayer PCB consists of several layers dedicated for specific signals.

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(62 mils is a popular number) for attaching circuit components as well as mounting the whole board assembly. Connections between individual board layers are provided using metalized via holes as depicted in Figure 3.13. There are three types of vias: standard, blind, and buried. Standard vias are drilled through the whole structure and can therefore connect all board layers. This arrangement is obviously redundant, since only two layers usually need connecting, and sometimes causes unnecessary interference between other layers. In contrast, blind vias do not go through the whole board but only connect an outside surface to one (or more) of the inner layers. This results in a more efficient use of space as well as less crosstalk. Buried vias only connect two (or more) inner layers and are not visible from the outside of the board (i.e., the via hole is completely “buried” inside the board). Although the blind and buried vias are more expensive, they are extremely useful for complex, high-density designs. A completed PCB sandwich is normally coated with a solder mask, which is a thin polymer layer placed over the PCB metallization pattern. The solder mask is typically green in color, although other colors are available. It surrounds component pads and prevents solder from bridging between components. The solder mask normally covers the whole PCB exposing only the areas to be soldered. However, it should be removed from certain high-frequency areas since it may introduce extra loss and change the characteristic impedance. The PCB is also silkscreened with component outlines, reference designators, and other information, which assists people in assembling and troubleshooting. A silkscreen is a special layer that looks like ink (usually white in color) placed over the solder mask. Sometimes it can be used in lieu of the solder mask; however, it is not the most preferable option since the silkscreen positioning is less accurate. The designed PCB is usually panelized as required by a specific manufacturing process. A panel is simply a large board containing many identical copies of the designed PCB. The fabricated PCB is preferably tested for electrical continuity as part of the PCB manufacturing process. Although it may result in Standard Via

Figure 3.13

Blind Via

Buried Via

Connections between PCB layers are provided using metalized via holes.

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101

a higher cost, this test is almost mandatory for multilayer boards. An inner layer short circuit is very hard (if at all possible) to fix and may require replacing of the whole PCB assembly. Once a PCB is fabricated, it is time to attach electronic components. This can be accomplished with three major techniques: hand, wave, and reflow soldering. Hand soldering is used for building small quantity prototypes as well as attaching some special components that cannot be done by other methods. Wave soldering is an automated process that involves loading components and placing the entire board into a bath of molten solder. The solder wets the exposed (i.e., not protected with a solder mask) metal areas creating a mechanical and electrical connection. The technique is simple and suitable for low-density designs. A proper solder mask is important to prevent bridging of component pins. Reflow soldering is the most widely used technique for attaching high-density surfacemount components. The unpopulated PCB is initially coated with a mask of solder paste over the component pads. Then the components are loaded and the whole assembly is heated in an oven. The solder paste melts, making all necessary joints. It should be noted that large metal areas (i.e., ground planes) work as a heat sink removing the heat. This may result in unreliable connections (often called dry or cold joints). Several short traces over the component pad may provide thermal relief and result in a more reliable connection. The completed assembly is inspected, packed into an electrostatically safe package, and delivered to a facility where it will be integrated into the final product.

3.4 Packaging A package is an essential part of any electronic design that provides electrical interface, environmental protection, electromagnetic shielding, mounting mechanism, and heat sinking. Although packaging techniques vary from IC surfacemount packages to large instrument boxes, we consider here a cavity-based metal enclosure as a typical example used in synthesizer module designs. 3.4.1

Electrical Interface

The synthesizer assembly is placed into a metal enclosure (also called housing), which is usually made from an aluminum alloy with a proper coating. The synthesizer delivers its output signal via an RF connector (such as SMA, K, and so forth), as shown in Figure 3.14. Certain effort is required to minimize discontinuity effects at the RF connector transition. For a chip-and-wire module or a single-layer board, the design is straightforward since the RF ground is in direct contact with the housing floor. In this case, the RF connector body is attached to the housing that ensures good grounding. An RF feedthrough may be placed between the connector socket and the signal trace. In this case, the RF connector

102

Frequency Synthesizers: Concept to Product RF connector RF signal pin PCB

Figure 3.14

RF connector interface example.

is field-replaceable, which is convenient if its repair is required. The feedthrough body is attached (soldered or epoxied) to the housing to form a 50-ohm coaxial line transition. The nonshielded pin length should be kept at minimum to reduce the line discontinuity. For a multilayer board design, however, the RF ground is in between the layers and is connected to the bottom layer through multiple via holes. This connection represents a relatively high inductance in the ground path that can affect the performance at microwave frequencies. A better grounding is achieved through the top layer (e.g., using an edge-mount connector shown in Figure 3.15) because of a shorter distance between the internal RF ground plane and connector body. From this point of view, the upper level material should be as thin as possible (e.g., 8-mil RO4003C), while other layers can be accommodated

Figure 3.15

Top layer metallization provides better grounding. (Courtesy of Phase Matrix, Inc.)

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103

using a thicker, lower-frequency material. Edge plating and coplanar waveguide transition are good solutions that help reduce discontinuity between the board structure and the RF connector. The transition has to be properly modeled to avoid signal mismatch and output power roll-off at high frequencies. Other interfaces (bias, control, reference) operate at much lower frequencies and usually represent no technological difficulties. 3.4.2

Environmental Protection

The metal enclosure provides necessary mechanical strength and therefore protects the electrical circuit from mechanical impact. It is completed (or sealed) with a metal cover that also protects the circuit from environmental contaminants such as dust, moisture, humidity, and salt spray. The cover should be in good mechanical contact with the housing body, which can be achieved through the various methods depicted in Figure 3.16. The simplest method to secure the cover is to put a number of screws around the perimeter of the cover. The cover can also be soldered or attached with a conductive epoxy to prevent formation of air gaps between the parts. A rubber ring is a good alternative that simplifies removal of the cover as required to repair the unit. However, the best (hermetically sealed) environmental protection is achieved by welding the cover to the housing using a laser welding technique. 3.4.3

Shielding

Electromagnetic shielding protects the electrical circuit from electromagnetic coupling to the external environment and vice versa. The metal enclosure, described above, usually provides adequate shielding since it naturally surrounds the circuit and therefore effectively blocks electromagnetic radiation. The level of protection depends on the housing material, its thickness, the shielded volume, air gaps, the frequency of electromagnetic fields, the coupling mechanism, and many other factors [12–14]. Shielding techniques vary based on applications and design features. A popular synthesizer construction example is shown in Figure 3.17. It consists of a PCB assembly sandwiched between metal shells that form the synthesizer’s housing. The structure is simple and provides reasonable shielding; however, some signal can leak through a gap between the metal shells. An edge-plated PCB with a ground strip between the shells (Figure 3.18) can significantly reduce this leakage. However, a full-metal enclosure described in Section 3.4.2 is obviously a better solution. Note that a metal cavity surrounding an electrical circuit acts as a resonator. Thus, the cavity should be designed carefully to avoid resonances and also ensure that waveguide modes are below the cutoff frequency. Coupling also occurs between internal components inside the housing itself. An inner cover works as a metal shell that isolates internal components

104

Frequency Synthesizers: Concept to Product Screws

Epoxy

Rubber ring

Laser welding

Figure 3.16 A cover should be properly attached to the housing to protect the electrical circuit from environmental contaminants.

Synthesizer Construction

105

PCB assembly Metal shells

Figure 3.17

A PCB assembly sandwiched between metal housing shells.

Edge plating

Figure 3.18

An edge-plated PCB ensures good grounding with metal shells.

as illustrated in Figure 3.19. Better isolation can be achieved by splitting the electrical circuit into separate blocks (such as digital control and RF boards) and confining them into fully isolated metal compartments as shown in Figure 3.20. The connection between the blocks can be established with special EMI filters that offer excellent signal suppression. The term EMI stands for electronagnetic interference and refers to signals interfering with a particular circuit or a full system. An EMI filter (also called a feedthrough) is a three-terminal device, which is available as a C, L, T, or Pi network as depicted in Figure 3.21. The C-type is the simplest and most common EMI filter that offers a much lower inductance between the signal line and ground than a regular surface-mount capacitor. This results in reliable, resonance-free signal suppression over a wide frequency range. The L-type filter includes an additional inductive element that results in better Inner cover

Figure 3.19

PCB assembly

An inner cover isolates internal components.

106

Frequency Synthesizers: Concept to Product EMI filter

PCB assemblies

Figure 3.20 Two separate boards are confined into isolated metal compartments and are connected with EMI filters. C type

L type

T type

Pi type

Figure 3.21

EMI filter types.

signal suppression. The T and Pi EMI filters consist of three elements and provide the highest level of signal suppression. EMI filters are available in different styles (e.g., threaded, solder-in, press-in) and are available from EMI Filter Company, Tusonix, Inc., and other manufacturers. 3.4.4

Mounting and Heat Sinking

A frequency synthesizer is often used as a component or module in a larger system. It can be mounted to a metal plate or chassis with mounting screws as shown in Figure 3.22. The number of screws and their size depends on the synthesizer’s dimensions and weight and should be adequate to provide necessary mechanical strength.

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107

Chassis

Figure 3.22

A frequency synthesizer is attached to a chassis with mounting screws.

Another concern is heat removal. A frequency synthesizer is a complex assembly that contains a number of active devices generating heat. Therefore, the synthesizer package and external chassis have to be in good thermal contact to provide heat sinking. This is usually achieved by reserving a sufficiently large contact surface between the synthesizer and the chassis. Alternatively, a fan can be used to generate airflow for effective heat removal.

References [1] Barret, R. M., “Microwave Printed Circuits—A Historical Survey,” IEEE Transactions on Microwave Theory and Techniques, Vol. 3, March 1955, pp. 1–9. [2] Wadell, B. C., Transmission Line Design Handbook, Norwood, MA: Artech House, 1991. [3] Lee, T. H., Planar Microwave Engineering. A Practical Guide to Theory, Measurements, and Circuits, New York: Cambridge University Press, 2004. [4] Bahl, I. J., and D. K. Trivedi, “A Designer’s Guide to Microstrip Line,” Microwaves, Vol. 16, May 1977, pp. 174–182. [5] Edwards, T. C., and M. B. Steer, Foundations of Interconnects and Microstrip Design, Third Edition, New York: John Wiley & Sons, 2001. [6] Gupta, K. C., et al., Microstrip Lines and Slotlines, 2nd ed., Norwood, MA: Artech House, 1996. [7] Howe, Jr., H., Stripline Circuit Design, Dedham, MA: Artech House, 1974. [8] Wen C. P., “Coplanar Waveguide: A Surface Strip Transmission Line Suitable for Nonreciprocal Gyromagnetic Device Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 17, December 1969, pp. 1087–1090. [9] Simons, R. N., Coplanar Waveguide Circuits, Components, and Systems, New York: John Wiley & Sons, 2001. [10] Maas, S. A., The RF and Microwave Circuit Design Cookbook, Norwood, MA: Artech House, 1998.

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[11] Ogawa, H., and A. Minagawa, “Uniplanar MIC Balanced Multiplier—A Proposed New Structure for MIC’s,” IEEE Transactions on Microwave Theory and Techniques, Vol. 35, December 1987, pp. 1363–1368. [12] Morrison, R., Grounding and Shielding Techniques in Instrumentation, New York: John Wiley & Sons, 1967. [13] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [14] Hemming, L. H., Architectural Electromagnetic Shedding Handbook: A Design and Specification Guide, New York: IEEE Press, 1992.

4 Design Process This chapter moves from general concepts to practical applications. A simple single-loop PLL example is used to demonstrate the most important aspects of the design process from the block diagram to production. This chapter begins by capturing and formulating design goals as formal specifications. A block diagram is created as a high-level pictorial model, which helps to understand the overall design concept. It is transformed into a schematic that shows all individual components and their connections. Component selection and circuit optimization are discussed in detail. The design is laid out and implemented on a printed circuit board. We also discuss how to bring the assembled board to life through step-by-step troubleshooting of its individual blocks. Finally, the circuit is refined, tested, and properly documented. Additional small changes may be required until the design develops into a stable product that can be released to production.

4.1 Specifications Specifications denote a set of requirements that have to be met by a product. These can be generated through market research identifying particular customer needs and market demands. Alternatively, the specifications can come from a customer, sometimes in a form of a wish list. The requirements are analyzed then gradually nailed down to a formal document that sets all parameters describing the product. As an example, let’s consider a customer who needs a frequency synthesizer that operates between 5 and 5.5 GHz and is used as a stimulus source for

109

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Frequency Synthesizers: Concept to Product

some experiments. The synthesizer’s output signal should be locked to an external 10-MHz reference provided by the customer. The synthesizer should come in a connectorized metal box and be programmed from a personal computer. Desired characteristics are summarized as follows: • Frequency range: 5.0–5.5 GHz; • Resolution: 1 MHz; • Tuning speed: 1 ms maximum; • Output power: 7 dBm minimum; • Spurs: −60 dBc maximum; • Harmonics: −30 dBc maximum; • Phase noise: −80 dBc/Hz at 10-kHz offset and −90 dBc/Hz at 100-kHz offset; • External reference: 10 MHz, square wave. Obviously, the specifications are not complete; however, we have enough information to start defining the synthesizer’s architecture and selecting its main components. Other parameters can be marked as TBD (to be determined), which gives us some flexibility at this stage, and then they can be further analyzed and negotiated.

4.2 Block Diagram A block diagram is a high-level pictorial model of a product that helps to convey the overall design concept. Taking a quick look at the parameters indicated above, one can conclude that the requirements are not difficult; a single-loop PLL should probably do the job. What components can be used? First, we need a VCO. Hittite’s HMC430LP4 seems to be an excellent candidate [1]. The part combines a negative-resistance active device, integrated resonator, varactor diode, and output buffer amplifier. It provides the desired frequency coverage (Figure 4.1) and is available in a low-cost, surface-mount package shown in Figure 4.2. The VCO is biased from a 3-V single-voltage DC supply and provides about 2-dBm typical output power across the entire frequency range. It generates a 5-GHz signal at approximately 1.5-V tuning voltage, which allows us to stay above 0-V rail at all operating conditions. The highest operating frequency of 5.5 GHz is set at 7.5V with a sufficient margin as well. We can also rely on the VCO’s free-running noise at 100-kHz frequency offset, which is better than −100 dBc/Hz. However, the phase noise at lower offsets looks marginal and therefore has to be controlled by a phase-lock loop.

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111

Figure 4.1 The HMC430LP4 VCO tunes between 5.0 and 5.5 GHz. (Courtesy of Hittite Microwave Corporation.)

Figure 4.2 The HMC430LP4 VCO is available in surface-mount form. (Courtesy of Hittite Microwave Corporation.)

Another critical component is a PLL IC that locks the VCO and suppresses its noise to a required level. Analog Devices’ ADF4106, described in Chapter 2, is a perfect choice. This part supports the desired operating frequency range and includes a digital phase-frequency detector with an integrated charge pump, both RF and reference dividers as well as lock detector circuitry [2–4]. All PLL parameters and functions are conveniently programmed through a built-in three-wire serial interface. Now we can draft a simplified block diagram as shown in Figure 4.3. It helps to quickly estimate some key design characteristics (e.g., phase noise, loop bandwidth, and tuning speed). The phase detector comparison frequency is obtained by dividing the external reference down to 1 MHz. The required division coefficient of 10 is provided by the reference divider. Since the required step size is 1 MHz, the RF divider coefficient should vary between 5,000 and 5,500. Note

112

Frequency Synthesizers: Concept to Product HMC430LP4 RF OUT VCO 5.0–5.5 GHz ADF4106 REF IN

÷R

÷N

10 MHz R = 10 N = 5,000–5,500 PFD Frequency = 1 MHz

Figure 4.3

Simplified block diagram.

that the prescaler maximum output frequency has to be limited to 325 MHz according to the ADF4106 datasheet. Therefore, the prescaler division coefficient must be set to 32 (5,500 MHz / 32 = 171.875 MHz < 325 MHz). Even if the VCO accidentally tunes to its highest possible frequency of 5.7 GHz (at a 10-V tuning voltage as indicated in the HMC430LP4 datasheet), the prescaler output is still below its allowable maximum (5,700 MHz / 32 = 178.125 MHz < 325 MHz). This guarantees that the ADF4106 divider limitations will not be violated at any VCO frequency. The prescaler division ratio can also be set to 64; however, the ratio of 16 will not satisfy the specified limit. Another parameter to check is the minimum contiguous division coefficient, which is equal to P(P − 1). In our case, the minimum division coefficient is 32 × 31 = 992 and supports the lowest operating frequency of 5,000 MHz. Thus, all operating conditions have been met, and the indicated part does support our frequency plan. The next step is to estimate PLL phase noise performance. According to the ADF4106 datasheet, the effective phase detector noise at 1-MHz comparison frequency is about −159 dBc/Hz. This noise is multiplied by the PLL at a rate of 20logN. Thus, the maximum degradation is about 75 dB for a 5.5-GHz output. Assuming that the PLL noise dominates, which means that the external reference noise is sufficiently low, we can estimate the RF output phase noise generated by the PLL itself at −84 dBc/Hz. Since the VCO free-running noise at 10-kHz frequency offset is worse, the PLL bandwidth should be set slightly above 10 kHz (let’s say, 20 kHz) for optimal phase noise performance. The switching time corresponding to this loop bandwidth is in the order of a few hundred microseconds (the exact number depends on the loop filter dynamic characteristics and will be determined later when we deal with the schematic). Thus, the phase noise and switching speed requirements seem to be met too. What else are we missing? The VCO tuning curve indicates that we need about 7.5V to steer the VCO to 5.5 GHz. However, the maximum voltage provided by the phase detector output is only 5.5V. Thus, an operational amplifier

Design Process

113

(such as AD820 manufactured by Analog Devices, Inc.) must be used to scale up the charge pump output. Moreover, we also need to boost the VCO RF output in order to get the desired output power. A number of parts can be used; Hittite’s HMC476MP86 gain block should work sufficiently well. It has about 11-dB gain and 11-dBm output power at 1-dB compression in our frequency range [5]. The amplifier is biased from a single 5-V DC supply with a minimal number of external components. A 6-dB resistive power splitter is added to the block diagram. A good block diagram also includes extra information (e.g., signal frequencies, power levels, and bias conditions) required to understand the circuit operation as illustrated in Figure 4.4. Let’s continue refining our block diagram. The RF output power appears marginal since some power will be lost in the output connector and internal traces. Note that we can save quite a bit of the energy we are losing in the 6-dB resistive splitter. Since the ADF4106 RF divider only needs a −10-dBm signal to operate (with a sufficient margin), unequal splitting can be used. In this case, only a small portion of the RF power is transferred into the PLL path that helps to balance the RF gain budget. A directional coupler is an even better choice since it provides isolation between the synthesizer output and PLL feedback path. This helps reduce undesired subharmonic products that are generated by the dividers and reflected back to the RF output. The coupler should be placed after the RF amplifier to avoid unnecessary amplification of these products. This results in better spurious characteristics as depicted in Figure 4.5. Note that the coupler can be printed on a PCB, which leads to an overall component count reduction. Further subharmonic rejection is achieved by putting a surface-mount highpass filter such as an HFCN-4600+ manufactured by Mini-Circuits. The filter passes the 5–5.5-GHz feedback signal to the RF divider suppressing signals below its cutoff frequency of 4.6 GHz as illustrated in Figure 4.6. In some cases, an additional RF amplifier may be inserted into the RF divider path to increase the isolation. After removing the resistive power splitter, we get more power in front of the amplifier, thus putting it in compression. This is not necessarily a bad result since it stabilizes the amplifier output level and therefore improves power flatness. Note, however, that keeping the amplifier oversaturated may affect its parameters (e.g., noise figure and input and output match) and also reduce the device’s lifetime. A small, fixed attenuator between the VCO and amplifier may be needed to keep the amplifier slightly compressed (but not oversaturated) and provide a better termination for the VCO output. It can also be used to adjust the output power level when necessary. Another potential problem is the output harmonics generated by the VCO and RF amplifier. The required specification of −30 dBc is handled by adding a lowpass filter at the amplifier output. The filter can be a purchased surfacemount component (such as an LFCN-6700+ from Mini-Circuits) or can be

Figure 4.4

5 dBm

10 MHz

DC

÷N

Gain = 3

DC

R = 10 N = 5,000–5,500 PFD Frequency = 1 MHz

÷R

Block diagram with more details.

REF IN

ADF4106 3V, 10 mA 5V, 0.4 mA

1.5–7.5V VCO

2 dBm

5.0–5.5 GHz

−4 dBm

5.0–5.5 GHz

HMC430LP4 3V, 27 mA

0.5–2.5V

AD820 10V, 0.8 mA

7 dBm

RF OUT 5.0–5.5 GHz Gain = 11 dB P-1 dB = 11 dBm −6 dB

−4 dBm

HMC476MP86 5V, 35 mA

114 Frequency Synthesizers: Concept to Product

Design Process

115

0 dBm Δ = −60 dBc −60 dBm

Signal = 0 dBm

Spur = −30 dBm

Coupling = −15 dB Directivity = 15 dB

10 dBm Δ = −70 dBc Signal = 10 dBm

Spur = −30 dBm

Figure 4.5

−60 dBm

Coupling = −15 dB Directivity = 15 dB

Coupling at the amplifier output results in lower spurious levels.

5.0–5.5 GHz

Fcut = 4.6 GHz

Figure 4.6

A highpass filter provides additional attenuation for subharmonic products.

printed on the board. Using the LFCN-6700+ part may be preferable at the indicated frequencies since it needs a smaller space compared to a printed filter. The measured insertion loss of the LFCN-6700+ filter is presented in Figure 4.7. The part offers low insertion loss between 5 and 5.5 GHz (less than 1 dB) while providing good rejection for the second and third harmonics. Finally, our block diagram is refined as shown in Figure 4.8. Now it is a good time to contact the customer again to discuss the characteristics we can potentially achieve (some margin should be added, of course) and clarify other parameters such as external reference phase noise and DC supply requirements.

116

Frequency Synthesizers: Concept to Product LFNC-6700+ 12 S21

dB 0 −5 −10 −15 −20

4

−25

3

−30 −35

6

−40 −45 −50

5 Start: 1.000000 GHz

Mkr Trace X-Axis

Figure 4.7 jection.

Stop: 18.000000 GHz Value

1

S21

5.000000 GHz

−0.4917 dB

2

S21

5.500000 GHz

−0.5567 dB

3

S21

10.000000 GHz

−32.1087 dB

4

S21

11.000000 GHz

−28.7406 dB

5

S21

15.000000 GHz

−55.6407 dB

6

S21

16.500000 GHz

−40.7936 dB

Notes

The LFCN-6700+ lowpass filter provides low insertion loss and good harmonic re-

Depending on the project complexity, the block diagram may need a formal design review to identify all weak places we may have overlooked. However, for a simple synthesizer design, this can be done after completing a schematic.

4.3 Schematic Armed with the clear design requirements and a block diagram, it is time to step into the schematic implementation phase. In practice, the process is iterative since the block diagram (and even design goals) may need adjusting. A schematic is a detailed circuit diagram that shows all individual components as graphic symbols as well as connections between the components. It is created with specialized software (e.g., OrCAD) that allows creating a library of component symbols for use in schematic entry. In contrast to the block diagram, the schematic represents an exact model of the desired product; thus, all the details (such as component values) should be thoroughly checked and optimized. The schematic

Figure 4.8

Final block diagram.

Design Process 117

118

Frequency Synthesizers: Concept to Product

drawing should identify each component by its reference designator as it will eventually relate to the assembly drawing and bill of materials. A simplified schematic, shown in Figure 4.9, represents the block diagram indicated above and serves as a starting point. The RF signal is generated by the HMC430LP4 VCO (U3), amplified by the HMC476MP86 gain block (U4), filtered by the LFCN-6700+ lowpass filter (A3), and delivered to the output SMA connector (J2). A 2-dB attenuator (A1) is placed between the VCO and RF amplifier. The part is A-0402WA-C-02dB surface-mount, thin-film attenuator manufactured by International Manufacturing Services, Inc. A portion of the RF signal is fed back to the ADF4106 PLL IC (U1) through a directional coupler, which is printed on the PCB, and the HFCN-4600+ highpass filter (A2). The ADF4106 IC is the heart of the design that provides all necessary PLL functions as described above. It accepts an external reference signal, coming from another SMA connector marked as J1. The RF feedback signal is delivered to the ADF4106 RF differential input through the C4 DC blocking capacitor. The IC is used in a single-ended configuration; thus, the other input is grounded via the C1 capacitor. The RF and reference signals are conditioned, divided down, and compared by a phase detector that connects to the external loop filter through a built-in charge pump. The charge pump sources or sinks current in proportion to the phase difference between the signals in front of the phase detector. The charge pump current is set by the R1 resistor at 5 mA and can be further adjusted (programmed) via the three-wire serial interface. The charge pump drives a lowpass filter formed by the C2 and R2-C3 components. The filter transforms the current pulses from the charge pump into a voltage that is amplified by the AD820 operational amplifier (U2). The amplifier gain is set to three with the R3 and R4 resistors to ensure sufficient drive level on the VCO tuning port. When properly programmed, the ADF4106 steers the VCO to a desired frequency and monitors its lock at the MUXOUT port connected to the J3 output connector. The connector also caries DC supply voltages delivered to all necessary bias points. Although this circuit will probably work (after some manipulations), it is far from perfect. What can be improved? Let’s examine the RF path first. Note that the VCO includes a DC blocking capacitor at its output; thus, no external capacitor is required. Similarly, the HFCN-4600+ filter provides DC blocking functions. Therefore, the C4 and C11 capacitors are redundant and may be eliminated. However, the HMC476MP86 gain block does need the C12 and C13 capacitors on both sides as indicated. The next part to focus on is the PLL IC. The ADF4106 reference input exhibits very high impedance and should work well with square-wave, 3-V CMOS signals. Other impedances can be set by adding a shunt resistor and DC blocking capacitors as depicted in Figure 4.10. Note that the minimum slew rate of 50 V/μs is required if the input reference frequency is less than 20 MHz. Thus,

Figure 4.9

Schematic start point.

Design Process 119

120

Frequency Synthesizers: Concept to Product +3V

High impedance

50 Ohm

0.01uF U1

J1

0.01uF

ADF4106BCPZ 8 12 13 14

2

SMA 0 01uF 1 REF IN

49.9

5 4

22pF

Figure 4.10

9 10 2 3 21

REF IN CLK DATA LE RF INA RF INB

AVDD AVDD DVDD DVDD VP RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

6 7 16 17 18 19 15 11 20 1

The reference input is reconfigured for a 50-ohm environment.

a sine-to-square wave converter should be added if a low-frequency, sine-wave, reference signal is used. A simple sine-to-square wave converter can be built by placing a resistor (e.g., 100 kOhm) across a CMOS inverting gate as illustrated in Figure 4.11. Note that the converter can contribute to the synthesizer’s output phase noise. Obviously, faster logic is preferable since the noise (jitter) is mainly generated in the transition region where the signal crosses the logic threshold. Better performance can be achieved using a special high-speed voltage comparator such as the LT1719 manufactured by Linear Technology Corporation. A 50-ohm resistor is incorporated as shown in Figure 4.12 to provide 50-ohm input impedance with a single DC supply. However, for a square-wave signal, no converter is needed. The ADF4106 RF input circuit match is not perfect either; an additional matching network is generally needed for a better match. However, a large RF input sensitivity window masks this imperfectness; hence, a direct connection is possible. Digital control lines are inherently less demanding. Nevertheless, it is a good idea to add protective resistors to the three-wire serial interface (CLK, DATA, and LE lines) as shown in Figure 4.13. The resistors limit the input current in case the IC inputs are driven by higher voltages. Similarly, a current-limiting

Figure 4.11 A sine-to-square wave converter is built by placing a resistor across a CMOS inverting gate.

Design Process

121

+5V

0.1uF

0.1uF

−

LT1719CS6 5 ShutD

4

5.11K

+

1

2

49.9

3

6

0.01uF

5.11K

A high-speed voltage comparator provides sine-to-square wave conversion func-

Figure 4.12 tion.

+3V

0.01uF U1

ADF4106BCPZ 8 12 13 14 5 4

22pF

9 10 2 3 21

REF IN CLK DATA LE

AVDD AVDD DVDD DVDD VP

RF INA RF INB

RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

J3 1 CLK

100

2 DATA

100

3 LE

100

4 LOCK

100

5 +3V

+3V

6 +5V

+5V

7 +10V

+10V

8

+ 2X4

Figure 4.13

10uF 16V

+

10uF 16V

+

10uF 16V

Current-limiting resistors are added to protect IC ports.

6 7 16 17 18 19 15 11 20 1

122

Frequency Synthesizers: Concept to Product

resistor is added to the MUXOUT output to prevent it from being accidentally shorted. Furthermore, small value capacitors can be added to form lowpass filters on the control signal lines. These filters help to suppress undesired products traveling between the synthesizer and a host controller. However, the RC constants should be properly calculated to avoid possible disturbance of the control signal waveforms. The major area of optimization of any PLL synthesizer is the loop filter. There are a number of programs that can simulate and even synthesize a PLL circuit with desired characteristics. Analog Devices’ ADIsimPLL is a simple yet very effective tool that can automatically synthesize loop filter values. The program allows selecting a specific loop filter topology and entering desired characteristics. Then it performs all necessary calculations and displays a synthesized filter schematic and performance plots. In our example, we started from the simplest configuration and calculated all the values for a 20-kHz loop bandwidth and 45° phase margin. As a rule of thumb, the loop filter bandwidth should be preferably kept at 1/10 (or lower) of the phase detector comparison frequency to provide sufficient rejection for reference spurs. The reference spurs are caused by parasitic phase detector leakages as well as narrow pulses (called antibacklash pulses) inserted intentionally to reduce phase detector dead-zone effects. Since our comparison frequency is 1 MHz, this condition is easily met. However, this filter is probably not the best since the operational amplifier equally boosts both the DC voltage and AC noise. Moreover, in order to steer the VCO between 5 and 5.5 GHz, the operational amplifier has to output the voltage between 1.5 and 7.5V. This corresponds to 0.5 to 2.5V at the charge pump output. Note that ADF4106 exhibits elevated spurs at low charge pump output voltages with a pronounced peak at about 0.75V (as indicated in the ADF4106 datasheet). It is possible to reset the operational amplifier gain to 1.5 that would require the charge pump output between 1 and 5V. This would improve the spurious characteristics at 5 GHz, but would make it worse at the high end. This is because the ADF4106 exhibits elevated spurs at high output voltages as well (with a local peak at 4.3V). In other words, the ADF4106 does not like working at either a low or a high rail. Fortunately, there are many other types of loop filters; specific configurations and design details are described in [6–17]. An integrator configuration, shown in Figure 4.14, seems to be a better choice. The R2, R5, C3 components form a desired gain profile of the operational amplifier. The C2 capacitor is kept at the charge pump output. It smoothes the charge pump pulses to ease the slew rate requirements for the operational amplifier. The C4 capacitor is introduced to reduce the operational amplifier gain at high frequencies; it can also be placed across R5 if desired. The circuit also needs a reference voltage (which is usually half of the charge pump DC supply voltage) delivered through a simple resistive divider (formed by the R3 and R4 resistors). A shunt capacitor C5 is needed to

Figure 4.14

DGND DGND AGND AGND CASE

RF INA RF INB

CLK DATA LE

REF IN

An integrator-based loop filter.

22pF

C1

9 10 2 3 21

5 4

12 13 14

8

U1

CP CPGND

CE

MUXOUT

RSET

AVDD AVDD DVDD DVDD VP

ADF4106BCPZ

20 1

11

15

19

6 7 16 17 18

+3V

C7

5.11K

R1

0.01uF

C2

C8

R3

0.01uF

10.0K

R4

R2

10.0K

+5V

3

2

R5

+

-

1.0uF

C5

C4

4

7

C9

V-

OUT

6

AD820

U2

C3

0.01uF

V+

+10V

C6

R6

Design Process 123

124

Frequency Synthesizers: Concept to Product

reduce the noise contribution of the external DC supply as well as the resistors themselves. Note that in steady state (i.e., when the VCO is locked), both amplifier inputs should be equal. For example, if we set its reference voltage to 2.5V, the other input will be kept at the same level. Therefore, the charge pump output will operate at 2.5V or, in other words, right in the middle of its operating range. This corresponds to the best spurious performance at any given frequency across the entire operating range. Note that the integrator introduces a signal inversion, which can be taken into account by changing the phase detector polarity to negative via the IC control interface. Operational amplifier selection is an important consideration in the loop filter design. Low input voltage and current noise are crucial characteristics that directly affect the PLL noise performance. The input bias current should be kept at a minimum since it contributes to leakage-induced spurs. High DC supply voltage and rail-to-rail output are also valuable features that help to steer the VCO within required limits and avoid negative bias. Rail-to-rail input may also be advantageous if a low-voltage charge pump output is used. High slew rate and wide bandwidth are usually desired characteristics as well, especially for wideband PLL applications. Low slew rate may slow down the operational amplifier reaction on the charge pump pulses and therefore result in increased spurious levels. Another concern is the operational amplifier output current capabilities, which may be insufficient in certain cases. Let’s assume that we want to jump to a frequency that induces a large difference between the operational amplifier input and output voltages. Note that the instantaneous peak current may exceed the driving capabilities of the utilized operational amplifier. The amplifier will exhibit current limiting that affects PLL dynamic characteristics and may lead to significant tuning speed degradation. Analog Devices’ AD8675 seems to be a better choice for our particular design since the part provides significantly lower input voltage noise compared to AD820. The operational amplifier is connected to the VCO tuning port through the R6 and C6 components that form a lowpass filter providing additional attenuation for the PLL broadband noise and reference spurs. However, this can also contribute to phase noise degradation caused by the thermal noise generated by the R6 resistor itself. The resistor noise voltage is described by Vn = 4RkT Δf

where R = resistor value k = Boltzmann’s constant (equal to 1.38 × 10−23 J/K) T = absolute temperature

(4.1)

Design Process

125

Δf = bandwidth The formula (4.1) can be rewritten to describe voltage noise density Hz . For example, the voltage noise density for a 1-kOhm resistor at a temperature of 300K, which is about 27°C, is calculated to 4.07 nV Hz . Assuming that the PLL loop is opened, this voltage modulates the VCO and appears as phase noise at its output described by vn = 4RkT calculated in V

 = 20 log

vn K V

(4.2)

2 fm

where νn = voltage noise density KV = VCO tuning sensitivity fm = offset frequency In our case, the VCO maximum tuning sensitivity is 150 MHz/V, which results in about −93 dBc/Hz phase noise at 20 kHz offset. Thus, selecting R6 at 1 kOhm or lower does not significantly affect our phase noise specification

+3V

+5V

+10V

C7

C8

0.01uF

C9

0.01uF

0.01uF

U1

ADF4106BCPZ 8 12 13 14 5 4

C1

22pF

9 10 2 3 21

REF IN CLK DATA LE RF INA RF INB

AVDD AVDD DVDD DVDD VP RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

6 7 16 17 18

C4

19 R5 15 11

R1

C3

R3

10 0K

5.11K

R2 20 1

2

-

7

C2

V+

R6 6

OUT 3

+

4

V-

C6

L1

U2

AD820

R4

10 0K

C5

1.0uF

C10

Figure 4.15 An LC-filter provides considerable rejection for the PLL reference spurs with minimal phase margin disturbance.

126

Frequency Synthesizers: Concept to Product

outside the PLL bandwidth. At lower offsets, the phase-lock loop suppresses the resistor noise (assuming the loop has enough gain). In general, this exercise should be done for all noise sources within the loop filter, including the operational amplifier, and compared to the noise target. Note that the R6-C6 filter provides additional attenuation for both spurs and broadband noise above its cutoff frequency. However, caution is required since these elements contribute to the loop filter phase margin. An excellent solution is to utilize a bandstop filter formed by the L1 and C10 components as depicted in Figure 4.15. The filter is tuned to the phase detector comparison frequency and provides considerable rejection for the PLL reference spurs with minimal phase margin disturbance. However, in our case this measure seems to be excessive. Note that every PLL component, including every single resistor, is critical and has to be carefully optimized based on particular design goals. Optimization is a complex process and all decisions are made on a case-by-case basis. Keeping all this in mind, let’s reconfigure our loop filter as shown in Figure 4.16 and move forward with optimization. Although the 45° phase margin provides a good trade-off between stability, noise picking, and tuning speed, a better (flatter) noise profile can be achieved by increasing the phase margin to higher numbers. The penalty is a slower tuning speed; however, this does not seem to be a problem since our requirements are not too demanding (1 ms). Thus, a phase margin of 65° is used for a flatter phase noise profile. Note that we made all calculations for the midband frequency of 5.25 GHz; at other frequencies, the loop bandwidth may change. This is because both RF divider division ratio and VCO tuning sensitivity change with frequency. In order to offset these effects, the nominal charge pump current is decreased to 2.5 mA. This allows adjusting the charge pump current (reducing at lower frequencies and increasing at higher frequencies) to keep the PLL filter bandwidth constant across the entire operating frequency range. The calculated phase noise behavior is shown in Figure 4.17. The switching time for 10° phase error is estimated to be less than 400 microseconds as illustrated in Figure 4.18. A separate subject is how to indicate that the synthesizer is in lock. The circuit carrying this function is called a lock detector. There are various lock detector schemes described in more detail in Chapter 5. However, in our case the ADF4106 itself does the job. It includes all necessary circuits and provides two modes: analog lock detection and digital lock detection. The digital lock detector determines the phase error at the phase detector inputs. If the phase error on five or more consecutive cycles is less than 15 nanoseconds, it considers the PLL to be in lock and outputs a logic high signal. If the phase error exceeds 30 nanoseconds on any subsequent phase detector cycle, it switches the output to logic low indicating an out-of-lock state. The IC allows controlling the lock detector sensitivity by programming the number of cycles that are counted before the lock is determined. An LED (light-emitting diode) can be added as shown

Figure 4.16

DGND DGND AGND AGND CASE

RF INA RF INB

CLK DATA LE

REF IN

RSET

AVDD AVDD DVDD DVDD VP

CP CPGND

CE

MUXOUT

A new loop filter configuration.

C1 22 pF

9 10 2 3 21

5 4

12 13 14

8

U1 ADF4106BCPZ

20 1

11

15

19

6 7 16 17 18

+3V

R1 5.11K

C7 0.01 uF

820 pF

C2

R3 10.0K

C8 0.01 uF

R4 10.0K

R2 221

+5V

C5 1.0 uF

3

2

R5 5.11K

C4 100 pF

+

-

4

7

V-

OUT

6

U2 AD8675

C3 6800 pF

C9 0.01 uF

V+

+10V

R6 1K

C6 820 pF

Design Process 127

128

Frequency Synthesizers: Concept to Product -40 -50 -60

Phase Noise (dBc/Hz)

-70 -80 -90 −100 −110 −120 −130 −140 −150 −160 −170 −180 100

Phase Error, degree

Figure 4.17

1,000

10,000 100,000 Offset Frequency (Hz)

1,000,000

Calculated phase noise profile at 5.25 GHz.

50 40 30 20 10 0 −10 −20 −30 −40 −50 0

100

200

300

400

500

600

700

800

900

1000

Time, uSec

Figure 4.18

PLL timing characteristics.

in Figure 4.19 to visually indicate the phase lock state if desired. A low-current LED should be used to prevent the MUXOUT port from overloading. Analog lock detection is realized by connecting the internal up and down phase detector outputs to a built-in NOR-gate. The NOR-gate has an open drain output requiring an external pull-up resistor. When the PLL is in lock,

Design Process

129

+3V C2

0.01uF U1

ADF4106BCPZ 8 12 13 14 5 4 9 10 2 3 21

REF IN CLK DATA LE RF INA RF INB

AVDD AVDD DVDD DVDD VP RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

6 7 16 17 18 19 R1

LOCK

15 11 20 1

R2 D1

Figure 4.19

An LED indicator visualizes the phase lock state.

the NOR-gate ideally generates a logic high output. However, this output is disturbed by antibacklash pulses. A simple lowpass filter can be used to remove these pulses as depicted in Figure 4.20. Further details related to the operation of the lock detector are given in the corresponding Analog Devices’ application note [4]. For our synthesizer we will utilize the digital lock detection mode by programming the ADF4106 MUXOUT output. The output is set to 3V when the synthesizer is in lock; otherwise, the MUXOUT switches to ground. A very important, but often overlooked, area of any frequency synthesizer design is the DC bias supply. It should deliver clean and stable voltages to the synthesizer’s components. Note that the current schematic requires three properly regulated and filtered DC voltages. Can we rely on the external bias? We have to specify the DC supply requirements and ask our customer to provide the necessary voltages. Alternatively, voltage regulators can be placed on the synthesizer board. It is recommended that the voltage regulators have good ripple rejection to reduce AM noise and spurs from the external world. Another concern is how to isolate all internal bias points to prevent undesired signal leakages and interference between individual components through their bias lines. A simple solution is to include an LC lowpass filter to suppress a

130

Frequency Synthesizers: Concept to Product +3V

+5V

C2

C3

0.01uF

0.01uF

U1

ADF4106BCPZ 8 12 13 14 5 4 9 10 2 3 21

Figure 4.20

REF IN CLK DATA LE RF INA RF INB

AVDD AVDD DVDD DVDD VP RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

6 7 16 17 18 R2 19

LOCK

R1 15 11

C1

20 1

Analog lock detector output.

high-frequency signal. Although an inductor can be used, a ferrite bead (as can be found in the BLM18H series manufactured by Murata Manufacturing Co., Ltd.) is a better choice. The inductor is normally utilized in a resonant circuit where a high Q-factor is required. In contrast, the ferrite bead demonstrates lowQ resistive loss over a wide range of frequencies. The bead is terminated with a capacitor, which is mounted as close as possible to an active component bias point as shown in Figure 4.21. Low ESR (equivalent series resistance) capacitors are preferred to ensure good AC grounding. Moreover, a combination of two (or more) capacitors is used at some locations where a good termination over a wide frequency range is crucial. For example, a relatively high value of 0.1 μF is utilized to minimize voltage ripple and low frequency noise while a 100-pF capacitor delivers a better, resonance-free performance at microwave frequencies. Finally, our schematic is transformed as shown in Figure 4.22. All reference designators are reannotated. The schematic should be carefully examined to catch possible corner cases and to ensure that all components are used within their specified operating conditions. This includes both active devices and passive components such as resistors and capacitors. For example, DC power, dissipated on R12 resistor, is about 69 mW. A 0805-sise resistor is recommended in this specific place while 0402-size resistors and capacitors are preferred in all other locations because of their smaller size and better RF characteristics. It is

Design Process

131 +3V

BEAD 0.1uF U1

100pF

ADF4106BCPZ 8 12 13 14 5 4 9 10 2 3 21

Figure 4.21 bias lines.

REF IN CLK DATA LE RF INA RF INB

AVDD AVDD DVDD DVDD VP RSET MUXOUT

DGND DGND AGND AGND CASE

CE CP CPGND

6 7 16 17 18 19 15 11 20 1

Internal bias points should be properly isolated to prevent signal leakages through

not a bad idea to reserve large pads under resistor terminals for better heat sinking. Also ensure that the maximum voltage ratings for the utilized capacitors are adequate. It is a good idea to add a margin (the process is called derating) in some places where the voltages can potentially exceed expected numbers. Note that C4 voltage rating has changed to 20V to reduce the risk of damage by an external voltage. It is also important to use high-quality capacitors in the loop filter to prevent piezoelectric effects manifesting themselves as sudden, short-term frequency drifts referred to as phase hits. Dielectric type has a noticeable effect on lock time too; thin-film and NPO types are recommended. Note that some of our measures are probably excessive while other areas can be further improved. Moreover, in many cases the synthesizer design is also governed by the cost of available components. Thus, the designer’s experience and intuition are probably the most important factors in the synthesizer development equation. Getting someone to check your design may sound unnecessary, but it is a very vital step. No matter how experienced you are, it is likely there will be something you overlooked. Thus, the schematic design is usually completed with a formal design review that ensures confidence to move to the next stage.

SMA

8

7 +10V

6 +5V

5 +3V

4 LOCK

3 LE

2 DATA

1 CLK

1

100

100

R4

R5

10uF 20V

+

10uF 16V

C5

+

C3

10uF 16V

C6

22pF

Final schematic.

+

100

R3

C4

100

0.01uF

C2

R2

49.9

R1

0.01uF

C1

Figure 4.22

2X4

J3

REF IN

J1

2

8

+3V

DGND DGND AGND AGND CASE

RF INA RF INB

CLK DATA LE

REF IN

+10V

C8

CP CPGND

CE

MUXOUT

RSET

20 1

11

15

19

5.11K

R6 R8

R9

10.0K

820pF

C10

221

R7

10.0K -

+

1.0uF

C12

3

2

5.11K

R10

4

7

100pF

C13

C11

0.1uF

C9

0.1uF

100pF

6 7 16 17 18

FB3

BLM18H 1000

FB2

BLM18H 1000

C7

0.1uF

AVDD AVDD DVDD DVDD VP

ADF4106BCPZ

+5V

9 10 2 3 21

5 4

12 13 14

U1

FB1

FB4

6

C16

1K

R11

AD8675 820pF

U2

V-

OUT

V+

6800pF

C15

0.1uF

C14

BLM18H 1000

22

C17

Vtune

100pF

+3V

20 Vcc

BLM18H 1000

GND 15

FB5

RFout

16

U3 HMC430LP4

0.1uF

C18

BLM18H 1000

BASE 25

+10V

1

A-0402WA-C-02dB

A1

C19

22pF

R12

100pF

C20

56.2

+5V

3

3

HFCN-4600+

A2

1

HMC476MP86

U4

2 4 2 4 5 6

C21

22pF

C22

6.8nH

L1

0.1uF

COUPLER 1

SMA

49.9

R13

RF OUT

J2

LFCN-6700+ 2 1

A3

3

+5V

4

+3V

2

132 Frequency Synthesizers: Concept to Product

Design Process

133

4.4 Board Layout Once the schematic has been refined, it is time to turn it into a printed circuit board. The PCB is the physical form of the circuit; thus, all connections are derived from the schematic. There are many computer-aided PCB design packages tied to a schematic. Most of the job is performed automatically; however, the best results for high-frequency designs are still achieved with a certain amount of manual placement and routing in order to control various signal interaction effects. The first step in the PCB layout process is to establish the board outline as well as critical dimensions such as mounting hole locations. These dimensions can simply be a part of the mechanical specifications. Alternatively, the design goal can be to minimize the overall board size. Once all critical dimensions and component footprints are determined, component placement begins. This is a very critical step that requires a lot of attention. The process is not straightforward and often depends on the intuition of a particular PCB designer. The best way to begin is just to drop all the parts onto the screen. This gives a good indication of whether or not the parts can fit onto the available space. If the board size is not sufficient, you may need to go back and reevaluate mechanical requirements or even modify your schematic. A possible alternative is to place components on both sides of a PCB if the mechanical design permits this. Assuming we have enough room, the next question is where to place the components. A good tactic is to break the schematic into functional blocks and divide the board space accordingly. The process is very similar to floor planning in a building. Then we start placing components within the defined areas, keeping in mind that ideally they should be lined up as they appear on the schematic. However, all components and building blocks must be treated individually on a case-by-cases basis. For example, adjacent inductors preferably should be placed perpendicularly with respect to each other. This arrangement reduces magnetic coupling between the inductors. Note that this is only one example as there are probably many different places that require the designer’s attention. Once you are satisfied with the placement of the components, you can start routing connections between components. Autorouting may be used first to get an idea of how the parts are connected. However, a certain amount of manual work is required since autorouting may overlook undesired signal interference effects. Both capacitive and inductive crosstalk occurs between long traces that run parallel. Interference is proportional to the length of the traces, operating frequency, and signal amplitude and is inversely proportional to the distance between traces. A grounded metal strip between traces may help to reduce crosstalk. However, do not leave any metal areas unconnected since they may work as resonators creating unexpected spikes in the frequency domain. As a rule of thumb, all unused areas should be grounded.

134

Frequency Synthesizers: Concept to Product

Similar to the schematic, the final layout has to be carefully checked. Most PCB design software packages have a very good set of design rule checkers. However, a manual check is highly recommended as well. This is done by comparing every single connection on the board against the schematic. Highlight each line on the schematic as you complete it. When you are finished, there should be no electrical connection left that is not highlighted. It may seem excessive (and even irritating) to manually check each connection, but it will give you confidence that the board is electrically and physically correct. Eventually, a fabrication drawing and Gerber files are created and sent to a PCB manufacturing facility. A fabrication drawing is the governing document that defines all details such as board dimensions, tolerances, hole sizes, materials, layers, and plating. Gerber files contain all necessary data in electronic form to support the PCB fabrication process.

4.5 Assembly Once a PCB has been fabricated (Figure 4.23), it is time to build a whole module. The board assembly can be done in the same facility or sent out to a specialized manufacturing company. In both cases, a complete component kit and supporting documents are required to initiate the assembly process. An assembly drawing indicates the proper orientation of the PCB and individual components, shows where the components are placed, and identifies them by reference designators as shown in Figure 4.24. There may be additional notes indicating

Figure 4.23

Fabricated PCB. (Courtesy of Phase Matrix, Inc.)

Design Process

P/N

Figure 4.24 tors.

135

Rev

An assembly drawing identifies all individual components by reference designa-

special requirements and assembly procedures that are not governed by, or are more restrictive than, regular applicable standards. The assembly drawing does not need to indicate detailed dimensions for the positioning of the individual components. This information is created by the PCB CAD software and is sent electronically as a “pick-and-place” file. The assembly drawing is accompanied by a part list referred to as a bill of materials. The bill of materials (BOM) defines all the components used in the assembly via reference designators, specifying them by part number. An assembly drawing, BOM, and all necessary electronic files are usually created in the PCB layout stage using the same software package. This ensures design integrity and minimizes possible errors. A manufacturing company usually performs its own analysis for all supplied materials and data. Once the completeness of the component kit and supporting documents has been verified, the assembling process begins and the board is eventually assembled (Figure 4.25).

4.6 Mechanical Design The assembled board is placed into a metal enclosure or housing, which is an essential part of the synthesizer design. It accommodates the PCB assembly and provides electrical shielding. The housing also works as a heat sink to absorb and dissipate heat generated by the active devices. Thus, proper grounding and

136

Figure 4.25

Frequency Synthesizers: Concept to Product

Assembled board. (Courtesy of Phase Matrix, Inc.)

good thermal contact are crucial factors in the mechanical design. Note that the enclosure provides not only mechanical and electrical support but also contributes to product attractiveness. Attention to visual appearance is an important consideration. Mechanical design starts with the defining of outline dimensions then gradually moves to internal details. The process is iterative since the housing structure is determined by PCB shape and vice versa. Drafting has historically been a two-dimensional process, but computer-aided design programs (such as AutoCAD and SolidWorks) now allow the designer to work in three dimensions. The files generated by the CAD programs can be submitted electronically to housing manufactures, thus speeding up programming of manufacturing machines. However, the main output is a formal mechanical drawing that shows all the dimensions, tolerances, utilized materials, coating, and other pertinent information necessary to manufacture a part. The mechanical drawing becomes a governing document that controls the manufacturing process.

4.7 Control Software To program the output frequency and other parameters, synthesizers require a control mechanism that can be implemented in many different ways depending on a particular application. The synthesizer is usually controlled by sending certain commands that set output frequency, power level, and other parameters. This requires a CPU or microcontroller internal to the synthesizer to perform a

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137

“handshake” or translation functions. A special program called firmware resides in the synthesizer’s memory and coordinates receiving an external command, performing all necessary calculations, and programming individual devices inside the synthesizer. Developing firmware for complex microwave synthesizers can be a challenging task and is usually developed by a separate team. In our case, no internal controller is required since the controlling program resides in an outside computer. The computer communicates with the synthesizer via a simple three-wire serial interface, which is implemented inside the ADF4106 IC. The IC includes a 24-bit input shift register that receives incoming data bit-by-bit on each rising edge of the clock signal. The received 24-bit controlling word is then transferred from the shift register to one of four latches on the rising edge of the LE (load enable) signal. The desired latch is chosen by setting two control bits in the shift register. The LE signal carries essentially the same function as the slave select signal does in a typical SPI interface. The only difference is that the three-wire interface does not allow reading the information back from the PLL IC. The controlling algorithm and all bit definitions are well documented in the ADF4106 datasheet [2]. Initially, all four latches are programmed (initialized) by sending four 24-bit words to set up PLL functions and constants as follows: • Prescaler division coefficient, P = 32; • RF divider division coefficient, N = 5,250 (A = 2, B = 164, P = 32, N = PB + A); • Reference divider division coefficient, R = 10; • Charge pump current = 2.5 mA; • Phase detector polarity = Negative; • MUXOUT = Digital lock detect. The synthesizer is now programmed to 5,250 MHz, which is right in the middle of the operating frequency range. Note that the charge pump current is set to the midpoint of its control range as well. For setting other frequencies, the division coefficient N has to be changed. For example, if we want to program the synthesizer to 5,000 MHz, A should be set to 8 and B should be set to 156. Besides changing the division coefficient N, it is necessary to adjust the charge pump current to keep the PLL filter bandwidth constant across the entire operating frequency range. A specific current value can be stored in memory and changed by setting corresponding bits in another latch. Thus, our control algorithm assumes calculating A and B values for any new given frequency, recalling a charge pump current value from memory and then sending two 24-bit words

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Frequency Synthesizers: Concept to Product

via ADF4106 serial interface. We may also want to monitor voltage on the lock detector line that indicates if the synthesizer is locked.

4.8 Troubleshooting Very few microwave synthesizer designs work perfectly from the first cut. Most likely, they will exhibit some undesirable behavior and require troubleshooting [18]. A basic principle in troubleshooting is to reproduce and isolate a particular problem. There is no troubleshooting harder than fixing a symptom that is intermittent or has more than one cause. The process normally starts from a visual inspection of a PCB assembly followed by checking DC bias for all active components. Confirm that all parts have been properly installed and there are no visual defects such as solder bridges. Also make sure that the board is clean and free of flux residue since it may result in synthesizer misbehavior. Check the DC resistance at all connectors interfacing to the external world to ensure there are no shorted pins. Now it is time to turn on the DC supply and verify DC bias voltages across the board. For example, measuring 3V at the output of the HMC476MP86 IC (Figure 4.26) reveals that the voltage drop across the R12 resistor is about 2V, and therefore, the current consumed by the amplifier is roughly 35 mA. This corresponds to the number indicated in the datasheet. The voltage may be slightly different; however, a significant +5V

+5V R12

56.2 C21

0.1uF C20

100pF

2V ~35mA

L1

6 8nH

+3V

U4 C19

HMC476MP86

22pF

22pF 3

2 4

1

Figure 4.26

DC bias check.

C22

Design Process

139

discrepancy indicates that the R12 resistor value may be wrong or the amplifier may be damaged. The next step is to check the RF power signal at the J2 connector. Since the PLL has not been programmed yet, the synthesizer output frequency will be incorrect (most likely corresponding to the low or high rail at the VCO tuning port). This normally should not be a problem for our initial RF power check. However, for more accurate results (or if the output frequency is not stable), you may want to remove the R11 resistor and bring the VCO to a desired frequency with an external voltage applied to the VCO tuning port as shown in Figure 4.27. The RF output at the J2 connector should be close to the predicted 9-dBm level and may be further adjusted by replacing the A1 attenuator if necessary. Otherwise, the RF signal path should be inspected by measuring and comparing signal levels at individual components from the VCO to the J2 connector with an RF probe. Note that a good RF ground is essential for accurate measurements at microwave frequencies. However, even if the probe does not provide an accurate power reading, it can give an idea if a component is functional. For example, measuring no power difference (or even a power drop) between the HMC476MP86 amplifier input and output (Figure 4.28) indicates that the circuit does not work properly. The failure can be due to incorrectly stuffed components (i.e., DC blocking capacitors or bias inductors have wrong values) or a defective +3V

FB5

BLM18H 1000 C18

0.1uF C17

EXTERNAL VOLTAGE

U3 HMC430LP4

Vcc

20

100pF

16

BASE

RFout

25

GND

C16

820pF

Vtune

15

22

N/C

Figure 4.27 The VCO output frequency can be controlled by an external voltage applied to its tuning port.

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Frequency Synthesizers: Concept to Product

−20 dBm

Figure 4.28

−22 dBm

Amplifier failure symptom.

amplifier. For more complex designs, it is a good idea to reserve designated RF test points using miniature coaxial connectors (such as shown in Figure 4.29), which can be connected or disconnected as necessary. Once the RF output level has been established, we move to the PLL area. Make sure that an external 10-MHz reference signal is present at the J1 connector and then program the ADF4106 from a controlling device (such as a personal computer) connected to the J3 connector. The output signal should move to the correct frequency; otherwise, the PLL needs troubleshooting. PLL debugging is greatly simplified since the ADF4106 IC provides programmable access to some internal points such as RF and reference divider outputs. Measuring output frequencies at these points, which should be equal to the desired step size, can give an idea as to what path is functioning. Program the ADF4106 MUXOUT to Vdd and observe 3-V DC voltage at the corresponding node. Change the MUXOUT to ground and confirm that the voltage drops down to 0V. This tells us that the ADF4106 interface is functional, which is great news. Next, program MUXOUT to the reference divider output and observe 1-MHz pulses. If the frequency differs, then the reference divider division coefficient may not be set correctly. Most likely, the mistake is in the software code. However, if the signal is not stable or not present at all, the input reference signal level or its slew rate may be insufficient. Check the external Amplifier input

Figure 4.29

Amplifier output

RF test points simplify module troubleshooting. (Courtesy of Phase Matrix, Inc.)

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141

signal as well as the C1, C2, and R1 components. In the worst-case scenario, the ADF4106 may be damaged and needs replacing. Similarly, check the RF divider functionality by monitoring 10-MHz pulses at the ADF4106 MUXOUT port. If the pulses are not stable, the RF divider or the whole loop may oscillate. Apply an external voltage to the VCO tuning port and make sure that the signal level in front of the RF divider is sufficient. The divider pulse repetition rate should correspond to the actual output frequency divided by the programmed number. Fix any discrepancy in the controlling software and troubleshoot the RF feedback path as necessary. Connect the VCO tuning port back to the loop filter output and check if the VCO is tuned to the correct frequency. If the VCO rails, make sure that the phase detector polarity is correct. A simple bit inversion may bring the PLL to life. You may also want to check how the phase detector output responds on a division coefficient and phase detector polarity change. No response indicates a possible phase detector failure; otherwise, the problem can relate to the operational amplifier or VCO parts. The VCO tuning characteristics can be checked by controlling its tuning port with an external DC voltage as indicated above; troubleshooting the operational amplifier is fairly simple as well. If PLL settings are correct and all active devices are functional, the failure is probably due to wrong passive loop filter components. Inspect all capacitors and resistors thoroughly. Modern components have become so small that visible labels are not possible. Perhaps the easiest way is just to replace all loop filter parts. Although it looks like a brutal-force solution, it can be the fastest way to fix the problem. Some of the most difficult troubleshooting issues relate to symptoms that are only intermittent. This is often due to components that are thermally sensitive. Compressed air can be used to cool down specific spots on a PCB, while a heat gun raises the temperature if necessary. The main idea is to reproduce a problem then find and replace a part responsible for the failure. In addition to fixing the damaged parts, some component adjustments or tuning may also be required. This is often true for printed filters; a PLL loop filter is another critical area that may need further optimizing. The process is accomplished with a detailed failure analysis and possible design changes.

4.9 Testing For any new product, a detailed test plan should be developed in advance. The test plan defines a sequence of tests required to ensure that the product meets certain specifications. The test plan is prepared as a formal document called a test procedure identifying the nature of all individual tests, necessary equipment, connection diagrams, instrument settings, and all other details required to perform the tests.

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Frequency Synthesizers: Concept to Product

What tests do we need to run for our simple synthesizer? First, we need to make sure that the synthesizer can be set to any given frequency within its operating frequency range. This can be accomplished with a frequency counter as depicted in Figure 4.30. The synthesizer is locked to a 10-MHz reference signal provided by the frequency counter. An additional sine-to-square wave converter (not shown) is required to ensure proper operation of the synthesizer’s reference circuit. The synthesizer is programmed to a sequence (list) of desired frequencies that are usually chosen in a random order. The counter verifies that the synthesizer output is set to the right frequency according to the list. The next step is to check the synthesizer output power using a power meter as illustrated in Figure 4.31. The reference signal is provided by a frequency counter or any other suitable source. The synthesizer is stepped through its operating frequency range with a desired step size (e.g., 10 MHz) and power measurement data is taken. The measured output power levels are about 10 dBm across the entire operating frequency range and can be further adjusted with a built-in attenuator if necessary. 10 MHz REF IN

Synthesizer

Figure 4.30

REF OUT RF

Frequency counter

Frequency setting test.

10 MHz REF OUT Frequency counter

REF IN Synthesizer

Figure 4.31

Output power test.

REF OUT RF

Power meter

Design Process

143

The synthesizer’s harmonics and spurs are measured with a spectrum analyzer as depicted in Figure 4.32. The reference signal comes from the spectrum analyzer backplane. The harmonics are checked at a few fixed frequencies that may correspond to the lowest, highest, and mid-band frequency points. Other frequency points may be added for more complex designs to reflect specific architecture features. The second harmonic level measured for a 5-GHz output signal is about −53 dBc as indicated in Figure 4.33. In contrast, a spurious test plan is usually much more sophisticated since spur locations are generally less predictable. In addition to the natural frequency 10 MHz REF IN

REF OUT RF

Synthesizer

Figure 4.32

Spectrum analyzer

Harmonics and spurious test.

dBm 5 GHz 10

1

0 −10 −20 −30

2-1

−40 −50 −60 −70 −80 −90

Figure 4.33

Start: 3.0000 GHz Res BW: 30 kHz

Vid BW: 30 kHz

Stop: 13.0000 GHz Sweep: 11.50s

Mkr

Trace

X-Axis

Value

1

5 GHz

5.0000 GHz

11.12 dBm

2-1

5 GHz

10.0000 GHz

−53.79 dB

Harmonics at 5 GHz.

Notes

144

Frequency Synthesizers: Concept to Product

boundaries mentioned above, spur levels may be checked at many other frequencies in a random order to catch possible “bad” spots. In our case, the random check is not absolutely necessary since the location of major spurs is easily predicted. Most likely, these should be PLL reference spurs at 1-MHz offset from the carrier. Spurious performance for a 5.25-GHz output is demonstrated in Figure 4.34. Synthesizer phase noise and switching speed can be measured with a spectrum analyzer. However, the measurements are greatly simplified with a specialized signal source analyzer, such as the E5052A + E5053A set up manufactured by Agilent Technologies, Inc. A connection diagram is presented in Figure 4.35. Measured phase noise at 5.25 GHz (Figure 4.36) is in agreement with the calculated profile. The measured switching speed is well below the specified limit of 1 ms as well. dBm 5.25 GHz 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80

Figure 4.34

Centre: 5.2500 GHz Span: 3.0000 MHz Res BW: 10 kHz Vid BW: 30 kHz Sweep: 30.00 ms

Spurious performance for a 5.25-GHz output.

10 MHz REF IN Synthesizer

Figure 4.35

REF OUT RF

Phase noise and switching speed test.

Signal source analyzer

Design Process

145

Finally, DC current consumption is measured and recorded. The measurement can be taken with a regular digital multimeter; however, using a GPIBdriven device (such as Agilent’s E3648A) allows automating the test. Initially, the tests are performed manually to validate not only the product but also the test plan itself. However, eventually an ATE station should be built. An ATE station includes all necessary instruments controlled via a GPIB bus as shown in Figure 4.37. Electromechanical switches can be added to minimize the operator’s effort in setting up individual test connections. The ATE station is controlled by specialized software that sets all the instruments, takes the data, performs data analysis, and generates a test report. It is also important to run all necessary tests not only at room temperature but also at the lowest and highest temperatures to ensure proper functionality at all operating conditions.

4.10 Documentation The design must be properly documented to ensure that the product can be duplicated and eventually produced in large quantities. A documentation set may include product specifications, block diagram, schematic, PCB fabrication drawing, mechanical drawing, assembly drawing with a corresponding bill of materials, test procedure, and other documents required to manufacture a product.

Figure 4.36

Measured phase noise at 5.25 GHz.

146

Figure 4.37

Frequency Synthesizers: Concept to Product

ATE station. (Courtesy of Phase Matrix, Inc.)

Throughout the design stages, all the documents are updated, thoroughly inspected, and eventually released. All further changes are implemented as an ECO (engineering change order) in accordance with company-specific rules and standards. A good documentation system is vital for quality manufacturing of any product. To test the product manufacturability, a pilot run of a greater number of units (typically 10 to 25) follows the prototyping stage. It is an opportunity to evaluate the reproducibility of the design as well as documentation completeness. Following the pilot run, there will likely be additional small changes until the design develops into a stable product.

References [1] Hittite, Inc., “HMC430LP4. MMIC VCO with Buffer Amplifier, 5.0-5.5 GHz,” Datasheet, www.hittite.com.

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[2] Analog Devices, Inc., “PLL Frequency Synthesizer, ADF4106,” Datasheet, www.analog. com. [3] Curtin, M., “Design a Direct 6-GHz Local Oscillator with a Wideband Integer-N PLL Synthesizer,” Analog Dialogue, Analog Devices, Inc., Vol. 35, No. 6, November-December, 2001. [4] Forbes, P., and I. Collins, “Lock Detect on the ADF4xxx Family of PLL Synthesizers,” Application Note AN-873, Analog Devices, Inc., www.analog.com. [5] Hittite, Inc., “HMC476MP86. SiGe HBT Gain Block MMIC Amplifier, DC-6.0 GHz,” Datasheet, www.hittite.com. [6] Banerjee, D., PLL Performance, Simulation and Design, 4th ed., Indianapolis, IN: Dog Ear Publishing, 2006. [7] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [8] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [9] Goldman, S. J., Phase-Locked Loop Engineering Handbook for Integrated Circuits, Norwood, MA: Artech House, 2007. [10] Colin, D., “Driving a Wideband Low Noise VCO from a Low Voltage PLL,” Wireless Design & Development, May 2003, pp. 11–13. [11] Drucker, E., “Model PLL Dynamics and Phase-Noise Performance. Part 1,” Microwaves & RF, November 1999, pp. 69–84. [12] Drucker, E., “Model PLL Dynamics and Phase-Noise Performance. Part 2,” Microwaves & RF, February 2000, pp. 73–117. [13] Drucker, E., “Model PLL Dynamics and Phase-Noise Performance. Part 3,” Microwaves & RF, May 2000, pp. 88–101. [14] Lascari, L., “Accurate Phase Noise Prediction in PLL Synthesizers. Part 1,” Applied Microwave & Wireless, April 2000, pp. 30–38. [15] Lascari, L., “Accurate Phase Noise Prediction in PLL Synthesizers. Part 2,” Applied Microwave & Wireless, May 2000, pp. 90–96. [16] Carlini, J., “Practical Developments Using Today’s Fractional Synthesizers,” High Frequency Electronics, September 2009, pp. 34–47. [17] Lee, J., “Phase Locked Loop Systems Design for Wireless Infrastructure Applications,” Microwave Journal, May 2010, pp. 74–84. [18] Kelly, B., “How to Debug a PLL Frequency Synthesizer,” RF Design, February 2004, pp.50–60.

5 Improving Performance The simple single-loop PLL synthesizer scheme, analyzed in Chapter 4, exhibits various limitations and trade-offs. This chapter examines various design alternatives to achieve different performance objectives such as fast-switching speed, low phase noise, and fine resolution. The design trade-offs are analyzed and complemented with a review of fractional-N, DDS, frequency offset, multiloop, and other schemes. This chapter also covers such important design aspects as initial frequency acquisition, lock monitoring, oscillator selection, harmonic filtering, and frequency extension.

5.1 Performance Trade-Offs The main PLL synthesizer parameters, such as output frequency range, step size, switching speed, spurs, and phase noise heavily depend on each other. First, the synthesizer switching speed is a function of its loop bandwidth, which, in turn, is defined by the phase detector comparison frequency or the step size. Thus, the smaller the step size is, the slower the switching speed. Trying to increase the loop bandwidth may lead to higher reference spurs because of insufficient loop filter rejection or even loop instability. Another concern is phase noise. Achieving fine frequency resolution calls for large division ratios that adversely affect phase noise characteristics. For example, in order to get a 10-GHz output with a 1-MHz step size, the feedback divider ratio has to be 10,000 (as shown in Figure 5.1), which corresponds to an 80-dB phase noise degradation. Furthermore, the discrete spurs at multiples of the reference frequency also tend to be proportional

149

150

Frequency Synthesizers: Concept to Product

to the loop division ratio. Thus, the conventional single-loop architecture suffers from mutually exclusive design goals. It is usually utilized in nondemanding applications or when low cost is the major concern. Is there any universal recipe to improve synthesizer parameters? Let’s imagine that we could use a higher phase detector comparison frequency for a given step size. It would result in several useful effects as illustrated in Figure 5.2. First, increasing the phase detector comparison frequency calls for smaller PLL division ratios that normally result in lower phase noise and spurs. Furthermore, a higher phase detector comparison frequency allows using a wider loop filter bandwidth that leads to faster tuning. Alternatively, we could keep the loop bandwidth unchanged for better stability and enjoy higher suppression of the reference spurs. Clearly, increasing the phase detector comparison frequency benefits virtually all synthesizer parameters. The only real question is how this can be achieved for a given (small) step size. A simple solution that follows from this logic is presented in Figure 5.3 (for simplicity, the loop filter and amplifier are omitted from the following block 1 MHz VCO

LPF

10 GHz

÷10,000

Figure 5.1 A conventional single-loop PLL exhibits significant phase noise degradation because of a large loop division ratio.

Higher comparison frequency

Wider loop filter bandwidth

Higher rejection of reference spurs

Smaller loop division ratios

Faster tuning

Lower spurs

Lower phase noise

Figure 5.2 Increasing phase detector comparison frequency benefits virtually all synthesizer parameters.

Improving Performance K f REF

VCO

K fOUT

151

÷K

f OUT

÷N

Figure 5.3

A simple way to improve single-loop PLL performance.

diagrams). The idea is to increase both phase detector input and VCO output frequencies by K times and then bring the synthesizer output frequency and step size down to desired numbers with an additional divider. Note that the loop division ratio N =

Kf OUT f = OUT remains unchanged. Although the phase Kf REF f REF

detector residual noise normally exhibits 10logK degradation when the comparison frequency increases, this degradation will be offset by 20logK by the output frequency divider. Therefore, this scheme may bring 10logK overall phase noise improvement as well as faster tuning speed or better spur rejection. However, the improvements are limited by availability of high-frequency VCOs and dividers. Achieving low step sizes still remains a big challenge.

5.2 Fractional-N In the PLL example above, we assumed that the RF signal was divided by integer numbers only. For example, if we need to generate some frequencies around 10 GHz with a 1-MHz step size (i.e., 10.000, 10.001, 10.002 GHz, and so forth), the phase detector comparison frequency should equal 1 MHz and the division coefficients should be set to 10,000, 10,001, 10,002, and so forth. Note that we could get these frequencies using a 10-MHz reference if we could set the loop division coefficient to fractional numbers (i.e., 1,000+0/10, 1,000+1/10, 1000+2/10, and so forth). Thus, we would be able to reduce the maximum loop division ratio by about 10 times and use a significantly higher phase detector comparison frequency that, as we just concluded, would benefit virtually all synthesizer parameters. How can fractional division coefficients be realized? In general, this is possible by alternating two dividers (such as shown Figure 5.4) and averaging the output frequency over a certain period of time. Another way to look at this process is to calculate the number of pulses delivered by this circuit for a given time interval, say, 1 second. Obviously, the average division coefficient will be

152

Frequency Synthesizers: Concept to Product ÷2 ÷3

Figure 5.4

Fractional division concept.

between two and three depending on how many pulses are processed by each divider. For simplicity, let’s assume that the incoming frequency is 60 MHz (i.e., 60 million cycles per second) and the incoming pulse sequence is split equally between the two dividers. The signal is divided by two during the first half second, thus delivering 30 million/2 = 15 million pulses at the output. Then the division coefficient changes to 3, and the circuit delivers 30 million/3 = 10 million more pulses during the second half. Altogether, it produces 25 million pulses per second that correspond to the average division coefficient of 2.4. Other division coefficients can be realized by adjusting the processing time intervals. A practical fractional-N synthesizer includes a dual-modulus divider in the feedback path as depicted in Figure 5.5. The synthesizer also includes a phase accumulator that is clocked by the divider output and controls its division ratio (which can be set to either N or N + 1). The operation of the accumulator is very similar to that discussed in Chapter 1. The accumulator content is preset by a control command and is incremented on each clock pulse until it reaches the capacity of the accumulator. Then it resets and the process starts over. Let’s assume that the accumulator’s length is K bits (i.e., it is able to process a sequence of 2K pulses). Let’s also assume that the accumulator controls f REF

f OUT

VCO

÷ N/(N+1)

Modulus control f CLK

Accumulator Tuning Word

Figure 5.5 A fractional-N synthesizer includes a dual-modulus divider controlled by a phase accumulator.

Improving Performance

153

the dual-modulus divider in such a way that the divider divides the incoming frequency by N + 1 during initial M cycles of the sequence and by N during remaining (2K − M) cycles as illustrated in Figure 5.6. In order to deliver NOUT = 2K pulses, the divider has to process NIN = M(N + 1) + (2K − M)N pulses at its input. The overall division ratio is determined by

N FRAC

M (N + 1) + (2K − M ) N M + 2K ⋅ N N IN M = = = =N + K N OUT 2K 2K 2

(5.1)

Thus, fractional division ratios are realizable by entering a tuning word M that defines a point when the dual-modulus divider division coefficient changes. The reference frequency and the length of the phase accumulator determine the frequency resolution of the fractional-N synthesizer by

f RES =

f REF 2K

(5.2)

For example, for a 10-bit accumulator and 10-MHz reference signal, the achievable step size is about 9.766 kHz. Increasing the length of the phase accumulator can further reduce the step size. The biggest concern associated with this scheme is that the instant frequency at the divider output is not constant. An abrupt change in the division coefficient between N and N + 1 leads to a phase discontinuity that produces a voltage spike at the phase detector output. Since the frequency division change occurs periodically with the same rate, it appears as discrete spurs in the synthesizer’s output spectrum. Suppression of the resulting spurs requires that the PLL filter bandwidth has to be sufficiently small, which is not always possible. Note ÷N ÷ (N+1) K

2 −M

M

÷ N/(N+1)

2K Figure 5.6 A dual-modulus divider divides the incoming frequency by N + 1 during initial M cycles of the output pulse sequence and by N during remaining (2K − M) cycles.

154

Frequency Synthesizers: Concept to Product

that the frequency division change is well defined in the time domain and can be potentially compensated by adding or subtracting a voltage at the phase detector output. This compensating voltage is generated by a DAC, which is conveniently controlled by the accumulator as illustrated in Figure 5.7. No perfect compensation, however, is possible. The suppression level depends on the error made in generating the compensating voltage that, in turn, depends on many factors such as DAC resolution, number of controlling bits, and phase detector linearity. Another method to reduce spurious levels is based on using a multimodulus divider that allows a larger number of division coefficients. In this case, we should expect a larger number of spurs of smaller amplitude compared to the dual-modulus scheme. A clever solution is to break the switching regularity, making the spur location randomized. In this case, the energy of spurs is spread through the spectrum, which leads to lower spurious levels. The multimodulus divider is often accompanied by a delta-sigma (ΔΣ or sigma-delta, ΣΔ) modulator that controls the switching process as depicted in Figure 5.8. The delta-sigma technique is well known in communication systems and has been used extensively for analog-to-digital conversion. The fundamental idea of utilizing ΔΣ-modulators is to shape the quantization noise in such a way that a smaller amount of noise power remains within the utilized signal bandwidth. The same idea can be successfully applied to fractional-N frequency synthesis applications by randomizing frequency spurs and pushing them towards higher offset frequencies where they can be easily filtered by the loop filter. Moreover, a ΔΣ-modulator can also reshape the residual noise spectrum so that it has more power at higher frequency offsets. Accompanied by a properly designed loop filter, this leads to better spurious and phase noise characteristics compared to the single-accumulator scheme. There are a number of fractional-N scheme variations, which are described in more detail in [1–6]. In general, designing a fractional-N system is a complex, iterative process because of the large set of system parameters that have to be f REF

Σ

f OUT

VCO

÷ N/(N+1)

Accumulator

DAC

Figure 5.7 A DAC generates a signal to suppress a phase detector voltage spike caused by an abrupt change in frequency division ratio.

Improving Performance

Figure 5.8

155

A fractional-N synthesizer employing a ΔΣ-modulator and a multimodulus divider.

optimized. Fortunately, there are many commercially available integrated circuits that employ fractional-N synthesis. A good example is the family of fractionalN PLL ICs from Analog Devices, Inc., which are pin-to-pin compatible with integer-N PLL counterparts discussed in Chapter 4. Thus, the design sequence remains virtually the same. Special attention, however, is required in frequency planning to make sure that the spurious signals do not fall into the loop filter bandwidth. In spite of various improvements, the main disadvantage of the fractionalN technique is the excessive spurious levels produced by phase errors inherent in the fractional division mechanism. Nevertheless, it is a simple and elegant solution for many applications where increased spurious performance can be tolerated.

5.3 Using a DDS The DDS is another effective solution to provide a very fine frequency resolution without a common penalty of the phase detector comparison frequency reduction. The DDS can serve as a fine-resolution, high-frequency reference (as shown in Figure 5.9) that allows the reducing of the loop division coefficient for a given step size compared to conventional PLL circuits. Moreover, since the DDS output can be programmed in wide limits, the loop division coefficient can be kept unchanged. Therefore, a programmable divider may be eliminated or substituted with a fixed-division ratio prescaler. This configuration, however, requires a high-frequency clock signal, which can be formed with a frequency multiplier or another PLL circuit. The configuration shown in Figure 5.10 employs a DDS as a fractional divider inserted into the PLL feedback path and clocked from the same PLL

156

Frequency Synthesizers: Concept to Product f CLK

f OUT

VCO

DDS

÷N

Figure 5.9

Using a DDS as a reference. f REF

DDS

Figure 5.10

f OUT

VCO

÷K

Using a DDS as a fractional divider.

output. This eliminates a separate circuit required to generate the clock signal. A high-frequency prescaler may be needed to keep the DDS input clock frequency within specified limits. Frequency tuning is achieved by adjusting the DDS’s output frequency with a proper tuning command. The idea is to keep the DDS output unchanged (equal to the reference frequency) for any desired RF output frequency. While a DDS provides excellent frequency resolution and phase noise characteristics, its spurious levels are quite high (−50 to −60 dBc are common representative numbers). Moreover, the spurs further degrade because of the PLL multiplication mechanism. Although the two architectures above look different, they both affect DDS spurs in the same manner. In both cases, the overall loop division coefficient is defined by the ratio between the VCO output and phase detector comparison frequencies. Degradation can be avoided by completely removing the DDS from the loop as depicted in Figure 5.11. In this case, the effective multiplication factor for the DDS output equals 1, and hence, the DDS spurs are not affected. Note that certain care is required to ensure that the mixer output is properly filtered. Two sideband signals of the same amplitude, generated by the mixer, may “confuse” the divider and result in its misbehavior. As a rule of thumb, all undesired signals in front of the divider should be kept −10 to −15 dB below the main tone to ensure proper operation. For a narrowband design, it is not a difficult task since the undesired mixer sideband can be easily filtered with a bandpass filter. However, a switched filter bank may be required

Improving Performance f REF

VCO

157 f OUT

÷N

f CLK

Figure 5.11

DDS

Removing a DDS from the phase-lock-loop eliminates spur degradation.

for wideband operation. An image-reject mixer is a simple and cost-efficient solution that eliminates the need for filtering at microwave frequencies. Even without degradation, the DDS-induced spurious levels may still be prohibitory in many applications. A number of solutions (both hardware and software based) can be utilized to reduce the DDS spurs [7–10]. Hardware techniques are usually based on upconversion of the DDS signal followed by a frequency divider as illustrated in Figure 5.12. Since the frequency mixing does not affect DDS spurs (assuming that undesired mixer products are properly filtered), the circuit reduces the DDS spurious content at a rate of 20 dB per decade inherent to the frequency division process. Unfortunately, it also reduces the available bandwidth, which may be a limiting factor in certain cases. Applying more LO frequencies and filters as depicted in Figure 5.13 can extend the DDS bandwidth. However, it also results in a higher component count similar to the direct analog schemes. Software techniques involve frequency planning to move DDS spurs in the frequency domain. These techniques are based on the fact that DDS spur

Figure 5.12

DDS spur reduction.

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Frequency Synthesizers: Concept to Product

Divider

DDS

LO 1

Figure 5.13

LO2 LO 3

LO N

DDS bandwidth extension.

location is a function of its output and clock frequencies. Therefore, for a given output frequency, one can move then filter out an undesired spur by adjusting the DDS input clock frequency and frequency tuning command as illustrated in Figure 5.14. This technique can be conveniently combined with PLL architectures, which provide a variable clock source as well as very efficient PLL-based filtering. In general, no technique alone can fully suppress DDS spurs. However, by combining various methods, it is possible to manage DDS spurs at reasonably low levels and to utilize its exceptional frequency resolution capabilities.

5.4 Frequency Offset Schemes The synthesizer’s main characteristics can be drastically improved using frequency conversion (mixing) within the synthesizer feedback path as shown in Figure 5.15. The idea is to convert the VCO output to a much lower frequency with the aid of a mixer and an offset frequency source. Let’s come back to our example where we needed to synthesize some frequencies around 10 GHz with 1-MHz step size (e.g., 10.000, 10.001, …, 10.100 GHz). If the offset frequency is 9 GHz (we use a rounded number for simplicity), the VCO output will be converted down to the 1.0- to 1.1-GHz frequency range. This will require setting the divider ratio between 1,000 and 1,100. This is about 10 times lower compared to a conventional integer-N solution. Note that the mixing process itself does not affect PLL phase noise characteristics. Assuming that offset signal noise

Improving Performance

159

f CLK

DDS Tuning command

Move spur Keep DDS output

Filter passband

dBm DDS Spurs 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 5.14

Start: 0 Hz

Stop: 200.0000 MHz

DDS spur filtering.

is sufficiently low (compared to residual characteristics of PLL components and the reference source), the PLL noise will be improved by 20 dB. Although the solution seems very straightforward, special care is required to prevent LO and reference leakage to the VCO output. Inserting a highpass filter into the feedback path can easily filter the reference signal. However, LO leakage presents a more serious challenge. Since the LO frequency is usually close to the RF signal (as it is required to reduce the PLL division ratio), in many cases it cannot be filtered and appears as a spur. High LO-to-RF isolation is a critical parameter that should be checked when selecting a mixer. The isolation can be further improved by inserting a directional coupler and an amplifier into the feedback path as shown in Figure 5.16. Based on particular requirements, the coupling path may include a chain of amplifiers separated by attenuators. Note that the mixer products also appear at the IF port; thus, proper termination and filtering should be applied. Furthermore, bias filtering and electrical shielding are important factors that also affect signal leakages.

160

Frequency Synthesizers: Concept to Product f REF

VCO

f OUT

÷N f OFFSET

Figure 5.15

Frequency mixing within RF feedback path.

f REF

VCO

f OUT

÷N f OFFSET

Figure 5.16

A directional coupler and amplifier are added to improve the LO-to-RF isolation.

In certain scenarios (e.g., when the operating frequency range is narrow) it is possible to eliminate the feedback frequency divider completely. In this case, the loop division coefficient equals 1, and no phase noise degradation occurs. Moreover, we can reduce PLL residual noise at the same 20logN rate by inserting a frequency multiplier into the feedback path instead of a divider as depicted in Figure 5.17. Although frequency offsetting brings a big relief for PLL residual noise characteristics, it introduces another noise source. The phase noise of the offset signal transfers dB for dB to the RF output (assuming no frequency multiplication or division is applied in front of the mixer) that can become a limiting factor. The offset signal is usually produced from the same reference using an additional PLL or a frequency multiplier as shown in Figure 5.18. A multiplier is a more preferable solution since it normally offers smaller phase noise degradation (beyond the fundamental 20logN rule) compared to a PLL counterpart.

Improving Performance f REF

VCO

161 f OUT

×N

f OFFSET

Figure 5.17

A frequency multiplier in the feedback path improves PLL noise performance.

f REF

VCO

f OUT

÷N

×M

Figure 5.18

An offset signal is produced from the reference using a frequency multiplier.

However, sometimes a required multiplication factor cannot be conveniently realized; thus, a PLL multiplier remains the only option. An attractive solution is a harmonic mixer that utilizes higher-order harmonics created by a built-in step recovery diode. This approach leads to a shorter bill of materials compared to fundamental mixing schemes. However, the harmonic mixer is quite sensitive to circuit parameters; making one work properly requires a certain design effort. Another concern is a reduced signal-to-noise ratio resulting from a high multiplication factor, as well as picking up the noise at reference harmonics. This phenomenon is illustrated in Figure 5.19. While converting the VCO signal to a desired IF frequency, the harmonic mixer also translates any other signals (including noise) near multiples of the reference frequency. This noise power is collected at many places and is eventually accumulated at the mixer output that can be a significant contribution to the noise

162

Frequency Synthesizers: Concept to Product LO N

LON+1

LO N+2

Noise IF

LON+3 RF

IF

Figure 5.19 A harmonic mixer collects noise power near multiples of the reference frequency.

budget. Thus, a fundamental mixer, driven by a frequency multiplier (or a chain of multipliers), generally provides superior noise characteristics. The main disadvantage of the simple frequency offset schemes is limited frequency coverage. Widening the output frequency bandwidth for a fixed offset frequency leads to a higher IF at the mixer output. This requires a divider with a larger division coefficient, thus defeating the idea of this method. The offset frequency signal should preferably be as close as possible to the RF output frequency in order to keep the division ratio at a minimum. This can be accomplished by inserting a chain of mixers into the PLL feedback path as depicted in Figure 5.20. This arrangement offers more flexibility in frequency planning yet requires more mixers and frequency offset sources. The offset signal can also be generated within the same PLL (as shown in Figure 5.21) by adding two programmable dividers at the mixer terminals as suggested in [11]. It is easy to show that f OUT = f REF N

AB ; thus, this scheme, A ±B

called a self-offset loop, allows fractional division coefficients that lead to the overall performance improvement compared to a conventional PLL design.

f REF

VCO

f1

Figure 5.20

f2

f OUT

fN

A mixer chain in the feedback path offers more flexibility in frequency planning.

Improving Performance f REF

163 f OUT

VCO

÷N

÷A

÷B

Figure 5.21

Self-offset loop.

5.5 Multiloop Architectures As mentioned in Section 5.4, the frequency offset signal can be generated with another PLL as depicted in Figure 5.22. What do we gain with this approach? Let’s revise again our need for a 1-MHz-step synthesizer operating around 10 GHz but in a wider frequency range, let’s say, between 9 and 10 GHz. The first PLL provides 9- to 10-GHz frequency coverage with a 100-MHz step by varying the division ratio N1 between 90 and 100. The output of the first PLL is used as an offset signal for the second loop to keep the mixer output below 100 MHz. Thus, for the desired 1-MHz step size, the maximum division ratio for the second loop does not exceed 100 as well. The phase noise degradation for both loops (set by the maximum division ratio) does not exceed 40 dB versus 80 dB 100 MHz ÷ 100

1 MHz

VCO2

9–10 GHz 1 MHz step

÷ N2 9–10 GHz 100 MHz step 100 MHz

VCO1

÷ N1

Figure 5.22

Dual-loop synthesizer example.

164

Figure 5.23

Frequency Synthesizers: Concept to Product

Multiloop frequency synthesizer.

for the single-loop alternative. Therefore, splitting the design in two loops can potentially result in an overall 40-dB phase noise improvement compared to our single-loop example. Greater phase noise improvement (or smaller step sizes) can be achieved using a larger number of PLLs as shown in Figure 5.23. The number of loops and frequency plan depend on particular synthesizer requirements such as operating frequency range, step size, and phase noise. Since there are a number of choices for managing the individual loop characteristics, the frequency planning is not trivial; some practical scenarios are discussed in more detail in [2].

5.6 Frequency Acquisition One of the problems associated with any frequency-mixing scheme is a possible false lock caused by undesired mixing products. Note that two different frequencies at the synthesizer output can produce the same IF as shown in Figure 5.24. However, the PLL circuit will process these frequencies in a different manner. If the output frequency changes (e.g., increases) the IF behaves differently (either

Improving Performance f REF

165 f OUT

VCO

fOUT1 = f LO + f IF fOUT2 = f LO − f IF ÷N

f IF

f LO

Figure 5.24

Two different frequencies at the synthesizer output can produce the same IF.

increases or decreases) depending on what sideband is utilized. The PLL recognizes this difference by properly selecting the operational amplifier gain sign or phase detector polarity, as it can be conveniently programmed in the ADF4106 PLL IC analyzed earlier. What happens if the synthesizer output frequency for some reason (let’s say, when it is just turned on) is on the wrong side of the LO frequency? The PLL may steer the VCO in the wrong direction, thus preventing PLL locking to the desired frequency. Let’s analyze another scenario when a harmonic mixer is utilized. Note that, in this case, there are a number of output frequencies that can produce the same IF as shown in Figure 5.25. Moreover, half of them will be processed correctly (i.e., will steer the VCO to the correct direction) and may cause the PLL to lock. Therefore, there are a number of places where the synthesizer can be potentially locked to a wrong frequency. This is an especially dangerous scenario since the PLL lock detector circuit may indicate that the synthesizer is locked or, in other words, is working properly. What should we do to prevent this scenario? The easiest solution is to restrict the VCO from going outside an acceptable frequency range. For a narrowband synthesizer, this can be accomplished by selecting a VCO with a sufficiently narrow tuning range (such as a CRO or DRO) and/or properly limiting LO N

LO N+1

LO N+2

LO N+3

Potential lock frequencies

Figure 5.25 A harmonic mixer exhibits a number of places where a synthesizer can be potentially locked to a wrong frequency.

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Frequency Synthesizers: Concept to Product

its tuning voltage. It is often accompanied by a search oscillator that generates a low-frequency, sawtooth voltage applied to the VCO tuning port. The sawtooth oscillator can be a separate device or can be built as part of the loop filter itself. The idea is to sweep the VCO output between its lower and upper limits until it reaches a lockable region as illustrated in Figure 5.26. Once the mixer produces a desired IF, the sweep stops and the PLL locks the VCO in a normal way. Another method, also applicable for wideband applications, is to pretune a VCO to approximately the correct frequency where it can be caught by the PLL circuit. This can be achieved with a digital-to-analog converter (DAC) as depicted in Figure 5.27. The VCO tuning port is initially connected to the DAC that generates a required voltage for coarse tuning. Then the VCO switches to the PLL and eventually locks to the exact frequency. Although it seems very straightforward, this acquisition aid requires linear and repeatable VCO tuning characteristics as well as precise frequency calibration to compensate the VCO temperature drift. This method works well with YIG-tuned oscillators because of their linear tuning characteristics. The f f HIGH f OUT

Lockable range

f LOW

t

Figure 5.26 A VCO sweeps between its lower and upper limits until it reaches a lockable region.

DAC f REF

VCO

f OUT

÷N f OFFSET

Figure 5.27

Initial frequency acquisition using a DAC.

Improving Performance

167

frequency calibration can be automated by using an analog-to-digital converter (ADC) as illustrated in Figure 5.28. The synthesizer is consequently tuned to several frequencies across its operating frequency range, and the ADC measures the exact tuning voltage when the oscillator is locked. The measured voltages are stored in a nonvolatile memory and are used in a coarse-tuning routine. A VCO can also be pretuned with an auxiliary, coarse-tuning PLL circuit that does not utilize frequency mixing and avoids output frequency uncertainty. Inserting an additional divider that bypasses the mixer, as depicted in Figure 5.29, forms the coarse-tuning PLL. The output of this divider connects to the phase detector with a switch. Initially, the switch is in the upper position, thus engaging the coarse-tuning PLL. The coarse-tuning PLL is a conventional single-loop circuit that provides a simple and reliable mechanism to pretune the VCO to a desired frequency. It also generates a lock detect signal indicating that the frequency acquisition is completed. Then the switch disconnects the coarsetuning path and connects the offset mixer chain. The synthesizer relocks to the same frequency providing better spectral purity performance. The phase noise and spurious characteristics of the coarse-tuning PLL are not a big concern since this path is completely disabled after initial frequency acquisition. The main advantage of this method is that the coarse-tuning mechanism does not depend on the VCO temperature drift or any other component instabilities. The frequency acquisition accuracy is entirely a function of the auxiliary loop characteristics (step size) and can be easily improved using a DDS or a fractional-N scheme. Practical implementation of this method may face some difficulties since the loop gain changes significantly when the circuit switches the PLL paths.

ADC CPU and Memory

DAC f REF

YIG

f OUT

÷N f OFFSET

Figure 5.28

An ADC measures the exact tuning voltage when the oscillator is locked.

168

Frequency Synthesizers: Concept to Product f REF

f OUT

VCO

÷K

÷N f OFFSET

Figure 5.29 A VCO can be pretuned with an additional PLL circuit that does not utilize frequency mixing.

Furthermore, the phase detector comparison frequency may also need changing. Another way to implement the coarse-tuning PLL concept is presented in Figure 5.30. The scheme includes two separate phase detectors and reference dividers; hence, both PLLs can be designed and optimized independently. Note, however, that the loop filter itself (or its portion) is still common, sharing a capacitor that keeps the VCO tuning voltage during the transition between two states. The coarse-tuning mechanism can also be implemented in many other forms. In a more general sense, it requires a frequency-sensing circuit to resolve output frequency uncertainty as illustrated in Figure 5.31. This circuit, called the frequency-difference detector or the frequency discriminator, generates an error signal, which is proportional to the difference between commanded and actual

÷ RK

÷K

f REF

VCO

÷ RN

f OUT

÷N f OFFSET

Figure 5.30

Two separate phase detectors simplify circuit design and optimization.

Improving Performance

169

Frequency detector f REF

VCO

f OUT

Phase detector f OFFSET

Figure 5.31 An offset PLL scheme is complemented by a frequency-sensing detector to resolve output frequency uncertainty.

output frequencies. Practical implementations include many different circuits discussed in more detail in [1, 2, 12].

5.7 Lock Monitoring Once the synthesizer locks to a desired frequency, it generates a signal indicating that the output frequency is set properly. The easiest way to accomplish this function is to monitor the voltage on the VCO tuning line with a window comparator as depicted in Figure 5.32. The comparator detects whether the VCO tuning voltage is within specified limits that correspond to a certain frequency range set by the resistive divider. For a wideband operation, the circuit can be complemented with a DAC that changes the comparator reference voltage with frequency change. The main disadvantage of this lock detector type is its poor accuracy. It only indicates that the VCO output is “close enough” to a desired VIN V REF

Lock

Figure 5.32

A window comparator detects if the VCO tuning voltage is within specified limits.

170

Frequency Synthesizers: Concept to Product

frequency rather than being truly locked. Note that in many PLL designs, the VCO voltage rails low or high (i.e., goes to either the most negative or the most positive available voltage) if the VCO is not locked. In this case, the voltage comparator provides an adequate indication of whether the synthesizer is locked or not. A more accurate lock indicator can be built using a coherent amplitude detector, also called a quadrature detector. The detector can be a balanced mixer that produces the maximum DC voltage if it is fed by two input signals of the same frequency but applied in quadrature (i.e., with a 90° phase shift). When the two input frequencies are not equal, the quadrature detector generates a beat note, which is filtered by a lowpass filter. An exclusive-OR gate behaves very similarly and is often incorporated into PLL ICs to execute the lock detection function as discussed earlier. Care is required when such a detector is used in frequency mixing architectures since the PLL can be locked to a wrong frequency. Combining two lock detector signals as illustrated in Figure 5.33 treats this case. The first detector (such as a quadrature detector) provides an indication that the signal is locked while the second detector (such as a window comparator or a frequency discriminator) checks if the synthesizer output is in a valid frequency range. A quite accurate lock indicator (or its frequency-sensing portion) can be built with a frequency counter approach. The idea is to count the number of pulses coming from a VCO (or divider following the VCO) during a certain time interval—exactly how it is done in frequency counter instruments. Although the implementation may seem complex, a fairly simple counter can be built using a single-chip microcontroller. Since instrument-grade precision is not required, such a counter provides a fast yet quite accurate reading of the actual output frequency.

5.8 Fast-Switching Designs Aside from frequency coverage, resolution, and spectral purity, a synthesizer’s switching speed is an important factor that limits the performance of modern RF and microwave system. Newer designs require faster switching because of the Frequency lock Lock Phase lock

Figure 5.33 signals.

A frequency uncertainty is removed by combining phase lock and frequency lock

Improving Performance

171

ongoing increase of data flow. Hence, reducing the PLL lock time is quite a typical design goal. Since the PLL settling time is inversely proportional to the loop bandwidth, widening the PLL bandwidth is a general approach in designing fast-switching synthesizers. However, a few concerns have to be addressed while designing a wideband PLL filter: • The loop filter has to provide an adequate spurious suppression for a given frequency plan. • The PLL should remain stable. • PLL residual noise should be sufficiently low (compared to the VCO free-running noise). Thus, widening PLL filter bandwidth requires balancing all design constraints, as will be further discussed in the next section, and is not always possible. Can we speed up the synthesizer response and still keep its optimum loop bandwidth? Note that the major contribution to PLL settling is the time required to charge a capacitor that stores the VCO tuning voltage. Let’s imagine a loop filter as a hypothetical RC circuit. Naturally, we can reduce the charge time by connecting the capacitor to a lower impedance voltage source as illustrated in Figure 5.34. It is essentially the same frequency acquisition aid discussed in the previous section. A DAC generates a voltage that quickly charges the loop filter capacitor to a required value. Then it is inserted back into the loop to complete the look. Widening the loop bandwidth for a short period of time during the initial frequency acquisition then switching back to a narrower bandwidth for normal operation can also reduce the PLL settling time. This can be done by switching different resistor values (as shown in Figure 5.35) or by changing the phase detector current injected into the loop. Many PLL ICs (such as the ADF4106 discussed earlier) allow the programming of charge pump current in wide limits to control the loop bandwidth. Although the idea seems quite simple, its practical implementation requires effort to optimize loop filter components. Note that the PLL has to remain stable in speed-up mode but not at steady state only. Also R LOW

DAC from PD

R

to VCO C

Figure 5.34

A DAC generates voltage to charge quickly a loop filter capacitor.

172

Frequency Synthesizers: Concept to Product

make sure that the utilized components can support high instantaneous peak currents. For example, an improperly selected operational amplifier may exhibit current limiting that results in tuning speed degradation.

5.9 VCO or YIG? Any PLL synthesizer design strongly depends on tuned oscillator characteristics. Historically, high-performance synthesizers have relied on YIG-tuned oscillators featuring broadband operation and excellent phase noise performance. YIG oscillators also offer very linear (and repeatable) tuning characteristics that simplify the synthesizer coarse tuning in multiloop schemes. The disadvantages include high power consumption, large size, and relatively high cost. However, the main problem inherent in YIG technology is slow tuning because of high inductance of the tuning coil. Typical achievable switching time is in the milliseconds range. An alternative to YIG oscillators is the use of VCOs. Unlike YIGs, VCOs tune much faster; microseconds operation is easily achieved. The size, power consumption, and cost of VCOs are generally lower compared to YIG devices. However, noise performance is considerably worse, which may restrict using a VCO in high-performance designs. Is there any way to improve the VCO-induced noise to a degree where it may be used in lieu of a YIG oscillator? Let’s compare phase noise behavior of two hypothetical oscillators (YIG and VCO) that utilize identical active device arrangements. At very high-frequency offsets, both oscillators should demonstrate the same behavior (noise floor) defined by the ratio of the available RF power and thermal noise of the active device as shown in Figure 5.36. The noise starts degrading at a rate of 20 dB per decade at lower frequency offsets. The degradation start point is defined by the Q-factor of a utilized resonator. In the last region, where the flicker noise dominates, the phase noise increases at 30 dB per decade. Clearly, the VCO demonstrates significantly higher phase noise in comparison with the YIG-oscillator because of the difference in their resonator Q-factors. Now let’s build a synthesizer using these oscillators or, in other words, lock them to a low-noise reference source. What phase noise behavior is expected? The answer obviously depends on the available reference noise characteristics, R LOW to VCO

from PD R

Figure 5.35

C

Loop filter bandwidth can be controlled by switching resistors.

Improving Performance

173



YIG VCO

fc

Figure 5.36

f 0 / 2QYIG

f 0 / 2QVCO

foffset

Phase noise comparison of free-running VCO and YIG oscillators.

the PLL residual noise floor, and the loop filter bandwidth as illustrated in Figure 5.37 (with the all noise contributions recalculated to the VCO output frequency). The loop filter bandwidth is preferably set to its optimal frequency, which is the cross point of the PLL multiplied noise and oscillator free-running noise curves, that provides the lowest overall phase noise response. A typical phase noise profile of a YIG-based synthesizer is shown in Figure 5.38. The reference source noise normally dominates at very low frequency offsets (region 1) while a relatively flat noise plateau in region 2 occurs mainly because of the PLL residual noise limitations. Outside the loop filter bandwidth, the noise follows the freerunning noise curve of the YIG oscillator (region 3).

Figure 5.37

Inserting VCO and YIG oscillators into a phase-lock-loop.

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Frequency Synthesizers: Concept to Product



VCO (not optimal) YIG 1 2

3 f YIG

Figure 5.38

f offset

Locking VCO and YIG oscillators within YIG optimal loop bandwidth.

Trying to lock the VCO within the same loop bandwidth will result in a very ugly noise profile because of excessive VCO noise at these offsets. A smoother phase noise profile is obtained by locking the VCO within its own optimal bandwidth as shown in Figure 5.39. Since the VCO is now locked within a wider loop bandwidth, it locks much faster than the YIG. However, the VCO phase noise curve is still well above the YIG counterpart. The difference in phase noise between the YIG and VCO-based synthesizers is set by the PLL noise floor and free-running oscillator noise curves and is indicated as a hatched area in Figure 5.40. Predictably, reducing the PLL noise floor and simultaneously widening the loop filter bandwidth minimize the difference, thus making a VCO-based synthesizer behavior similar to its YIG counterpart. Can a VCO-based design achieve a YIG-comparable performance? Assuming we have an ideal, noiseless PLL mechanism, the output phase noise is still limited by the available reference that becomes a dominating factor. Today’s 

YIG

f YIG

Figure 5.39

f VCO

VCO

f offset

Locking VCO and YIG oscillators within their own optimal loop bandwidths.

Improving Performance

175

ᏸ

YIG VCO PLL noise floor

o

t

Figure 5.40 Reducing the PLL noise floor and widening the loop filter bandwidth minimize the difference in phase noise between YIG and VCO-based synthesizers.

commercial crystal oscillators can perform within −160 to −180 dBc/Hz at a 10kHz offset at a 100-MHz output. These numbers can be potentially translated to −120 to −140 dBc/Hz at 10 GHz, which corresponds or even supersedes the performance of the best YIG oscillators at the same frequency settings. YIG oscillator noise can be still superior at higher frequency offsets (a few hundred kilohertz to a few megahertz) that would require a more complex reference scheme, which will be discussed in Section 5.10. However, in general, a high-Q, fixedfrequency, reference oscillator is capable of delivering a low phase noise signal comparable (or better) to that generated by a YIG oscillator at any frequency offset. Therefore, the limitations are mainly set by PLL residual noise characteristics or, in other words, by a particular synthesizer architecture. In summary, the key principles in designing low-noise, fast-switching, VCO-based PLL synthesizers are as follows: • Using a very low-noise reference source; • Reducing the PLL residual noise floor; • Extending the loop filter bandwidth. What technology is more preferable? The VCO clearly dominates in lowcost, low- to moderate-performance designs. However, for high-performance, broadband, low-noise applications, the answer is not so obvious. YIG-based solutions are usually simpler since the YIG-oscillator can mask many design imperfections. One can achieve respectable phase noise performance with a simple single- or dual-loop PLL. Achieving YIG-comparable noise characteristics for a VCO-based design is not a trivial task. This calls for advanced multiloop

176

Frequency Synthesizers: Concept to Product

solutions and also requires a great deal of effort to treat various “secondary” effects. Nevertheless, the need for faster tuning and lower cost makes the VCO an attractive alternative for many practical scenarios.

5.10 Reference Generation and Distribution A reference oscillator is one of the most important parts that define stability and phase noise characteristics of a frequency synthesizer. Various reference oscillator schemes are possible as shown in Figure 5.41. A 10-MHz TCXO is a simple solution for low-cost designs. Better stability and noise characteristics are achieved by using an OCXO, which, however, is a more expensive and bulky part with higher power consumption. It is worth mentioning that using a higherfrequency OCXO (e.g., 100 MHz instead of 10 MHz) can potentially result in better synthesizer noise because of comparable noise floor for both parts but significantly lower overall multiplication factor. Even better phase noise performance at higher-frequency offsets (100 kHz and above) can be obtained with additional low-noise oscillators (e.g., SAW, CRO, or DRO) locked to the main OCXO. The chain of oscillators, which can include two or even more parts, allows optimizing the phase noise profile at any frequency offset (as illustrated in Figure 5.42) and can be used in high-end synthesizer designs. The multioscillator, high-frequency reference can be used as a fixed-frequency offset signal as depicted in Figure 5.43. The phase detector comparison frequency is derived from a lower-frequency stage or by utilizing an additional high-frequency prescaler. A wideband synthesizer can involve a more complex signal distribution scheme such as shown in Figure 5.44. The design consists of a number of mixers driven by offset signals that are derived from a common

TCXO

OCXO

OCXO

Figure 5.41

10 MHz

100 MHz

100 MHz

SAW

Reference oscillator schemes.

1 GHz

DRO

10 GHz

Improving Performance

177

Figure 5.42 A combination of low-noise oscillators is utilized to optimize phase noise at any frequency offset.

VCO

f OUT

÷N

÷R

REF1

Figure 5.43

REF2

REF3

A high-frequency reference is used in a frequency offset scheme.

high-frequency source. The implementation may vary based on particular design goals as well as available components.

5.11 Filtering Harmonics Harmonics are well separated from the main tone and therefore usually are not as troublesome as spurs. Nevertheless, they need to be minimized for some har-

178

Frequency Synthesizers: Concept to Product f OUT

VCO M1

÷ R1

÷ R2

REF1

Figure 5.44

M2

MK

÷ RK

REF2

REF3

A more complex reference distribution scheme.

monic-sensitive applications such as test-and-measurement instruments. For a narrowband synthesizer, it is easily achieved by placing a lowpass filter at the output. However, a switched filter bank or a tunable filter is required for bandwidths reaching or exceeding an octave. This is illustrated in Figure 5.45 for a synthesizer covering the f to 2f frequency range (an octave). Naturally, the output filter has to pass the signal in this range. Note that the second harmonic of the lowest frequency equals 2f and therefore falls into the filter passband. Hence, the filter needs tuning depending on what frequency is applied. A tunable filter can be built using YIG or varactor-tuned resonators. A YIG filter consists of a chain of YIG resonators (Figure 5.46), which are placed between two poles of an electromagnet and driven by a common magnetic field. Changing DC current injected into the electromagnet coil controls the magnetic field and, consequently, the YIG resonance frequency. The number of resonators and their coupling is selected to form a required filter response. YIG-tuned filters provide decent rejection in a very wide frequency range such as the 2- to 18-GHz range covered by the module shown in Figure 5.47. They are widely used in testand-measurement instruments such as signal generators and spectrum analyzers. Filter passband Operating range

f

Figure 5.45

Second harmonic range

2f

The second harmonic falls into the filter passband.

4f

Improving Performance YIG resonator

IN

179

Electromagnet

OUT

Figure 5.46 A YIG filter consists of a chain of YIG resonators placed between two poles of an electromagnet.

Figure 5.47

A YIG-tuned filter covers 2 to 18 GHz. (Courtesy of Micro Lambda Wireless, Inc.)

The disadvantages are similar to the YIG oscillators and include relatively large size, high power consumption, and slow tuning. They also introduce loss that can be quite significant for a multistage filter. Another phenomenon of YIG material is signal limiting that can be in order of 10 dBm, dependent on a particular filter design and utilized material [13–21]. A varactor-tuned filter is a lower-cost alternative that offers much faster tuning [22–25]. Unfortunately, the frequency coverage is not as wide as it is for YIG counterparts. Octave tuning is rarely exceeded. Varactor-tuned filters are also quite lossy due to the loading effect caused by the varactor’s impedance. Note that a varactor is a nonlinear device, which may introduce signal distortion when high-power input signals are present. Nevertheless, the varactor-tuned filters can be conveniently used in some low-frequency or low-power designs. Another solution is to break the operating frequency range in subbands where fixed-frequency lowpass filters can be used [25]. This solution is well known as a switched filter bank. It consists of the input and output switches

180

Figure 5.48

Frequency Synthesizers: Concept to Product

A switched filter bank is used for bandwidths reaching or exceeding an octave.

as well as the number of lowpass filters (Figure 5.48) as required to cover the whole operating range. Pin-diodes or FET devices are usually utilized. Switching schemes may vary; for example, a circuit on Figure 5.49 includes a larger number of SPDT (single pole, double throw) switches, which are easier to implement. A switched filter bank provides better power handling and much faster switching compared to YIG-tuned filters. Harmonic suppression is generally adequate, although it can be limited by isolation between individual filter channels. Moreover, harmonics can be regenerated in the output switch if high power is applied. Thus, switch isolation, linearity, and insertion loss are critical parameters that define performance of switched filter banks. A higher output power can be provided by incorporating amplifiers (as depicted in Figure 5.50) that

Figure 5.49

Another configuration using SPDT switches.

Figure 5.50

A switched amplifier bank eliminates loss in the input switch.

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offset signal loss introduced by the input switch. Since the input switch loss is applied at the amplifier input but not at the output, lower power amplifiers may be used. Furthermore, the input switch can be completely eliminated (Figure 5.51) by utilizing a passive signal-distribution scheme (e.g., Wilkinson dividers) while turning off unused amplifiers improves the isolation between individual channels. Although this scheme may seem unnecessarily complex, it can be a preferred solution since it utilizes relatively narrowband, lower-power, and lower-cost amplifiers.

5.12 Frequency Extension Wideband frequency coverage is desired in many applications. Multi-octave coverage is easily achieved with YIG oscillators. However, slow tuning may be prohibitory in some applications. In contrast, VCOs are fast but rarely exceed an octave tuning. Utilizing several VCOs with overlapping bands extends the operating bandwidth. The individual oscillators are combined in a switched VCO bank as shown in Figure 5.52 in a similar manner to how it is done in a switched filter bank. Since only one VCO is used in a particular moment, the unused VCOs are switched off to prevent output signal contamination. This solution also allows using narrowband VCOs with better phase noise characteristics as compared to a wideband single-VCO alternative. A frequency multiplier is used to extend the frequency coverage to higher frequencies. A doubler is the most commonly used device that provides continuous coverage for an octave input (e.g., 1 to 2 GHz as shown in Figure 5.53). A combination of multipliers with different multiplication factors is used when less than an octave input bandwidth is available. This is illustrated in Figure 5.54 for the 4- to 6-GHz input signal. The doubler extends this bandwidth to

Bias

Figure 5.51

The input switch is substituted with passive signal dividers.

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Frequency Synthesizers: Concept to Product

VCO 1

Out

VCO 2

Tuning

VCO 3

Bias

Figure 5.52

Switched VCO bank.

8 to 12 GHz while the frequency tripler covers 12 to 18 GHz. Thus, together two multipliers provide wider coverage than an octave (8 to 18 GHz) with no frequency gap. The multipliers degrade synthesizer phase noise and spurs at a 20logN rate (i.e., 6 dB per octave) inherent to the frequency multiplication process. Note that the frequency multipliers also generate subharmonic products, which are generally treated as spurs. For a narrowband design, the subharmonics are rejected by using a single bandpass filter. However, a tunable filter or a switched filter bank is required for wideband coverage. Note that isolation between individual channels is even a greater concern (as compared to harmonic filters discussed above) because of much tighter requirements for spurious characteristics. A switched doubler bank shown in Figure 5.55 is a possible alternative. It allows using the input switch at much lower (two times) frequencies where it normally demonstrates better isolation characteristics. Adding switched bias amplifiers into filter channels can further increase channel isolation if required. Lower frequencies are obtained using a frequency divider in a very similar manner. The frequency division process offers a 20logN improvement for phase ×2

2–4

1–2

1–4 1–2

Figure 5.53

Using a doubler for frequency extension.

Improving Performance ×2

183

8–12

4–6

8–18 ×3

12–18

Figure 5.54 A combination of multipliers with different multiplication factors is used for less than an octave input bandwidth.

×2

×2

×2

Figure 5.55

Switched doubler bank.

noise and spurs; no subharmonics are created. Note, however, that the divider output waveform is a square wave that is rich in odd-order harmonics. Even harmonics are usually well suppressed. Depending on harmonic requirements, a single lowpass filter may provide an adequate rejection within a full octave as illustrated in Figure 5.56. Similar to the frequency multiplier case, an octave (or wider) coverage can be created from a narrower bandwidth by utilizing different division coefficients as illustrated in Figure 5.57. The synthesizer frequency range can also be extended using a frequency mixer as illustrated in Figure 5.58. As discussed earlier, the frequency mixing process normally does not affect phase noise and spurious characteristics. Moreover, it retains modulation (such as AM, FM, or even IQ modulation) applied

Figure 5.56

A single lowpass filter treats divider odd harmonics within a full octave band.

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Frequency Synthesizers: Concept to Product

÷2

6–9

12–18

4–9 ÷3

Figure 5.57

4–6

Frequency extension with frequency dividers.

1–10 0.01–10 1–10

9.01–10

0.01–1

9

Figure 5.58

Frequency extension with frequency mixing.

to the input signal. Because of this fact, downconversion is often used in signal generators to extend operating frequency range to very low frequencies [26]. Note that the mixer LO and sideband products are conveniently suppressed by a single lowpass filter. The disadvantage of this downconversion scheme is that phase noise (and spurs) is preserved as compared to the 20logN improvement, which potentially could be achieved with a frequency division alternative. Furthermore, intermodulation products are generally introduced that may degrade synthesizer spurious performance.

References [1] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [2] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [3] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [4] Crawford, J. A., Advanced Phase-Lock Techniques, Norwood, MA: Artech House, 2008. [5] Hanneman, C. K., “Method and Apparatus for Decreasing Channel Spacing in Digital Frequency Synthesizers,” U.S. Patent 3,872,397, March 1975.

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[6] Carlini, J., “Practical Developments Using Today’s Fractional Synthesizers,” High Frequency Electronics, September 2009, pp. 34–47. [7] Kroupa V. F., (ed.), Direct Digital Frequency Synthesizers, New York: IEEE Press, 1999. [8] Reinhardt, V. S., “Spur Reduction Techniques in Direct Digital Synthesizers,” IEEE Intl. Frequency Control Symposium Proc., June 1993, pp. 230–241. [9] Karlquist, R. K., “A 3 to 30 MHz High-Resolution Synthesizer Consisting of a DDS, Divide-and-Mix Modules, and a M/N Synthesizer,” IEEE Intl. Frequency Control Symposium Proc., June 1996, pp. 928–933. [10] Chenakin, A., “Frequency Synthesis: Current Solutions and New Trends,” Microwave Journal, May 2007, pp. 256–266. [11] Sadowski, B., “A Self-Offset Phase-locked Loop,” Microwave Journal, April 2008, pp. 116– 124. [12] Messerschmitt, D. G., “Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery,” IEEE Transactions on Communications, September 1979, pp. 1288–1295. [13] Helszajn, J., YIG Resonators and Filters, New York: John Wiley & Sons, 1985. [14] Kotzebue, K. L., “Frequency-Selective Limiting in YIG Filters,” Journal of Applied Physics, Vol. 33, February 1962, p. 747. [15] Suhl, H., “The Nonlinear Behavior of Ferrites at High Microwave Signal Levels,” IRE Proc., Vol. 44, October 1956, pp. 1270–1284. [16] Kemanis, G., and S. Wong, “Analysis of High-Power Effects in Ferrimagnetics from the Point of View of Energy Transfer,” Journal of Applied Physics, Vol. 35, May 1964, pp. 1465– 1470. [17] Carter, Jr., P. S., “Magnetically-Tunable Microwave Filters Using Single-Crystal YttriumIron-Garnet Resonators,” IRE Transactions on Microwave Theory and Techniques, Vol. 9, May 1961, pp. 252–260. [18] Carter, Jr., P. S., “Equivalent Circuit of Orthogonal-Loop-Coupled Magnetic Resonance Filters and Bandwidth Narrowing due to Coupling Inductance,” IEEE Transactions on Microwave Theory and Techniques, Vol. 18, February 1970, pp. 100–105. [19] Harris, D. L., “A 4-40 GHz Wide Bandwidth, Magnetically Tuned Bandpass Filter,” IEEE International Microwave Symposium Dig., May 1990, pp. 1019–1022. [20] Adam, J. D., et al., “Ferrite Devices and Materials,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, March 2002, pp. 721–737. [21] Uher, J., and W. J. R. Hoefer, “Tunable Microwave and Millimeter-Wave Band-Pass Filters,” IEEE Transactions on Microwave Theory and Techniques, Vol. 39, April 1991, pp. 643–653. [22] Makimoto M., and M. Sagawa, “Varactor Tuned Bandpass Filters Using Microstrip-Line Ring Resonators,” IEEE International MTT-S Symposium Dig., June 1986, pp. 411–414. [23] Katzin, P., B. Bedard, and Y. Ayasli, “Narrow-Band MMIC Filters with Automatic Tuning and Q-Factor Control,” IEEE International Microwave and Millimeter-Wave Monolithic Circuits Symposium Dig., June 1993, pp. 141–144. [24] Brown, A. R., and G. M. Rebeiz, “A Varactor-Tuned RF Filter,” IEEE Transactions on Microwave Theory and Techniques, Vol. 48, July 2000, pp. 1157–1160.

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[25] Wong, P. W., and I. Hunter, “Electronically Tunable Filters,” IEEE Microwave Magazine, October 2009, pp. 46–54. [26] Coombs, Jr., C. F., (ed.), Electronic Instrument Handbook, 3rd ed., New York: McGraw-Hill, 1999.

6 Advanced Functions The main function of any frequency synthesizer is to deliver a stable and clean signal. However, there are many other aspects that impact a system where the synthesizer is employed. Frequency synchronization is an important factor that may affect overall system performance. Many applications require not only frequency but also power control and sweep functions. Modulation capability is a desirable feature as well. Many of these features can be implemented with dedicated devices either external or internal to the synthesizer core itself. However, inside any synthesizer there are many circuits that can carry multiple functions and be reused to increase the functionality without a significant increase in cost. This chapter concludes with notes on advanced design options that address frequency synchronization, sophisticated frequency and power control, and various modulation functions.

6.1 Frequency Stability and Synchronization Frequency accuracy is an important characteristic of any frequency synthesizer. Since the synthesizer output frequency is mathematically derived from a reference frequency, the synthesizer accuracy solely depends on its reference. A crystal oscillator is the most commonly used reference source that exhibits excellent frequency stability over short averaging times. Note that any crystal oscillator needs initial frequency calibration. Immediately after the calibration, the frequency starts changing because of thermal stability and aging effects. For example, a temperature drift of 10 ppm (a typical number for a conventional 10-MHz crystal oscillator) corresponds to a 10-kHz error at a 10-GHz output. This can be

187

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Frequency Synthesizers: Concept to Product

quite a significant discrepancy for many applications. Stability can be improved by utilizing TCXO or OCXO devices. However, even the best OCXO still exhibits temperature variations and aging. Atomic clocks (rubidium gas cell, cesium beam, and hydrogen maser) introduce a much higher degree of long-term frequency stability [1–5]. Their operation is based on fundamental physical constants rather than on mechanical dimensions. Atoms exist in discrete states characterized by a specific value of internal energy. An atom can be raised from one energy state to another by exciting it with electromagnetic radiation at a certain frequency determined by

f =

ΔE h

(6.1)

where ΔE denotes the difference between the energy states and h is Planck’s constant. In practice, this phenomenon manifests itself as a resonance-like energy absorption that can be detected by optical means. This principle is used in a rubidium frequency standard that utilizes a rubidium vapor resonating at about 6.8 GHz. This value is determined by the fundamental constants and is extremely stable. The device includes a crystal oscillator, which is essentially locked to the rubidium resonance frequency and carries its stability. The main disadvantage of atomic standards is their complexity and cost. However, there are tens of atomic clocks circling the Earth and available for use by virtually anybody. They belong to satellite-based global navigation systems (such as GPS and GLONASS). For example, a GPS (global positioning system) satellite broadcasts a signal that is extracted from an on-board high-precision atomic source. A GPS receiver processes the signals from four (or more) satellites to calculate the device position (i.e., latitude, longitude, and altitude) as well as local time with high accuracy. As a side benefit to this process, the receiver produces a timing pulse once each second. Thus, the output of the GPS receiver is a 1-pps (pulse per second) pulse stream that can be used to calibrate or adjust (discipline) the synthesizer reference frequency. In general, the control circuit is a phase-lock-loop that compares two 1-pps signals and generates an error voltage to adjust the reference oscillator frequency. However, because of long time constants involved, frequency comparison is often done digitally (e.g., by calculating a number of pulses during a certain time interval) with the help of a microcontroller as illustrated in Figure 6.1. The microcontroller computes the frequency difference and controls a DAC to generate a proper error signal. As a result, the reference oscillator exhibits virtually the same long-term stability as the high-precision atomic clocks employed by the GPS. The GPS receiver is a simple circuit that can be easily incorporated into a frequency synthesizer if desired. GPS reception is line of sight (i.e., the antenna must be installed outside a

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GPS antenna 1 pps GPS receiver Micro controller OCXO

÷R

DAC

Reference

Figure 6.1 GPS-disciplined frequency reference.

building with a clear view of the sky). Thus, the GPS signal is primarily utilized as a frequency standard for calibration and verification purposes. In many cases, it is important to provide not the best absolute accuracy but rather frequency synchronization between individual devices within a system. This is illustrated in Figure 6.2 by measuring the output frequency of a synthesizer with a spectrum analyzer. The synthesizer output frequency is set (commanded) to 10 MHz. Note that the spectrum analyzer shows about a 1.8Hz discrepancy because of its reference mismatch. If we lock the synthesizer and spectrum analyzer references to each other (regardless of what the “primary” standard is), the synthesizer frequency will be perfectly centered on the spectrum analyzer screen showing no frequency error. Thus, two devices will work in unison even if their references are not perfectly accurate. Therefore, a sophisticated synthesizer design has to provide the ability to adjust its internal reference and also lock it to an external signal. Figure 6.3 shows a block diagram of a reference module that provides these functions. It consists of a high-stability 10-MHz OCXO that drives other synthesizer modules. The output of the OCXO is routed to the synthesizer front panel through a buffer amplifier. The buffer amplifier must provide sufficient isolation to protect the internal OCXO from external contaminants. The OCXO free-running frequency is controlled by a DAC that provides initial frequency calibration and further adjustment to compensate for aging. The module also includes an external reference detector and PLL circuit driven by an external 10-MHz signal. When the detector detects an external signal of adequate amplitude, it automatically connects the OCXO to the phase detector output. The OCXO locks to the external signal, provided that it is within the OCXO locking range. The loop filter bandwidth should be set at relatively low frequency (e.g., 25 Hz) to avoid

190

Frequency Synthesizers: Concept to Product 10 MHz Output Locked / Unlocked dBm Ext Ref ON Ext Ref OFF 20 1 2-1 0 −20 −40 −60 −80 −100 −120 −140 −160 −180

Start: 10.0000 MHz Res BW: 1 Hz

Mkr Trace 1 Ext Ref ON 2-1

Ext Ref OFF

Stop: 10.0000 MHz Sweep: 8.00s

Vid BW: 1 Hz

X-Axis 10.0000 MHz

Value 0.10 dBm

1.8000 Hz

0.11 dBm

Notes

Figure 6.2 The synthesizer output frequency is centered on a spectrum analyzer screen once both instruments are synchronized.

DAC REF IN

Reference REF OUT OCXO

10 MHz

10 MHz

Figure 6.3 A block diagram of a synthesizer reference module.

the influence of the external source on the OCXO phase noise. Therefore, the OCXO is disciplined by the external signal yet retains its own low phase noise characteristics. If the external signal is not present, the OCXO connects back to the DAC.

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6.2 Frequency Control A generic frequency synthesizer is intended to output a frequency set by a proper frequency command. More sophisticated designs include other frequency control options such as blanking, frequency sweep, and list mode, as described next. 6.2.1

Blanking

What happens when a synthesizer is commanded to change its frequency? In a PLL design, the generated frequency follows the VCO tuning voltage change. Depending on the dynamic characteristics of a particular loop filter, the VCO can pass on the destination frequency and then come back, exhibiting ringing. Even in a direct analog synthesizer, the frequency transition is not instantaneous. Thus, the synthesizer exhibits a frequency uncertainty while it transitions to the programmed frequency. This uncertainty may result in unexpected behavior of a system where the synthesizer is utilized. For example, when a frequency synthesizer is employed as an LO source in a receiver system, this uncertainty may produce uncontrolled spurs at the IF output. The receiver has to ignore (turn off ) the IF output during the LO frequency change. Another way to protect the system is to turn off the synthesizer output itself as shown in Figure 6.4. This function is called blanking. It is realized by adding a switch at the synthesizer output as depicted in Figure 6.5.

ΔF

f

f2

f1 t1

t2

t

t1

t2

t

P P0

Figure 6.4 Synthesizer output is blanked during frequency transition.

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Frequency Synthesizers: Concept to Product

FNEW

RF power OFF Microcontroller

Lock

S Q R

Figure 6.5 The blanking function is realized by controlling a switch at the synthesizer output.

Blanking is initiated by setting the control flip-flop to logic high (or low). The setting pulse is generated by a microcontroller when a new frequency setting command arrives. The flip-flop disconnects the synthesizer output and remains in this state until the output signal reaches the destination frequency within a preset window (e.g., ±1 MHz or ±50 kHz). The reset signal is normally generated by a lock indicator and can be further processed by the microcontroller (e.g., an extra time delay can be added to provide an adequate margin). If the synthesizer does not lock to a desired frequency, the lock indicator generates an error signal and the synthesizer remains blanked. The blanking function can be disabled by the same microcontroller by sending a corresponding command (blanking on/off ) as desired. 6.2.2

Frequency Sweep

It is often desired to linearly change the output frequency within certain limits. This function is called frequency sweep and is widely used in test-and-measurement applications for characterizing various devices across their operating frequency range [6, 7]. The frequency sweep is a mandatory function in many instruments such as network and spectrum analyzers. The frequency sweep is defined by setting start frequency, stop frequency, and sweep time. There are two basic modes: continuous and stepped sweeps. The continuous (analog) sweep is realized by changing the VCO tuning voltage directly (i.e., breaking the phaselock-loop) with a sawtooth generator or a DAC as depicted in Figure 6.6. This mode requires linear and repeatable tuning characteristics and is commonly used in conjunction with YIG-tuned oscillators. However, a frequency error is always present since the oscillator remains unlocked during the sweep. Thus, the continuous sweep is used in applications (e.g., scalar network analyzers) where

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Figure 6.6 Continuous frequency sweep is realized by changing a tuning voltage with a DAC.

a certain frequency error can be tolerated. Various techniques exist to lock the oscillator at one or more points across the sweep range for better accuracy. The stepped (also called discrete or digital) frequency sweep is realized by changing the synthesizer output frequency in discrete frequency increments (steps) as illustrated in Figure 6.7. It assumes that the VCO is locked at every discrete point across the sweep range. Hence, this mode provides significantly better frequency accuracy and is used in precise instruments such as vector network analyzers. The digital sweep function poses a serious challenge for synthesizer switching speed characteristics. For example, assume that we are making a 401-point digital sweep measurement (e.g., a network or spectrum analysis) using a source with 25-ms switching time (this is a typical number for a YIG-based synthesizer). In this case, the dead time per one sweep measurement exceeds 10 seconds. This delay may not be satisfactory in repetitive measurements (such as automated RF IC tests). Note that if we use a synthesizer with 100-μs switching, the dead time is reduced to about 40 ms as illustrated in Table 6.1. This is quite a significant throughput improvement. f

Continuous sweep

f STOP

Stepped sweep f START t START

t STOP

Figure 6.7 Continuous and stepped frequency sweeps.

t

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Frequency Synthesizers: Concept to Product Table 6.1 Measurement Dead Time as a Function of Switching Speed

6.2.3

Switching Time

Number of Points

Measurement Dead Time

25 ms

401

~10 seconds

0.1 ms

401

~0.04 second

List Mode

The digital sweep mode normally assumes that the synthesizer steps linearly in the frequency domain, but what if the frequency has to change with a different algorithm? A list mode provides better flexibility. The idea is to create a table (list) of frequencies and store it in the synthesizer’s memory. The list is executed by sending a proper command or by applying a trigger signal, which is a voltage pulse, to a corresponding control line. Once the synthesizer’s microcontroller detects a trigger pulse, it commands the synthesizer to move from one frequency to another according to the programmed list. Alternatively, the synthesizer can go to the next frequency, stop there, and wait for the next trigger pulse; then the process repeats. What do we gain using the list mode instead of continuously sending regular frequency setting commands? Note that the synthesizer needs time to receive a new frequency command and make all necessary calculations according to an employed tuning algorithm. By setting a list of frequencies that we want to jump between, we can precalculate and memorize all necessary parameters required to control individual components of the synthesizer. Thus, all calculations can be avoided by the time we execute the list. This results in a significant throughput improvement compared to normal programming. Moreover, in list mode one can control not only frequency but also output power level and other functions while stepping through the list, as shown in Figure 6.8.

6.3 Output Power Control For a simple synthesizer design, the output power can vary across the operating frequency range because of individual component gain variations. More sophisticated designs bring the ability to equalize the output power response and also change the power level as needed. A synthesizer’s output power can be controlled in many different ways. Some popular options are reviewed next. 6.3.1

Open-Loop Control

RF output power can be controlled with a built-in attenuator and a DAC as depicted in Figure 6.9. The DAC generates a proper voltage for any given fre-

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Figure 6.8 List mode allows the controlling of synthesizer output frequency, power level, dwell time, power mute, and pulse modulation settings for every list point. (Courtesy of Phase Matrix, Inc.)

DAC

Temp sensor

CPU and Memory

Figure 6.9 RF output power is controlled with a built-in attenuator and a DAC.

quency to ensure a flat output response across the entire operating frequency range. The DAC values are generated during a calibration routine and are stored in a look-up table. The output power can be changed within certain limits (set by the available attenuator dynamic range), adding one more dimension to the cali-

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Frequency Synthesizers: Concept to Product

bration table. Note that the synthesizer output circuit may include many devices (VCO, dividers, multipliers, amplifiers, filters, and switches) that exhibit temperature variations. Thus, the synthesizer may also include a temperature sensor to provide further correction if required. By employing a sophisticated interpolation routine, this technique provides reasonably flat and repeatable output power characteristics across operating frequency and temperature ranges. Note that the output power is set almost instantaneously. Therefore, the open-loop method is well suited for fast switching applications. The main disadvantage of this method is limited accuracy caused by component temperature variations. The output power delivered to an external load also depends on how well the synthesizer and load impedances are matched. 6.3.2

Closed-Loop Control

Better (more accurate and repeatable) power control is achieved with a closedloop automatic level control (ALC) technique illustrated in Figure 6.10. The output power is sampled with a directional coupler and routed to an RF detector. The detector generates a voltage proportional to the output power. This voltage is compared to a reference voltage generated by a DAC. An error signal controls the attenuator, thus closing the loop. In other words, the RF detector continuously measures and adjusts the output power to a value set by the DAC. This configuration ensures a precise output power level regardless of the load mismatch. Furthermore, temperature variations of the synthesizer components are also taken into account. The only significant source of temperature instability is the RF detector itself (and, to a smaller degree, the directional coupler). Temperature variations of the detector are further reduced by controlling (i.e.,

DAC

Figure 6.10 Closed-loop ALC.

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stabilizing) its temperature. The power control range can be extended by adding an electromechanical step attenuator if needed. 6.3.3

Power Equalizer

In general, it is possible to create not only flat but also custom output power responses by storing appropriate DAC values in the synthesizer memory as illustrated in Figure 6.11. This option allows the creating of virtually any frequencyto-power profile (within the available power control range) similar to that accomplished in old-style sound equalizers. Such an equalizer can be very helpful to compensate for frequency roll-offs as well as other irregularities of the devices external to the synthesizer. 6.3.4

Power Sweep

Synthesizer output power can also be swept between desired power levels. This function (called power sweep) is used in characterization of output power and linearity characteristics (P−1 dB compression point, IP3 ) of various devices such as transistors, amplifiers, mixers, and many others. The synthesizer output power can be swept continuously or in steps. It can also be a parameter to be controlled in a list mode. In this case, any desired output power profile can be created, stored, and executed.

Figure 6.11 Power equalizer. (Courtesy of Phase Matrix, Inc.)

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6.3.5

Frequency Synthesizers: Concept to Product

Power Mute

Output power can be completely turned off. This function is called power mute and is realized by controlling a switch (or a chain of switches) at the synthesizer output. The output power amplifier can also be turned off (as illustrated in Figure 6.12) to minimize signal leakages and reduce DC power consumption while the synthesizer is in mute mode. Note that the VCO and PLL core should remain biased to avoid any frequency disturbance when the synthesizer returns to normal operation.

6.4 Modulation Microwave systems utilize various modulation modes ranging from simple pulse, amplitude, frequency, and phase modulation to complex digital modulation formats. Although modulators are usually realized as external devices, they can also be incorporated into a frequency synthesizer core. This results in a more cost efficient and versatile design. The most commonly used modulation schemes are reviewed next. Further details on modulation theory and implementation techniques are provided in [7–11]. 6.4.1

Pulse Modulation

Pulse modulation is probably the simplest modulation form. It is achieved by switching the output signal on and off in accordance with the applied modulating pulses. The result is a sequence of RF pulses that replicate (or tend to replicate) the input modulating signal. The minimum RF pulse width, rise time, fall time, and overshoot are important characteristics that define how well the modulating signal is replicated. Typical rise time and fall time numbers required are in the order of 10 nanoseconds. Pulse modulation on/off ratio is another critical parameter. A typical specification is 80 dB or higher. The modulating signal frequency (also called rate) can be between DC and several megahertz.

Mute

Figure 6.12 The output power amplifier is turned off to reduce signal leakages and DC power consumption.

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Pulse modulation is practically implemented by inserting a switch (or a chain of switches for a higher on/off ratio) into the synthesizer output path. The switch can be built using pin-diodes or FET devices that support nanosecond switching. Alternatively, the pulse modulator can be conveniently combined with a switched filter bank used for harmonic (or subharmonic) rejection. The idea is to reduce the design complexity and cost by utilizing the same devices for both functions. Furthermore, no additional loss is introduced. In this case, the pulse modulator incorporates a digital decoder (as shown in Figure 6.13) to control the switches in such a manner that they will provide the highest possible on/off ratio for any given frequency subband. The isolation between individual signal paths is a critical design parameter. Another concern is the leakage of the modulating signal, called a video feedthrough, to the synthesizer output. This leakage can be controlled by adding a highpass filter as depicted in Figure 6.14.

Pulse

Decoder Subband

Microcontroller

Figure 6.13 A pulse modulator is integrated into a switched filter bank.

Pulse

Figure 6.14 A highpass filter at the synthesizer output suppresses the modulating signal leakage.

200

6.4.2

Frequency Synthesizers: Concept to Product

Amplitude Modulation

Amplitude modulation (AM) historically has been one of the most popular methods for carrying information via RF frequencies. It is realized by varying the output signal amplitude in accordance with an applied modulating signal. The simplest way to implement AM is to control the insertion loss of an attenuator inserted into the synthesizer output circuit. This can be naturally combined with an open-loop amplitude control as depicted in Figure 6.15. The synthesizer is first commanded to set a desired output power level by programming DAC voltage. Then a modulating voltage is applied over the DAC voltage to vary the output signal around its nominal value. Naturally, the output power cannot be set at its highest (or lowest) level since certain headroom is needed to allow further power changes. The maximum power variation (which can also be expressed in terms of modulation index or depth) is achieved by setting the output power level in the middle of its control range. Another important requirement is linearity, since the modulator must translate the modulating signal with minimal distortion. This may further limit a realizable modulation depth. Various linearization techniques can be applied to minimize AM signal distortion. In some cases, it is desirable to implement not a linear but a logarithmic modulating scale, meaning that the output power changes in dB per volt. This mode is utilized for large power variations (e.g., for simulation of rotating antenna patterns) and is called deep AM. Alternatively, amplitude modulation can be implemented by summing the modulating signal into the ALC loop as shown in Figure. 6.16. In general, the ALC-based amplitude modulation offers better linearity and repeatability characteristics. However, the modulation depth may be limited by the available ALC dynamic range, which, in turn, depends on the utilized detector. The maximum modulating signal rate is also lower compared to the open-loop alternative because of the settling time of the closed-loop ALC system.

AM

Σ

DAC

Figure 6.15 Amplitude modulation is combined with an open-loop amplitude control.

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201

Σ

DAC

Figure 6.16 Amplitude modulation can be realized by summing the modulating signal into the ALC loop.

6.4.3

Frequency and Phase Modulation

Frequency modulation (FM) is another popular form of analog modulation that offers better signal immunity compared to AM. The process of producing a frequency-modulated signal involves the variation of the synthesizer output frequency in accordance with the modulating signal. The frequency bandwidth where the synthesized signal fluctuates is proportional to the peak amplitude of the modulating signal and is called frequency deviation. FM can also be described by modulation index, which is the ratio of the maximum frequency deviation to the frequency of the modulating signal. Note that we can vary not only the frequency but also the phase of the synthesized signal, thus producing phase modulation (PM). Both processes are quite similar, since in both cases we vary the argument (the angle) of the same sine function as illustrated in Figure 6.17. Hence, the angular modulation is a

Angular modulation FM VOUT = A 0 sin( ω0 t + ϕ ) Figure 6.17 Frequency and phase modulation.

PM

202

Frequency Synthesizers: Concept to Product

more general case that represents both FM and PM. The difference is not in the output signal waveform but rather in the modulator circuit configuration, that is, what parameter (frequency or phase) is directly proportional to the amplitude of the modulating signal. Since the instantaneous angular frequency is mathematically the time derivative of the phase, it is possible to convert FM to PM (and vice versa) by adding an integrator (or differentiator) circuit into the modulating signal path. How can we modulate the synthesizer output frequency? From first glance, it is quite straightforward—we can simply modulate (i.e., change) the VCO tuning voltage around the value where it is settled. The problem, however, is that the PLL will tend to correct any voltage change that we introduce. Most likely, we will lose this battle unless we change the tuning voltage so fast that the PLL will not be able to react to the change. This is exactly the idea that stands behind a so-called wideband FM modulation mode. The FM modulator is built by adding a circuit (e.g., an operational amplifier) that sums an external modulating signal with the control voltage delivered by PLL as depicted in Figure 6.18. The PLL remains locked all the time, thus ensuring that the overage output frequency remains correct. For proper operation, the modulating signal rate has to be well above the loop filter bandwidth. Thus, the PLL filter bandwidth is adjusted (narrowed down) to allow lower modulating rates. As a result, the phase noise increases when FM is enabled. Typical achievable modulating rates range from a few kilohertz to tens of megahertz. What if we need to apply a lower-frequency modulating signal? Obviously, we have to further decrease the loop filter bandwidth, which may not always be possible because of prohibitory high VCO free-running phase noise at low frequency offsets. An alternative solution is to modulate not the VCO but the reference oscillator as shown in Figure 6.19. If the modulating signal rate is sufficiently low, the PLL will track the reference frequency change and translate the modulation to the VCO output. Therefore, in this case, the PLL works for us. This mode is often called narrowband FM since the modulating frequency must f REF

Σ

VCO

f OUT

FM

÷N

Figure 6.18 Frequency modulation is realized by modulating the VCO tuning voltage.

Advanced Functions FM

REF

VCO

203 f OUT

÷N

Figure 6.19 A modulating signal is applied to the reference oscillator.

be within PLL filter bandwidth. The loop filter bandwidth should be set as wide as possible to allow higher modulating rates. Typical rates start from nearly DC to a few tens of kilohertz. Thus, the narrowband mode complements its wideband counterpart to extend the overall modulating frequency range. A disadvantage of this technique is low achievable deviation caused by very low tuning sensitivity of the reference oscillator. Although the reference frequency deviation is multiplied up by the PLL at the same 20logN rate (once again, the PLL works for us), the synthesizer output deviation may be insufficient. A higher deviation can be achieved by changing not the reference frequency but rather its phase as depicted in Figure 6.20. This represents a classical phase modulation; however, as we agreed, both forms are interchangeable. Practical implementation requires a phase shifter that can be purchased or can be built using discrete devices such as varactor diodes. An interesting solution is to control the division ratio of a frequency divider inserted into either the PLL reference or feedback path as illustrated in Figure 6.21. The divider has to be a high-resolution device such as a fractionalN divider or DDS. The modulating signal is first digitized by an analog-todigital converter and then is summed with the DDS tuning word to vary the DDS’s output frequency. Since the DDS offers exceptionally small frequency increments and a fast update rate, a simple yet high-performance FM (or PM) modulator can be constructed. f REF

ϕ

VCO

PM ÷N

Figure 6.20 A phase shifter provides a phase modulation function.

f OUT

204

Frequency Synthesizers: Concept to Product f CLK

f OUT

VCO

DDS

CPU

÷N

ADC FM Figure 6.21 Frequency modulation is realized by controlling the DDS output frequency.

6.4.4

Complex Modulation

More effective modulation formats are possible by simultaneously varying both amplitude and phase. The simplest way to visualize such a complex signal is to draw it as a vector on a polar diagram. The amplitude and phase are represented as the length and the angle of the vector as shown in Figure 6.22. In digital communication systems, such a signal is expressed in I (in-phase) and Q (quadrature) terms, which are projections of the signal vector on a corresponding orthogonal axis. Therefore, the amplitude and phase modulation assumes the change of the signal vector, which can be conveniently accomplished by varying two independent IQ components. Hence, such a complex modulation is called vector or IQ modulation. Vector modulation can be applied directly at RF frequencies by utilizing an IQ modulator such as that described in Chapter 2. It consists of two identical mixers driven with a 90° phase shift at their LO ports as shown in Figure 6.23. Amplitude

Phase

Q I

Figure 6.22 A signal is presented as a vector on a polar diagram.

Advanced Functions

205

DC offset

Q LO

RF

90° hybrid

DC offset

I I Calibration module Q

Figure 6.23 A vector modulator is calibrated by adjusting IQ-components and mixer DC offsets.

The baseband data signals are applied directly to the IF ports, upconverted, and summed together with no phase shift between them. The resulting output is an IQ-modulated signal at the same carrier frequency as the LO. The quality of the synthesized signal can be tested by applying two baseband signals of the same frequency and amplitude with a 90° phase shift with respect to each other. For a perfect modulator, only one sideband should be present. However, in reality, the output signal contains another sideband because of imperfect amplitude and phase balance. Furthermore, a LO leakage also takes place. The undesired sideband can be suppressed (cancelled) by adjusting the amplitude and phase of the applied IQ signals. The LO leakage can be controlled by adjusting DC offset voltages for the diodes used in the balanced mixers. Therefore, it is generally possible to calibrate the modulator characteristics to a degree where it can be practically utilized. The difficulty is that this calibration has to be implemented at many frequencies across the entire operating range. Moreover, the calibration has to survive over time and temperature changes. Thus, achieving a good image and LO leakage suppression (e.g., 40 to 50 dB or better) for a broadband, highfrequency, direct IQ-modulator is a very challenging task. An alternative solution is to create a desired IQ-modulated signal at a lower, fixed frequency and upconvert it to microwave frequencies as illustrated in Figure 6.24. Obviously, it is much easier to achieve better cancellation of undesired products at a single (and lower-frequency) point. However, the difficulty now moves to the upconversion side. We still need to remove the undesired

206

Frequency Synthesizers: Concept to Product I

RF

IQ-modulator Q LO 1 (fixed)

LO 2 (variable)

Figure 6.24 Upconversion technique.

sideband and LO leakage posted by the second (regular) mixer. However, since the product separation is much larger (compared to the direct IQ-modulation), a hardware filter can be used. For a broadband operation, a YIG-tuned filter is a simple and effective solution. The disadvantage of the YIG filter is slow tuning speed and relatively narrow passband that can be insufficient in certain applications. A switched filter bank offers better characteristics. However, it requires a larger number of channels (compared to devices used for harmonic and subharmonic filtering) and hence is hardware extensive. Thus, implementing a highquality, broadband IQ-modulation is a good exercise to test engineering skills.

References [1] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [2] Vanier, J., and C. Audoin, The Quantum Physics of Atomic Frequency Standards, Bristol, U.K.: Adam Hilger, 1989. [3] Hellwig, H., “Time and Frequency Applications,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 40, September 1993, pp. 538–543. [4] Bregni, S., “Clock Stability Characterization and Measurement in Telecommunications,” IEEE Transactions on Instrumentation and Measurement, Vol. 46, December 1997, pp. 1284–1294. [5] Johansson, S., “Counter/Timer Accurately Calibrates Frequency,” Test & Measurement World, May 2002, pp. 23–28. [6] Witte, R. A., Spectrum and Network Measurements, Atlanta, GA: Noble Publishing, 2001. [7] Coombs, Jr., C. F., (ed.), Electronic Instrument Handbook, 3rd ed., New York: McGraw-Hill, 1999. [8] Terman, F. E., Electronic and Radio Engineering, New York: McGraw-Hill, 1955. [9] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [10] Crawford, J. A., Advanced Phase-Lock Techniques, Norwood, MA: Artech House, 2008. [11] Gentile, K., “Fundamentals of Digital Quadrature Modulation,” RF Design, February 2003, pp. 40–47.

About the Author Alexander Chenakin graduated from Kiev Polytechnic Institute, Ukraine, in 1992 (engineer diploma) and obtained his doctorate degree (kandidat nauk) in 1996. Since then, he has worked in a variety of technical and managerial positions around the world. He has led the development of advanced products for Celeritek, Inc., Nextek Microwaves & RF, Inc., Micro Lambda Wireless, Inc., General Electronic Devices, Inc., and other companies. He also founded Critical Design Company, LLC, a consulting firm specializing in the design of low phase noise microwave oscillators and frequency synthesizers. Dr. Chenakin is now the vice president of the Signal Sources Group at Phase Matrix, Inc., where he oversees the development of advanced frequency synthesizer products for testand-measurement applications. Dr. Chenakin’s professional achievements have been widely presented in trade publications and international conferences. He also holds a U.S. patent. He received the best contribution award at the 2009 ARMMS Conference for his work on fast-switching frequency synthesizers. He was an invited lecturer at the 2008 IEEE International Frequency Control Symposium tutorials. Dr. Chenakin is also a senior IEEE member.

207

Index Balun 61 Bank switched doubler 182, 183 switched amplifier 180 switched filter 6, 63, 156, 178–182, 199, 206 switched VCO 181, 182 Bead, ferrite 130, 131 Blanking 191, 192 Boltzmann’s constant 43, 124 Buffer amplifier 110, 189

Accumulator, phase 32, 33, 34, 152, 153 Aging 3, 4, 187-189 Alumina 46, 90, 93, 94, 97, 98 Aluminum 94, 97, 101 Aluminum nitride 51, 93, 94 Amplifier auxiliary 56 buffer 110, 189 chain of 159 defective 139 feedforward 54 gain 118, 165 in compression 8 input 124, 139, 140, 181 intermodulation distortion 55 loop 36 low-noise 57 main 55, 56 operational 112, 118, 122, 124, 141, 165, 172, 202 output 53, 113, 140 power 181, 198 RF 113, 118 transistor 57 transposed-gain 55 switched bank 180 switched bias 182 unused 181 Amplitude modulation 59, 200, 201 AM-to-PM conversion 59, 70, 71 Analog-to-digital converter 167 AXIe 24

Carrier 5, 10, 43, 57, 73, 94, 97, 98, 144, 205 Characteristic impedance 87, 88, 90, 91, 100 Charge pump built-in 118 circuit 77, 78 current 79, 118, 126, 137, 171 integrated 79, 111 output 81, 113, 122, 124 pulses 122, 124 Chassis 21–23, 106, 107 Control interface 3, 7, 16, 124 Conversion AM-to-PM 59, 70, 71 analog-to-digital 154 frequency 38 gain 64 loss 59, 64 signal 51 sine-to-square wave 121 Coplanar waveguide 91, 92, 103, 107 Copper 94, 95, 97, 99 Counter 66-68, 79, 142, 170, 209

210

Frequency Synthesizers: Concept to Product

Delta-sigma modulator 154, 155 Detector coherent amplitude 170 frequency 169 frequency-difference 168 frequency-sensing 169 lock 79, 81, 111, 126, 129, 138, 165, 169, 170 output 74-76 phase (see phase detector) phase-frequency 76-79, 111 quadrature 170 reference 189 RF 196 sampling 75 state 66, 67 Digital-to-analog converter 31, 166 Diode antiparallel 60, 71 balanced 60 bridge 62 characteristics 60, 62 impedance 59, 60 light-emitting 126 limiter 8 mixer 71 multipliers 64 nonlinearity 59 pair 60, 62, 71, 72 pin 180, 199 Schottky- 59 Schottky-barrier 70 single- 59, 60, 71 step recovery 63, 161 varactor 49, 64, 69, 110, 203 Discontinuity 87, 95, 101–103, 153 Discriminator, frequency 56, 57, 168, 170 Dispersion 90 Doubler balanced 60, 61 double-balanced 62 frequency 6, 58 output 58 single-diode 59 switched bank 182, 183 transistor 64 Edge-coupled 94 Edge-mount 102 Edge-plated 103, 105

EMI 105, 106 Enclosure 90, 97, 101, 103, 135, 136 Feedforward amplifier 54 Ferrite bead 130, 131 FET 54, 57, 64, 180, 199 Filter bandpass 54, 90, 97, 156, 182 bandstop 126 channels 30, 180, 182 edge-coupled 94 EMI 105, 106 fixed-frequency 63 harmonic 182 highpass 113, 118, 159, 199 lowpass 6, 31, 33, 38, 69, 74, 75, 113, 118, 122, 124, 129, 170, 178–180, 183, 184 L-type 105 multistage 179 output 178 passband 159, 178 PLL 4, 36, 126, 137, 153, 171, 202, 203 printed 115, 141 response 178 schematic 122 settling 25 switched bank 6, 63, 156, 178-182, 199, 206 tunable 6, 178, 182 varactor-tuned 179 YIG 178, 206 YIG-tuned 178, 180, 206 Flip-flop 18, 19, 65, 66, 76, 77, 192 Fractional-N 2, 38, 149, 151-155, 167, 203 Frequency accuracy 3, 187, 193 Frequency acquisition 4, 5, 164, 167 accuracy 167 aid 75, 76, 171 initial 75, 78, 149, 166, 167, 171 Frequency counter 142, 170 Frequency deviation 201, 203 Frequency discriminator 56, 57, 168, 170 Frequency divider 6, 26, 64, 70, 157, 182, 203 analog 69 feedback 160 fractional 34 frequency extension with 184

Index output 151 programmable 4 regenerative 69 with a variable frequency division ratio 35 Frequency doubler 6, 58 Frequency extension 149, 181, 182, 184 Frequency mixer 12, 33, 69, 74, 183 Frequency modulation 201, 202, 204 Frequency stability 41, 50, 187, 188 Frequency sweep 191–193 Frequency synthesizer classes 2 concept 1, 2 core 198 designs 46, 50, 89, 98, 129 generic 191 incorporated into 188 indirect 35 microwave 41, 87 modules 20, 21 multiloop 164 phase noise characteristics of 176 schemes 25 Frequency tripler 62, 182 Fused silica 52, 93, 94 GaAs, 54 Gain active device 42–44 amplifier 118, 122, 165 block 113, 118 budget 113 compression 42 conversion 64 equalizers 12 loop 54, 167 profile 122 roll-off 12 small-signal 42 transistor 53 transposed 51, 55, 56 variations 194 General purpose interface bus 21 Gold 94, 95, 97, 99 HEMT 54 Housing 14, 101–105, 135, 136 I2C 20 Image-reject mixer 72, 157

211 Impedance 3, 90 50-ohm 90 characteristic 87–91, 100 diode 59, 60 high 18, 118, 120 input 120 line 90 load 13, 89, 196 output 13, 89 proper 95 source 89 varactor’s 179 Interface, control 3, 7, 16, 124 Jitter 3, 8, 120 Kovar 94, 97 Leeson’s equation 43 Linearization 45, 54, 200 List mode 191, 194, 195, 197 Local oscillator 1, 23 Lock analog 126 detection circuit 76 detection function 170 detector 79, 81, 126, 129, 130, 138, 169, 170 digital 126, 129, 137 false 164 frequency 35, 57, 82, 165, 170 indicator 14, 16, 170, 192 out of 75, 77 monitoring 149, 169 phase 128, 129, 170 PLL 165, 171 state 128 time 131 Loop filter bandwidth 36, 122, 150, 155, 173, 174, 189, 202, 203 capacitor 171 components 14, 82, 141, 171 design 124 dynamic characteristics 112 external 118 output 141 parts 141 phase margin 126 PLL 141 rejection 149

212

Frequency Synthesizers: Concept to Product

Loop filter (continued) specific configuration 122 topology 122 values 122 Loss conductive 91, 94, 95 conductor 90 conversion 59, 64, 71 dielectric 47, 94 in frequency resolution 68 insertion 52, 115, 116, 180, 200 in the input switch 180 in the metal walls 46 line 52 overall 42 power 88 radiation 46, 90 resistive 90, 130 resonator 42, 53 return 3, 13, 14 signal 64, 181 switch 181 tangent 93 LXI 23, 24 Microcontroller 15, 136, 170, 188, 192, 194, 199 Microstrip line 46, 89–92, 97, 99 Mixer, frequency 12, 33, 69, 74, 183 Modulation amplitude 59, 200, 201 analog 201 angular 201 capability 187 complex 204 depth 200 formats 198, 204 frequency 201, 202, 204 functions 187 index 200, 201 IQ 73, 183, 204, 206 modes 15, 198 options 14 phase 58, 198, 201, 203, 204 pulse 195, 198, 199 schemes 198 sources 15 theory 198 vector 73, 204 Modulator

delta-sigma 154, 155 FM 202 IQ 73, 74, 204, 206 pulse 199 single-sideband 72, 73 vector 205 Molybdenum 51, 94, 97 Noise density 125 Noise figure 45, 113 Noise voltage 124 Nickel 94, 95, 97 Operational amplifier 112, 118, 122, 124, 141, 165, 172, 202 Oscillator chain of 176 ceramic resonator 46 circulator-based 53, 54 components 42, 44, 50 crystal 3, 50, 175, 186, 188 design 53 dielectric resonator 46 feedback 42, 51, 53 free-running 173, 174 frequency-locked 57 fundamental 54 GaAs-based 54 half bandwidth 45 high-frequency 25, 35 local 1, 23 low-noise 54, 56, 176, 177 microwave 42-45, 53 noise behavior 43 nonlinearities 45 optoelectronic 51, 52 output frequency drift 50 output spectrum 44 parameters 43 phase noise 41–43, 45 reference 50, 175, 176, 188, 202, 203 resonant element 57 sawtooth 166 scheme 53 search 166 selection 149 signal-to-thermal noise ratio 44–46 time-stable 50 topology 53 transistor 54 transposed gain 51, 56

Index varactor-tuned 49 voltage-controlled 1, 49, 50 wideband 53 YIG- 49, 172-175, 179, 181 YIG-tuned 49, 53, 166, 172, 192 Parallel interface 16, 17, 33 Phase accumulator 32, 33, 34, 152, 153 Phase detector comparison frequency 79, 111, 122, 126, 149-151, 155, 156, 168, 176 current 171 cycle 126 DC errors 57 dead-zone 122 failure 141 flip-flop 77 input 36, 67, 126, 151 leakages 122 linearity 154 noise 112 output 112, 141, 153, 154, 189 polarity 79, 82, 124, 137, 141, 165 residual noise 151 schemes 76 sensitivity 56 voltage spike 154 Phase-lock-loop block diagram 36 fractional-N 2 synthesizers 96 techniques 35 Phase margin 122, 125, 126 Phase modulation 58, 198, 201, 203, 204 Phase shifter 203 Phase truncation 33 Photodetector 51, 52 Plating 103, 105, 134 Power supply 14, 15 Prescaler division coefficient 37, 112, 137 division ratio 67, 68, 112 dual-modulus 67, 68, 79 high-frequency 60, 67, 156, 176 input 68 maximum output frequency 112 output 67, 79, 112 Printed circuit board 14, 46, 61, 62, 87, 91, 98, 109, 133 Pulse modulation 195, 198, 199

213 PXI 22-24 Q-factor 43, 46, 47, 49-53, 56, 130, 172 Return loss 3, 13, 14 RS-232 20 Sapphire 25, 47, 56, 57, 93, 94 Serial peripheral interface 17 Shielding 14, 87, 101, 103, 135, 159 SiGe 54 Silicon 44, 49, 54, 55 Silkscreen 100 Silver 94, 95 Slotline 92, 93 Soldering 97, 101 Solder mask 100, 101 Spectrum analysis 193 analyzer 3, 143, 144, 158, 189, 190, 192 contaminated 31 noise 154 of the synthesized signal 32 output 8, 34, 42, 44, 61, 63, 66, 75, 153 synthesizer 5, 7 typical 9, 62 Step recovery diode 63, 161 Stripline 91, 99 Substrate 46, 51, 89–94, 96–99 Testing 141 Transistor bipolar 44, 49, 54, 56 characteristics 64 DC bias 64 doubler 64 field-effect 53 gain 53 multiplier 64 silicon-bipolar-junction Troubleshooting 100, 109, 138, 140, 141 Triplate 91 Tripler, frequency 62, 182 Tungsten copper 94, 97 Universal serial bus 20 Varactor diode 49, 64, 69, 110, 203 Vector modulator 205 Via holes 91, 92, 100, 102

214

Frequency Synthesizers: Concept to Product

VSWR 13 VXI 21-23 Waveform arbitrary 35 construction 33 output 2, 60, 61 signal 3, 31, 33, 58, 64, 202 square-wave 6, 65, 183 synthesized 31 Wilkinson divider 181

YIG -based solutions 175 -based synthesizer 173, 193 devices 172 filter 178, 179, 206 material 49, 179 optimal loop bandwidth 174 oscillator 49, 172–175 resonance frequency 178 resonator 47–49, 178, 179 sphere 47–49 technology 172 -tuned filter 178–180, 206 -tuned oscillator 49, 53, 166, 172, 181, 192

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