Radiation Effects in the Space Telecom Environment

1999 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference Short Course

Radiation Effects in the Space Telecom Environment

July 12, 1999 Sponsored by: IEEE/NPSS Radiation Effects Committee Supported by: Defense Threat Reduction Agency Sandia National Laboratories Air Force Research Laboratory Jet Propulsion Laboratory NASA – Goddard Space Flight Center Approved for public release; distribution is unlimited.

1999 IEEE Nuclear and Space Radiation Effects Conference

Short Course

Radiation Effects in the Space Telecom Environment July 12, 1999 Norfolk Virginia

Copyright© 1999 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. For all other copying, reprint, or replication permission, write to Copyrights and Permissions Department, IEEE Publishing Services, 445 Hoes Lane, Piscataway, NJ 08555-1331.

Table of Contents

SECTION I …………………………………………………………... I 1-5 INTRODUCTION Daniel M. Fleetwood Sandia National Laboratories

SECTION II ……………………………………………………….. II 1-85 BASIC MECHANISMS FOR SINGLE-EVENT EFFECTS Paul E. Dodd Sandia National Laboratories

SECTION III …………………………………….……………… III 1-114 TOTAL-DOSE EFFECTS: MODELING FOR PRESENT AND FUTURE Jean-Luc Leray CEA/DAM Ile-de-France

SECTION IV ………………………………..…………………… IV 1-110 PROTON EFFECTS AND TEST ISSUES FOR SATELLITE APPLICATIONS Paul W. Marshall, Consultant Cheryl J. Marshall, NASA Goddard Space Flight Center

SECTION V ………………………………………………………... V 1-68 SYSTEM LEVEL MITIGATION STRATEGIES William F. Heidergott Motorola, Inc., Satellite Communications Group

AFTERWORD …………. Order information for Short Course CD ROM

1999 IEEE NSREC SHORT COURSE

SECTION I

INTRODUCTION

Daniel M. Fleetwood Sandia National Laboratories

Approved for public release; distribution is unlimited.

INTRODUCTION This Short Course covers in a tutorial fashion selected topics of relevance to space telecommunications systems. This is the 20th year in which the Short Course has been offered in conjunction with the IEEE Nuclear and Space Radiation Effects Conference (NSREC). The themes of the short course are selected each year to reflect the varying interests and requirements of the attendees of the IEEE NSREC. This year’s theme “RADIATION EFFECTS IN THE SPACE TELECOM ENVIRONMENT” is especially appropriate given the emerging interest in large-scale commercial space telecommunications systems. However, the information contained within the four segments should be useful to all systems that must operate reliably in the challenging radiation environment of space. The greatest challenge to commercial success in space is the integration of commercial and custom components into a system that can achieve its mission reliably and affordably. Rising to this challenge requires knowledge of the space radiation environment external to and within the satellite or spacecraft of interest, the effects of the environment on electronic and photonic devices, and system engineering techniques to mitigate these effects where possible. These requirements present significant constraints on component selection, and on system design and operation. The space telecommunications systems that best meet these challenges through proper assessment of the environment, disciplined parts selection and testing, judicious use of design margin, and efficient system design and integration will be the ones that best exploit commercial opportunities in space. The outline of the course is as follows: In Section II “BASIC MECHANISMS FOR SINGLE-EVENT EFFECTS” Paul Dodd presents an overview of the mechanisms responsible for single-event effects (SEE), with a particular eye toward the use of physics-based modeling and simulation to shed light on the fundamental processes involved. After a brief review of the space radiation environment responsible for SEE, nondestructive and destructive SEE failure modes are discussed. Techniques for mitigating SEE are reviewed, as well as newer topics such as particle energy effects and gate rupture in thin oxides. Future trends in SEE susceptibility are also addressed, including growing concerns for SEE in terrestrial microelectronics. In Section III “TOTAL-DOSE EFFECTS: MODELING FOR PRESENT AND FUTURE” Jean-Luc Leray reviews the basic mechanisms of total ionizing dose effects on semiconductor devices in the natural space environment. Time dependent effects on radiation response are discussed, as are new issues of especial interest to commercial off-the-shelf (COTS) parts. Detailed examples are presented that incorporate numerical modeling of total dose effects in several cases of interest. In Section IV “PROTON EFFECTS & TEST ISSUES FOR SATELLITE APPLICATIONS” Paul and Cheryl Marshall briefly review the proton environments, and

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discuss single event, total ionizing dose, and displacement damage issues specific to proton effects in space. Case studies are presented that illustrate typical applications of single event rate predictions and displacement damage analysis tools. Current issues pertaining to emerging technologies, on-orbit predictions, and test fidelity are also discussed. In Section V, “SYSTEM LEVEL MITIGATION STRATEGIES” Bill Heidergott addresses the commercial space telecommunications industry and satellite systems, space environment effects on spacecraft payloads, and design for radiation environment compatibility. The presentation includes brief discussions of the environment, models, and effects on devices; the primary focus is on single event upset and transient effects, and fault tolerance techniques for mitigating their impact to system operations. I want to personally thank the five Short Course authors, Paul Dodd, Jean-Luc Leray, Paul Marshall, Cheryl Marshall, and Bill Heidergott for their efforts in preparing this Short Course. It is the diligence and expertise of the authors that has continued the tradition of excellence in NSREC Short Courses through the years, and that makes it a highlight of the conference week and a resource for the remainder of the year. This year, we are especially pleased that this tradition has been recognized with a CD-ROM that contains previous NSREC Short Courses from 1980-1998, provided to each course registrant. We thank the Radiation Effects Steering Group (especially Dale Platteter) and the 1999 NSREC Conference Committee for making this possible. I also thank Lew Cohn for his efforts in reviewing the Short Course and ensuring that the notes were printed on schedule, and the DTRA printing office for printing the notebooks.

Daniel M. Fleetwood Albuquerque, New Mexico

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Biographies Daniel M. Fleetwood Short Course Organizer Sandia National Laboratories Daniel M. Fleetwood received his B. S. in Physics and Applied Mathematics from Purdue University in 1980, and his M. S. and Ph. D. degrees in Physics from Purdue in 1981 and 1984. He is a Distinguished Member of the Technical Staff in the Radiation Technology and Assurance Department at Sandia National Laboratories. He has been active in the field of radiation effects in microelectronics since joining Sandia in 1984, is the author or co-author of more than 175 publications, and holds two patents. In 1997 and 1998 he received R&D 100, Industry Week, and Discover Magazine awards for co-invention of a nonvolatile memory based on hydrogen-annealed SiO2. Dr. Fleetwood has served the radiation effects community as a guest editor of the December 1988-1990 and April 1996 special issues of the IEEE Transactions on Nuclear Science, as technical program chair and short course instructor for the IEEE NSREC, and as vice-chair/publications on the Radiation Effects Steering Group. He has received Outstanding Paper Awards for the 1985, 1988, and 1995-1998 IEEE NSREC’s and 1988, 1990, and 1995 HEART Conferences. He was awarded the International Correspondence Chess Master title in 1997, and is a member of The American Physical Society, Phi Beta Kappa, Sigma Pi Sigma, and a Fellow of IEEE. Dr. Fleetwood has accepted the position of Professor of Electrical Engineering at Vanderbilt University beginning August 1999.

Paul E. Dodd Sandia National Laboratories Paul E. Dodd received his B.S. and M.S. in Electrical Engineering from Purdue University in 1988 and 1989. He received his Ph.D. from Purdue in 1993 for research on novel cryogenic InAs bipolar transistors and experimental and theoretical studies of GaAs-based heterojunction bipolar transistors. He joined Sandia National Laboratories in 1993, and is a Senior Member of the Technical Staff in the Radiation Technology and Assurance Department. He is actively involved in the development of Sandia’s 0.5-µm and 0.35-µm bulk and SOI CMOS technologies, and the computer simulation of singleevent, total-dose, and transient radiation effects on microelectronics. Dr. Dodd has served the radiation effects community as publicity chairman and session chairman for the IEEE NSREC, and has been a session chairman for the Single-Event Effects Symposium. He has also served the IEEE International Electron Devices Meeting as a member of the Modeling and Simulation technical subcommittee and session chairman. Dr. Dodd is the author or co-author of more than 30 publications and is a member of the IEEE.

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Jean-Luc Leray CEA/DAM Ile-de-France Jean-Luc Leray received his Engineering Degree from the “Ecole Centrale des Arts et Manufactures de Paris” in 1978, and the “Docteur d'État es Sciences Physiques” Degree from the University of Orsay, Paris, in 1989. Meanwhile, he was successively research engineer, project leader, and group leader at "Commissariat A l'Energie Atomique" (CEA), the French Agency for Atomic Energy. In 1992, he became head of the Radiation Hardening Section at CEA. In 1994, Dr. Leray was awarded "Grand Prix de l’Electronique Général Ferrié" by SEE (Société des Electriciens et des Electroniciens, Paris) and FIEE (French Federation of the Electronic Industries) for works in design and hardening of integrated technologies for military, space, and high-energy physics applications. Dr. Leray has served as Session Chair for the IEEE NSREC, and as Short Course Instructor and Technical Program Chair for RADECS. He is the author or coauthor of more than 110 publications and 4 book chapters, and holds one patent. In 1998, he was awarded the medal "Chevalier des Palmes Académiques" by the Ministry of Education and Research. Dr. Leray is now a scientific assistant and program advisor to the director of the department in charge of hardening matters at CEA. He is a "Membre Sénior" of SEE and a Senior Member of the IEEE.

Paul W. Marshall Consultant Paul W. Marshall received his B. S. in Physics from James Madison University in 1980, his M. S. in Radiation Biophysics from the Medical College of Virginia in 1982, and his Ph. D. from the Department of Nuclear Engineering and Engineering Physics at the University of Virginia in 1985. Since 1985, he has been employed by SFA, Incorporated, under contracts supporting the Naval Research Laboratory’s Radiation Effects Branch. His activities there have included development of proton test capabilities for microelectronic and photonic components of interest to satellite developers. Basic mechanisms of proton interactions have been a major emphasis in his studies of displacement damage and single event effects from protons. Since 1991 Dr. Marshall has been engaged, first as a collaborator and more recently as a consultant, with the NASA Goddard Space Flight Center’s Radiation Effects Group where he supports component and subsystem evaluations for numerous flight projects and continues investigations into basic mechanisms of proton and other radiation effects in emerging technologies. Dr. Marshall has chaired sessions and served on several committees for the NSREC, and he is a member of the IEEE and NPSS with over 80 published papers.

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Cheryl J. Marshall NASA Goddard Space Flight Center Cheryl J. Marshall received her B. S. degrees in Physics and Chemistry from Georgetown University in 1979, and her Ph.D. in Physics from the University of North Carolina at Chapel Hill in 1986. From 1986 until 1998, she worked as a research physicist for the Naval Research Laboratory, investigating basic mechanisms of radiation damage in microelectronic and optoelectronic technologies critical to satellite imaging and communications. She also served as Section Head of the Emerging Technologies Section in the Radiation Effects Branch at NRL, and provided flight program support. Dr. Marshall has served as the Defense Threat Reduction Agency’s Program Area Reviewer for Single Event Effects, and chaired the 10th and 11th Single Event Effects Symposia. Since 1998, Dr. Marshall has worked for the NASA Goddard Space Flight Center, evaluating radiation effects in emerging technologies and providing flight program support. She has participated in the IEEE NSREC on several committees and chaired sessions (including the Poster Session in 1998). She is a member of the IEEE and NPSS with over 80 published papers.

William F. Heidergott Motorola, Inc., Satellite Communications Group William F. Heidergott received his B. S. in Electrical Engineering from the University of Arizona in 1974. Since joining Motorola, Inc., he has worked in the design and development of CMOS custom devices, application specific integrated circuits and standard products, and subsystem design and system development for numerous DoD, NASA, and commercial space programs. Mr. Heidergott’s recent assignments include program engineering support in design for radiation environment compatibility and management of technology for commercial space programs. In 1998 he chaired the inaugural NSREC session on radiation effects in commercial electronics and space systems.

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BASIC MECHANISMS FOR SINGLE-EVENT EFFECTS Paul E. Dodd Sandia National Laboratories Albuquerque, New Mexico 1.0

Introduction

2.0

Brief Overview of Environments 2.1 Trapped Particles 2.1.1 Protons 2.1.2 Heavy Ions 2.2 Transient Particles 2.2.1 Solar Event Protons and Heavy Ions 2.2.2 Galactic Cosmic Rays 2.3 Secondary Particles

3.0

Basic Mechanisms for Non-Destructive Single-Event Effects 3.1 Charge Deposition 3.1.1 Direct Ionization 3.1.2 Nuclear Reaction Effects 3.2 Charge Collection 3.2.1 Basic Physics of Charge Transport 3.2.2 New Charge-Collection Mechanisms in Submicron Devices 3.3 Single-Event Upset Mechanisms in DRAMs 3.3.1 Storage Cell Errors 3.3.2 Bit-Line Errors 3.3.3 Combined Cell and Bit-Line Errors 3.4 Single-Event Upset Mechanisms in SRAMs 3.5 Single-Event Upset in Other Circuit Types 3.6 Single-Event Multiple-Bit Upset 3.7 Particle Energy Effects 3.8 Mitigation Techniques 3.8.1 Technology Hardening 3.8.2 Circuit- and System-Level Hardening

4.0

Basic Mechanisms for Destructive Single-Event Effects 4.1 Single-Event Latchup 4.1.1 Single-Event Latchup Mechanism 4.1.2 Mitigation Techniques 4.2 Single-Event Gate Rupture 4.2.1 Single-Event Gate Rupture Mechanism 4.2.2 Single-Event Gate Rupture in Power MOSFETs 4.2.3 Single-Event Gate Rupture in Thin Gate Oxides 4.3 Single-Event Burnout

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5.0

Modeling and Simulation of Single-Event Mechanisms 5.1 Interaction Models 5.1.1 Track Structure Models 5.2 Physics-Based Device Models 5.2.1 3D Device and Mixed-Level Simulations 5.2.2 Recent Enhancements

6.0

Future Trends 6.1 Technology Drivers Impacting Single-Event Effects 6.2 Hardening Strategies 6.3 Terrestrial and High-Altitude Single-Event Effects 6.3.1 The Atmospheric Radiation Environment 6.3.2 Historical Perspective and Recent Studies 6.3.3 Mitigation Techniques

7.0

Summary and Conclusions

8.0

Acknowledgments

9.0

References

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1.0

INTRODUCTION

Single-event effects (SEE) in microelectronics are caused when highly energetic particles present in the natural space environment (e.g., protons, neutrons, alpha particles, or other heavy ions) strike sensitive regions of a microelectronic circuit. Depending on several factors, the particle strike may cause no observable effect, a temporary disruption of circuit operation, or even permanent damage to the device or integrated circuit (IC). Single-event effects may be broadly characterized as either non-destructive or destructive SEE. Examples of non-destructive SEE include single-event upset in logic or memory circuits (SEU, or equivalently, soft errors) and single-event current transients (SET) in photodetectors. Destructive SEE include such phenomena as single-event latchup (SEL, which can be either destructive or non-destructive depending on circuit design), single-event burnout (SEB), and single-event gate rupture (SEGR). Any of these effects can cause unacceptable system performance in space applications, and possibly jeopardize mission success. In this short course segment, we will examine the basic physical mechanisms causing singleevent effects in microelectronics for spaceborne applications. We start with a brief overview of the particle environment encountered in space in order to get to know the enemy. We will then discuss the mechanisms and characteristics of many of the non-destructive and destructive SEE mentioned above in detail, including techniques for mitigation. Next we review modeling and simulation methods that have proved useful for gaining physical insight and predicting SEE in microelectronics. We conclude with a look into technology trends that may affect future device susceptibility to SEE and areas of emerging concern. Reflecting their relative importance in the commercial marketplace, most of this short course segment will focus on silicon MOS devices and circuits, but where appropriate we will examine other technologies of interest.

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2.0

BRIEF OVERVIEW OF ENVIRONMENTS

Previous NSREC Short Course segments have given excellent detailed descriptions of the space radiation environment [1,2]. Several review articles on the subject were also published as part of the recent Special Issue on Single Event Effects and the Space Radiation Environment in the IEEE Transactions on Nuclear Science [3-8]. The intent is not to repeat a great deal of this information here, but rather to give a brief overview of some of the more important points that may be of use later as SEE mechanisms are discussed. The reader is directed to the above references for more details on the space radiation environment. 2.1

Trapped Particles

Charged particles that come into contact with the Earth’s magnetic field can become trapped in the near-Earth environment. These particles include electrons, protons, and heavy ions. Electrons are very important components of the space environment because they inflict damage on spacecraft through total ionizing radiation dose and spacecraft charging effects [9-11]. Because electrons do not usually contribute to single-event effects, we will limit our discussions to trapped proton and heavy ion populations. The trapped particle belts (Van Allen belts) consist of two regions of trapped particles: an inner belt centered at about 1.5 Earth radii, and an outer belt of particles at about 5 Earth radii, separated by a region of reduced (but non-zero) particle flux (the so-called “slot” region). References [1] and [2] contain helpful illustrations of the belt structure around the Earth. Although the origin of trapped particles in the near-Earth environment is not completely understood [1], sources include the solar wind and transient solar events, cosmic ray particles from interplanetary space, and reaction products from cosmic ray collisions with the Earth’s atmosphere. It was recently discovered that transient solar events can actually produce new trapped particle belts of surprisingly long duration [4,6]. 2.1.1

Protons

Regardless of origin, energetic protons do exist in the near-Earth environment and are one of the most prominent sources of SEE. They range in energy from tens of keV to hundreds of MeV, with fluxes as high as 105 protons/cm2/sec for protons with energy > 30 MeV [1]. Protons with these energies are easily able to penetrate shielding and impinge on electronics within spacecraft. The altitude at which proton flux peaks depends on the proton energy, with high energy (>30 MeV) protons being cut off by around 3.5 Earth radii, but lower energy protons existing throughout the slot region. Probably the most important region for proton SEE is the South Atlantic Anomaly (SAA), a region off the east coast of South America with greatly increased proton flux at altitudes less than 1000-2000 km. The SAA exists because of the difference between the Earth’s geographic spin axis and its magnetic axis, which causes a localized region of lower magnetic field off the Argentine coast [1]. During passes through the SAA, the flux of energetic (>30 MeV) protons can be more than 104 times as intense than at equivalent altitudes over other regions of the Earth [12]. The SAA is illustrated in Figure 2.1, which shows flux contours for protons with energy > 30 MeV as a function of latitude and longitude at altitudes of 500 km (Fig. 2.1a), 1000 km

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(Fig. 2.1b), and 3000 km (Fig. 2.1c) [1]. At low altitudes, the SAA is highly localized, and as altitude increases, the SAA becomes less distinct until at 3000 km (Fig. 2.1c) the normal Van Allen belt structure re-emerges. 2.1.2

Heavy Ions

The Van Allen belts are predominantly composed of trapped electrons and protons, but it is now well accepted that heavy ions are also trapped by the Earth’s magnetic field. The origin of these particles is thought to be anomalous cosmic rays, which are neutral interstellar particles that drift into the solar system, become ionized by the solar wind and accelerated to 10’s of MeV/nucleon, and are subsequently trapped by the magnetosphere [1]. Trapped heavy ions (e.g., He, C, N, O, and Ne) have been measured by the SAMPEX spacecraft, and an example geographic distribution is shown in Figure 2.2 for oxygen ions [13]. Similar results have been

a)

b)

c) Figure 2.1

Integral proton flux contours as a function of latitude and longitude after Barth [1]. Altitudes are a) 500 km, b) 1000 km, and c) 3000 km. Note the South Atlantic Anomaly, which is visible at lower altitudes but disappears by 3000 km. II-5

obtained by the Japanese satellite MIDORI [14]. The oxygen ions shown in the polar regions in Fig. 2.2 are not trapped heavy ions, but are due to galactic cosmic rays, as discussed below. Trapped oxygen ions are evident in the region near the SAA for the same reason that proton fluxes are greatest there, i.e., the lower magnetic field in the SAA allows the ion flux to dip down to lower altitudes. The peak in trapped heavy ion fluxes is at altitudes just above the inner proton belt (i.e., 1.8 to 2 Earth radii). Because the trapped heavy ions have relatively low energies (10’s of MeV/nucleon), these particles may not penetrate through spacecraft shielding and therefore are not expected to be a major concern for SEE [1]. 2.2

Transient Particles

In this section, the classification of “transient” particles encompasses all particles in the nearEarth space environment that are not stably trapped in the magnetosphere. This includes particles introduced into the environment by solar events such as flares and coronal mass ejections (CMEs), as well as energetic ions incident from interstellar space. 2.2.1

Solar Event Protons and Heavy Ions

The activity level of the Sun is never constant, but follows a cyclical variation of active years followed by quiet years. The period of recent solar cycles has varied between 9 and 13 years, with an average of about 11 years. Solar cycle activity is frequently gauged by the observed number of sunspots, but many solar processes show the same variation. Importantly for the

Figure 2.2

Geographic distribution of trapped oxygen ions during solar quiet time as measured by the Mass Spectrometer Telescope (MAST) on SAMPEX [13]. II-6

present case, this includes the incidence of energetic solar events, with maximum numbers of solar flares and CMEs occurring during active years. Solar events still occur during solar quiet times, but they occur less frequently. We have long associated solar flares with an increased flux of energetic particles, but the evidence appears to support that CMEs may be more important [1]. Solar events can be broadly characterized as being either gradual or impulsive. The gradual events produce a raised particle flux that decays slowly over several hours or even days, and have been correlated to CMEs. These events are proton-rich and can produce high-energy (> 30 MeV) proton fluences higher than 109 protons/cm2 accumulated over a few days. Gradual events are responsible for the majority of large proton fluence events, and occur at a frequency of about 10 per year during solar maximum conditions. Impulsive events are by definition of much shorter duration (hours at most), and are marked by increased fluences of heavy ions and low energy electrons. Impulsive events produce heavy ion fluences that can be orders of magnitude above the galactic cosmic ray background. These heavy ions have energies ranging from tens of MeV/nucleon to hundreds of GeV/nucleon, but at the upper end of this range the flux falls below the galactic cosmic ray background. Impulsive events may be associated with solar flare activity and are responsible for about 1000 small solar particle events per year at solar maximum [1,3]. Figure 2.3 shows solar event proton fluences for the last three solar cycles, superimposed over a plot of the sunspot number [1]. The cyclical variation of the sunspot number is readily apparent, as is the fact that most (but not all) high-fluence proton events occur during solar active years. While solar particle events can be broadly classified as gradual or impulsive, individual events have their own very unique properties in terms of duration, particle fluence, energy spectrum, etc. Stassinopoulos et al. have presented a classification system where events are classified from small to extremely large, and solar cycles are classified from extremely mild to Event Fluences For Cycles 20 - 22 1011

Cycle 21

Cycle 22

> 10 MeV; > 108 p/cm2 > 30 MeV; > 107 p/cm2 Zurich Smoothed Sunspot Number

200 180 160

Protons/cm2

1010 140 120 109

100 80 60

108 40 20 10

Zurich Smoothed Sunspot Number

Cycle 20

0

7

1965

1970

1975

1980

1985

1990

1995

Year

Figure 2.3

Correlation of proton solar event fluence to sunspot number for solar cycles 20-22 [1]. Sunspot number is shown by the solid line plot, and proton solar event fluences by the bars.

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extremely severe [5]. It can be seen in Figure 2.3 that solar cycle 20 was in general extremely quiet with the exception of an extremely large solar event in August 1972; this solar cycle was classified as very mild. Solar cycle 21 was extremely mild, with no individual events of highenergy proton fluence > 109 protons/cm2. By contrast, solar cycle 22 had 8 events with highenergy proton fluence > 109 protons/cm2; this cycle is considered extremely severe [5]. Some events (such as the August 1972 event) are actually a series of closely-spaced events, where proton fluxes have not yet decayed to their original level before the next event occurs. The importance of individual large solar events cannot be overestimated – the August 1972 event by itself accounted for 84% of the total high-energy proton fluence received by spacecraft during the entire 20th solar cycle. Accurate models to predict worst-case particle fluence from solar events are crucial to appropriate parts selection and survivable spacecraft design. 2.2.2

Galactic Cosmic Rays

6-Hour-Averaged Flux (cm2-s-sr)-1

Solar event particles are true transient particles in the sense that elevated fluxes of particles are observed only for a short time following an event (although recall that following a large event increased levels of trapped particles are observed and in some cases can produce new trapped particle belts). In contrast, galactic cosmic rays (GCR) form a background component of radiation that shows a slow cyclical variation with solar activity. GCRs are composed of very highly energetic protons and heavy ions that come from outside the solar system. These particles must fight against the solar wind to enter the solar system and are therefore at their maximum intensity at solar minimum and drop off a factor of 2 to 10 at solar maximum. The cyclical variation of GCRs is shown in Figure 2.4, which is a plot of 25-95 MeV/nucleon He flux over a 20-year period as measured by the IMP-8 satellite [15]. The spikes on this plot are due to increased heavy ion fluences from solar events. Note that these spikes are more likely to occur at solar maximum, when the baseline GCR heavy ion flux is lowest.

Figure 2.4

Solar cycle variation of heavy ions (in this case He nuclei) as measured by the Cosmic Ray Telescope (CRT) aboard the IMP-8 satellite [15]. Note the spikes in He flux caused by solar events. II-8

The particle composition of GCRs is shown in Figure 2.5 [16]. Protons comprise about 83% of the GCR flux, He nuclei (alpha particles) account for 13%, 3% are electrons, and the remaining 1% are heavier nuclei. Even though they are not very abundant, heavy ions are very important to SEE because they deposit the most energy per unit pathlength, as discussed in later sections. Note that beyond Fe, the heavy ion flux drops dramatically. This turns out to be important, because the energy deposited by an ion per unit pathlength depends on its atomic number. Ions heavier than Fe are more ionizing, but are much less abundant. Therefore, radiation hardening microelectronics so that they don’t experience SEE from ions up to Fe can result in low SEE rates. This is sometimes referred to as the “iron threshold.” GCRs that come into contact with the near-Earth environment encounter Earth’s geomagnetic field. Because they are so energetic (tens of MeV/nucleon to hundreds of GeV/nucleon), they do not become trapped and are not significantly attenuated by spacecraft shielding. GCRs that hit the atmosphere form a cascade of secondary particles, as mentioned in the next section. GCRs with polar trajectories can penetrate to low altitudes because of the reduced geomagnetic rigidity in the polar regions. Spacecraft with high inclination angles are therefore at greatest risk of encountering SEE due to GCRs. 2.3

Secondary Particles

Secondary particles are produced when GCRs strike the Earth’s atmosphere and produce a shower of particles in the atmospheric environment. Because this component of the radiation environment is important only for microelectronics operating in the Earth’s atmosphere, a description of the secondary particle environment will be delayed until Section 6.3, Terrestrial and High-Altitude Single-Event Effects.

Figure 2.5

Particle composition of galactic cosmic rays [16]. Note that Hydrogen and Helium nuclei (i.e., protons and alpha-particles) account for the vast majority of GCR flux, while heavy ions comprise only about 1%. II-9

3.0

BASIC MECHANISMS FOR NON-DESTRUCTIVE SINGLE-EVENT EFFECTS

All non-destructive single-event effects are caused by the same fundamental mechanism: collection of charge at a sensitive region of a microcircuit following the passage of an energetic particle through the device. In this section we look at the release of mobile carriers along the path of an incident particle, the collection of these carriers, and how the resulting transient currents interact with the circuit to generate a single-event upset. 3.1

Charge Deposition

By definition, as ionizing radiation passes through a target material electrons and holes are released along the path of ionizing particles. There are two primary methods by which carriers are released: direct ionization by the incident particle and ionization by secondary particles created by nuclear reactions between the incident particle and the target material. Direct ionization can cause SEU if the incident particle (such as a heavy ion) is ionizing enough to free a very high density of carriers. For lighter particles (e.g., protons), direct ionization may produce an insufficient amount of charge to cause upset directly and SEU may instead be due to ionization produced by secondary particles. 3.1.1

Direct Ionization

As we have said, when an energetic particle passes through a semiconductor material it frees charged carriers along its path as it loses energy. When all of its energy is lost, the particle comes to rest in the semiconductor, having traveled a total path length referred to as the particle’s range. We frequently use the terms linear energy transfer (LET) or dE/dx to describe the energy loss per unit path length of a particle as it passes through a material. LET has the seemingly odd units of MeV-cm2/mg, but this is simply because the energy loss per unit path length (in MeV/cm) is normalized by the density of the target material (in mg/cm3). We can easily relate the LET of a particle to its charge deposition per unit path length, because for a given material it takes a certain amount of energy to release an electron-hole pair. For example, in silicon one electronhole pair is produced for every 3.6 eV of energy lost, and silicon has a density of 2328 mg/cm3 [17]. Using these values it is easy to show that an LET of 97 MeV-cm2/mg corresponds to a charge deposition of 1 pC/µm. This conversion factor of about 100 is handy to keep in mind if you need to go back and forth between energy loss (LET) and charge deposition. A curve of particular interest for understanding the interaction of a given energetic particle with matter is the LET of the particle versus depth as it travels through the target material. Figure 3.1 shows such a curve for a 210-MeV chlorine ion traveling through silicon (a common heavy ion beam used for SEU testing at the Tandem Van de Graaff at Brookhaven National Laboratory). Such curves are readily obtained using computer codes derived from the work of Ziegler, et al (e.g., the TRIM and SRIM family of codes, [18]). This figure shows the basic characteristics of ion-induced charge deposition as a function of depth. A peak in the charge deposition occurs as the particle nears its range, and then a precipitous drop in deposition as the particle reaches its range and comes to rest. The peak in charge deposition is referred to as the Bragg peak, and in general occurs as the particle reaches an energy near 1 MeV/nucleon. A more rigorous discussion of the Bragg curve and the Bragg peak is found in reference [19].

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30

2

LET (MeV-cm /mg)

Bragg Peak

20

10

0 0

20

40

60

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Depth (µm) Figure 3.1

Linear energy transfer (LET) vs. depth curve for 210-MeV chlorine ions in silicon.

Whether or not the charge deposited through direct ionization is sufficient to cause an upset of course depends on the individual device and circuit that has been struck as well as the strike location and trajectory. Direct ionization is the primary charge deposition mechanism for upsets caused by heavy ions, where we rather loosely define a heavy ion as any ion with atomic number Z ≥ 2 (i.e., He and above, or put another way, particles other than protons, electrons, neutrons, or pions). Lighter particles such as protons do not usually produce enough charge by direct ionization to cause upsets in memory circuits, but recent research has suggested that as devices become ever more susceptible, upsets due to direct ionization by protons may occur [20,21]. This effect has not been experimentally confirmed to date. As discussed in references [21] and [22], these upsets will likely be difficult to observe and of limited importance to the overall upset rate because the upset rates will continue to be dominated by proton-silicon reactions for typical orbits and spacecraft configurations. In contrast to memories, upsets in photodiodes used in optocoupler applications have been observed and correlated to direct ionization by protons [2326]. Single-event current transients (SET) resulting from proton direct ionization are capable of causing upsets in these photodiodes because they are by design very large and operate at very high data rates [27]. A recent analysis suggests that a combination of direct ionization and recoils are responsible for the anomalous angular dependence of proton upsets in optocouplers [28]. Charge-coupled devices (CCDs) can also be sensitive to direct ionization by protons because of their large collection depths [29]. For more information on these devices and their susceptibility to protons the reader is directed to the third segment of this short course [30]. 3.1.2

Nuclear Reaction Effects

As mentioned above, direct ionization by light particles usually does not produce a high enough charge density to cause upsets. Unfortunately, this does not mean that we can ignore

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these lighter particles. Protons and neutrons can both produce significant upset rates due to indirect mechanisms. As a high-energy proton or neutron enters the semiconductor lattice it may undergo an inelastic collision with a target nucleus. This may result in the emission of alpha (α) or gamma (γ) particles and the recoil of a daughter nucleus (e.g., Si emits α-particle and a recoiling Mg nucleus), or a spallation reaction, in which the target nucleus is broken into two fragments (e.g., Si breaks into C and O ions), each of which can recoil. Any of these reaction products can now deposit energy along their paths by direct ionization. Because these particles are much heavier than the original proton or neutron, they can deposit higher charge densities as they travel and therefore may be capable of causing an SEU. These inelastic collision products typically have fairly low energies and do not travel far from the particle impact site. They also tend to be forward-scattered in the direction of the original particle; this has consequences for the SEU sensitivity as a function of the angle of incidence [31]. Historically neglected, recent experiments and simulations have shown that elastic collisions may become important for very sensitive devices [32,33]. Low-energy secondary particles (primarily protons and neutrons) generated within packaging or shielding may be an even more significant source of SEU in these sensitive devices [33]. Once a nuclear reaction has occurred, the charge deposition is not greatly different in character from a directly ionizing heavy ion strike. Therefore, once deposited, it is subject to the same fields and concentration gradients and is collected in a similar manner. 3.2

Charge Collection

The basic properties of charge collection following a particle strike have been studied using a variety of experimental and theoretical methods. Broadbeam charge collection spectroscopy measurements have been used to determine SEU-sensitive volumes in SRAMs [34-36], and ion microbeams and lasers have been used with high-speed sampling oscilloscopes to measure charge-collection transients in Si and GaAs devices [37-46]. Ion microbeams and lasers have also been used to map integrated charge collection as a function of position in ICs [45,47,48], and more recently as a function of both time and position [49]. The physics of charge collection have also been intently studied through the use of two- and three-dimensional numerical simulation [50,51]. It is beyond the scope of this short course segment to comprehensively review the massive literature on charge collection; we seek to touch the main highlights and recent developments only. 3.2.1

Basic Physics of Charge Transport

There are basically only three mechanisms that act on the charge deposited by an energetic particle strike: 1) carriers can move by drift in response to applied or built-in fields in the device, 2) carriers can move by diffusion under the influence of carrier concentration gradients within the device, or 3) carriers can be annihilated by recombination through direct or non-direct processes. These three mechanisms are of course not unique to the particle strike problem and are in fact the governing processes of charge transport in semiconductors under most operating conditions [52]. When a particle strikes a microelectronic device, the most sensitive regions are reversebiased p/n junctions, as illustrated in Figure 3.2. The high field present in a reverse-biased junction depletion region can very efficiently collect the particle-induced charge through drift processes, leading to a transient current at the junction contact. The situation is not too dissimilar II-12

from the operation of a solar cell, where large-area p/n junctions are reverse-biased to collect charge liberated in the semiconductor by sunlight. Strikes near a depletion region can also result in a significant transient current as carriers diffuse into the vicinity of the depletion region field where they can be efficiently collected. Note that even for direct strikes, diffusion plays a role as carriers generated beyond the depletion region can diffuse back toward the junction. Shortly following the discovery of SEU, researchers at IBM used numerical device simulators to compute the response of reverse-biased p/n junctions to alpha-particle strikes [50,53,54]. An important insight gained from these early charge-collection simulations was the existence of a transient disturbance in the junction electrostatic potential, which was termed the “field funnel,” as shown in Figure 3.3 [53]. Charge generated along the particle track can locally collapse the junction electric field due to the highly conductive nature of the charge track and separation of charge by the depletion region field. This funneling effect can increase charge collection at the struck node by extending the junction electric field away from the junction and deep into the substrate, such that charge deposited some distance from the junction can be collected through the efficient drift process. The funnel effect has been investigated in further detail by later researchers [55-59], including the influence of epitaxial substrates on the transient charge-collection characteristics [60-62]. Several important additional insights have been gained from these studies. The reader is referred to [59-62] for more comprehensive discussions of funneling, but here are a few key points to keep in mind:

Ion Pa th

1) The term “funnel length” is a misnomer (as is funneling itself to some extent). There is no well-defined length that can be associated with funneling from a physical standpoint [58,61,62]. Funnel length is thus only a useful concept inasmuch as it can be used as a quasi-physical “fudge factor” in error rate calculations. In this case it can be used to represent any charge collection from outside the defined sensitive volume, including the effects of funneling.

Funnel

–+ +– – + Drift +– –+ + – Diffusion ++ –+

Depletion Region

Recombination Figure 3.2. Illustration of an ion strike on a p/n junction showing drift, diffusion, recombination, and funneling. II-13

2) Expecting funnel-assisted drift charge collection to be “prompt” can be misleading. In cases where the substrate is lightly-doped, funneling can take a long time (nanoseconds) to develop and to collect charge [54,60]. 3) Funneling does not require a direct strike on a depletion region. Near misses can also cause funneling if a high enough carrier density diffuses into the depletion region to collapse it [54,61]. 4) Funneling in epitaxial diodes is limited by the heavily-doped substrate underneath the epi layer. Once sufficient minority carriers are removed from the epi layer, the depletion region is reformed, funneling stops, and charge collection continues at a much slower rate. This leads to a characteristic knee in the charge-collection characteristics of n/p epitaxial diodes, as shown by the dashed curve in Fig. 3.4 [60,61]. 5) Because of differences in the hole and electron mobility, funneling occurs in reversebiased n/p diodes, but is much weaker or nonexistent in equivalent p/n diodes. This is indicated in Fig 3.4 by the lack of a knee in the p/n charge-collection characteristics (solid curve). [59,61]. 6) The total charge collected in an epitaxial diode can be approximated by the charge liberated in the epitaxial layer plus the charge liberated within a diffusion length of the epi/substrate boundary [61]. Funneling affects the rate at which the charge deposited in the epi layer is collected, but does not appear to change the total charge collection, since this charge would usually be collected even in the absence of funneling. While in some cases important to charge collection in isolated p/n junctions with constant applied bias, the role of the funnel is less significant in the case of static circuits such as SRAMs, where reverse-biased transistor junctions are connected to active external circuitry. In this scenario, the applied voltage at the struck junction is not constant, and in fact very often the

Figure 3.3. Illustration of funneling in an n+/p silicon junction following an ion strike: a) electrostatic potential, b) electron concentration. Note that contours of electrostatic potential are distorted along the path of the ion [53]. II-14

Figure 3.4. Charge-collection transients in n+/p and p+/n epitaxial diodes following ion strikes [61]. Note the lack of a knee in the p+/n diode curve, which indicates that funneling is very weak for this case. struck node may switch from being reverse-biased to zero-biased (see Section 3.4). This loss of bias at the struck node tends to lessen the importance of drift collection (and hence the funnel) as the single-event transient proceeds [63]. In such cases, funneling may play a role in the early-time response of the circuit by helping initially flip the node voltage, but it is late-time collection by diffusion that ensures the bit stays flipped (see Section 3.4 for further details about the upset process in SRAM circuits). 3.2.2

New Charge-Collection Mechanisms in Submicron Devices

The charge-collection response of a single p/n junction is generally presumed to accurately depict the response of the sensitive junction of a transistor, typically a reverse-biased drain region. Studies have indicated that a new charge-collection mechanism may exist for submicron MOS transistors which requires considering the entire transistor [64,65]. Termed the alphaparticle source-drain penetration effect (ALPEN), this charge-collection mechanism results from a disturbance in the channel potential that the authors referred to as a funneling effect. The effect is illustrated in Figure 3.5a and is triggered by a particle strike that passes through both the source and the drain at near-grazing incidence. Immediately following the strike, the electrostatic potential in the channel region is perturbed to the extent that i) there is no longer a potential barrier between the source and channel, and ii) there is a substantial potential gradient between the source and the drain. These two conditions together can lead to a significant (but short-lived) source-drain conduction current which mimics the “on” state of the transistor. This mechanism was revealed by 3D alpha-particle simulations and has been experimentally verified. The experiments indicate that source charge injection due to the ALPEN mechanism increases rapidly II-15

a)

b)

Figure 3.5. a) Illustration of the alpha-particle induced source-drain penetration (ALPEN) effect [64]. b) Charge injected by the source due to the ALPEN mechanism as a function of gate length. For gate lengths below 0.5 µm, this mechanism may become critical. for effective gate lengths below about 0.5 µm, as shown in Fig. 3.5b. Later work predicted the same direct channel conduction mechanism can occur in 0.3-µm gate length MOSFETs even for normal incidence strikes, and can lead to charge multiplication [66]. This mechanism may forebode a serious vulnerability to SEU for deep submicron MOSFETs. A somewhat similar, but distinct mechanism exists when electrons or holes released by a particle strike are confined to a well or body region in which a transistor is located. For example, for an n-channel MOS transistor located in a p-well, electrons induced by a particle strike can be collected at either the drain/well junction or the well/substrate junction. However, holes left in the well raise the well potential and lower the source/well potential barrier, and the source injects electrons into the channel, as illustrated in Figure 3.6 [67-70]. These electrons can be collected at the drain, where they add to the original particle-induced current and can cause an increased SEU sensitivity. Because the electrons are injected over the source/well barrier, this is referred to as a bipolar transistor effect, where the source acts as the emitter, the channel as the base region, and the drain as the collector. Reducing the channel length effectively decreases the base width, and the effect becomes more pronounced [69]. Essentially the same effect occurs in floating body silicon-on-insulator (SOI) devices, where excess carriers in the body turn on the parasitic bipolar transistor [69,71,72]. This bipolar effect severely impacts the intrinsic SEU hardness of floatingbody SOI transistors.

II-16

Source

Gate

Drain

P-Well

N-Substrate

Figure 3.6. Electron concentration contours inside an n-channel MOS transistor following a heavy ion strike [70]. The bipolar effect is evidenced by the contours emanating from the source, showing that the source is injecting electrons into the p-well, where they may be collected at the substrate or at the drain.

3.3

Single-Event Upset Mechanisms in DRAMs

We’ve seen how an ion strike releases charge along its path through a semiconductor and how this charge can be collected by p/n junctions, but what really matters is determining whether the event actually causes an error in circuit operation. In the following subsections we’ll study how charge collection interacts with the circuit type and design to create a single-event upset. The focus will primarily be on memory circuits, but we’ll briefly address SEU in other circuit types at the end of the section. SEUs in terrestrial electronics were first observed in DRAMs [73,74]. DRAMs have historically been quite susceptible to soft errors because they rely on passive storage of charge to represent information. Their charge state is readily modified by funnel-assisted drift or diffusion following an energetic particle strike. DRAMs have therefore received less use in space systems as engineers have preferred SRAM technologies [75]. As the need for very large amounts of onboard memory is increasing, the use of DRAM technologies in space systems is becoming more common [76-81]. DRAMs are prone to SEU due to three primary mechanisms: storage cell errors, bit-line errors, and a combination of the two. The reader is directed to the review article by Massengill [75] for an excellent in-depth summary of SEU effects in DRAMs. 3.3.1

Storage Cell Errors

Figure 3.7 illustrates the mechanism for storage cell errors in a field plate capacitor DRAM [75]. In this kind of DRAM a stored “0” is represented by electrons occupying a potential well under the field plate, while a stored “1” corresponds to electrons being depleted under the plate. Following a particle strike, electrons can be collected at the reverse-biased field plate. In the case of a stored “0”, this just reinforces the original state, but a stored “1” can look like a stored “0” after electron collection. DRAM storage cell errors therefore can characteristically show a very II-17

large pattern dependence. Note also that data patterns may be inverted internally depending on the memory, so that “0” to “1” errors are observed externally [73,74]. Two other effects can lead to storage cell errors in DRAMs. The ALPEN effect described in Section 3.2.2 can lead to channel conduction that shunts charge onto the storage cell, disturbing the cell information [64]. In DRAMs with closely spaced trench storage cells, charge can be transferred between two storage nodes by a particle track shunt effect [82]. In this case, the particle track intersects neighboring storage nodes in opposite memory states, and the resulting charge transfer between nodes can upset one or both storage nodes. 3.3.2

Bit-Line Errors

Bit-line errors can result if sufficient charge is collected during a read cycle to create a charge imbalance on the precharged bit lines [75]. Because they can only occur during a read cycle, bitline errors have a direct dependency on the read access frequency, with an increasing error rate as the access frequency increases [83,84]. Bit-line errors can be caused by strikes to the access transistor drains along the floating bit-line or strikes to the sense amplifier circuitry itself [75,85]. Because of their inverse dependency on cycle time, bit-line errors become a significant reliability concern as memory speeds increase. 3.3.3

Combined Cell and Bit-Line Errors

A new failure mode for DRAMs was demonstrated ten years ago when it was found that charge collection at both the storage cell and bit line that was insufficient to individually cause an upset could cause an error in combination [86]. This new failure mode, dubbed the combined cell-bit line (CCB) error, was shown to dominate the storage cell and bit-line error rates for very short cycle times. The three components of soft errors in a 512K DRAM are shown in Figure 3.8 as a function of the cycle time. Note the independence of storage-cell errors on cycle time, and the domination of CCB errors for short cycle times [86].

Ion Path Bit Line

Poly Word Line Poly

Field Plate Poly +

+ -+

+

n+

n+

Stored Information Charge

Figure 3.7. Illustration of storage cell SEU in a field-plate DRAM after Massengill [75]. Collection of electrons at the reverse-biased field plate reinforces a stored “0,” but can lead to an upset of a stored “1.” II-18

104 Source: AM241

Soft Error Rate (arbitrary units)

103

102

10

1

CCB Component Bit Line Component Cell Component

10-1 10

102

103

104

105

Cycle Time (ns)

Figure 3.8. Components of soft-error rate in a DRAM [86]. The storage cell component is not dependent on the cycle time, while soft errors involving the bit lines increase dramatically as the cycle time decreases. 3.4

Single-Event Upset Mechanisms in SRAMs

The upset process in SRAMs is quite different from DRAMs, due to the active feedback in the cross-coupled inverter pair that forms a typical SRAM memory cell. When an energetic particle strikes a sensitive location in a SRAM (typically the reverse-biased drain junction of a transistor biased in the “off” state [70,87], for example the “off” n-channel transistor shown in Figure 3.9), charge collected by the junction results in a transient current in the struck transistor. As this current flows through the struck transistor, the restoring transistor (“on” p-channel transistor in Fig. 3.9) sources current in an attempt to balance the particle-induced current. Unfortunately, the restoring transistor has a finite amount of current drive, and equally importantly, a finite channel conductance. Current flow therefore induces a voltage drop at the drain of the restoring transistor. This voltage transient in response to the single-event current transient is actually the mechanism that can cause upset in SRAM cells. The voltage transient is essentially similar to a write pulse, and can cause the wrong memory state to be locked into the memory cell. In SRAM cells, there are four possible sensitive strike locations, namely the four transistor drains interior to the SRAM circuit. An important consideration for charge collection is whether the junction is located inside a well or in the substrate [70,87]. A diagram of mechanisms for each drain strike location in an n-substrate technology is shown in Figure 3.10. Generally speaking, in each case the transient resulting from an ion strike has a quick initial response followed by a slower, sustained current mechanism [70]. For example, in the familiar outsidethe-well “off” strike (Figure 3.10a), there is an initial drift photocurrent (ip ) followed by diffusion II-19

VDD “on” p-channel (restoring transistor)

Rfb

Ion Strike

Feedback

Rfb

“off” n-channel (struck transistor)

Figure 3.9. Competition between the feedback process and the recovery process governs the SEU response of SRAM cells. current (id ). Both currents are directed such that they tend to raise the struck node voltage and cause SEU. This is the most sensitive strike location for most technologies [87]. In the outsidethe-well “on” strike (Figure 3.10b), the initial drift current again raises the node voltage, but this reinforces the stored logic state. As the node rises, the struck junction becomes slightly forwardbiased, and a conduction (diffusion) current flows opposite to the initial drift current, returning the SRAM to its initial state. This strike location does not produce SEU. Inside-the-well strikes are particularly interesting because of shunt and bipolar effects that can occur in multilayer structures [67]. For the inside-the-well “off” strike (Figure 3.10c), the initial drift current pulls down the struck node potential, initiating the upset process. As the transient proceeds, holes deposited in the p-well are collected at the p-well ties, raising the well potential and leading to injection of electrons by the source [67,68,70,88]. This initiates the inside-the-well bipolar effect discussed in Section 3.2.2 and illustrated in Fig. 3.6. Electrons collected by the substrate do not contribute to upset because the substrate is attached to VDD . However, electrons collected by the n-drain constitute a bipolar current in the same direction as the initial photocurrent, and do contribute to the upset process [70]. For small geometries, the inside-the-well “off” strike can become an important mechanism. In the inside-the-well “on” strike (Figure 3.10d), the ion strike bridges two n-type regions that are at an initial potential difference of VDD . The result is a shunt current that quickly raises the struck node voltage and starts the upset process [89]. This mechanism is self-limiting. As the struck node voltage rises, the potential difference across the shunt disappears. Similar to the inside-the-well “off” strike, holes collected at the p-well ties initiate a bipolar effect, but this time the bipolar current tends to restore the node to its original state. For small geometries, the bipolar effect is strong enough to provide a great deal of intrinsic protection from such strikes [70]. Interestingly, incident particles far below the upset threshold are often sufficiently ionizing to induce a momentary voltage “flip” at the struck node of an SRAM. For example, Figure 3.11 shows drain voltage transients in an SRAM for a particle strike with LET well below the upset II-20

threshold, just below the upset threshold, and just above the upset threshold. Even the particle with LET well below the upset threshold causes a significant voltage transient at the struck drain. Whether an observable SEU occurs depends on which happens faster: the feedback of the voltage transient through the opposite inverter, or recovery of the struck node voltage as the single-event current dies out [63,89,90]. Note that in terms of the fundamental charge-collection characteristics discussed in Section 3.2, drift (including funneling effects) is responsible for the rapid initial flip of the cell, while long-term charge collection by diffusion prolongs the recovery process; both mechanisms are critical to the upset process. The recovery time of an SRAM cell to a particle strike depends on many factors, such as the particle LET, the strike location, etc. From a technology standpoint, the recovery time depends on the restoring transistor current drive and minority carrier lifetimes in the substrate [89,90]. A higher restoring current leads to a faster recovery time, as do decreased minority carrier lifetimes. a) Outside-the-well OFF Strike

b) Outside-the-well ON Strike

VDD

VDD VDD

n-epi p+

VDD

p+

ip

n-epi p+

p+

id

ip

id

VDD➟VDD+

0➟VDD

ip = drift photocurrent id = diffusion current ib = bipolar current

c) Inside-the-well OFF Strike VDD

is = shunt current

VDD

VDD

n+ p-well n-epi

VDD

VDD➟0

0➟VDD➟0

ip

is

ib

n+

n+ p-well n-epi

VDD

Figure 3.10.

d) Inside-the-well ON Strike

ib

n+

VDD

Illustration of possible SRAM upset strike locations and mechanisms [70]. II-21

5.0

Struck Drain Voltage (V)

Threshold LET ≈ 42 MeV-cm2/mg

4.0 2

LET = 9 MeV-cm /mg

3.0 2.0

2

LET = 40.5 MeV-cm /mg

1.0

2

LET = 45 MeV-cm /mg

0.0 10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

Time (s) Figure 3.11. SRAM struck drain voltage transients for ion strikes with LET well below, just below, and just above the SEU threshold. Even the ion strike with LET well below the actual SEU threshold is sufficiently ionizing to momentarily flip the struck node voltage. This is because a higher restoring current is more quickly able to re-establish the struck node voltage, while decreased substrate minority carrier lifetimes reduce the diffusion current at the struck node. The cell feedback time is simply the time required for the disturbed node voltage to feed back through the cross-coupled inverters and latch the struck device in its disturbed state. This time is related to the cell write time and in its simplest form can be thought of as the RC delay in the inverter pair. This RC time constant is thus a critical parameter for determining SEU sensitivity in SRAMs – the smaller the RC delay, the faster the cell can respond to voltage transients (including write pulses) and the more susceptible the SRAM is to SEU. Obviously this has implications for the sensitivity of future, higher speed technologies, as discussed in Section 6. 3.5

Single-Event Upset in Other Circuit Types

Although we have concentrated on SEU in memory circuits, the reader should be aware that SEUs can occur in almost any integrated circuit. For example, SEU is not constrained to digital circuits, but occurs in analog circuits as well. We have already mentioned the problem of SET in optocouplers, which can lead to errors in data transmission [23,28]. Errors are observed in many analog circuit types, including operational amplifiers [91-93], comparators [93,94], and analogto-digital converters (ADCs) [95-97]. Upsets in ADCs are interesting in that analog errors are observed as corruptions in digital output codes [98]. Figure 3.12 shows an example of analog SEU in a 12-bit ADC, where the SEUs appear as a distribution of erroneous codes around the expected output (4 codes centered at 1428 that were removed in this plot for clarity [95]). An excellent summary of SEU in analog ICs is found in [98]. II-22

Figure 3.12. SEU in a 12-bit analog-to-digital converter [95]. Errors are indicated by deviations from the expected digital output codes (4 codes centered at 1428 that were removed in this plot for clarity). SEUs also occur in digital circuits other than memories, prime examples being microprocessors [99-103] and digital signal processors [103,104]. These digital logic circuits are very difficult to test for SEU due to their complexity, especially for advanced high-speed technologies [105]. Errors in logic circuits are also very sensitive to critical timing windows and logic paths, and may never propagate to the output pins [106-109]. As circuit operating speeds continue to increase, the probability of a momentary glitch in a line voltage from a single-event transient (SET) propagating through a logic path to become an observable error rises. Given the ever-growing demand for higher functionality, faster speeds, and greater integration in tomorrow’s space systems, SEU testing increasingly complex logic ICs will be one of the biggest challenges for the future. 3.6

Single-Event Multiple-Bit Upset

Single-event multiple-bit upsets (MBUs) occur when a single particle strike causes more than one error in an IC. For example, diffusion of charge to closely-spaced junctions can upset more than one bit in both SRAM and DRAM cells [60,110]. For a particle striking an IC at a grazing angle of incidence, the charge track may intersect several sensitive regions and cause multiple upsets [111]. The effects of MBU are typically alleviated by a combination of error-correcting codes that work on a word-by-word basis (see Section 3.8.2) and layout rules that prevent physically-adjacent bits from belonging to the same word of memory. Still, single-word multiplebit upsets (SMUs) can occur and pose a substantial threat to system integrity [112]. MBUs have been observed in on-orbit spacecraft data [113,114].

II-23

Multiple-bit upset in DRAMs has been studied fairly extensively using experiments and 2D cylindrically-symmetric simulations [110,115,116]. Figure 3.13 shows an example error map obtained from heavy-ion exposure of a 256Kb DRAM. MBU error locations are shown as solid capacitor areas, surrounded by the outlines of adjacent capacitors where no errors were observed [110]. Simulations showed that for normal-incidence strikes the charge-collection mechanism responsible for MBU in DRAMs was lateral diffusion of the ion-induced charge to multiple junctions. Funneling can increase charge collected at the struck node, reducing the charge available for diffusive transport to adjacent nodes [115]. Zoutendyk et al. found that for the small capacitances typically associated with individual storage elements, funnel-assisted drift collection for direct hits on a storage node is very limited. For direct bit-line hits with larger nodal capacitance, however, substantially reduced charge collection at adjacent nodes was observed [110]. Ion tracks that do not hit a junction therefore allow the greatest amount of lateral charge transport and constitute the worst-case strike location for MBU [110]. The issue of MBUs in SRAMs has also been studied using simulations [60,117]. In [60], two adjacent SRAM cells were simulated, and the strike location was varied to determine the region of sensitivity to multiple-bit upset from normally-incident heavy ion strikes. A simulated error map was produced showing the region of vulnerability to MBU, as shown in Figure 3.14. Only strikes incident between the two cells were capable of producing MBU for the ion strikes simulated in this work. Strikes directly incident on the drain of one cell resulted in upset of the struck cell, but insufficient charge was collected at the adjacent cell to cause upset. The mechanism for multiple-bit upset in the simulated SRAMs thus was found to be diffusion from between-cell strikes, similar to the DRAM results [60]. For grazing angles of incidence and very closely-spaced cells, however, drift collection and funneling can be expected to play greater roles.

Figure 3.13. Physical map of a cluster of errors due to single-event multiple-bit upset in a 256K DRAM [110]. Error locations are shown as solid black capacitor regions, while outlined capacitor regions indicate bits without errors. II-24

4 µm D ra in

xx

x

xx

D ra in

x x x

T1

G a te

x x x x x x

G a te

T2

S o urc e

S o urc e

S trik e h e re u p s e ts bo th c e lls S trike h e re up s e ts a s in g le ce ll

Figure 3.14. Simulated multiple-bit upset map for two adjacent SRAM cells [60]. For this SRAM, diffusion of charge from ion strikes between cells is responsible for MBU.

3.7

Particle Energy Effects

Heavy-ion tests at accelerator facilities are frequently performed to study mechanisms of SEU, estimate on-orbit error rates, and qualify parts for use in space-based systems. In most facilities used for such SEU testing, the energy of the particles is on the order of a few (1-10) MeV per nucleon (or equivalently, MeV/amu). However, in the actual space environment, the energy of particles reaches hundreds of GeV/amu, with a peak flux at a few hundred MeV/amu [1]. Figure 3.15 shows the galactic cosmic ray energy spectrum for Fe ions in a geostationary orbit at solar minimum conditions behind 100 mil of Al shielding [118]. The range of ion energies available at typical low-energy accelerators such as the Tandem Van de Graaff at Brookhaven National Laboratory (BNL) is marked by the light gray band. Higher energy ions (10-100 MeV/amu) are available at a few facilities, for example the GANIL cyclotron in France and the National Superconducting Cyclotron Laboratory (NSCL) at Michigan State University. The range of ions available at these facilities is marked by the darker gray band in Figure 3.15. Note that even the “high” energy facilities produce ions with energies well below the maximum encountered in space. The linear energy transfer (LET) of the Fe ions as a function of energy is denoted in Figure 3.15 by the shading of the symbols. The usual low-energy test facilities produce ions with energies where they have maximum LET (greater than 20 MeV-cm2/mg for the case of Fe) but lower fluences in space. Ions with intermediate energies (10-100 MeV/amu) are much more abundant and can still possess large enough LETs (between 5 and 20 MeVcm2/mg for Fe) to be of concern, especially for sensitive commercial technologies. Note also that spacecraft shielding becomes ineffective with increased ion energy [1]. Extremely high-energy ions usually have low LETs (less than 0.2 MeV-cm2/mg for Fe) and therefore do not pose a serious SEU threat except for very sensitive devices. At a given LET, a high-energy cosmic ion track will have a much larger radius and much longer range than a low-energy accelerator ion track. This might lead to different chargeII-25

Ion Fluence (#/cm2/day/MeV/amu)

100 2

Ion LET (MeV-cm /mg) 0.2 5

10-1

20

10-2 10-3 10-4

"High" Low Energy Energy Test Test Range Range (GANIL (BNL) & MSU)

10-5 10-6 10-1

100

101

102

103

104

105

106

Energy (MeV/amu) Figure 3.15. Galactic cosmic ray iron spectrum vs. energy with LET denoted by symbol shading [118]. Ion energies available at typical accelerator facilities range from approximately 1-100 MeV/amu. collection properties, and hence, different SEU response. Recent SEU tests at high-energy accelerator facilities have indeed suggested a difference in IC response to particles with different energies. For example, differences between low- and high-energy ion tests have been seen to date in SEU thresholds and saturation cross-sections [119,120], single-event multiple-bit upset (MBU) occurrence [111,121,122], and unexplained inconsistencies in single-event burnout data [123]. Yet, in some cases, no appreciable difference has been observed between low- and highenergy heavy ion data [124-126]. The results that show differences are worrisome in that they raise concerns about the fidelity of accelerator-based tests for simulating the response of parts to the real high-energy ion environment found in space [127,128]. There are certainly cases where low-energy and high-energy ions have unambiguously given different test results. In these cases, however, it is the greatly increased range of high-energy ions that has led to differences rather than radial track structure effects. For example, in grazing angle irradiations, the greatly increased track-length of high-energy ions leads to multiple-bit upsets of many more cells along the track than would be seen with the shorter range of low-energy ions [111,121]. There may be other cases where the larger range of high-energy ions leads to different results, such as cases where the ions must pass through a great deal of material to reach the sensitive region [129]. Devices with vertical structures (e.g., power MOSFETs) may be sensitive to charge collection deep within the substrate and may exhibit interesting energy effects [130]. A recent study using carefully controlled experiments demonstrated that for four CMOS SRAM technologies, no significant differences were observed between low- and high-energy II-26

heavy ion SEU data [118]. For example, Figures 3.16 and 3.17 show low- and high-energy data for two of the tested technologies, a 256Kb SRAM and a 1Mb SRAM. Within experimental uncertainty, the cross-section data measured with low-energy ions (open symbols) and highenergy ions (solid symbols) appear the same. In the few inconclusive cases where there may have been small differences, the low-energy ion data were always conservative compared to the highenergy data. This suggests that standard low-energy ion testing is sufficiently (but not overly) conservative for CMOS SRAM technologies down to 0.5 µm (the smallest technology tested). The results were explained by the fact that the track structures of low- and high-energy ions are not greatly different except in the outer regions where they have low charge density. Due to the large radial extent of the track, high-energy ions might be expected to cause more MBUs than equivalent low-energy ions. The authors of [118] therefore examined their highenergy SEU data for evidence of MBUs. None of the almost 4000 error maps taken at low- and high-energy facilities showed physically adjacent upset locations. Unfortunately, only about 400 of the error maps were from high-energy facilities, but none of these maps gave evidence of an increase in normal-incidence MBUs due to high-energy ions. Of course, at grazing angles of incidence we would expect a big difference between low- and high-energy MBU results due to range effects. In the future it is possible that there will be devices sensitive to the low induced charge densities in the outer regions of high-energy ion tracks, but this does not appear to be the case yet. If such effects do appear, they may manifest themselves as an increase in the cross-section for high-energy ions as devices become more sensitive to indirect strikes that do not hit the junction [118]. These results validate the continued use of standard low-energy heavy ion test facilities such as the BNL Tandem Van de Graaff and the Berkeley 88" Cyclotron for part testing

Cross-section (cm2 )

100 10-1 10-2 Matra 65656 256Kb SRAM All SNs VDD = 4.5 V

10-3 10-4

Brookhaven GANIL MSU

-5

10

10-6 0

10

20

30

40

2

Effective LET (MeV-cm /mg) Figure 3.16. High- vs. low-energy SEU cross-sections for 256Kb SRAMs manufactured in a 0.8-µm radiation-tolerant technology [118]. II-27

Cross-section (cm2 )

100 10-1 10-2 Matra 65608E 1Mb SRAM VDD = 4.5 V

10-3 10-4

Brookhaven GANIL MSU

-5

10

10-6 0

10

20

30

40

2

Effective LET (MeV-cm /mg) Figure 3.17. High- vs. low-energy SEU cross-sections for 1Mb SRAMs manufactured in a 0.5-µm radiation-tolerant technology [118]. and qualification. This is important because the low-energy facilities are in general much better developed as user facilities, more accessible, and considerably cheaper to use. There are cases (e.g., grazing angle of incidence studies) where the use of high-energy ions is essential because of their increased range, and it is possible that in the future energy effects will become more significant. It is also possible that other device types or materials will prove to be more sensitive to energy effects than the Si CMOS SRAMs tested here. Based on the similarity in low-energy and high-energy ion track structures this seems unlikely, but cannot be positively ruled out. For the present, it appears that in most cases standard low-energy heavy-ion test methods are adequate to qualify similar technologies for current spacecraft use. 3.8

Mitigation Techniques

SEU mitigation techniques can be roughly classified into three distinct categories. Systemlevel techniques deal with SEU at the system architecture level. Circuit-level techniques rely on changes in the circuit design to reduce SEU sensitivity. Technology- or device-level hardening requires fundamental changes to the underlying fabrication technology used to manufacture ICs. Because they flow directly from the basic mechanisms of SEU, we will concentrate on technology hardening methods and give only a brief description of circuit- and system-level hardening. A review of several hardening techniques is also found in [131]. 3.8.1

Technology Hardening

The most fundamental method for hardening against SEU is to reduce charge collection at sensitive nodes. This can be accomplished in DRAMs and SRAMs by introducing extra doping layers to limit substrate charge collection [132]. In advanced SRAMs, triple-well [133] and even II-28

quadruple-well [134] structures have been proposed to decrease SEU sensitivity. Retrograde wells and buried layers can also be used to provide an internal electric field that opposes substrate charge collection [135,136]. Even the simple use of an epitaxial substrate instead of a bulk substrate affords some level of reduced charge collection [60,83]. In GaAs-based heterojunction insulated gate FETs (HIGFETs), the use of GaAs buffer layers grown at low temperatures (LT GaAs) has proven a very effective means of limiting charge collection [44,137,138]. The LT GaAs buffer layer prevents charge-enhancement mechanisms and substantially reduces charge collection (by as much as a factor of 100 [44]) because of its subpicosecond minority carrier lifetimes [139]. Figure 3.18 shows measured drain charge-collection transients for 3-MeV α-particle strikes, illustrating the dramatic reduction in charge collection for the LT GaAs HIGFET [44]. An effective technique for reducing charge collection in silicon devices is the use of SOI substrates [140]. In this case the collection volume is reduced by the fact that the active device is fabricated in a thin silicon layer that is dielectrically isolated from the substrate. A diagram of a thin-film partially-depleted SOI transistor is shown in Figure 3.19. In a typical thin-film SOI device, the source and drain penetrate all the way to the buried isolation oxide (BOX). This substantially reduces the SEU-sensitive area, because the reverse-biased drain junction area is limited to the depletion region between the drain and the body of the transistor, as shown in Fig. 3.19. Charge deposited in the silicon substrate underneath the BOX cannot be collected at the drain due to the dielectric isolation. Unfortunately, as briefly mentioned in Section 3.2.2, charge deposited in the body region (for example, by a particle strike to the gate region) can trigger a bipolar mechanism that limits the SEU hardness of SOI circuits [71,140]. Following a

Figure 3.18. Measured charge-collection transients in LT GaAs and conventional GaAs HIGFETs following a 3-MeV alpha-particle strike [44]. Charge collection is greatly reduced by the incorporation of the LT GaAs buffer layer. II-29

Gate

STI

n+ Source

n+ Drain

p Body Buried Oxide

~2000 A STI ~2000 A

Substrate

Figure 3.19. Diagram of a thin-film partially-depleted n-channel SOI transistor. The chargecollection volume is greatly reduced because the top silicon active layer is very thin. Unfortunately, ion strikes to the body region can initiate a bipolar conduction mechanism that limits the SEU hardness of SOI circuits. particle strike to the body of an n-channel SOI transistor, electrons can be collected at the source and drain electrodes. Holes can only escape through the body tie contact, if there is one, or slowly through recombination if there is no body tie. Residual holes left in the body raise the body potential and trigger the lateral parasitic bipolar transistor inherent to the SOI transistor, with the source serving as the emitter, the body as the base, and the drain as the collector. This bipolar current considerably lowers the SEU hardness of SOI and can even lead to a single-event induced latch-up condition in SOI transistors without body ties if the bipolar conduction is sustained [72]. Body ties are sometimes used commercially to reduce floating-body effects under DC operation, and careful attention to body tie design is crucial to maintaining good SEU performance [71,141146]. Even in body-tied SOI designs, manufacturers have found it necessary to incorporate other hardening methods for applications where very high upset thresholds are desired [147,148]. Fully-depleted SOI transistors exhibit reduced floating-body effects, and have shown excellent SEU performance [149]. Given an understanding of the upset mechanism in SRAMs, we can immediately understand another typical technology-level technique used to harden SRAMs against SEU. We have discussed (Section 3.4) how the SEU process in an SRAM is essentially a race condition between the feedback and recovery processes. To harden an SRAM, we need to either slow the feedback process or decrease the recovery time. The feedback process can be slowed by adding either resistance or capacitance to the feedback loop [150]. Cross-coupled feedback resistors (see Fig. 3.9) are the classical method of increasing the cell feedback time by increasing the RC delay in the feedback loop. Unfortunately, because the SEU process in SRAMs looks just like the write process, this same RC delay directly impacts the write pulse width of the SRAM. The resistive decoupling technique is very effective, as illustrated in Figure 3.20. This figure shows the measured SEU cross-section (area of the chip sensitive to SEU) as a function of LET for a microprocessor before and after hardening by resistive decoupling [101]. The predicted upset rate in a geosynchronous orbit for the unhardened microprocessor is about once a day, while in the resistively-hardened part it is about once per century. Unfortunately, the effectiveness of resistive hardening does not come without a price. We have already mentioned the speed penalty incurred by adding feedback resistors. Probably even

II-30

Figure 3.20. Measured SEU cross-section of a 16-bit commercial microprocessor showing the effectiveness of resistive hardening for mitigating SEU [101]. worse than this penalty is the increased process complexity introduced by adding feedback resistors. These resistors are typically implemented in the cell layout as lightly-doped polysilicon regions. Because the resistivity of polysilicon is very sensitive to the doping concentration and numerous other factors, it is very difficult to control the resistor value [151]. Rockett reports that SEU feedback resistor variance may be as much as half the mean value [152]. To add to this problem, polysilicon resistivity has a negative temperature dependence. This leads to a temperature dependence of both the write speed and the SEU response. As low temperature, the feedback resistance increases, providing good SEU performance, but slowing the maximum operating frequency. At higher temperature, the part operates faster, but the SEU threshold drops. These characteristics make it challenging to optimize a resistively-hardened technology so that it will operate within specifications across a wide temperature range. A variation on the resistive hardening method is the use of gated resistors (essentially thinfilm polysilicon transistors) as a feedback element [152]. The advantage of this approach is that during a write pulse the feedback resistance can be lowered to reduce the impact of the feedback element on operating speed. A diagram of the gated resistor-hardened SRAM cell is shown in Figure 3.21. During a write operation, the resistor gates are clocked into a low-resistance condition by the wordline pulse, greatly improving the write speed over a standard resistivelyhardened SRAM. At all other times the resistors are in their “off” (high-resistance) state and protect against SEU in the usual manner. The gated-resistor SRAM is therefore faster than a standard resistively-hardened SRAM, has reduced temperature dependence, and may require no additional area to implement [152]. It does, however, require two levels of polysilicon, which although fairly common, are not present in all technologies. II-31

Figure 3.21. Diagram of a gated-resistor hardened SRAM [152]. Clocking the gated resistor with the wordline reduces the feedback resistance during write pulses, thereby minimizing the timing penalties usually associated with feedback resistors. A similar, but distinct, approach has been used to harden high-density SRAMs in SOI [153]. In this approach an extra transistor is fabricated in the silicon device layer in parallel with a standard cross-coupled polysilicon feedback resistor. Under normal operation, this transistor is off, and the feedback signal must pass through the resistor in the usual manner. During a write pulse, the transistor is turned on, effectively shorting out the feedback resistor and maintaining the write performance of the memory cell. Other decoupling techniques have been proposed that place resistors or diodes in different locations [154-157], usually for the purpose of reducing the impact of the resistors on timing parameters or increasing manufacturability. For the most part these techniques have not been widely used (if at all) and have their own associated tradeoffs. Capacitors have been successfully used as a feedback element in SOI SRAMs [140,147,148], and very recently as a means to improve the soft-error performance of deep-submicron CMOS SRAMs for terrestrial applications [158]. While adding capacitance still degrades timing parameters, one advantage is reduced temperature-dependence compared to resistive hardening. 3.8.2

Circuit- and System-Level Hardening

Because of the invasive nature of device-level hardening (i.e., the requirement for fundamental changes in the manufacturing process), easier to implement methods have been a frequent topic of research. The goal of circuit-level hardening techniques is to design circuits that are inherently SEU-hardened and can therefore be manufactured using any commercial fabrication process. Also sometimes referred to as design-level hardening, this can be an important technique in cases when parts from a radiation-hardened technology are not available II-32

[159]. Several design-hardened SRAM and latch circuits have been proposed and fabricated [160-165]. These memory cells typically rely on redundant circuit elements (usually 12-16 transistors per memory cell as opposed to 6 in a standard unhardened cell) to protect against SEU. Because of the large number of transistors per cell, these designs consume considerably more area (and frequently more power) than 6 transistor cells. While these cells can be appropriate for protecting a limited number of critical data paths, they are not usually suitable for very highly-integrated circuits. A design-hardened SEU tolerant DRAM cell that is comparable in size to conventional single transistor DRAMs has also been proposed [166]. System-level hardening approaches include the use of error detection and correction (EDAC) circuitry to monitor and correct errors as they occur [167-169]. This approach requires that extra bits of information be stored with the data to reconstruct the original data in the event of an upset. System overhead can be non-negligible, but this is sometimes the only method available if relatively susceptible parts must be used. Cruder methods such as watchdog timers, redundancy, lockstep operation, majority voting, etc., are commonly used to detect control system errors [170]. While simple in concept, overhead can again be significant, but in many cases this is the only option available to the spacecraft engineer. Last year’s NSREC Short Course segment by Kinnison and this year’s segment by Heidergott contain additional information on system-level hardening methodology [170,171].

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4.0

BASIC MECHANISMS FOR DESTRUCTIVE SINGLE-EVENT EFFECTS

In this section we will briefly discuss mechanisms for destructive SEE, namely single-event latchup (SEL), single-event gate rupture (SEGR), and single-event burnout (SEB). This is not intended to be a complete list of destructive SEE failure modes, but are some of the more commonly encountered effects. For a more comprehensive discussion of destructive SEE, the reader is directed to the recent NSREC Short Course segment by Johnson and Galloway [172]. 4.1

Single-Event Latchup

It is well-documented that in semiconductors with a p/n/p/n structure, a high-current destructive failure mode known as latchup can occur [173]. Unfortunately, just such a structure occurs in all CMOS technologies when an n-channel transistor is located next to a p-channel transistor, such as in a CMOS inverter used in an SRAM. The p/n/p/n structure can be thought of as a connection of two parasitic bipolar junction transistors (BJTs), as illustrated in Figure 4.1 [174]. For the CMOS structure shown in this figure, a parasitic lateral npn transistor is formed by the n-channel source (emitter), p-substrate (base), and n-well (collector). Similarly, a parasitic vertical pnp transistor is formed by the p-channel source (emitter), n-well (base), and p-substrate (collector). Note that the collector of each parasitic BJT is the base region of its counterpart. This leads to a positive feedback loop between the two transistors, although in normal operation both transistors are in an “off” condition. Depending on interdevice spacing, junction depths, doping densities, etc., the parasitic BJTs can be turned “on” and the positive feedback loop can be activated by a device overvoltage, improper sequencing of power supplies, or the presence of a large substrate or n-well current [173]. Once triggered, the device goes into a sustained highcurrent mode that can destroy the device due to thermal runaway or failure of metallization [174].

Figure 4.1. Illustration of the parasitic latchup structure inherent to bulk CMOS technologies [174]. II-34

Usually it is necessary to reduce or remove power from a device in a latched state to return it to normal operation before destructive failure. 4.1.1

Single-Event Latchup Mechanism

The astute reader will note that one of the triggering mechanisms for latchup listed above was well or substrate currents. This is, of course, exactly what one has in the case of an energetic particle strike, so it should not be surprising that latchup can indeed be initiated by a single-event strike. Single-event latchup (SEL) was observed in ground tests as early as 1979 [175], and at first was limited to heavy ions and bulk technologies. As technology parameters evolved, it was found that some devices fabricated on epitaxial substrates could exhibit latchup [176], and worse still, that protons could induce latchup in sensitive technologies [177-179]. It is beyond our purpose here to give a comprehensive discussion of all that is known on SEL. The reader is referred to many excellent reviews and analyses of the subject for further information [172,174-178,180-186]. As mentioned above, the latchup condition is triggered when the parasitic BJTs inherent in CMOS turn “on”, establishing a positive feedback loop. For SEL, the triggering involves four distinct steps, as described by Johnston, et al. [174]: 1) The particle strike induces a transient current in the well-substrate junction, which in turn results in a voltage drop within the well. The magnitude of the voltage drop depends on the resistivity of the well, well depth, and distance of the strike from the well tie contact. 2) If the voltage drop in the well is large enough, the vertical parasitic BJT becomes forward biased and magnifies current flow into the substrate due to bipolar amplification. 3) Current flowing in the substrate from the vertical BJT produces a voltage drop in the substrate, which in turn forward biases the lateral BJT. Collector current from the lateral BJT provides base current to the vertical BJT, initiating the positive feedback process. 4) Once the regenerative feedback process begins, current increases rapidly and the device can remain latched even after the subsidence of the original particle-induced current. References [174,180,186] give further details of the charge-collection process and initiation of SEL. 4.1.2

Mitigation Techniques

Like almost any single-event effect, techniques have been developed to mitigate the occurrence of SEL. One difference with SEL is that since latchup can also be initiated by electrical signals in normal terrestrial ICs, it is not unique to the space environment. This means that high-volume commercial IC manufacturers also have to deal with latchup on their own accord. Unfortunately, it does not follow that just because an IC is latchup immune in normal environments it will also be latchup free in space [174]. However, the same general techniques that improve latchup characteristics on the ground can usually be expected to improve the SEL response in space environments. The keys to decreasing latchup susceptibility are to decrease the ability of the parasitic BJTs to become forward biased, and to decrease the current gain of the BJTs should they become forward biased. Factors which make it harder to forward bias the BJTs include increasing the substrate and well doping levels (heavier doping decreases series resistance and hence limits II-35

voltage drops) and increasing the well thickness (thicker decreases resistance and again limits voltage drops). Using an epitaxial substrate can decrease latchup sensitivity both by limiting the charge-collection volume, and by decreasing the substrate series resistance. Increasing the spacing between devices lowers the current gain of the lateral BJT (basically by increasing the base thickness), and increasing the well thickness can do the same for the vertical BJT. While at first it seemed that fabrication on epitaxial substrates was enough to eliminate latchup, this can no longer be considered to be the case. Figure 4.2 shows a compilation of data where the latchup threshold LET for several devices and technologies is plotted against the epitaxial layer thickness. The data were compiled from [186,187] after the method of [174]. Because latchup depends on a diverse set of process and layout parameters, there is no clear trend, and in fact one of the most SEL-sensitive parts ever tested is an AMD K-5 microprocessor (latchup threshold = 0.4 MeV-cm2/mg) fabricated on a very thin (2.5 µm) epitaxial substrate [186]. This unexpected result indicates that SEL could become a serious concern for advanced devices that may be designed with very little margin to the latchup point. Other technology changes which decrease latchup susceptibility include the use of retrograde wells and trench isolation [188,189]. The effectiveness of trench isolation for decreasing latchup sensitivity depends heavily on the trench depth, with deeper trenches preventing latchup better than shallow trenches. In technologies such as CMOS/SOI or CMOS/SOS, the latchup path can be completely eliminated due to total dielectric isolation between adjacent devices [190]. Guard bands have been used to lower latchup sensitivity [180,191,192], as have neutron-irradiated substrates to kill parasitic BJT gain [193].

AMD K-5 (0.35 mm)

Figure 4.2. Latchup threshold as a function of epitaxial layer thickness for several technologies [174]. The AMD K-5 is one of the most single-event latchup-sensitive parts that has been tested, even though it is fabricated on a thin epitaxial substrate. II-36

4.2

Single-Event Gate Rupture

Dielectric breakdown can occur when the electric field across an insulating material exceeds some threshold value. When initiated by an energetic particle strike to the gate region of an MOS device, this phenomenon is referred to as a single-event gate rupture (SEGR). In this section we will present the basic mechanism for SEGR, and discuss recent results obtained in power MOSFETs and devices with thin gate oxides. 4.2.1

Single-Event Gate Rupture Mechanism

Single-event gate rupture has been studied most extensively for power devices such as double-diffused power MOSFETs (DMOS), so we will use this device for describing the SEGR mechanism. As shown in Figure 4.3, current flow in the DMOS structure is vertical rather than lateral as in a standard MOSFET [194,195]. Application of a positive bias to the gate in this nchannel DMOSFET inverts the p-body region to form a channel between the n-source at the top of the structure and the drain (substrate) contact at the bottom of the structure. To handle large currents, the full structure usually contains hundreds or thousands of these cells connected in parallel. The thick lightly-doped epitaxial region allows the power MOSFET to sustain high voltages without breakdown. When an ion strikes the neck region through the gate oxide, SEGR can occur as charge is transported near the Si/SiO2 interface. As charge from the ion strike accumulates underneath the gate region (and depending on the gate bias), the electric field in the gate insulator can temporarily increase to above the critical field to breakdown, causing a localized dielectric failure (i.e., an SEGR). The SEGR response in vertical power MOSFETs has two components [196]. The “capacitor response” describes the interaction of the ion directly with the gate dielectric, inducing an oxide breakdown at a lower field than would occur in the absence of the ion strike. If a drain bias is applied when the ion strike occurs, part of the drain voltage Io n P a th neck

G a te

p+

S o u rc e

n+ p

n+ p

p+

ho le s ele ctron s n ep ila ye r n + s u bs tra te

D ra in

Figure 4.3. Structure of a vertical power MOSFET and current flow paths following a heavy ion strike [195]. II-37

may be transferred through the epitaxial layer to the gate interface [194]. This part of the response is referred to as the “substrate response.” Increasing the gate voltage increases susceptibility to SEGR through the capacitor response by increasing the pre-existing electric field in the oxide. Increasing the drain voltage also increases the susceptibility to SEGR because part of this voltage can be coupled to the interface through the substrate response. 4.2.2

Single-Event Gate Rupture in Power MOSFETs

Typical SEGR data taken for vertical power MOSFETs include the critical field to dielectric breakdown as a function of LET [197]. Note that because SEGR is a destructive event, obtaining such data requires that many devices be destroyed during the experiment. Semi-empirical expressions that relate the voltage threshold for SEGR as a function of bias conditions, oxide thickness, and incident particle LET have been developed for specific devices and fit measured SEGR data very well [197,198]. As implied above, the sensitive region for SEGR in vertical power MOSFETs is the neck region under the gate contact, since this is where high fields exist in an oxide. Much of this gate area is not necessary to device operation, and recent studies have proposed eliminating parts of the gate polysilicon (e.g., the cross-hatched region in Fig. 4.3) to decrease the area sensitive to SEGR [199]. Two interesting recent papers have studied the effects of ion energy on SEGR in vertical power MOSFETs [196,200]. The first of these showed that the substrate response had a clear dependence on ion energy [200]. As ion energy increased, the maximum gate voltage that could be applied without producing SEGR decreased until the ion range was sufficient to penetrate the entire epitaxial layer. At this point the device was most sensitive to SEGR. The results were explained by the fact that this condition resulted in the maximum amount of charge being deposited into the epitaxial layer [200]. The authors noted that at zero drain bias (i.e., no substrate response component), there appeared to be no energy dependence of the SEGR gate bias threshold. This observation spurred further research to explicitly measure the capacitor response as a function of ion energy [196]. In this study, no apparent difference was found in the SEGR gate bias threshold as a function of ion, corroborating the earlier data. Data from this study are shown in Figure 4.4. Note the surprising result that the gate bias at the onset of SEGR does not track with the LET value, appearing to be a constant value regardless of the ion energy. Although the results are still not fully understood, the authors presented a new model for the critical gate field to cause SEGR in terms of the atomic number of the incident ion rather than its LET. Further study is necessary in this field to develop physical explanations for this result. 4.2.3

Single-Event Gate Rupture in Thin Gate Oxides

SEGR effects have been studied for some time in power devices, but a topic that has recently received a considerable amount interest is SEGR in logic and memory ICs. As gate oxide thicknesses decrease, SEGR could become a problem in ICs because they will likely be operated at somewhat higher electric fields. Hard errors have occasionally been observed during heavy ion tests of SRAMs, and have been attributed to local total ionizing dose deposition (“microdose”) [201-203]. In 1994, Swift et al. noted the occurrence of a new kind of hard error in 4 Mbit DRAMs that was clearly inconsistent with the microdose phenomenon [204]. For example, these errors did not disappear with high-temperature annealing and showed different retention-time characteristics than microdose hard errors. Other characteristics of the mechanism seemed

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Figure 4.4. Energy dependence of SEGR failure threshold in vertical power MOSFETs for niobium ions [196]. The failure threshold is roughly constant even though the ion LET varies considerably over the energy range. consistent with SEGR failures, but the mechanism was not conclusively identified. Of particular concern was the fact that 4 Mbit DRAMs from the same manufacturer that had undergone a die shrink (0.8 µm to 0.6 µm) were even more sensitive to SEGR, showing hard errors at lower LET and with a much greater cross-section. The electric fields at which ruptures were observed were less than 3 MV/cm. These results led Johnston et al. to conclude that SEGR could become a major failure mechanism for scaled microelectronics in space [205]. Below a feature size of about 0.25 µm, it was predicted that the threshold LET for SEGR would fall below that of Fe, a significant component of the galactic cosmic ray flux. If this were to happen, the SEGR error rate in space would increase several orders of magnitude, making the usage of deep submicron devices in space problematical. This prediction has inspired recent research into scaling trends and mechanisms for SEGR in thin gate oxides [206-209]. The first of these studies investigated the impact of oxide thickness on the critical electric field to rupture in gate oxide capacitors and CMOS ICs [206]. The authors found much higher critical fields to rupture than in [204]. Their results for gate oxide capacitors with an area of ~10-3 cm2 are shown in Figure 4.5 as a function of particle LET and gate oxide thickness. The critical field for SEGR is higher than 5 MV/cm in all cases, and decreasing the oxide thickness increases the critical field for SEGR at any given LET. Similar trends were observed for 16 Kbit and 256 Kbit SRAMs and 12-stage delay chains, although the critical fields to rupture were somewhat lower [206]. The thinnest oxides in Figure 4.5 have critical fields approaching 8 MV/cm, suggesting that advanced technologies may in fact show improved resistance to SEGR. This improvement in critical field to rupture II-39

12

ECR (MV/cm)

10 8

6.5 nm 6.0 nm

6

12 nm 18 nm

4 2 0 20

30

40

50

60

70

80

90

100

2

LET (MeV-cm /mg) Figure 4.5. Critical field to SEGR in thin oxide capacitors as a function of ion LET [206]. correlated well to improved breakdown field strengths prior to irradiation, due to reduced defect generation by hot carriers in thin oxides. It was cautioned, however, that future voltage scaling is highly uncertain and if fields do exceed 5 MV/cm, SEGR could still be a significant concern. Another issue is that not all gate oxides can be expected to behave the same. Oxides from different processes have in fact exhibited different critical fields to rupture. In [207], for example, capacitors with 4.5-nm and 7.5-nm gate oxides from a different process showed much lower critical fields to SEGR compared to the data of [206], although the qualitative trend was similar. As noted by the authors, these differences due to processing make it difficult to conclusively establish whether in the future SEGR will be a problem for a particular technology operating at a specific oxide thickness and power supply voltage. It does appear, however, that the preirradiation dielectric breakdown field strengths are a reliable indicator of relative SEGR vulnerability. Regardless of processing technology, the published data all confirm that for a given oxide thickness, the higher the pre-irradiation breakdown field, the higher the critical field to SEGR [206,208,209]. Clearly there are some technologies where the critical field to SEGR is in the range of 5-6 MeV/cm, at least for high LET ions. Whether SEGR will in fact be a problem in the future depends on many factors, including what voltage scaling trends are actually adopted and if alternative dielectric materials are used [208]. Recent work has probed not only scaling trends, but also the underlying mechanisms for SEGR in thin gate oxides [208,209]. Based on a limited amount of data for varying ion fluences, earlier work suggested that multiple ion hits might be necessary to initiate SEGR [207]. More extensive data gathered since then conclusively show that there is at most a small effect of fluence per irradiation step on the SEGR threshold. Figure 4.6 shows the critical voltage to rupture measured in capacitors with a 7-nm oxide as a function of the number of ions received per irradiation step [209]. There is only a very weak dependence: 15% difference in critical II-40

voltage to SEGR over more than three orders of magnitude of fluence per step. Two pre-stress points are also marked on the plot. For these two points, capacitors were pre-stressed at zero bias with a fluence of 2×108 ions/cm2. Even after this enormous pre-stress†, the voltage to rupture remained unchanged. These data strongly support a true single-ion model for gate rupture [209]. Although SEGR appears to be a true single-ion effect, there is no question that an accumulated fluence of particles does introduce damage to the oxide. This damage (termed precursor ion damage in [209]) does not affect the SEGR threshold, but does increase capacitor leakage currents. Figure 4.7 shows measured I-V curves for a 7-nm capacitor after exposure to successive fluences of Au ions at increasing bias voltages [209]. The fluence step between each curve is 106 ions/cm2. At irradiation bias voltages below 3.7 V, increasing leakage currents beyond 2 V are observed with accumulated particle fluence. This leakage current is associated with precursor ion damage. After 3.7 V was applied during the heavy ion exposure the capacitor’s I-V curve changed dramatically, with the leakage current increasing by four orders of magnitude. This pronounced change in the I-V curve is the characteristic signature of SEGR. The critical voltage to SEGR in this 7-nm oxide capacitor for 360-MeV Au ions is thus 3.7 V. Accumulated fluence damage effects such as those shown before rupture in Fig. 4.7 are an interesting topic to study from a basic mechanisms standpoint. However, the data show that precursor ion damage and SEGR in thin oxides are largely unrelated effects. Also, because of the very low flux of high-LET particles in the near-Earth environment (on the order of 7 Br

6

VCR (V)

5 Au

4 3 2

After prestress of 2E8 ions/cm2 w/ no bias

1

Nominal Fluence

0 1

10

100

1000

10000

Average Ions/Step Figure 4.6. Critical voltage to rupture as a function of heavy ion fluence per step [209]. Only a weak dependence of the rupture voltage is observed over more than three orders of magnitude of particle fluence per step. †

For reference, it would take roughly the present age of the universe to accumulate a fluence of high-LET particles this large in the near-Earth environment.

II-41

10-4

Gate Current (A)

10-5

Area = 0.0025 cm2

Irradiation Bias Pre 3.0 V 3.2 V 3.3 V 3.4 V 3.5 V 3.6 V 3.7 V

10-6 10-7 10-8 10-9 10-10 10-11 10-12 0

1

2

3

4

5

Gate Voltage (V) Figure 4.7. Thin oxide capacitor current-voltage characteristics after successive 106 ions/cm2 irradiations with increasing gate bias [209]. Precursor ion damage is evidenced by the increasing gate current above 2 V as ion fluence was accumulated. The sudden increased current at all voltages for the 3.7-V irradiation is the characteristic signature of SEGR; this capacitor had a SEGR failure threshold of 3.7 V. 0.4 ions/cm2/year with LET ≥ 40 MeV-cm2/mg), precursor ion damage is not expected to have any practical impact on reliability in space. For further information on particle-induced damage effects in thermal and nitrided oxides, the reader is directed to [209]. SEGR has been investigated in oxides thinner than 5 nm [208,209]. These oxides can behave fundamentally differently than thicker oxides. Specifically, they often exhibit a soft breakdown characteristic rather than the hard breakdown shown in Fig. 4.7. For example, 4.5-nm oxide capacitors tested in [208] showed soft breakdown leakage currents on the order of tens to hundreds of µA, compared to 1-10 mA rupture currents observed in identical capacitors with 7.5-nm oxides. Similarly, 5-nm oxide capacitors tested in [209] typically showed only a gradual increase in leakage current similar to precursor ion damage buildup, even at fields as high as 12 MV/cm. For a few capacitors clear rupture signatures were obtained, but these were rare. In cases such as these, the ability to sweep full I-V curves at the irradiation site is invaluable, as simple current monitoring is not very instructive. Interestingly, reliability studies of very thin oxides often show similar soft breakdown characteristics [210]. Another recent result of interest is the angular dependence of SEGR in thin oxides. Traditionally, normal incidence is considered to be the worst-case ion trajectory for SEGR, with the critical voltage to rupture showing a somewhat less than cos(θ) dependence [194]. In early work on SEGR, Wrobel predicted that the angular dependence would disappear when the oxide thickness approached the diameter of the ion track [211]. In [209], the authors investigated the angular dependence of the critical field to rupture as a function of oxide thickness. Their results II-42

are shown in Figure 4.8, where the critical field has been normalized to the value at normal incidence. The results clearly show that the angular dependence of SEGR does indeed disappear for thin oxides. The fact that off-normal ion strikes are effective at producing SEGR increases the threat environment in the isotropic heavy ion environment of space, and this must be accounted for when estimating SEGR susceptibility for thin oxides [209]. The angular data have been explained in terms of ion track structure, and an analytical model for the angular dependence based on a conductive pipe mechanism has been proposed [209]. 4.3

Single-Event Burnout

Single-event burnout (SEB) due to heavy ions, neutrons, and protons has been observed in both vertical power MOSFETs and bipolar transistors [194,195,212-216]. Similar to single-event latchup, SEB is a destructive failure mechanism that comes about due to a parasitic bipolar transistor structure inherent to some devices. Looking again at the power MOSFET structure in Fig. 4.3, a parasitic bipolar transistor is formed by the n-source (emitter), p-body (base), and nepitaxial (collector) regions. Following an ion strike, currents flowing in the p-body can forward bias the emitter-base junction of the parasitic BJT due to the finite conductivity of the p-body region. The parasitic BJT is now operating in the forward active regime, and if the drain-tosource voltage is higher than the breakdown voltage (BVCEO) of the parasitic BJT, avalanche multiplication of the BJT collector current can occur. If this positive feedback (regenerative) current is not limited, it can lead to junction heating and the eventual burnout of the device [212].

2.5 Normalized ECR (MV/cm)

283-MeV Br LET ~ 37 MeV-cm2/mg 1/cos(θ)

2.0

19.2 nm Wrobel '87

1.5

18 nm 12 nm

1.0

7 nm

1

2

3

1/cos(θ) Figure 4.8. Angular dependence of the critical field to rupture for oxides of varying thickness [209]. The angular dependence disappears as the oxide thickness approaches the diameter of the 283-MeV bromine ion track. II-43

One fortunate difference between SEB and SEGR is that non-destructive test procedures exist for SEB. In the simpler of these techniques, a load resistor attached to the drain of the MOSFET provides current limiting and prevents destructive SEB [217]. Current pulses at the source can be counted as SEB events and the SEB cross-section can be non-destructively obtained as a function of either the drain voltage or the particle LET. A newer technique, called Energetic ParticleInduced Charge Spectroscopy (EPICS), measures the collected charge from SEB events rather than sensing current pulses [218]. This technique was developed to give more information on the triggering mechanisms responsible for SEB, and has offered experimental confirmation of the mechanisms described above. An example of results using EPICS for power MOSFETs is shown in Figure 4.9 [218]. At low drain voltages (Fig. 4.9a), a single peak at a collected charge of about 10 pC was observed and corresponded to charge collection in the depletion layer. At moderate drain voltages (Fig. 4.9b), a second peak appears and indicates that the parasitic BJT has been turned on and the source is injecting current into the device. Note that the original peak also moves to the right (higher charge collection) somewhat. This movement was postulated to be due to avalanche multiplication of the primary ion-induced current [218]. At still higher drain voltages (Fig. 4.9c), the regenerative feedback mechanism is established and SEB occurs. This results in a new peak with 3-4 orders of magnitude more collected charge; this peak is the characteristic signature of SEB in EPICS measurements. A new variation on the EPICS technique was recently reported by Kuboyama, et al. [216]. In this study, the authors connected an EPICS system to both the base and collector electrodes of the bipolar transistors under test. Using the “2-dimensional” EPICS spectra, the authors were able to distinguish between SEB events due to ion strikes to different areas of the emitter.

Figure 4.9. Illustration of energetic particle induced charge spectroscopy (EPICS) technique for measuring single-event burnout [218]. II-44

Many other studies of SEB have been performed; not all of them can be summarized here. These include studies of the position-dependence of SEB [219], temperature-dependence of SEB [220], and hardening strategies [221-223]. The interested reader is directed to references [212223] and references therein for further information.

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5.0

MODELING AND SIMULATION OF SINGLE-EVENT MECHANISMS

From the earliest history of numerical device modeling, the radiation effects community has recognized the value of computational modeling for providing insight into the effects of ionizing radiation on microelectronic devices. In fact, pioneering work on one-dimensional drift-diffusion numerical modeling was presented at the Nuclear and Space Radiation Effects Conference as early as 1967 [224,225], winning the Best Paper award for that year [224]. This early work focused on transient radiation response, as single-event upset (SEU) would not be observed experimentally until almost 10 years later [226]. Given the consequences of SEU (potential loss of mission for space applications, a possible show-stopper for increased integration density in terrestrial memory cells), the rapid development of models to explain and predict radiation effects was essential. The development and use of numerical models for radiation effects has proceeded on many levels: the interaction of ionizing particles with matter, physical device simulators that predict the response of devices to incident radiation, circuit simulators that model circuit response to a single event, and codes that predict the error rate that will be observed for a specific part flying in particular orbit. In this short course segment we will only discuss the models that most directly pertain to the actual upset process itself, namely models for simulating ion track structure in semiconductors, and device/circuit models that predict the response of devices to the ion track. Models for predicting error rates have been covered elsewhere [19,22,227]. 5.1

Interaction Models

As discussed earlier, energetic particles can interact with an IC through either direct ionization or nuclear interactions. Computer codes have been developed that simulate spallation reactions and/or upset rates for protons, neutrons, and other cosmic ray components [36,228232]. Since spallation reactions eventually cause upset through the direct ionization process also, we will limit our discussion here to models that predict the direct ionization-induced ion track structure in the semiconductor. The reader is directed to the above references if they desire further information on the simulation of nuclear reactions. 5.1.1

Track Structure Models

An aspect of SEU and charge-collection simulation that has received considerable attention recently is that of the ion-strike track structure used as input to physical device simulation. Most work until the last few years has employed a simple cylinder of uniform charge generation to represent the ion strike. Detailed calculations of ion strike track structure have been performed using Monte Carlo methods [128,233]. As mentioned in Section 3.7, differences in the track structure between typical particles used in SEU experiments and high-energy particles which might be encountered in a real space environment have raised concerns over the fidelity of the operating environment simulated by accelerator tests [118,128]. Charge production around the path of an incident particle is accomplished by the release of energetic electrons (also referred to as delta rays) along the track, which subsequently travel away from the path and produce further electron-hole pairs. The higher the energy of the incident particle, the higher the energy of the delta rays and the larger the radial extent of the induced charge distribution. As it passes through the silicon device, the particle loses energy and hence II-46

the delta rays also become less energetic, releasing charge nearer the center of the path as the particle nears the end of its range. Incident particles therefore generate a characteristic coneshaped charge plasma in the silicon IC. Analytic models for ion track structure have been developed [234-236] and introduced to the radiation effects community [118,237,238]. These models are easy to implement as computer programs, and due to their analytic nature run very quickly. Analytic methods of computing track structure divide the target material into thin slabs perpendicular to the ion path. The incident ion and energy are specified, and the delta ray distribution and radial deposition of charge are calculated analytically in the first slab [237]. The particle energy is updated based on the energy deposition in the slab and the calculation proceeds to the next slab. In some codes, the LET in the slab is calculated by a call to a TRIM subroutine [18], and the energy is instead updated based on this LET and the thickness of the slab [118]. This method may be more accurate because the radial energy deposition tends to somewhat underestimate the energy loss in the slab, especially near the end of the ion path [237]. Analytical track structure codes have been extensively validated against available Monte Carlo results in the literature. Figure 5.1 compares the analytically-computed radial track structures of high- and low-energy ions that have the same incident LET of 11.4 MeV-cm2/mg: 210 MeV Cl and 5.04 GeV Kr [118]. The higher-energy ion strike is more nearly representative of a cosmic particle that might be encountered in the space environment, but such particles are difficult to achieve in typical laboratory particle accelerators. The Cl ion has an energy of 6 MeV/amu, and the Kr ion has an energy of 60 MeV/amu (ranges in silicon are 63.1 µm and 1.1 mm, respectively). The generated charge density at the silicon surface is shown, as a function of radius from the center of the ion track. Note that both axes of this figure are plotted on a log scale, and the charge density is very 1023

Charge Density (cm-3)

1022 210 MeV Chlorine

1021 1020 1019 1018 1017

5.04 GeV Krypton

1016 1015 1014 1013

Gaussian Approximation

1012 1011 0.001

0.01

0.1

1

10

100

Radial Distance (µm) Figure 5.1. High- and low-energy ion track radial charge distribution profiles [118]. Both ions have the same surface-incident LET. II-47

highly peaked about the center of the ion track. The maximum delta-ray radius at the surface for the 210 MeV Cl strike is about 1.9 µm, so beyond this point the generated charge density falls to zero. For the 5.04 GeV Kr strike the maximum delta-ray radius is about 100 µm, so a low density of carriers (with respect to the central core of the track) exists out to this point. For the highenergy Kr ion, the charge deposited beyond 1.9 µm amounts to less than 15% of the total. Since the curves have the same integral charge (i.e., the ions have the same surface-incident LET), this means the high-energy ion has 15% less charge in the central region of the track (evidenced in Figure 5.1 by the fact that the Kr curve is slightly underneath the Cl curve at small radii). If there were a difference in the SEU response caused by the two ions, one would expect the low-energy ion to be more upsetting since the track is slightly more concentrated and can deposit a greater amount of charge in a small sensitive volume [118]. For the high-energy ion, more charge is deposited at large distances where it may not be collected by the sensitive node [239]. Still, this is expected to be a small effect, since so little of the high-energy ion’s charge is deposited past the boundary of the low-energy ion’s path. For a given ion strike, there is also the more fundamental issue of variation of charge density along the path (i.e., LET is not constant as a function of depth, as seen in Fig. 3.1). Detailed studies of the importance of faithfully representing the track structure within device simulations have shown that it is important to include this effect [240,241]. Neglecting this effect can change the transient current response by as much as 20%, while various fits to the radial track structure typically produce less than a 5% change in the total charge collected for ion strikes on simple p/n diodes [241]. In any event, since the analytic track structures are relatively easy to compute, simulation track structures including at least the variation of LET along the path and reasonable estimates of radial charge distribution are recommended [240]. 5.2

Physics-Based Device Models

In previous sections, we have mentioned device modeling and in some cases shown device simulation results, but so far we have been deliberately vague about the actual techniques used for device modeling. In the present section we will remedy this situation and go into some detail into the actual device models used, what they tell us, and some interesting new developments in the field. Certainly the most commonly used formalism for device simulation is that of drift-diffusion models. In a drift-diffusion model, the semiconductor device equations are derived from the Boltzmann Transport Equation using numerous approximations. The equations to be solved are the Poisson equation and the current continuity equations [17], & (1) ∇ •ε E = ρ , & ∂n   ∇ • Jn = q R − G +  , ∂t  

(2)

& ∂p   ∇ • J p = q G − R −  , ∂t  

(3)

together with the constitutive relationships for current density (the actual drift-diffusion equations): II-48

& & J n = qnµ n E + qDn ∇n , & & J p = qpµ p E − qD p ∇p .

(4) (5)

& & In these equations, E and J are the electric field and current density vectors, ρ is the net charge density, R and G are carrier recombination and generation rates, and n and p are the electron and hole densities. In addition, q is the electronic charge, and µ and D are carrier mobility and diffusivity, respectively. These equations are discretized and solved on the mesh using finite-difference or finite-element techniques [242,243]. Drift-diffusion models are highly evolved, and relatively speaking, not terribly computationally intensive, except in the case of 3D models. Because of the assumptions they are based on, however, they are ill-suited to treat many effects becoming important in small-geometry devices, such as velocity overshoot, carrier heating, and quasi-ballistic transport [244]. Nevertheless, because of their computational efficiency, they remain the workhorse simulation tool, even for deep submicron devices. The next step up the device-simulation hierarchy is hydrodynamic and energy balance codes. Based on fewer assumptions, these codes begin to treat non-local effects, but are correspondingly more computer-intensive, based on five equations of state rather than the three of the driftdiffusion method. Energy balance options are available in commercial drift-diffusion-based codes [245], but have not been extensively used for SEU calculations. 2D energy transport codes have been used for ion-induced charge-collection simulations in GaAs devices, where offequilibrium effects are particularly important [138,246,247]. The top rung of the device simulation ladder is Monte Carlo simulation, which makes the fewest assumptions and approximations [248]. Rather than being based on approximations to complicated macroscopic equations, Monte Carlo methods describe carrier transport on a fundamental, microscopic scale using classical equations of motion (e.g., Newton’s first law). The motion of individual carriers is followed as they drift in fields and interact with scattering centers until statistical significance is achieved. Few assumptions are involved other than transport is described using classical physics. The penalty is very high computational intensity as the trajectories of many thousands of particles must be tracked to attain meaningful statistics. The utility of the Monte Carlo method for simulating radiation-induced charge collection was realized very quickly [249]. Early simulations computed two-dimensional “collection maps” of alpha-particle generated carriers in regular arrays of cells, while a follow-up study looked at scaling effects on SEU in DRAMs [249,250]. The methodology was also extended to cosmic-ray induced SEUs [251]. To reduce computation time, these simulations treated the third dimension (depth into the substrate) with analytic models. Monte Carlo simulation has also been applied to studying SEU in short-channel CMOS on SOI technologies [252]. Recently, a fully threedimensional Monte Carlo simulator has been described [253], and used in combination with a circuit simulator [254]. Due to high computational requirements, the response during only the first hundred or so picoseconds was calculated, but continuing improvements in computer speed and computational efficiency can be expected to overcome these limitations. In the future, Monte Carlo SEU simulations may become more commonplace, especially as Monte Carlo algorithms are frequently inherently easy to parallelize.

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5.2.1

3D Device and Mixed-Level Simulations

One of the many challenges of device simulation of radiation effects is the need for advanced, three-dimensional modeling tools. The inherently three-dimensional nature of an ion passing through a microelectronic device is difficult to address with the two-dimensional simulation programs that are routinely used in the semiconductor industry for device analysis. The development of full three-dimensional tools has been fairly recent, however, and much insight has been gained in the past through the use of two-dimensional programs [50,53,54,56,67, 87,89,90,138,154,182,255-263]. The fundamental problem with representing a three-dimensional ion strike in fewer dimensions is shown in Figure 5.2. In a two-dimensional simulation, all quantities are assumed to be extruded into the third dimension, and hence either the correct generated charge density or the correct total charge can be simulated, not both. Scaling schemes have been proposed that adjust the Auger recombination rate in an attempt to correct for geometry effects [258]. Another method is to use quasi-three-dimensional versions of the popular PISCES-II code, based on cylindrical symmetry and coordinate transformations [264]. Many charge collection and SEU studies have been performed using these modified two-dimensional codes [57,59,61,110,115,116,240,241, 265-268]. Unfortunately, there are few devices that exhibit circular symmetry, although through clever use of geometrical approximations, cylindrically symmetric simulations have proven revealing and surprisingly accurate in some cases [110,116]. Full 3D device codes are necessary to model the effects of angled ion strikes [68,241,269] Fully-3D device simulators were first reported in the literature in 1980 [270,271], and some of the early work on three-dimensional device simulation was motivated by alpha-particle reliability issues [272-274]. An early comparison of 2D and 3D charge-collection simulations showed that while the transient responses were qualitatively similar, significant quantitative differences existed, both in the magnitude of the current response and the time scale over which

-+ + + + + -

-+

-+

-+

-+

+ + + + -

+ + + + -

Ion Strike

Two-Dim ensional

Quasi-Three-Dimensional

Three-Dimensional

Correct charge density or Correct total charge Incorrect geom etry Com putationally efficient

Correct charge density Correct total charge Incorrect geom etry Com putationally efficient

Correct charge density Correct total charge Correct geom etry Com putationally intensive

Figure 5.2. Illustration of the inherently three-dimensional nature of ion strikes [51].

II-50

collection was observed [275]. The implication of these results is that while 2D simulations may provide basic insight, 3D simulation is necessary if truly predictive results are to be obtained. Throughout the 1980s companies developed internal 3D device simulators [276-280], but most of these were proprietary and optimized for super-computers. Only in the present decade have numerical techniques and microprocessor speeds been sufficiently improved to bring such tools to the desktop workstation. In the last few years fully three-dimensional device simulators have become commercially available [245,281-283]. Optimized for high-end workstations, a fairly large 3D simulation can generally be performed in about a day. Another consideration that arises in modeling charge collection and SEU is the tight coupling of device and circuit response to incident ionizing radiation. In SRAMs, for example, modeling the struck transistor with typical constant boundary conditions (or even including passive, lumped elements) will never result in an upset being observed in the simulation – by construction the device will always return to its pre-strike state. The best that can be done in this situation is to study the charge-collection characteristics of the struck device, and compare the collected charge to some critical charge to upset. However, the usefulness of this approach is extremely limited for SRAMs, since the charge-collection characteristics are greatly influenced by external loading and the feedback mechanism in latches [67,284]. Additionally, the critical charge itself may be ill-defined, once again being dependent on external loading and specific circuit designs [63,88,285]. Nevertheless, unloaded device simulation has been useful for studying the basic physical properties of charge collection, and for studying DRAMs, where loading effects are not as prevalent and critical charge is well-defined by noise margins [75]. For studying the upset process itself in SRAMs, circuit simulation has been a more usable tool. The single-event induced transient current is modeled as a current source at the struck node, and the effects on the SRAM are calculated with a circuit simulator such as SPICE [285-288]. One strength of this approach is the large scale of the circuit in question that can be modeled; another is its computational efficiency. A drawback is the accuracy of the transient current used as the input stimulus. For example, if the current is based on device simulations of a struck, unloaded device [117], then the circuit simulation inherits the inaccuracy of the improperlyloaded device simulation. If the charge collection input is approximated using one-dimensional, analytical models [288], even greater inaccuracy may result, particularly for heavily-ionizing particles. Still, circuit simulations have provided considerable insight into SEU in SRAMs and have resulted in improvements to hardening techniques for a variety of circuits [131,150,152, 155,166,286,289,290]. In the best of all possible worlds, one would desire a simulation methodology for SRAMs that allows either modeling the entire memory cell in the device domain, or allows concurrent solution of device and circuit equations. The former method has been used quite successfully with the simulation code SIFCOD [291], which permits numerical modeling of multiple devices at once. Modeling an SRAM cell consists of four simultaneous device simulations, tied together through contact boundary conditions, as illustrated in Figure 5.3 [67]. These simulations were the first reported that were capable of studying the actual upset process at the device level, and were thus key to forming an understanding of fundamental mechanisms leading to upset [67,89,90]. Because four numerical device simulations must be performed at once, this technique is fairly computer intensive. More importantly, however, the SIFCOD program performed only 2D computations and hence suffered from the geometric limitations that have been discussed above. II-51

N+

N+

P+

N-EPITAXIAL

N+

+ P

VDD

P2

P1

N+

P-WELL

+ P

N+

N-EPITAXIAL

P+

+

N+

N+

N

N+

N-EPITAXIAL

P

+

P+

ION PATH

N1 N

N+

+

N2

P

+

P+

P-WELL

N-EPITAXIAL

N+

VSS

Figure 5.3. Illustration of the use of multiple simultaneous device simulation to compute the SEU characteristics of a CMOS SRAM [67]. Each device’s characteristics are simulated in the multidimensional device domain. Commercial 3D simulators such as Davinci have a similar capability to simultaneously simulate multiple devices [245], but are not generally used in this mode. Recently, the simultaneous solution of device and circuit equations has been increasingly used. This technique, known as mixed-mode or mixed-level simulation, was developed by Rollins at USC/Aerospace in the late 1980s [292]. The term “mixed-level” is probably less confusing and more descriptive than “mixed-mode.” In a mixed-level simulation of SEU, the struck device is modeled in the “device domain” (i.e., using multi-dimensional device simulation), while the rest of the memory cell is represented by SPICE-like compact circuit models, as illustrated in Figure 5.4. The two regimes are tied together by the boundary conditions at contacts, and the solution to both sets of equations is rolled into one matrix solution [292,293]. The advantage is that only the struck device is modeled in multiple dimensions, while the rest of the circuit consists of computationally-efficient SPICE models. This decreases simulation times over multiple-device techniques and greatly increases the complexity of the external circuitry that can be modeled. Mixed-level capability has been incorporated into many of the commerciallyavailable 3D device codes [245,281-283]. These codes were first used to study SEU in CMOS SRAMs in 1991 [294], and since then have received a great deal of continued use for this purpose [51]. II-52

VDD

Circuit Simulation

Particle Strike

Device Simulation

Figure 5.4. Mixed-level simulations solve the device and circuit equations simultaneously, taking advantage of the localization of the ion strike. Only the struck device is modeled in the multidimensional device domain, reducing the computational burden. 5.2.2

Recent Enhancements

A drawback of the mixed-level method is that coupling effects between adjacent transistors have been shown to exist at the device level using 2D simulations [258]. These effects cannot be taken into account when only the struck device is modeled at the device level. To address this difficulty, a recent paper has described simulation of the entire SRAM cell in the 3D device domain [295]. An illustration of the technique is shown in Figure 5.5 (interconnects between device regions are defined in the usual manner for an SRAM cell, but are not shown in the illustration for clarity). The authors compared the results to standard mixed-level simulations and found that in cases where no coupling effects between transistors existed, mixed-level simulations were adequate to reproduce the full SRAM cell results. For some strike locations, however, coupling effects between adjacent transistors were observed [295]. Mixed-level simulations are incapable of predicting such effects. As inter-device spacing decreases with increasing integration levels, coupling effects can be expected to become more important, and simulating entire the SRAM cell in the device domain may become routinely necessary [295]. Techniques like mixed-level simulation are useful for in-depth studies of SEU in specific small-scale circuits and for given ion strikes. A system designer, however, is more likely to be interested in the total error rate for a large circuit containing many transistors, and operating in some particular environment of interest. Because this is a very difficult problem, requiring detailed environmental models, the probability that a given ion strike causes an SEU is usually treated using analytical methods such as the rectangular parallelpided (RPP) model. Typical methods of solution have been covered in a previous short course and review articles [19,22,227]. Two groups have recently reported on large-scale SEU simulation systems which are aimed at predicting system error rates using a more first-principles basis of the interaction of ions with devices.

II-53

The simpler of these two models [296] targeted the terrestrial alpha-particle-induced softerror rate (SER) in SRAMs. In this system, analytic models with fitting parameters based on 3D device simulations were used for the alpha-induced charge collection and noise current. An equivalent circuit was extracted and circuit simulations were used to determine error margin, or the probability of an upset for a given incident alpha-particle energy and angle. In parallel with this, the probability of a given alpha-particle being emitted by the metal wiring (interconnects or on-chip solder bumps) and impinging on the circuit was computed from topography simulations and emission rates of the materials. The SER is then just the running summation of the probability that a given alpha-particle will be emitted multiplied by the probability that such an alpha-particle would cause an error. Comparisons of simulated and experimentally-observed error rates were reasonably close at low supply voltages, but only within a factor of five at higher voltages, with the simulations underestimating the observed SER [296]. The authors later rewrote the model to include neutron-generated reaction products and found improved agreement with accelerated data obtained using a high-flux neutron beam [297-299]. IBM has taken a similar approach in the development of their advanced soft-error modeling system (SEMM) [300-302]. This code models both terrestrial cosmic rays and on-chip alphaparticle sources, and includes a nuclear spallation simulator to model particle-silicon recoil spectra from first principles [230,303]. In addition to a nuclear spallation model, SEMM includes a Monte Carlo model for diffusion of the incident charge based on the earlier work of Sai-Halasz [249-251], fitting to transient device simulation to determine the temporal shape of the charge collected at the various junctions, circuit simulation to determine critical charges, and can also

p-channel transistors

Ion Path

n-channel transistors

Figure 5.5. Illustration of the simulation of an entire SRAM cell in the three-dimensional device simulation domain. II-54

incorporate statistical data from process variations. This is very computationally intensive, so SEMM makes extensive use of history files to reduce the amount of computation necessary for any one run. Good agreement has been obtained between SEMM results and field experiments with no parameter adjustments, indicating the predictive nature of the model. Figure 5.6 shows the simulated components of the soft-error rate in a bipolar chip [304]. Components are computed due to both alpha-particle sources and the cosmic ray spectrum. Alpha-particle sources include three levels of metal, Pb-Sn solder pads, and a ceramic layer. Note that for events with small critical charge, alpha particles are dominant and mostly come from the Pb-Sn solder and ceramic materials. For critical charges above 250 fC, only cosmic ray events are capable of inducing upset in this chip. IBM has marketed a soft-error simulation service to outside customers based on these capabilities [305].

Figure 5.6. Simulations of relative soft-error rate in a bipolar memory cell due to terrestrial cosmic rays and various on-chip and package-related alpha-particle sources [304].

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6.0

FUTURE TRENDS

One of the biggest worries for single-event effects is how technology trends will impact device susceptibility in the future. Effects such as SEU have already been getting worse with technology evolution. In this section, we discuss key technology drivers, how technology trends may affect hardening strategies, and the phenomenon of single-event effects in ground-based and aircraft microelectronics, a topic of growing concern. 6.1

Technology Drivers Impacting Single-Event Effects

Technology parameters that influence the SEU sensitivity include gate length, gate oxide thickness, and power supply voltage. Increased SEU susceptibility as gate length is decreased has been well documented, and may be due to direct channel conduction [66], bipolar coupling mechanisms between the source and drain [70], or decreased gate capacitance as the gate area is reduced [260]. Figure 6.1 shows an example of the decreased threshold for SEU for two strike locations as gate length is decreased and all other parameters are held constant [70]. The strike locations are the center of the drain for the outside-the-well “off” transistor and the inside-thewell “off” transistor (panels (a) and (c) in Figure 3.10). The results shown were obtained using 3D mixed-level simulations of a model p-substrate technology with 150 kΩ feedback resistors. As gate length is decreased, the SEU threshold for outside-the-well “off” strikes decreases slightly, and the threshold for inside-the-well “off” strikes decreases rapidly due to the bipolar effect [70]. As the power supply is decreased and all other parameters are held constant, the SEU threshold again decreases due to reduced current drive in the restoring transistor and less stored

1000 Outside the well OFF Inside the well OFF

100

10 0.0

1.0 Gate Length (µm)

2.0

Figure 6.1. Scaling trend for SEU threshold LET as a function of gate length from simulations of a p-substrate technology with feedback resistors [70]. All other technology parameters were held constant. II-56

charge in the cell. Simulations of this situation are shown in Figure 6.2a. However, reductions in power supply voltage are usually accompanied by reduced gate oxide thickness. Thinner gate oxides result in higher gate capacitance and higher current drives, so SEU thresholds increase with decreasing gate oxide thickness if all other parameters are constant (Figure 6.2b). However, if all parameters are taken into account, the overall trend is still a general increase in SEU susceptibility with each technology generation. This trend is shown in Figure 6.3, which is a plot of the simulated and experimentally-measured SEU threshold for SRAMs without feedback resistors in the three most recent Sandia CMOS technologies [70]. A factor that is at least as important as the fundamental changes to the physics is simply the reduction in total capacitance as technologies shrink. Remember that the feedback time for the SRAM cell is to first order related to the RC delay in the inverter pair. As device areas shrink, the gate and drain capacitance shrinks, making the device faster but consequently much more susceptible to SEU. SEU can therefore be expected to continue as a growing concern for scaled technologies. Another area that is likely to become increasingly important is the propagation of singleevent transients (SETs) in digital logic circuits. The problem here is that as circuit speeds rise, the probability that a momentary glitch will be clocked as valid data and propagated down the line increases. For example, in Figure 3.11 we saw that even a particle well below the upset threshold can cause a momentary flip in the state of an SRAM cell. Consider the case where this memory cell is actually a digital latch circuit in a microprocessor. In the example of Figure 3.11, if this latch value is read 10 picoseconds after an ion strike and the value is clocked down the line, it matters little that the struck latch eventually returns to its original state, because the corrupt value has already been passed on to the next stage of the circuit. These types of errors are likely to become a pervasive problem as clock speeds continue to increase, and will be difficult to protect against, especially in commercial microprocessors where speed is paramount. It has been suggested that for circuits built in technologies below 0.35 µm, propagated SETs will be a 100

50

10

10 2.5

3.0

3.5

4.0

4.5

5 50

5.0

VDD (V)

a)

100 150 200 Oxide Thickness (Angstroms)

250

b)

Figure 6.2. Simulated scaling trends for SEU threshold LET as a function of a) power supply voltage, and b) gate oxide thickness. II-57

Threshold LET (MeV-cm2/mg)

100 Experimental Range

10

1 0.0

1.0

2.0

Feature Size (µm) Figure 6.3. Overall SEU threshold LET technology trend for the last three generations of Sandia CMOS SRAMs without feedback resistors [70]. The points are the results of 3D mixed-level simulations, and the shaded regions are the measured range. primary single-event failure mode [306]. The interested reader is directed to the final segment of this short course for more information on SETs in digital logic circuits and mitigation strategies [171]. For SEL, the trends from technology evolution are more difficult to predict. Technology trends working to increase SEL susceptibility are decreased well thicknesses and interdevice spacing. On the other hand, the decreased power supply voltages demanded in newer low-power technologies may alleviate latchup concerns, while technologies such as trench isolation also tend to improve latchup resistance. If CMOS/SOI technology proves to be manufacturable and becomes a mainstream technology solution, traditional latchup concerns may vanish. 6.2

Hardening Strategies

A considerable concern for SRAMs requiring SEU hardness in the future is whether traditional resistive hardening techniques will remain a viable option. The resistive decoupling technique is fundamentally incompatible with high speed because it relies on slowing the cell down so that it cannot respond quickly to SEU voltage transients. This tends to mean that the write performance of hardened SRAM cells has to be kept at a nearly constant level to maintain a constant level of SEU hardness. Also, because a smaller, faster SRAM cell has lower capacitance, the feedback resistance required to harden the cell has to be raised to compensate. This can lead to a requirement for very large resistors in advanced technologies. This point is illustrated in Figure 6.4, which shows the results of 3D mixed-level simulations of two resistively-hardened SRAM technology generations. The simulated SEU threshold LET is plotted as a function of feedback resistor value for a 0.6-µm, 5-V technology with transistor widths of II-58

2.3 µm and 1.3 µm, and for a 0.35-µm, 3.3-V technology with a transistor width of 0.75 µm. As can be seen from the predictions, achieving a target LET threshold of 40 MeV-cm2/mg would require a 200-kΩ resistor for the 2.3×0.6 µm2 device, a 600-kΩ resistor for the 1.3×0.6 µm2 device, and a whopping 1.1-MΩ resistor for the 0.75×0.35 µm2 device. Such large resistors would be very difficult to controllably manufacture and would show a significant temperature dependence [151]. Because of this problem and stagnant performance levels, it is likely that for applications requiring a high level of SEU hardness, devices below about 0.5-µm will utilize other hardening techniques, such as SOI, active feedback elements, or circuit hardening. 6.3

Terrestrial and High-Altitude Single-Event Effects

To this point we have discussed the natural space radiation environment and how it interacts with microelectronics to cause single-event effects. A radiation environment also exists in the Earth’s atmosphere, and although less harsh than the space environment, it can also give rise to SEE. In the following sections we will discuss the high-altitude and terrestrial radiation environments and their effects on microelectronics in aircraft electronics systems and at ground level. 6.3.1

The Atmospheric Radiation Environment

2.3 x 0.6 µm

80

2

Threshold LET (MeV-cm /mg)

The atmospheric radiation environment comes about as a result of the space radiation environment impinging on Earth’s atmosphere. As very highly energetic cosmic rays enter the upper atmosphere they interact with oxygen and nitrogen in the atmosphere and produce a

60

1.3 x 0.6 µm

40

0.75 x 0.35 µm

20

0 0

500

1000

1500

Feedback Resistance (kΩ) Figure 6.4. Predicted SEU threshold LET vs. feedback resistance from 3D mixed-level simulations of a 0.6-µm, 5-V technology and a 0.35-µm, 3.3-V technology. Note the requirement for extremely large resistors as the fabrication technology scales. II-59

cosmic ray shower of daughter products [1,307-309]. Note that the primary galactic cosmic rays are so energetic that some of the daughter products can reach all the way through the atmosphere to ground level, equivalent to passing through more than 13 feet of concrete [308]. A diagram of a cosmic ray shower is shown in Figure 6.5. The daughter products primarily responsible for causing upsets in high-altitude and terrestrial electronics are neutrons and protons [307]. The fluxes of neutrons and protons have similar characteristics with respect to energy and altitude variation, with both populations extending to energies greater than 1 GeV. Both neutrons and protons show a maximum flux at an altitude of 55,000-60,000 feet (17-18 km), with the sea-level flux being several hundred times lower than at aircraft altitudes [307]. A plot of the altitude variation of the neutron flux is shown in Figure 6.6a. The neutron flux also varies as a function of latitude, as shown in Figure 6.6b. The neutron flux is highest at the poles, because the primary galactic cosmic rays can penetrate furthest into the atmosphere there due to reduced geomagnetic rigidity [1]. Models have been produced that give the variation of atmospheric neutron flux as a function of altitude, latitude, and solar activity [310]. Note that the atmospheric neutron flux varies with solar activity due to its dependence on the incident galactic cosmic ray flux. Further details on the terrestrial and high-altitude radiation environment can be found in [307,309] and references therein.

Figure 6.5. Illustration of the terrestrial cosmic ray shower caused by the interaction of galactic cosmic rays with the Earth’s atmosphere [308]. II-60

a)

b) Figure 6.6. Variation of the atmospheric neutron flux with a) altitude, and b) latitude [307]. 6.3.2

Historical Perspective and Recent Studies

Oddly enough, the first paper to ever deal with the issue of SEU was not a paper on the use of electronics in the space environment, but a paper assessing scaling trends in terrestrial microelectronics [311]. Interestingly, the authors predicted that the minimum volume of semiconductor devices would be limited to about 10 µm on a side due to terrestrial cosmic ray upsets! The actual occurrence of soft errors in terrestrial microelectronics did not manifest itself until some time later, shortly after the first observations of SEU in space [73]. This first paper from authors at Intel found a significant error rate in DRAMs as integration density increased to 16K and 64K, spurring a flurry of SEU-related work in the late 1970’s [312]. The primary cause of soft errors at the ground level was quickly diagnosed as alpha-particle contaminants in packaging materials. For example, according to Ziegler, the Intel problem was traced to a new LSI ceramic packaging plant that had just been built downstream from the tailings of an abandoned uranium mine [308]. Radioactive contaminants in the water used by the factory were contaminating the ceramic packages they manufactured. After considerable early activity, the II-61

terrestrial soft error problem was mostly alleviated by using low-activity materials and on-chip shielding coatings [308,313]. Occasionally, changes in suppliers or procedures have caused semiconductor manufacturers temporary but considerable headaches due to raised radioactive contaminant levels in materials such as nitric and phosphoric acid [308,314]. The march toward higher integration densities has made soft-error concerns a continual design consideration for advanced DRAM and SRAM development in the last decade. A particular area of recent concern is flip-chip packaging technologies that place a source of alpha particles (Pb-Sn solder bumps) right on the die itself, where they cannot be shielded by coating layers [299]. Even in the absence of on-chip sources of radiation, recent studies have conclusively proved that terrestrial cosmic rays (primarily neutrons) are a significant source of soft errors in both DRAMs and SRAMs [315-317]. Upsets have been observed both at ground level and in aircraft and have been convincingly correlated to the altitude and latitude variation of the neutron flux, as shown in Figure 6.7 [307,315,317]. Lage, et al. have shown that even without alpha particles, a baseline of cosmic-ray upsets still exists for high-density SRAMs [316]. This result is shown in Figure 6.8, which plots the correlation between the measured accelerated soft error rate (ASER, measured using an intense alpha-particle source placed over the SRAM) and the system soft error rate (SSER, the real application error rate measured in many SRAMs operating over a long period of time). If the system SEU rate were due entirely to alpha particles, there would be a simple direct correlation between the SSER and the ASER, but instead the data show a baseline SER due to neutron upsets even in the absence of alpha-particle upsets [316]. O’Gorman has shown that neutron upsets disappear for DRAMs placed 200 meters underground in a salt mine, while they increase dramatically for systems operated above 10,000 feet in Leadville, CO [315]. In addition to SEU observed in memories used in large computer systems and aircraft, upsets have been observed in SRAMs used in implantable medical devices such as cardiac defibrillators

Figure 6.7. Excellent correlation is observed between upsets recorded in avionics and the atmospheric neutron flux [307]. II-62

Figure 6.8. Correlation between system SER (SSER, from field testing) and accelerated SER (ASER, from intense alpha-particle source testing) [316]. The SSER exhibits a baseline error rate due to neutron-induced upsets. [318]. Neutron-induced single-event burnout has even caused destructive failures in large-area, high-voltage power diodes used for railroad applications in Europe [319]. 6.3.3

Mitigation Techniques

Neutron-induced ground-level upset rates have been estimated to be 1-2×10-12 upsets/bit-hr across a range of commercial DRAMs and SRAMs [317]. For a computer workstation with 1 Gbit of memory (128 Mbytes), this could lead to as many as 1-2 errors per month, depending on how much of the memory space is in daily use [317]. Revelations such as these have significant implications for manufacturers of commercial memory chips and computer systems, because systems can’t realistically be shielded against incident neutrons. Meeting specified failure rates is expected to be a significant challenge for commercial semiconductor manufacturers. Terrestrial soft error failure rate specifications are usually given in terms of FIT rates, where FIT = Failure in Time = 1 error in 109 device hours. A typical specification is to maintain a FIT rate less than 1000 [316]. A complicating factor is that since FIT rates are specified per device, meeting a constant FIT rate specification actually requires reducing the error rate per bit as the number of bits per device is increased. It has been suggested that because manufacturers of commercial microelectronics for terrestrial applications have had to deal with alpha-particle-induced upsets from packaging materials, commercial parts will by design remain hard to at least the alpha-particle threshold, as illustrated in Figure 6.9 [207]. This figure shows the critical charge to upset as a function of gate

II-63

length, with the horizontal line indicating the maximum charge supplied by a 5-MeV alpha particle. Indeed, there is historical evidence supporting this view as data from more than 10 years of microprocessor evolution show a constant upset threshold just above the threshold for alpha particle upset. However, it is also known that many manufacturers have specific soft-error driven design rules for placement of devices relative to on-chip solder bumps and/or use hardened circuit designs for I/O circuitry that must be in the vicinity of such on-chip alpha sources [299,320]. This clearly implies that many devices being manufactured are in fact already below the alpha-particle threshold for upset. Many of the techniques traditionally used in the radiation effects community to SEU-harden devices are of such a nature that they would never be adopted by commercial manufacturers. They tend to consume more power, reduce manufacturability, and severely impact IC performance. Commercial DRAMs have generally exhibited a fairly constant SEU performance because DRAM manufacturers have intentionally maintained the unit cell capacitance through the use of clever modifications to the storage cell [321]. The nodal capacitance for SRAMs, however, has been steadily shrinking [316]. To counteract increased terrestrial soft error rates, manufacturers may find it necessary to explicitly add capacitance to high-density SRAMs [158,316]. Lage has predicted that this will be necessary for the 4 Mbit generation of SRAMs and beyond [316]. Design-hardened circuits may be useful for critical paths or circuitry, but because of area penalties will not be adopted on a large scale [320]. The use of error-correcting memory architectures is already becoming more common again and this trend will likely continue. Mitigating soft errors in high-speed digital logic circuits will be especially challenging. Fault-

Figure 6.9. Technology trend for critical charge to upset as a function of feature size, suggesting that SEU sensitivity will be kept above the alpha-particle limit by manufacturers [207]. II-64

tolerant systems are routinely used in aircraft mechanical systems and seem a natural choice for preventing neutron-induced SEU in avionics [322]. SOI is a possible solution to the terrestrial SEU problem, although as noted previously SOI is not automatically upset immune. Manufacturers have demonstrated the ability to produce ultra large-scale SOI DRAMs [323], microprocessors [324], and SRAMs [325], although others remain skeptical of the advantages of SOI [326]. In any event, the fact that commercial manufacturers will be studying SEU should prove beneficial to the radiation effects community inasmuch as it brings new resources to bear on the problem.

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7.0

SUMMARY AND CONCLUSIONS

In this short course segment we began with a review of the radiation environment encountered by space telecommunications systems. In general, the environment consists of trapped and transient protons, heavy ions, and electrons. Because electrons are rarely important for SEE, they were not treated in this segment. Protons are trapped by the Earth’s magnetic field in two belts around the planet, an inner belt and an outer belt. Trapped heavy ions also exist but are not in general energetic enough to cause SEE in shielded systems. The South Atlantic Anomaly is a localized region of intense proton flux at low altitudes (<3000 km) and is an important SEE threat for systems operating in low Earth orbits. Transient particles (protons and heavy ions) ejected by solar events are also important contributors to SEE. Solar events follow a several-year cyclical variation but can occur at any time and produce large particle fluences. The galactic cosmic ray background is inversely proportional to the solar cycle and produces highenergy heavily-ionizing particles. Secondary neutrons and protons are produced by the interaction of galactic cosmic rays with the atmosphere and are important for terrestrial and high-altitude SEE. Non-destructive SEE are caused by charge deposition by direct ionization from heavy ions, and indirect ionization from protons and neutrons. The deposited charge can be collected by drift and diffusion in semiconductor devices, causing current transients that can result in circuit malfunction. Funneling can increase the charge collected due to drift processes, and is especially important for DRAMs and devices not fabricated on epitaxial substrates. In SRAMs, voltage transients can cause upsets by mimicking the write process. In complex and high-speed circuits such as microprocessors, even a momentary glitch can propagate through an IC to cause upsets. SEUs are not unique to digital circuits, and have been observed in analog devices. Multiple-bit upsets occur when more than one bit in a digital circuit is upset by a single particle strike. Mitigation techniques for SEU include system-level methods such as error detection and correction, lockstep execution, and redundant systems using voting. Circuit-level methods are also effective, and several SEU-hardened latch designs have been proposed. These techniques have the advantage of allowing the use of commercial fabrication technologies, but usually lead to greatly increased transistor counts. Traditional radiation-hardened circuits use process techniques such as lightly-doped polysilicon feedback resistors to provide SEU immunity. While very effective, passive feedback elements reduce circuit performance and degrade IC manufacturability. SEE can also cause permanent failures in ICs, such as single-event gate rupture (SEGR), burnout (SEB), or latchup (SEL). Latchup is a concern for any standard CMOS technology, and can be triggered by particle strikes in ICs that are otherwise immune to electrically-induced latchup. Thin epitaxial substrates are usually effective at limiting SEL, but recent data indicate that this may not always be the case. Lower supply voltages in the future may reduce the SEL susceptibility of low-power ICs. SEGR, long a concern for power devices, is a possible concern for other ICs as the gate oxide is thinned. Recent data show that thinner oxides have higher critical fields to rupture, but on the other hand, devices are being run at higher fields these days. In the end the susceptibility of commercial ICs to SEGR in space environments will depend on what scaling rules the manufacturers choose for terrestrial operation. SEB remains a concern primarily for power devices, and must be considered for proper system design. II-66

Simulations of SEE have been crucial to developing an understanding of the mechanisms behind SEE and for suggesting methods for hardening devices. As devices continue to evolve to smaller dimensions, device-level modeling will encounter new challenges such as the ion strike affecting more than a single transistor at a time. A greater level of usefulness can be reached when simulation tools prove to be validated and predictive. At this level, simulations become essential during the design process for reducing the number of “fab-and-test” cycles that must be completed to develop radiation-hardened technologies. Technology trends are unfortunately such that SEE are likely to become even more of a concern for the future. Decreasing feature sizes, lower operating voltage, and higher speeds all conspire to increase susceptibility to SEU. Upset in avionics is an established concern. Upset at the ground level will continue to be an increasing concern for manufacturers of microelectronics for terrestrial applications. The use of flip-chip packaging and multiple levels of metals will only serve to further exacerbate the problem. Typical methods of mitigation that either increase the transistor count or reduce IC performance will likely not be acceptable to commercial manufacturers, and new methods will need to be developed. Silicon-on-insulator (SOI) technology may help in this regard, but is not a magic bullet to end all SEE concerns. Hopefully, the fact that commercial manufacturers must deal with SEE concerns will provide a collateral benefit to the radiation effects community as more resources are brought to bear on the problem.

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8.0

ACKNOWLEDGMENTS

The author is grateful for the continuing support, encouragement, and camaraderie of the Radiation Technology and Assurance Department at Sandia National Laboratories. Were it not for the accumulated expertise in the department and hours of stimulating discussions with Peter Winokur, Fred Sexton, Marty Shaneyfelt, Jim Schwank, Dan Fleetwood, and a host of others, the understanding of basic mechanisms of single-event effects represented in this paper would not have been possible. I especially want to thank my family and friends for their patience and understanding as I undertook this work, and especially my wife Melanie whose encouragement was unwavering. I would also like to acknowledge the partial support of Lew Cohn and the Defense Threat Reduction Agency. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under contract DE-AC04-94AL85000.

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9.0

REFERENCES

[1]

J. L. Barth, “Modeling Space Radiation Environments,” 1997 IEEE NSREC Short Course, Snowmass, CO.

[2]

C. S. Dyer, “Space Radiation Environment Dosimetry,” 1998 IEEE NSREC Short Course, Newport Beach, CA.

[3]

J. Feynman and S. B. Gabriel, “High-energy charged particles in space at one astronomical unit,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 344-352, 1996.

[4]

M. S. Gussenhoven, E. G. Mullen, and D. H. Brautigam, “Improved understanding of the Earth’s radiation belts from the CRRES satellite,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 353-368, 1996.

[5]

E. G. Stassinopoulos, G. J. Brucker, D. W. Nakamura, C. A. Stauffer, G. B. Gee, and J. L. Barth, “Solar flare proton evaluation at geostationary orbits for engineering applications,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 369-382, 1996.

[6]

C. S. Dyer, A. Sims, and C. Underwood, “Measurements of the SEE environment from sea level to GEO using the CREAM and CREDO experiments,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 383-402, 1996.

[7]

E. J. Daly, J. Lemaire, D. Heynderickx, and D. J. Rodgers, “Problems with models of the radiation belts,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 403-415, 1996.

[8]

D. Boscher, S. Bourdarie, and T. Beutier, “Dynamic modeling of trapped particles,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 416-425, 1996.

[9]

T. P. Ma and P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices & Circuits, (Wiley, New York, 1989).

[10]

R. L. Pease, “Total-dose issues for microelectronics in space systems,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 442-452, 1996.

[11]

A. R. Frederickson, “Upsets related to spacecraft charging,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 426441, 1996.

[12]

E. L. Petersen, “Soft errors due to protons in the radiation belt,” IEEE Trans. Nucl. Sci., vol. 28, no. 6, pp. 3981-3986, 1981.

[13]

J. R. Cummings, A. C. Cummings, R. A. Mewaldt, R. S. Selesnick, E. C. Stone, T. T. von Rosenvinge, and J. B. Blake, “SAMPEX measurements of heavy ions trapped in the magnetosphere,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1458-1462, 1993.

[14]

T. Kohno, H. Miyasaka, H. Kato, C. Kato, T. Goka, and H. Matsumoto, “Heavy ion radiation in space observed by Japanese satellite,” Proc. 3rd Int. Workshop Rad. Effects on Semiconductor Devices for Space Application, Takasaki, Japan, pp. 90-95, 1998.

[15]

A. J. Tylka, W. F. Dietrich, and P. R. Boberg, “Probability distributions of high-energy solar-heavy-ion fluxes from IMP-8: 1973-1996,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2140-2149, 1997.

[16]

F. W. Sexton, “Measurement of single event phenomena in devices and ICs,” 1992 IEEE NSREC Short Course, New Orleans, LA.

[17]

S. M. Sze, Physics of Semiconductor Devices, (Wiley, New York, 1981).

[18]

J. F. Ziegler, J. P. Biersack, and U. Littmark, The Stopping and Range of Ions in Solids, (Pergamon Press, New York, 1985).

[19]

E. L. Petersen, “Single Event Analysis and Prediction,” 1997 IEEE NSREC Short Course, Snowmass, CO.

All references are unclassified

II-69

[20]

J. Barak, J. Levinson, M. Victoria, and W. Hajdas, “Direct processes in the energy deposition of protons in silicon,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2820-2826, 1996.

[21]

S. Duzellier, R. Ecoffet, D. Falguère, T. Nuns, L. Guibert, W. Hajdas, M. C. Calvet, “Low energy proton induced SEE in memories,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2306-2310, 1997.

[22]

E. L. Petersen, “Approaches to proton single-event rate calculations,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 496-504, 1996.

[23]

P. W. Marshall, C. J. Dale, M. A. Carts, and K. A. LaBel, “Particle-induced bit errors in high performance fiber optic data links for satellite data management,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 1958-1965, 1994.

[24]

K. A. LaBel, P. W. Marshall, C. J. Marshall, M. D’Ordine, M. Carts, G. K. Lum, H. S. Kim, C. M. Seidleck, T. Powell, R. Abbott, J. Barth, and E. G. Stassinopoulos, “Proton-induced transients in optocouplers: in-flight anomalies, ground irradiation test, mitigation and implications,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 1885-1892, 1997.

[25]

R. A. Reed, P. W. Marshall, A. H. Johnston, J. L. Barth, C. J. Marshall, K. A. LaBel, M. D’Ordine, H. S. Kim, and M. A. Carts, “Emerging optocoupler issues with energetic particle-induced transients and permanent radiation degradation,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2833-2841, 1998.

[26]

C. J. Marshall, P. W. Marshall, M. A. Carts, R. A. Reed, and K. A. LaBel, “Proton-induced transient effects in a metal-semiconductor-metal (MSM) photodetector for optical-based data transfer,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2842-2848, 1998.

[27]

P. W. Marshall, C. J. Dale, and K. A. LaBel, “Space radiation effects in high performance fiber optic data links for satellite data management,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 645-653, 1996.

[28]

A. H. Johnston, G. M. Swift, T. Miyahira, S. Guertin, and L. D. Edmonds, “Single-event upset effects in optocouplers,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2867-2875, 1998.

[29]

G. R. Hopkinson, C. J. Dale, and P. W. Marshall, “Proton effects in charge-coupled devices,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 614-627, 1996.

[30]

P. W. Marshall and C. J. Marshall, “Proton Effects and Test Issues for Satellite Applications,” 1999 IEEE NSREC Short Course, Norfolk, VA.

[31]

R. A. Reed, P. J. McNulty, and W. G. Abdel-Kader, “Implications of angle of incidence in SEU testing of modern circuits,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2049-2054, 1994.

[32]

C. Inguimbert, S. Duzellier, R. Ecoffet, and J. Bourrieau, “Proton upset rate simulation by a Monte Carlo method: importance of the elastic scattering mechanism,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 22432249, 1997.

[33]

M. W. Savage, P. J. McNulty, D. R. Roth, and C. C. Foster, “Possible role for secondary particles in proton-induced single event upsets of modern devices,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 27452751, 1998.

[34]

P. J. McNulty, W. J. Beauvais, and D. R. Roth, “Determination of SEU parameters of NMOS and CMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1463-1470, 1991.

[35]

R. A. Reed, P. J. McNulty, W. J. Beauvais, and D. R. Roth, “Charge collection spectroscopy,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1880-1887, 1993.

[36]

P. J. McNulty, “Single-event effects experienced by astronauts and microelectronic circuits flown in space,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 475-482, 1996.

[37]

R. S. Wagner, J. M. Bradley, C. J. Maggiore, J. G. Beery, and R. B. Hammond, “An approach to measure ultrafast-funneling-current transients,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1651-1656, 1986.

All references are unclassified

II-70

[38]

R. S. Wagner, J. M. Bradley, N. Bordes, C. J. Maggiore, D. N. Sinha, and R. B. Hammond, “Transient measurements of ultrafast charge collection in semiconductor diodes,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1240-1245, 1987.

[39]

R. S. Wagner, N. Bordes, J. M. Bradley, C. J. Maggiore, A. R. Knudson, and A. B. Campbell, “Alpha, boron, silicon, and iron ion-induced current transients in low-capacitance silicon and GaAs diodes,” IEEE Trans. Nucl. Sci., vol. 35, pp. 1578-1584, 1988.

[40]

S. J. Heileman, W. R. Eisenstadt, R. M. Fox, R. S. Wagner, N. Bordes, and J. M. Bradley, “CMOS VLSI single event transient characterization,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2287-2291, 1989.

[41]

I. Nashiyama, T. Hirao, T. Kamiya, H. Yutoh, T. Nishijima, and H. Sekiguti, “Single-event current transients induced by high energy ion microbeams,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1935-1940, 1993.

[42]

D. McMorrow, J. S. Melinger, N. Thantu, A. B. Campbell, T. R. Weatherford, A. R. Knudson, L. H. Tran, and A. Peczalski, “Charge-collection mechanisms of heterostructure FETs,” IEEE Trans. Nucl. Sci., vol. 41, pp. 2055, 1994.

[43]

J. R. Schwank, F. W. Sexton, T. R. Weatherford, D. McMorrow, A. R. Knudson, and J. S. Melinger, “Charge collection in GaAs MESFETs fabricated in semi-insulating substrates,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1585-1591, 1995.

[44]

D. McMorrow, T. R. Weatherford, W. R. Curtice, A. R. Knudson, S. Buchner, J. S. Melinger, J. H. Tran, and A. B. Campbell, “Elimination of charge-enhancement effects in GaAs FETs with a low-temperature grown GaAs buffer layer,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1837-1843, 1995.

[45]

S. Buchner, A. B. Campbell, T. Weatherford, A. Knudson, P. McDonald, D. McMorrow, B. Fischer, S. Metzger, and M. Schlögl, “Charge collection in GaAs MESFET circuits using a high energy microbeam,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2897-2903, 1996.

[46]

D. McMorrow, J. S. Melinger, A. R. Knudson, S. Buchner, and A. B. Campbell, “Charge-collection mechanisms of AlGaAs/GaAs HBTs,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2274-2281, 1997.

[47]

F. W. Sexton, “Microbeam studies of single-event effects,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 687695, 1996.

[48]

S. Buchner, J. B. Langworthy, W. J. Stapor, A. B. Campbell, and S. Rivet, “Implications of the spatial dependence of the single-event upset threshold in SRAMs measured with a pulsed laser,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2195-2202, 1994.

[49]

H. Schöne, D. S. Walsh, F. W. Sexton, B. L. Doyle, P. E. Dodd, J. F. Aurand, R. S. Flores, N. Wing, “Time-resolved ion beam induced charge collection (TRIBICC) in microelectronics,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2544-2549, 1998.

[50]

C. M. Hsieh, P. C. Murley, and R. R. O’Brien, “A field-funneling effect on the collection of alpha-particlegenerated carriers in silicon devices,” IEEE Electron Device Lett., vol. 2, no. 4, pp. 103-105, 1981.

[51]

P. E. Dodd, “Device simulation of charge collection and single-event upset,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 561-575, 1996.

[52]

R. F. Pierret, Advanced Semiconductor Fundamentals, Volume VI of the Modular Series on Solid State Devices, (Addison-Wesley, Reading, MA, 1987).

[53]

C. M. Hsieh, P. C. Murley, and R. R. O’Brien, “Dynamics of charge collection from alpha-particle tracks in integrated circuits,” Proc. IEEE Int. Reliability Phys. Symp., pp. 38-42, 1981.

[54]

C. M. Hsieh, P. C. Murley, and R. R. O’Brien, “Collection of charge from alpha-particle tracks in silicon devices,” IEEE Trans. Electron Devices, vol. 30, no. 6, pp. 686-693, 1983.

[55]

F. B. McLean and T. R. Oldham, “Charge funneling in n and p-type Si substrates,” IEEE Trans. Nucl. Sci., vol. 29, no. 6, pp. 2018-2023, 1982. All references are unclassified

II-71

[56]

H. L. Grubin, J. P. Kreskovsky, and B. C. Weinberg, “Numerical studies of charge collection and funneling in silicon device,” IEEE Trans. Nucl. Sci., vol. 31, no. 6, pp. 1161-1166, 1984.

[57]

L. D. Edmonds, “A simple estimate of funneling-assisted charge collection,” IEEE Trans. Nucl. Sci., vol. 38, no. 2, pp. 828-833, 1991.

[58]

L. D. Edmonds, “A theoretical analysis of steady-state photocurrents in simple silicon diodes,” JPL Publication 95-10, March 1995.

[59]

N. E. Islam, R. D. Pugh, C. P. Brothers, W. M. Shedd, B. K. Singaraju, J. W. Howard, Jr., H. Dussault, and O. Fageeha, “Basic mechanisms for enhanced prompt charge collection in a n+p junction following single charged particle interaction,” J. Appl. Phys., vol. 84, no. 5, pp. 2690-2696, 1998.

[60]

P. E. Dodd, F. W. Sexton, and P. S. Winokur, “Three-dimensional simulation of charge collection and multiple-bit upset in Si devices,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2005-2017, 1994.

[61]

L. D. Edmonds, “Charge collection from ion tracks in simple EPI diodes,” IEEE Trans. Nucl. Sci., vol. 44, no. 3, pp. 1448-1463, 1997.

[62]

L. D. Edmonds, “Electric currents through ion tracks in silicon devices,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 3153-3164, 1998.

[63]

P. E. Dodd and F. W. Sexton, “Critical charge concepts for CMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1764-1771, 1995.

[64]

E. Takeda, D. Hisamoto, and T. Toyabe, “A new soft-error phenomenon in VLSIs– the alpha-particleinduced source/drain penetration (ALPEN) effect,” Proc. IEEE Int. Reliability Phys. Symp., pp. 109-112, 1988.

[65]

E. Takeda, K. Takeuchi, D. Hisamoto, T. Toyabe, K. Ohshima, and K. Itoh, “A cross section of α-particleinduced soft-error phenomena in VLSIs,” IEEE Trans. Electron Dev., vol. 36, no. 11, pp. 2567-2575, 1989.

[66]

S. Velacheri, L. W. Massengill, and S. E. Kerns, “Single-event-induced charge collection and direct channel conduction in submicron MOSFETs,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2103-2111, 1994.

[67]

J. S. Fu, C. L. Axness, and H. T. Weaver, “Memory SEU simulations using 2-D transport calculations,” IEEE Electron Device Lett., vol. 6, no. 8, pp. 422-424, 1985.

[68]

R. L. Woodruff and P. J. Rudeck, “Three-dimensional numerical simulation of single event upset of an SRAM cell,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1795-1803, 1993.

[69]

O. Musseau, “Charge collection and SEU mechanisms,” Radiat. Phys. Chem., vol. 43, no. 1/2, pp. 151-163, 1994.

[70]

P. E. Dodd, F. W. Sexton, G. L. Hash, M. R. Shaneyfelt, B. L. Draper, A. J. Farino, and R. S. Flores, “Impact of technology trends on SEU in CMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 27972804, 1996.

[71]

S. E. Kerns, L. W. Massengill, D. V. Kerns, Jr., M. L. Alles, T. W. Houston, H. Lu, and L. R. Hite, “Model for CMOS/SOI single-event vulnerability,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2305-2310, 1989.

[72]

H. Iwata and T. Ohzone, “Numerical analysis of alpha-particle-induced soft errors in SOI MOS devices,” IEEE Trans. Electron Dev., vol. 39, no. 5, pp. 1184-1190, 1992.

[73]

T. C. May and M. H. Woods, “A new physical mechanism for soft errors in dynamic memories,” Proc. IEEE Int. Reliability Phys. Symp., pp. 33-40, 1978.

[74]

T. C. May and M. H. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. 26, no. 1, pp. 2-9, 1979.

[75]

L. W. Massengill, “Cosmic and terrestrial single-event radiation effects in dynamic random access memories,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 576-593, 1996.

All references are unclassified

II-72

[76]

D. C. Shaw, G. M. Swift, and A. H. Johnston, “Radiation evaluation of an advanced 64Mb 3.3V DRAM and insights into the effects of scaling on radiation hardness,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1674-1680, 1995.

[77]

T. Matsukawa, S. Mori, T. Tanii, T. Arimura, M. Koh, K. Igarashi, T. Sugimoto, and I. Ohdomari, “Evaluation of soft-error hardness of DRAMs under quasi-heavy ion irradiation using He single ion microprobe technique,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2849-2855, 1996.

[78]

K. A. LaBel, M. M. Gates, A. K. Moran, H. S. Kim, C. M. Seidleck, P. Marshall, J. Kinnison, and B. Carkhuff, “Radiation effect characterization and test methods of single-chip and multi-chip stacked 16Mbit DRAMs,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2974-2981, 1996.

[79]

C. I. Lee, D. N. Nguyen, and A. H. Johnston, “Total ionizing dose effects on 64Mb 3.3V DRAMs,” IEEE NSREC Data Workshop Record, pp. 97-100, 1997.

[80]

R. Harboe-Sørensen, M. Brüggemann, R. Müller, and F. J. Rombeck, “Radiation evaluation of 3.3 volt 16 M-bit DRAMs for solid state mass memory space applications,” IEEE NSREC Data Workshop Record, pp. 74-79, 1998.

[81]

K. A. LaBel, P. W. Marshall, J. L. Barth, R. B. Katz, R. A. Reed, H. W. Leidecker, H. S. Kim, and C. J. Marshall, “Anatomy of an in-flight anomaly: investigation of proton-induced SEE test results for stacked IBM DRAMs,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2898-2903, 1998.

[82]

J.-H. Chern, P. Yang, P. Pattnaik, and J. Seitchik, “Alpha-particle-induced charge transfer between closely spaced memory cells,” IEEE Trans. Electron Dev., vol. 33, no. 6, pp. 822-834, 1986.

[83]

D. S. Yaney, J. T. Nelson, and L. L. Vanskike, “Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability,” IEEE Trans. Electron Dev., vol. 26, no. 1, pp. 10-16, 1979.

[84]

T. Toyabe, T. Shinoda, M. Aoki, H. Kawamoto, K. Mitsusada, T. Masuhara, and S. Asai, “A soft error rate model for MOS dynamic RAMs,” IEEE J. Solid-State Circuits, vol. 17, no. 2, pp. 362-367, 1982.

[85]

G. Schindlbeck, “Analysis of dynamic RAMs by use of alpha irradiation,” Proc. IEEE Int. Reliability Phys. Symp., pp. 30-34, 1979.

[86]

T. V. Rajeevakumar, N. C. Liu, W. H. Henkels, W. Hwang, and R. Franch, “A new failure mode of radiation-induced soft errors in dynamic memories,” IEEE Electron Dev. Lett., vol. 9, no. 12, pp. 644-646, 1988.

[87]

H. T. Weaver, “Soft error stability of p-well versus n-well CMOS latches derived from 2D, transient simulations,” IEDM Tech. Digest, pp. 512-515, 1988.

[88]

C. Detcheverry, C. Dachs, E. Lorfèvre, C. Sudre, G. Bruguier, J. M. Palau, J. Gasiot, and R. Ecoffet, “SEU critical charge and sensitive area in a submicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2266-2273, 1997.

[89]

C. L. Axness, H. T. Weaver, J. S. Fu, R. Koga, and W. A. Kolasinski, “Mechanisms leading to single event upset,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1577-1580, 1986.

[90]

H. T. Weaver, C. L. Axness, J. S. Fu, J. S. Binkley, and J. Mansfield, “RAM cell recovery mechanisms following high-energy ion strikes,” IEEE Electron Device Lett., vol. 8, no. 1, pp. 7-9, 1987.

[91]

R. Koga, S. D. Pinkerton, S. C. Moss, D. C. Mayer, S. LaLumondiere, S. J. Hansel, K. B. Crawford, and W. R. Crain, “Observation of single event upsets in analog microcircuits,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1838-1844, 1993.

[92]

R. Ecoffet, S. Duzellier, P. Tastet, C. Aicardi, and M. Labrunee, “Observation of heavy ion induced transients in linear circuits,” IEEE NSREC Data Workshop Record, pp. 72-77, 1994.

[93]

M. V. O’Bryan, K. A. LaBel, R. A. Reed, J. L. Barth, C. M. Seidleck, P. Marshall, C. Marshall, and M. Carts, “Single event effect and radiation damage results for candidate spacecraft electronics,” IEEE NSREC Data Workshop Record, pp. 39-50, 1998. All references are unclassified

II-73

[94]

D. K. Nichols, J. R. Coss, T. F. Miyahira, and H. R. Schwartz, “Heavy ion and proton induced single event transients in comparators,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2960-2967, 1996.

[95]

T. L. Turflinger and M. V. Davey, “Transient radiation test techniques for high-speed analog-to-digital converters,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2356-2361, 1989.

[96]

T. L. Turflinger, M. V. Davey, and B. M. Mappes, “Single event effects in analog-to-digital converters: device performance and system impact,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2187-2194, 1994.

[97]

S. Bee, G. R. Hopkinson, R. Harboe-Sørensen, L. Adams, and A. Smith, “Heavy-ion study of single event effects in 12- and 16-bit ADCs,” IEEE NSREC Data Workshop Record, pp. 58-67, 1998.

[98]

T. L. Turflinger, “Single-event effects in analog and mixed-signal integrated circuits,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 594-602, 1996.

[99]

S. E. Diehl-Nagle, J. E. Vinson, and E. L. Petersen, “Single-event upset rate predictions for complex logic systems,” IEEE Trans. Nucl. Sci., vol. 31, no. 6, pp. 1132-1138, 1984.

[100]

R. Koga, W. A. Kolasinski, M. T. Marra, and W. A. Hanna, “Techniques of microprocessor testing and SEU-rate prediction,” IEEE Trans. Nucl. Sci., vol. 32, no. 6, pp. 4219-4224, 1985.

[101]

F. W. Sexton, W. T. Corbett, R. K. Treece, K. J. Hass, K. L. Hughes, C. L. Axness, G. L. Hash, M. R. Shaneyfelt, and T. F. Wunsch, “SEU simulation and testing of resistor hardened D-latches in the SA3300 microprocessor,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1521-1528, 1991.

[102]

V. Asenek, C. Underwood, R. Velazco, S. Rezgui, M. Oldfield, Ph. Cheynet, and R. Ecoffet, “SEU induced errors observed in microprocessor systems,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2876-2883, 1998.

[103]

S. H. Crain, W. R. Crain, K. B. Crawford, S. J. Hansel, P. Yu, and R. Koga, “Single event effects test results for the 80C186 and 80C286 microprocessors and the SMJ320C30 and SMJ320C40 digital signal processors,” IEEE NSREC Data Workshop Record, pp. 51-57, 1998.

[104]

R. Koga, K. B. Crawford, S. J. Hansel, W. R. Crain, S. H. Penzin, and S. W. Miller, “The risk of utilizing SEE sensitive COTS digital signal processor (DSP) devices in space,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2982-2989, 1996.

[105]

W. J. Stapor, “Single Event Effects (SEE) Qualification,” 1995 IEEE NSREC Short Course, Madison, WI.

[106]

N. Kaul, B. L. Bhuva, and S. E. Kerns, “Simulation of SEU transients in CMOS ICs,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1514-1520, 1991.

[107]

M. P. Baze, S. Buchner, W. G. Bartholet, and T. A. Dao, “An SEU analysis approach for error propagation in digital VLSI CMOS ASICs,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1863-1869, 1995.

[108]

S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, “Comparison of error rates in combinational and sequential logic,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2209-2216, 1997.

[109]

M. P. Baze and S. P. Buchner, “Attenuation of single event induced pulses in CMOS combinational logic,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2217-2223, 1997.

[110]

J. A. Zoutendyk, L. D. Edmonds, and L. S. Smith, “Characterization of multiple-bit errors from single-ion tracks in integrated circuits,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2267-2274, 1989.

[111]

O. Musseau, F. Gardic, P. Roche, T. Corbière, R. A. Reed, S. Buchner, P. McDonald, J. Melinger, L. Tran, and A. B. Campbell, “Analysis of multiple bit upsets (MBU) in a CMOS SRAM,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2879-2888, 1996.

[112]

R. Koga, S. D. Pinkerton, T. J. Lie, and K. B. Crawford, “Single-word multiple-bit upsets in static random access devices,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1941-1946, 1993.

[113]

J. B. Blake and R. Mandel, “On-orbit observations of single event upset in Harris HB-6508 1K RAMs,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1616-1619, 1986.

All references are unclassified

II-74

[114]

C. I. Underwood, J. W. Ward, C. S. Dyer, and A. J. Sims, “Observations of single-event upsets in nonhardened high-density SRAMs in Sun-synchronous orbit,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 18171827, 1992.

[115]

J. A. Zoutendyk, H. R. Schwartz, and L. R. Nevill, “Lateral charge transport from heavy-ion tracks in integrated circuit chips,” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1644-1647, 1988.

[116]

J. A. Zoutendyk, L. S. Smith, and L. D. Edmonds, “Response of a DRAM to single-ion tracks of different heavy-ion species and stopping powers,” IEEE Trans. Nucl. Sci., vol. 37, no. 6, pp. 1844-1848, 1990.

[117]

Y. Song, K. N. Vu, J. S. Cable, A. A. Witteles, W. A. Kolasinski, R. Koga, J. H. Elder, J. V. Osborn, R. C. Martin, and N. M. Ghoniem, “Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64K × 1 NMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1673-1677, 1988.

[118]

P. E. Dodd, O. Musseau, M. R. Shaneyfelt, F. W. Sexton, C. D’hose, G. L. Hash, M. Martinez, R. A. Loemker, J.-L. Leray, and P. S. Winokur, “Impact of ion energy on single-event upset,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2483-2491, 1998.

[119]

S. Duzellier, D. Falguère, L. Moulière, R. Ecoffet, and J. Buisson, “SEE results using high energy ions,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1797-1802, 1995.

[120]

W. J. Stapor, A. Knudson, J. D. Kinnison, B. G. Carkhuff, and H. Dussault, “A comparison of single-event results from lower energy and higher energy ion beams,” presented at the 32nd Ann. Int. Nuclear and Space Radiation Effects Conf., Madison, WI, 1995.

[121]

T. L. Criswell, P. R. Measel, and K. L. Wahlin, “Single event upset testing with relativistic heavy ions,” IEEE Trans. Nucl. Sci., vol. 31, no. 6, pp. 1559-1562, 1984.

[122]

A. B. Campbell, O. Musseau, V. Ferlet-Cavrois, W. J. Stapor, and P. T. McDonald, “Analysis of single event effects at grazing angle,” IEEE Trans. Nucl. Sci., vol. 45, no. 3, pp. 1603-1611, 1998.

[123]

D. K. Nichols, K. P. McCarty, J. R. Coss, A. Waskiewicz, J. Groninger, D. Oberg, J. Wert, P. Majewski, and R. Koga, “Observations of single event failure in power MOSFETs,” IEEE NSREC Radiation Effects Data Workshop Record, pp. 41-54, 1994.

[124]

R. Ecoffet, S. Duzellier, D. Falguère, L. Guibert, and C. Inguimbert, “Low LET cross-section measurements using high energy carbon beam,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2230-2236, 1997.

[125]

R. A. Reed, M. A. Carts, P. W. Marshall, C. J. Marshall, S. Buchner, M. LaMacchia, B. Mathes, and D. McMorrow, “Single event upset cross sections at various data rates,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2862-2867, 1996.

[126]

R. Koga, S. H. Crain, W. R. Crain, K. B. Crawford, and S. J. Hansel, “Comparative SEU sensitivies to relativistic heavy ions,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2475-2482, 1998.

[127]

W. J. Stapor, P. T. McDonald, A. R. Knudson, A. B. Campbell, and B. G. Glagola, “Charge collection in silicon for ions of different energy but same linear energy transfer (LET),” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1585-1590, 1988.

[128]

R. C. Martin, N. M. Ghoniem, Y. Song, and J. S. Cable, “The size effect of ion charge tracks on single event multiple-bit upset,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1305-1309, 1987.

[129]

O. Musseau, V. Ferlet-Cavrois, A. B. Campbell, W. J. Stapor, and P. T. McDonald, “Comparison of single event phenomena for front/back irradiations,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2250-2255, Dec. 1997.

[130]

J. L. Titus, C. F. Wheatley, K. M. Van Tyne, J. F. Krieg, D. I. Burton, and A. B. Campbell, “Effect of ion energy upon dielectric breakdown of the capacitor response in vertical power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2492-2499, 1998.

[131]

S. E. Kerns and B. D. Shafer, Eds., “The design of radiation-hardened ICs for space: a compendium of approaches,” Proc. IEEE, vol. 76, no. 11, pp. 1470-1509, 1988. All references are unclassified

II-75

[132]

S.-W. Fu, A. M. Mohsen, and T. C. May, “Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-well protection barrier on VLSI memories,” IEEE Trans. Electron Dev., vol. 32, no. 1, pp. 49-54, 1985.

[133]

D. Burnett, C. Lage, and A. Bormann, “Soft-error-rate improvement in advanced BiCMOS SRAMs,” Proc. IEEE Int. Reliability Phys. Symp., pp. 156-160, 1993.

[134]

J. D. Hayden, R. C. Taft, P. Kenkare, C. Mazur, C. Gunderson, B. Y. Nguyen, M. Woo, C. Lage, B. J. Roman, S. Radhakrishna, R. Subrahmanyan, A. R. Sitaram, P. Pelley, J. H. Lin, K. Kemp, and H. Kirsch, “A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAMs,” IEEE Trans. Electron Dev., vol. 41, no. 12, pp. 2318-2325, 1994.

[135]

T. Kishimoto, M. Takai, Y. Ohno, T. Nishimura, and M. Inuishi, “Control of carrier collection efficiency in n+p diode with retrograde well and epitaxial layers,” Jpn. J. Appl. Phys., vol. 36, pt. 1, no. 6A, pp. 34603462, 1997.

[136]

M. Takai, T. Kishimoto, Y. Ohno, H. Sayama, K. Sonoda, S. Satoh, T. Nishimura, H. Miyoshi, A. Kinomura, Y. Horino, and K. Fujii, “Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 696-704, 1996.

[137]

P. W. Marshall, C. J. Dale, T. R. Weatherford, M. Carts, D. McMorrow, A. Peczalski, S. Baier, J. Nohava, and J. Skogen, “Heavy ion SEU immunity of a GaAs complementary HIGFET circuit fabricated on a low temperature grown buffer layer,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1850-1855, 1995.

[138]

T. R. Weatherford, D. McMorrow, A. B. Campbell, and W. R. Curtice, “Significant reduction in the soft error susceptibility of GaAs field-effect transistors with a low-temperature grown GaAs buffer layer,” Appl. Phys. Lett., vol. 67, no. 5, pp. 703-705, 1995.

[139]

D. McMorrow, T. R. Weatherford, S. Buchner, A. R. Knudson, J. S. Melinger, L. H. Tran, and A. B. Campbell, “Single-event phenomena in GaAs devices and circuits,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 628-644, 1996.

[140]

O. Musseau, “Single-event effects in SOI technologies and devices,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 603-613, 1996.

[141]

G. E. Davis, L. R. Hite, T. G. W. Blake, C. E. Chen, H. W. Lam, and R. DeMoyer, “Transient radiation effects in SOI memories,” IEEE Trans. Nucl. Sci., vol. 32, no. 6, pp. 4432-4437, 1985.

[142]

L. W. Massengill, D. V. Kerns, S. E. Kerns, and M. L. Alles, “Single event charge enhancement in SOI devices,” IEEE Electron Dev. Lett., vol. 11, no. 2, pp. 98-99, 1990.

[143]

M. L. Alles, S. E. Kerns, L. W. Massengill, J. E. Clark, K. L. Jones, and R. E. Lowther, “Body tie placement in CMOS/SOI digital circuits for transient radiation environments,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1259-1264, 1991.

[144]

J. Gautier, M. M. Pelella, and J. G. Fossum, “SOI floating-body, device and circuit issues,” IEDM Tech. Digest, pp. 407-410, 1997.

[145]

J. Sleight and K. Mistry, “A compact Schottky body contact technology for SOI transistors,” IEDM Tech. Digest, pp. 419-422, 1997.

[146]

J. W. Sleight, K. R. Mistry, and D. A. Antonaidis, “Transient measurements of SOI body contact effectiveness,” IEEE Electron Dev. Lett., vol. 19, no. 12, pp. 499-501, 1998.

[147]

L. R. Hite, H. Lu, T. W. Houston, D. S. Hurta, and W. E. Bailey, “An SEU resistant 256k SOI SRAM,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 2121-2125, 1992.

[148]

N. van Vonno and B. R. Doyle, “A 256k SRAM implemented in SOI technology,” Proc. RADECS-93, pp. 392-395, 1993.

[149]

P. Francis, J.-P. Colinge, and G. Berger, “Temporal analysis of SEU in SOI/GAA SRAMs,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 2127-2137, 1995. All references are unclassified

II-76

[150]

J. L. Andrews, J. E. Schroeder, B. L. Gingerich, W. A. Kolasinski, R. Koga, and S. E. Diehl, “Single event error immune CMOS RAM,” IEEE Trans. Nucl. Sci., vol. 29, no. 6, pp. 2040-2043, 1982.

[151]

P. S. Winokur, F. W. Sexton, D. M. Fleetwood, M. D. Terry, M. R. Shaneyfelt, P. V. Dressendorfer, and J. R. Schwank, “Implementing QML for radiation hardness assurance,” IEEE Trans. Nucl. Sci., vol. 37, no. 6, pp. 1794-1805, 1990.

[152]

L. R. Rockett, Jr., “Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors,” IEEE Trans. Nucl. Sci., vol. 39, no. 5, pp. 1532-1541, 1992.

[153]

L. M. Cohn, Defense Threat Reduction Agency, private communication.

[154]

H. T. Weaver, C. L. Axness, J. D. McBrayer, J. S. Browning, J. S. Fu, A. Ochoa, and R. Koga, “An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1281-1286, 1987.

[155]

R. L. Johnson, Jr., and S. E. Diehl, “An improved single event resistive-hardening technique for CMOS static RAMs,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1730-1733, 1986.

[156]

A. Ochoa, Jr., C. L. Axness, H. T. Weaver, and J. S. Fu, “A proposed new structure for SEU immunity in SRAM employing drain resistance,” IEEE Electron Dev. Lett., vol. 8, no. 11, pp. 537-539, 1987.

[157]

S. Verghese, J. J. Wortman, and S. E. Kerns, “A novel CMOS SRAM feedback element for SEU environments,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1641-1646, 1987.

[158]

F. Ootsuka, M. Nakamura, T. Miyake, S. Iwahashi, Y. Ohira, T. Tamaru, K. Kikushima, and K. Yamaguchi, “A novel 0.20 µm full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity,” IEDM Tech. Digest, pp. 205-208, 1998.

[159]

D. R. Alexander, “Design Issues for Radiation Tolerant Microcircuits for Space,” 1996 IEEE NSREC Short Course, Indian Wells, CA.

[160]

L. R. Rockett, Jr., “An SEU hardened CMOS data latch design,” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1682-1687, 1988.

[161]

H. T. Weaver, W. T. Corbett, and J. M. Pimbley, “Soft error protection using asymmetric response latches,” IEEE Trans. Electron Dev., vol. 38, no. 6, pp. 1555-1557, 1991.

[162]

M. N. Liu and S. Whitaker, “Low power SEU immune CMOS memory circuits,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1679-1684, 1992.

[163]

D. Wiseman, J. Canaris, S. Whitaker, J. Venbrux, K. Cameron, K. Arave, L. Arave, M. N. Liu, and K. Liu, “Design and testing of SEU/SEL immune memory and logic circuits in a commercial CMOS process,” IEEE NSREC Data Workshop Record, pp. 51-55, 1993.

[164]

R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, and R. Koga, “Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2229-2234, 1994.

[165]

T. Calin, M. Nicolaidis, and R. Velazco, “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, 1996.

[166]

G. R. Agrawal, L. W. Massengill, and K. Gulati, “A proposed SEU tolerant dynamic random access memory (DRAM) cell,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2035-2042, 1994.

[167]

D. C. Bossen and M. Y. Hsaio, “A system solution to the memory soft error problem,” IBM J. Res. Develop., vol. 24, no. 3, pp. 390-397, 1980.

[168]

C. L. Chen and M. Y. Hsiao, “Error-correcting codes for semiconductor memory applications: a state-ofthe-art review,” IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, 1984.

[169]

P. M. O’Neill and G. D. Badhwar, “Single event upsets for space shuttle flights of new general purpose computer memory devices,” IEEE Trans. Nucl. Sci., vol. 41, no. 5, pp. 1755-1764, 1994.

All references are unclassified

II-77

[170]

J. D. Kinnison, “Achieving Reliable, Affordable Systems,” 1998 IEEE NSREC Short Course, Newport Beach, CA.

[171]

W. F. Heidergott, “System Level Mitigation Strategies,” 1999 IEEE NSREC Short Course, Norfolk, VA.

[172]

G. H. Johnson and K. F. Galloway, “Catastrophic Single-Event Effects in the Natural Space Radiation Environment,” 1996 IEEE NSREC Short Course, Indian Wells, CA.

[173]

R. R. Troutman, Latchup in CMOS Technology : The Problem and its Cure, (Kluwer Academic Publishers, Boston, 1986).

[174]

A. H. Johnston, “The influence of VLSI technology evolution on radiation-induced latchup in space systems,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 505-521, 1996.

[175]

W. A. Kolasinski, J. B. Blake, J. K. Anthony, W. E. Price, and E. C. Smith, “Simulation of cosmic-ray induced soft errors and latchup in integrated-circuit computer memories,” IEEE Trans. Nucl. Sci., vol. 26, no. 6, pp. 5087-5091, 1979.

[176]

D. K. Nichols, W. E. Price, M. A. Shoga, J. Duffey, W. A. Kolasinski, and R. Koga, “Discovery of heavyion induced latchup in CMOS/Epi devices,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, p. 1696, 1986.

[177]

L. Adams, E. J. Daly, R. Harboe-Sørensen, R. Nickson, J. Haines, W. Schafer, M. Conrad, H. Griech, J. Merkel, T. Schwall, and R. Henneck, “A verified proton-induced latch-up in space,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1804-1808, 1992.

[178]

D. K. Nichols, J. R. Coss, R. K. Watson, H. R. Schwartz, and R. L. Pease, “An observation of protoninduced latchup,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1654-1656, 1992.

[179]

B. Johlander, R. Harboe-Sørensen, G. Olsson, and L. Bylander, “Ground verification of in-orbit anomalies in the double probe electric field experiment on Freja,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 27672771, 1996.

[180]

G. Bruguier and J.-M. Palau, “Single particle-induced latchup,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 522-532, 1996.

[181]

K. Soliman and D. K. Nichols, “Latchup in CMOS devices from heavy ions,” IEEE Trans. Nucl. Sci., vol. 30, no. 6, pp. 4514-4519, 1983.

[182]

J. G. Rollins, W. A. Kolasinski, D. C. Marvin, and R. Koga, “Numerical simulation of SEU induced latchup,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1565-1570, 1986.

[183]

A. H. Johnston and B. W. Hughlock, “Latchup in CMOS from single particles,” IEEE Trans. Nucl. Sci., vol. 37, no. 6, pp. 1886-1893, 1990.

[184]

Y. Moreau, H. de La Rochette, G. Bruguier, J. Gasiot, F. Pélanchon, C. Sudre, and R. Ecoffet, “The latchup risk of CMOS technology in space,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1831-1837, 1993.

[185]

H. de La Rochette, G. Bruguier, J.-M. Palau, J. Gasiot, and R. Ecoffet, “The effect of layout modification on latchup triggering in CMOS by experimental and simulation approaches,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2222-2228, 1994.

[186]

A. H. Johnston, G. M. Swift, and L. D. Edmonds, “Latchup in integrated circuits from energetic protons,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2367-2377, 1997.

[187]

T. Chapuis, H. C. Erems, and L. H. Rosier, “Latch-up on CMOS/Epi devices,” IEEE Trans. Nucl. Sci., vol. 37, no. 6, pp. 1839-1842, 1990.

[188]

A. G. Lewis, R. A. Martin, T. H. Huang, J. O. Chen, and M. Koyanagi, “Latchup performance of retrograde and conventional n-well CMOS technologies,” IEEE Trans. Electron Dev., vol. 34, no. 10, pp. 2156-2160, 1987.

[189]

P. V. Gilbert, P. E. Crabtree, and S. W. Sun, “Latch-up performance of a sub-0.5 micron inter-well deep trench technology,” IEDM Tech. Dig., pp. 731-734, 1993. All references are unclassified

II-78

[190]

J. P. Colinge, Silicon on Insulator Technology: Materials to VLSI, (Kluwer Academic, Boston, 1991).

[191]

A. Ochoa, Jr. And P. V. Dressendorfer, “A discussion of the role of distributed effects in latch-up,” IEEE Trans. Nucl. Sci., vol. 28, no. 6, pp. 4292-4294, 1981.

[192]

N. Shiono, Y. Sakagawa, T. Matsumoto, and Y. Akasaka, “A 64K SRAM with high immunity from heavy ion induced latch-up,” IEEE Electron Dev. Lett., vol. 7, no. 1, pp. 20-22, 1986.

[193]

J. R. Adams and R. J. Sokel, “Neutron irradiation for prevention of latchup in MOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. 26, no. 6, pp. 5069-5073, 1979.

[194]

J. L. Titus and C. F. Wheatley, “Experimental studies of single-event gate rupture and burnout in vertical power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 533-545, 1996.

[195]

G. H. Johnson, J.-M. Palau, C. Dachs, K. F. Galloway, and R. D. Schrimpf, “A review of the techniques used for modeling single-event effects in power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 546-560, 1996.

[196]

J. L. Titus, C. F. Wheatley, K. M. Van Tyne, J. F. Krieg, D. I. Burton, and A. B. Campbell, “Effect of ion energy upon dielectric breakdown of the capacitor response in vertical power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2492-2499, 1998.

[197]

J. L. Titus, C. F. Wheatley, D. I. Burton, M. Allenspach, J. Brews, R. D. Schrimpf, K. Galloway, I. Mouret, and R. L. Pease, “Impact of oxide thickness on SEGR failure in vertical power MOSFETs; Development of a semi-empirical expression,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1928-1934, 1995.

[198]

C. F. Wheatley, J. L. Titus, and D. I. Burton, “Single-event gate rupture in vertical power MOSFETS; An original empirical expression,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2152-2159, 1994.

[199]

M. Allenspach, C. Dachs, G. H. Johnson, R. D. Schrimpf, E. Lorfèvre, J.-M. Palau, J. R. Brews, K. F. Galloway, J. L. Titus, and C. F. Wheatley, “SEGR and SEB in n-channel power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2927-2931, 1996.

[200]

J. L. Titus, C. F. Wheatley, M. Allenspach, R. D. Schrimpf, D. I. Burton, J. R. Brews, K. F. Galloway, and R. L. Pease, “Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2938-2943, 1996.

[201]

R. Koga, W. R. Crain, K. B. Crawford, D. D. Lau, S. D. Pinkerton, B. K. Yi, and R. Chitty, “On the suitability of non-hardened high density SRAMs for space applications,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1507-1511, 1991.

[202]

C. Dufour, P. Garnier, T. Carrière, J. Beaucour, R. Ecoffet, and M. Labrunée, “Heavy ion induced single hard errors on submicronic memories,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1693-1697, 1992.

[203]

T. R. Oldham, K. W. Bennett, J. Beaucour, T. Carrière, C. Poivey, and P. Garnier, “Total dose failures in advanced electronics from single ions,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1820-1830, 1993.

[204]

G. M. Swift, D. J. Padgett, and A. H. Johnston, “A new class of single event hard errors,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2043-2048, 1994.

[205]

A. H. Johnston, C. I. Lee, B. G. Rax, and D. C. Shaw, “Using commercial semiconductor technologies in space,” Proc. RADECS-95, pp. 175-182, 1995.

[206]

F. W. Sexton, D. M. Fleetwood, M. R. Shaneyfelt, P. E. Dodd, and G. L. Hash, “Single event gate rupture in thin gate oxides,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2345-2352, 1997.

[207]

A. H. Johnston, “Radiation effects in advanced microelectronics technologies,” IEEE Trans. Nucl. Sci., vol. 45, no. 3, pp. 1339-1354, 1998.

[208]

A. H. Johnston, G. M. Swift, T. Miyahira, and L. D. Edmonds, “Breakdown of gate oxides during irradiation with heavy ions,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2500-2508, 1998.

All references are unclassified

II-79

[209]

F. W. Sexton, D. M. Fleetwood, M. R. Shaneyfelt, P. E. Dodd, G. L. Hash, L. P. Schanwald, R. A. Loemker, K. S. Krisch, M. L. Green, B. E. Weir, and P. J. Silverman, “Precursor ion damage and angular dependence of single event gate rupture in thin oxides,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 25092518, 1998.

[210]

B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. A. Alam, G. B. Alers, T. W. Sorsch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, “Ultra-thin gate dielectrics: They break down, but do they fail?” IEDM Tech. Dig., pp. 73-76, 1997.

[211]

T. F. Wrobel, “On heavy ion induced hard-errors in dielectric structures,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 1262-1268, 1987.

[212]

A. W. Waskiewicz, J. W. Groninger, V. H. Strahan, and D. M. Long, “Burnout of power MOS transistors with heavy ions of Californium-252,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1710-1713, 1986.

[213]

J. L. Titus, G. H. Johnson, R. D. Schrimpf, and K. F. Galloway, “Single-event burnout of power bipolar junction transistors,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1315-1322, 1991.

[214]

D. L. Oberg, J. L. Wert, E. Normand, P. P. Majewski, and S. A. Wender, “First observations of power MOSFET burnout with high energy neutrons,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2913-2920, 1996.

[215]

J. W. Adolphsen, J. L. Barth, and G. B. Gee, “First observation of proton induced power MOSFET burnout in space: The CRUX experiment on APEX,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2921-2926, 1996.

[216]

S. Kuboyama, K. Sugimoto, S. Shugyo, S. Matsuda, and T. Hirao, “Single-event burnout of epitaxial bipolar transistors,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2527-2533, 1998.

[217]

D. L. Oberg and J. L. Wert, “First nondestructive measurements of power MOSFET single event burnout cross sections,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1736-1744, 1987.

[218]

S. Kuboyama, S. Matsuda, T. Kanno, and T. Ishii, “Mechanism for single-event burnout of power MOSFETs and its characterization technique,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1698-1703, 1992.

[219]

C. Dachs, F. Roubaud, J.-M. Palau, G. Bruguier, J. Gasiot, and P. Tastet, “Evidence of the ion’s impact position effect on SEB in n-channel power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 21672171, 1994.

[220]

G. H. Johnson, R. D. Schrimpf, K. F. Galloway, and R. Koga, “Temperature dependence of single-event burnout in n-channel power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1605-1612, 1992.

[221]

J. L. Titus, L. S. Jamiolkowski, and C. F. Wheatley, “Development of cosmic ray hardened power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2375-2382, 1989.

[222]

T. F. Wrobel and D. E. Beutler, “Solutions to heavy ion induced avalanche burnout in power devices,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1636-1641, 1992.

[223]

C. Dachs, F. Roubaud, J.-M. Palau, Guy Bruguier, J. Gasiot, P. Tastet, M.-C. Calvet, and P. Calvel, “Simulation aided hardening of n-channel power MOSFETs to prevent single event burnout,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1935-1939, 1995.

[224]

C. W. Gwyn, D. L. Scharfetter, and J. L. Wirth, “The analysis of radiation effects in semiconductor junction devices,” IEEE Trans. Nucl. Sci., vol. 14, no. 6, pp. 153-169, 1967.

[225]

V. A. J. van Lint, J. H. Alexander, D. K. Nichols, and P. R. Ward, “Computerized model for response of transistors to a pulse of ionizing radiation,” IEEE Trans. Nucl. Sci., vol. 14, no. 6, pp. 170-178, 1967.

[226]

D. Binder, E. C. Smith, and A. B. Holman, “Satellite anomalies from galactic cosmic rays,” IEEE Trans. Nucl. Sci., vol. 22, no. 7, pp. 2675-2680, 1975.

[227]

J. C. Pickel, “Single-event effects rate prediction,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 483-495, 1996.

[228]

P. J. McNulty, W. G. Abdel-Kader, and G. E. Farrell, “Proton induced spallation reactions,” Radiat. Phys. Chem., vol. 43, pp. 139-149, 1994. All references are unclassified

II-80

[229]

R. A. Reed, P. J. McNulty, W. J. Beauvais, W. G. Abdel-Kader, E. G. Stassinopoulos, and J. L. Barth, “A simple algorithm for predicting proton SEU rates in space compared to the rates measured on the CRRES satellite,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2389-2395, 1994.

[230]

H. H. K. Tang, G. R. Srinivasan, and N. Azziz, “Cascade statistical model for nucleon-induced reactions on light nuclei in the energy range 50 MeV-1 GeV,” Phys. Rev. C, vol. 42, pp. 1598-1622, 1990.

[231]

E. Normand, “Extensions of the burst generation rate method for wider application to proton/neutroninduced single event effects,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2904-2914, 1998.

[232]

C. Vial, J.-M. Palau, J. Gasiot, M. C. Calvet, and S. Fourtine, “A new approach for the prediction of the neutron-induced SEU rate,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2915-2920, 1998.

[233]

R. N. Hamm, J. E. Turner, H. A. Wright, and R. H. Ritchie, “Heavy-ion track structure in silicon,” IEEE Trans. Nucl. Sci., vol. 26, no. 6, pp. 4892-4895, 1979.

[234]

E. J. Kobetich and R. Katz, “Energy deposition by electron beams and δ rays,” Phys. Rev., vol. 170, no. 2, pp. 391-396, 1968.

[235]

M. P. R. Waligórski, R. N. Hamm, and R. Katz, “The radial distribution of dose around the path of a heavy ion in liquid water,” Int. J. Radiat. Appl. Instrum. D, vol. 11, no. 6, pp. 309-319, 1986.

[236]

R. Katz, K. S. Loh, L. Daling, and G. R. Huang, “An analytic representation of the radial distribution of dose from energetic heavy ions in water, Si, LiF, NaI, and SiO2,” Rad. Eff. Def. Solids, vol. 114, no. 1, pp. 15-20, 1990.

[237]

W. J. Stapor and P. T. McDonald, “Practical approach to ion track energy distribution,” J. Appl. Phys., vol. 64, no. 9, pp. 4430-4434, 1988.

[238]

O. Fageeha, J. Howard, and R. C. Block, “Distribution of radial energy deposition around the track of energetic charged particles in silicon,” J. Appl. Phys., vol. 75, no. 5, pp. 2317-2321, 1994.

[239]

M. A. Xapsos, “Applicability of LET to single events in microelectronic structures,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1613-1621, Dec. 1992.

[240]

H. Dussault, J. W. Howard, Jr., R. C. Block, M. R. Pinto, W. J. Stapor, and A. R. Knudson, “Numerical simulation of heavy ion charge generation and collection dynamics,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1926-1934, 1993.

[241]

H. Dussault, J. W. Howard, Jr., R. C. Block, M. R. Pinto, W. J. Stapor, and A. R. Knudson, “The effects of ion track structure in simulating single event phenomena,” Proc. RADECS93, pp. 509-516, 1993.

[242]

M. Kurata, Numerical Analysis for Semiconductor Devices, (D. C. Heath and Co., Lexington, 1982).

[243]

S. Selberherr, Analysis and Simulation of Semiconductor Devices, (Springer-Verlag, Vienna, 1984).

[244]

M. S. Lundstrom, Fundamentals of Carrier Transport, Volume X of the Modular Series on Solid State Devices, (Addison-Wesley, Reading, MA, 1990).

[245]

Davinci 4.1 User’s Manual (Avant! Corporation, TCAD Business Unit, 1998).

[246]

T. R. Weatherford, D. McMorrow, W. R. Curtice, A. R. Knudson, and A. B. Campbell, “Single event induced charge transport modeling of GaAs MESFETs,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 18671871, 1993.

[247]

J. S. Melinger, S. Buchner, D. McMorrow, W. J. Stapor, T. R. Weatherford, and A. B. Campbell, “Critical evaluation of the pulsed laser method for single event effects testing and fundamental studies,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2574-2584, 1994.

[248]

K. Hess, Monte Carlo Device Simulation: Full Band and Beyond, (Kluwer Academic, Boston, 1991).

[249]

G. A. Sai-Halasz and M. R. Wordeman, “Monte Carlo modeling of the transport of ionizing radiation created carriers in integrated circuits,” IEEE Electron Device Lett., vol. 1, no. 10, pp. 211-213, 1980. All references are unclassified

II-81

[250]

G. A. Sai-Halasz, M. R. Wordeman, and R. H. Dennard, “Alpha-particle-induced soft error rate in VLSI circuits,” IEEE Trans. Electron Devices, vol. 29, no. 4, pp. 725-731, 1982.

[251]

G. A. Sai-Halasz, “Cosmic ray induced soft error rate in VLSI circuits,” IEEE Electron Device Lett., vol. 4, no. 6, pp. 172-174, 1983.

[252]

C. Brisset, P. Dollfus, P. Hesto, and O. Musseau, “Monte Carlo simulation of the dynamic behavior of a CMOS inverter struck by a heavy ion,” IEEE Trans. Nucl. Sci., vol. 41, no. 3, pp. 619-624, 1994.

[253]

C. Brisset, P. Dollfus, N. Chemarin, R. Castagné, and P. Hesto, “Three-dimensional Monte Carlo simulation of submicron devices,” Proc. 5th Int. Conf. Simulation of Semiconductor Devices and Processes (SISDEP), pp. 189-192, 1993.

[254]

C. Brisset, P. Dollfus, O. Musseau, J.-L. Leray, and P. Hesto, “Theoretical study of SEUs in 0.25-µm fullydepleted CMOS/SOI technology,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2297-2303, 1994.

[255]

J. P. Kreskovsky and H. L. Grubin, “Simulation of charge collection in a multilayer device,” IEEE Trans. Nucl. Sci., vol. 32, no. 6, pp. 4140-4144, 1985.

[256]

W. T. Anderson, A. R. Knudson, F. A. Buot, H. L. Grubin, J. P. Kreskovsky, and A. B. Campbell, “Experimental and theoretical study of alpha particle induced charge collection in GaAs FETs,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1326-1331, 1987.

[257]

J. S. Fu, C. L. Axness, and H. T. Weaver, “Two-dimensional simulation of single event induced bipolar current in CMOS structures,” IEEE Trans. Nucl. Sci., vol. 31, no. 6, pp. 1155-1159, 1984.

[258]

J. S. Fu, H. T. Weaver, R. Koga, and W. A. Kolasinski, “Comparison of 2D memory SEU transport simulation with experiments,” IEEE Trans. Nucl. Sci., vol. 32, no. 6, pp. 4145-4149, 1985.

[259]

J. S. Fu, K. H. Lee, R. Koga, W. A. Kolasinski, H. T. Weaver, and J. S. Browning, “Processing enhanced SEU tolerance in high density SRAMs,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1322-1325, 1987.

[260]

J. S. Fu, K. H. Lee, R. Koga, F. W. Hewlett, R. Flores, R. E. Anderson, J. C. Desko, W. J. Nagy, J. A. Shimer, R. A. Kohler, and S. D. Steenwyk, “Scaling studies of CMOS SRAM soft-error tolerances– from 16k to 256k,” IEDM Tech. Digest, pp. 540-543, 1987.

[261]

J. G. Rollins, J. Choma, Jr., and W. A. Kolasinski, “Single event upset in SOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1713-1717, 1987.

[262]

J. H. Chern, J. A. Seitchik, and P. Yang, “Single event charge collection modeling in CMOS multi-junctions structure,” IEDM Tech. Digest, pp. 538-541, 1986.

[263]

D. McMorrow, J. S. Melinger, A. R. Knudson, S. Buchner, L. H. Tran, and A. B. Campbell, “Chargeenhancement mechanisms of GaAs field-effect transistors: experiment and simulation,” Proc. RADECS-97, pp. 346-352, 1997.

[264]

J. G. Rollins, T. K. Tsubota, W. A. Kolasinski, N. F. Haddad, L. Rockett, M. Cerrila, and W. B. Hennley, “Cost-effective numerical simulation of SEU,” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1608-1612, 1988.

[265]

J. A. Zoutendyk, L. S. Smith, G. A. Soli, and R. Y. Lo, “Experimental evidence for a new single-event upset (SEU) model in a CMOS SRAM obtained from model verification,” IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1292-1299, 1987.

[266]

J. A. Zoutendyk, E. C. Secrest, and D. F. Berndt, “Investigation of single-event upset (SEU) in an advanced bipolar process,” IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1573-1577, 1988.

[267]

A. R. Knudson and A. B. Campbell, “Comparison of experimental charge collection waveforms with PISCES calculations,” IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1540-1545, 1991.

[268]

E. Worley, R. Williams, A. Waskiewicz, and J. Groninger, “Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs,” IEEE Trans. Nucl. Sci., vol. 37, no. 6, pp. 1855-1860, 1990. All references are unclassified

II-82

[269]

P. E. Dodd, M. R. Shaneyfelt, and F. W. Sexton, “Charge collection and SEU from angled ion strikes,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2256-2265, 1997.

[270]

E. M. Buturla, P. E. Cottrell, B. M. Grossman, K. A. Salsburg, M. B. Lawlor, and C. T. McMullen, “Threedimensional finite element simulation of semiconductor devices,” IEEE International Solid-State Circuits Conf. Digest of Tech. Papers, pp. 76-77, 1980.

[271]

E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, “Finite-element analysis of semiconductor devices: the FIELDAY program,” IBM J. Res. Develop., vol. 25, no. 4, pp. 218-231, 1981.

[272]

E. Takeda, K. Takeuchi, E. Yamasaki, T. Toyabe, K. Ohshima, and K. Itoh, “The scaling law of alphaparticle induced soft errors for VLSI’s,” IEDM Tech. Dig., pp. 542-545, 1986.

[273]

D. Hisamoto, T. Toyabe, and E. Takeda, “Alpha-particle-induced source-drain penetration (ALPEN) effects— A new soft error phenomenon,” Ext. Abs. Conf. Solid-State Dev. Mat., pp. 39-42, 1987.

[274]

J. H. Chern, J. T. Maeda, L. A. Arledge, Jr., and P. Yang, “SIERRA: a 3-D device simulator for reliability modeling,” IEEE Trans. Computer-Aided Design, vol. 8, no. 5, pp. 516-527, 1989.

[275]

J. P. Kreskovsky and H. L. Grubin, “Numerical simulation of charge collection in two- and threedimensional silicon diodes— a comparison,” Solid–State Electron., vol. 29, no. 5, pp. 505-518, 1986.

[276]

A. Yoshii, H. Kitazawa, M. Tomizawa, S. Horiguchi, and T. Sudo, “A three-dimensional analysis of semiconductor devices,” IEEE Trans. Electron Devices, vol. 9, no. 2, pp. 184-189, 1982.

[277]

T. Toyabe, H. Masuda, Y. Aoki, H. Shukuri, and T. Hagiwara, “Three-dimensional device simulator CADDETH with highly-convergent matrix solution algorithms,” IEEE Trans. Electron Devices, vol. 32, no. 10, pp. 2038-2043, 1985.

[278]

W. Fichtner, R. L. Johnston, and D. J. Rose, “Three-dimensional numerical modeling of small-size MOSFETs,” IEEE Trans. Electron Devices, vol. 28, no. 10, pp. 1215-1216, 1981.

[279]

M. R. Pinto, W. M. Coughran, Jr., C. S. Rafferty, R. K. Smith, and E. Sangiori, “Device simulation for silicon ULSI,” in Computational Electronics, edited by K. Hess, J. P. Leburton, and U. Ravaioli (Kluwer Academic Publishers, Boston, 1991), pp. 3-13.

[280]

N. Shigyo and R. Dang, “Analysis of an anomalous subthreshold current in a fully recessed oxide MOSFET using a three-dimensional device simulator,” IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 441-445, 1985.

[281]

Taurus Process/Device User’s Manual (Avant! Corporation, TCAD Business Unit, 1998).

[282]

Athena/Atlas User’s Manual (Silvaco International, 1997).

[283]

DESSIS User’s Manual, Release 4, Vol. 5 (ISE Integrated Systems Engineering AG, 1997).

[284]

P. E. Dodd, “Analyzing heavy-ion-induced charge collection in Si devices by three-dimensional simulation,” presented at the 13th Int. Conf. on the Application of Accelerators in Research and Industry, Denton, TX, 1994.

[285]

S. E. Kerns, “Transient-ionization and single-event phenomena,” in Ionizing Radiation Effects in MOS Devices and Circuits, edited by T. P. Ma and P. V. Dressendorfer (Wiley, New York, 1989), pp. 485-576.

[286]

L. W. Massengill, “SEU modeling and prediction techniques,” 1993 IEEE NSREC Short Course, Snowbird, UT.

[287]

R. J. McPartland, “Circuit simulations of alpha-particle-induced soft errors in MOS dynamic RAM’s,” IEEE J. Solid-State Circuits, vol. 16, no. 1, pp. 31-34, 1981.

[288]

R. L. Johnson, Jr., S. E. Diehl-Nagle, and J. R. Hauser, “Simulation approach for modeling single event upsets on advanced CMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 32, no. 6, pp. 4122-4127, 1985.

[289]

D. D. Tang and C. Chuang, “A circuit concept for reducing soft error in high-speed memory cells,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 201-203, 1988. All references are unclassified

II-83

[290]

K. Gulati, L. W. Massengill, and G. R. Agrawal, “Single event mirroring and DRAM sense amplifier designs for improved single–event–upset performance,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 20262034, 1994.

[291]

M. S. Mock, Numerical Analysis of Semiconductor Devices and Integrated Circuits, edited by B. T. Browne and J. J. H. Miller (Boole Press, Dublin, 1981).

[292]

J. G. Rollins and J. Choma, Jr., “Mixed-mode PISCES-SPICE coupled circuit and device solver,” IEEE. Trans. Computer-Aided Design, vol. 7, no. 8, pp. 862-867, 1988.

[293]

K. Mayaram, J. H. Chern, and P. Yang, “Algorithms for transient three-dimensional mixed-level circuit and device simulation,” IEEE Trans. Computer-Aided Design, vol. 12, no. 11, pp. 1726-1733, 1993.

[294]

K. Mayaram, P. Yang, and J. H. Chern, “Transient three-dimensional mixed-level circuit and device simulation: Algorithm and applications,” Proc. ICCAD-91, pp. 112-115, 1991.

[295]

Ph. Roche, J. M. Palau, K. Belhaddad, G. Bruguier, R. Ecoffet, and J. Gasiot, “SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2534-2543, 1998.

[296]

S. Satoh, R. Sudo, H. Tashiro, N. Higaki, and N. Nakayama, “CMOS-SRAM soft-error simulation system,” Proc. IEEE Int. Reliability Phys. Symp., pp. 339-343, 1994.

[297]

Y. Tosaka, S. Satoh, T. Itakura, K. Suzuki, T. Sugii, H. Ehara, and G. A. Woffinden, “Cosmic ray neutroninduced soft errors in sub-half micron CMOS circuits,” IEEE Electron Dev. Lett., vol. 18, no. 3, pp. 99-101, 1997.

[298]

Y. Tosaka, S. Satoh, K. Suzuki, T. Sugii, N. Nakayama, H. Ehara, G. A. Woffinden, and S. A. Wender, “Measurements and analysis of neutron-reaction-induced charges in a silicon surface region,” IEEE Trans. Nucl. Sci., vol. 44, no. 2, pp. 173-178, 1997.

[299]

Y. Tosaka, S. Satoh, T. Itakura, H. Ehara, T. Ueda, G. Woffinden, and S. A. Wender, “Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits,” IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1453-1458, 1998.

[300]

G. R. Srinivasan, P. C. Murley, and H. K. Tang, “Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation,” Proc. IEEE Int. Reliability Phys. Symp., pp. 12-16, 1994.

[301]

G. R. Srinivasan, H. K. Tang, and P. C. Murley, “Parameter-free, predictive modeling of single event upsets due to protons, neutrons, and pions in terrestrial cosmic rays,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2063-2070, 1994.

[302]

P. C. Murley and G. R. Srinivasan, “Soft-error Monte Carlo modeling program, SEMM,” IBM J. Res. Develop., vol. 40, no. 1, pp. 109-118, 1996.

[303]

H. H. K. Tang, “Nuclear physics of cosmic ray interaction with semiconductor materials: particle-induced soft errors from a physicist’s perspective,” IBM J. Res. Develop., vol. 40, no. 1, pp. 91-108, 1996.

[304]

G. R. Srinivasan, “Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview,” IBM J. Res. Develop., vol. 40, no. 1, pp. 77-89, 1996.

[305]

Soft Error Rate Prediction Service, IBM Microelectronics Division brochure, 1994.

[306]

D. G. Mavis and P. H. Eaton, “Temporally redundant latch for preventing single event disruptions in sequential integrated circuits,” Mission Research Corporation Tech. Rep. P8111.29, September 1998.

[307]

E. Normand, “Single-event effects in avionics,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 461-474, 1996.

[308]

J. F. Ziegler, H. W. Curtis, H. P. Muhlfeld, C. J. Montrose, B. Chin, M. Nicewicz, C. A. Russell, W. Y. Yang, L. B. Freeman, P. Hosier, L. E. LaFave, J. L. Walsh, J. M. Orro, G. J. Unger, J. M. Ross, T. J. O’Gorman, B. Messina, T. D. Sullivan, A. J. Sykes, H. Yourke, T. A. Enger, V. Tolat, T. S. Scott, A. H. Taber, R. J. Sussman, W. A. Klein, and C. W. Wahaus, “IBM experiments in soft fails in computer electronics (1978-1994), IBM J. Res. Develop., vol. 40, no. 1, pp. 3-18, 1996. All references are unclassified

II-84

[309]

J. F. Ziegler, “Terrestrial cosmic rays,” IBM J. Res. Develop., vol. 40, no. 1, pp. 19-39, 1996.

[310]

E. Normand and T. J. Baker, “Altitude and latitude variations in avionics SEU and atmospheric neutrons,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1484-1490, 1993.

[311]

J. T. Wallmark and S. M. Marcus, “Minimum size and maximum packing density of nonredundant semiconductor devices,” Proc. IRE, vol. 50, pp. 286-298, 1962.

[312]

See numerous papers in the 1978-1980 proceedings of the IEEE NSREC and the IEEE International Reliability Physics Symposium.

[313]

T. C. May, “Soft errors in VLSI: present and future,” IEEE Trans. Components, Hybrids, Manuf. Tech., vol. 2, no. 4, pp. 377-387, 1979.

[314]

Z. Hasnain and A. Ditali, “Building-in reliability: soft errors– a case study,” Proc. IEEE Int. Reliability Phys. Symp., pp. 276-280, 1992.

[315]

T. J. O’Gorman, “The effect of cosmic rays on the soft error rate of a DRAM at ground level,” IEEE Trans. Electron Devices, vol. 41, no. 4, pp. 553-557, 1994.

[316]

C. Lage, D. Burnett, T. McNelly, K. Baker, A. Bormann, D. Dreier, and V. Soorholtz, “Soft error rate and stored charge requirements in advanced high-density SRAMs,” IEDM Tech. Dig., pp. 821-824, 1993.

[317]

E. Normand, “Single event upset at ground level,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2742-2750, 1996.

[318]

P. D. Bradley and E. Normand, “Single event upsets in implantable cardioverter defibrillators,” IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2929-2940, 1998.

[319]

E. Normand, J. L. Wert, D. L. Oberg, P. P. Majewski, P. Voss, and S. A. Wender, “Neutron-induced single event burnout in high voltage electronics,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2358-2366, 1997.

[320]

Private communication, numerous US semiconductor and computer manufacturers.

[321]

M. Takada, “DRAM technology for giga-bit age,” Ext. Abs. Solid-State Dev. Mat. Conf., pp. 874-876, 1993.

[322]

A. H. Taber and E. Normand, “Investigation and characterization of SEU effects and hardening strategies in avionics,” DNA Technical Report DNA-TR-94-123, 1995.

[323]

Y. H. Koh. M. R. Oh, J. W. Lee, J. W. Yang, W. C. Lee, C. K. Park, J. B. Park, Y. C. Heo, K. M. Rho, B. C. Lee, M. J. Chung, M. Huh, H. S. Kim, K. S. Choi, W. C. Lee, J. K. Lee, K. H. Ahn, K. W. Park, J. Y. Yang, H. K. Kim, D. H. Lee, and I. S. Hwang, “1 gigabit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure,” IEDM Tech. Dig., pp. 579-582, 1997.

[324]

K. Mistry, G. Grula, J. Sleight, L. Bair, R. Stephany, R. Flatley, and P. Skerry, “A 2.0V, 0.35µm partiallydepleted SOI-CMOS technology,” IEDM Tech. Dig., pp. 583-586, 1997.

[325]

D. J. Schepis, F. Assaderaghi, D. S. Yee, W. Rausch, R. J. Bolam, A. C. Ajmera, E. Leobandung, S. B. Kulkarni, R. Flaker, D. Sadana, H. J. Hovel, T. Kebede, C. Schiller, S. Wu, L. F. Wagner, M. J. Saccamango, S. Ratanaphanyarat, J. B. Kuang, M. C. Hsieh, K. A. Tallman, R. M. Martino, D. Fitzpatrick, D. A. Badami, M. Hakey, S. F. Chu, B. Davari, and G. G. Shahidi, “A 0.25 µm CMOS SOI technology and its application to 4 Mb SRAM,” IEDM Tech. Dig., pp. 587-590, 1997.

[326]

R. Chau, R. Arghavani, M. Alavi, D. Douglas, J. Greason, R. Green, S. Tyagi, J. Xu, P. Packan, S. Yu, and C. Liang, “Scalability of partially depleted SOI technology for sub-0.25 µm logic applications,” IEDM Tech. Dig., pp. 591-594, 1997.

All references are unclassified

II-85

1999 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference Short Course

TOTAL DOSE EFFECTS: MODELING FOR PRESENT AND FUTURE Jean-Luc Leray CEA/DAM Ile-de-France

Approved for public release; diffusion is unlimited

1998 IEEE NSREC Short Course TOTAL DOSE EFFECTS: MODELING FOR PRESENT AND FUTURE Jean-Luc Leray CEA/DAM Ile-de-France B.P. 12, F-91680 Bruyères-Le-Châtel, France

1.

COURSE DESCRIPTION

2.

CONTEXT: TOTAL-DOSE ENVIRONMENT IN SPACE 2.1. 2.2. 2.3.

2.4. 2.5. 2.6. 3.

Recalling the order of magnitude of radiation in space The orbits and example of mission dose profiles The interactions: permanent effects of the cumulated dose 2.3.1. Interactions and track radii. Uniform or dispersed dose? 2.3.2. Equivalence between fluxes and dose rates Radiative environments and simulation of these environments Hardening vs. Shielding? Trade-offs between weight and cost Example at the component level: LEO satellites

ANALYTICAL MODELING OF TRAPPING EFFECTS IN MOS TRANSISTORS 3.1. 3.2. 3.3. 3.4. 3.5. 3.6.

3.7.

3.8. 3.9.

3.10. 3.11. 3.12.

Consequences for transistors and circuits The basic picture for hole and electron trapping Charge contained in the insulator and threshold voltage shift of MOS transistor Positive and negative trapped charge: present understanding First step: creation and separation of electron-hole pairs in SiO2 Second step: motion of the holes 3.6.1. Basic observations 3.6.2. Interpretation 3.6.3. Modeling of the early regime of motion and the self trapping of holes Third step: towards permanent trapping of charge 3.7.1. Modeling the trapping 3.7.2. Equations relative to carriers 3.7.3. Equations relative to trapped carriers 3.7.4. Equation relative to the electric field 3.7.5. Equations relative to the currents Solution for the steady-state case of irradiation: Mean free paths for holes and electrons. Limiting cases Case of a single type of trap 3.9.1. Solution for positive bias 3.9.2. Solution for negative bias Low dose and high dose regimes in the simplifying case of interface trapping Analytical modeling Practical applications 3.12.1. Electrical measurement techniques 3.12.2. Behavior in the low dose regime III-1

3.13.

3.14. 3.15.

4.

NUMERICAL MODELING OF TRAPPING 4.1. 4.2.

4.3. 4.4.

4.5. 5.

Annealing, reverse-annealing and rebound Modeling the trapping and thermal detrapping effects 5.2.1. Modeling PIE in terms of energy spectra: principles and equations 5.2.2. Results

TRAPPING AND LINKS WITH THE MANUFACTURING PROCESS 6.1. 6.2.

6.3.

6.4.

7.

Background Simplified Numerical 1D on laptop computer: the TRAPPOXR v.4 code and various applications 4.2.1. V-Model 4.2.2. J-Model 4.2.3. Trends in modeling 4.2.4. Method used in TRAPPOXR v.4 and code implementation 4.2.5. The effects of gate bias: the cases of trapping in volume and at interface Case of an unhardened power MOS transistor. The field collapse effect 4.4.1. Consequences in the case of an irradiation under positive gate bias 4.4.2. Consequences in the case of an irradiation under negative gate bias 4.4.3. Conclusions 4.4.4. Numerical illustrations using three different codes Gate bias switching

DETRAPPING AND TIME-EVOLVING EFFECTS 5.1. 5.2.

6.

3.12.3. Case of charge trapping at the SiO2/Si interface 3.12.4. Case of charge trapping in the bulk of the oxide 3.12.5. Case of a multilayer insulator 3.12.6. Behavior in the high dose regime Simple method to evaluate the hardness factor of a MOS process for the trapping of holes 3.13.1. Simplified formula 3.13.2. Number of traps Nt as a key parameter Extraction of trap parameters Case where two type of traps are present 3.15.1. Case of uniform distribution of traps 3.15.2. Case of interfacial distribution of traps

Defects Some views on response of thermal oxides modeling 6.2.1. Manufacturing process of the thermal oxide 6.2.2. Gate oxide thickness downscaling Empirical Process engineering curves for the thermal gate oxide and modeling 6.3.1. Correlations concerning oxidations and anneals 6.3.2. Furnace Anneals and Rapid Anneals (RTA) Some theories about the process engineering empirical curves 6.4.1. Interpretation by the flow of SiO2 6.4.2. Interpretation in term of exo-diffusion of oxygen

INTERFACE STATES 7.1.

Consequences of interface state build-up for ∆VTN and ∆VTP III-2

7.2. 7.3.

Consequence for mobility reduction in silicon Interface state build-up

8.

BIPOLAR TRANSISTORS

9.

LEAKAGE CURRENTS: VISIBLE AND HIDDEN TRANSISTORS 9.1.

9.2. 9.3. 9.4. 10.

Edge field oxides (E-FOX) modeling 9.1.1. Lateral thick oxides: LOCOS type 9.1.2. Example of consequences of leakage for circuits 9.1.3. Conceptual modeling of edge transistors and experiments 9.1.4. Numerical modeling of edge leakage transistors 9.1.5. Trends of supply voltage during irradiation 9.1.6. Other types of edge oxides Planar isolation oxides (P-FOX) The case of leakage in bipolar technologies Consequences of leakage currents for CMOS circuits and perspectives linked to progress of the integration

SOI TECHNOLOGIES 10.1. 10.2. 10.3. 10.4.

Principles of SOI technologies The three types of SOI technologies Parasitics in a thin-film SOI technology Modeling the trapped charge in SOI devices

11.

CONCLUSIONS: TRENDS, MODELING, AND NEW ISSUES

12.

ACKNOWLEDGMENTS

13.

APPENDIX 13.1. 13.2.

14.

Self-consistent codes used Parameters 13.2.1. Parameters used in chapter 4 13.2.2. Parameters used in chapter 10

REFERENCES

III-3

1. COURSE DESCRIPTION Knowing the dose only is insufficient to assess the actual impact of ionizing radiation on electronic components. Due to annealing, reverse-annealing effects, all affected by voltage bias, dose-rate and operation during mission profile is also of utmost importance. A lot of work has been done in the last 40 years, with the vast majority having been published in IEEE Transactions. A lot of models, data, perspectives have been compiled in NSREC Short Courses since 1980. For instance, one can refer to the 1998 issue of this series, especially “Basic Mechanisms for the New Millenium” by Paul V. Dressendorfer, which recalls much of the physics involved in radiation effects [Dres-98]. Consequently, we shall not address in detail all the work done by generations of experts these last 40 years, as thorough treatments of this rich and still mysterious subject have been done. The objective of this chapter is therefore only to give a review on the subject of total dose modeling with emphasis on analytical and numerical schemes as developed now. We shall also only introduce the debatable issues of interface states, bipolar transistors and prediction and specification in a time-dependent radiation environment. As leakage currents in MOS technologies are a major concern for the range of dose considered, we shall focus on modeling of the oxide trapped charge, especially in medium-to-thick oxides, and describe situations in field oxides of bulk CMOS and buried oxides in SOI. For that purpose, we shall follow a natural roadmap, starting from basics to go on with analytical equations and modeling, and finally use computer codes, lab-made or commercially available. 2. CONTEXT: TOTAL-DOSE ENVIRONMENT IN SPACE 2.1.

RECALLING THE ORDER OF MAGNITUDE OF RADIATION IN SPACE

Two types of particles can be encountered by space vehicles and interact inside components in spite of shields: -

A pervasive component that comes directly from outer space (Sun, our galaxy, foreign galaxies).

-

Another component that resides in magnetic fields of the Van Allen Belts and impacts the spacecraft orbiting in them or crossing them.

The components of these fluxes have been extensively studied and are recalled of fig. 1. The reader can refer for further description to recent Short Courses of this collection [Barth-97], [Dyer-98].

III-4

a) Trapped-electron

Figure 1.

b) Trapped-proton

Radiation environment and particle densities close to the Earth [Daly-88].

Figure 2 translates these fluxes into the actual dose a silicon device receives at a given location per second, from trapped electron and proton belts, being shielded by 2.1 millimeters of aluminum (CRRES experiment data). As for fig. 1, these data are recorded for a “quiet” situation, i.e. without enhancement due to Solar transient activiy.

Figure 2.

2.2.

In-orbit dose rate received behind a 2.1 mm Al shield [Kern-92].

THE ORBITS AND EXAMPLE OF MISSION DOSE PROFILES

Constellations of satellites devoted to the global consumer market, have been the major innovations of the last decade. These telecommunication constellations had been preceded by military networks and by Global Positioning Networks such as GPS in the United States and Glonass in the former USSR. As the push of the telecommunication market requires more complex features of satellites, the altitude of the orbits gets more into the radiation belts and the total dose or ionizing radiation absorbed increases. Table 1 and fig. 3 depict some examples. It can be seen that the next III-5

generation of systems will roughly need to endure 10 times more radiation dose than the present one. Status

perigee x apogee/inclin. External D ose

D ose / 1 mm A lu.

Manned LEO: Space Stations Space Station

project

450 x 450 km

51°

150 krad/year

1 krad/year

Little or Big Low Earth Orbit (<2000km): Constellations Iridium

operational

780 x 780 km

86°

1.7 M rad/year

9 krad/year

note: w ith overshielding = > 1 krad/year

Celestri

project

1400 x 1400

48°

17 M rad/year

63 krad/year

Teledesic

project

1400 x 1400

84.6°

18 M rad/year

51 krad/year

Skybridge

project

1457 x 1457

55°

28 M rad/year

73 krad/year

(abandoned)

note: w ith overshielding = > 7 krad/year

Ecco

project

2000 x 2000

0°

81 M rad/year

670 krad/year 50 krad/year

note: w ith overshielding = >

MEO (10000km)/GEO (36000km):GPS, Telecommunication Relays,etc

Table 1.

G eosynchronous any satellite

35790 x 35790 0°

1.1 G rad/year 1.1 M rad/year overshielding = > 1-2 krad/year

G PS-II

operational

22600 x 22600 55°

9.1 G rad/year

(or G LO N ASS

= end of life

19132 x 19132

overshielding = >

64.8° )

1.9 M rad/year 1-10 krad/year

Yearly radiation doses for various types of satellites (overshielding example is given for RadpakTM shield case [SEI]).

in

circular

orbits

DOSE in Krad(Si)

1 000 D o s e v s A lt itude 9 Y ears & 5 5 ° ( 10 m m A l )

100

10

1 100

1 000

10 000

100 000

C IRC U LA R O R B IT A L T IT U D E in km

Figure 3.

Indication of the dose received behind 10 mm Aluminum for 50 to 60° orbit as a function of altitude. Trend for present and new spacecrafts or constellations (Space Station, Celestri, Skybridge, GPS-II, etc) [Calv-99].

This increased regime needs enhanced strategies of procurement, modeling of radiation effects and radiation hardness assurance. 2.3.

THE INTERACTIONS: PERMANENT EFFECTS OF THE CUMULATED DOSE

III-6

2.3.1. INTERACTIONS AND TRACK RADII. UNIFORM OR DISPERSED DOSE? In matter, the interaction of photons, ions, protons or high-energy electrons present in the environment generates secondary electrons that are themselves very energetic with respect to the energies of the valence electrons or even of core electrons of atoms.

Figure 4.

Cascades of electrons resulting from the primary interaction.

Thus, secondary electrons can ionize atoms, generating electron-hole pairs or collective excitations of valence electrons (plasmon modes). Oscillations of plasmon modes can eventually generate electron hole pairs. As long as energies of the generated electrons and holes are greater than the minimal energy required for an electron-hole pair, they can in turn generate supplementary pairs. Consequently, one lone photon of high energy, or electron or proton or ion, can create thousand or million of electron-hole pairs. 2.3.2. EQUIVALENCE BETWEEN FLUXES AND DOSE RATES For uniformly deposited dose, a simple relation ties energy, fluence and absorbed ionizing dose derivatives: & = 1.6 10 −5 D

(1)

dE ρdx

Φ

with & D Φ dx dE ρ In

the derivative of the absorbed dose in rad(material).s-1 the particle flux in cm-2.s-1 the elementary abscissa in cm, projected along the particle track (flux vector) the ionizing energy in MeV transferred per dx mass density of the material in g.cm-3

dE , the Linear Energy Transfer (LET) in MeV.cm2.mg-1 can be easily recognized. ρdx

From the tables of LET versus particles and energies, the following set of curves can be obtained III-7

(fig. 5). For practical use, one has to be careful to observe conditions of validity, i.e. sufficient number of particles and sufficiently far from interfaces between materials so that secondary electrons clouds overlap and be considered as homogeneous. Integrating over time, it gives also the relation between dose and fluence.

Figure 5.

Relation between dose and fluence for homogeneous dose deposition (after [VanL-75], completed).

2.4. RADIATIVE ENVIRONMENTS AND SIMULATION OF THESE ENVIRONMENTS Photon interactions are not a primary concern for satellites in the natural environment. However, photon interactions are important in hardness assurance testing of devices devoted to space equipment, since most laboratories use photon sources (low energy X-rays or high energy gamma rays) to simulate total-dose effects for space applications [Holm-93], [Adam-91]. This is well suited for simulation of military environments and the nuclear power industry [Shar-94], [Coen-95] where gamma photons are encountered [Glas-77], [Boud-93], which both result from nuclear energy. But the concern exists for the reproduction of space ionizing radiation, and for the recent concern of high energy physics equipment [Stev-92], where the environments deal mostly with charged particles whereas tests are made with low energy X-rays or high energy gamma rays sources (this issue of great concern has been treated at length in other references, notably: NSREC Short Courses and [Brow-90], [Flee-95], [1019], [1892], [22900], [Wino-94]). 2.5. HARDENING VS. SHIELDING? TRADE-OFFS BETWEEN WEIGHT AND COST The figure 6 gives the range (in aluminum) of typical particles encountered in the field of radiation hardening. It can be seen that, for typical thickness compatible with reasonable shield III-8

weight (1 to 5 millimeters), most of radiation penetrates, if energy exceeds cutoff of photons above 20 keV, electrons above 1 MeV, and protons above 10 MeV. Hopefully, the disposition of the equipments in satellite provide natural shielding, but nevertheless total dose cannot be avoided, especially for those satellite orbiting deep into van Allen Belts. Extra-weight must be more and more avoided, as the goal for constellation is a drastic gain in launch cost. On the other hand, the use of components from the global commercial market rises questions about hardness assurance methods. This is why these new requirements force to pay more attention to prediction of in-orbit behavior of components, especially so as to take profit of their natural annealing capabilities. To get grounds to these efforts, a method is to go back to basics and step-by-step provide models capable of accurate numerical description of reality based ground-tests, being extrapolated to in-orbit mission. Range in aluminum (mm)

Energy (MeV) Figure 6.

2.6.

Orders of magnitude of particle range in matter [Adams-91].

EXAMPLE AT THE COMPONENT LEVEL: LEO SATELLITES

Table 2 illustrates the range of doses in a typical LEO orbit (800 to 900 km). It shows that the required hardness of a given part depends on the position inside the spacecraft. This results in a very broad spectrum from 1 to 16 kilorad(Si)/year. High-level functions are protected by positioning the component deep inside the spacecraft. In Constellation satellites orbiting higher, the dose can be 10 times as much.

III-9

Category Diodes

Transistors

Linear Integrated Circuits Digital Integrated Circuits

Function Ultra High Frequency Signal Zener UHF Bipolar Power MOS Amplifiers Regulators Bipolar TTL-LS CMOS 4000B HCMOS

Microprocessors Memories Table 2.

Dose (krad(Si)) per Year 12 8 4 16 5 1 3 4 8 4 1.5 1 1

Example of a LEO Satellite [CTTS].

3. ANALYTICAL MODELING OF TRAPPING EFFECTS IN MOS TRANSISTORS The ionizing dose affects MOS technologies by mainly two different phenomena that lead to the presence of trapped charge. This results in an induced electrical field, which is added to the applied field existing in the functioning component and disturbs this field. As an example, one can take the simplest case of signal (low-power) MOS transistor 2N4351 (Ntype) and 3N164 (P-type) irradiated all pins shorted (fig. 7).

Figure 7.

Examples of variations of the threshold voltage for small-signal discrete N and P-MOS transistors (irradiated with Co-60 gamma rays under VGS=VDS=VBS =0 V).

III-10

In this figure are summarized certain typical features of total dose effects on MOS devices: -

linear dependence at low dose

-

sublinear regime at intermediate dose

-

saturation or very slow dependence at high dose

-

variation with manufacturing lots

-

difference between N and P type transistors

The basic frame of understanding is that “something” is building up under the influence of dose. This “something” may takes several forms according to the type of the device, the time scale at which it is considered and the way the device has been manufactured, and therefore a comprehensive modeling is required to master all the aspects. This course will only introduce certain aspects, some others being beyond the scope, or some question being too much a matter of research or debate to be addressed in a course. The similar beginnings at low dose is attributed to a common phenomenon to N and P-type, whereas the difference at larger dose is attributed to another different phenomenon which can produce similar effects in N and P, but with sign opposed. More specifically, the variation of threshold voltage is divided into two components named as follows: (2)

∆VtN = ∆VotN + ∆VitN

Figure 8.

and

∆VtP = ∆VotP − ∆VitP

Interpretation of threshold voltage shifts as the sum of two components.

Figure 8 displays the typical negative threshold voltage variation for PMOS, and the firstly negative then positive variation for NMOS. This last phenomenon is due to the fact that ∆VOT saturates, while ∆VIT presents much weaker (or no) saturation. The position from the point of III-11

turn-around according to laws and parameters, as well as the thickness of the oxide and the electric field (bias) has to be analyzed. In the following, we first address the common component to the two types of transistors. 3.1.

CONSEQUENCES FOR TRANSISTORS AND CIRCUITS

For transistors of N type, consequences of negative threshold voltage values, or positive but close to zero (<0.5 V), are an increase of the NMOS leakage current. At higher levels of irradiation, there is the loss of functionality of the circuit which contains the transistor. At the level of integrated circuit, these effects provoke loss of performance, increase of the power consumption, then circuit failure. This increase of leakage of various kinds that happens equally in other types of technology as CMOS, leads notably to increases of power consumption, contributes to drops of the bipolar transistor gain, and increases of the noise and the offsets of linear circuits. 3.2.

THE BASIC PICTURE FOR HOLE AND ELECTRON TRAPPING

Although the sketches of mechanisms that occur from the initial interaction until the “permanent trapping” are numerous, complex and not fully understood up to now, it can be crudely described in a few words as follows: if a transistor is exposed to high energy ionizing irradiation, electronhole pairs are created uniformly throughout the oxide. Immediately after their generation, electrons drift rapidly out of the oxide toward the negative electrode (within picoseconds) and holes drift toward the other electrode depending on the electric field direction (fig. 9). However, even before electrons leave the oxide, some fraction will recombine with holes. The fraction of holes that survives initial recombination is then available for either trapping or escaping toward electrodes.

S i-p E

electrons flux

X-Rays

electron traps

f

Rp

S iO2

Rn hole traps

R : Recombination : Charged T r aps : Neutral Trap

holes flux

Gate (V>0) Electric Field

Figure 9.

Illustration of charge transport and trapping in the MOS structure for positive gate bias [Herv-93].

III-12

3.3. CHARGE CONTAINED IN THE INSULATOR AND THRESHOLD VOLTAGE SHIFT OF MOS TRANSISTOR For a standard thermal oxide, the drift of the threshold voltage is related to the density of charge present in the insulator by:

1 t ox x ρ( x ) dx C ox ∫0 t ox

(3)

∆Vt = −

with

0 and tox ρ( x ) = q p( x) − n ( x) C ox =

ε ox t ox

the abscissa of gate and silicon interface, respectively the net volume charge (charge density) present in the oxide the gate oxide capacitance per unit area

The net trapped charge density resulting from the irradiation can have many causes: (i) In volume - free charge just after their creation - self-trapped charge again capable of movement by processes such hopping from trapping site to other trapping site [Mott-77]. (ii) In volume or in interface boundary - charge deeply trapped on defects, or more generally modification of the state of defect charge, in volume or in interface. (iii) At the interface with silicon strictly speaking - interface states. Interface states are, in principle, sites that are able to exchange charge with the silicon in indefinitely reversible manner, in thermodynamic equilibrium with the electronic population of the surface of the silicon. This must be done in a finite time (generally in the order of a microsecond for so-called “rapid states” that are usually the most common). These sites are therefore located practically in the “interfacial layer” and, in the sense of extended wave functions of this interface, they belong both to the silicon and to the oxide. It is important to note that interface states are not charged by themselves, but “porters” (sites) of charge (Bardeen states [Scho-39]). It is therefore natural to think that lattice defects, notably those caused at the interface by secondary effects of irradiation, are the cause of such electrically-active sites (e.g. Pb centers) (c.f. also mechanisms of Revesz-Griscom, reminded hereafter). But one can also note that some states cannot be defects in the crystalline sense of the term, but quantum levels caused by the passage of a system to an other (states of Tamm [Tamm32]). Some authors have imagined that charges trapped close to the interface could create allowed levels in the forbidden band-gap of the interfacial silicon by simple electrostatic influence. III-13

The standard classification is by convention that resulting from the “Deal Commission” [Deal80], approved by the Electrochemical Society and the IEEE (fig. 10).

Figure 10. Classification of charges [Deal-80].

Since then, finer studies have shown that reality is not as clear. It seems likely that there exist sites in the volume close to the interface that exchange charge with the surface of the silicon [Fleet-92], in a reversible manner as for states, but much more slowly (these slow states are called “border traps” or “switching states”). There also exist time-evolving phenomena that are identified by the (irreversible) neutralization of charge in the volume close to the interface. In what follows, we develop simple statements without describing the “border traps” concepts. Restrained to the charges that do not exchange reversibly with silicon, the global formula for threshold voltage shift here becomes: (4)

∆Vot = −

q ε ox

∫

t ox

0

x . [p t ( x ) − n t ( x ) + p( x ) − n ( x )] dx

where Vot is the oxide-trapped charge, and nt and pt are the oxide-trapped electron and hole densities of charge (in units charge.cm-3). The exact trap profile is most of the time unknown. It is therefore convenient to define an integral of this density rather than the profile itself. One can define ∆Qe and ∆Qh (more simply Qe and Qh when no ambiguity occurs), as: (5)

t Q e = ∫ ox x . [n ( x ) + n t ( x )] dx

(6)

t Q h = ∫ ox x . [p( x ) + p t ( x )] dx

0

0

To more easily allow reasoning on trapped charge profile, two useful additional quantities can be III-14

defined to represent the charge distribution by its first moment, i.e. the location of charge centroids in the oxide:

xe =

(7)

xh =

(8)

∫

t ox

0

x . [n ( x ) + n t ( x )] dx Q tot

∫

t ox

0

x . [p( x ) + p t ( x )] dx Q tot

where t Q tot = ∫ ox

(9)

0

[p t ( x) − n t ( x ) + p(x ) − n (x )] dx

is the total charge present (except the interface and border traps), and: (10)

t Q ot = ∫ ox x . [p t ( x ) − n t ( x ) + p( x ) − n ( x )] dx 0

is the projected total charge (note that all the quantities Q are surface densities of charges expressed in unit “number of charges per unit area”). Therefore, one can write a simple expression of the voltage shift, each term with a different signification:

(11)

∆Vot = −

Q ot (Q − Q e ) t =− h = − ox C ox C ox ε ox

 xh xe  −   Q tot  t ox t ox 

The free carrier density, as will be computed numerically in next sections, is insignificant in long-lasting natural irradiations (n and p are between 100 and 106 carriers.cm-3 for dose rates ranging between 10-3 and 103 rad.s-1). It is of course not the case for trapped charges as they accumulate on trapped sites: densities up to 1018 cm-3 can be reached. In this course, we will develop as possible the models that link: -

The ∆Vot threshold voltage shift and the trapped charge Qe and Qh, projected at the silicon interface.

-

The trapped charge Qe and Qh and the charge density profile nt and pt.

-

The charge profile nt and pt and the density of traps Ntn and Ntp.

-

The density of traps Ntn and Ntp and the material and process characteristics.

3.4. POSITIVE AND NEGATIVE TRAPPED CHARGE: PRESENT UNDERSTANDING III-15

The positive and negative charges trapped in the oxide therefore consist of the fraction of the holes and electrons that has not been lost via recombination, and eventually trapped. In the first decade of radiation effects, it was believed that trapped holes only exist, as the trapped charge always revealed as positive. However, evidences of negative charge appeared in metal-implanted oxides [e.g., Wang-75]. Later, it was recognized that trapped charge could be evidenced, even before irradiation, in pure thermal oxides [Shan-83] by combination of Thermally Stimulated Current technique (TSC) and Capacitance-Voltage measurement (C-V). However, the amount of trapped electrons is generally lower as compared to the quantity of trapped holes, which explains the general observation of a net positive trapped charge.

Table 3.

Type of oxide

Thickness

Range of dose

Thermal hard (ATT) Thermal hard (wet) Thermal hard (wet) Thermal hard Thermal hard (wet) Thermal hard (dry) Thermal hard Thermal soft Thermal soft SIMOX (SOI oxide)

18 nm 23 nm 47 nm 45 nm 100 nm 104 nm 98 nm 350 nm 348 nm 380 nm

5 Mrad 2 Mrad 1 Mrad 0.1-5 Mrad 0.5 Mrad 0.25 Mrad Idem 6 krad 20 krad 1 Mrad

Range of the electric field +1 to 2 MV/cm +1 to 2 MV/cm +1 to 2 MV/cm + 1 MV/cm +1 to 2 MV/cm +1 to 2 MV/cm + 2 MV/cm + 1 MV/cm +1 to 2 MV/cm -0.75 MV/cm

Qe/Qh and method used 0.48 TSC 0.083 TSC 0.47 TSC 0.55 TSC 0.14 TSC 0.43 TSC 0.46 TSC 0.15 TSC 0.19 TSC 1.3 (∆Vot bi-ex. fit)

Ratio of trapped electrons Qe to trapped holes Qh as measured under various circumstances (TSC from [Flee-92], bi-exponential fit (sect. 3.15.2 for SIMOX from [Lera-88, Pail95c]).

As recalled in table 3, the ratio of trapped electrons to trapped holes ranges from some percent to one half [Fleet-92], table 2, adapted). However, it is likely that a coherent modeling should require the two components. These data were interpreted in terms of wet and dry process, as in fig. 11.

Figure 11. Trapped electrons/trapped holes ratio for various processes [Flee-92].

III-16

In some specific cases, such as oxides used as substrate insulator for Silicon-On-Insulator under negative bias during irradiation, this ratio can be superior to 1, meaning that the net charge is negative in this case [Lera-88]. However, we shall consider as a first approach valid a first sight that the net charge is globally positive, as it has been considered for 30 years from the late 50’s In table 4, electron and hole densities of traps are measured instead of trapped charges (according to a method described in [Pail-95a] and [Pail-99] and summarized tn section 3.14). As will be seen later, the two items generally differ because a quantity depicting capacity of traps to be filled (NTN and NTP) is not generally the same as another measuring the amount of traps filled (Qe or Qh). Type of oxide

Thickness

Range of dose

SIMOX

380 nm

1 Mrad

SIMOX

80 nm

1 Mrad

UNIBONDTM

400 nm

1 Mrad

Thermal wet 400 nm annealed 1320°C

1 Mrad

Table 4.

Range of the electric field + and – 1 MV/cm + and – 1 MV/cm + and – 1 MV/cm + and – 1 MV/cm

NTH/NTP and method used 0.2 to 0.8 Vt-Vg 1 Vt-Vg 0.06 Vt-Vg 0.75 Vt-Vg

Reference [Pail-93] [Pail-95a] [Pail-95a] [Pail-93]

Ratio of electrons trap NTN to hole traps NTP densities as measured under various circumstances.

It can be seen that holes, although generally the most numerous, never come alone. In this course, this will be the guideline for further understanding. 3.5. FIRST STEP: CREATION AND SEPARATION OF ELECTRON-HOLE PAIRS IN SIO2 Globally, electron and holes are created in equal quantities at a rate: (12)

R0 =

∂n ∂p = = g 0 D' ∂t ∂t

g0 =

ρ = 7.8 1012 w

with: (13)

cm −3 . rad(SiO 2 ) −1

and ρ=2.27 g.cm-3. w=18 eV is the average energy required to generate one electron and one hole in SiO2 via high-energy interactions (an experimental value). Note that, the experimental uncertainty being of the order of 1 eV, some authors use g0=8.2 1012 coming from w=17 eV. However, SiO2 seems to be an exception as compared to Si, GaAs, C, etc., because a certain amount of electron and holes recombine, and this recombination depends essentially on the electric field applied. This “mutual recombination” of the generated carriers is the first part of a series of processes, well separated in time, whereas charge trapping is the last picture. In this series of successive interactions and physics that takes place from the very early moment of energy deposition, let us come back to this early events when the tracks take form. III-17

Figure 13. Fraction of unrecombined pairs versus the applied electric field for various incident radiations [McGa-80], [Oldh-83].

Figure 12. Separation of electron and holes.

According to the particles that interact with the oxide, the density of ionization is more or less important and two borderline cases are considered: -

The recombination of one particle of the pair undertaken with the parent particle. It is the case for electrons or incident photons that give a weak density of ionization.

-

The recombination undertaken randomly with a not-correlated particle in the ionized column. It is the case for ionization due to heavy particles.

The fraction of pairs that overcome this initial recombination and separate depends therefore on energy and the type of the incident particle and also on the electrical field present in the insulator that favors this separation. This fraction has been characterized by several independent workers working on scaled technologies since the mid 70’s: [Ausm75] initiated with 105 nm oxide and 4 keV electrons, [Srou-77b] compared the yield at 77K and 300K, [Hugh-75] for thermal SiO2 and suprasil glass in pulsed irradiation mode, [Boes-76] with 13 MeV electrons at 80K, [Peas-85] studied thick oxide under very low fields used in bipolar emitter-base spacers. A representation can be found in data recalled on fig. 12. Brown and Dozier made thorough studies of dependence versus the energy of photons and the structure of the ionizing tracks ([Dozi-81], [Brow-81], [Oldh-81/83/85]). [Oldh-82, [Oldh-84] and [Ausm-86] presented a refined analytical or numerical model taking into account the track density. A very simple model helps to picture the reasoning [Brow-81]. First, it is assumed that the cloud of holes and the cloud of electrons are swept apart in time tr by an applied field. Second, it is assumed that while the electron and the hole clouds overlap, electron-hole recombination takes place following bimolecular kinetics, i.e. (14)

dR = −χ R 2 dt

where χ is a recombination coefficient and R is the electron (and the hole) density at time III-18

t. This equation can be integrated simply: (15)

1 1 = + χ tr Rf Ri

with t r = d µ E is the time needed for columns separation, and µ the (ambipolar) mobility. This leads to the simplest formula for the non-recombination or yield function: (16)

Y(E)= R f / R i =

E / Ec 1 + E / Ec

with Ec a critical field defined by µ E c = χ . This simple calculation of “columnar” recombination is not always adequate because it supposes sufficiently dense tracks ([Oldh-84] showed it is valid for 107 electrons and holes generated per cm of track, i.e. for protons below 3 MeV, and electrons below 3 keV). Otherwise, a better model would be the “geminate” recombination, based on similar physics but where carriers are more dilute so that they recombine as isolated pairs [Ausm86]. It leads anyway to similar conclusions. On fig. 13, the yield dependence is presented versus energy of particles, that is to say, track density. One notes the low yield for heavy particles and the influence of the electrical field Eox. For Co-60 and 10 keV X-rays, several updates were made in the late 80’s and in the 90’s, and precise comparison have been made ([Bene-86], [Shan-91]). When one comes to analytical approximations, sigmoid curves can be suggested, such as, for X and γ photons:

(17)

 E  Y(E) = 1 + c  E 

−m

where m and Ec are coefficient that depends on the type of radiation. Table 5 gives examples of fitting parameters. Photons From [Flament95] From [Oldh-81/83/85] Table 5.

Co-60 γ rays 1.17-1.33 MeV Ec (MV/cm)=0.65 m = 0.9 0.5 0.7

X rays 10 keV 1.35 0.9 1.35 0.9

Coefficients for the empirical function of non-recombination Y(E).

More specifically to take into account a possible residue Y0 at zero field and temperatures above 150 K (as evoked by [Ausm-86]):

III-19

(18)

(19)

Y(E) = Y0 +

Y(E) =

1 − Y0  E  1 +   Ec 

( )

E + E0 m E + Ec

m

or (other approximate expression):

and E0 = Y0 . EC

with Y0 is about 0.05 at room temperature [Farm-73], [Lera-89a]. 3.6.

SECOND STEP: MOTION OF THE HOLES

3.6.1. BASIC OBSERVATIONS From the point of view of electron and hole processes, one can consider that, whatever the duration of irradiations, it can be decomposed into an infinite series of small quasiinstantaneous elementary irradiations. This method of the “pulsed response” allows a more didactic statement of the successive processes that follow the creation of electron-hole pairs (fig. 14). The use of «flash X» or linac irradiation machines provides conditions to measure the real impulse response of MOS and to suitably model the successive phenomena [Hugh-75a, Hugh-75b, Curt-77, Lera-85, Lera-89a, Peyr-91].

BEFORE

+V

DURING IRRADIATION

DURING AND AFTER IRRADIATION

+V

+V

gate SiO2

+- +- + - +- +- + - +-+ - + - + - + - + +-+-+ - + - + - + -

+ + + + + + + +

Si IONIZATION AND RECOMBINATION

DRIFT, DIFFUSION AND TRAPPING

Figure 14. Generation and the trapping of charge in the insulator of MOS structures.

Contrarily to semiconductors where the free carrier mobilities of electrons and holes have similar magnitudes, they differ here by several orders of magnitude. For electrons, III-20

mobility µ e of about 10 cm2.V-1.s-1 has been reported [Hugh-75] from photocurrent measurements. On the contrary, the positive charge due to holes is slowly evacuated, allowing one to define an effective mobility derived from the time-of-flight of the moving holes [Boes-75, Curt-77]: (20)

µ peff =

t ox E . t1/ 2

with t1/2 the time needed for decreasing the charge to one-half its original value. This behavior has been first attributed to shallow traps situated to the vicinity of the valence band. Their apparent mobility µ peff varies therefore strongly with the temperature [Srou-76], [Srou-77b], [Boes-75], [Curt-77], [Lera-85]: (21)

µ peff = µ p0 exp(-Ei/kT)

In [Hugh-75b], an example of parameter set is given: µ peff = 20cm2/V.s exp(-0.6eV/kT) for thick thermal SiO2 film (862 nm).

III-21

3.6.2. INTERPRETATION In fact, there is a broad distribution of activation energies, and it has been shown that the shallow traps were intrinsic to SiO2 in the sense that the hole becomes self-trapped due to its own electrostatic potential on oxygen atoms constituting the network (polaron effect, [Mott-77, McLe-77]). This is probably why this behavior is so universal among the various kinds of oxides tried, although a slight dependency of activation energies has been found to depend on process [Lera-85], with high-temperature annealed oxides having smaller t1/2, higher hole mobility and lower activation energies. This might be related to the hopping mechanism between sites, favored by denser oxides [Lera-89a]. The figure 15 summarizes the main transport and trapping mechanisms in SiO2 by showing the importance of the spatial and energy distribution of traps.

Free hole

self-trapping

hopping transport

Figure 15. Simplified illustration of transport and trapping mechanisms of holes in SiO2 [McLe-77].

A global hole movement occurs as determined by this trap-controlled mobility under the electrical field toward electrodes. This movement has been measured after irradiations delivered in pulsed mode with X-ray or electron flash machines, and modeled by describing the transport equations in the presence of traps distributed in volume and in energy [Boes-74], [Boes-77], [Lera-89a], [Peyr-91]. For time scales of the order of irradiation experiments, [Wino-94] suggests to use an activation energy of about 0.4 eV.

III-22

It must be noted that such polaron behavior has been investigated for electrons, but no evidence has been found [Othm-80]. R.C. Hughes made thorough investigations on SiO2 photocurrents, and mesured the dependence of electron drift velocity versus electric field (fig. 16). It is similar with other type of semiconductors, except that the critical field is higher (200 kV/cm). This is attributed to the high value of the optical phonons in this material. Ferry calculated the theoretical value of the saturation velocity (2 107 cm s-1) [Ferr], which is in good agreement with the experimental value of Hughes [Hugh-73, Hugh-78].

Figure 16. Drift velocity of electrons in SiO2 versus electric field for three thicknesses of Suprasil-II glass [Hugh-75]. The slope is the electron mobility of 21± ±2 cm2 V-1 s-1.

3.6.3. MODELING OF THE EARLY REGIME OF MOTION AND THE SELF TRAPPING OF HOLES For “free” holes (called also “dry holes” as opposed to “self-trapped” holes or “polaron”), Hughes introduced and indirectly measured a lifetime τp0 before it becomes self trapped. For this to achieve, he measures the product µ p0τp0 ≈ 1.4 10-12 cm2 V-1 by integrating the current released in thermal silicon dioxide irradiated by 3 nanosecond pulses [Hugh-78]. This value is also found in other type of experiments [Curt-75, Boes-76, Srou-76, Srou-77a]. Hughes derived a value for τp0 by theoretical estimation of µ p0, based on the value of the mass attributed to the free holes. With µ p0=1 cm2 V-1 s-1, it gives τp0 ≈ 1.4 10-12 s which is a value compatible with the self-trapping phenomenology [Hugh-98]. So, if we note p0 and jp0 the “dry” hole density and current:

(22)

∂p 0 ∂jp 0 & Y(E) − p 0 + = go D ∂t ∂x τ p0

In steady state, the first term can be neglected (it requires that the dose rate does not vary much in time comparable with τp0, which might be questionable in case of heavy ion strike, for instance). If we neglect diffusion before the drift term, the current equation becomes simply jp0 = p0 µ p0 E. The differential equation can be solved in x for 1D problems: (23)

& Y(E) τp0 (1 − exp − x µ p 0 τ p 0 E ) p0 = go D

Provided that E < tox/µ p0τp0 = 106 V cm-1 for tox=10 nm, the “dry” hole density is nearly uniform and we can have an order of magnitude of the steady-state free hole density: p0 ≈ 7 carriers cm-3 III-23

per rad/s, which could seem very low. However, these carriers must not be neglected. They are not lost as they appear as inputs in the following equations related to the subsequent step where the deep trapping occurs. 3.7.

THIRD STEP: TOWARDS PERMANENT TRAPPING OF CHARGE

In the vicinity of the semiconductor interface, there exists a disturbed region that is the transition between the crystalline silicon and the amorphous silicon dioxide. Deep hole traps, initially neutral, become converted into positive fixed charge by trapping holes (and eventually relaxing into another configuration state which stabilizes the trapping). The probability of capture for a hole is a function of the density of empty traps, and therefore scales with dose initially, before becoming sublinear and saturating at higher doses. 3.7.1.

MODELING THE TRAPPING

Before modeling the detrapping, we shall follow the method developed in [Pail-99], which is a complete treatment of models having been proposed these 20 last years by [McGa-80] for low dose regime, and extended to saturation regime in [Lera-89a]. All these models are based on trapping of hole and electron participating to the flux on a given trap profile, according to the proposition of [Kran-87]. Here, the fluxes are defined by drift-diffusion equations. Note that an alternative formulation exists, where the “flux” is defined as the product of the thermal velocity by the carrier density. These two alternatives categorized as the “J-Model” and the “V-Model” will be compared in the section 4.2. We first describe the J-Model which is probably easier to picture out, and which has been much more in use during the last decade. 3.7.2.

EQUATIONS RELATIVE TO CARRIERS

As mentioned above, during irradiation two charge trapping mechanisms can take place in the oxide for each type of carrier. The continuity equations (for holes in the valence band and for electrons in the conduction band of silica) can thus be written by taking into account the generation term, the flux gradient and both trapping phenomena. Using a one-dimensional formulation, and noting simply p the hole density at interest for this deep trapping model, we get: (24)

∂n ∂jn (x, t ) & Y(E) − σnt(E)jn(x,t)[NTN(x)−nt(x,t)] −σnr(E)jn(x,t)pt(x,t) + = go D ∂t ∂x

(25)

∂p ∂jp (x, t ) p 0 + = − σpt(E)jp(x,t)[NTP(x)−pt(x,t)] −σpr(E)jp(x,t)nt(x,t) ∂t ∂x τ p0

where: n(x,t) and p(x,t) are respectively the density of free electrons in the conduction band and that of free holes in the valence band, go is the density of electron-hole pairs generated per rad(SiO2), represents the dose rate [rad(SiO2).s-1], Y(E) is the probability of escaping initial recombination (also called the yield function), nt(x,t) and pt(x,t) are respectively the density of trapped electrons and trapped holes, t designates the time evolved since the beginning of irradiation, and q represents the charge of the electron. Note that current densities are defined III-24

here as currents of particles (in cm-2.s-1) and not currents of charges (in A.cm-2). By replacing the value obtained for p0 in the steady state, and provided that E < tox/µ p0τp0 = 106 V cm-1 for tox=10 nm, we have:

(26)

&τ g 0 Y(E) D p0 h0 (1 − exp − x µ p0 τ p0 E )= g 0 Y(E) D& (1 − exp − x µ p0 τ p0 E ) = τh0 τh0

So, under these assumptions only, and for x > µ p0τp0 E, the equation of hole trapping simplifies and becomes apparently similar to the equation for electrons:

(27)

∂p ∂jp (x, t ) & Y(E) − σpt(E)jp(x,t)[NTP(x)−pt(x,t)] −σpr(E)jp(x,t)nt(x,t) + = go D ∂t ∂x

The only difference lies in the equation for currents, in which the mobility (and the diffusivity) is defined by a specific law, strongly depending on temperature as recalled before. 3.7.3.

EQUATIONS RELATIVE TO TRAPPED CARRIERS

To be able to derive equations for trapped carriers, we must first assume that there only exists one trapping level for holes and one level for electrons in the bandgap of the insulator, and that these traps are deep enough so that we can neglect carrier detrapping during irradiation, at the temperature of the experiment, which is certainly an oversimplification. The continuity equations for trapped electrons and trapped holes can then be written:

(28)

∂n t = σnt(E)jn(x,t)[NTN(x)−nt(x,t)] − σpr(E)jp(x,t)nt(x,t) ∂t

(29)

∂p t = σpt(E)jp(x,t)[NTP(x)−pt(x,t)] − σnr(E)jn(x,t)pt(x,t) ∂t

The first term of each equation corresponds to the trapping of free carriers. This mechanism depends both on the number of “candidates” (brought by the current), and on the number of available trapping sites (e.g. NTN - nt). The second term accounts for the recombination of already trapped charges with free carriers of opposite sign. The trapping of a free charge on a trapped carrier of opposite sign does not a priori depend on the direction of its displacement. Therefore, only the absolute values of each current are taken into account. In the presence of electric field (coming from the space-charge + from the applied voltage), one expects a cross-section variation in Eox-n [Ning-76], [Kran-87], [Esco-95a]. 3.7.4.

EQUATION RELATIVE TO THE ELECTRIC FIELD

In order to simplify the equations, the internal electric field in the oxide will be written E, although it should more correctly be written E(x,t) since it depends both on the space coordinate and on time. Indeed, E does evolve with the build-up of the trapped charge, both in time and space. The evolution of the field is obtained from the Poisson equation, which for this oneIII-25

dimensional model yields: (30)

∂E q [pt(x,t)−nt(x,t)+ p(x,t)−n(x,t)]] = ∂x ε ox

where εox represents the dielectric permittivity of silica. This equation links the local concentrations of trapped carriers to the local field value E(x,t). Free carriers are not taken into account because during irradiation, their density rapidly becoming negligible compared with the trapped charge density. 3.7.5. EQUATIONS RELATIVE TO THE CURRENTS The expressions of the electron and hole currents must now be defined. Each current density of particles can be written in its very general form, as the sum of a drift term and of a diffusion term. It follows: (31)

jn(x,t) = − n(x,t) µn E(x,t) − Dn

(32)

jp(x,t) = p(x,t) µp E(x,t) − Dp

∂n ( x , t ) ∂x

∂p( x , t ) ∂x

where Dn and Dp are the diffusion coefficients for electrons and for holes, which verify the Einstein relationship recalled below: (33)

Dn =

kT kT µ n and Dp = µ peff q q

with µ peff = µ p0 exp(-Ei/kT)

(cf. Eqn. 21).

The expressions of currents jn and jp can be inserted into the preceding equations. The four continuity equations for free carriers and trapped charges, coupled with the equation of the internal electric field, constitute the system that allows us to calculate the profiles of the charge trapped in the oxide. The voltage shifts associated with charge trapping in the oxide can then be deduced by integration. Without any further simplifying hypothesis, this system of five coupled equations can only be solved numerically. In the following, we shall make simplifying assumptions to derive usable analytical expressions. 3.8. SOLUTION FOR THE STEADY-STATE CASE OF IRRADIATION: MEAN FREE PATHS FOR HOLES AND ELECTRONS. LIMITING CASES Instead of trying to solve numerically this system of five coupled equations, we can attempt to find some simple analytical solutions corresponding to typical profiles of trapped charges. These analytical resolutions are valid as long as the generation of free carriers remains little disturbed by the trapped charge, i.e. when the space charge effect is not too important. They are therefore limited to low doses of irradiation, and need simplifying hypotheses. III-26

• The first simplifying assumption is that corresponding to the stationary regime. The method [Lera-89a, Lee-91, Kran-87] then basically consists in solving the continuity equations for free carriers, by assuming that ∂n/∂t = ∂p/∂t = 0. We assume that the radiation-induced free carriers do not accumulate in the oxide, and thus are either trapped, or swept away at the electrodes.

Si

2 e

GATE jn

λn >> t ox

jp

λp << t ox

h+ t ox

0

Figure 17. Illustration of the electron and hole currents in the oxide (for a constant dose rate), under positive gate bias.

In the following, let us examine the case of an irradiation under a positive gate bias. The case of a negative bias will be deduced by symmetry. The boundary conditions for currents jp(x) and jn(x) are in this case: jp(0)=0 and jn(tox)=0 (we thus assume that the electrodes do not inject any carrier). The traps are supposed to be uniformly distributed in the oxide. This limitation is not compulsory, but it greatly simplifies the calculations. With these boundary conditions, we obtain the following solutions to Eqs. (24) and (27):

(34)

  & Y(E) λn 1 − exp − t ox − x  jn(x) = go D   λ n   

(35)

 & Y(E) λp 1 − exp − x jp(x) = go D  λ  n 

  

The above expressions have been simplified by introducing the concepts of mean free path before capture for electrons (λn), and holes (λp), which can respectively be written: 1

(36)

λn =

σ nr p t + σ nt (N TN − n t )

(37)

λp =

1

σ pr n t + σ pt (N TP − p t )

The currents are represented schematically in fig. 17 above. Because of the uniform distribution of traps, the continuity equations for trapped holes and trapped electrons can be written in this case: III-27

(38)

∂n t ( x , t ) = σptjp(x,t)[NTP−pt(x,t)] − σnr(E)jn(x,t)pt(x,t) ∂t

(39)

∂p t ( x , t ) = σntjn(x,t)[NTN−nt(x,t)] − σpr(E)jp(x,t)nt(x,t) ∂t

These expressions contain cross-coupled terms jp(x,t) and jn(x,t), which makes it very complex to find an analytical solution. • An additional simplifying assumption is to neglect the free carrier-trapped charge recombination. In this case, the expressions of the mean free paths before capture (i.e. (27) and (28)) become: 1

(40)

λn =

σ nt (N TN − n t )

(41)

λp =

1

σ pt (N TP − p t )

The continuity equations for trapped carriers then reduce to:

(42)

∂n t ( x , t ) = σntjn(x,t)[NTN−nt] ∂t

(43)

∂p t ( x , t ) = σptjp(x,t)[NTP−pt] ∂t

In the next paragraphs, the calculation of the voltage shifts associated with charge trapping will be detailed, first by taking into account only one type of trapped carrier, then by taking into account both types, using the superposition theorem.

III-28

3.9.

CASE OF A SINGLE TYPE OF TRAP

3.9.1. SOLUTION FOR POSITIVE BIAS Let us consider for the moment that the material only contains hole traps, uniformly distributed in the oxide, and a positive gate bias. Replacing jp(x,t) by expression (35) into Eqn. (43), we get: (44)

∂p t ( x , t ) & Y(E) 1 − exp (− σ pt [N TP − p t ] x ) = go D ∂t

[

]

& is the dose rate. This equation can be rewritten: where D

(45)

∂p t ( x , t ) & Y(E) 1 − exp (− σ pt N TP x ) exp (− σ pt p t x ) = go D ∂t

[

]

In the low dose regime, the trapped charge density remains small, and we can develop the exponential term to the first order. It yields:

(46)

∂p t ( x , t ) & Y(E) 1 − exp (− σ pt N TP x )(1 + σ pt p t x ) = go D ∂t

[

]

By integrating over time, we find the following expression of the positive charge trapped in the oxide as a function of x: (47)

[

]

pt(x,tirr) = go D Y(E) 1 − exp (− σ pt N TP x )

Here, D being the (integrated) absorbed dose (D =

t irr

∫0

& (t) dt where tirr is the irradiation D

duration). The spatial distribution of this positive trapped charge after a given irradiation time t is represented schematically in fig. 18 below: Gate

SiO2

Si N

TP

E p

t

h+

t ox

0

Figure 18. Distribution of the positive charge trapped in the bulk of the oxide (at a given dose), under positive gate bias (see text for assumptions made).

It is now necessary to calculate the voltage shift associated with this trapped charge. This voltage shift corresponds in fact to the voltage one must apply to the gate, to compensate the image III-29

charge induced in the silicon substrate by the charge trapped in the oxide. This image charge is given by the first moment of the space charge distribution. The voltage shift associated with this charge can then be written: (48)

∆Vot h+ = −

q ε ox

∫

t ox

0

x p t ( x, t irr ) dx

(∆Vot h+ is the voltage shift due to the oxide-trapped hole charge, under positive gate voltage.) Replacing pt(x,tirr) by expression (47) yields : (49)

∆Vot h+ = −

[

]

q g 0 D Y t ox x 1 − exp(− σ pt N TP x ) dx ε ox ∫0

After integration, it becomes: ∆Vot h+ = 2   q g 0 D Y t ox  1 1 1 (1 − exp (− σ pt N TP t ox ))  − exp (− σ pt N TP t ox ) −  + ε ox σ pt N TP t ox  2 σ pt N TP t ox   

(50)

If we note that the mean free path before capture, in the low dose regime (neglecting the electron , then the voltage shift can be written: - trapped hole recombination), is: λp = 1 σ pt N TP

(51)

∆Vot h

+

q g 0 D Y t ox = − ε ox

2

 1 λ p  +  2 t ox

  t exp  − ox  λ  p 

 λp   1 − exp  − t ox −  t ox   λp   

          

Expression (51) gives the voltage shift associated with the positive charge trapped on hole traps uniformly distributed in the oxide, in the case of a positive applied electric field. The ratio κ=tox/λ λp evidently plays a critical role as representing the capture efficiency. The equation can be rewritten:

(52)

∆Vot h

+

q g 0 D Y t ox =− ε ox

2

ϕ + ( κ)

with

(53)

1 1  1 ϕ + (κ ) =  + e − κ − 1 − e − κ κ 2 κ 

(

)  

and

III-30

(54)

κ=

t ox = σ tp N TP t ox = σ tp N TPS λp

NTPS representing the total trap density per unit area (uniform distribution). This equation can be simplified in two limit cases: when the mean free path is much greater than the oxide thickness (case of a low trap density), or much smaller than it. It yields: • When the mean free path is larger than the oxide thickness, i.e. when κ= σ tp N TPS <<1, then by developing the exponential term to the third order we find that ϕ+(κ) tends towards σ tp N TPS /3. • When the mean free path is smaller than the oxide thickness, i.e. when κ= σ tp N TPS >>1, then ϕ+(κ) tends towards 1/2. In summary ∆V can always be written under the following forms: (55)

∆Vot h+ ≈ − α β Ω Y(E) t ox D 2

q g0 a constant of silicon dioxide and a and b two factors, related to the process and to ε ox the trapped charge profile, respectively.

with Ω =

α and β represent the trapping coefficient and the trapped charge distribution can be asserted from the series development in two limiting cases: - when the quantity of traps is small (κ<<1):

- for a large quantity of traps (κ>>1):

 3  α = ϕ + ( κ) = σ tp N TPS 1 − σ tp N TPS + ..   8  and β=1/3 α=1 and β=1/2

3.9.2. SOLUTION FOR NEGATIVE BIAS The current is determined from the boundary condition jp(tox)=0:

(56)

  & Y(E) λp 1 − exp − t ox − x  jp(x) = go D  λ n   

Like for the positive bias, the trapped charge profile is obtained by integrating the trapping equation, and the voltage shift by a second integration. It yields:

(57)

∆Vot h

-

q g 0 D Y t ox =− ε ox

2

ϕ − ( κ)

with: III-31

(58)

1 1  1 ϕ − (κ ) =  − 1 − 1 − e − κ 2 κ  κ

(

)  

This equation can be simplified in two limit cases: when the mean free path is much greater than the oxide thickness (case of a low trap density), or much smaller than it. It yields: • When the mean free path is larger than the oxide thickness, i.e. when κ= σ tp N TPS <<1, then by developing the exponential term to the third order we find that ϕ−(κ)tends towards σ tp N TPS /6. • When the mean free path is smaller than the oxide thickness, i.e. when κ= σ tp N TPS >>1, then ϕ−(κ) tends towards 1/2. We can summarize the limiting cases in table 6: κ= σ tp N TPS

κ= σ tp N TPS <<1

>>1

ϕ+(κ) =

( σ tp N TPS )/3

1/2

ϕ−(κ) =

( σ tp N TPS )/6

1/2

∆Vot h-/∆Vot h+=ϕ−(κ)/ϕ+(κ)

1/2

1

Table 6.

Characteristic coefficients in the case of uniform density of traps.

Remark: To come to these reasonably simple analytical solutions, we have assumed that the traps are uniformly distributed across the oxide bulk. This hypothesis is only justified to simplify the calculation. Indeed, expression (47) and fig. 18 show that the trapped charge will have a nonuniform spatial distribution, even if the trap density is uniform. For all practical purposes, the only thing that matters is that the traps be distributed in the oxide bulk (more or less uniformly). This calculation can be made in other cases of interest, such as trapping at one interface. One can define a set of coefficients α and β for this case. Another solution is to get use of numerical integration, as it is addressed in chapter 4. 3.10. LOW DOSE AND HIGH DOSE REGIMES IN THE SIMPLIFYING CASE OF INTERFACE TRAPPING This model has been widely used in the literature for more than 25 years to account for charge trapping in thermal oxides. Although we know for 15 years that it is not completely true, the most often used hypothesis is that these oxides only possess hole traps. We therefore neglect electron trapping in neutral traps, and consider that electrons are only able to recombine with trapped holes. The hole traps are supposed to be entirely located at the Si/SiO2 interface. The equations in this case are simplified compared to the previous case, since we consider that the carriers generated by irradiation can move through the oxide without trapping in the bulk, and only be trapped at the interface. By taking recombination phenomena into account, the evolution equation for charged traps at the III-32

interface can be written:

(59)

∂N TPS ∂t

+

= [NTPS− NTPS+] σpt(E) jp(tox) - NTPS+ σnr(E) jn(tox)

where NTPS now represents the trap density at the interface and NTPS+ is the fraction of charged traps. Note that we now take the recombination of trapped holes with free electrons into account, as one goal is to account for saturation behavior when a steady state occurs between the effects of the hole and electron fluxes. To get the expression of the current at the interface, we need the integration of continuity and transport equation in the volume of oxide. From the hypothesis, no deep trap NTP is supposed to exist in the volume, so that carriers will be only subjected to be self-trapped of recombined. We shall gather all this physics into a first-order kinetics, characterized by a lifetime τn (for electrons) and τp (for the holes). Note that as no deep traps exist in the volume, it is likely that the value of τp identifies with the “free” hole lifetime τp0 (see section 3.6.3), and so does µ p with µ p0. This gives a value of µ pτp of nearly 10-12 cm2 V-1, used in many models since the 60s and relatively independent of the temperature. (The situation is not as clear for choice of a value for the electrons.) The expression of current jp at the interface is obtained by solving the continuity equation for free holes in the stationary regime.

(60)

∂p ∂ j p & Y(E) − p + = g0 D ∂t ∂x τp

and

By neglecting the diffusion term and in the case of quasi-uniform electric fields, the current ∂j p ∂p( x , t ) ∂p gradient is simply = µ p E , and since = 0 in the stationary regime, we get: ∂x ∂x ∂t (61)

dp( x ) & Y(E) − p( x ) µ p E = g0 D dx τp

which yields:

(62)

& Y(E) tox jp(tox) = p(tox,t) µp E = g0 D

 µ p τp E  t ox  1 − exp −  t ox   µ p τ p E 

& Y(E) tox f h (E) = g0 D with

(63)

f h (E) =

 µ p τp E  t ox  1 − exp −  t ox  µ τ E p p   III-33

which corresponds to the hole collection function at the interface. For strong fields, f h (E) ≈1. For low fields, f h (E) ≈

µ p τp E t ox

.

In the same manner, we can calculate the expression of the electron current at the interface for VG positive by solving the continuity equation for free electrons in the stationary regime. For this purpose, let us introduce the actual extension of the hole trap distribution, and let us assume this extension is small before tox. Be Xh the centroid of the trapped holes (small with respect to tox). We obtain: (64)

& Y(E) Xh f e (E) jn(x=Xh) = g0 D

where f e (E) corresponds to the electron collection function at the interface. As electrons are much more mobile than holes, expression of fe should gather several components: -

The drift component, as calculated for holes. However, we can assume that

µn τn E t ox

>> 1 so

that fe≈1 -

Other mechanisms not described here, such as diffusion, hot electrons. (Extension could be made to electron injection from silicon, not addressed here). We proposed to lump these k T µn τn terms, into two terms Ldif/tox= representing diffusion and LH/tox representing 2 q t ox possible hot-electron component.

We can therefore solve the evolution equation for charged traps at the Si/SiO2 interface by replacing the currents by their expressions. It becomes:

(65)

+

N TPS (D) =

[

]

N TPS 1 − exp(− σ pt g 0 f h (E) Y(E) t ox [1 + F(E)] D ) 1 + F(E)

where

(66)

F(E)=

σ nr f e (E ) X h σ pt f h (E ) t ox

The voltage shift associated with this charge trapped at the interface can be written [Lera-89a]:

(67)

∆Vot h+ = −

[

]

q N TPS t ox 1 − exp(− σ pt g 0 f h (E) Y(E) t ox [1 + F(E)] D ) ε ox 1 + F(E )

It is possible to separate the behaviors at low and high dose by developing the exponential term in linear and in saturation parts. It yields: III-34

- at low doses, (68)

∆Vot h+ ≈ − α β Ω f h (E) Y(E) t ox D 2

- at high doses,

(69)

∆Vot h+ ≈ − A

N TPS t ox 1 + F(E)

with o q = 4.76 Volts / k A / 1012 charges.cm-2, being introduced as another characteristic ε ox constant of SiO2.

A=

III-35

3.11.

ANALYTICAL MODELING

Eqn. 68 and 69 can easily be used. It gives the following set of representation (fig 19.). The two curves a and b refer to the response at low dose (linear) and at high dose (saturation), respectively [Lera-89a].

Large dose Weak dose

Figure 19. Analytical modeling of ∆Vot at low and high dose. ∆Vot versus EG (MV/cm). Case of a 65 nm oxide and σpt =σpr=10-12 cm2

3.12.

PRACTICAL APPLICATIONS

Due to the complexity of the phenomena occurring during the generation, transport and trapping of charges in an irradiated oxide, simple analytical expressions can only be obtained when broad simplifying assumptions are made. The equations derived from these models are then only usable in the experimental context that satisfies the series of assumptions made. To simplify the interpretation of experimental results even further, we attempt next to schematize the behavior of some typical oxides. This will give us a tool to rapidly identify specific trends by the simple observation of some measured electrical characteristics. 3.12.1. ELECTRICAL MEASUREMENT TECHNIQUES Before beginning to discuss and interpret experimental results, let us briefly recall some of the most common measurement techniques used to electrically characterize defects in MOS devices. In practical applications, the experimental structure being tested is either a MOS capacitor or a MOS transistor. • In the case of a MOS capacitor, the technique consists in recording the capacitance-voltage curve (C-V curve), either using a small AC signal superimposed on a DC voltage ramp (high or low frequency C-V), or using a quasi static C-V technique. Fig. 20 shows typical high frequency (1MHz) C-V curves obtained on a p-substrate MOS capacitor, before and after irradiation at a dose of 10 Mrad(SiO2). The dashed lines in fig. 20 show the position of the flatband (Cfb) and midgap (Cmg) capacitances, defined respectively as the capacitance value for which the silicon surface potential equals 0 and φB. Potential φB is the bulk potential given by:

III-36

(70)

φB =

kT  N A  ln  q  ni 

where q is the elementary charge of an electron, k is the Boltzmann's constant, T is the absolute temperature, NA is the substrate doping concentration, and ni is the intrinsic carrier concentration. The gate voltage applied to reach Cfb (resp. Cmg) is the flatband voltage Vfb (resp. migdap voltage Vmg). The traps at the Si/SiO2 interface are amphoteric, which means that their charge state can change depending on the value of the surface potential of silicon. The traps thus can be positive, neutral, or negative. Traps in the lower half of the Si bandgap are predominantly donorlike (i.e. they “give off” an electron when the Fermi level at the interface is below the trap energy level), and traps in the upper half of the bandgap are essentially acceptor-like (i.e. they “accept” an electron when the Fermi level at the interface is above the trap energy level). The most widely accepted assumption (well confirmed by recent results [Flee-92]) is that interface traps are approximately charge neutral at midgap [Kim-88, Wino-88, McWh-52]. With this assumption, the midgap voltage shift (∆Vmg) caused by irradiation is only due to the oxide trapped charge (∆Vot), while the flatband voltage shift takes into account both the oxide trapped charge and the charge trapped on interface traps between flatband and midgap. CHF (pF) 65 60

Figure 20. Typical high frequency (1MHz) C-V curves of a MOS capacitor before and after a 10 Mrad(SiO2) irradiation. The structure was biased at VG = 0 V during irradiation.

C fb

55

0 krad 50

10 Mrad

45 40

C mg

35

-40

V mg

V fb

30

-30

-20

-10 VG (V)

0

10

20

• In the case of a MOS transistor, the most usual technique consists in recording the currentvoltage curve (I-V curve), usually the drain current IDS versus gate-to-source bias VGS, at a given drain-to-source bias VDS either in the linear region (small VDS) or in the saturation region (large VDS). The threshold voltage of a transistor is determined basically from the intercept with the voltage axis of the ID vs VGS curve in the linear region, or of the (ID)1/2 vs VGS curve in the saturation region. Another method, which is similar to that used for capacitor studies, is to determine the gate voltage for which the surface potential of the silicon substrate equals 2φB, which corresponds to the onset of strong inversion [McWh-86]. Figures 21 and 22 show typical I-V curves obtained on an n-MOS transistor, before and after irradiation. On fig. 22, the position of the “threshold current” and “midgap current” is defined as those values of IDS for which the surface potential of silicon equals 2φB and φB respectively. The amplitudes of the threshold and midgap voltage shifts caused by irradiation are also shown in fig. 22. III-37

The calculated “midgap current” is usually very low, thus the midgap voltage is obtained by extrapolating the I-V curves to the low current level required, and by determining the voltage corresponding to that “midgap current”. Except for the extrapolation step, this method is very similar to the high-frequency C-V method. Using the same assumption, ∆Vot is equal to the midgap voltage shift (∆Vmg), whereas the threshold voltage shift (∆Vth) is equal to the sum of ∆Vot and ∆Vit. Consequently, the voltage shift due solely to the interface trapped charge, ∆Vit, can be determined by the stretch-out of the I-V curve (i.e. by difference ∆Vth - ∆Vmg). Ids (mA) -3

10

I DS

-5

10 10

VOT

VOT

∆Vth

-7 -9

10

Post-rad

Pre-rad

-11

10

-13

10

MOS P

MOS N

V GS

∆Vmg

-15

10

-3

-2

-1

0

1

2

3

VGS (V)

Figure 21. Drift of MOS transistor characteristics in the case of only the trapping of positive charge in the oxide.

Figure 22. Typical sub-threshold I-V curves of an n-MOS transistor revealing the contribution of interface states.

Other techniques have been developed to determine ∆Vot and ∆Vit, especially the dual-transistor techniques, combining threshold voltage measurements with either mobility measurements or charge pumping techniques. The reader is referred for instance to [Wino-92] and [Autr-99] for more details. 3.12.2. BEHAVIOR IN THE LOW DOSE REGIME After a low dose irradiation of a silicon oxide, a net positive charge is created in the insulator. Depending on the process used to manufacture the oxide, this trapped charge can be distributed in different ways in the material. To determine the type of charge trapping taking place, a simple method consists in measuring the trapped charge for different biases applied during irradiation. We can thus evaluate how the electric field influences charge trapping, which gives information on the position of the centroid of the net trapped charge. In the next paragraphs, several typical cases are presented. 3.12.3. CASE OF CHARGE TRAPPING AT THE SIO2/SI INTERFACE This is the simplest case, and that most often used to interpret charge trapping in thermal oxides. III-38

The traps are assumed to be all located at the SiO2/Si interface. • During an irradiation under a positive bias (VG > 0), the generated holes flow toward the interface and can get trapped there. This trapping gives birth to an important image charge in the semiconductor, and therefore to a significant voltage shift of the irradiated structure. ∆Vt

Si

SiO2

ρ

Gate

E>0

ox

E<0 0

-E

0 Applied electric field

+E

eox

Thickness

0

Figure 23. Schematic representation of the electric field dependence of the measured voltage shift, in the case of an interfacial charge trapping (left). The corresponding trap distribution (NTP(x)) and charge distribution ρ(x) in each case (E>0 and E<0) are also shown (right).

• On the other hand, during an irradiation under a negative bias, holes flow toward the gate, and only a very small fraction of them can get trapped at the SiO2/Si interface. In this case, the image charge in the semiconductor is reduced and leads to a far less important voltage shift. ∆Vt (Volts) Figure 24. Measured midgap voltage shift versus gate bias applied during irradiation, of a thermal oxide at a dose of 10 krad(SiO2) [Pail-94].

20 16 12 8 4 0 -40

-30

-20

-10

0 10 VG (V)

20

30

40

One thus obtains a completely asymmetrical ∆Vot(E) characteristic. This asymmetrical shape is typical of a distribution of hole traps close to the Si/SiO2 interface. Figure 23 illustrates this expected behavior, as well as the trap and charge distributions corresponding to such a case. Figure 24 shows an example of the voltage shift induced by the oxide charge trapped in a thermal oxide, as a function of the gate bias applied during irradiation [Pail-94]. 3.12.4. CASE OF CHARGE TRAPPING IN THE BULK OF THE OXIDE III-39

Let us now consider the case of hole traps uniformly distributed in the oxide. During an irradiation under a positive bias, the hole current flows toward the SiO2/Si interface. Holes can then get trapped in the bulk of the oxide, and give birth to a positive space charge growing from the gate up to the interface, as illustrated in fig. 25.

ρ

0 -E

0

E

Applied electric fied

e ox

0 Thickness

Figure 25. Schematic representation of the field dependence of the measured voltage shift, for a uniform bulk charge trapping (left). The corresponding trap distribution (NT=cst) and charge distribution ρ(x) in each case (E>0 and E<0) are also shown (right).

The centroid of the trapped charge is in this case close to the SiO2/Si interface, and the image charge induced in the silicon substrate is therefore sizeable. Charge trapping also increases with increasing applied field, because the fraction of holes escaping initial recombination increases, and more holes are available to be trapped. For a similar irradiation, but under a negative bias and uniform trap density, the trapping process is symmetrical. Holes flow toward the gate, but can however get trapped in the oxide bulk. The centroid of the trapped charge is then displaced toward the gate, and the image charge induced in the silicon substrate is less important than under a positive bias. A similar dose of irradiation, but deposited under zero applied bias, leads to a very small voltage shift, smaller than that obtained under negative and positive bias. Indeed, under zero applied bias, the fraction of separated pairs is far smaller and recombination is enhanced, and thus, the number of carriers likely to get trapped is greatly reduced. The ∆Vot (E) curve, obtained in the case of a uniform trap distribution, displays an almost symmetrical behavior with regards to the sign of the applied field. The shift obtained under negative field remains however smaller than that obtained under positive field. By integrating the trapped charge profiles shown schematically in fig. 25, we can evaluate the associated voltage shifts. In this case of uniform trap distribution, and if the trap density is not too high, it has been − & / D ratio of 1/2. shown that analytical calculation as developed above leads to a ∆Vot

III-40

20

MOS Capacitors

NMOS Transistors

15

10

5

0 -40

-20

0

20

40

Applied gate voltage (V) Figure 26. The voltage shifts, measured on MOS capacitors and transistors using SIMOX oxide irradiated at a dose of 10 krad(SiO2), are plotted versus the gate voltage applied during irradiation [Pail94].

Figure 26 shows an example of the experimentally measured voltage shifts induced by the oxide charge trapped in a SIMOX oxide, as a function of the gate bias applied during irradiation. In this example, both MOS capacitors and NMOS transistors have been irradiated to a dose of 10 krad(SiO2)). 3.12.5. CASE OF A MULTILAYER INSULATOR Multilayer insulators possess by construction several interfaces, which are potential sources of defects, and which therefore act as preferential trapping locations during irradiation. Historically, multilayer oxides have been ised in the 60s for better reliability at that time [Hugh-71]. These multilayer structures are used for example to manufacture field oxides. The purpose in this case is to replace the thick thermal LOCOS oxide by a doped oxide usually less sensitive to radiation. The doped oxide is placed between a thermal oxide (which ensures a good Si/SiO2 interface) and an undoped oxide, in order to limit the diffusion of dopants. Some nitrided oxides (ONO structure) can also be considered as multilayer structures, the silicon/oxide interface being fabricated from a pure thermal. MOS devices with Ta2O5 dielectric can also be considered as multilayer, because of the presence of silicon oxide as transition layer between Si and tantalum pentoxide [Autr-95]. Even if they are made up of thermal oxides, buried oxides obtained by wafer bonding (BESOI, e.g. UnibondTM) must also be regarded as multilayers, because of the presence of the bonding interface [Pail-95a], [Lera-97]. These various structures being generally made up of oxides, which exhibit little bulk charge trapping, the traps may be considered as being mostly located in the interfacial regions. The expected trap distribution profiles are illustrated in fig. 27 (right). The structure represented here is a two-layer one, and the oxide/silicon interface is supposed to be of good quality. On the other hand, the interface separating the two insulating layers contains a much larger defect density, which is often the case for deposited or bonded oxides.

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ρ

ox

E<0 E>0

0 -E

0 Applied electric field

E

eox

Thickness

0

Figure 27. Schematic representation of the field dependence of the measured voltage shift, in the case of charge trapping at the interfaces of a multilayer oxide (left). The corresponding trap distribution (NTP=cst) and charge distributions ρ(x) in each case (E>0 and E<0) are also shown (right).

During irradiation under a positive bias, the hole current is maximum at the Si/SiO2 interface (see fig.27), and the holes get trapped mainly near the Si/SiO2 interface, which contains few defects. Many fewer holes get trapped at the interface between the two oxides. Under a negative bias on the other hand, holes are attracted by the gate, and mostly get trapped at the interface between the two oxides. The defect density being much more important there, the image charge induced in the silicon substrate will be more important in this case. It is therefore possible for a negative bias to produce a voltage shift that is larger than that produced under a positive bias (as illustrated in fig. 27), and this is exactly the opposite of what would be found for a pure thermal oxide [an example is given e.g., in Hugh-71]. 3.12.6. BEHAVIOR IN THE HIGH DOSE REGIME In the high dose regime, the electric field in the oxide can no longer be considered as equal to the applied field. The presence of a large trapped charge can strongly disturb the internal field, especially if the charge is distributed throughout the volume. In case of thick oxide, the internal field can be reduced to almost zero in a large part of the oxide. This “Field Collapse Effect” has been conceptually described very early [Grov-66], [Mitc-67] (pp. 63-67). This was experimentally studied by Hughes [Hugh-85] in the case of thermal oxides irradiated at low temperature where significant hole trapping occurs, and by Boesch [Boes-91] in the case of implanted oxides. Only numerical calculation of trapping, self-consistent with the Poisson equation, can adequately describe this second-order effect, and the reader is invited to refer to the section “Numerical Modeling”. 3.13. SIMPLE METHOD TO EVALUATE THE HARDNESS FACTOR OF A MOS PROCESS FOR THE TRAPPING OF HOLES The sensitivity of a given oxide + interface system is measured by the fraction of trapped holes as compared to the quantity of holes that have escaped the initial recombination. If one considers only the interfacial trapping, the problem is greatly simplified since it suffices to evaluate the relationship between the quantity of trapped holes (cross-section notions are applicable) and the III-42

quantity of holes that cross the interface by escaping the trapping. The hardening of the oxide consists in this case to reduce this quantity of trapped holes at the interface. 3.13.1. SIMPLIFIED FORMULA In the following, assume that the two ∆Vit and ∆Vot components have been separated by one of the standard methods. We make the additional assumptions or requirements: - There is negligible apparent quantity of trapped electrons. - The NMOS transistor is positively biased during irradiation with not too much space charge effect (EGS>1 MV/cm during irradiation, and ∆Vt / tox< 1 V/10nm). The consequence of these on hole trapping effects is the negative drift of MOS threshold voltages. In the low dose regime, we generalize the simple formula we have derived from the uniform and the interface distribution of traps: (71)

∆Vt ≈ − α β Ω f h (E) Y(E) t ox D 2

with: α=

σ.Nt trapping coefficient (Nt = surface density)

β=

xh/tox position of charge distribution centroid

Ω=

& 2 / krad(SiO2) or 36 mV/nm2 / Mrad(SiO2) 36 V/ µm 2 / krad(SiO2) or 0.36 V/ k A

fh(E) =

function of charge collection at the trapping location

Y(E) =

function of non-recombination

It can be recalled that this type of analysis has been proposed from 70s by Freeman and HolmesSiedle (coefficients “F=R.A.D” [Free-78]). It has been extended by [McGa-80] and [Benedetto] (introducing coefficients ft, fy). The present formulation is that of the CEA team (coefficients a=σ.Nt, Y and ft functions, F functions cf. [Lera-89a], [Pail-99] and this chapter). All these formulations proceed from the same spirit. Authors have widened this formulation to interface states (cf. hereafter) [Flee-92, Berl-92], but physical basis are not so firm as for charge trapping (coefficients fot, fit). Anyway the major drawback of these schemes is to skip all the physics involved in the kinetics of charge build-up and detrapping. But they are instrumental as a first-order approach. 3.13.2. NUMBER OF TRAPS NT AS A KEY PARAMETER When at sufficiently high dose, all traps are filled, and saturation is reached. Charge density is then in the case of interface trapping: (72)

Qot = Nt III-43

and therefore the saturation value of the threshold voltage shift is (under the simplifying assumptions): (73)

with A =

∆Vot ,sat = − A N t t ox

q ε ox

& / 1012 charges.cm-2 = 4.76 Volts / k A

According to this model, the parameter Nt is present at low doses and large doses (fig. 28). It is therefore this parameter that one must reduce. This generally implies the modification of the manufacturing process.

Figure 28. Separation of Vot threshold voltage component at low and high dose under simplifying assumptions

We note that this simple formula is linear as a function of dose (Volt/kilorad) and quadratic as compared to the oxide thickness. It applies only at low to moderate dose (e.g. some kilorads or hundred kilorad) and depends substantially on manufacturing process and oxide thickmess. Beyond this limit, the response is governed by a more complex exponential relationship or can’t be understood without numerical integration of the set of differential equations, with the correct parameters. 3.14.

EXTRACTION OF TRAP PARAMETERS

Once we have determined the trapping behavior of a particular oxide by means of the techniques presented in the preceding sections, we can try to estimate the characteristic parameters of the oxide traps. The reasoning is made then in terms of net equivalent charge projected at the Si/SiO2 interface, which corresponds to what is measured experimentally. We therefore use the equation of the voltage shift due to a trap distribution at the interface in the regime of strong applied electric field (i.e. with fh(E) ≈ 1): (74)

∆Vot+ = −

[

]

q N TPS t ox 1 − exp(− σ pt g 0 f h (E) Y(E) t ox [1 + F(E)] D ) ε ox 1 + F(E) III-44

in which we further assume F(E)≈0. By differentiating with respect to D, we can write:

(75)

 d∆Vot + ln  dD

  = − σ pt N TPS q g 0 Y(E) t ox 2 − σ pt g 0 Y(E) t ox D  ε ox 

The plotting of ln(-d∆Vot+/dD) as a function of dose leads to a separate extraction of the capture cross section and of the net equivalent charge at the interface, by determining the slope of the obtained curve and its intercept with the y-axis. For hole traps, this procedure of parameter extraction is only valid when the internal field is not too significantly disturbed by the trapped charge, i.e. in the low dose regime with a large applied electric field. When charge trapping occurs at the Si/SiO2 interface, the extraction of trap parameters is straightforward from the set of Eqns. (75) and (76) after extraction of the Vot component,. It becomes more difficult when charge trapping takes place in the oxide bulk (Eqn. 52 or 57). However this method is limited, because it only gives access to the product of the capture cross section by the trap density. The evaluation of the trap density usually requires to push irradiation in the saturation region, where internal electric field is distorted by the space-charge effect due to the trapped charges itself. Anyway, to assess this self-consistent effect, it is necessary to use a model of trap profile. 3.15.

CASE WHERE TWO TYPE OF TRAPS ARE PRESENT

3.15.1. CASE OF UNIFORM DISTRIBUTION OF TRAPS In the same manner as before, we can calculate the voltage shift associated with a negative charge trapped on uniformly distributed electron traps, for a positive applied bias In the case of uniform trapping, we must go back to differential equations (boundary conditions have to be exchanged) and the analytical resolution gives [Pail-99]:

(76)

+

∆Vot ,e = −

qg 0 ε ox

 1  1 1 (1 − exp(− σ pt N TN t ox ))  Y(E) t ox 2 D  − 1 −  2 σ nt N TN t ox  σ nt N TN t ox  

The net total shift obtained for a positive applied field is then simply the sum of the contributions 1 due to negative and positive trapped charges. We then obtain (with λn = being the σ nt N TN mean free path for electrons): (77) qg − 0 ε ox

+

∆Vot ,e + h =  λ p   t ox

  t exp − ox   λ p

 λp   1 − exp − t ox −  t   λ ox  p  

  λ n  λ n   t   + 1 − exp − ox 1−  λ   t  t  ox   ox   n  

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      Y(E) t ox 2 D    

and symmetrically for negative bias: (78)

−

∆Vot ,e + h =

 λ  λ   t ox   λ n   t ox  λ n   t ox    p p         Y(E) t ox 2 D  − 1 − + 1 − exp − 1 − exp − exp −         λ n     t ox  t ox   λ p   t ox   λ n  t ox  We therefore come to a system of two non-linear equations with two variables, which must be solved to extract the values of λn and λp from experimental data. (In the literature, this type of method has been first applied to photocurrents [Bene-87, Penn-90, Penn-92, Boes-94]. We here consider a similar approach, based on voltage shifts). The main disadvantage of such models is that it only gives access to values of the σtNT products. It is not possible to assess independently the capture cross-section and the trap density. qg − 0 ε ox

For that purpose, it is necessary to use a simpler model, based on the following idea: although trapped charges are distributed in the bulk, what we experimentally measure is the net equivalent charge, projected at the Si/SiO2 interface. It is thus possible to assimilate this equivalent charge to a charge located at the Si/SiO2 interface, and to use a simplified model, presented in the following paragraph. 3.15.2. CASE OF INTERFACIAL DISTRIBUTION OF TRAPS Electron trapping in oxides is only revealed in the case of a high dose irradiation when a large negative bias is applied. Due to large discrepancies in the capture cross sections of holes and electrons, the corresponding net voltage shift can be separated into two exponential components given by (67). Each one can be fitted with its set of trap-related parameters.

III-46

Figure 29. Oxide trapped charge contribution ∆Vot as a function of dose for -1 MV/cm back gate applied field [Pail-95b].

∆Vot

(Volts) 5 0 -5 -10

The symbols refer to different SIMOX oxide variants: Thin oxide, Medium I, Medium II, Standard. The solid lines correspond to the biexponential model fit. i S

iO S 2

-15

Gate

ρ E>0 ox

<0 E

0 -E

0 Appliedelectricfield

E +

eox Thick ness 0

-20

E = -1MV/cm

-25 10

0

10

1

10

2

10

3

4 10

10

5

Dose (krad)

Examples of such a trap parameter fit is shown in fig. 29, where the symbols refer to experimental data, and the solid line refers to this simple model fit with the case of the 80 nm “thin” SIMOX oxide. A very good agreement is shown here for SIMOX oxides of different thicknesses. The complete set of trap parameters (i.e., those extracted for large positive and negative fields) is given next in table 7. Hole Traps Oxide Type

Oxide thickness

NT

σt

NT

σt

[nm]

[cm-2]

[cm2]

[cm-2]

[cm2]

2.7 ± 0.3 ×1012 4.3 ± 0.2 ×1012 5.6 ± 2.2 ×1012 1.3 ± 0.4 ×1013

2.9 ± 0.3 ×10-13 2.8 ± 0.2 ×10-13 3.7 ± 1.7 ×10-13 5.2 ± 1.3 ×10-14

7.1 ± 0.1 ×1011 2 ± 0.2 ×1012 2.4 ± 0.3 ×1012 2.5 ± 0.3 ×1012

28 ± 16 ×10-15 15 ± 10 ×10-15 7.9 ± 3.3 ×10-15 5.4 ± 3.2 ×10-15

Thin SIMOX

80

Medium SIMOX

95

Medium SIMOX

121.5

Thick SIMOX

400

Table 7.

Electron Traps

Summary of trap densities and capture cross sections extracted from ∆Vot vs dose data using the exponential fit method [Pail95b].

III-47

4. NUMERICAL MODELING OF TRAPPING 4.1.

BACKGROUND

Since the mid-70’s, a series of modeling efforts have been pursued to numerically account for the trapping of charges in oxide. These stages of development have the following ideas and assumptions in common: - In most of low to moderate dose cases, oxide degradation is dominated by charge trapping whereas interface state contribution is less important. Anyway, the charge separation technique [McWh-86] has been widely applied and accepted for 15 years and a device response can most of the time be separated into oxide-trapped and interface-states contributions, which makes sense of separate modeling of Vot and Vit. - Whereas interface states physics is still a matter of debate, trapped charge equation is to first order better known, as far as several assumptions can be accepted. And, moreover, the charge trapping component is known to be the major component in parasitic medium to thick oxides such the lateral isolation edge in bulk-MOS and MOS/SOI, the field oxide in bulk-CMOS, and the buried oxide in CMOS/SOI. However, we shall point out that analytical solutions are not tractable in case of thick oxide, because the internal electric field developed by the charge itself is comparable to the field applied from the gate voltage and produces large distortions of the trapped charge profile, as remarked by [Boes-76]. We therefore show the unique help of a simple 1-D code, allowing investigations of the complex relation between trap profile (TP), internal potential build-up (PB), field-collapse (FC) and field-enhancement (FE). The knowledge of oxide parameters in space and energy is mandatory to fully predict charge trapping in any situation of time-dependent voltage profile. We show this process can be applied to various real-life situations such as MOS, CMOS, POWER-MOS, Field-Oxide parasitic transistors, and even LOCOS and Trench lateral transistors with some simplifying assumptions. 4.2. SIMPLIFIED NUMERICAL 1D ON LAPTOP COMPUTER: THE TRAPPOXR V.4 CODE AND VARIOUS APPLICATIONS In this simplified code, we take only the trapping of holes into account. (79)

∂p t = C p − R pn ∂t

where Cp and Rpn stand for hole capture and trapped hole recombination with free electrons. The continuity equations for electrons and holes gives the “drivers” n and p for this trapped charge:

III-48

(80)

∂n + div ( j n ) = G − R pn ∂t

and

∂p + div ( j p ) = G − C p ∂t

where jn and jP observe the drift-diffusion equation. The generation factor that creates an equal density of electrons and holes n and p is in turn written as follows: (81)

& G = g 0 Y(E) D

where D’ is the time derivative of the dose versus time, g0 = 8.2 x1012 rad(SiO2)-1.cm-3 and Y(E) the generation yield of electron-hole pairs escaping the initial recombination:

(82)

Y(E ) = Y0 + (1 − Y0 )

( )

m E E + Ec

(m=0.9 and Ec=1.35 MV/cm for 10 keV X-rays and m=0.9 and Ec=0.55 MV/cm for 1.33 MeV γ-rays).

60

Co 1.17-

Evidently, it is of most importance in medium-to-thick oxides operating at relatively low applied voltage to take into account the internal field modulation by the charge density through Poisson equation. This makes the analytical scheme really tricky and makes the whole problem really self-consistent. Although analytical solutions have been developed in limiting cases [see chapters above], they fail to describe actual cases on the whole gate voltage and dose range. This is the scope of this modeling to bring new insights on this. At this point, it can be remarked that two types of models have been considered these last 20 years, which differ from one another in the C and R terms. We shall categorize them as “VModel” (deriving from thermal velocity Vth) and “J-Model” (deriving from current flux j). 4.2.1. V-MODEL The equation is simply based on the carrier density at abscissa x. Note the similarity with some limiting cases of the Shockley-Read-Hall equation. (83)

C p = ( N TP − p t ) σ pt Vthp p

and

R pn = p t σ nr Vthn n

where Vthn and Vthp are the “thermal velocities” of the electrons and holes involved in the trapping and recombination process. 4.2.2.

J-MODEL

These equations derive from simple ballistic probability of a localized particle participating to fluxes j, to be trapped with a probability expressed by cross sections σ: (84)

C p = ( N TP − p t ) σ pt j p

and

R pn = p t σ nr jn

III-49

4.2.3.

TRENDS IN MODELING

The V-model seems to have had the favors of early workers (e.g. [Tayl-82], [Hugh-85], [Lera89a] p. 173, [Vasu-94]), whereas since the last 10 years, the J-model is used by a strong majority (e.g. [Kran-87], [Lera-89a] p.69, [Krantz-91], [Lee-91], [Flam-92], [Herv-94], [Pail-94], [Pail95b], [Esco-95b], [Bris-96], [Mila-98], [Grav-98]). It is nearly evident that the response of the two settings are strongly different with respect to one input, i.e. the hole mobility, and one output, i.e. the Vot shift per unit of dose as the gate bias during irradiation is made varying. The results presented here compare the two sets of equations implemented as options in a single code TRAPPOXR v.4. 4.2.4.

METHOD USED IN TRAPPOXR V.4 AND CODE IMPLEMENTATION

In the case of medium (Power-MOS) or thick (any parasitic MOS structure, spacer (bipolar base), lateral (edge or field oxide of MOS transistors) or buried (SOI)), the (external) weak field developed by boundary electrodes (gates, emitter electrode, supply or signal lines in actual devices) can be easily overcome by the internal field created by the charges present. The actual charge quantity and, more important, the actual charge profile depends not only on the trap profile, but also on the evolution of the internal field when irradiation proceeds. This is why a comprehensive understanding of these kinds of oxides must use two sources: - The dependence of the image charge on the dose level and the irradiation bias (in the following, such a dependence with bias will be called “bias spectrum”). - The calculation of the electrical field present from minimal hypotheses, compatible with the experimental spectrum and fitting dose dependence. In other words, the method for modeling the oxide trapping properties consists of heuristically resolving the inverse problem of determining a trap spatial profile from spectra of charge versus bias obtained at various doses. For this to occur, one must have in hand a simple, flexible tool to simulate charge response at any bias and any dose, given a population of traps characterized by their spatial distribution and cross-section. For this to happen, we present here the CEATRAPPOXR code version 4, whose aims are to exercise the oxide-trapped charge (∆Vot) response of devices under the assumption of 1-dimensional finite-difference treatment, but with the advantage of a fast treatment and user-friendliness provided by the principal mathematics platforms of the moment (MatlabTM, PV-WaveTM), or run-time on personal or portable computer [Lera-99b]. 4.2.5.

THE EFFECTS OF GATE BIAS: THE CASES OF TRAPPING IN VOLUME AND AT INTERFACE

In the following, we take the example of a Field Oxide transistor of 300 nm thickness. The voltage shift in Volt/kilorad can be seen in fig. 30 and 31 for the two models, different trap locations and variation of the hole mobility. One can see the difficulty of the V-Model to account for the asymmetry of the bias spectrum for the uniform distribution of traps. Hole mobility must be taken equal to electron mobility to show asymmetry versus bias.

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-1 300 A silicon side

-0,9 -0,8

dVot/dD (V/kilorad)

Figure 30. Simulation results for JModels and various traps location (hole mobility of 10-5 cm2/V.s, see appendix).

-0,7

1500 A silicon side

-0,6 -0,5 1500 A gate side -0,4 -0,3 3000 A uniform distribution

-0,2 -0,1 -40 -35 -30 -25 -20 -15 -10 -5 0 0

5

10 15 20 25 30 35 40

APPLIED VOLTAGE (Volts)

Here can be seen that asymmetry factor ∆Vot h-/∆Vot h+ is related to the trap distribution centroid Xp/tox, as predicted from the analytical model (section 3.9). The ratio is equal to ½ for a uniform distribution of traps, and becomes superior to 1 if the traps are concentrated near the gate. The situation is not so clear in the case of the V-model, and becomes strongly dependent on the mobility of the holes, as depicted in fig. 31. -1,5 'V 3000 A uniform µp=1E-5

Figure 31. Simulation results for VModels, uniform trap distribution and various hole mobility values.

dVot/dD (V/kilorad)

-1,3 -1,1 -0,9

V 3000 A uniform µp=0.1

-0,7 -0,5

V 3000 uniform µp=10

-0,3 -40 -35 -30 -25 -20 -15 -10 -0,1 -5 0

5 10 15 20 25 30 35 40

GATE BIAS (Volts)

4.3.

CASE OF AN UNHARDENED POWER MOS TRANSISTOR.

As can be seen, agreement is excellent for a thickness of 90 nm and a U-shaped profile of traps with the following approximation made using three boxes: - a box near the gate (2.5 1018 traps/cm3 on 45 nm) - a box mid of oxide (3.3 1017 traps/cm3 on 25 nm) - a box in the middle of the silicon interface (2.8 1018 traps/cm3 on 20 nm)

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-0,14

Figure 32. Comparison of the J-Model with experiment in the case of a power MOSFET with a U-shaped distribution of traps. Vot-Vg spectrum: example at 1 kilorad(SiO2).

EXPERIMENTAL

dVot/dD (V/kilorad)

-0,12 -0,1

J-MODEL 900 m1 -0,08 -0,06 -0,04 -0,02 -20

-15

-10

-5

0

5

10

15

20

0 GATE BIAS (V)

With this triple location if traps, this case ressembles the multilayred insulator depicted above. 4.4.

THE FIELD COLLAPSE EFFECT

Let us consider the case, illustrated schematically in fig. 33, of an oxide displaying a uniform density of hole traps, and for which electron trapping is first supposed to be negligible. Before irradiation, no trapped charge is present in the material; the internal electric field is therefore uniform in the oxide and equal to the applied field (case a). v e r y lo w d o se

no trap p ed charg e

lo w d o s e

h ig h d o s e

ρ

E

ox

V g /t ox 0

t ox

a)

0

b)

t ox 0

c)

t ox

0

d)

t ox

Figure 33. Illustration of the field collapse effect in an oxide (after [Boes-91]). (top) Profile of the trapped charge density. (bottom) Profile of the internal electric field. Cases a), b), c), d) are described in the text.

At the beginning of irradiation, a positive trapped charge is created uniformly in the bulk (case b). The electric field induced by the positive trapped charge tends to reduce the applied field at the anode, and to increase it at the cathode. The internal electric field, initially uniform in the oxide (no trapped charge), varies now linearly in the oxide, from anode to cathode (case b).

(

)

When the trapped charge i.e. ∫ qpt (x)dx becomes sufficient, it cancels the action of the field at the anode (case c). By assuming that the charge is uniformly trapped, we can calculate the value of the trapped charge density (Q+) for which the field at the anode becomes nil: it is that density which produces a voltage shift equal to the applied voltage. It yields:

III-52

(85)

- ∆Vot =

q ε ox

∫

2

t ox

x p t ( x ) dx =

0

t ox Q + = VG 2 ε ox

and thus

(86)

Q+ =

2 ε ox VG t ox

2

= 4.2 1016 charges.cm-3/Volt/(100 nm)2

If we assume that this charge is spread nearly uniformly in the oxide, the equivalent surface density of trapped charge is: Qtot= tox.Q+ = 4.2 1011/Volt/100 nm, which is a very usual value encountered in oxides. Therefore, the field collapse is a rather usual situation, in oxides of thickness above 100 nm. For this trapped charge density, the separation of electron-hole pairs is small in the anode region since the electric field there is nil. On the other hand the field is increased at the cathode, and the generated electrons, separated in this strong field region, are swept to the low field region, where they recombine with the existing trapped holes. The space charge in this region then tends to disappear, which leads to an extension of the zero field region (cases c and d). Let us now examine what are the consequences of the internal field collapse effect described above on the characteristic voltage shifts obtained under positive and negative bias. 4.4.1.

CONSEQUENCES IN THE CASE OF AN IRRADIATION UNDER POSITIVE GATE BIAS

When a positive bias is applied on the gate of a MOS structure, this electrode corresponds to the anode, and the cathode corresponds to the Si/SiO2 interface. In this case, the field collapse occurs under the gate, and the region of strong recombination extends from the gate into the oxide bulk. The trapped charge is therefore found mostly in that region (of thickness W) where the field is not nil, as illustrated in fig. 34. G a te

S iO 2

ρ (x )

Si

G a te

S iO 2

Si

E(x)

Q+

W W 0

0

t ox

t ox

Figure 34. Illustration of the field collapse effect under positive bias. Schematic representation of: left) the trapped charge density right) its contribution to the internal electric field.

When the absorbed dose increases, while VG remains unchanged, the thickness of this trapping region decreases. This is because Q+ increases with dose, and thus its associated internal electric field contribution increases also. Since the integration of the net internal electric field must remain equal to VG, W must decrease accordingly. The region where the field is not nil has therefore a thickness of:

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(87)

2ε V W =  ox G  Q+ 

1/ 2

   

When the trapped charge Q+ increases, W decreases. The calculation of the obtained voltage shift yields:

(88)

- ∆Vot,sat =

q

t ox

ε ox ∫0

Q + t ox x p t ( x ) dx = x dx ε ox ∫t ox − W

After integrating, and inserting W, we obtain:

(89)

 2 Q+ VG −∆Vot,sat =   εox 

1/ 2

   

t ox -VG

This model predicts that for an irradiation under positive field, the voltage shift increases with increasing dose, beyond the applied bias, but in a sub-linear manner. 4.4.2.

CONSEQUENCES IN THE CASE OF AN IRRADIATION UNDER NEGATIVE GATE BIAS

When a negative bias is applied on the gate electrode of a MOS structure, the anode corresponds to the surface of the silicon, and the cathode is the gate electrode. G ate

S iO 2

ρ (x )

Si

G a te

S iO 2

E (x)

ρ+

Q +W ε

Q+x ε

0

Si

W

0

t ox

W

t ox

Figure 35. Illustration of the field collapse effect under negative bias [Boes-91]. Schematic representation of: left) the trapped charge density right) its contribution to the internal electric field .

It follows that the internal field collapse effect now occurs near the SiO2/Si interface, and the region where the field is virtually nil extends from the interface into the oxide bulk. The trapped charge distribution and its contribution to the internal electric field are illustrated in fig. 35. By symmetry, the cancellation of the field at the interface is obtained for the same density of trapped charge as previously, but in this case the charge is distributed over a thickness W under the gate electrode. The calculation of the associated voltage shift in this case can be written :

(90)

- ∆Vot,sat =

q

t ox

εox ∫0

Q+ W x dx x p t ( x ) dx = ε ox ∫0 III-54

which, after integration, and after inserting W, leads to: (91)

∆Vot,sat = VG

This model therefore predicts that with a negative applied voltage on the gate electrode, the voltage shift associated to the oxide trapped charge saturates at a value ∆Vot,sat = VG when dose increases. 4.4.3.

CONCLUSIONS

This simple model of the “field collapse effect” has the advantage of yielding correct orders of magnitude. It agrees quite well with experimental data, provided we can measure voltage shifts due solely to the charge trapped in the oxide. As a matter of fact, the charge trapped in interface states is absolutely not taken into account in this model. In the case where interface trapping is important, this model is incomplete and must be revised. 4.4.4.

NUMERICAL ILLUSTRATIONS USING THREE DIFFERENT CODES

A significant number of 1D codes have been developed in-house these last 20 years, mainly for research use of the individual or the team itself. A new development is the appearance of 2D and 3D codes treating the trapping in oxides, inserted as modules into existing suites like ATHENA (now ORCHID) and DESSIS. To take examples, we can use here two commercial numerical tools (code A being commercialized by ISE, and code B by SILVACO). In order to simplify comparison, we adopt a uniform profile of traps. The Field Collapse model, anticipated by [Boes-76], and extended by [Hugh-85] and [Boes-91], is globally verified whatever the J- or V-model options used. However, this study demonstrates the striking effect of Field Enhancement (F.E.) that necessarily exists along with the Field Collapse to ensure the external boundary voltage imposed (gate bias), as pointed out in [Boes-91]. Also well demonstrated is the necessity of recombination to observe charge collapse (C.C.) as a consequence of Field Collapse. For this comparison, we use an oxide of 450 nm biased at +5 Volts (representing a Field-Oxide), featuring a uniform density of traps of NTP=4.41016 cm-3 (1012 cm-2) with σpt=σpr=10-12 cm-2. Field collapse in TRAPPOXR and code A operating in the V-Model Two cases are run: one with the recombination of trapped holes by electron flux and the other without (σpr=0).

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Electric Field (V/cm)

Figure 36. Field collapse with TRAPPOXR in the VModel (with e-h recombination).

oxide thickness (A)

Dose (krad(SiO2)

In figure 36 (above), the 3D representation allows to picture the electric field (z-axis) at any point of the oxide depth (left axis, from gate to silicon). Just at the beginning of irradiation, the gate potential is switched from 0 to +5V and the field is constant across the oxide. Then trapping begins to occur and the field enhances in the silicon region, while it decreases at the gate. At 30 kilorads, the gate field drops to zero, but contrarily to the oversimplified analytical model, charge does not collapse in a sufficient area to allow the field to stay at zero. On the contrary, field enhanced again, going into negative values. At that point, field at the silicon side enhances to greater values (Field Enhancement), allowing the integral of field over oxide to remain at +5 V. The following simulation (fig. 37) shows another simulation with a different 2D representation (code A) based on the same parameters, but using the V-model. It can be clearly seen that Field and Charge Collapse exist in the two cases independently of the code structure. Figure 37. Charge collapse with code A in the V-model (with e-h recombination σpr=10-13 cm2).

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Another interesting feature permitted by simulation is the calculation of the trapped charge profile with and without trapped charge recombination with electrons (fig. 38 and 39). Two extreme recombination cross-sections were used: 10-16 cm2 and 0. As can be seen, the recombination cross section, even at low values, is an essential parameter to field collapse and the trapped charge profile can be very different from the trap profile itself.

Figure 38. Charge collapse with code A in the V- Figure 39. Absence of charge collapse with code A in Model with e-h recombination purposely the V-Model with e-h recombination set at low value with σpr=10-16 cm2. switched off with σpr=0 cm2.

Field collapse in TRAPPOXR v.4 and code B operating in the J-Model Figure 40. Field collapse with TRAPPOXR in the J-model (with e-h recombination).

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Figure 41. Field collapse with code B in the J-model.

Code A in the V-model (lin scale)

Code B in the J-model (log scale)

Figure 42. Absence of charge collapse (without e-h recombination)with code A in the V-model and code B in the J-model.

This code is used with the feature of ignoring the recombination of trapped holes by electron flux (σpr=0). In this case, it is clearly seen that field collapse occurs (FC) along with Field Enhancement (FE) at the interface regions, but not the charge collapse as for code A. 4.5.

GATE BIAS SWITCHING III-58

Bias switching is an important issue, as in real operational life, devices are operated in the dynamic mode where voltages are continuously varying. However, hardness assurance tests are most often performed in steady state representing the “worst case”. It would be an advantage of modeling to obtain extrapolation from steady state experiments to real dynamic operation. Additionally, it has been remarked for long that most devices can recover to some extent if operated in the proper biasing. This situation has been first noted for MOS threshold voltage, silicon-on-sapphire leakage [Srou-76] currents and parasitic MOS edge leakage currents. This has been understood as the neutralization of trapped holes by electron currents, which can be enhanced if bias is made evolving towards a larger overlap of electron current flooding the trapped holes area. Consequences have been studied in details in [Flee-90], who called this effect “Radiation-Induced Charge Neutralization” (RICN), thus affecting ∆Vot. By taking into account the fact that the interface states are basically not affected by this electron flooding, [Flee-90] took advantage of the separation into two components Vot and Vit to propose “Twelve Rules”, presented nearly as theorems, to serve as guidelines to predict the behavior of a given MOS under switched bias condition, on a purely experimental basis and without invoking any calculation. However, analytical treatment of switched bias is possible [Lera-89a p. 83 and Lera-89b]. In this course, numerical modeling is exemplified by considering successively trapping at the interface and trapping in the volume. In the example given in fig. 43 to 48, a 300 nm oxide is studied with CEA-TRAPPOXR v.4, as representing a Field Oxide (parameters given in the Appendix) [Lera-99b]. The bias is switched from +5 to -5 V within 0.1 second at 2.5 seconds after the beginning of irradiation (i.e. at 2.5 kilorad(SiO2). In a first set of calculations, we consider the case of a distribution of traps located in the first 30 nm on the silicon side. One clearly sees a “recovery” due to the neutralization of the trapped charge by the electron flux when the bias is reversed from +5 to -5 V.

∆Vot (Volts) Voltage at mid-oxide (Volts)

Figure 43. Trapping at interface: Vot and the voltage at mid-oxide when the gate bias is reversed at 2.5 kilorad(SiO2).

Dose (kilorad(SiO2)

pt (charges/cm3) [x1016]

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E (kV/cm) [x105]

oxide thickness (A) gate silicon

dose (kilorad(SiO2))

Figure 44. Trapping at interface: trapped charge distribution across the oxide when the gate bias is reversed at 2.5 kilorad(SiO2).

oxide thickness (A) gate silicon

dose (kilorad(SiO2))

Figure 45. Trapping at interface: electric field distribution across the oxide when the gate bias is reversed at 2.5 kilorad(SiO2).

In a second set of calculations, we consider the case of interface plus bulk trapping.

∆Vot (Volts) Voltage at mid-oxide (Volts)

Figure 46. Trapping at interface plus oxide bulk: Vot and the voltage at mid-oxide when the gate bias is reversed at 2.5 kilorad(SiO2).

Dose (kilorad(SiO2) No recovery is observed because, whereas the charge trapped near silicon decreases, the charge trapped in the half-region near gate increases. In this case, it is sufficient to make the charge increase.

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pt (charges/cm3) [x1016] E (kV/cm) [x105]

oxide thickness (A) gate silicon

dose (kilorad(SiO2))

Figure 47. Trapping at interface plus oxide bulk: trapped charge distribution across the oxide when the gate bias is reversed at 2.5 kilorad(SiO2)

oxide thickness (A) gate silicon

dose (kilorad(SiO2))

Figure 48. Trapping at interface plus oxide bulk: electric field distribution across the oxide when the gate bias is reversed at 2.5 kilorad(SiO2)

In these figures, one can see the internal field modification across the oxide. At the end of the irradiation (50 kilorad), one can easily see the field collapse (FC) near silicon (positive electrode) and the field enhancement (FE) near the gate (negative electrode). As the field increases from 167 kV/cm before irradiation to nearly 300 kV/cm at 50 kilorad (Field-Enhancement), this has great importance in any physical process involved at the trapping site. On the other hand, the field vanishes to less than 70 kV/cm at the negative electrode (Field-Collapse) so as to fulfill the integral condition of developing the externally imposed -5 Volts. Conclusions and methods used in 1D used are useful as a start for conveniently handling more complex 2D and 3D simulations. In the following, other causes of annealing of the trapped charge are addressed.

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5. DETRAPPING AND TIME-EVOLVING EFFECTS 5.1.

ANNEALING, REVERSE-ANNEALING AND REBOUND

In the prior discussion, we have treated the trapped charge as being stable in time after the irradiation. This is only partially true and these effects are permanent only in appearance. We observe that a part of the trapped charge decreases slowly after the irradiation. That puts serious problems of tests validation and of qualification [Wino-94 for example]. Moreover one can separate the apparently permanent part of the effect that exists immediately after the irradiation, and the part that evolves in time through the use of “Post-Irradiation Effects” (PIE) analysis. The speed of neutralization of trapped charge is both a function of the temperature and of the electrical field (applied + space-charge). For example, at room temperature, 50% of charge can be neutralized between 100 and 1000 hours, but the coefficient of neutralization is essentially variable from a manufacturing process to the other, and of the oxide “quality”, and of the irradiation duration and dose rate itself. Two mechanisms are generally invoked: -

The compensation of positive charge by electrons, coming from the silicon, that cross the barrier of the interface by tunneling. The probability of tunneling is independent of temperature (if the tunnel effect is not assisted), and varies exponentially with the distance to interface.

-

Thermal emission of electron from the valence band to traps: the thermal emission varies exponentially with the inverse of temperature but it is independent of the spatial trap distribution.

Figure 49. Example of recovery mechanism of trapped charge by tunnel effect and thermal emission. According to [Oldh-86], [McWh-90].

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Tunneling can be envisioned as a front that advances in time at a speed of 0.2 to 0.4 nm per decade of time. The distance that the front moves into the oxide at a given time t is given by [McWh-90]: (92) where

χm = ln(αt) /2β α is the attempt to escape frequency β is a tunneling parameter related to electron barrier height

If the trap is farther than ~ 4 nm from the interface, it will be essentially inaccessible through tunneling during measurable times. As the spatial distribution of traps in the oxide is assumed to depend on the oxide fabrication process, the P.I.E. component due to tunneling can vastly differ from one process to another. -

One can therefore imagine a front of thermal neutralization similar to the front of tunneling neutralization. This thermal emission front can be written as:

(93) where

φm (t) = kT/q ln (AT2t) φ is the difference in energy between trap and oxide valence band A is a constant which depends on the capture cross section

These effects can be combined as indicated in fig. 49, according to [McWh-90]). As a consequence of these slow evolving post-irradiation processes, the simple data of the couple (value of a parameter, value of the dose at which it is obtained) is sometimes a poor indication of the actual response of a transistor. Other important parameters involved in the characterization and the response of a transistor are: the duration of the irradiation, the electric bias of the device during irradiation and after (or more generally the history of dose rates and biases), the record of the ambient temperature, etc. Thus, one must specify what sort of procedure has been used to perform the irradiation and obtain the data. The choice of the (presumably) standard procedure itself is determined by the context for which the data will be used (space, military, High Energy Physics, etc.). Standards have been edited for some of these contexts and discussed at length in previous Courses ([VanV95], [Flee-95], [Wino-92], [Peas-90], [Brow-90] and several lectures of the preceding decade).

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5.2.

MODELING THE TRAPPING AND THERMAL DETRAPPING EFFECTS

The set of trapping continuity equations has to be completed to take into account detrapping or neutralization. In the following, the case of thermal detrapping will be addressed. 5.2.1.

MODELING PIE IN TERMS OF ENERGY SPECTRA: PRINCIPLES AND EQUATIONS

It has been recognized that the trap depth is not unique, but exhibits a trap distribution. The following figure describes a way to model this distribution into approximate trap types: exponential tail representing shallow traps close to valence band, gaussian-like levels, boxes.

Dp(E) cm-2 eV-1 E2 ∆E2 E1 exp -E/∆E ∆E1

E3 ∆E3

E4 ∆E4

etc...

E-Ev Figure 50. Methods of modeling the distribution of deep traps in energy.

For one energy level i, the detrapping term can be described as follows by adding the terms ei .nt,i and ei . pt,i in the continuity equations. (94)

(95)

(96)

(97)

∂n & Y(E) − σnt,i(E)jn(x,t)[NTN,i(x)−nt,i(x,t)] + div jn = go D ∂t − σnr,i(E)jn(x,t)pt,i(x,t) + ei . nt,i ∂p & Y(E) − σpt,i(E)jp(x,t)[NTP,i(x)−pt,i(x,t)] + div jp = go D ∂t − σpr,i(E)jp(x,t)nt,i(x,t) + ei . pt,i ∂n t ,i

= σnt,i(E)jn(x,t)[NTN,i(x)−nt,i(x,t)] ∂t − σnr,i(E)jn(x,t)pt,i(x,t) − ei . nt,i ∂p t ,i ∂t

= σpt,i(E)jp(x,t)[NTP,i(x)−pt,i(x,t)] III-64

− σpr,i(E)jp(x,t)nt,i(x,t) − ei . pt,i − E Ani kT

(98)

e ni = σ nti Vth n N C e

(99)

e pi = σ pti Vth p N V e

− E Api kT

3k T ), NV are NC densities of states in the q valence and conduction band and EApi the trap depth in energy, with respect to the band edge. Here vth is the carrier thermal velocity ( v th =

This set of equations has been numerically integrated for 10 levels of energy and, for medium and thick thermal oxides, the result gives very good agreements with experimental data. Details are given at length in [Cirb-96] and [Pail-98]. The resulting set of continuity equations for free carriers is therefore (written in a generalized manner):

q

(100)

 k  (i )  (i ) (i )  ∂p (i ) (i )  l ( j) ( j) + div j p = G − ∑  σpt N p − p t jp −e p p t − ∑ σpr n t jp   ∂t i =1  j=1

     l  ( j)  ( j) ( j)  ∂n ( j) ( j)  k (i ) (i ) + div j n = G − ∑  σnt N n − n t σnr p t jn q   jn −e n n t −i∑ ∂t j=1 =1    

along with Poisson’s equation: (101) ∇ 2 Ψ = −

5.2.2.

  k l  p − n + ∑ p (i ) − ∑ n ( j )  t t ε  i =1 j =1 ox  q

RESULTS

A. Medium-thin oxide We have simulated a MOS capacitor structure having a thermal oxide of 45 nm. The trap energy distribution was taken from experimental results [Flee-92c], and is shown in Fig. 51.

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Hard oxide, 45 nm

Q/Qtot

0.2

0.1

0 1

1.2

1.4

1.6

1.8

2

2.2

2.4

Energy (eV) Figure 51. Energy distribution used for 45 nm thick oxides, from [Flee-92c].

100 Hard, 45 nm, 1Mrad@+5V TSC bias -10V

ITSC (pA)

10

1

0.1 0

100 200 Temperature (°C)

300

Figure 52. Simulated (dotted line) vs experimental (solid line) TSC on a 45 nm hard oxide MOS capacitor (TSC bias -10V), irradiated to 1 Mrad(SiO2) (irradiation bias +5V) [Pail-98]. The result is compared to experimental data from [Flee-92c].

The variations of experimental (solid line) and simulated (dotted line) ITSC are plotted in fig. 52 as a function of temperature. A very good agreement is obtained with experimental results as a function of temperature, despite the fact that no attempt has been made to modify the default values of the parameters given previously. The simulation has been then taken one step further, to see if the evolution of charge trapping with total dose in this oxide could be fitted as well. To this purpose, TSC simulations have been carried out at different irradiation doses, and the total TSC charge (i.e. integration of ITSC(t)) has been calculated at each dose level. The results of the dose dependence of this total TSC charge are shown in fig. 53. Once again, a very good agreement is obtained between simulation results and experimental data. Under the assumptions of the thermal detrapping model, this method can be straightforwardly applied to the calculation of the oxide charge release and threshold voltage recovery.

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Trapped charge (nC)

10 Irradiation +5V TSC bias -10V

1 Simulation Experiment

0.1 0.1

1 Dose [Mrad(SiO2)]

10

Figure 53. Simulated TSC charge on a 45 nm hard oxide MOS capacitor (TSC bias -10V), as a function of total dose [Pail-98].

B. Thick oxide We have also simulated a MOS capacitor structure having a 350 nm thick thermal oxide, representing a Field Oxide (see chapter 9). This thick soft oxide has a different radiation response than the thin hard oxide of the previous section. This difference is accounted for by means of a different trap energy distribution. This energy distribution was taken from experimental data [Pail-95c], [Pail-98], and is shown in fig. 54. 0.12 0.10

Soft oxide 350 nm

Q/Qtot

0.08 0.06 0.04 0.02 0.00 0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Energy (eV)

Figure 54. Energy distribution and discretization used for 350 nm thick soft oxides [Flee-92c].

This structure has been irradiated to a dose of 20 krad(SiO2) at +30V. Then a TSC experiment has been simulated on the irradiated structure (TSC bias -100V, ramp rate 0.1 °C/s). The comparison of experimental and simulated ITSC is plotted in fig. 55 as a function of temperature.

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20 350 nm, 20 krad@+30V TSC Bias -100V

ITSC (pA)

15

Experimental Simulation

10 5 0

0

50

100 150 200 250 300 350 400 Temperature (°C)

Figure 55. Simulated TSC on a 350 nm soft oxide MOS capacitor (TSC bias -100V), irradiated to 20 krad (irradiation bias +30V) [Pail-98].

A simulation code has been developed to calculate charge transport, trapping and detrapping properties in MOS structures. The results presented fit very well with experimental data on thermally stimulated currents. Further improvements of the models, such as tunnel assisted trapping phenomena for example, will enable the description of charge compensation effects in MOS structures. It will then be possible to predict the evolution of a component under its real operating conditions (i.e. for example long time irradiation at a low dose rate and variable temperature for space applications). This set of equations has been implemented in 1-D code [Cirba-95, Pail-98] under the name “TRAPPOXR v.3-CEA/CEM), and used for MOS purposes [Pail-98] and, with modification, for bipolar modeling [Grav-98]. It is presently implemented in 3-D under the name RADTRAPPOXTM v.5-CEA/ISE (see Appendix). From the experimental viewpoint, work is underway to get use of isochronal annealing along with TSC so as to obtain energy profiles [Chab-97a, Chab-97b, Saig-97, Flee-98, Flam-99] under specified circumstances. 6. TRAPPING AND LINKS WITH THE MANUFACTURING PROCESS 6.1.

DEFECTS

The trapping is described as the capture of a hole on a pre-existing defect called a precursor. The simplest example of a mechanism of this type is the breaking of a steady bond by the trapping of one hole.

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+

h+

+

Figure 56. An example of trap to hole: representation of the trapping of a positive charge on a oxygen vacancy bond

The oxide is generally described as an amorphous substance at least comprising defects such as strained Si-Si bonds, vacancies of oxygen in the form Si-Si and superoxided Si-O-O-Si bonds. This indicates the importance of the local stoichiometry. Indeed, oxygen intervenes in all aspects of the behavior of holes: trapping and transport (valence band edge), polaron regime (deformation of the Si-O-Si bonds by polarization), trapping (for example on oxygen vacancy SiSi). Fig. 57 shows an example of defect calculation using quantum chemistry codes. Such work allows understanding the configurations of defects (bond lengths and position) and energies levels associated with charge states.

a-SiO2 no defect

V0 neutral Oxygen Vacancy

V 0+ positively charged Oxygen Vacancy

Figure 57. Atomistic calculation of oxygen vacancy by the method of clusters using Density-Functional Theory (DMOL and Fast-Structure codes) [Cour-99].

The relaxation of bond lengths is clearly seen after trapping a positive charge (all dimensions in Angstroms). Beyond this oxygen vcancy, there exists a number of defects, intrinsic or extrinsic (Si-OH for example), more or less well known or measurable [Chu-90], [Warr-92], [Pail-95c]. If the process is not well controlled, the hardness level has is likely to be unstable (irreproducible) at one time. This is due of course to variations of the microstructure of the oxide and its interface with the silicon. Indeed, quantities at stake are very weak (with respect to the total number of bonds, the number of precursors NT is on the order of 10-4 in surface and 10-6 in volume). Moreover, these defect ratios are very sensitive to manufacturing variations, some of which are known (temperatures, anneal atmospheres), and others, probably unknown. It appears often during the change of machines, modifications of process (plasmas, rampings, various deposits sometimes well after the end of oxidation), and that these modifications apparently III-69

without influence on electrical transistor parameters or capacitors have an influence on the hardness level. It is necessary then to isolate the cause among many parameters, and to attempt to remedy there, or to demonstrate that it is necessary to renounce the modification.

Figure 58. Simple example of manufacturing process with erratic behavior before the institution of systematic process-control concerning the effects of X or gamma irradiation.

6.2.

SOME VIEWS ON RESPONSE OF THERMAL OXIDES MODELING

Always under hypotheses of chap. 3, three classes of factors influencing hardness can be indicated, as pictured below.

Figure 59. Basic trapping factors influencing hardness.

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6.2.1.

MANUFACTURING PROCESS OF THE THERMAL OXIDE

Success was been historically obtained over twenty five years ago by use of ultra-clean oxides, explained by the reduction of this precursor defects constituted by atoms or impurity ions [Hugh72]. Far more notable improvements have been obtained during this period by lowering the temperature of oxidation [Aubu-70], [Derb-75], [Dawe-76]. Many studies have then shown that it was in general necessary to also lower the temperature of post-oxidation anneal ([Schw-88], [Lera-89a] among others), and that steps of process were inter-dependent [Wino-85]. 6.2.2.

GATE OXIDE THICKNESS DOWNSCALING

It is well known that, in integrated circuits, a consequence of the Moore’s law is a gigantic reduction of the gate oxide thickness (reduced from 170 nm to less than 10 nm in 30 years) [SIA98]. As the oxide thickness is the most effective factor influencing the dose hardness, modern gate oxides take vast benefit of the downscaling, as illustrated in the following experimental curve. In principle, this gain is strongly observed in the low dose regime (tox2) and also, but in a lesser magnitude, in the saturation regime (tox1). Note that discrete components, often devoted to medium to high voltage application, escape the Moore’s law and therefore still remain potentially very sensitive to total-dose.

Figure 60. Straightforward influence of thickness downscaling [Lera-89a].

6.3. EMPIRICAL PROCESS ENGINEERING CURVES FOR THE THERMAL GATE OXIDE AND MODELING 6.3.1. CORRELATIONS CONCERNING OXIDATIONS AND ANNEALS Figure 61 shows examples of correlation between the alpha coefficient and various temperatures: - the temperature of oxidation (in the left chart, the anneal temperature is constant). - the maximal temperature attained by the SiO2/Si layer during the process (right chart). The nature of the gate is indicated as a parameter.

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Figure 61. Examples of empirical correlation curves. The left figure present typical rough data. The right figure is a compilation of tens of data published in the literature of the 70s and 80s, normalized to tox2 and interpreted by means of the trapping coefficient α [Lera-89a].

These correlations have to be considered as indications of trends, and not as absolute rules [Dawe-76, Wino-85, Schw-88, Conl-97]. A lot of factors interfere in fact in these complex processes, such as gas annealing durations, inducing thus great confusion in the spirit of engineers in charge of these processes! Without precise insights about the physical and technological mechanisms involved, the process of optimization is nothing but a succession of “try and test”, and this approach may often result in a series of expensive and disappointing adventures. 6.3.2.

FURNACE ANNEALS AND RAPID ANNEALS (RTA)

It is therefore known that for the classic oven anneals, the main effect is connected to the maximum temperature during the process. A more recent method of anneal, called “Rapid Thermal Anneal” (RTA), in which the heating is obtained by the exposure of the wafer to powerful halogen lamps. The duration of the exposure is reduced to some seconds or tens of seconds, against minutes or tens of minutes in a classic oven. Recent results show an analogous correlation between the temperature of the rapid anneal RTA and the variation of the threshold voltage ∆Vot [Flam-95b]. The figure 62 shows the ∆VT for NMOS transistors in the central part of wafers annealed to different temperatures by using two methods: (i) Classical oven anneal in nitrogen during 30 minutes (ii) Rapid Thermal Anneal during 10 seconds As shows figure 62, a threshold of radiation sensitivity appears between 975°C and 1025°C for the RTA anneal. The effect of threshold appears also for the classic anneals oven, at “low” temperature, as it has been found previously.

III-72

Average and "Max-Min" deviation of∆Vt (mV)

0 -100 -200 -300 -400 -500 -600 Furnace

-700 -800 800

RTA

850

900 950 1000 Anneal Temperature (°C)

1050

1100

Figure 62. ∆VT after 1 Mrad(SiO2), according to the temperature anneal for a NMOS transistor [Flam-95b].

6.4. SOME THEORIES ABOUT THE PROCESS ENGINEERING EMPIRICAL CURVES 6.4.1.

INTERPRETATION BY THE FLOW OF SIO2

Results show that the gate oxide hardening is a sensitive function of anneals temperatures. However, the comparison between the RTA and oven anneals shows that the temperature is not the unique parameter of this sensitivity. The duration is a second very influential parameter. To explain these phenomena mixing the temperature and the duration of anneals, one has researched key-parameters of the SiO2 material, that would allow us to understand the build-up of defects from the mechanics of layers. The first proposed parameters have been the constants of dilatation, Si and SiO2 elastic modulus and the viscosity of SiO2 [Eern-76]. This is the viscoelastic theory. The observation of effects linked to the thermal processing duration is coherent with characteristic time constants of the SiO2 flow [Eern-76, Lera-89a]. These time constants vary from some tens of seconds to several minutes for temperatures usually employed in anneals. More, the increase of the threshold of temperature observed for the RTA could be explained by the fact that in this case, the duration of anneal can become inferior to the characteristic time of the viscous flow, for temperatures under 975°C. The figure 63 shows the Arrhenius plot of the results obtained in [Flam-95b], compiled with results of [Win-85] and [Lera-89a] (to see also [Schw-88]).

III-73

100

RTA anneal Furnace anneal Normalized ∆Vt

After Ref. [3]

10

1 0.74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 0.9 0.92

1000/T (K)

Figure 63. Arrhenius plot of ∆VT after 1 Mrad(SiO2), versus the anneal temperature for NMOS transistor [Flam-95b].

We notice that the slope is similar for the three sets of data (nearly 3 eV). This slope, representative of energy of creation of defects is similar and independent of the type of anneals (either furnace or RTA). More, as processing (oxidation ovens, atmospheres of anneal, temperature, thickness of oxide, nature of the gate, etc.) and conditions of anneal (for example duration of the anneal), employed in the 70s [Eern-76], in the 80s [Wino-85] and in the 90s in this study [Flam-95] are very different, this suggests that this energy of creation could be an intrinsic property of the material SiO2, which tends to support the viscoelastic theory. However, it is noticeable that other activation energies (more exactly, enthalpy), has been reported, e.g. 1.5 eV only [Conl-97], but on a very simple process based on dry oxide. At that point, it might be noted that in fig. 61 the slope seems to be influenced by the entire process, so that it is likely that this simple parameter could depend also on many other features related to the process sequences. On a macroscopic scale, implied intrinsic properties are the mechanical constant (rheological) of SiO2 and Si (coefficients of dilatation, elastic modules of Young and Poisson, viscosity of SiO2). On the microscopic scale, the consequence of stress fields and flows have to be the generation of defects and strained bonds in the silica and at interface, which would be only partially annealed during the processing. Despite the ability of these theories of the 70s and 80s to explain remarkably well the range of value of the threshold in the temperature and the activation energy, they fundamentally fail to describe the involved microscopic mechanisms at the level of atomic bonds. Another reasoning has therefore been researched by authors in the last 10 years [Warr-94, Devi-95, (and Mathiot), Flam-95, Kak-89], based on the contrary on microscopic mechanisms of chemical nature such as the diffusion and the solubility of oxygen in the silicon. 6.4.2.

INTERPRETATION IN TERM OF EXO-DIFFUSION OF OXYGEN

Observe first of all that the layer of silicon oxide is confined between two layers of Si (substrate or polysilicon gate). This model is based on the observation that the solubility limit of oxygen interstitials at elevated temperature is not negligible: (102)

O

* Si

= 1.531021 exp ( −1. 03 eV / kT ) cm-3

and therefore, an effect of “gettering” can exist due to Fick’s law of diffusion for oxygen surface concentration at the Si/SiO2 interface. Silicon substrate being very thick, a certain amount of III-74

oxygen can penetrate more or less deeply into it, basically leaving oxygen vacancies in the oxide in a quantity determined by the temperature and the duration of the anneal. This should result in the build-up of oxygen vacancies on the silicon dioxide side of the interface, which are one of the defect precursors related to positive trapped charge [Lena-83], [Chu-90], [Devi-94], [Pail95-c]. If we consider this mechanism, the simplest resolution of Fick’s equation allows us to calculate the profile of O interstitials in the silicon substrate: (103)

[O]Si = [O]*Si erfc(x

2 D Si t

)

x is the abscissa in silicon taken from the Si/SiO2 interface

where:

t is the anneal time (in this simple model, ramping up and down temperature histories are not taken into account) O 22

* Si

=k O

* SiO 2

is the concentration of O in the oxide adjacent to the interface (≅5.

-3

10 cm ), k being the solubility segregation coefficient derived from (1). Dsi is the diffusion coefficient for O interstitials in Si, modeled as: (104) DSi = 0.17 exp( −2.54 eV / kT ) In order to evaluate the validity of these assumptions, one must first compare the density of traps revealed by irradiation and the quantity of the out-diffused oxygen. Let Nox be the density of oxygen vacancy in the oxide (cm-2) due to high temperature anneals. Let Voxy be the voltage shift developed at the MOS interface by the “oxygen vacancies”, in the case where they were all charged positively: (105) Voxy = - q Nox / Cox The calculated out-diffused concentration of oxygen is shown in fig. 64. Figure 64. Quantity of exodiffused oxygen.

Nox (1012 cm-2)

6

Furnace 30min 5

RTA 10s

4 3 2 1 0 800

850

900

950

1000

1050

1100

Anneal Temperature (°C)

To that purpose, we have simply strictly followed the calculation process pointed out [Warr-94], but applied to various RTA and furnace anneals conditions. The authors first calculate the outdiffused oxygen profile nox (cm-3): III-75

(106) nox ≈ O

* Si

( DSi / Dox )1/ 2 erfc − xSiO 2 / 2 ( Dox t )1/ 2

where x SiO 2 is the abscissa taken from the Si/SiO2 interface, and: (107) D Si = 0.17 exp ( −2. 54 eV / kT ) (108) D ox = 2. 6 exp ( −4. 7 eV / kT ) are the diffusivities (cm2.s-1) in silicon and oxide respectively. Then the integration of the profile over x SiO 2 gives Nox at a given time. One supposes that cooling down is instantaneous and does not cause oxygen back-diffusion into SiO2. Although the model is simple, this physical process can explain the difference between the two types of annealing. The model accounts for the two experimental key parameters, i.e. the temperature and time of the anneal. Furthermore, the rate limiting process is the O diffusion and the activation energy (2.54 eV) is compatible with the slope of Arrhenius plot (around 3 eV). To show that the model closely matches the temperature and time effects of post-oxidation anneal, we have calculated the corresponding voltage. Fig. 65 illustrates the ∆Vot shift after 1 Mrad(SiO2) and the calculated voltage induced by out-diffusion as function of anneal temperature. The shape of the predicted curves is in agreement with the experimental data. Differences in magnitude could be explained by the three following considerations (i) the predicted voltage Voxy is calculated by considering only positive charge traps, (ii) the radiation induced positive charge are not related one to one to oxygen vacancy precursors, and (iii) the dose level of the experimental data is not sufficient to fill up the available defect precursors. ∆Vot (V)

Figure 65. Comparison between predicted and experimental threshold voltage shift.

Voxy (V) 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 800

0 -1.6 -3.2 -4.8 -6.4 -8.0 -9.6 -11.2 -12.8 -14.4 -16.0

Experimental data Predicted data : RTA Furnace

850

900

950

1000

1050

1100

Anneal Temperature (°C)

7. INTERFACE STATES The equations of interface state generation are still a subject of debate. Consequently, it is not the goal of this course to address much of this matter, and the interested reader may refer to preceding Short Courses [Dres-98], or to review books [Ma-89]. However, a brief review will be made and parallel with charge trapping will be suggested. III-76

7.1.

CONSEQUENCES OF INTERFACE STATE BUILD-UP FOR ∆VTN AND ∆VTP

“Interface states” are interpreted to first order as missing (dangling) bonds between the silicon and the SiO2. These charges are so close to silicon (even belonging to the silicon in some sense) that they act as scattering centers for carriers moving in silicon (e.g. from source to drain). These states situated to the Si-SiO2 interface have energy levels situated in the forbidden band of the silicon, and the charge depends on the position of the surface potential with respect to the silicon bulk. The most interesting case occurs when the transistors are biased at or above threshold voltage. In this case, the interface states are filled in by carriers belonging to silicon, as depicted in the figure 66 below. During the functioning of the MOS transistor in conduction (beyond the threshold voltage), these states are charged negatively in the case of the NMOS with electron carriers channel, and positively in the case of the PMOS with hole channel. MOS N

MOS P

SiO2 Si

N

P

N

P

VIT > 0

N

P

VIT < 0

Figure 66. Second component ∆VIT of the drift of the due threshold voltage to the presence of interface states.

7.2.

CONSEQUENCE FOR MOBILITY REDUCTION IN SILICON

It has been recognized that mobility can be strongly affected by interface states. Let us recall that a direct consequence is the decrease of the current drive capability of the transistors. This effect is very detrimental to Power MOS transistors, as for instance, the ON resistance (RDSon) is affected. [Gall-84] developped a simple formula based on scattering of carriers in silicon by the surface charges [Sun-80], firstly depending on Qit, always proved valid since then [Zupa-93]. This model has been then extended to Qot by simply adding a supplementary term:

(109)

µ (D) µ ( D=0)

=

1 1 + α it . Q it (D) + α ots . Q ots (D)

with: 1) αit and αot having the dimension of a cross-section. 2) Q it the charge of the interface states (closely related at threshold voltage to the average Dit the interface state density by: Q it =∆Vit/Cox ≅ Dit .ΦB, where ΦB is the Fermi energy). 3) Q ots the portion of the oxide-trapped charge residing close to the Si/SiO2 interface. III-77

αit is nearly identical for N and P channels, for instance, αit= (0.8±0.2) 10-12 cm2 for NMOS [Gall-84] and (0.9±0.2) 10-12 cm2 for PMOS [Gall-85]. These values compare well with [Sext85]), determined as (0.7±0.13) 10-12 cm2. 7.3.

INTERFACE STATE BUILD-UP

Interface states generally manifest themselves about 100s after an instantaneous irradiation but some can appear only after 105 to 106 s (for a review, [Schw-94] can be referred to). Several models have been proposed to explain the generation of interface states: - Some authors suggest that hydrogen intervenes in the form of an ion [McLe-80] or neutral atom [Gris-85]. -

Others [Lai-83] associate this creation as a consequence of the detrapping of holes, which release energy when they reach the Si/SiO2 interface and “plunge” into the silicon valence band.

These mechanisms, in principle, have as a common origin the localization of carriers of electronic charge at a chemical bond. This can be understood if one considers that there is a parallel with what can be observed in gases and organic insulators (cf. radiolysis). The role of hydrogen has been suggested by [Reve-77], [Swen-78] and [McLe-80]. The main identified mechanism is the liberation of species linked to hydrogen, such as H0 or H+. Such mechanisms have been studied by [Brow-83, Brow-85, Gris-88], and confirmed by more recent authors ([Boes-88] and [Saks-89, Saks-90, Saks-91, Mrst-91, Stah-93]). The figure 67, from [Gris-88], gives a complete picture of the known or suggested electrical and chemical radiationinduced processes in the hydrogen model of interface-trap formation. Based on this picture, data have been interpreted by H+ drift, being the likely rate-limiting step in a two-stage process [Saks89]. Based on these results, [Shan-90] proposed a hole-trapping/hydrogen transport (HT)2 model-involving hole trapping and subsequent near-interfacial H+ release, transport, and reaction at the interface-as a possible explanation of ∆Vit buildup in polysilicon- and metal-gate transistors. Anyway, these model are difficult to quantify, because of the difficulty to measure the amount of hydrogen present and the various forms it can take. This, along with the exact model of hydrogen drift or diffusion, is up to now a great obstacle of numerical implementation in codes, whereas the modeling of hole trapping is much more advanced. The concern of modeling in the surface oxide of bipolar transistors may incite evolution in this domain [Witz98] (see next chapter).

III-78

Figure 67. Diagram of electronic and chemical processes induced by radiations in MOS structures of SiO2 and its interface with silicon [Gris-88].

Hydrogen ions liberated in the oxide during the irradiation can migrate to the Si/SiO2 interface, where they can react and form interface traps. These two types of defects, traps with positive charge in the oxide and interface traps, cause degradation of electrical parameters of elementary transistors. As a summary, a parallel is drawn in table 8 between phenomena where carriers are electrical charges only and those where the agent is a chemical species: Radiation Fluxes RF Absorbed Energy / Dose Profile Free Carriers Yield Function Y(E) Charge Separation, Photocurrent at Electrodes CSPE Charge Imbalance CImb Imbalanced Charge Branch Drift, Self-Trapping, Transient De-Trapping Shallow/Deep Trapping Thermal Detrapping and Drift Tunneling Neutralisation Carrier Dipoles Border Traps Effects Swiched Oxide-Trapped Charge

Table 8.

DSTTDT SDT TDD TN CD BTE SOTC

AEDP FCYF

Unstable Chemical Species Branch Carrier Localization at Weak Bond of Foreign Atoms in bulk SiO2 CLAB (i.e. Si-H, Si-Si, Si-OH, …) X-Species Release X-SR (e.g. X = H, or H+, or other) X Drift X-D (possibly polaronic if X=H+ ) X-X’ Reaction at SiO2/Si Interface XX’RI

Vot Oxide-Trapped Branch oxide traps

Vit Interface-Trapped Branch interface states

slow exchange with silicon or quasi-stable charge

reversible and fast exchange with silicon

Parallel between trapped charge and interface-states build-up.

Two chains of radiation processes can exist in SiO2, having in common the transport and transformation of a species X released by radiation in the volume of SiO2, then interacting, mostly transformed (or trapped) at or near an interface to produce the resulting degradation III-79

expressed by an electrically-active species Q. For the purpose of modeling, the issue is to find out the different channels of release and interaction, and chain equations together in a coherent manner with the correct parameters. The table 9 depicts a framework in the case of processes relevant to first-order kinetics. 1) Release of a Species X in a Given Volume X = G.Y.D’ G = conversion factor between the absorbed dose D and the species X 2) Transport towards an active Site Current Flux J = F.X in the coefficient F : drift-diffusion, CTRW, multiple trapping-detrapping, etc 3) Formation of an electrically-active species Reaction forward With R = trapping coefficient Reaction backward With R’= detrapping coefficient

Table 9.

Q dQ/dt=(N-Q).R.X -Q.R’.Z Z=e0 .exp-Ea/kt, Z=Tunneling probability, etc

Types of quantities and equations for release and transformation of species in MOS structures.

III-80

8. BIPOLAR TRANSISTORS The primary effect of radiation exposure on bipolar transistor is the reduction of gain, with larger degradation at low operating currents. Figure 68 displays bipolar NPN characteristics. One sees that for a reduction of the maximum current gain of near 50% (approximately Vbe=0.7-0.8V or Ic=10-5-10-3 A), the reduction being much worse at lower current levels. Globally, it is observed an inverse dependence of gain versus dose (exponent m with m<1), but with a proportionality factor depending largely on the drain current (formula on fig. 69). Gain degradation comes from minority carrier recombination at the base interface in the separation or passivation oxide (base/emitter spacer). If positive charge is trapped in this oxide, it induces depletion or inversion at the surface of the base (P-type for a NPN), and it results in a diffusion of minority carrier current toward the depleted zone and recombination in this zone. Recent works [Nowl-93] have shown that this recombination causes an increase in base current Ib, proportional to exp (αNox2) where Nox is the total net charge trapped in the spacer oxide (in the notations of this Author, Nox= Qot + Qit). This increase in Ib then results in the reduction of the BJT gain (Ic/Ib).

Vbe (V)

Figure 68. Typical degradation of the gain in a bipolar transistor [Nowl-92].

Figure 69. Diagram of the recombination currents of minority carriers causing the degradation of the gain and simple law versus dose.

In addition to this pure electrostatic effect of controling surface potential by the oxide charge Nox, interface states play also the role of recombination centers. As the total charge Nox shifts the surface potential ϕs, the recombination current changes exponentially, in accordance with the Shockley-Read-Hall statistics [Emil-96]. The expression of the base current can be obtained, by recalling the Poisson’s law in the depleted base of (assumed) constant doping level NA. By considering that the depletion is entirely caused by the radiation-induced charge Nox, we can express the surface potential ϕs with respect to Nox and NA (in cm-2 and cm-3): 2

(110) ϕ s =

q N ox 2 ε Si N A

This gives finally give, with Wdep the surface depletion width [Pers-97]: III-81

I 1 (111) ∆  = ∆ b β  Ic

VBE

N

2

N

2

ox ox  ∆I b n i e k T 2 εSi kT N A 2 εSi kT N A  = = q v TH N it (ϕ s ) σ st Wdep e ∝ Wdep e NA Ic  Ic

2

For PNP transistors, phenomena in the oxide are similar, producing generally a net positive charge Nox, but electric fields are inverted in the oxide. Another major dirrerence comes from the doping type of the base itself: it ensues that the net positive charge Nox accumulates the N type base instead of depleting it. [Pers-97] noted that the expression of the recombination current is different for a PNP transistor, and this dependence should be in 1/Nox2 instead of exp (α Nox2). In vertical NPN and PNP, most of the recombination current flows from the base to the perimeter of the emitter junction, as reviewed in [Mess-92] and illustrated, e.g. in [Nowl-92] and [Flam94]. In this case, the variation of the reciprocal current gain can be expressed as follows:  1  ∆ (s Wdep ) Pe W (112) ∆  = Db Ae β where: s Ae Pe W Wdep Db

recombination velocity (function of Nox as noted above) emitter area emitter perimeter base width surface depletion width base diffusion constant

In this formula, s and Wdep are function of dose in a complex manner, because both the trapping properties of the base-emitter spacer insulator and the doping profile in the base are involved. For modeling this behavior, pioneering work has been done by numerically asserting the effects of the trapped charges in the depletion layer by [Schr-96] (aiming at calculating the effective s(D) [Kosi-94] and Wdep(D) as a function of Nox for a given doping profile). A second step has been to model and compute the trapped charge itself and the interface states component, which are a complex function of time and dose-rate [Grav-98]. A third effect, attributed to hydrogen release by irradiation, affecting the boron doping level, has recently been noticed and should probably be taken into account [Witz-98]. As a consequence of these recent observations, it is likely that modeling of radiation effects in base-emitter spacer oxide requires to take into account not only electron and holes, but three charge carriers: e, h, and H under the form of H+, their motion, trapping, neutralization and chemical reactions producing interface states and boron dopant passivation. Note that due to the small electric field applied by the VBE bias, most of the charge and proton motion is driven by diffusion and the effect of the fringing fields [Pers-97] established by the built-in base-emitter voltage and the depletion layer. Consequently, codes must be self-consistent with Poisson’s equation. Such work is only at its beginning, and, consequently, complete modeling of effects in bipolar transistors is not sufficiently mature to be presented at the present time. Anyway, a sure thing derived from this formula is that the degradation is very sensitive to the Pe/Ae ratio, as pointed out in [Peas-74] [Mess-92]. In one hand, transistors are traditionally designed to maximize perimeter-to-area ratio, in order to reduce the base spreading resistance and obtain higher transition frequency and reduce emitter crowding. But on the other hand, this III-82

also increases total-dose sensitivity, the effect is particularly important in interdigitated transistors. This explain why it not uncommon to observe bipolar transistors significantly affected by doses in the range of 100 kilorad(SiO2), and sometimes 10 kilorad(SiO2) only. At larger doses, collector-emitter leakage currents can also possibly appear for very vulnerable NPN transistors. Because of the possible appearance of a surface channel between the collector and a part of the basis, the avalanche voltage VCE0 can decrease for NPN transistors. The above discussions primarily deal with vertical transistors, which are ordinarily the most robust. Additionally, it must be noted that commercial (COTS) analog integrated circuits commonly use lateral transistors or substrate PNP transistors (those working with collector built at the surface of silicon like the drain of a MOS transistor) [Emil-96]. These parasitic transistors are generally much more vulnerable, due to the large surface of base exposed to insulator [Schm95] [Schm-96], and, due to this enhanced vulnerability, may present large sensitivity to dose-rate and time-related effects [Witz-96]. Improvements can be realized by work on the oxide “spacer”. The sensitivity of spacer oxides formed with transition to medium to thick has been pointed out [Johns-96]. On the other hand, there is a tendency to use trenches. Recent developments in the bipolar technology concern the bipolar with epitaxial base SiGe (Bipolar Transistor Heterojunction (HBT) [Hara-95]). This process has as potential the improvement of performances in transition frequency, so as to compete with GaAs transistor in some extent, with as favorable asset the compatibility of manufacturing lines with silicon ones due to common equipment and compatible chemistry. It has been shown that such devices present remarkable behavior after radiation with degradation of gain less than 20% after total dose exposure to 10 Mrad [Babc-95]. For this type of device, the cause of the improvement resides in the oxide/nitride spacer and a strong doping level under the surface of the base region. 9. LEAKAGE CURRENTS: VISIBLE AND HIDDEN TRANSISTORS Parasitic transistors exist in all technology processes (Bipolar or CMOS). Trapped charges can turn-on these parasitic devices, causing leakage paths and inversion or accumulation channels. These channels act as MOS transistors and connect active transistors with each other or with supply lines, causing leakage currents. These leakage currents can cause the device to malfunction or simply degrade, with consequences on the system performance. In fig. 70, let us first describe the simple case of a CMOS with LOCOS.

III-83

Figure 70. Cross section of an actual CMOS technology (FACTTM JAN of NSC [Mahe-94].

The figure 71 depicts very classical location of leakage currents in this kind of planar process.

Figure 71. Some MOS parasitic transistors in bulk silicon structures

Basically a 2D view (fig. 72) helps to differentiate between Edge-Field Oxides (E-FOX) and the two main types of Planar-Field Oxides (P-FOX). This essential topological difference helps to define a modeling strategy. Edge transistors share their gate with the main transistor, wgereas planar Field-Oxide transistors occur when a supply or bit line is deposited over a P-type region comprising two N-type zones (drain, N-well contact, guard-band, etc). In any case, an electron leakage channel occurs when the voltage applied on this parasitic gate approaches or passes over the threshold voltage of this parasitic transistor. III-84

Planar FO X in ter-tra n sisto rs

Ed g e FO X

N+

N+

+ + +

N+

P-substrate

N+

+ + + + + + +

N+

Planar FO X tran sisto r/w e ll

P+

P+

Planar FO X in te r-tra n sistors

Ed g e FO X

N+

P+

+ + +

N+

N-well

N+

N+

+ + + + + + +

P-well

Planar FO X transistor/w e ll

P+

P+

N-substrate

Trapped charge

Trapped charge Parasitic leakage channel

Parasitic leakage channel

Figure 72. Decomposition of parasitics into edge and planar topology of oxides. Two examples of situations in N-well and P-well technologies, among many other possible.

9.1.

EDGE FIELD OXIDES (E-FOX) MODELING

Drain Current (A)

The section is devoted to total-dose modeling with special attention paid to the subtle effects encountered in the actual devices, i.e. the geometry and internal field developed by the trapped charges. Classical models will be reviewed first, and adapted to actual 1D, 2D or even 3D situations, such as encountered in parasitic transistors responsible for leakage. Field oxides, edge parasitics and SOI parasitics will be used as examples. Fig. 73 describes the basic characteristics of leagage current, with build-up with dose and, very commonly, post-irradiation slow partial recovery.

10m 1m PMOS 100µ Transistor 10µ 1µ 100n 10n 1n 100p 10p 1p 100f 10f -5 -4 -3 -2

NMOS Transistor Before Irradiation After 10krad(SiO ) 2

After 30krad(SiO ) 2

After 265H Storage

-1

0

1

2

3

4

5

Gate Voltage (V) Figure 73. Typical features of parasitic leakage in a 0.35 µm technology irradiated under 3.3 Volts [Chab97a].

9.1.1.

LATERAL THICK OXIDES: LOCOS TYPE

The “LOCOS bird’s beak transistor” gives an example of lateral structure. It can be depicted as a parasitic thick oxide transistor in parallel with the principal transistor with a sharing gate. In the classic LOCOS, the “beak” is the fine part, while the “head” of the bird is the thicker section of the LOCOS [Kooi-91].

Parasitic MOS transistors

Leakage path

Gate

Leakage path Field oxide

Gate Bird's beak Positive trapped charge

P-type Substrate

Figure 74. Illustration of parasitic transistors of lateral and field oxide, showing leakage paths [Flam-98].

An “knee” in the characteristic log Ids-Vgs reveals this effect. The substhreshold value of the current can be also raised up to a tenth of the primary current of the transistor after the onset of conduction.

Figure 75. Principle of a log Ids-Vgs characteristic for a transistor affected by a lateral leakage.

III-86

9.1.2. EXAMPLE OF CONSEQUENCES OF LEAKAGE FOR CIRCUITS Two main consequences are observed: -

In complex circuits, due to the large number of transistors, the total supply current rapidly exceed limits, and internal voltage drops occurs due to Ohmic loss in supply lines. Before this extremity, signal can be corrupted and margin exceeded. And even before, integrity of sensitive internal analog function such as amplifiers and comparators can be exceeded.

-

In simple circuits, input leakage current can exceed data recommended by the product sheet, being a cause of part rejection.

The two following figures show the behavior of the same type of circuits (DRAM from 4 to 64 megabytes). It is remarkable that the loss of functionality remains in the same range of dose (10 to 30 kilorads), despite a decade of time and three generations have passed between them. This will be discussed at the end of this chapter. Meanwhile, we will go further into modeling so as to prepare this discussion.

Figure 76. Correlation of failure and leakage current in 4 Mb DRAMs (TMS44100DM) (After L. Adam, R. Harboe-Sorensen et al., ESA group, radiation Summary Sheet 5 and 9, 1991).

III-87

Figure 77. Correlation of failure and leakage current in 64 Mb DRAMs [Shaw-95].

Leakage currents strikingly escape the Moore’s law, i.e. they still are susceptible to appear in the range 5-20 kilorad in CMOS technologies, despite the considerable evolution these last 20 years. 9.1.3. CONCEPTUAL MODELING OF EDGE TRANSISTORS AND EXPERIMENTS More specifically, parasitic transistor can be viewed as a series of transistors in parallel. It can be shown [Flam-98], that the response of these elementary transistors can be deconvolved by considering the ∆Vt shift of each level of current: 7

Id (log)

Vt (V)

Fixed Drain Currents 1.00E-11 I

6

Before Irradiation After Irradiation

5

1.00E-10 1.00E-09

4

Thin Transistor

1.00E-08

3

Vt αeox

2

Thin Transistor y = -0.2854x + 4.44

1.00E-07 1.00E-06

2

R = 0.9901

1

Dose (krad)

0 0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

-1 -2

Thick Transistor

-3 -4 -5

∆Vot α e²ox

Vg

-6

Thick Transistor y = -0.6446x + 6.0741 R2 = 0.9918

∆Vt≈∆Vot=-α.Ω.f(E).Y(E).D.e²ox

-7

Figure 78. Method for obtaining the elementary transistors of an edge structure [Flam-98].

It is important to notice that leakage current generally evolves in time, as typified in this sequence of experiments (fig. 78).

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Room Temperature Evolution 10-2

Irradiation

Drain Current Id (A)

10-2 Before Irradiation From 10 to 20 krad by 1krad steps

Drain Current Id (A)

10-3

After Irradiation After half decades in time

10-3

10-4 10-5

10-4

(t from 103 to 3.106s) Before Irradiation

10-5 10-6 10-7 10-8

103s 3.103s 104s 3.104s

10-9 10-10

105s

3.10 5s 106s 3.10 6s

10-11

10-6

-5

20 krad

10-7

-4

-3

-1

0

1

Gate Voltage Vg (V)

15 krad

10-8

-2

10-9

Progressive Elevation of Temperature

Before 10 krad Irradiation

10-10 10-11 -5

-4

-3

-2

-1

0

1

Gate Voltage Vg (V)

10-2 After 1x & 2x5' at T (T from RT to 300°C by 25°C steps) Before Irradiation

Drain Current Id (A)

10-3 10-4 10-5 10-6 10-7 10-8 10-9

1x5' 125°C

2x5' 100°C

10-10

2x5' 125°C 1x5' 150°C

10-11 -5

-4

-3

-2

-1

0

1

Gate Voltage Vg (V)

Figure 79. As for gate transistors, leakage lateral is capable of time-dependence or thermally-activated recovery [Chab-97a].

As for gate transistors, this recovery can be modeled by considering the equations and parameters of the thermal detrapping for each of the elementary lateral transistors. By relating the current level and the lateral position, the energy spectrum of traps can be extracted from isochronal anneals [Chab-97a]. The reader is invited to look further in this reference. 9.1.4.

NUMERICAL MODELING OF EDGE LEAKAGE TRANSISTORS

We follow here the method exposed in [Briss-96], applied to LOCOS (however, this method can be generalized to any edge structure). elementary transistor

y

tox(x)

Gate

x u Silicon

Figure 80. 2D-representation into a continuum of transistors [Bris-96].

The simulated structure is decomposed into elementary transistors (ashed region), delimited by the field lines. Here, tox(x) is computed from the elementary oxide capacitance Cox(x), and can be interpreted as the length of the field lines in the bird's beak of a non-irradiated device (fig. 80). The function tox(x) is then related to the bird's beak shape. Cox(x) is calculated by the 2D code with the Gauss' along the field lines [Esco-95b]. III-89

Vox(x) is the oxide voltage drop. Qsc(x) is the net charge per unit area in the silicon layer. Qsc(x) is given by:

(113)

⌠ t ox Qox ( x ) =  ⌡0

( x)

t ox ( x ) − u p t ( x , u) du t ox ( x )

where u is the distance along the field line at the abscissa x doping at the abscissa x. Using these method and a 2D-version of the TRAPPOXR code (version 2.0 issued with University of Montpellier under the name “ACCESS” [Esco-95a], [Esco-95b]), we obtain the threshold voltage at the abscissa x, and then, integrating over all the elementary transistors, a good description of the edge leakage current can be obtained [Bris-96]:

10-3 10-4 10-5

50 krad

10-7

40 krad

10-8

I

DS

(A)

10-6

10-9

Simulation Experiment

30 krad 20 krad

10-10 10-11

10 krad

10-12 10-13 -4

-2

0

V

GS

2

4

(V)

Figure 81. Variations of IDS as a function of VGS. The device has been irradiated at VGS=5 V.

Additionally, this simulation has obtained new insights. As trapping depends both on the nonrecombination yield Y(E) and on the oxide thickness, a maximum is reached at a point where the electric field lines are the longest (fig. 83). It finally gives access to the lateral threshold voltage versus the position on the edge (fig. 84).

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Bird's beak region

1.0

Thick oxide

Gate oxide

ox

Q (1012 cm-2)

1.5

0.5

0.0 0.0

0.5

1.0

1.5

2.0

2.5

3.0

x (µm)

Figure 82. Simulated Qot(x) at 50 krad with VGS=5 V during irradiation [Briss-96]. Bird's beak region 0.8

0.5

0.7

Y(E) t

0.4

ox

Thick oxide

Gate oxide

0.2

0.4

ox

0.3 0.5

t (nm)

Y(E)

0.6

0.1

0.3 0.2

0.0

0.0

0.5

1.0

1.5 x (µm)

2.0

2.5

3.0

Figure 83. Variation of Y(E) and tox(x) along the Si / SiO2 interface [Bris-96].

15

0 krad

10

10 krad 20 krad

5

T

V (V)

Bird's beak region

30 krad

0

40 krad -5 -10 -15 0.0

50 krad Gate oxide 0.5

1.0

Field oxide 1.5

2.0

2.5

x (µm)

Figure 84. Evolution of the threshold voltage along the interface before and after irradiation [Briss-96].

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Bird's beak region 100

100 krad

10-1

50 krad 40 krad

10-2 10-3

30 krad

10-4

I

D0

(µA/µm)

101

10-5 10-6

Gate oxide

Field oxide

10-7 10-8

0.0

0.5

1.0

1.5

2.0

2.5

x (µm)

Figure 85. Evolution of ID0(x) (IDS(x) at VGS = 0 V and VDS = 5 V) along the interface after irradiation [ibidem].

9.1.5.

TRENDS OF SUPPLY VOLTAGE DURING IRRADIATION

The use of simulation can also be exploited to understand the influence of the decrease of supply voltage on dose hardness. For this analysis, the modeling exposed above is calibrated at 5 V and applied at decreasing gate voltages:

10-5

10-7

Simulation : V =5V

10-8

V =3V

10-9

V =1V

10-10

V =0V

10-11

Experiment : V =5V

I

D0

(A)

10-6

GS GS GS GS

10-12 10-13 101

GS

102

103

Dose (krad) Figure 86. Simulated ID0 vs dose for VGS=0 V to 5 V during irradiation. Experimental results are also plotted, with open symbols [Bris-96].

At a given dose, the VGS bias during irradiation has an important effect on ID0. Since the electric field in the oxide decreases when VGS decreases, the probability of initial recombination 1 - Y(E) of the generated electron-hole pairs increases. Consequently, a lower density of holes is trapped in the oxide during irradiation. The leakage current appears at a higher dose when VGS is lower. The hardening for low voltage, low power technologies should be easier to optimize than for 5volt technologies thanks to the lower supply voltage. III-92

This can be compared to data originating from global leakage of commercial parts, i.e. 54AC series of National Semiconductors fabricated using the FACTTM JAN process [Mahe-94]. The trend is verified between 5V and 3.3V.

Figure 87. Supply stand-by current of 54AC circuits in FACTTM technology [Mahe-94].

9.1.6.

OTHER TYPES OF EDGE OXIDES

A part of the commercial semiconductor market is driven by need of best electrical performances, obtained for always lower power supply consumption, and that to a lesser cost for the electrical functions. The new generations of components need to allow smaller characteristic dimensions, higher integration levels and reduced defect densities. As commercial integrated circuit technologies continue to advance, sensitivities to radiation tend to evolve, unpredictably. For example, LOCOS is being replaced by more compact isolation as trenches.

Figure 88. Two leakage paths in a trench isolation technology [Shan-98].

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Figure 89. Electric field distribution in an example of trench lateral isolation [Shan-98].

In the modeling work of [Shan-98], two parasitic transistors are identified (fig. 88), resembling the LOCOS case. As in LOCOS technologies, the most active is the edge transistor. At the difference of LOCOS, the maximum of trapping occurs where the oxide thickness is at its smallest, i.e. at the corner of the trench. It is also the place where the electric field is at its maximum due to the field line fringing (fig. 89). 9.2.

PLANAR ISOLATION OXIDES (P-FOX)

Planar Field Oxides (P-FOX) are topologically and perhaps physically different from lateral oxides. They are fundamentally thick insulators with a constant thickness, and their role is to separate lines of interconnections (poly, metal) of the surface of silicon. Hereafter is shown an example for the case of the CMOS technology.

Figure 90. Illustration of different parasitic “Planar Field Oxide transistors” in a 2-metal layer technology.

The vulnerability of a planar technology to the field oxide leakage comes from the possibility of surface inversion of the silicon, allowing charge induced conducting paths between sources or drain of transistors (adjacent transistor most of the time) or wells of appropriate type of doping [Adam-76]. Also The inversion is caused by charges trapped in the thick field oxide. As trapped charges are mostly positive when it concerns thermal silicon oxide, the surface of the silicon enriches always in electrons, so that leakage is established between NMOS transistors or NPN bipolar. The parasitic structure can be considered as a field effect transistor with a “virtual gate” and a threshold voltage can be defined by analogy with real transistors. Leakage currents in trenches belong also to this category, connecting surfaces via the bottom of the trench [Raym92], regardless of CMOS or bipolar technologies, regardless the trench is filled by polysilicon of an insulator. The situation is worsened when a interconnect line exists above this leakage path, because it acts a real gate possibly biased at positive voltage and then can increase the leakage current. These effects are measurable by designing “Field-Oxide” transistors with a dedicated control gate or FOXFET [Dawe-77], [Oldh-87].

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9.3.

THE CASE OF LEAKAGE IN BIPOLAR TECHNOLOGIES

Furthermore, in bipolar integrated technologies, parasitic “Field Oxide” transistors can exist, and create leakage between adjacent collectors of NPN transistor as for source or drains or wells of MOS technologies. For example, TTL input protection arrays support a recessed Field Oxide which is a source of leakage in the range of 10 kilorad(SiO2). These problems have been analyzed in detail ([Peas-85] and more recent works of the same team, and [Pers-92]). Solutions reside there again in the “channel stops” or “hardened field oxides”. Another radical solution resides in the lateral dielectric insulation, the modern version of which uses trenches [Enlo-89, Raym-92]. However, this author shows it can again exist a parasitic transistor located in the bottom of the trench, that can be avoided by using a bottom isolator as in SOI technology to achieve maximum hardening [Plat-88, Flam-95]. 9.4. CONSEQUENCES OF LEAKAGE CURRENTS FOR CMOS CIRCUITS AND PERSPECTIVES LINKED TO PROGRESS OF THE INTEGRATION These parasitic channels can be extremely numerous in complex circuits because there exist a great number of topological situations where NMOS transistors are facing in such a way that they can be connected and also are possibly N wells or well plugs. The voltage of the interconnection lines can play a great role because, in the worse-case, it can influence the parasitic structure by polarizing it positively. This line voltage can be distributed in an unpredictable or variable manner during the irradiation, because it results from the status of variable logic levels. Parasitic leakage paths can affect complex circuits above a certain level of dose consequently and become unpredictable. One sees therefore the fundamental role that the parasitic leakage currents play in modern integrated technologies, while the effects related to gate oxides tend to be relatively less important. This is due to the fact that progress of the integration leads to a strong diminution of the thickness of the gate oxide, and consequently, for a given dose, threshold voltages of the main transistor decrease strongly because of the decrease in radiation-induced charge trapping with the “square” of the thickness (in first approximation, cf. supra) [SIA-98], [John-98]. On the contrary, lateral transistor leakage does not decrease with the same factor, as the lateral oxide does not scale with the same roadmap and those due to parasitic “field” transistors not more, since the thickness of the field insulator of tend to decrease only in well lesser proportions (e.g., [Shaw-95] reports 340 nm for 16 Mb DRAM of three manufacturers and 240 nm for 64 Mb DRAM). And, LOCOS is now being abandoned, even in its modified “encapsulated” more abrupt version when evolving from 0.25 µm to below [John-98]. With the use of Shallow Trenches Isolation (STI), new problems arise, notably related to doping loss, electric field enhancement due to fringing and control of the shape at corner [Shan-98]. More, progresses of the integration increase strongly the number of transistors, and consequently the global leakage current at the circuit level tends to increase. On the other hand, supply voltage of core logic circuits will go on decreasing, from 3.3 V (1995) to 1.8 V (1999) and below 1 V (circa 2005). At this level, the applied voltages, the space charge voltage due to the trapped charges and the built-in potentials (eg. Φms) will become on the same order of magnitude in the lateral thick oxides. This is the reason why the analysis of radiation effects will require self-consistent models, able to take field-collapse and field-enhancement into account, and numerical modeling will probably become mandatory. This is the reason why we III-95

stress all these points in this Course. 10. SOI TECHNOLOGIES Silicon On insulator (SOI) technology is an efficient method that aims to prevent or reduce parasitic couplings between transistors and between data or supply lines. It consists in separating transistors by using insulating layers underneath and almost always around transistors. It is envisioned by SIA as a credible technology for low-power, low-voltage CMOS technology [SIA-98], and is likely to be introduced in mass production. As will be seen, SOI present some advantages for total dose hardness, as leakage between transistors is avoided, but at the same time can be inherently prone to radiation vulnerability due to leakage within the transistor surfaces itself. First recall that all the SOI variants have in common to use a specific substrate, which can be sapphire with epitaxied silicon film (Silicon-On-Sapphire) or a thin silicon dioxide film, topped with a silicon layer (specifically refered to by the community as “SOI SOI technologies have now a long and complex history, dating of the early times of microelectronics (for reviews on SOI, see [Cris-95, Coli-97]. In the latter case, the silicon dioxide is called “buried oxide (BOX). In this spirit, it is natural to refer the gate silicon dioxide

gate

source

drain

substrate

Figure 91. Source-Drain cross-section of a SOI structure ready for simulation.

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10.1.

PRINCIPLES OF SOI TECHNOLOGIES

In SOI technologies, the unnecessary silicon outside transistors is etched or converted in SiO2 by thermal oxidation. In the Mesa variant, the useless silicon between transistors is eliminated or dissolved. However, a deposited insulator for the purpose of planarization can optionally refill this span between Mesa. In the LOCOS SOI, it is locally oxidized until to reach the underlying buried oxide (BOX). Trench isolation performs as in standard bulk silicon technologies.

Figure 92. Fundamental SOI structures compared to corresponding structures in bulk silicon.

Usually, bulk silicon technologies are converted into SOI as can be imagined from fig. 92 [Plat88, Lera-88a, Lera-88b, Lera-99a]. By using SOI, most PN junctions are converted in dielectric isolation and leakage paths attributed to parasitic field transistors in bulk silicon technologies are automatically avoided. Moreover, the removal of the lateral silicon around transistors allows the complete isolation of paths of surface leakage. Therefore, a substantial gain is obtained since transistors can be manufactured in a simpler manner and placed closer to each other, giving higher packing density. In addition, latch-up of transistors is completely eliminated. 10.2.

THE THREE TYPES OF SOI TECHNOLOGIES

SOI technologies exhibit different types of structures, mostly differing by thickness of the active silicon film.

III-97

Bulk

Thick-Film SOI

Thin-Film SOI

Figure 93. Types of SOI technologies compared to bulk silicon.

-

For transistors processed on a thick silicon (e.g. tSi > 1µm) substrate (“bulk-like technologies”), no effect of parasitic buried transistor with ionizing dose is observed. In this case the hardness of an SOI technology is identical to bulk technology since buried oxide is moved away from Drain/Source [Davi-85, Plat-88, Flam-93, Flam-94].

-

For technology processed on relatively thin or intermediate-thin silicon (tSi ~ 2000 Å), devices operate in partial depletion, and coupling effects with buried transistor are evolving with ionizing dose. This coupling with the effect of field of charge then trapped in the buried oxide obliges us to take into account the hardening of this type of oxide [Lera-85].

-

Transistors manufactured on very thin silicon (tSi ~ 800 Å or less) work in total depletion regime, and this mode is directly controlled by the electric field created by charges which are present in the buried oxide. Thus, the behavior of the buried oxide is of extreme importance, especially for applications where high ionizing dose level is encountered [Ferl-96].

The total dose hardness of an SOI technology depends primarily on the radiation response of the same kinds of oxides as in bulk technologies: gate oxide and lateral isolation. This lateral isolation can be LOCOS or Trench, as in bulk silicon. Another system of lateral isolation specific to SOI is Mesa, which can be view as a Trench without refill. And finally, the ionizing dose response of MOS/SOI transistors can also depends on Buried Oxide, as is descibed in the following subsection. 10.3.

PARASITICS IN A THIN-FILM SOI TECHNOLOGY

Once a SOI structure is irradiated, charge trapping in the buried oxide gives birth to a parasitic effect, called “back parasitic transistor” as represented in fig. 93. A leakage current is usually observed in N-type MOS transistors, due to an electron conduction channel, which shows that the trapped charge is overall positive.

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Polysilicon gate Gate oxide

N+ diffusion LOCOS Back conduction Buried oxide Silicon substrate

Figure 94. Illustration of a radiation-induced back transistor in a SOI structure (after [Ferl-96, Flam-95c]).

Charge trapping not only generates a back-gate FET effect but also a lateral FET effect and often also a parasitic bipolar transistor effect. The improvement brought about by the SOI technology over bulk CMOS technology is that these parasitic structures are located in the silicon island instead of being distributed in the bulk or at the surface of the silicon chip. On the other hand, as noted above, a new parasitic FET transistor appears due to the buried oxide, the underlying substrate acting as a back gate.

Figure 95. Illustration of parasitic elements in a MOS/SOI or MOS/SOS transistor a) The five regions of transistor b) The corresponding parasitic elements [Lera-88b]

10.4.

MODELING THE TRAPPED CHARGE IN SOI DEVICES

In the following, is presented the application of the modeling equations of chapter 3 to the realistic situation of a NMOS transistor on SOI, with the use of codes computing selfconsistently the charges, currents and the electric field. Two kinds of modeling have been presented up to know. A first kind uses the standard codes, by supposing a trapped charge distribution at the silicon surface. This allows useful insights, because the functioning of the silicon part of the device can be evaluated [Ferl-98]. But the modeling is not complete and is based on charge amount and profile that must be supposed. Major improvement is allowed by the use of self-consistent codes, in which the trapped charge is computed by taking into account fluxes, field and traps in the surrounding oxides. Such codes, necessarily in 2 or 3D for SOI, exist only since recently. For example self-consistent modeling with code B has been presented for a lateral cross-section of the SOI structure [Mila98], realistically computing the back-channel induced MOS as a function of dose and of the body-tied-to-source (BTS) dimensions. In the following, as another application of numerical modeling, we present a study using the code A, on a typical thin-film partially-depleted SOI technology, with gate length of 0.5 µm and III-99

LDD feature. This study can be viewed as “orthogonal” to the [Mila-98], as it operates in another cross-section, orthogonal to the previous one. We aim at describing here the other cause of leakage in NMOS/SOI, i.e. the back-channel leakage current, whereas [Mila-98] described the edge-channel leakage current. In SOI, the “mechanical substrate”, i.e. the bulk silicon underlying the buried oxide, is connected to the chip case, and usually tied to ground. In other terms, back-gate is usually at zero Volt with respect to the source. This is typically a case where electric field is low (determined, for instance, by built-in potential between the two silicon facing each other, e.g. P-type for the N-channel MOS and P- type for the bulk silicon substrate). If drain is itself at zero voltage during irradiation, in effect, trapping is at minimum and usually no back-channel parasitic transistor appears. However, it has been recognized since the early times that the worst-case of irradiation occurs when the NMOS drain bias is at supply voltage (e.g. +5 V). In this situation, the back-MOS threshold voltage shifts significantly and the back-MOS transistor can be revealed and cause a major drain-source leakage current. The following set of figures verifies this hypothesis, by computing the electric field, the induced MOS current in the back-side of the silicon film, the trapped charge in the buried with the selfconsistent code A. These set of experiments reveals the field-collapse effect in the two-dimensional situation of the buried oxide laterally biased the drain voltage. The first set of figures depicts the phenomena under a 4-V drain voltage, all the other electrodes being grounded. The last figure compares the trapped hole charge density for drain bias varying between 0 and 2 V. As it could be anticipated, the charge trapping is not nil at zero-bias, because of built-in fields resulting from doping. But, naturally, the amount of trapped charge is increase with the drain bias. This is why the dose threshold at which the back-gate leakage MOS is triggered is strongly influenced by the drain voltage.

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Figure 96. Chart of the electric field in a 0.5 µm NMOS/SOI transistor in worst case during irradiation (VDS=+4V) using the self-consistent code A.

One clearly sees the strong deformation of the equipotential. At the beginning of the irradiation, we observe the situation of the “drain side-gating” in this thin-film SOI transistor: the electric field lines go directly from the drain to the backside of the transistor. Therefore, holes are directed toward the backside and build-up of the charge begins. In this figure, a 2D field collapse is clearly seen, as expected from [Boes-91] and the modeling in 1D exposed above in chapter 4.4. At the end of the irradiation, the field is nearly horizontal and reinforced, because the space charge has considerably extended.

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Figure 97. Apparition of an electron current at the back-side of the MOS between 90 and 210 krads in the back-side of a SOI transistor due to the turn-on of the back parasitic MOS in a N transistor biased in worst case during irradiation (VDS=+4V) using the self-consistent code A.

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VDS=+4V Figure 98. Trapped charge in the oxides of a NMOS/SOI transistor in worst case during irradiation using the self-consistent code A.

VDS=0

VDS=+1V

VDS=+2V

Figure 99. Charts of the charge build-up for other drain voltages of 0V, 1V and 2V using the self-consistent code A.

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11. CONCLUSIONS: TRENDS, MODELING, AND NEW ISSUES As radiation dose increases for new generation of satellites, it becomes more stringent to correctly use devices closer to their limits. For that, we have to look further on modeling and characterization. In this course, we have focuses on the oxide trapped charge as it is of first concern in discrete parts (Power MOS), most post-irradiation effects (rebound) and circuit leakage currents (build-up and recovery), and explored links with process and various situations as case studies. As gate oxide thickness decreases with the progress device integration, the total dose hardness of MOS transistors is mostly limited by parasitic MOS structures. The gate oxide to field oxide bird's beak forms a non-planar transistor responsible for leakage current at low dose. 1D, 2D and 3D-simulation codes are available or are being developed to calculate charge transport and trapping in non-planar MOS structures. Some codes are introducing detrapping phenomena. The dose induced leakage current is due to the threshold voltage shift of the lateral parasitic transistor mainly in the edge, which is directly related to the slope of the surface of parasitic transistors. The isolation geometry is determinant for the behavior of a technology. The isolation shape, the silicon doping level, the supply voltage and the trap parameters in the insulators are the key parameter tools to optimize a rad-tolerant technology. This appears is the key parameter to evaluate the variation of the trapped charge density in the parasitic MOS structures. As test structures are very unpractical, only numerical simulation can help to figure out what is instrumental. Anyway, to feed the codes with data in proper foer, new methods for acquiring parameters have now to be developed. Numerical modeling of interface traps component build-up and bipolar transistor gain degradation is foreseeable, although effective links with the manufacturing process apparently seem more obscure than for the trapped charge. Dose-rate or time-dependent effects are beginning to be implemented, and thus provide help for better understanding of circuit behavior. These conceptual and numerical tools could provide help for technology assessments, ground testing and in-flight predictions. 12. ACKNOWLEDGMENTS Dan Fleetwood, Lew Cohn for encouragement and careful reading. Gérard Barbottin for help in English correction of a large part of this text. The author sincerely wishes to associate Philippe Paillet in co-authorship of large parts of the work concerning, among other topics, analytical solutions and the modeling of detrapping, and co-workers Jean-Luc Autran, Christian Chabrerie, Dominique Hervé, Olivier Flament, Véronique Ferlet-Cavrois and Alphonse Torrès and also Clément Tavernier and Philippe Calvel for their kind participation to the material prepared and exploited.

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13. APPENDIX 13.1.

SELF-CONSISTENT CODES USED

In the following, we report the codes used here, which all share the essential characteristics to compute self consistently the potential, the current and the trapped charge. Only this type of codes can be credibly used for radiation effects modeling in oxides. Code A B C D E F Table 10.

13.2.

Name RAD-TRAPPOXTM v.5 ATLAS/DGEM/ORCHIDTM TRAPPOXR v.4 ACCESS-TRAPPOXR v.3 ACCESS-TRAPPOXR v.2 ASTEC3-TRAPPOXR v.1 and v.0

Origin ISE-CEA SILVACO [Mila-98] CEA [Lera-99b] CEA-CEM [Pail-98] CEA-CEM [Esco-95b, Bris-96] CEA [Herv-94, Lera-89]

Type 2D & 3D J and V-Models 2D & 3D J-Model 1D J and V-Models 2D+detrapping J-Model 2D J-Model 1D J and V-Models

Tables of the self-consistent codes used to illustrate this course.

PARAMETERS

We report here the main parameters used for simulations in chapter 4 (MOS) and 10 (MOS/SOI): 13.2.1. PARAMETERS USED IN CHAPTER 4 - The 450 nm (representing a Field-Oxide for field-collapse study). CEA Code: TRAPPOXR v.4 [Lera-99b] Parameters used: Model = J or V; oxide thickness tox = 450 nm; Finite difference; Number of nodes = 101; Not=1 1012 cm-2; NTP=4.41016 cm-3 ; σpt=1.10-12 cm2 + field dependence [Ning-76]; σpr=1.10-12 cm2; Y0 = 0.1; m =0.9;Ec = 6.5 105 V/cm; µ n= 10 cm2/V.s + field dependence; µ p= 10-5 cm2/V.s [Srour77b]+field dependence. ISE-CEA Code A: RAD-TRAPPOXTM v.5 Parameters used: Model = V; oxide thickness tox = 450 nm; Finite elements; Not=1. 1012 cm-2; NTP=4.41016 cm-3 ; σpt=1.10-12 cm2 + field dependence [Ning-76]; σpr=1.10-12 cm2; Y0 = 0.1; m =0.9;Ec = 6.5 105 V/cm; µ n= 10 cm2/V.s + field dependence; µ p= 10-5 cm2/V.s [Srour77b]+field dependence. SILVACO Code B Parameters used: Model = J; oxide thickness tox = 450 nm; Finite elements; Not=1. 1012 cm-2; NTP=4.41016 cm-3 ; σpt=1.10-12 cm2; σpr=0.10-12 cm2; Y0 = 0.0; Y=exponential saturation; µ p= 10-5 cm2/V. - The 300 nm (representing another Field-Oxide for gate bias switching). III-105

CEA Code: TRAPPOXR v.4 [Lera-99b] Parameters used: Model = J; oxide thickness tox = 300 nm; Finite difference;Number of nodes = 101; Not=0.5 1012 cm-2; NTP=3.31016 cm-3 ; σpt=1.10-12 cm2 + field dependence [Ning-76]; σpr=1.10-12 cm2; Y0 = 0.1; m =0.9;Ec = 6.5 105 V/cm; µ n= 10 cm2/V.s + field dependence; µ p= 10-5 cm2/V.s [Srour77b]+field dependence. 13.2.2. PARAMETERS USED IN CHAPTER 10 ISE-CEA Code A: RAD-TRAPPOXTM v.5 Parameters used: Model = V; Finite elements; gate length Lg= 0.5 µm; LDD ; gate oxide thickness tox1 = 10 nm; NTP1=3. 1018 cm-3; uniform density of traps; buried oxide thickness tox2 = 300 nm; NTP2=3. 1018 cm-3; uniform density of traps; for the two oxides: σpt=5.10-14 cm2 + field dependence [Ning-76]; σpr=5.10-14 cm2; Y0 = 0.1; m =0.9;Ec = 6.5 105 V/cm; µ n= 10 cm2/V.s + field dependence; µ p= 10-5 cm2/V.s [Srour77b]+field dependence. 14. REFERENCES [1019] [1892] [22900] [Adam-76] [Adam-77] [Adam-91] [Aubu-71] [Ausm-86] [Autr-95]

[Autr-99]

[Babc-95]

[Bart-97] [Bene-86] [Bene-87]

[Boes-75] [Boes-76] [Boes-86]

MIL-Std 883, Method 1019, DoD, USA and Web pages. ASTM F-1892, USA and Wep pages. ESA/SCC Basic Specifications, Method 22900 and Web pages for preview. J.R. Adams, F.N. Coppage, “Field oxide inversion effects in irradiated CMOS devices”, IEEE Trans Nucl. Sci., NS-23, 6, 1604 (1976). J.R. Adams, W.R. Dawes, T.J. Sanders, “A radiation-hardened field oxide”, IEEE Trans. Nucl. Sci., NS-24, 6, 2099 (Dec. 1977). L. Adams and A. Holmes-Siedle, “La survie de l'électronique dans l'espace”, La Recherche, Vol. 22, Oct. 1991, pp. 1182-1189. K.G. Aubuchon, “Radiation hardening of PMOS devices by optimization of thermal SiO2 gate insulator”, IEEE Trans. Nucl. Sci. NS-17, 6, (1971). G.A. Ausman, “Field-dependence of geminate recombination in a dielectric medium”, Harry Diamond Laboratories report n° 2097, Adelphi, MD, U.S.A., (1986). J.L. Autran, P. Paillet, J.L. Leray, R. Devine, “Conduction mechanisms and space-charge effects in typical thin-film insulators (SiO2, Ta2O5, PbZrxTi1-xO3)”, 2nd Intl Conf. On Space Cherge in Solids Dielectrics CSC2, edited in “Le Vide”, n°275, March 1995, pp. 44-53. J.L. Autran, “Charge Pumping Techniques. Their use for diagnosis and interface studies in MOS transistors”, in “Instabilities in Silicon Devices”, Vol. 3, pp. 405-494, G. Barbottin and A. Vapaille, Editors (North-Holland ISBN 0 444 81801 4). J.A.Babcock, S.D. Clark, J.D. Cressler, D.L. Harame, R.C. Jaeger and L.S. Vempati, “Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD”, IEEE Trans. Nucl. Sci ,NS-42, 6, 1558 (1995). J. Barth, “Modeling Space Radiation Environment”, 1997 IEEE NSREC Short Course. J.M. Benedetto and H.E. Boesch, “The relationship between 60Co and 10-keV x-ray damage in MOS devices”, IEEE Trans. Nucl. Sci, NS-33, No 6., 1318 (1986). J.M. Benedetto, H.E. Boesch, T.R. Oldham and G.A. Brown, “Measurement of low-energy x-ray dose enhancement in MOS devices with metal silicided devices”, IEEE Trans. Nucl. Sci., NS-34, 6, 1540 (1987). H.E. Boesch, F.B. McLean, J.M. McGarrity, J. Ausman, “Hole transport and charge relaxation in irradiated MOS capacitor”, T-NS 22, 6, 2163 (1975). H.E. Boesch and J.M. McGarrity, “Charge yield and dose effects in MOS capacitors at 80K”, IEEE Trans. Nucl. Sci., NS-23, 6, 1520 (1976). H. E. Boesch, F. B. McLean, J. Benedetto and J. McGarrity, “Saturation of threshold voltage shift in All references are unclassified

III-106

[Boes-88] [Boes-91] [Boes-94] [Boud-93] [Bris-96]

[Brow-81] [Brow-83] [Brow-85] [Brow-90] [Calv-99] [Chab-97a]

[Chab-97b]

[Chu-90] [Cirb-95]

[Coli-97] [Conl-97] [Cour-99] [Cris-95] [CTVS] [Curt-75] [Curt-77] [Daly-88] [Davi-85] [Dawe-76] [Deal-80] [Derb-75]

NS-33, 6, 1191 (1986). H.E. Boesch, “Time-dependent interface trap effects in MOS devices”, IEEE Trans. Nucl. Sci. NS35, 6, 1160 (1988). H. E. Boesch, G. A. Brown, “Charge buildup at high dose and low fields in SIMOX buried oxides”, IEEE Trans. Nucl. Sci., NS-38, 6, 1234 (1991). H.E. Boesch and C.A. Pennise, “Measurement and modeling of radiation response of multilayer BESOI buried insulators”, IEEE Trans. Nucl. Sci., NS-41, 6, 2322 (1994). J.C.Boudenot, “Interaction Mechanisms and Environments”, Short Course, RADECS-93 Conference (The RADECS Association, C/O Joseph Pinel, Toulouse, France). C. Brisset, V. Ferlet-Cavrois, O. Flament, O. Musseau, J. L. Leray, J. L. Pelloie, R. Escoffier, A.Michez, C. Cirba, G. Bordure, “Two-dimensional simulation of total dose effects on NMOSFET with lateral parasitic transistor”, IEEE Trans. Nucl. Sci., NS-43, 6, 2651 (1996). C.M. Dozier and D.B. Brown, “Electron-hole recombination from a microdosimetry viewpoint”, IEEE Trans. Nucl. Sci., NS-28, 6, 4142 (1981). D.B. Brown, “Thermal annealing of radiation induced defects: a diffusion-limited process? Trans. Nucl. Sci., NS-30, 6, 4059 (1983). D.B. Brown, “Time dependence of interface states production”, IEEE Trans. Nucl. Sci., NS-32, 6, 3900 (1985). D. B. Brown, “Total-Dose Effects at Dose Rates Typical of Space”, 1990 IEEE NSREC Short Course. Philippe Calvel, Alcatel-Space, Priv. Com. C. Chabrerie, “De l’utilisation des recuits isothermes et isochrones pour la caractérisation de structures CMOS irradiées”, Doctoral Thesis in Physics, Université Paris 7, Paris, France, March 1997 (available in microfiche at ANRT/University of Grenoble-II). C. Chabrerie, J.L. Autran, P. Paillet, O. Flament, J.L. Leray and J.C. Boudenot, “Isothermal and isochronal annealing method to study post-irradiation temperature activated phenomena”, IEEE Trans. Nucl. Sci, NS-44, 6, 2007 (1997). A.X. Chu and W.B. Fowler, “Theory of oxide defects near the Si-SiO2 interface”, Phys. Rev. B, 41, 8, 5061 (1990). C. Cirba, “Simulation numérique du piégeage et du dépiégeage dans les oxydes de composants MOS”, Thèse de doctorat en Sciences Physiques, Université de Montpellier II, France, Dec. 16th , 1996, n°96MON2237 (available in microfiche at ANRT/University of Grenoble-II). J.-P. Colinge, “Silicon-On-Insulator Technology: Material to VLSI”, Kluwer Academic Publishers, Boston, (2nd edition, 1997) ISBN 0-7923-8007-X. J.F. Conley, P.M. Lenahan, B.D. Wallace and P. Cole, “Quantitative model of radiation induced charge trapping in SiO2”, IEEE Trans. Nucl. Sci., NS-44, 6, 1804 (1997). A. Courtot-Descharles, P. Paillet, J.L. Leray, “Theoretical study using density functional theory of defects in amorphous silicon dioxide”, Journ. Of Non-Crystalline Solids, 245, 154 (1990). S. Cristoloveanu and S.S.Li, “Electrical characterization of Silicon-On-Insulator materials and , Kluwer Academic Publishers (1995), ISBN 0-7923-9548-4. “Cours de Technologie des Véhicules Spatiaux”, Vol. 1 et 3. Centre National d’Etude Spatiales CEPADUES-Editions (111 rue Nicolas Vauquelin, Toulouse, France). O.L. Curtis, J.R. Srour and K.Y. Chiu, “Physical mechanisms of radiation hardening of MOS devices NS-22, 6, 2174 (1975). O.L. Curtis, J.R. Srour, “The multiple trapping model and hole transport in a-SiO2”, J. App. Phys. 48, 9, 3819 (1977). E.J. Daly, “Evaluation of the space environment for the ESA projects”, ESA Journal, 88, 12, 229 (1988). G.E Davis, T.G. Blake, C.E. Chen, R. DeMoyer Jr, L.R. Hite, H.W. Lam, “Transient radiation effects NS-42, 6, 4432 (1985). W.R. Dawes, Jr., G.F. Derbenwick, and B.L. Gregory, “Process technology for radiation-hardened CMOS integrated circuits”, IEEE J. Solid State Circuits SC11(4), 459 (1976). B.E. Deal, “Standardized terminology for oxide charges associated with thermally oxidized silicon”, IEEE Trans. Electron Devices, ED-27, 3, 606-607 (1980). G.F. Derbenwick and B. Gregory, “Process optimization of radiation-hardened CMOS integrated circuits”, IEEE Trans. Nucl. Sci, NS-22, 6, 2151 (1975). All references are unclassified

III-107

[Devi-94] [Devi-95] [Dozi-81] [Dres-98] [Dupo-91]

[Dyer-98] [Eern-76] [Emil-96] [Enlo-89] [Esco-95a]

[Esco-95b]

R.A.B. Devine, “The structure of SiO2, its defects and radiation hardness”, IEEE Trans. Nucl. Sci., NS-41, 3, 452 (June 1994) and Proceeding RADECS-93. R.A.B. Devine, W.L. Warren, J.B. Xu, I.H. Wilson, P. Paillet and J.L. Leray, “Oxygen gettering and oxide degradation during annealing of Si/SiO2/Si structures”, J.Appl. Phys., 77 (1), 1, (1995). D.B. Brown and C.M. Dozier, “Effect of photon energy on the response of MOS devices”, IEEE Trans. Nucl. Sci., NS-28, 6, 4137 (1981). Paul V. Dressendorfer, “Basic Mechanisms for the New Millenium”, IEEE 1998 NSREC Short Course. E.Dupont-Nivet, E.Delagnes, J.L.Leray, J.L.Martin, J.Montaron, J.P.Blanc, E.Delevoye, J.Gautier, J. de Poncharra, R.Truche, E.Beuville, M.Dentan and N.Fourches, “A hardened technology on SOI for analog devices”, RADECS-91, IEEE Proceedings 91TH0400-2, 15, p. 211 (1991). C. Dyer, “Space Radiation Environment Dosimetry”, 1998 IEEE NSREC Short Course. E.P.Eernisse and G.F.Derbenwick, “Viscous shear flow model for MOS device radiation sensitivity”, IEEE Trans. Nucl. Sci. NS-23, 6, 1534 (1976). David Emily, “Total-Dose Response of Bipolar Microcircuits”, 1996 IEEE NSREC Short Course. E.W. Enlow, R.L. Pease, W.E. Combs and D.G. Platteter, “Total dose induced hole trapping in trench NS-36, 6, 2415 (1989). R. Escoffier, “Simulation numérique de l’effet des charges induites par l’irradiation dans les oxydes des structures MOS”, Thèse de doctorat en Sciences Physiques, Université de Montpellier II, France, Sept. 29th ,1995, (available in microfiche at ANRT/University of Grenoble-II). R. Escoffier, A. Michez, C. Cirba, G. Bordure, P. Paillet, V. Ferlet-Cavrois and J.L. Leray, “Radiation induced shift study in parasitic MOS structures by 2D numerical simulation”, 3nd European Conference on Radiation and their Effects on Devices and Systems (RADECS-95), IEEE 95TH8147.

[Euro-92]

[Farm-73]

[Ferl-96]

J.L. Leray, Training Course ME-10 “Electromagnetic and radiation Effects on Electronics”, Lecture 07 available in video and hard copy at EUROPACE (EUROPean Advanced Continuing Education), Paris La Défense (92), France. J. Farmer, “X-ray induced currents and space-charge build-up in MOS capacitor”, PhD Thesis, Kansas State University, 74-25/599 (1974) (available in microfiche at Xerox University Microfilms, Ann Arbor, Michigan). V. Ferlet-Cavrois, O. Musseau, J. L. Leray, J. L. Pelloie, C. Raynaud, “Total dose effects on short channel NMOS/SOI transistors and its lateral transistor”, IEEE Trans. Electron Devices., ED-44, 6, 965 (1996) and 3nd European Conference on Radiation and their Effects on Devices and Systems (RADECS95), IEEE 95TH8147, p. 142 (1995).

[Ferl-98]

[Ferr] [Flam-92]

[Flam-94]

[Flam-95a] [Flam-95b]

[Flam-95c]

[Flam-98]

[Flam-99]

V. Ferlet-Cavrois, O. Musseau, O. Flament, J. L. Leray, J. L. Pelloie, C. Raynaud and O. Faynot, “Total dose induced latch in short channel NMOS/SOI transistors”, IEEE Trans. Nucl. Sci., NS-45, 6, 2458 (1992). D.K. Ferry, “Semiconductors”, p. 323, Maxwell MacMillan Engineering Editions. O. Flament, D. Hervé, O. Musseau, Ph. Bonnel, M. Raffaelli, J.L. Leray, J. Margail, B. Giffard, A.J. Auberton-Hervé, “Field dependent charge trapping effects in SIMOX buried oxides at very high ,NS-39, 6, 2132 (1992). O.Flament, J.L.Leray, J.L.Martin, J.Montaron, M.Raffaelli, J.P.Blanc, E.Delevoye, J.Gautier, J.de Poncharra, R.Truche, E.Delagnes, M.Dentan and N.Fourches, “Radiation effects on SOI analog devices parameters”, Trans. Nucl. Sci., NS-41, 3, 565 (1994) and RADECS-93, IEEE Conference Records Catalog Number 93TH0616-3, ISBN 0-7803-1793-9. O. Flament, “X-ray radiation sources for process development and qualification”, L'Onde Electrique, 75, May 3rd (1995), and Proc. of the RADECS-SEE Workshop, Toulouse 23 Sept. 1994. O.Flament, J.L.Leray, F. Martin, E.Orsier, J.L.Pelloie, R.Truche, and R.A.B. Devine, “The effect of rapid thermal annealing on radiation hardening of MOS devices”, IEEE Trans. Nucl. Sci., NS-42, 6, 1667 (1995). O.Flament, J.L.Leray, O.Musseau, “A mixed-mode analog-digital CMOS-NPN-PJFET on insulator technology and applications”, in “ , G.A. Machado Ed., IEE Circuits and Systems Series 8, Laventham Press, Laventham, UK ISBN 0-85296-874-4 (1995). O. Flament, C. Chabrerie, V. Ferlet-Cavrois, J.L. Leray, F. Faccio and P. Jarron, “A methodology to study lateral parasitic transistor in CMOS technologies”, IEEE Trans. Nucl. Sci., NS-45, 3, 1385 (June 1998). O. Flament, P. Paillet, J.L. Leray and D.M. Fleetwood, “Consideration on isochronal technique: from All references are unclassified

III-108

[Flee-90] [Flee-91] [Flee-92a] [Flee-92b] [Flee-92c]

[Flee-95] [Flee-98]

[Free-78] [Gall-84] [Gall-85] [Grav-98]

[Grisc-85] [Grisc-88]

[Grov-66] [Hara-95]

[Herv-93]

[Herv-94] [Holm-93] [Hugh-71] [Hugh-72] [Hugh-73] [Hugh-75a] [Hugh-75b] [Hugh-78] [Hugh-85] [John-96]

measurement to Physics”, 1999 NSREC, this Conference. D.M. Fleetwood, P.S. Winokur and L.C. Riewe, “Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices”, IEEE Trans. Nucl. Sci., NS-37, 6, 1632, (1990). D. M. Fleetwood, R. A. Reber, Jr., and P. S. Winokur, “Effect of bias on thermally stimulated current (TSC) in Irradiated MOS devices”, IEEE Trans. Nucl. Sci., NS-38, 6, 1066, (1991). D.M. Fleetwood, “Long-term annealing study of midgap interface-trap charge neutrality”, Appl. Phys. Lett., 60, 2883 (1992). D.M. Fleetwood, “Border traps in MOS devices”, IEEE Trans. Nucl. Sci., NS-39, 2, 269-71 (Apr. 1992). D. M. Fleetwood, S. L. Miller, R. A. Reber, Jr., P. J. McWhorter, P. S. Winokur, M. R. Shaneyfelt, and J. R. Schwank, “New insights into radiation-induced oxide-trap charge through thermally stimulated current measurement and analysis”, IEEE Trans. Nucl. Sci., NS-39, 6, 2192 (1992). D. M. Fleetwood, “A First-Principle Approach to Total-Dose Hardness Assurance”, 1995 IEEE NSREC Short Course. D.M. Fleetwood, P.S. Winokur, M.R. Shaneyfelt, L.C. Riewe, O. Flament, P. Paillet and J.L. Leray, “Effects of isochronal annealing and irradiation temperature on radiation-induced trapped charge”, IEEE Trans. Nucl. Sci, NS-45, 6, 2366 (1998). R.F.A. Freeman, A.G. Holmes-Siedle, “A simple model for the effects of radiation on MOS devices”, IEEE Trans. Nucl. Sci., NS-25, 6, 1216 (1978). K.G. Galloway, M. Gaitan and T.J. Russell, “A Simple Model for Separating Interface and Oxide Charge Effects in MOS Device Characteristics”, IEEE Trans Nucl. Sci., NS-31, 6, 1497 (1984). K.G. Galloway, C.L. Wilson, L.C. Witte, “Charge-Sheet Model Fitting to Extract Radiation-Included Oxide and Interface Charge”, IEEE Trans Nucl. Sci., NS-32, 6, 4461 (1985). R.J. Graves, C.R. Cirba, R.D. Schrimpf, R.J. Milanowski, A. Michez, D.M. Fleetwood, S.C. Witczak, F. Saigne, “Modeling low-dose-rate effects in irradiated bipolar-base oxides”, IEEE Trans. Nucl. Sci., NS-45, 6, 2352 (1998). D.L. Griscom, “Diffusion of radiolytic molecular hydrogen as a mechanism for the post-irradiation build-up of interface states in SiO2 on Si structures”, J.App.Phys., 58, 7, 2524 (1985). D.L. Griscom, D.B. Brown, N.S. Saks, “Nature of radiation-induced point defects in amorphous SiO2 and their role in SiO2-on-Si structures”, in “The physics and chemistry of SiO2 and the Si-SiO2 interface”, C.R. Helms and B.E. Deal Editors, Plenum Press (1988), p. 287. A.S. Grove and E.H. Snow, Proc. IEEE, 54, 1966, pp. 894-895. D.L. Harame, J.H. Comfort, J.D. Cressler, E.F. Crabbé, J.Y.C. Sun, B.S. Meyerson, and T.Tice, “Si/SiGe epitaxial-base transistors-Part II: Process integration and analog applications”, IEEE Trans. Electron Devices, NS-42, 3, 469 (1995). D. Hervé, “Effets à long terme des rayonnements dans les structures métal-oxyde-semiconducteur. Application aux dispositifs à transfert de charge”, Doctoral Thesis in Physics, n°2711, Université Paris 11, Orsay, France, Jan. 1993 (available in microfiche at ANRT/University of Grenoble-II). D. Hervé, P. Paillet and J.L. Leray, “Space charge effects in SIMOX buried oxides”, IEEE Trans. Nucl. Sci., NS-41, 466 (1994). A. Holmes-Siedle and L. Adams, “Handbook of radiation effects”, Oxford University Press (1993). H.L. Hughes, “A survey of radiation-induced perturbations in Metal-Insulator-Semiconductor th Ann. Proc. Reliability Physics Symposium, 33 (1972). H.L. Hughes, “Dependence of MOS device radiation sensitivity on oxide impurities”, IEEE Trans. Nucl. Sci., NS-19, 6, 256 (1972). R.C. Hughes, “Charge-carrier transport phenomena in amorphous SiO2: direct measurement of the drift mobility and lifetime”, Phys. Rev. Lett., 30, n°26, 1333 (1973). R.C. Hughes, E.P. EerNisse and H.J. Stein, “Hole transport in MOS oxides”, IEEE Trans. Nucl. Sci., NS-22, 6, 2227 (1975). R.C. Hughes, “Hole mobility and transport in thin SiO2 films”, App. Phys. Lett., 26, n°8, 436 (1975). R.C. Hughes, “High field properties of SiO2”, Solid-State Electron., 21, 251-258 (1978). R.C. Hughes, “Theory of response of radiation sensing field effect transistors”, J. Appl. Phys., 58, 1375 (1985). A.H. Johnston, C.I. Lee and B.G. Rax, “Enhanced damage in bipolar devices at low dose rates: effects at very low dose rates”, IEEE Nucl. Sci., NS-43, 6, 3049 (1996). All references are unclassified

III-109

[John-98] [Kako-89] [Kern-92] [Kim-88] [Kooi-91] [Kosi-94]

[Kran-87] [Kran-91] [Lai-83] [Lee-91] [Lena-83] [Lera-85] [Lera-88a] [Lera-88b]

[Lera-88c]

[Lera-89a]

[Lera-89b] [Lera-90]

[Lera-99a]

[Lera-99b]

[Ma-89] [Mahe-94] [McGa-80] [McLe-80]

A.H. Johnston, “Radiation Effects in Advanced Microelectronics technologies”, RADECS-97 Conference and , IEEE Trans. Nucl. Sci., NS-45, 3, 1339 (June 1998). R. Kakoschke and E. Bussmann, “Simulation of temperature effects during rapid thermal processing”, MRS Symposium Proceedings, Vol. 146 (1989). K.G. Kerns and M.S. Gussenhoven, report PL-TR-922201 n°1105 on CRESSRAD experiment, USAir Force Philips Lab. (1992). Y.Y. Kim and P.M. Lenahan, “Electron-Spin-Resonance study of radiation-induced paramagnetic defects in oxides grown on (100) silicon substrates”, J. Appl. Phys., 64, p. 3551, (1988). E. Kooi, “The invention of LOCOS”, IEEE Case studies of achievement in science and technology Vol. 1, NY (1991). S.L. Kosier, W.E. Combs, A. Wei, R.D. Schrimpf, D.M. Fleetwood, M. DeLaus and R.L. Pease, “Bounding the total-dose response of modern bipolar transistors”, IEEE Trans. Nucl. Sci., NS-41, 6, 1864 (1994). R.J. Krantz, L.W. Aukerman, T.C. Zietlow, “Applied field and total dose dependence of trapped charge build-up”, IEEE Trans. Nucl. Sci., NS-34, 6, p. 1196, (1987). R.J. Krantz, J. Scarpulla, J.S. Cable, “Total dose-induced charge build-up in nitrided-oxide MOS devices “, IEEE Trans. Nucl. Sci. NS-38, 6, Dec. 1991, pp. 1746. S.K. Lai, “Interface trap generation in silicon dioxide when electrons are captured by trapped holes”, J.App.Phys., 54, 5, 2540 (1983). Der-Sun Lee and Chung-Yu Chan, “Oxide charge accumulation in Metal-Oxide Semiconductors devices during Irradiation”, J. Appl. Phys., 69 (10), 15 May 1991. P.M. Lenahan and P.V. Dressendorfer, “Micro-structural variations in radiation hard and soft oxides observed through electron-spin-resonance”, IEEE Trans. Nucl. Sci., NS-30, 6, 4602 (1983). J.L. Leray, “Activation energies of oxide charge recovery in SOS or SOI structures after an ionizing NS-32, 6, 3921 (1985). J.L. Leray, “Assessments of SOI technologies for hardening”, Microelectronic Engineering, Vol. 8 , n°3-4, p.187 (Dec. 1988) and 1st European SOI workshop, Meylan, France, 1988. J.L. Leray, E. Dupont-Nivet, P. Lalande, O. Musseau, Y.M. Coïc, A.J. Auberton-Hervé, M. Bruel, C. VLSI : investigations of hardened SIMOX without epitaxy for dose, dose rate and SEU”, IEEE Trans. Nucl. Science, NS-35, 6, 1355 (1988). J.L. Leray, O. Musseau, E. Dupont-Nivet, J.F. Péré and Y.M. Coïc, “A study of the sensitivity to cosmic rays and integrated dose of bit-slice microprocessors in CMOS and CMOS on Insulator technologies”, 6th International Conference on Reliability and Maintainability, Biarritz “λ−µ6”, ADERA edit. (Bordeaux, France), p. 625 (1998). J.L. Leray, “Contribution à l'étude des phénomènes induits par les rayonnements ionisants dans les structures à effet de champ au silicium et à l'arséniure de gallium”, Thèse de doctorat d'Etat es Sciences Physiques, n°3576, Université Paris 11, Orsay, France (Dec. 1989) (available in microfiche at ANRT/University of Grenoble-II). J.L. Leray, “Structures à Effet de Champ en Irradiation. Effets de la Dose de Rayonnement”, Short Course, RADECS-1989 (The RADECS Association, C/O Joseph Pinel, Toulouse, France). J.L. Leray, E. Dupont-Nivet, J.F. Péré, Y.M. Coïc, M. Raffaelli, A.J. Auberton-Hervé, M. Bruel, B. Giffard and J. Margail, “CMOS/SOI hardening above 100 megarad(SiO2): limits and liabilities”, IEEE Trans. Nucl. Science, NS-37, 6 (1990). J.L. Leray, “A review of buried oxides and SOI technologies”, in “Instabilities in Silicon Devices”, Vol. 3, pp. 145-232, G. Barbottin and A. Vapaille, Editors (North-Holland ISBN 0 444 81801 4) (1999). J.L Leray, P. Paillet, O. Flament and A. Torrès, “Oxide charge modeling with Trappox code version 4. Comparison of trapping models on desktop computer”, to be presented at 1999 RADECS Conference, Fontevrault (France). TP. Ma et P. V. Dressendorfer, “Ionizing radiation effects in MOS devices and circuits”, J. Wiley & sons, N.Y. (1989). M. Maher, “Total dose testing of Advanced CMOS Logic at low voltage”, National Semiconductor, Application Note AN-927 (1994) (available in Web site). J.M. McGarrity, “Considerations for hardening MOS devices and circuits for low radiation doses”, IEEE Trans. Nucl. Sci., NS-27, 6, 1739 (Dec. 1980). F.B. McLean “A framework for understanding radiation-induced interface states in MOS structures”, All references are unclassified

III-110

[McLe-87] [McWh-86] [McWh-88] [McWh-90] [Mess-92]

IEEE Nuc.Sci. NS-27, 6, 1651 (1980). F.B. McLean, “Basic Mechanisms of Radiation Effects on Electronic Materials, Devices and Integrated Crcuits”, 1987 IEEE NSREC Short Course. P.J. McWhorter and P.S. Winokur, “Simple technique for separating the effects of interface traps and trapped-oxide charge in Metal-Oxide-Semiconductor transistors”, Appl. Phys. Lett. 48, 133 (1986). P.J. McWhorter, P.S. Winokur, and R.A. Pastorek, “Donor/acceptor nature of radiation-induced interface traps”, IEEE Trans. Nucl. Sci., NS-35, 6, 1154 (1988). P.J. McWhorter, S. L. Miller, and W. M. Miller, “Modeling the anneal of radiation-induced trapped holes in a varying thermal environment”, IEEE Nucl. Sci. NS-37, 6, 1682 (1990). G.C. Messenger and M.S. Ash, “The Effects of Radiations on Electronic Systems”, van Nostrand Rheinhold, ISBN 0-442-2359-1 (2nd Ed., 1992), p. 334, ISBN 0-442-25417-2.

[Mila-98]

R.J. Milanowski, M.P. Pagey, L.W. Massengill, R.D. Schrimpf, M.E. Wood, B.W. Offord, R.J. Graves, K.F. Galloway, C.J. Nicklaw and E.P. Kelley, “TCAD-assisted analysis of back-channel leakage in irradiated Mesa SOI NMOSFETs”, IEEE Trans. Nucl. Sci., NS-45, 6, 2593 (1998).

[Mitc-67]

J.P. Mitchell and D.K. Wilson, “Surface effects of radiation on semiconductor devices”, The Bell System Technical Journal, Vol. XLVI, n°1, pp. 1-80 (Jan. 1967). N.F. Mott, A.M. Stoneham, “The lifetime of electrons, holes and excitons before self-trapping”, J. Pys. Chem. Solid State Physics, 10, 3391 (1977). B.J. Mrstik, R.W. Rendell, “Si-SiO2 interface-state generation during x-ray irradiation and during post-irradiation exposure to a hydrogen ambient”, IEEE Trans. Nucl. Sci., NS-38, 6, 1101 (1990). T.H. Ning, “High-field capture of electrons by coulomb-attraction centers in silicon dioxide”, J. Appl. Phys, 45, 7, 1976. R.N. Nowlin, E.W. Enlow, R.D. Schrimpf, and W.E. Combs, “Trends in the total-dose response of modern bipolar transistors”, IEEE Trans.Nucl.Sci., NS-39, 6, 2026 (1992). R.N. Nowlin, D.M. Fleetwood, R.D. Schrimpf, R.L. Pease, and W.E. Combs, “Hardness-assurance and testing issues for bipolar/BICMOS devices”, IEEE Trans.Nucl.Sci., NS-40, 6, 1686 (1993). T.R. Oldham and J. M. McGarrity, “Ionization of SiO2 by heavy charged particles”, IEEE Trans. Nucl. Sci. NS-28, 6, 3975 (1981). T.R. Oldham, “Charge generation and recombination in silicon dioxide”, Harry Diamond Laboratories report n° 1985, Adelphi, MD, U.S.A., (1986). T.R. Oldham and J.M. McGarrity, “Comparison of 60Co response and 10 keV x-ray response in

[Mott-77] [Mrst-91] [Ning-76] [Nowl-92] [Nowl-93] [Oldh-81] [Oldh-82] [Oldh-83] [Oldh-84] [Oldh-86] [Oldh-87] [Othm-80] [Pail-93]

[Pail-94] [Pail-95a]

[Pail-95b]

[Pail-95c]

[Pail-98]

MOS capacitors”, IEEE Trans. Nucl. Sci., NS-30, 6, 4377 (1983). T.R. Oldham, “Analysis of damage in MOS for several radiation environments”, IEEE Trans. Nucl. Sci,, NS-31, 6, 1236 (1984). T. Oldham, A. Lelis and F.B. McLean, “Spatial dependence of trapped holes determined from tunneling analysis”, IEEE Trans. Nucl. Sci., NS-33, 6, 1203 (1986). T.R. Oldham, A.J. Lelis, H.E. Boesch, J.M. Benedetto, F.B. McLean and J.M. McGarrity, “Postirradiation effects in field-oxide isolation structures”, IEEE Trans. Nucl. Sci., NS-34, 6, 1184 (1987). S. Othmer and J.R. Srour, “Electron transport in SiO2 at low temperatures”, in “The Physics of MOS Insulators”, G. Lukovsky, S.T. Pantelides Editors, Pergamon (1980), p. 49. Ph. Paillet, D. Hervé, J.L. Leray and R. Devine, “Effect of high temperature processing of Si/SiO2/Si structures on their response to X-ray irradiation”, Appl. Phys. Lett., 63 (15), 2088-2090, 11 October 1993. P. Paillet, D. Hervé, J.L. Leray and R.A.B. Devine, “Evidence of Negative Charge Trapping in High Temperature Annealed Thermal Oxide”, IEEE Trans. Nucl. Sci., NS-41, p. 473 (1994). Ph. Paillet,P. Gonon, C. Schwebel and J.L. Leray, “Comparison of X-Ray-Induced Electron and Hole Trapping in Various Materials (YSZ, SIMOX, Thermal SiO2)”, Journal of Non-Crystalline Solids, 187 (1995) and E-MRS Spring Meeting, May 24-27 1994, Strasbourg (France). P. Paillet, J. L. Autran, J. L. Leray, B. Aspar and A. J. Auberton-Hervé, “Trapping-detrapping properties of irradiated ultra-thin SIMOX buried oxides”, IEEE Trans. Nucl. Sci., NS-42, 6, 2108 (1995). P. Paillet, “Effet du procédé de fabrication des isolants sur la charge d’espace créée par rayonnement X: application aux technologies silicium sur isolant”, Thèse de doctorat en Sciences Physiques, n°95MON2042, Université de Montpellier II, France, March 30th, 1995 (available in microfiche at ANRT/University of Grenoble-II). P. Paillet, J.L. Touron, J.L. Leray, C. Cirba, A. Michez, “Simulation of Multi-Level radiationAll references are unclassified

III-111

[Pail-99]

[Peas-74] [Peas-85] [Peas-90] [Penn-90] [Penn-92] [Pers-92]

[Pers-97]

[Peyr-91]

[Plat-88] [Raym-92]

[Reve-77] [Saig-97]

[Saks-89] [Saks-90] [Saks-91] [Schm-95]

[Schm-96]

[Scho-39] [Schr-96]

[Schw-88]

[Schw-96]

Induced Charge Trapping and Thermally Activated Phenomena in SiO2”, RADECS-97 Conference and IEEE Trans. Nucl. Sci., NS-45, 3, 1379 (June 1998). P. Paillet and J.L. Leray, “Defects and radiation-induced charge trapping phenomena in silica”, in , Vol. 3, pp. 723-780, G. Barbottin and A. Vapaille, Editors (NorthHolland ISBN 0 444 81801 4). R.L. Pease, F.N. Coppage and E.D. Graham, “Dependence of ionizing radiation-induced hFE degradation on emitter periphery”, IEEE Trans. Nucl. Sci., NS-21, 2, 1216 (Apr. 1974). R. Pease, D. Emilly, H.E. Boesch, “Total dose induced hole trapping and interface states generation in bipolar recessed field oxides”, IEEE Trans Nucl. Sci., NS-32, 6, 3946 (1985). R. Pease, “Radiation Testing of Semiconductors for Space Electronics”, 1990 IEEE NSREC Short Course. C.A. Pennise and H.E. Boesch, “Determination of the charge-trapping characteristics of buried oxides using a 10-keV X-ray source”, IEEE Trans. Nucl. Sci., NS-37, 6, 1990 (1990). C.A. Pennise and H.E. Boesch, “Photoconduction measurements of the charge trapping and transport characteristics of bond-and-etch-back buried oxides”, IEEE Trans. Nucl. Sci., NS-39, 6, 2139 (1992). V.S. Pershenkov and V.V. Chuikin, “The Effect of junction fringing field on radiation-induced leakage current in oxide isolation structures and nonuniform damage near the channel edges in MOSFETs”, IEEE Trans Nucl. Sci., NS-39, 6, 2044 (1992). V.S. Pershenkov, V.B. Maslov, S.V. Cherepko, I.N. Shvetzov-Shilovsky, V.V. Belyakov, A.V. Sogoyan, V.I. Rusanovsky, V.N. Ulimov, V.V. Emelianov and V.S. Nasibullin, “The effect of emitter junction bias on the low dose-rate radiation response of bipolar devices”, IEEE Trans Nucl. Sci., NS44, 6, 1840 (1997). D. Peyre, “Contribution à l’étude des effets semi-permanents induits par les rayonnements ionisants dans les transistors MOS”, Thèse de doctorat en Sciences Physiques France, 1991 (available in microfiche at ANRT/University of Grenoble-II). D.G. Platteter and T.F. Cheek Jr., “The use of multiple oxygen implants for fabrication of bipolar silicon-on-insulator integrated circuits”, IEEE Trans. Nucl. Sci., NS-35, 6, 1350 (1988). J.P. Raymond, R.A. Gardner and G.E. LaMar, “Characterization of radiation effects on trenchisolated bipolar analog microcircuits technology”, IEEE Trans Nucl.Sci., NS-39, 3, 405 (June 1992) and Proc. RADECS-91. A.G. Revesz, “Chemical and structural aspects of the irradiation behavior of SiO2 films on silicon”, IEEE Trans. Nucl. Sci., NS-24, 6, 2102 (1977). F. Saigné, L. Dusseau, J. Fesquet, J. Gasiot, R. Ecoffet, J.P. David, R.D. Schrimpf and K.F. Galloway, “Experimental validation of an accelerated method of oxide-trap-level characterization for predicting long term thermal effects in metal-oxide semiconductor devices”, IEEE Trans. Nucl. Sci, NS-44, 6, 2001 (1997). N.S. Saks and D.B. Brown, “Interface-states formation via the two-stage process”, IEEE Trans. Nucl. Sci., NS-36, 6, 1848 (1989). N.S. Saks and D.B. Brown, “Observation of the H+ motion during the two-stage process”, IEEE Trans. Nucl. Sci., NS-37, 6, 1624 (1990). N.S. Saks and D.B. Brown, “Effects of switched gate bias on radiation-induced interface trap formation”, IEEE Trans. Nucl. Sci., NS-38, 6, 1130 (1990). D.M. Schmidt, D.M. Fleetwood, R.D. Schrimpf, R.L. Pease, R.J. Graves, G.H. Johnson, K.F. Galloway and W.E. Combs, “Comparison of ionizing radiation-induced gain degradation in lateral, substrate and vertical PNP BJTs”, Trans. Nucl. Sci., NS-42, 6, 1541 (1995). D.M. Schmidt, A. Wu, R.D. Schrimpf, D.M. Fleetwood and R.L. Pease, “Modeling ionizing radiation induced gain degradation of the lateral PNP bipolar junction transistor”, Trans. Nucl. Sci., NS-43, 6, 3032 (1996). W. Schockley, Phys. Rev., 56, 10, 317 (1939). R.D. Schrimpf, “Recent advances in understanding total-dose effects in bipolar transistors”, Proc. RADECS-95 and IEEE Trans. Nucl. Sci., NS-43, 3, 787 (June 1996). J.R. Schwank and D.M. Fleetwood, “Effect of post-oxidation anneal temperature on radiationinduced charge trapping in metal-oxide-semiconductor devices”, App. Phys. Lett. 53, 9, 770 (Aug. 1988). James R. Schwank, “Space and Military Radiation Effects in Silicon-On-Insulator Devices”, 1996 All references are unclassified

III-112

[SEI] [Sext-85] [Shan-83] [Shan-90]

[Shan-91] [Shan-98] [Shar-94] [Shaw-95]

[SIA-98] [Srou-76] [Srou-77a] [Srou-77b]

[Stah-93]

[Sun-80] [Sven-78] [Tamm-32] [Tayl-82] [Terr-89]

[VanL-75] [VanL-80] [VanV-95] [Vasu-94] [Wang-75] [Warr-92] [Warr-94]

[Wino-84]

[Wino-85]

IEEE International SOI Conference Short Course. Space Electronic Inc., San Diego, USA, www.spaceelectronics.com and TID Calculator (1998). F.W. Sexton and J.R. Schwank, “Correlation of radiation effects in transistors and integrated circuits”, IEEE Trans. Nucl. Sci., NS-32, 6, 3975 (1985). Z. Shanfield, “Thermally stimulated current measurements on irradiated MOS capacitors”, IEEE Trans. Nucl. Sci., NS-30, 6, 4064 (1983). M.R. Shaneyfelt, J.R. Schwank, D.M. Fleetwood, P.S. Winokur, K.L. Hughes and F.W. Sexton, “Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices”, IEEE Trans. Nucl. Sci., NS-37, 6, 1632 (1990). M.R. Shaneyfelt, D.M. Fleetwood, J.R. Schwank and K.L. Hughes, “Charge yield for Cobalt-60 and 10-keV x-ray irradiations of MOS devices”, IEEE Trans. Nucl. Sci., NS-38, 6, 1187-1194, (1991). M.R. Shaneyfelt, P.E. Dodd, B.L. Draper and R.S. Flores, “Challenges in hardening technologies using shallow-trench isolation”, IEEE Trans. Nucl. Sci., NS-45, 6, 2584 (1998). R.E.Sharp et D.R.Garlick, “Radiation Effects on Electronic Equipement, a Designers/Users’ Guide for the Nuclear Power Industry”, Radiation Testing Service of AEA Technology (January 1994). D.C. Shaw, G.M. Swift and A.H. Johnston, “Radiation evaluation of an advanced 64 Mb 3.3V DRAM and insight into the effects of scaling on radiation hardness”, IEEE Trans. Nucl. Sci., NS-42, 6, 1674 (1995). “The National Technology Roadmap for Semiconductors. Technology Needs”. SIA Semiconductor Association, San Jose, CA, (1997-1998) and www.semichips.org.. J.R. Srour, S. Othmer, O.L. Curtis and K.Y. Chiu, “Radiation-induced charge transport and charge build-up at low temperature”, IEEE Trans. Nucl. Sci., NS-23, 6, 1513 (1977). J.R. Srour and K.Y. Chiu, “MOS hardening for low-temperature applications”, IEEE Trans. Nucl. Sci., NS-24, 6, 2140 (1977). J.R. Srour, S. Othmer, O.L. Curtis and K.Y. Chiu, “Ionizing radiation effects on silicon-on-sapphire devices and silicon dioxide films”, Harry Diamond Laboratories report n° HDL-CR-77-090-1, Adelphi, MD, U.S.A. (1977). R.E. Stahlbush, A.H. Edwards, D.L. Griscom, B.J. Mrstik, “Post-irradiation cracking of H2 and formation of interface states in irradiated Metal-Oxide-Semiconductor field effect transistors”, J. Appl. Phys., 73, 658 (1993). S.C. Sun and J.D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces”, IEEE Trans. Electron Dev., ED-27, 1497 (1980). C.M. Svensson, Proc. Intl. Conf. On Physics of SiO2 and its interfaces (Pergamon, NY 1978), p. 328. I. Tamm, Z. Phys., 76, 849, (1932) and 3, 34 (1933) cit. Th. Wolkenstein, (Mir Edit., Moskow, 1973). D.M. and T.P.T. Williams, “The dynamics of space-charge accumulation in irradiated MOS capacitors”, Journal of Physics D: Appl. Phys. 15 , 2483-2493 (1982) (printed in UK). J.M. Terrell, T.R. Oldham, A.J. Lelis, H.E. Boesch and J.M. Benedetto, “Time-dependent annealing of radiation-induced leakage currents in MOS devices”, IEEE Trans. Nucl. Sci., NS-36, 6, 2205 (1989). V.A.J. Van Lint, G. Gigas and J. Barengolt, “Correlation of displacement effects produced by electrons, protons and neutrons”, IEEE Trans. Nucl. Sci., NS-22, 6, 2663 (1975). V.A.J. Van Lint, T.M. Flanagan, R.E. Leadon, J.A. Naber and V.C. Rodgers, “Mechanisms of radiation effects in electronic materials”, Vol 1, John Wiley, NewYork (1980). N. van Vonno, “Advanced Test Methodology”, 1995 IEEE NSREC Short Course. V. Vasudevan and J. Vasi, “A two-dimensional numerical simulation of oxide charge build-up in MOS transistors due to radiation”, IEEE Trans. Electron Devices, ED-41, 3, 383 (1994). C.T Wang, B.S.H. Royce and T.J. Russel, “The effect of ion implantation on charge storage in MOS NS-22, 6, 2168 (1975). W.L. Warren et al., J.ECS, 199, 872 (March 1992). W.L.Warren, D.M.Fleetwood, M.R.Shaneyfelt, J.R.Schwank and P.S.Winokur, “Links between oxide, interface, and border traps in high-temperature annealed Si/SiO2 systems”, Appl. Phys. Lett. 64 (25), (1994). P.S. Winokur, J.R. Schwank, P.J. McWhorter, P.V. Dressendorfer and D.C. Turpin, “Correlating the radiation response of MOS capacitors and transistors”, IEEE Trans. Nucl. Sci., NS-31, 6, 1453 (1984). P.S. Winokur, E.B. Erret, D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, “Optimizing and All references are unclassified

III-113

[Wino-92] [Wino-94]

[Witz-96]

[Witz-98]

[Zupa-93]

controlling the radiation hardness of Si-gate CMOS process”, IEEE Trans. Nucl. Sci. NS-32, 6, 3954 (1985). P.S. Winokur, “Total-Dose Radiation Effects”, 1992 IEEE NSREC Short Course. P.S. Winokur, M.R. Shaneyfelt, T.L. Mesenheimer, D.M. Fleetwood, “Advanced qualification techniques” , RADECS-93 Conference, IEEE catalog number 937H0616-3 p. 289, and IEEE Trans. Nucl. Sci., NS-41, 4, 538 (June 1994) (in English), “Techniques avancées de qualification , L'Onde Electrique, Vol. 75 n°3, 20 (mai 1995) (in French). S. Witzack, R.D. Schrimpf, K.F. Galloway, D.M. Fleetwood, R.L. Pease, J.M. Puhl, D.M. Schmidt, W.E. Combs and J.S. Suehle, “Accelerated tests for simulating low dose rate gain degradation of lateral and substrate PNP bipolar junction transistors”, IEEE Trans. Nucl. Sci. , NS-43, 6, 3151 (1996). S. Witzack, R.C Lacoe, D.C. Mayer, D.M. Fleetwood, R.D. Schrimpf and K.F. Galloway, “Space charge limited degradation of bipolar oxides at low electric fields”, IEEE Trans. Nucl. Sci., NS-45, 6, 2339 (1998). D. Zupac, K.F. Galloway, P. Khosropour, S.R. Anderson, R.D. Schrimpf and P. Calvel, “Separation of effects of oxide-trapped charge, interface trapped charge on mobility in irradiated power MOSFETs”, IEEE Trans. Nucl. Sci. , NS-40, 6, 1307 (1993).

All references are unclassified

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1999 NSREC SHORT COURSE

SECTION IV

PROTON EFFECTS AND TEST ISSUES FOR SATELLITE DESIGNERS

Paul W. Marshall Consultant Cheryl J. Marshall NASA/Goddard Space Flight Center

IV. Proton Effects and Test Issues for Satellite Designers General Introduction This portion of the Short Course is divided into two segments to separately address the two major proton-related effects confronting satellite designers: ionization effects and displacement damage effects. While both of these topics are deeply rooted in “traditional” descriptions of space radiation effects, there are several factors at play to cause renewed concern for satellite systems being designed today. For example, emphasis on Commercial Off-The-Shelf (COTS) technologies in both commercial and government systems increases both Total Ionizing Dose (TID) and Single Event Effect (SEE) concerns. Scaling trends exacerbate the problems, especially with regard to SEEs where protons can dominate soft error rates and even cause destructive failure. In addition, proton-induced displacement damage at fluences encountered in natural space environments can cause degradation in modern bipolar circuitry as well as in many emerging electronic and opto-electronic technologies. A crude, but nevertheless telling, indication of the level of concern for proton effects follows from surveying the themes treated in papers presented at this conference. The table lists themes found in the IEEE Transaction on Nuclear Science (TNS) December issue from the past year and compares them with the December issue’s content a decade earlier. Ten years ago there were nine papers, or about 10% of the total, dealing with the four indicated topics. At that time, single event effects from protons were the primary concern, and these were thought to be possible only when a nuclear reaction initiated energetic recoil atoms. This is shown in the table as the ‘traditional” SEE subject. A decade later, submissions addressing this topic had doubled, while papers devoted to displacement damage studies had increased from one to nine! More importantly, displacement damage effects in the natural space environments have become a concern for degradation in modern devices (other than solar cells), and this was not so ten years earlier. Table: Growth of concern for proton effects over the past decade Topic IEEE TNS, Vol. 35, No. 6, 1988 IEEE TNS, Vol. 45, No. 6, 1998 Environments 1 5 Dosimetry 4 2 Displacement Damage 1 9 “Traditional” SEE 3 6 New Effects 4 Total 9 (~10% of total) 26 (~30% of total) In the recent Transactions, four papers were devoted to effects that were either unknown or considered unimportant a decade earlier. These include soft errors from direct ionization by protons [Mars-98, Reed-98] and from nuclear elastic scattering events [Ingu-97, Savage-98, Johnston-98], along with hard failure SEE mechanisms such as latch-up [Norm98] and dielectric breakdown in power MOS devices [Titu-98]. The aggregate level of

IV-1

concern is obvious with a total of 26 papers, or about one third of the articles, in the 1998 December TNS dealing substantially with proton-related issues. In this Short Course segment we will attempt to survey the important developments that have taken place in the past few years. The material we cover emphasizes the developments affecting design tradeoffs for current satellite systems with the recognition that any given component can potentially be used so long as the risks are identified adequately and mitigated appropriately. We approach this task by citing the studies that identify the various effects that protons can have, and then by indicating and demonstrating the tools available to radiation effects experts and knowledgeable designers to quantify the associated risks. To place the material in the context of the needs of the satellite design engineer, we offer the following list of reasons that might motivate the need for proton testing of a given device or circuit. Reasons to test with protons: 1. Expect proton SEEs and have no satisfactory means of predicting response without proton test data. • Have no SEE data on part type and need to characterize for a proton rich environment • Have heavy ion SEE data and correlation approaches indicate “marginal” performance • Need to gain general idea of heavy ion sensitivity and have package penetration test issues • Suspect a sensitivity to direct ionization induced SEEs from protons (e.g., optocouplers) • Need to assess sensitivity to destructive failure (e.g., latch-up) from protons 2. Expect proton displacement damage and have no satisfactory means of predicting response without test data. • Have no displacement damage data on part type and need to characterize for a proton rich environment • Need to verify response on flight-lot devices where lot-to-lot variations can be large (e.g., COTS) • Have neutron data and correlation approaches indicate “marginal” performance • Need to measure a “damage function” energy dependence to reduce uncertainty associated with predictive tools • Mixed damage and TID from protons in application indicates need for proton tests 3. Need to assess TID response to proton-induced dose with high precision (e.g., calibration of p-MOS dosimeters)

Following the major division indicated in the above list, the subject material for this section of the course is divided into two segments with Part A devoted to ionization effects and Part B to displacement damage effects. The section on ionization effects addresses the environment and satellite configuration considerations to identify scenarios where proton dose can play an important role in TID effects. Proton-induced single event effects occurring from IV-2

either direct ionization or generation of reaction recoils will be included in this section, but the emphasis will be on more recent studies describing new sensitivities to proton-induced ionization events. The reader will be referred to previous Short Course notes and related literature for discussions of mechanisms and rate calculations for “traditional” proton SEE and TID concerns, with the exception of two case studies. These two studies examine special concerns for modern communications satellite constellations that route high-speed signals. The section on displacement damage considers the numerous device types exhibiting sensitivity to displacement effects. The primary tools, like the concept of Non-Ionizing Energy Loss (NIEL), now used to treat proton-induced displacement effects have been mostly developed within the past decade. This section addresses the justifications, methodology, and associated uncertainties in applying these tools to various classes of Si-based devices as well as emerging III-V technologies for electronic and opto-electronic applications. Emphasis will be given to satellite environments, including shielding efficacy and tradeoffs. Our goal is to capture the current understanding of the many proton-related concerns important to the satellite subsystem engineer. At the beginning of the first section on ionizing effects, a top-level treatment of the environments internal to satellites will be provided, along with references to previous Short Course discussions for additional detail. The emphasis of the remaining material throughout both sections is on the effects, tools, and associated information to enable informed tradeoffs of design options.

IV-3

Section IV. Proton Effects and Test Issues for Satellite Designers Part A: Ionization Effects Paul W. Marshall 7655 Hat Creek Road Brookneal, VA 24528

Cheryl J. Marshall NASA Goddard Space Flight Center Code 562 Greenbelt, MD 20771

1.0 Introduction………………………………………………………………………………6 2.0 Proton Environments for Satellites………………………………………..……….…... 6 2.1 Environment Description and Issues……………………………….….………. 6 2.2 Example Proton Environment Description……………………………..……… 9 2.3 Requirements: Proton Specific Issues…………………………….…..………...13 2.3.1 Total Ionizing Dose…………………………………….…………...13 2.3.2

Destructive SEE……………………………………….…………… 13

2.3.3

Nondestructive SEE………………………………………..………. 13

2.3.4

Margin………………………………………………………………14

2.3.5

Nonstandard Parts and Waivers……………………………………14

2.4 Recent Updates to the Proton Environment Models……………………………15 3.0 Total Ionizing Dose and Protons………………………………………………………..16 3.1 Proton-Induced Total Ionizing Dose: Mechanisms and Issues…………………16 3.2 Is a rad always a rad? ………………………………………………………….. 18 3.2.1

Lateral Nonuniformities (LNUs) ………………………………….. 19

3.2.2

Electron-Hole Recombination…………………………………...… 20

IV-4

4.0 Proton-Induced Single Event Effects…………………………………………………...22 4.1 Test Issues and Special Cases………………………………………………….. 23 4.1.1 High Speed Technologies…………………………………………...24 4.1.2

Small Probability Events……………………………………………26

4.1.3

Single Event Transients in Linear Devices………………………… 27

4.1.4

Correlation Between Proton and Heavy Ion SEE Sensitivities……. 28

4.2 Proton Direct Ionization and SEEs…………………………………………….. 29 4.2.1

CCDs ……………………………………………………………….29

4.2.2

Optical Link Photodetectors……………………………………….. 31

4.2.3

Optocouplers and MSM Photodiodes……………………………… 36

4.3 Destructive Failures from Single Proton Interactions…………………………. 39 4.3.1

Latch-Up (and COTS) …………………………………………….. 39

4.3.2

Proton-Induced Single Event Burnout….………………………….. 40

4.3.3

Stuck Bits…………………………………………………………... 41

5.0 Summary……………………………………………………………………………..… 43 6.0 Acknowledgments………………………………………………………………………43 7.0 References for General Introduction and Section IVA…………………………………44

IV-5

SECTION IVA: IONIZATION EFFECTS Paul W. Marshall and Cheryl J. Marshall 1.0

INTRODUCTION

This first segment covers various ways in which proton-induced ionization can affect circuit operation. For our purpose, this includes TID effects as well as both direct and indirect single event phenomena. Before addressing the device and circuit effects, we offer a brief overview of the near-Earth proton environments and issues impacting the environment description internal to the satellite. This section also provides examples and discusses issues concerning the generation of design requirements based on the expected environment. Following the environment section, we offer a brief discussion of proton-specific concerns for TID effects. Next, the fourth section examines soft errors due to protons, again with emphasis on recent developments, and the fifth section looks at hard errors.

2.0

PROTON ENVIRONMENTS FOR SATELLITES

Protons occur in every imaginable orbit with variations in spectral energy composition, arrival rates, and sometimes arrival trajectories. The three sources are trapped protons in the inner Van Allen radiation belt, the proton component of solar particle events, and hydrogen nuclei from intergalactic cosmic rays. Careful discussions of the near-Earth, interplanetary, and other planet proton environment models are available in the Conference Short Course notes from 1997 [Bart-97]. The interested reader should refer to those notes and the cited literature to gain an understanding of the characteristics and shortcomings of the widely used NASA AP-8 [Sawy-76] model for trapped protons, the CREME-96 [Tylk-96] cosmic ray model, and various descriptions of solar proton probability models. These models should be viewed only as working approximations aimed at describing the major features of the external environment with the recognition that both the subtleties and major features of the environments are the concern for numerous space-borne experiments and ongoing modeling efforts.

2.1 Environment Description and Issues With regard to the range of proton environments and the factors affecting them, the basic models cited above are the predictive tools of the environment specialists. The 1997 Short Course by Janet Barth [Bart-97] offers an excellent discussion of these and several other models, their applicability, issues affecting their accuracy, and the proton environments as they change with orbital position and solar cycle period. Detailed treatment is outside the scope of this material, but in addition to those notes, interested readers may wish to locate the 1988 review article “The Natural Radiation Environment Inside a Spacecraft,” [Stass-88] or this conference’s Short Course notes on “Radiation Environments in Space” [Stass-90]. For quick reference, the general character of the trapped proton belts external to the spacecraft is provided here as figure 1.

IV-6

Figure 1. The AP-8 model for solar minimum conditions at 0 degrees inclination indicates the higher energy protons at lower altitudes [after Stass-88]. The orbit altitude in km is related to dipole shell as [(L x 6370 km)-6370 km] where 6370 km is the Earth’s radius.

There is a document in development to supplement the various radiation models with practical considerations for satellite applications and make general trends more accessible to design engineers. The IEEE (Draft) Standard 1156.4 [IEEE-1156.4] document is aimed at establishing generic descriptions of four orbit categories: Low Earth Orbit (LEO) below about 10,000 km, Medium Earth Orbit (MEO) from 10,000 to 20,000 km, Geostationary Orbit (GEO) at 36,000 km, and transfer or Highly Elliptical Orbit (HEO). This document identifies example orbits in each of these categories and illustrates proton and other radiation characteristics of those orbits for the purpose of ionizing (but not displacement) effects in space-borne computers. Be warned though, that these are only examples and there is no justification to generalize from those orbits even to other orbits within the same category. For the designer, detailed understandings of the environment models are fortunately not usually necessary. Instead, the proton and other radiation related requirements are either supplied by the procuring organization or generated “in house” by resident radiation environment experts. Several years ago, it was not uncommon to see radiation design specifications expressed in terms of total ionizing dose (or depth-dose curves) supplemented with either Linear Energy Transfer (LET) spectra or guidance with respect to LET threshold for single event induced hard errors and upset rates from cosmic rays. Proton contributions to IV-7

the depth-dose may have been identified, but often there was no breakout of the expected proton energy spectra and fluxes. In many cases, it was assumed that components that could be upset by protons would be screened out by the requirement for a high threshold LET for cosmic ray effects. With today’s emphasis on high performance systems and the component selections now available, all that has changed. Now a more reasonable assumption would be that proton effects are expected, and part of the designer’s task is to manage the associated risk. Increasingly, it is the responsibility of the design team to assess radiation-related risk, and proton effects are often an important part of this equation. There is still quite a variation in the level of detail called out in the proton environment description provided to the design effort. It usually contains some, but rarely all, of the following elements: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

trapped proton total ionizing dose contribution to a depth-dose relation trapped proton energy spectra behind typical shield thickness peak trapped proton flux with energy composition (in orbit “hot spot”) average daily trapped proton flux mission fluence for protons > 25 MeV (or some other cutoff) solar particle event (SPE) proton energy spectrum with fluence per mission peak (worst case) proton flux from SPE with energy composition assumed frequency of occurrence of design case SPE cosmic ray LET spectrum including proton contributions variations on each of the preceding to reflect solar cycle related changes variations on each of the preceding to reflect uncertainties and design margins

There are no standardized formats for identifying either the proton environments or the radiation-related requirements for proton effects. The preceding list offers several environment descriptions that are commonly seen in various combinations. Often, the intention is to identify TID levels, a mission-duration proton spectrum for SEE and possibly displacement damage concerns, and a peak flux (or fluxes) for use in assessing peak SEE rates. Item ten in the list touches on the often seen practice of inflating the expected environment to add margin for various reasons, ranging from uncertainties in environment models to part-to-part response non-uniformity and response uncertainty. Margin will be discussed in a later section. In practice, the environments identified in many requirements documents do not always adequately specify the details needed to properly assess proton-related effects. This situation follows, in some part, from a natural lag between the identification of a given important effect (e.g., displacement damage in optocouplers, or proton upset response best described by a two parameter Bendel formalism as discussed later) and the recognition of the need to include detailed proton spectral information rather than just proton-induced rad(Si) and > 25 MeV fluences. Also, the timeline associated with procuring flight hardware may result in periods of years between the definition of the orbit environment description to the detailed design, and new effects, which may emphasize previously unimportant aspects of the environment, are continually identified. From the radiation effects perspective, it’s hard to overdo the level of detail in the environment description called out in a requirement. IV-8

2.2 Example Proton Environment Description As an example of the proton environment description in a program currently under way, the interested reader may examine the document SSP 30512 Rev. C entitled “Space Station Ionizing Radiation Design Environment” [SSP-30512]. This document, released in June of 1994, describes the ionizing radiation environment as calculated for the International Space Station Alpha (ISSA) at an altitude of 500 kilometers and inclination of 51.6 degrees. Five years later, it remains the reference environment description for hardware currently being designed for ISSA, and it has general applicability to the multi-national and multi-agency effort. We include this example because this program is of general interest and also because the proton environment description is unusually thorough. The descriptions of various proton environments for ISSA are contained in table 1. The first item accounts for most of the protons encountered in the low-Earth orbit. Though not indicated explicitly in any of the ten items, most of these protons will be encountered during passes through the South Atlantic Anomaly (SAA). The average daily proton flux predicted in this table is calculated by using the AP-8 model for solar maximum conditions and shown below in integral form as figure 2. In table 1 the second and third listings address the depth-dose relation and are included here since protons account for a portion of the total ionizing dose. Figure 3 shows the relative annual dose contributions for electrons and protons at the center of a solid aluminum sphere. The chart indicates how protons dominate the TID for shield thicknesses greater than about 200 mils Al, and this result is typical of most orbits that encounter the trapped proton belts. Careful inspection of the proton curve illustrates how ineffective shielding is for stopping protons. Note the steep falloff in the electron dose with increasing depth and the relatively flat character of the proton curve. Increasing the shield thickness form 100 to 1000 mils only reduces the resulting dose by about 50%. For this reason, and others discussed later, shielding is often not the best technique for minimizing proton effects. Table 1: List of tables describing proton-related environments for ISSA [SSP-30512] Item Table Description 1 3.1.1-2 AP8MAX differential and integral flux energy spectra for trapped protons 2 3.1.2-1 One year dose at the center of a solid aluminum sphere (rads(Si)) 3 3.1.2-2 One year dose in semi-infinite aluminum medium (rads(Si)) 4 3.2.1.1-1 Daily average internal proton integral flux spectrum 5 3.2.1.1-2 Daily average internal proton differential flux spectrum 6 3.2.1.2-1 SAA pass internal peak proton integral flux spectrum 7 3.2.1.2-2 SAA pass internal peak proton differential flux spectrum 8 3.2.1.4-1 Combined integral flux LET spectra (WI1=4) no solar flare flux 9 3.2.2-1 Maximum solar flare peak proton integral flux spectrum 10 3.2.2-2 Maximum solar flare peak proton differential flux spectrum 1 WI = weather index

IV-9

AP8-MAX Integral Flux for ISSA 1.0E+08

Integral Flux (p+/cm2/day)

1.0E+07 1.0E+06 1.0E+05 1.0E+04 1.0E+03 1.0E+02 1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

Proton Energy (MeV) Figure 2. Integral daily proton flux for the example International Space Station Alpha orbit of 500 km x 51.6 degrees shows the large numbers of low energy protons that are easily shielded. Fluxes in the tens to hundreds of MeV can penetrate to sensitive components resulting in single event effects and both ionizing dose and non-ionizing dose.

Dose (rads (Si/year)

1.E+05 1.E+04

Proton Dose (rad(Si)) Electron Dose (rad(Si))

1.E+03

Total Dose (rad(Si))

1.E+02 1.E+01 1.E+00 1.E-01 10

100

1000

10000

Shield Thickness (mils Al) Figure 3. For the 500 km x 51.6 degree orbit for ISSA, the dose from trapped protons dominates for Al shield thicknesses above 200 mils. With increasing shield thickness, the average proton energy increases. IV-10

The fourth and fifth items in table 1 provide detailed information on spectral energy composition for aluminum shield thicknesses of 0, 50, 500, 1000, 2000, 4000, and 7000 mils. The inclusion of predictions for very thick shielding is appropriate for the manned bays in ISSA, but is atypical for unmanned vehicles. Items six and seven in table 1 address the peak proton flux expected from trapped protons during passages through the South Atlantic Anomaly. Note that the peak flux occurring due to trapped protons is almost always lower than the peak flux due to solar particle events, with the exception being low inclination LEO orbits. However the SAA is encountered on about 50% of ISSA orbits (several times a day) as opposed to the relatively rare solar events. In this case, the peak from SAA trapped protons, integrated over energies > 10 MeV, is 2.04 x 103 p/cm2/s, which is 54 times the orbitaveraged rate. Table 1, items nine and ten describe the modeled peak rates corresponding to solar particle events, including effects of the Earth’s geomagnetic shielding. Data listed in these tables indicate an expected peak (for design purposes) of 3.36 x 105 p/cm2/s. This is 165 times the peak rate during SAA passages. This event would be expected, as described in [SSP-30512], once per 11 year solar cycle, or approximately once per mission for ISSA. Peak proton arrival rates for a given mission cannot be predicted in a deterministic manner. The use of the October 1989 flare as a design environment, shown in figure 4, for ISSA is a somewhat arbitrary choice. Other options exist, including other peak solar particle models incorporated in CREME-96 [Tylk-96, Tylk-96a]. More recently, a probabilistic model for predicting peak flux based on solar cycles 20, 21, and 22 has been proposed [Xaps98], and this allows a more quantitative approach to assessing the risk of exceeding a given proton flux. Please see the discussion of peak SPE proton rates in the 1997 Short Course notes [Bart-97] for more information and discussion on this topic. The eighth table entry (combined integral flux LET spectra (weather index=4) no solar flare flux) describes the cosmic ray design environment for ISSA in terms of the LET spectrum from heavy ions. We acknowledge that for orbits encountering the trapped proton belts there are relatively few cosmic ray protons. However, for devices (e.g., detectors) sensitive to single events from proton ionization, cosmic ray protons may be a concern. Hydrogen ions (protons) are after all the most abundant constituent of the composite cosmic ray spectrum, and they account for 83% of all cosmic rays outside the effects of the Earth’s magnetic field. Figure 5 indicates the composite LET spectrum with two shield thicknesses for ISSA. In terms of LET, protons account for only about 1 in 105 incident particles at the lowest LET value shown in the figure (0.1 MeVcm2/mg). Though not shown, at LET values of 0.01 MeVcm2/mg and 0.001 MeVcm2/mg proton contributions increase to 0.5% and 88% respectively. If lower LET values are important, then the proton component of cosmic rays may dominate. Most cosmic ray protons are very energetic and shielding has little effect. For the ISSA environment definitions, proton spectra are provided with various shield thicknesses. Not all design efforts provide this level of detail, and it is often necessary to modify the provided spectra to evaluate the detailed effects of additional shielding. Several transport code based routines are available to provide spectra and sometimes dose behind additional shielding. The capability and complexity of these tools cover a broad range from transport through relatively simple spherical or slab single thickness to full-up ray tracing and IV-11

Maximum Solar Proton Flux for ISSA

0 MILS AL 50 MILS AL 500 MILS AL

1.E+10

2

Integral Flux (p /cm /day > E)

1.E+11

+

1.E+09

1.E+08

1.E+07

1.E+06 0

100

200

300

400

500

600

700

Proton Energy (MeV)

Figure 4. Peak solar proton flux from the October 1989 event, as propagated into the 500 km x 51.6 degree Space Station orbit, shows that less than a third of the protons reaching that orbit are stopped by 50 mils Al shielding. Also note that some protons above 400 MeV are present, in contrast to the trapped belt models.

Integral Flux (particles/cm2/day > LET)

ISSA Cosmic Ray Environment 1.0E+06 50 MILS AL 500 MILS AL

1.0E+03 1.0E+00 1.0E-03 1.0E-06 1.0E-09 1.E-01

1.E+00

1.E+01

1.E+02

LET (MeVcm2/mg)

Figure 5. Proton contributions to the cosmic ray environment at 500 km and 51.6 degrees are included in the heavy ion LET spectrum. They account for 87% of all particles at an LET of 0.001 MeVcm2/mg, but only .002% at the lowest LET shown in the chart. IV-12

high-density sector calculations. Additional discussion and a list of references are provided in the 1998 Short Course notes from this conference in section V part 3.1 [Kinn-98]. These tools play an important role in determining the dose or associated proton spectra at the box and component level. Usually, after surrounding boxes and satellite structural elements are considered, the resulting exposure at the subsystem and device level is less than that for a 100 mil Al spherical shield. However, the protection offered by structural shielding is of much less benefit than in the case of electron exposure because of the penetrating nature of protons.

2.3 Requirements: Proton Specific Issues Expressions of requirements vary greatly from program to program. Top level requirements usually address performance of a system in a specified environment in terms of system lifetime, availability to perform mission objectives, and accuracy in meeting those objectives. At this level proton effects, along with other radiation effects, are only part of the reliability picture. From this level, system engineers usually arrive at a set of derived requirements that are applied to individual subsystems. These will likely address destructive failures, TID failure levels, and possibly soft error rates. Most often proton effects are lumped together with associated effects from other radiation sources. More recently, with the increasingly important role of displacement effects, proton levels may be specified explicitly for component types known to be susceptible to proton-specific effects, such as optocouplers, Charge Coupled Devices (CCDs), and others. 2.3.1 Total Ionizing Dose: TID requirements for a given mission are usually based on the composite electron-proton dose based on the depth-dose relation for the given mission. TID evaluations are customarily made using Co-60 test facilities with the assumption that there is a linear superposition of dose from protons and electrons (this assumption will be examined in a section IVA.3). 2.3.2 Destructive SEE: Similarly, for the case of single events effects resulting in hard failure, requirements for proton-related failure modes are rarely specified separately from heavy ion induced failure, though they sometimes should be. In practice however, extreme measures are usually taken to avoid hard failure, including the requirement that hard failures (e.g., latch-up) may not occur below the iron cutoff (or some higher LET value) of the heavy ion LET spectrum. If such measures are taken, then proton-induced hard failure will also be avoided, since proton sensitivity to SEEs is not expected where such high LET threshold values apply. Unless such assurances are in place, we suggest that requirements should be written to address the possibility of hard failures due to protons. In LEO applications of commercial power MOSFETs, for example, flight data has demonstrated that burnout is much more probable from protons than from heavy ions, even though the orbit inclination is 700 [Bart-98]. Expression of a requirement in terms of only LET would therefore be inadequate. Associated issues will be addressed in section 4.3.2 on Single Event Burnout (SEB). 2.3.3 Nondestructive SEE: It is more common for requirements to address proton-induced soft errors, at least indirectly, through the expression of requirements for average and peak error rates. Historically, this issue arose due to soft errors in memories, but in recent years the IV-13

literature (and unpublished flight data) provides many cases of microprocessors, ASICs, linear circuits, ADCs, detectors, and other components which exhibit sensitivity to soft errors from protons. Typically, requirement documents call for a level of performance, and it is the job of the box manufacturer to allocate error rates due to various expected sources. For orbits encountering the inner belts, protons often dominate average soft error rates in technologies sensitive to their effects. Where error rates are required to stay below some allowed maximum, the peak trapped proton flux and peak solar particle event fluxes represent the greatest challenges. For orbits outside of the proton belts, such as geostationary at 36,000 km, average proton arrival rates may be extremely low, but proton upset sensitivity can be a design driver with the infrequent solar particle event in mind. 2.3.4 Margin: Design margins arise from a variety of concerns and are expressed in a variety of ways, with some of these concerns specific to protons. Where large uncertainties exist either in the ability to predict the environment with high confidence or in the ability to predict circuit response, margin is applied to mitigate risk. In fact, the degree of margin is often scaled according to the criticality of the function being performed with the idea that survival is most important and some mission objectives are more important than others [e.g., Gate-96]. One of the sources of uncertainty is in the environment models. As an example, for trapped protons, the 23 year old AP-8 model has served to establish average and peak proton fluxes as well as proton dose for the radiation belts. The uncertainty associated with that model is stated to be a factor of two for long term orbit averages and higher for short duration periods (e.g., less than 1 year) [Sawy-76]. Therefore, it is appropriate to either double the predicted trapped particle environment or impose margin on the ability of the system to perform in the predicted environment. System designers frequently employ either approach. New information impacting the uncertainty of the AP-8 model is discussed in section 2.4. Uncertain device response and the inability of imperfect predictive models to accurately describe performance also call for radiation design margin. These factors can be quite large, especially where the key variables governing device response are not well understood. In the portion of this Short Course segment concerning displacement damage we will illustrate this point for the cases of CCD damage and optocoupler degradation. Design margins of over two are warranted in each of these situations. After factoring in more customary arguments for margin (e.g., part-to-part and lot-tolot differences in response) the suggestion of additional factors of two or greater for each of these other proton specific sources usually comes as quite a shock to the design engineer. Resolution of these issues varies from program to program, usually with some element of compromise and the hope that either the components easily meet the requirements with margin or the design can be modified to accommodate the anticipated degradation. It is important that both the radiation effects specialist and the design engineer realize the needs for margin and not fall into the trap of assuming that the factor of 2 applied for environment uncertainty also accommodates uncertainties from other sources such as the response model. 2.3.5 Nonstandard Parts and Waivers: Every flight project design effort tracks parts that do not meet requirements with margin or that require “special” considerations. Often, IV-14

additional testing is required and special considerations are needed to evaluate risk. Nowadays, with the emergence of displacement damage concerns in Light Emitting Diodes (LEDs), optocouplers, and CCDs, many proton radiation effects are dealt with in this forum. As specifications of proton environments and requirements improve, along with predictive models for the environments and device responses, these issues will likely be dealt with on a more routine basis and factors indicating needs for large design margins can be minimized. However, for now, many proton effects are only beginning to work their way into the concerns of the typical design effort. Proton testing is still viewed as an expensive alternative to be used sparingly. In many cases the details of defining proton test approaches and deciding on acceptable margins falls within the scope of “nonstandard parts evaluation” efforts. Resolution of these issues can present a significant set of interesting challenges.

2.4 Recent Updates to the Proton Environment Models The preceding discussions have identified many of the proton environment models now being used, and indicated references for additional information. There are however a few key points to make regarding the dynamic status of the environment models. Janet Barth, in the 1997 Short Course notes [Bart-97], includes a section entitled “Problems with the AP-8 and AE-8 Models,” and she follows this with a section entitled “Dynamic Models, A Beginning.” These notes are well worth reading to see the path toward revisions to the existing NASA models. Last year, at this conference, Houston and Pfitzer presented a paper entitled “A New Model for the Low Altitude Trapped Proton Environment,” [Hous-98]. This “new model” is based on data acquired by instruments on the TIROS/NOAA spacecraft from 1978 through 1995. The key finding, from the satellite designer’s perspective, is that the predicted fluxes are about twice as high as those from the AP-8 model, as indicated in figure 6. This finding seems to hold for proton energies of interest to satellite designers (> 16 MeV). The data cover the altitude range from 250-850 km. In conjunction with the CRESSPRO model [Meff-94], this significantly improves the empirical basis for major revision to the AP-8 model. The probabilistic model for SPE peak fluxes presented at the 1998 NSREC has already been mentioned [Xaps-98]. Environment specialists also rely on a probabilistic modeling tool for predicting solar proton fluences during a mission [Feyn-96]. J. Feynman and co-workers at JPL have performed a statistical analysis including data on solar particle event proton fluences from the past three solar cycles. Their findings show that the largest events, such as the August-72 and October-89 events, belong in the same statistical distribution as other events. They provide a Monte Carlo based tool for assessing probability of exceeding a given fluence level during a specified mission duration. This model is especially important for geostationary and interplanetary missions, and it has rapidly gained acceptance. The key point is that our understanding of even the gross features of the space radiation environment is not precise. Revisions and enhancements to the existing models are ongoing. IV-15

Figure 6. Recent dosimetry data from TIROS/NOAA satellites provide the basis for a revised model for trapped protons. The above figure and discussion in [Hous-98], by S.L. Houston and K.A. Pfitzer, indicate about twice the flux predicted by AP-8 for the three energy bins listed in the legend.

3.0

TOTAL IONIZING DOSE AND PROTONS

In this section we discuss several issues specific to total ionizing dose deposited by protons. Topics will include typical situations where proton-induced TID may be important to satellite systems, a discussion of the equivalence between proton dose and ionizing dose from other sources in the natural space environment, and finally a discussion of microdosimetry issues specific to protons. The emphasis will be on ionizing dose with the recognition that protons also deposit non-ionizing dose, which causes displacement damage. That is treated in the segment IVB of these notes.

3.1 Proton-Induced Total Ionizing Dose: Mechanisms and Issues As protons traverse a solid, their positive charge presents an electrostatic force to the orbital electrons of the surrounding material. Excited electrons are freed from their bound state thereby creating electron-hole pairs. Some of these electrons (called delta rays) are liberated with sufficient energy to interact with other electrons at some distance from the incident proton’s trajectory, thereby leading to an ionization track with some structure. This coulombic scattering process liberates electron-hole pairs at a rate that depends on the proton energy and also on the material it traverses. In Si, for example, the electron-hole pair creation requires (on average) 3.6 eV in energy from the incident proton. This empirically determined value is referred to as the ionization potential, and it depends on a number of factors including the material band-gap for the case of semiconductors. In insulators, ionization potentials are significantly larger, e.g., ~ 17 eV in SiO2. IV-16

LET and Range for Protons in Si 1.E+03 LET (MeV*cm2/mg) Range (cm Si)

1.E+01 1.E-01 1.E-01 1.E-02 1.E-03

1.E-05

1. 00 E 2. -02 80 E 1. -02 00 E 2. -01 80 E 1. -01 00 E 2. +00 80 E 1. +00 00 E 2. +01 80 E 1. +01 00 E 2. +02 80 E 1. +0 00 2 E+ 03

1.E-03

Range (cm Si)

LET (MeVcm 2/mg)

1.E+00

Proton Energy (MeV) Figure 7. Lower energy protons with higher LETs are effectively stopped in satellite structural materials due to their short ranges. Higher energy protons are very penetrating, but fortunately transfer their energy at a lower rate. These relations do not address nuclear reactions occur for higher energy protons (>10 MeV) with a probability of about 10-5 for a pathlength of a few microns in Si.

The rate of energy loss for a proton (or any heavy ion) is termed the Linear Energy Transfer (LET) or stopping power, and the usual units are MeVcm2/mg though it can be converted to energy per unit pathlength by multiplying by the target material density. Again, this is an empirically determined relation, and its dependence on proton energy, known as the specific ionization curve, is shown in figure 7 along with the relation between proton range and energy. Note that the LET tends to decrease with increasing energy in the MeV regime encountered within satellites. Also, as the proton loses energy, the decrease in range is highly nonlinear. These energy loss kinematics are the basis for the situation in which the low energy protons are preferentially stopped by spacecraft materials. When the naturally occurring spectrum encounters satellite materials, protons at all energies lose energy, but the mean proton energy reaching the payload electronics actually increases with increasing shield thickness. Along the trajectory of an individual proton, the path of ionization produces more and more electron-hole pairs per unit length until the proton approaches the end of its range. The LET actually peaks at an energy of about 80 keV in Si. This maximum in energy loss is often (inappropriately) referred to as the Bragg peak. IV-17

The precise details of energy loss are beyond the scope of this discussion, but it should be noted that proton dose is deposited along ionization tracks. On a micro-dosimetry scale the presence of these tracks leads to dose deposition that is therefore highly nonuniform in nature. In the following sections, ionization effects to electronic materials will be discussed and the inherent non-uniformity of proton dose on the microdosimetric scale will be placed into perspective by making comparisons to electron (or Co-60) dose deposition, which is much more uniform in nature. Finally, it should be noted that the coulombic electronic scattering mechanism is by far the dominant mechanism for ionization purposes and for affecting proton energy loss, but other processes do occur. Nuclear elastic and inelastic processes lead to some ionizing dose deposition, but these are orders of magnitude down from electronic scattering. By far their most important role in electronic materials is in imparting non-ionizing energy leading to atomic displacements. These processes are discussed in detail in Part B of this Short Course section. In the previous section on environments, it was noted that protons are encountered in all orbits. However, protons are significant contributors of TID only in certain cases. As indicated in figure 3, from the ISSA example in low-Earth orbit, the relative contribution of proton to electron dose increases with increasing shielding. The exact thickness at which proton dose becomes important varies with orbit. Proton dose may be a concern for low-Earth orbits or highly elliptical orbits that encounter the inner Van Allen belts, for orbits encountering high fluences from Solar Energetic Particle (SEP) events, or for missions reaching proton belts surrounding other planets. For circular orbits between about 1,500 and 5,000 km (the heart of the belts) the multi-year mission doses from protons can easily exceed 100 krad(Si). Whether in an orbit dominated by protons or one with mixed electron/proton exposures, the components most sensitive to TID effects are often buried deep in the spacecraft or protected with spot shielding. Consequently they may receive a substantial fraction of their dose from protons.

3.2 Is a rad always a rad? The widely accepted unit for total ionizing dose from ionizing radiation is the rad (from Radiation Absorbed Dose). The rad is defined as 100 ergs per gram of energy absorbed in the exposed material, and 100 rads is equal to 1 Grey (Gy). For the case of heavy ions (including protons), the exposure in rads is determined from the ion LET and the particle fluence according to equation 1. Note that the LET and corresponding dose for a given particle fluence are material dependent quantities. As an example, a 100 MeV proton has an LET in silicon of 5.93 x 10-3 MeVcm2/mg. For a fluence of 1 proton per square centimeter, the corresponding dose would be 9.5 x 10-8 rad(Si). This relation is depicted versus proton energy as figure 8.

(

)

 LET ( matl.) MeV ⋅cm2  ⋅  fluence⋅ 1  ⋅ 1.60⋅10−5⋅mg⋅rad = X ⋅ rad ( matl.)     mg MeV    cm2 

IV-18

[1]

Dose per Unit Fluence for Protons in Si Dose (rad[Si]/proton/cm 2)

1.0E-05

1.0E-06

1.0E-07

1.0E-08 1

10

100

1000

Proton Energy (MeV) Figure 8. On average, each proton deposits dose according to its LET and the relation expressed in equation 1. The dependence in the above figure describes dose deposition from protons in silicon.

The basis for the use, or even the existence, of the rad is that the effects of the ionizing radiation in question, whether it be electrons, photons, protons, or other ions, will be equivalent for a given amount of adsorbed dose, irrespective of the radiation source. The radiation effects community has examined this assumption for several important cases, for example, the equivalence of 10 keV x-rays and Co-60 dose and the role of secondary electronic equilibrium at material interfaces. In the following paragraphs, we consider two microdosimetry issues that are specific to proton dose. 3.2.1 Lateral nonuniformities (LNUs): The term LNU in the context of radiation damage in MOS transistors describes the nonuniform distribution of holes in gate oxides. The initial papers addressing the phenomenon are cited in [Frie-88]. This paper describes a detailed investigation of the causes and effects; especially the false indication of interface state production using the subthreshold method when applied under cryogenic conditions. All of the initial work assessed the role of LNUs in gate oxides that were exposed to either Co-60 gamma rays or 10 keV x-rays. In the paper by Frietag, et al., a statistical formalism for the analysis of microscopic fluctuations in dose was introduced and applied to describe the behavior of the subthreshold current. The following year the microdosimetry formalism from [Frie-88] was invoked and modified to treat the problem of LNUs arising from proton damage using a two component model [Xaps-89]. Conceptually, the problem of nonuniform dose deposition from protons might be suspected to cause significant effects when small geometries are considered such as in thin gate oxides. After all, there is a track structure, at least in the initial dose deposition. While the data and analyses presented in [Xaps-89] do demonstrate measurable effects in subthreshold leakage current stretch-out at 77o K, perhaps the most remarkable result of this body

IV-19

of work lies in the fact that, at least to first order, the microdosimetric fluctuations in ionizing dose deposition from protons are unimportant to satellite electronics. 3.2.2 Electron-Hole Recombination: This issue concerns the fate of the electron-hole pairs produced as the proton loses energy in a material. For traditional TID effects, holes are the more important since either trapped oxide charge or interface state formation lead to parameter shifts in transistor performance. The unique characteristic of electron-hole production along ion tracks is that electron-hole pairs along ion tracks are in relatively close proximity to neighboring charge pairs as compared to those generated by photon or electron radiation sources. This close proximity can affect the charge yield for a given dose deposition through two mechanisms: geminate recombination and columnar recombination. Both recombination processes are well documented in literature extending back to the early 1900’s. For the case of protons incident on Si, [Oldh-84] established what is today recognized as the definitive study on these effects. This reference provides vectors to the relevant literature, including the model developed to assess these effects for ions simulating cosmic ray effects [Oldh-83]. The geminate recombination model applies to the situation in which electron-hole pairs are widely separated from other charge pairs and therefore more likely to interact and possibly recombine with each other. Columnar recombination applies to densely ionized tracks along which charge pairs are so dense, and recombination is as likely to occur with pairs initiated in separate events. Figure 9, reproduced from [Oldh-84], indicates the energy dependence of the two recombination models and shows comparisons with published data acquired on n-type silicon. The yield in figure 9 is fractional, and at high proton energies where the geminate model applies the yield is expected to be the same as with Co-60. Note that even at high proton energies the relative yield does not approach unity. Furthermore, at lower proton energies important to both space environments and to test facilities, the yield decreases dramatically with decreasing proton energy. Recall from figure 7 that the lower energies correspond to increased LET and therefore more densely ionizing track structure. The importance of proton dose in LEO missions notwithstanding, there have been few carefully controlled comparisons of Co-60 versus proton-induced TID response. A discussion of much of the relevant data is found in [Ma-89]. Investigation into p-MOSFET dosimeter response to proton dose has indicated similar behavior to that reported in [Oldh-84], but with indications of correlation between charge yield and electric field strength [Augu-82]. Figure 10, which is reproduced from the later work, indicates the relation between threshold voltage shift and gate bias on 1100 angstrom thick oxides for several different radiations, including 37 MeV protons. In [Stap-85], a clear trend was noted in the threshold voltage shifts of p-MOS transistors for the case of heavy ions versus literature data on Co-60. However, the comparison between Co-60 and 62 MeV protons showed no significant difference at a dose of 10 krad(Si). Recent comparisons of modern p-MOS dosimeters indicate similar behavior with a possible slight reduction is high energy proton response versus that from Co-60 [Peas-99]. Three papers have reported comparisons of photon versus proton-induced dose in devices other than p-MOS dosimeters. A careful experimental and modeling effort into the IV-20

1.0

YIELD

GEMINATE MODEL

0.1 SOFT OXIDES HARD OXIDES

COLUMNAR MODEL

0.01

1

10

100

PROTON ENERGY (MeV) Figure 9. This figure is reproduced from [Oldh-84], and it indicates the energy dependence of the two recombination models. The yield is fractional, and at high proton energies where the geminate model applies the yield is expected to be the same as with Co-60

Figure 10. p-MOSFET dosimeter response to dose from proton and other sources indicates a correlation between charge yield and gate bias which affects electric field strength. The oxide thickness is 1100 angstroms.

IV-21

response of radiochromic dye film dosimeters indicated the importance of the columnar recombination mechanism for protons [Hans-84]. This work also investigated track structure effects on charge yield and modeled these effects for protons from 3 to 16 MeV. [Xaps-90] reported a comparison of proton to Co-60 dose response of hardened gate oxides in terms of interface state buildup as measured by the sub-threshold technique. The data did not show a significant difference in response, and their work noted the high value of electric field as being a possible explanation for apparent dose equivalence. There are three implications for the effects of recombination on the charge yield from proton exposures. First, the reduced effect per unit dose suggests that proton studies to assess TID effects should be approached very cautiously, especially if the intended application is in a mixed proton-electron environment, or worse, an environment dominated by electrons. The proton results could lead to slight underestimation of the environment effects. Secondly, if proton dose dominates in the application and the dose response is based on Co-60 studies, they may be slightly conservative. In the absence of detailed proton and Co-60 response comparisons on the parts being considered for flight, good engineering practice argues against factoring the reduced response to protons into the expected part lifetime. Finally, p-MOS dosimeters flown on board satellites may exhibit a reduced response to protons and therefore slightly underestimate the environment, unless the calibration is performed with consideration of the anticipated environment and the energy (and possibly field) dependence of the device response. In summary, to first order, the concept of dose works well for assessing combined effects of various space radiation sources, including protons. In other words, 100 ergs per gram (1 rad) of energy deposition from one radiation source results in approximately the same device response as the same amount of energy deposited from another source. For TID purposes, LNUs from proton exposure do not appear to be an important effect. Geminate and columnar recombination lead to reduced charge yield, per unit rad, in proton environments. Even so, the assumption of a linear superposition of electron and proton dose, combined with Co-60 or 10 keV x-ray testing for component evaluations leads to reasonable estimates which may be slightly conservative in proton dominated dose environments. In closing, we would like to remind the reader that these comments address the fidelity of response estimated for proton-induced total ionizing dose only. If displacement effects are important, then there is no substitute for carefully planned tests, and x-ray or gamma ray testing is probably not appropriate. More will be made of this point in the section IVB on displacement effects.

4.0 PROTON-INDUCED SINGLE EVENT EFFECTS The basis for the classic approach to single event effects from protons first appeared in [Guen-79]. Here, the upset mechanism description involved the proton (or neutron) initiating an inelastic nuclear reaction leading to high energy recoil atoms and subsequent localized ionization sufficient to cause upset. Proton upset in satellite microelectronics was not a major concern at first because of the larger feature sizes and correspondingly high critical charge required for upset. In time this would change, and within a few years, missions routinely saw upset rate increases corresponding to high proton fluxes. In the 1995 NSREC Short Course

IV-22

segment on “Single Event Effects Qualification,” Bill Stapor includes a list of 30 missions with confirmed proton-induced SEE experiences. Today, that list would be much longer. In 1984 the key paper appeared, “Predicting Single Event Upsets in the Earth’s Proton Belts” [Bend-84]. This semi-empirical model assumes the proton reaction based mechanism and allows the use of SEE test data at a single proton energy or multiple energies for the prediction of upset rates in the proton belts. In the single parameter model, the parameter relates the proton upset sensitivity to the proton energy threshold for upset production. The basic formalism for proton-induced SEEs from nuclear reaction recoil products has not changed appreciably since its introduction in the mid-1980s. In 1989, a paper emphasizing application of the 2-parameter Bendel approach showed improved agreement with test data for modern devices with small feature size [Shim-89]. This was followed the next year by another paper advocating the 2-parameter approach and pointing out the importance of proton testing at higher energies to increase rate prediction accuracy [Stap-90]. In addition to the 1995 Short Course notes, the interested reader should refer to the 1997 NSREC Short Course segment on “Single Event Analysis and Prediction” by Ed Petersen [Pete-97]. This course offers an excellent discussion of proton upset mechanisms, models, and rate prediction tools, as well as practical consideration for proton upset cross section measurement. These course notes also provide detailed descriptions of the expanded range of component types for which proton SEEs are important. This includes not only memories, but also processors, ASICs, linears, and most modern circuit families. Additional related materials are found in Ed Petersen’s review article on, “Approaches to Proton Single Event Rate Calculations,” [Pete-96]. Given the level of discussion on the general topics of proton upset measurement and rate predictions in these two previous Short Courses (and references therein), the following material will be devoted to other proton-related special topics important to spacecraft developers. In the three sections to follow, we first treat two special topics related to the “classic” phenomenology of proton-induced recoil initiated SEEs. Next we treat a relatively recent phenomenon affecting several types of very sensitive devices in which protons can initiate upsets by direct ionization. Finally, the last portion of this section will examine various classes of proton-initiated hard errors.

4.1 Test Issues and Special Cases The “classic” approach to proton SEE testing of memories involves loading a pattern and setting up desired test conditions, exposing the Device Under Test (DUT) to some predetermined fluence, and interrogating the device to determine level of functionality and changes from the initial test conditions. The exposures may take place either in air or vacuum for high energy (>10 MeV) protons, and it is almost always required, for health safety reasons, that test personnel be remote to the exposure area during irradiations. Usually, the test setup involves test equipment (e.g., memory tester, computer with controller card, transient digitizer, etc.) local to the test and the ability to control that equipment remotely from either an extended monitor and keyboard or across a communication link or network connection. IV-23

For devices other than memories, the test instrumentation can become quite complicated. For example, processor tests may require comparison with either a second (ghost) processor or with expected results emulated in software. Such a test usually involves real time monitoring of the DUT during exposure. Often, testing of a given component must be done in situ with supporting flight hardware and software to fully assess the impact of SEEs and their likelihood of propagating through the system. This is especially true for circuit implementations incorporating error detection and correction circuitry. Throughout this section, the examples for discussion and case studies have been selected to illustrate not only some of the effects that protons may have, but also the choices and tradeoffs confronting the test engineer in gathering meaningful data without overcomplicating the test effort. 4.1.1 High Speed Technologies: While there still exists some controversy regarding the ability to accurately correlate proton and heavy ion SEE sensitivities, it is generally agreed that protons are more likely to affect technologies which exhibit lower thresholds for heavy ion SEE effects (e.g., LETth below ~10 MeVcm2/mg). By virtue of their lower nodal capacitance and lower switching energies, as well as the absence of a complementary structure, this tends to include several high speed technologies. Protons are known to cause SEEs in Si bipolar devices (ECL), GaAs MESFET and HIGFET devices, GaAs HBT based devices, and other high speed technologies [McMo-96, and references therein]. In general, if the technology has been developed with high speed in mind, then it is likely to be sensitive to proton SEEs, unless SEE hardening has been explicitly incorporated. For a given component, the effect on the circuit and subsystem can be extremely dependent on how the part functions in the circuit, and how follow-on circuit parameters affect error propagation. Investigations have shown that SEE cross sections in high speed technologies can be very dependent on device clock speeds [Mars-95, Reed-96], and even circuit hardening attempts may exhibit a clock speed dependence [Schn-92]. This is understood in terms of reduced noise margins during switching so that the circuit is more vulnerable to SEEs and that vulnerability occurs more often as the clock speed increases [Reed-96, and references therein]. The combination of inherent SEE softness in high speed logic with the increased sensitivity at high data rates argues for in situ proton testing of high speed circuitry where accurate flight error rate predictions are desired. Such testing is conceptually straight forward, but often challenging to carry out. Complications include the need to provide the DUT with high data rate signals and detect errors “on the fly” without being sensitive to the electrically noisy accelerator environment. The requirement to do this remotely argues for test automation with custom software and hardware. Supporting test hardware must itself be capable of the speeds of the DUT, and should in fact have broadband characteristics with ample bandwidth margin. This often requires the design of test circuits that must be fabricated to operate in the GHz regime. Figure 11 illustrates the test hardware and software environments used in the proton SEE evaluation of a commercial fiber channel transceiver set fabricated in a Si p-ECL process [Cart-97]. The referenced paper describes the DUT and analyzes the test results, but a

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VXI Mainframe Equipment controller (LABVIEW program) GPIB

GPIB

Digital Input/Output

User Interface (keyboard, monitor) Experimenter facility Irradiation room

GPIB

Programmable Serial Bit Stream Generator

GPIB

Fiber Channel Interface Receiver

20

Fiber Channel Interface Transmitter

1

Bit Error Rate Analyzer

Evaluation board GPIB Signal Generator (53.124 MHz)

Signal Generator (53.124 MHz)

Figure 11. Block diagram for a 1.0625 gigabit per second proton-induced single event effects test of a commercial fiber channel chip set [Cart-97]. Testing required automatic data logging and remote control of both the DUTs and also the bit error rate test equipment.

significant portion of the paper is devoted to the test hardware and methodology with emphasis on the fact that meaningful proton evaluations of high-speed technologies are nontrivial. As the data rates increase into the Gbps regime, availability of state-of-the-art bit error rate test equipment becomes a significant issue. Combined equipment costs can exceed $1M. The test development time and risk associated with transport to accelerator facilities are important concerns. As identified in figure 11, the test relied on a “VME eXtended for Instrumentation” (VXI) mainframe running LABVIEW software to control instruments and capture data. Test conditions were set from the VXI chassis via a digital I/O card interface and General Purpose Interface Bus (GPIB). Software controlling the test flow included interfaces to the commercial 12.5 Gbps bit error rate test equipment as well as the custom hardware evaluation boards. During the test, errors were logged automatically and stored on the VXI controller’s embedded processor module’s hard drive, and simultaneously made available over an Eithernet hub for remote archival storage. The test flow control and software interface were exercised by test personnel using a keyboard and monitor extension, but all high speed test equipment and control equipment had to be placed in the target room. Whenever test equipment must be located near the target it is a good, if not necessary, precaution to be aware of the possibility of scattered protons and neutrons reaching the equipment and place more sensitive units where the exposures will be minimized.

IV-25

The previous example described the evaluation of a commercially available device that was being considered for flight. Often, the interest is in the proton SEE characteristics of a technology, and test circuits may be used resulting in simplification of DUT interfaces. Examples are described in [Mars-95 and Reed-96] along with data showing the importance of going to the trouble of the high speed test approach. Figure 11a illustrates that significant differences in proton upset sensitivity for static versus dynamic testing can result as the data rates enter the hundreds of Mbps regime. The explanation is based on an enhanced sensitivity as data transitions near clock edges, and this is carefully mapped out in [Reed-96]. In general, it is important to test a device with as much fidelity as possible to the intended application, and this is especially important with regard to clock speed where high data rates are required. Design of test hardware and DUT fixtures for high data rates is challenging in itself, and misleading results can follow from bandwidth-limited test configurations [Reed-96]. For this reason, broadband test sets with excess bandwidth are highly recommended.

10

-9

SCFL Static SEU Test SCFL 400 Mbps

2

Error Cross-Section (cm / bit)

Proton Cross-section Speed Dependence

-10

10

-11

10

-12

10

10

30

50

70

Proton Energy (MeV) Figure 11a. Bit error rate testing of GaAs HIGFET shift registers showed that static upset measurements would underpredict the upset rates by large factors if the intended application involves fast clock speeds [Mars-95]. These factors increase as the data rates increase and can approach 100.

4.1.2 Small Probability Events: A recent Short Course [Pete-97] pointed out that the total dose sensitivity of a technology can place practical limitations on the accurate determination of proton SEE cross sections. This can be true for TID hardened parts where assurances of very low cross sections are needed, but it may be much more important for COTS or other unhardened devices for which the TID failure levels may be only a few krad(Si). If the TID failure level of a candidate component is on the order of ~10 krad(Si), then testing on an individual DUT will be limited to that dose. If protons of ~60 MeV are used, this corresponds IV-26

to a device cross section of ~10-11 cm2. Smaller cross sections cannot be measured with a single device, although they may be important, especially for hard failures and disruptive soft error modes. The accurate determination of SEE cross sections for important events can require testing of many devices to TID failure levels to get even poor SEE statistics. Such measures may be required when the SEE may lead to catastrophic failure, when many copies of the same device are present on the same satellite, or when many copies of the same device are used in a constellation of identical satellites. The NASA Hubble Space Telescope offers one such example with its 12 Gbit Solid State Recorder (SSR). The SSR is based on DRAM technology and uses 1440 die with each containing 16 Mbits. Details of the proton SEE response of the individual die are provided in [LaBe-98], along with a description of in-flight anomalies that indicated proton sensitivity. Prior to flight, testing had been performed with both heavy ions and protons and on flight lot die. In these tests, block errors were identified through heavy ion testing, and the LET threshold was measured at about 5 MeVcm2/mg. With such a low threshold, protons might be also be expected to cause block errors, but after 3 flight lot die were tested to proton fluences of ~ 3 x 1011 (~30 krad(Si)), the devices failed from TID without exhibiting the single event induced block error. However, after launch, two block errors were noticed and correlated with the proton environment. To understand the source of the these errors, further analysis pointed to the need for additional proton testing with a larger sample size. After a second round of testing with a sample size of 100 die, it was determined that protons could lead to the block error condition, and 9 such events were noted on the 100 die sample set. Calculations of the error cross section and expected in-flight error rate showed good agreement with the anomaly rate. Fortunately, for the HST case the block errors were easily corrected with robust ReedSolomon EDAC protection. The details of this example and others are found in [LaBe-98]. If the error condition were not easily corrected, or worse, if permanent failure resulted, the condition would not have been predicted with a small test sample set. When large numbers of a given device are flown either on the same spacecraft or across a large number of satellites, correspondingly large samples sizes must be used to assess all possible SEE modes. The exact number will be a function of both the orbit and the TID response of the DUT. If hard failure modes are possible, then large sample sizes may be warranted, even if only one device is to be flown. 4.1.3 Single Event Transients in Linear Devices: Transient effects in linear circuits were first reported by Koga, et al. in [Koga-93]. Their study examined transient signals that propagate to the output of analog circuits as a result of heavy ion irradiation. The following year, Ecoffet and coworkers confirmed the findings of Koga, et al., and extended the study to examine transients in several linear circuits, including LM 108 operational amplifiers, LM 111 voltage comparators, LM 218H operational amplifiers, and LM 211 voltage comparators [Ecof-94]. Their findings demonstrated the impact of the problem in each of these part types, and more importantly, showed that for some cases the heavy ion LET IV-27

threshold for initiating transients can be quite low (e.g. well below 5 MeVcm2/mg for the LM 108 and LM 111 devices). Ecoffet, et al., point out that such a low threshold would be expected to result in sensitivity to high energy protons. Nichols, et al., reported proton-induced transients in LM 111 and LM 139 comparators. Their analysis indicated that the transient duration could exceed 200 ns in some cases. Proton error cross sections were on the order of 10-10 cm2 per device over the range from 30 MeV to 200 MeV. Measurements showed varying sensitivity with input voltage levels and also included heavy ion measurements on the same device types. LaBel, et al., have also noted the sensitivity of linear circuits to proton induced transients [LaBe-95a]. Currently, the risk associated with proton induced transients is being assessed by a number of groups. If anything, it is more complex than with digital circuits since the magnitude and duration of the transient vary greatly with several parameters (e.g., input conditions, output loading, proton energy, etc.), and the effects are highly circuit and application dependent. 4.1.4 Correlation Between Proton and Heavy Ion SEE Sensitivities: Before concluding this discussion of “traditional” proton SEE we briefly examine approaches that have been offered to correlate proton SEE with heavy ion SEE. Such correlation can be useful for estimating proton upset sensitivity when heavy ion data is available. In addition, for present technologies, the correlation approaches can allow the estimation of heavy ion sensitivity when only proton data exist or when packaging issues preclude penetration by heavy ions to the active device regions. These estimates can be useful, but if high confidence predictions are required, these estimates should not be substituted for test results from the flight lot devices in application specific test configurations. PROFIT (for Proton Fit) is an empirical model that allows fitting of heavy ion data or heavy ion data combined with proton test data to extract parameters allowing prediction of proton upset rates [Calv-96]. The approach requires knowledge of the number of sensitive cells. It assumes that sensitive cells have the same spatial dimensions but may have differing critical charge levels. In comparisons with the two-parameter Bendel approach, the referenced paper showed very good agreement for the 18 different device types used in the study. In [O’Ne-98], another approach based on proton reaction kinematics shows how upper bounds on the heavy ion upset rates and failure probabilities can be estimated from 200 MeV proton data. This correlation requires proton data as input, and can be especially useful when heavy ion data are not available. The method does not allow estimation of proton upset sensitivity from heavy ion data. The final correlation technique we will discuss was first reported in 1983 and has been revised several times with the most recent being “The SEU Figure of Merit and Proton Upset Rate Calculations” [Pete-98 and references therein]. This approach is based on the claim that upset sensitivity for a given device can be summarized by a single parameter, the figure of merit (FOM). The referenced paper indicates how the FOM can be calculated based on either the heavy ion upset saturation cross section and threshold or from the proton upset saturation cross section. Once determined from either data set, the same FOM can be used to estimate IV-28

upset rates from either trapped protons or from heavy ions. The aggregate upset rate will then be the combination of the two contributions. The referenced paper shows good agreement for a variety of device types with varying levels of SEE sensitivity. In some instances it is of interest to assess neutron SEE sensitivity, such as in avionics applications. In [Norm-98] the Burst Generation Rate (BGR) technique for assessing proton upset sensitivity is compared with neutron BGR calculations and data. If neutron SEE data were available on a device, this approach could be taken to gain an idea of proton upset sensitivity, but as the reference indicates the correlation is not precise. Though it was not mentioned in the introduction where reasons for proton testing were listed, one possibility would be that the assessment with protons could be used with the BGR correlation to estimate neutron SEE sensitivity for avionics applications.

4.2 Proton Direct Ionization and SEEs The preceding section examined special cases of the conventional indirect proton SEE mechanism, which involves heavily ionizing nuclear reaction recoil products. Until just a few years ago, this was considered to be the only important mechanism for proton-induced single event effects. In several recent studies, SEEs due to direct ionization by protons have been reported. Though these may be “special” cases, their treatment in terms of mechanism identification, test issues, hardening solutions, and rate predictions are unique, and the remainder of this section will address these issues. At the outset, we note that for the indirect mechanism to occur there must be a reaction, and the reaction cross sections are so low such that only about 1 proton in ten thousand undergoes such an event. Most protons traverse the region and leave only an ionization track, which often matters little. However, if the circuit is sensitive to the amount of charge deposited by a single ionization track from a proton traversal, then the event cross sections may be greatly increased, by up to four orders of magnitude over the indirect mechanism. Such devices will therefore be very likely to exhibit SEEs with high rates in proton environments. 4.2.1 CCDs: In order for a device to be sensitive to direct ionization from protons, it is likely designed for an application requiring high sensitivity. In the case of the charge coupled device imaging array, the sensitivity is required to register faint signals from distant objects. For some applications, the signal may literally be only a few electrons integrated into the imager’s depletion volume prior to readout. Not surprisingly, when a proton traverses the same depletion region or nearby material from which the deposited charge can diffuse, the CCD pixel registers a false signal. These false signals from proton SEEs can affect science instruments and star tracker based navigational equipment as well. An excellent reference exists which examines the rates and charge signatures for carefully controlled test conditions and provides orbital predictions for a LEO application in the proton belts [Lomh-90]. There are two techniques to minimize the effects from unwanted proton strikes. Imaging arrays on the NASA HST mission are troubled with these stray signals when in the South Atlantic Anomaly so much that they curtail the science operations when passing IV-29

through this high flux region. When stopping operation is not practical, such as with a star tracker, transient events are usually rejected by using a Kalman filter approach to average over several frames of imagery and reject signals which are not repeated in subsequent frames taken in view of the same region. In figure 12, the four images have been acquired by a 1024 pixel by 1024 pixel CCD incorporated into one of the chronograph instruments on board the Solar and Heliospheric Observarory (SOHO) satellite. SOHO occupies an orbit around the L1 libration point that sits 930,000 miles from the Earth on the Sun-Earth line. The coronagraph instrument filters the bright orb to focus on the details of the coronal structure; hence the dark circles in the center. The four panels depict the development of a coronal mass ejection (CME) on 11/6/97. CMEs and solar flares are the two categories of solar disturbances that can result in solar proton events at satellite positions. The two lower panels show the effects of CME protons reaching the coronagraph’s CCD. Even though the instrument has heavy shielding to protect the CCD, the > 100 MeV protons from the CME penetrated to the focal plane. Note the range of proton

Figure 12. Coronagraphs from the SOHO satellite follow the evolution of a coronal mass ejection. Protons from the event reach the instrument’s CCD and “pepper” the image with transients in the lower two panels. IV-30

transient sizes and path trajectories indicating apparent omnidirectional arrival. Also note that the images are from different frames, and the proton transients are not repeated in the same image locations. For this reason, temporal filtering techniques can minimize the interference from the proton strikes for star trackers and other applications requiring tracking of bright objects against a cluttered background. More can be found on these images at the website, “sohowww.nascom.nasa.gov”. 4.2.2 Optical Link Photodetectors: In recent years several missions have implemented fiber-optic based local area networks for spacecraft telemetry and control busses as well as high data rate payload busses. Data transmission via optical fiber offers advantages in terms of power savings and reduced electromagnetic interference concerns, and these issues become increasingly important at data rates in the Gbps regime. The optical signal level representing a digital “1” may contain very little energy. When received at the link’s terminal and converted back to an electrical signal by an optoelectronic photodetector, the signal level may be only a few hundred or thousand electrons prior to amplification. Several studies have demonstrated how the photodetector, by virtue of its low signal level, can be sensitive to false signals from direct ionization by incident protons. For details and additional information, please see the review article [Mars-96, and references therein]. The sensitivity of the photodetector is perhaps not so surprising in view of the fact that this optoelectronic detector functions to capture digital information at rates into the Gbps regime from optical signals with average powers of only a few µW. This results in valid signals of only a few hundred electrons in some cases. Also, the photodiode must necessarily be large enough to capture the optical signal. For typical multimode fiber, this corresponds to surface areas of thousands of square microns (the device examined in our study has a 75 micron optical aperture with an 80 micron diameter junction). Photodiode physical cross -5 2 sections can easily exceed 10 cm , and due to their extreme sensitivity, the error cross sections can be correspondingly large. Figure 13 depicts the disk-shaped planar photodiode structure under reverse bias conditions and indicates various particle trajectories that deposit charge by direct ionization. The sketch beneath shows resulting current pulses sensed in the receiver circuit which decay with an RC time constant determined by the circuit bandwidth. Also depicted is the received signal provided in a no-return-to-zero (NRZ) protocol containing the digital information. The ratio between the high and low current levels (the “extinction ratio”) is typically about 10. Receiver circuits are almost always designed to accommodate a range of incident average optical powers and automatically adjust the decision level, or threshold, to be midway between the high and low levels. As suggested in the figure, data can be disrupted if ioninduced current exceeding the threshold current is sensed at the critical mid-bit decision when a "0" is being transmitted. Though the photodiode must be large enough to capture the optical signal, it obviously should be no larger. The analysis indicates better SEE characteristics for III-V direct bandgap detectors since a depletion depth of only about 2-3 microns can result in > 80% quantum efficiency. This is in contrast with indirect bandgap detectors, such as Si for 830 nm applications, in which depletion depths are about twenty times larger. Specifically, the thinner InGaAs structure minimizes both the "target" size for ion strikes as well as the ion IV-31

pathlength when hit. Also, the III-V device is characteristic of the design choices being considered for high bandwidth data busses since the thin junction offers minimal capacitance. To take advantage of these benefits, most design efforts use III-V InGaAs detectors for 1300 nm lightwave detection. More recently, 850 nm photodetectors with thin depletion regions and favorable SEE performance have been identified [Mars-98]. 4.2.2.1 Proton SEE Measurements on Fiber Optic Receiver Circuits: Proton testing of operating links can be done in situ using subsystem hardware or on components using a commercial bit error rate test set. For the purpose of understanding the test approach and underlying mechanisms and their effects, we present the latter approach here. The subsystem hardware level effects can in turn be inferred from this material, and the impact on the subsystem will differ according to the particular protocol and architecture. Examples of the relation between hardware level effects from “generic” device testing and the impact on specific subsystems can be found in [Carts-97, Dale-97, Mars-96, and references therein]. The SEE response of all associated circuitry must be considered, but we focus on bit errors in the photodetector receiver since it is primary importance in many cases. Figure 14 illustrates a typical test setup for measuring link bit-error-ratio (BER) performance at the component level. The BER is ratio of bits in error to total bits transferred for a given transmission interval. Full details of the measurement are found in [Mars-94a]. This setup for proton testing is similar to that shown in figure 11 for fiber-channel transceiver hardware, and the need for software controlled data collection and logging applies here too.

Proton Induced Bit Errors L

p+ Proton ionization tracks or reaction recoils generate charge in detectors.

Lmax

“1” is not corrupted

This “0” may be corrupted

This “0” is corrupted

i1 ith i0

Time Decision Points

Figure 13. The reverse biased disk-shaped planar collects charge that is deposited by direct ionization from protons. Resulting current pulses sensed in the receiver circuit decay with an RC time constant determined by the circuit bandwidth. Data can be disrupted if ion-induced current exceeding the threshold current is sensed at the critical mid-bit decision when a "0" is being transmitted. IV-32

P r o to n B E R M e a s u re m e n t P N D a ta S e q u e n c e G e n e r a to r, 2 7 -1 Sequence R e c o v e ry

0 .2 , 0 .4 , o r 1 G b p s

B E R C a lc u la tio n O p tic a l D a ta M o d u la to r 1300 nm Laser

P ro to n B eam O s c illo s c o p e

S h ie ld O p tic a l A tte n u a to r L ig h tw a v e P o w e r M e te r

P h o to d io d e U nder Test

A m p lifie r C lo c k R e c o v e ry

T IA D a ta R e g e n e ra to r

Figure 14. This illustrates a typical test setup for measuring link bit-error-rate performance. Full details of the measurement are found in [Mars-94a]. The automated test set uses commercially available bit error rate test equipment.

The tester was set to generate a serial pseudo random numeric (PN or PRN) sequence of bits in length. Data rates of 200, 400, and 1000 Mbps were established by an external waveform generator. The fiber link included a programmable attenuator so that the desired optical power level could be adjusted over the range of -30 dBm to 0 dBm (or 1 µW to 1 mW). The optical power was monitored by an external light wave meter or coupled onto the surface of the photodiode under test. Light was launched onto the photodiode using a 3axis micro-manipulator stage, and coupling efficiency was maximized by tuning and monitoring the photodiode output on a digital sampling oscilloscope. Signals were amplified by a Trans-Impedance Amplifier (TIA) and evaluated for errors resulting from proton strikes. (27-1)

With protons incident on the photodiode, we monitored the BER and recorded the number of errors. Measurements of BER were typically made with >100 total errors to assure good statistics. This usually covered a time interval of minutes. By logging the percent of error free intervals, we verified that for protons the errors were due to individual events and not contiguous errors from a single strike. Similarly, for higher LET He ions, we determined the average number of errors per strike using this method. These measurements described here and in [Mars-94a] were performed at the Naval Research Laboratory beam-line (beam-line 2) at the Crocker Laboratory, University of California. For in situ measurements of data transmission with bit periods of only a few nanoseconds, one must carefully consider the beam’s temporal structure and its relation to the data stream. We examined the impact of the 22 MHz cyclotron frequency (at 63 MeV) which provides micro-pulses of approximately 1.3 ns duration every 44 ns. Our experiments were IV-33

conducted in a manner to assure this did not influence bit-error cross section measurements. Consideration of the microstructure of the timing of proton arrivals may be an important experimental issue is some situations [LaBe-93], especially when high data rates are involved. Most high energy proton facilities have similar concerns. 4.2.2.2 Analysis and Indication of the Role of Direct Ionization in Photodetectors: Next we consider the example of errors from proton-induced direct ionization in photodetectors to show that they can be quantified with the well-developed tools used in more conventional single event investigations. As is customary with spatially separated arrays of memory elements in Random Access Memories (RAMs), we define bit error cross sections for temporally separated bits in a data stream as the ratio of failed bits to the particle fluence incident on the device during the interval in which the failures are measured. Our objective is to understand the error cross section dependence on environmental factors such particle flux and also the particle energy and angle of incidence, which impact the effective linear energy transfer (LET). Also, for a given receiver design, we measure the cross section dependence on the data link characteristics including the data rate and the optical power incident on the photodiode. The result is a data set that can be readily analyzed with existing descriptions of the expected environment to produce estimates of link performance in orbit. In [Mars-94a] the case is made for treating link bit errors as arising from direct as opposed to the indirect upset mechanism. Several indications point to this interpretation including the angular dependence of measured cross section data, the relation between ionization induced charge and electrical signal size, the relation between device physical size and the magnitude of the error cross section, and the particle and LET dependence of the measured cross section. Realizing that direct ionization causes upsets has two important implications for rate predictions for proton-induced errors. First, the traditional Bendel approach does not apply, and second, the proper approach should more closely follow the approach developed for heavy ion induced upset based on LET. Figure 15, and the discussion found in [Mars-94a], show that the proton-induced error data can in fact be usefully viewed as dependent on the effective particle LET, even though the errors are due to protons. The solid lines in the curve follow the customary Weibull form (equation 2), where a, b and c are fitted parameters and σsat is the saturation cross section of the cross section versus LET relation. The family of Weibull curves corresponds to different levels of optical power used in the operating link. It is important to note that the data of figure 15 correspond to a particular data rate and the LET is for the InGaAs detector material.

σ ( LET )

−  = 1 − e 

   

LET − a  c   b

 σ 

[2] sat

To assess proton effects on the link at other data rates, we could analyze other data sets measured at other rates as we have for the 400 Mbps data set. However more general results can be obtained by inspecting figure 16, which plots cross section dependence on IV-34

optical power for 200, 400, and 1000 Mbps. The two data sets shown represent the high and low LET particles, namely He ions and high energy protons. Note that across the full optical power range and for these two extremes in particle LET, the cross section exhibits, to first order, a direct proportionality to data rate. This trend was noted in all of the detector BER data, and it is consistent with the arguments pertaining to clock rate dependence made earlier in this section. According to equation 3, a cross section that is proportional to data rate results in a BER which is independent of data rate. The cross section is represented by σ, and φ is the particle flux. The on-orbit error rate in terms of errors per day, however, would be expected to scale linearly with error cross section. It would be up to the application as to whether the BER or the error rate is the more important metric. BER =

σ ⋅φ # errors = Bits Transmitted Data Rate

[3]

By using the Weibull approximation we can describe the LET dependence of the proton-induced error cross section and then combine this response with the LET spectrum arising from direct ionization by protons in the detector material system. Then it is possible to exercise the conventional tools for heavy ion upset rate predictions to assess link BER performance in proton rich orbits. This general approach has been validated against flight data with excellent agreement [LaBe-97a, Mars-96, and references therein].

-3

ETX75 InGaAs p-i-n Diode at 400 Mbps

2

Error Cross-Section (cm )

10

10

-5

Optical Power

10

10

-7

-25 -23 -21 -19 -17 -15

-9

10

100

dBm dBm dBm dBm dBm dBm

1000 2

LET in InGaAs (MeV cm /g) Figure 15. Proton-induced bit error data depends on the effective particle LET, even though the errors are due to direct ionization from protons [Mars-94a],. The solid lines in the curve follow the customary Weibull form, and the family of Weibull curves corresponds to different levels of optical power used in the operating link.

IV-35

BER is # bits lost per bit transmitted

BER =

σ φ Data Rate

2

σ ∝ Data Rate

Error Cross-Section (cm )

Data Rate Effects on Cross-Section 10

10

10

-4

ETX75 18 MeV He Ions at 70°

-6

1.0 GHz 0.4 GHz 0.2 GHz -8

+

63 MeV p at 50° -10

10

-20

-15

-10

Optical Power (dBm)

Figure 16. The Bit Error Ratio (BER) cross section for proton strikes on a photodetector is approximately proportional to data rate irrespective of optical power or LET. The relations indicate that a cross section that is proportional to data rate results in a BER which is independent of data rate.

4.2.3 Optocouplers and Metal-Semiconductor-Metal (MSM) Photodiodes: The introduction and section 4.1 offered discussion and references to the extensive literature describing “conventional” proton effects involving nuclear reactions and the indirect upset mechanism. The section 4.2 then dealt with a newer formalism that applies to devices that exhibit behavior that is dominated by direct ionization from protons. Not surprisingly, some devices show characteristics of both behaviors. This section examines two such examples. Optocouplers have received a great deal of attention for their sensitivity to displacement damage from protons and this will be discussed at length in Section IVB on displacement effects. At the 1997 NSREC it was reported that high bandwidth optocouplers could also be sensitive to proton-induced transient effects [LaBe-97]. That study reported that proton initiated transients exhibited a rapid onset and then dissipated with a time constant governed by the bandwidth of the device. At first this appeared to be another example of the general problem of transient effects in linear devices, caused presumably by proton reaction recoil products. But on closer inspection, the angular dependence seen in figure 17 shows an enhancement in the cross section around the plane of the package. For the classic reaction recoil mechanism, no angular dependence would be expected. In [LaBe-97] the explanation is offered in terms of a combination of mechanisms. Figure 18 depicts the situation in which the device response is dominated by strikes to the optocoupler’s internal photodetector with nuclear reactions causing transients when they occur, regardless of the angle of incidence. However, for protons traversing the plane of the photodetector sufficient signal can follow from direct ionization across the longer pathlengths.

IV-36

-7

2

Device Cross Section (cm )

4x10

3x10

2x10

1x10

-7

-7

-7

0

0

30

60

90

120

Angle of Incidence (degrees) Figure 17. Proton-induced transients in optocouplers exhibit an enhancement in the cross section when the beam is directed in the plane of the package. For the classic reaction recoil mechanism, no angular dependence would be expected. In [LaBe-97] this behavior is explained in terms of a combination of direct ionization through the plane of the photodetector and indirect reaction mechanisms.

Direct Ionization Across Long Pathlengths

+ + - + -- + + + - + +- -+ +- + - -+ ++ - + +- -++- + - - + ++ ++ - + - ++++-- -+- -++++--- -+++--- + ++ +- -- ++ -- + --- ++ - - +++--+-- -++ - + + - ++++ + +-+--+-++- - + + +++-+--- + ++- -- -+++ - --++ + - - + - + + -+ - - + - + + -

Proton

380 µ m + + - + -- + + + - + -- + ++- -++-+-+-+-++- -+- + + - - + -+ +- ++- - - + + - +- -+- -+ +- ++-+ +- - + - ++-

Proton

And Nuclear Reaction Recoils.

Figure 18. This drawing from [LaBe-97] depicts the situation in which the device response is dominated by strikes to the optocoupler’s internal photodetector with nuclear reactions causing transients when they occur, regardless of the angle of incidence. For protons traversing the plane of the photodetector, sufficient signal can follow from direct ionization across the longer pathlengths.

IV-37

Cross-Section (cm2/device)

1.2E-07 0 degrees 85 degrees 87.5 degrees 90 degrees 92.5 degrees 95 degrees

1.0E-07 8.0E-08 6.0E-08 4.0E-08 2.0E-08 0.0E+00 30

80

130

180

230

280

Proton Energy (MeV) Figure 19. Data supporting the role of the direct ionization mechanism for optocoupler transients shows an apparent LET threshold for the effect [Reed-98]. The increased cross section seen when protons traverse the plane of the diode does not occur with protons above a certain LET (corresponding to ~100 MeV protons).

The following year Reed, et al. reported additional data supporting the role of the direct ionization mechanism in terms of an apparent LET threshold for the effect [Reed-98]. Figure 19, reproduced from that paper, reveals that the increased cross section seen when protons traverse the plane of the diode does not occur with protons above a certain LET (corresponding to ~ 100 MeV). Johnston, et al. extended the study to other devices and included heavy ions as well as protons [John-98]. Their findings suggest that at higher LET’s corresponding to cosmic rays the follow-on amplifier circuit may also lead to transient effects, and that for protons the nuclear elastic scattering may be important to the process. Another study has pointed to the important combination of direct and indirect mechanisms for the case of Metal-Semiconductor-Metal (MSM) photodetectors for use in digital data links such as the fiber-based data busses already described [Mars-98]. The MSM detector technology offers the advantage of a nearly planar geometry which minimizes the pathlengths (and ionization signature) when traversed by protons. Enhanced proton transient cross sections in the plane of the detector and the signature of a threshold LET for direct ionization effects were both noted for MSM devices in [Mars-98]. The existence of multiple mechanisms for transient effects has important implications for the methods and accuracy of transient rate predictions. It has been suggested [LaBe-97] that the aggregate transient rate must be calculated as the sum of the rates for indirect effects using the Bendel formalism plus the direct contribution using the modified RPP approach and measured Weibull-type LET dependence as described for photodetectors in the previous section. For devices exhibiting large enhancements in the cross section near the plane of the IV-38

device as in figure 18, both mechanisms are obviously important, and the dominant one would depend on the details of the application and the environment. It should be assumed that the rates would depend on how such a device is operated in terms of expected signal levels and detection sensitivity.

4.3 Destructive Failures The concerns for TID failure and soft errors treated in the last two sections are serious issues for designers, but the possibility of an unrecoverable catastrophic failure from a single particle event ranks among the highest concerns. Where cosmic ray heavy ions are present, proton-induced hard failures may not be the dominant threat from the natural environment; however, these failure modes should not be overlooked. In the three sections below on Single Event Latch-up (SEL), Single Event Burnout (SEB), and stuck bits, we examine the various ways in which proton-induced single events can render a circuit unusable. 4.3.1 Latch-Up (and COTS): We first consider SEL with the recognition that it is not solely a COTS issue, but it is a major concern when using COTS CMOS parts in space. Latch-up in CMOS devices is well understood in terms of a particle-induced triggering of an SCR action in a parasitic p-n-p-n path. Details of the mechanism, modeling tools, hardening approaches, and references to related topics are in covered in the NSREC Short Course Notes from 1996 [John-96]. It should be noted that not all latch-up modes lead to destructive failure, and in some cases power cycling may be used to restore nominal operating conditions. For many years, SEL was considered to be a CMOS phenomenon only in cosmic ray environments, but at the 1992 NSREC two papers reported first the laboratory confirmation of proton-induced latch-up [Nich-92] and the observation of a proton-induced latch-up event in space [Adam-92]. In these studies, the affected CMOS devices were either on a bulk or a thick epitaxial substrate, and the corresponding heavy ion latch-up threshold was fairly low (below 10 MeVcm2/mg). Even so, the proton energy threshold below 50 MeV for both cases suggests that proton-induced latch-up may be a higher risk than cosmic ray induced latch-up in mid-latitude LEO applications. Since 1992 there have been many examples of proton-induced latch-up, both in the laboratory and in-flight. Table 2 has been reproduced from [Norm-98] where it was compiled to show several examples from the literature as the basis for evaluating his formulation of the Burst Generation Rate (BGR) model for predicting latch-up sensitivity in microprocessors. Note the K-5 processor results as fabricated on the 2 micron thick epitaxial material. This is one of the more unexpected results, and it is noted, though not explained, in the original reference [John-97]. Both of these papers, and references therein, note the general correlation between susceptibility to heavy ion induced latch-up with low LET threshold, and the sensitivity to proton-induced latch-up. The lack of a more quantitative correlation is blamed on the differences between charge deposition by heavy ions and proton-induced recoils and the associated charge collection processes [John-97]. For crude estimates, it is probably reasonable to assume that devices which exhibit a low heavy ion latch-up threshold (below 5 MeVcm2/mg) will also be sensitive to protonIV-39

induced latch-up and even devices with LET thresholds of twice that may be suspect. The K5 example also illustrates that fabrication on a thin epitaxial starting material does not necessarily guard against latch-up, though systematic study of varying epi-layer thickness in one process has shown this to be an important step toward hardening against latch-up [LaBe-95]. Conversely, it is probably a safe assumption that if a device has been demonstrated to be hard or immune to latch-up by heavy ions then it will show similar hardness with respect to protons. Table 2: Measured and Calculated Proton SEL Cross Sections Device

Measr’d Proton SEL X-Section, cm²

BGR Calct’d Proton SEL X-Section, cm²

HM65162 NEC-4464 K-5 K-5 LSI-64811 LCA200K XC96002 XC96002 IDT3081

1.4E-10 1.8E-10 6.6E-9 6.6E-9 1.7E-11 1.4-4.1E-11 4.5E-9 4.5E-9 3E-11

1.4E-10 1.5E-10 2.2E-11 4E-9 6E-12 7.6E-11 2.6E-10 8.8E-9 0.9E-11

Remarks

t=6µm t=2µm

t=6µm t=4µm

Ref. for Data 31 32 32 32 32 8 33 33 34

More detailed discussion of the present understanding of the mechanisms and modeling for proton-induced SEL can be found in the references provided. In general, even if knowledge of a thin epitaxial material suggests latch-up immunity, latch-up testing should be performed prior to consideration for flight application when the process under question is not well known. Heavy ion screening would be a first step with proton latch-up testing advised only if the heavy ion threshold were low and there was a need to quantify the risk in a proton rich environment. In practice, most missions would avoid the use any part susceptible to failure by proton-induced latch-up for a critical application based on the risk to heavy ion induced failure alone. 4.3.2 Proton-induced Single Event Burnout (SEB) in Power MOSFETs: Single event burnout occurs when an ion or proton-induced recoil atom strikes a power MOSFET in its “off” state and triggers a parasitic bipolar junction transistor. This “on” transistor creates a conduction path between source and drain, and the resulting regenerative feedback leads to a high current state causing second breakdown and burnout. Single event burnout in power MOSFETs has received considerable attention as a hard failure mode from heavy ion effects [Titu-96, Alle-96, Ober-96, Adol-96, and references therein]. Recently, as was the case with latch-up, both experimental investigations and in-flight experience have pointed to protons as a possible cause for burnout. Two 1996 NSREC papers addressed this issue, one with laboratory measurements [Ober-96] and the other with flight data [Adol-96]. Oberg and co-authors evaluated the response of power MOSFETs to both high-energy proton and to high energy neutron irradiation [Ober-96]. Their evidence indicated some correlation between proton SEB cross sections and those for neutrons and heavy ions, with the IV-40

more energetic protons being more likely to cause burnout. The flight data from the CRUX experiment [Adol-96] both confirmed the effect for orbital protons and showed it to be more likely on the higher voltage (200 V) device, as expected. Figure 20 shows additional flight data and correlation of SEB rate with the applied voltage on the CRUX experiment that appear in [Bart-98]. The bias dependence is expected based on electric field dependence of the problem as described in [Titu-96, and references therein]. If proton-induced hard failure is possible, then heavy ion induced hard failure would also be possible. The determination of which failure mode would be more likely depends on the particle environment internal to the satellite and on the relative sensitivities of the device in question. [Bart-98] compares two sets of power MOSFETS flown on the CRUX experiment and shows that on a given satellite, proton-induced burnout may dominate for one device while heavy ion burnout dominates for another. In practice, power MOSFET applications typically de-rate the devices to improve reliability, avoid gate rupture, and prevent burnout. With proper de-rating, the threat of proton-induced burnout can be avoided. 4.3.3 Stuck Bits: The key paper introducing this topic was presented by Oldham, et al., in 1993 with the title “Total Dose Failures in Advanced Electronic from Single Ions,” [Oldh-93]. Their work describes the ability of a single ion to deposit sufficient energy along its path to result in localized increases in trapped oxide charge and interface state generation. In fact, for small feature sizes, an entire transistor gate can be affected and undergo failure as a result of localized dose deposition and threshold voltage shift. The initial work in DRAMs resulted in bits which could not be rewritten, hence the term “stuck bits”. This effect can occur in any device type, and is not just a problem for memories. Their paper also points out the expected increasing importance of this problem with decreasing feature size, and this has since been observed. The following year, Poivey, et al. expanded the study in terms of device types, ion species, and analysis. In that paper, the more formal term “Single Hard Error (SHE)” was introduced [Poiv-94]. At present, proton-induced stuck bits are not considered to be a significant problem, though scaling trends suggest that this may soon change. Proton-induced stuck bits may be either temporary or permanent as reported in [Sore-95]. Figure 21, from the CRUX experiment, indicates that stuck bits have occurred in all device types included in the experiment. Though they have been correlated with solar particle events, [Bart-98] points out that most events have been outside of the SAA and therefore are more likely due to heavy ions. From a test perspective, it is common to see stuck bits during proton SEE testing as the TID limit of the technology is approached. That, along with increased leakage currents, is an indication of the need to resume the test with a fresh device.

IV-41

SEBs As Function of Voltage Drain-to-Source For L < 3 (August 11, 1994 to May 17, 1996) 200

Number of SEBs

175 150 125 100 75 50 25 Results For 200 Volt Boards 0 160

166

172

178

184

190

196

Voltage Drain-to-Source (Volts)

Figure 20. The results of the power MOSFET single event burnout experiment flying on CRUX confirm that protons can lead to device failure and showed that the proton rates can exceed heavy ion induced SEB rates [Bart-98]. Stuck Bit Errors on CR UX SRAMs

Dipole Shell Parameter - L

100 MICRON 1M ED I 1M HITACHI/E LMO 1M MICR ON 256K ED I 256K IDT 256K L=3 Solar E ve nt

10

1 0

1 00

200

300

400

500

6 00

7 00

Number of Days from Launch

Figure 21. Stuck bits have occurred in all the modern memory devices flying on the CRUX experiment [Bart-98]. The chart indicates that some (for L < 3) are probably due to protons, but most are thought to be heavy ion related. IV-42

5.0

SUMMARY

Satellite microelectronic and photonic devices subjected to the ionizing effects of protons may exhibit responses either from total ionizing dose or from single event phenomena. Heavily shielded devices will likely receive dose primarily from protons in orbits encountering the inner radiation belts. For total ionizing dose, we have reviewed the literature comparing the equivalence of proton dose versus other sources of dose deposition found in either the space environment or in laboratory test facilities. We conclude that Co-60 and electron dose satisfactorily simulate proton dose for most purposes. Many different single event phenomena arise from protons including soft errors from nuclear inelastic reaction events, nuclear scattering events, and even direct ionization in several types of more sensitive devices. Special considerations are needed for SEU testing of high speed devices and for evaluations of devices with low soft error cross sections relative to their TID failure levels. In addition, both destructive and nondestructive hard errors may result from proton-induced reactions. In many cases, the concern for hard errors will be greater for cosmic rays, but in geomagnetically shielded (e.g., low-Earth orbits) the greater risk can be proton-related. Satellite subsystem design efforts benefit from proper expression of the anticipated proton environments in thorough requirements aimed at describing realistic typical and worst case proton flux and fluence levels. We have discussed many aspects of the environment models and their associated uncertainties as they affect the requirement definition.

6.0

ACKNOWLEDGMENTS

We gratefully acknowledge partial support, technical suggestions, and complete encouragement from our colleagues and friends in the Radiation Effects and Analysis Group and Radiation Physics Office at NASA Goddard Space Flight Center. We also appreciate the helpful interactions with the Radiation Effects Branch members at the Naval Research Laboratory and throughout the radiation effects community.

IV-43

7.0

REFERENCES FOR INTRODUCTION AND PART A

(All references are unclassified.) [Adam-92]

L. Adams, E.J. Daly, R. Harboe-Sorensen, R. Nickson, J. Haines, W. Schafer, M. Conrad, H. Griech, J. Merkel, T. Schwall, and R. Henneck, “A Verified Proton-Induced Latch-up in Space,” IEEE Trans. Nucl. Sci., Vol. 39, No. 6, pp. 1804-1808, 1992.

[Adol-96]

John W. Adolphsen, Janet L. Barth, and George B. Gee, “First Observation of ProtonInduced Power MOSFET Burnout in Space: The CRUX Experiment on APEX,” IEEE Trans. Nucl. Sci., NS-43, No. 6, pp. 2921-2926, 1996.

[Alle-96]

M. Allenspach, C. Dachs, G.H. Johnson, R.D. Schrimpf, E. Lorfevre, J.M. Palau, J.R. Brews, K.F. Galloway, J.L. Titus, and C.F. Wheatley, “SEGR and SEB in N-Channel Power MOSFETS,” IEEE Trans. Nucl. Sci., NS-43, No. 6, pp. 2927-2937, 1996.

[Augu-82]

L.S. August, “Estimating and Reducing Errors in MOS Dosimeters Caused by Exposure to Different Radiations,” IEEE Trans. Nucl. Sci., Vol. 29, No. 6, pp. 2000-2003, 1982.

[Bart-97]

Janet Barth, “Modeling Space Radiation Environments,” Notes from the 1997 IEEE Nuclear and Space Radiation Effects Conference Short Course, 1997.

[Bart-98]

Janet L. Barth, John W. Adolphsen, and George B. Gee, “Single Event Effects on Commercial SRAMS and Power MOSFETS: Final Results of the CRUX Flight Experiment on APEX,” 1998 IEEE Radiation Effects Data Workshop Record, pp. 1-10.

[Bend-84]

W.L Bendel and E.L. Petersen, “Predicting Single Event Upsets in the Earth’s Proton Belts,” IEEE Trans. Nucl. Sci., Vol. 31, No. 6, pp. 1201-1207, 1984.

[Calv-96]

Philippe Calvel, Catherine Barillot, and Pierre Lamonthe, “An Empirical Model for Predicting Proton Induced Upset,” IEEE Trans. Nucl. Sci., NS-43, No. 6, pp. 28272832, 1996.

[Cart-97]

M.A. Carts, P.W. Marshall, C.J. Marshall, K.A. LaBel, M. Flanegan, and J. Bretthauer, “Single Event Test Methodology and Test Results of Commercial Gigabit per Second Fiber Channel Hardware,” IEEE Trans. Nucl. Sci., NS-44, No. 6, pp. 1878-1884, 1997.

[Ecof-94]

R. Ecoffet, S. Duzellier, P. Tastet, C. Aicardi, and M. Labrunee, “Observation of Heavy Ion Induced Transients in Linear Circuits,” IEEE NSREC Radiation Effects Data Workshop Record, pp. 72-77, 1994.

[Feyn-96]

J. Feynman and S.B. Gabriel, “High Energy Charged Particles in Space at One Astronomical Unit,” IEEE Trans. Nucl. Sci, Vol. 43, No. 2, pp. 344-352, 1996.

[Frie-88]

R.K. Frietag, E.A. Burke, C.M. Dozier, and D.B. Brown, “The Development of NonUniform Deposition of Holes in Gate Oxides,” IEEE Trans. Nucl. Sci., NS-35, No. 6, pp. 1203-1207, 1988.

IV-44

(All references are unclassified.) [Gate-96]

Michele Gates, Kenneth A. LaBel, Janet Barth, Allan Johnston, and Paul W. Marshall, “Single Event Effects Criticality Analysis,” NASA Report, See NASA GSFC Radiation Effects & Analysis Home Page, http://flick.gsfc.nasa.gov/radhome.htm, 1996.

[Guen-79]

C.S. Guenzer, E.A. Wolicki, and R.G. Allas, “Single Event Upset in Dynamic RAMs by Neutrons and Protons,” IEEE Trans. Nucl. Sci., NS-26, No. 6, pp. 5048-5055, 1979.

[Hous-98]

S.L. Houston and K.A. Pfitzer, “A New Model for the Low Altitude Trapped Proton Environment,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2972-2978, 1998.

[IEEE-1156] IEEE P1156.4, “Standard for Environmental Specifications for Spaceborne Computer Modules,” 1995. [Ingu-97]

C. Inguimbert, S. Duzellier, R. Ecoffet, and J. Bourrieau, “Proton Upset Rate Simulation by a Monte Carlo Method: Importance of the Elastic Scattering Mechanism,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp. 2243-2249, 1997.

[John-96]

Gregory H. Johnson and Kenneth F. Galloway, “Catastrophic Single Event Effects in the Natural Radiation Environment,” Section IV from the 1996 IEEE Nuclear and Space Radiation Effects Conference Short Course Notes.

[John-97]

A.H. Johnston, G.M. Swift, and L.D. Edmonds, “Latchup in Integrated Circuits from Energetic Protons,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp. 2367-2377, 1997.

[John-98]

A.H Johnston, G.M. Swift, T. Miyahira, S. Guertin, and L.D. Edmonds, “Single Event Upset Effects in Optocouplers,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2867-2875, 1998.

[Kinn-98]

James D. Kinnison, “Achieving Reliable, Affordable Systems,” Section V from the 1998 IEEE Nuclear and Space Radiation Effects Conference Short Course Notes.

[Koga-93]

R. Koga, S.D. Pinkerton, S.C. Moss, D.C. Mayer, S. LaLumondiere, S.J. Hansel, K.B. Crawford, and W.R. Crain, “Observation of SEUs in Analog Microcircuits,” IEEE Trans. Nucl. Sci., NS-40, No. 6, pp. 1838-1844, 1993.

[LaBe-93]

Kenneth A. LaBel, Paul Marshall, Cheryl Dale, Christina Crabtree, E.G. Stassinopolous, Jay T. Miller, and Michele M. Gates, “SEDS MIL-STD-1773 Fiber Optic Data Bus: Proton Irradiation Test Results and Spaceflight SEU Data,” IEEE Trans. Nucl. Sci., Vol. 40, No. 6, pp. 1638-1645, 1993.

[LaBe-95]

K.A. LaBel, Donald K. Hawkins, J.A. Kinnison, W.P. Stapor, P.W. Marshall, “Single Event Effect Characteristics of CMOS Devices Employing Various epi-Layer Thicknesses,” IEEE Proc. of RADECS, 95TH8147, pp. 258-262, Sep 1995.

[LaBe-95a]

K.A. LaBel, A.K. Moran, D.K. Hawkins, A.B. Sanders, E.G. Stassinopoulos, R.K. Barry, C.M. Seidlick, H.S. Kim, J. Forney, P.Marshall, and C. Dale, “Single Event Effect Proton and Heavy Ion Test Results in Support of Candidate NASA Programs,” NSREC Radiation Effects Data Workshop, pp. 16-32, 1995.

IV-45

(All references are unclassified.) [LaBe-97]

Kenneth A. LaBel, Paul Marshall, C.J. Marshall, M. D’Ordine, M. Carts, G. Lum, H.S. Kim, C.M. Seidleck, T. Powell, R. Abbott, J. Barth, and E.G. Stassinopolous, “Proton Induced Transients in Optocouplers: In-flight Anomalies, Ground Irradiation Test, Mitigation and Implications,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp. 1885-1892, 1997.

[LaBe-97a]

K.A. LaBel, P.W. Marshall, C.J. Marshall, J. Barth, H. Leidecker, R. Reed, and C.M. Seidlick, “Comparison of MIL-STD-1773 Fiber Optic Data Bus Terminals: Single Event Proton Test Irradiation, In Flight Performance, and Prediction Techniques,” Proceedings of RADECS 97, pp. 332-338, 1997.

[LaBe-98]

K.A. LaBel, P.W. Marshall, J.L. Barth, R.B. Katz, R.A. Reed, H.W. Leidecker, H.S. Kim, and C.J. Marshall, “Anatomy of an Anomaly: Investigation of Proton Induced SEE Test Results for Stacked IBM DRAMs,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2898-2903, 1998.

[Lomh-90]

T.S. Lomheim, R.M. Shima, J.R. Angione, W.F. Woodward, D.J. Asman, R.A. Keller, and L.W. Schumann, “Imaging Charged-Coupled Device (CCD) Transient Response to 17 and 50 MeV Proton and Heavy Ion Irradiation,” IEEE Trans. Nucl. Sci., Vol. 37, No. 6, pp. 1876-1885, 1990.

[Ma-89]

Ionizing Radiation Effects in MOS Devices and Circuits, T.P. Ma and Paul V. Dressendorfer, John Wiley and Sons, New York: 1989.

[Mars-94]

Paul W. Marshall, Cheryl J. Dale, E. Joseph Friebele, and Kenneth LaBel, "Survivable Fiber-Based Data Links for Satellite Radiation Environments," SPIE Critical Review CR-50 on Fiber Optic Reliability and Testing, 1994.

[Mars-94a]

Paul W. Marshall, Cheryl J. Dale, Martin A. Carts, and Kenneth A. LaBel, “Particle Induced Bit Erors in High Performance Fiber Optic Data Links for Satellite Data Management,” IEEE Trans. Nucl. Sci., NS-41, No. 6, pp. 1958-1965, 1994.

[Mars-95]

Paul W. Marshall, Cheryl J. Dale, Todd R. Weatherford, Michael La Macchia, and Kenneth A. LaBel, “Particle Indiced Mitigation of SEU Sensitivity in High Data Rate GaAs HIGFET Technologies,” IEEE Trans. Nucl. Sci., NS-42, No. 6, pp. 1844-1854, 1995.

[Mars-95a]

Paul W. Marshall, Cheryl J. Dale, Martin E. Fritz, Michael de La Chapelle, Martin A. Carts, and Kenneth A. LaBel, “Total ionizing dose and single particle effects in a 200 Mbps star-coupled fiber optic data bus,” Proc. of SPIE Conference on Photonics for Space Environments III, Proc. # 2482, 1995.

[Mars-96]

P.W. Marshall, C.J. Dale, and Kenneth A. LaBel, “Space Radiation Effects in High Performance Fiber Optic Data Links for Satellite Data Management,” IEEE Trans. Nucl. Sci. NS-43, Vol. 2, p. 645 (1996).

IV-46

(All references are unclassified.) [Mars-98]

C.J. Marshall, P.W. Marshall, M.A. Carts, R.A. Reed, and K.A. LaBel, “Proton Induced Effects in a Metal-Semiconductor-Metal (MSM) Photodetector for Optical Based Data Transfer,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2842-2848, 1998.

[McMo-96]

D. McMorrow, T.R. Weatherford, S. Buchner. A.R. Knudson, J.S. Melinger, L.H Tran, and A.B. Campbell, “Single Event Effects in GaAs Devices and Circuits,” IEEE Trans. Nucl. Sci., NS-43, No. 2, pp. 628-624, 1996.

[Meff-94]

J.D. Meffert and M.S. Gussenhoven, CRESSPRO Documentation, PL-TR-94-2218, Phillips Laboratory, Hanscom AFB, Mass., 1994.

[Nich-92]

Donald K. Nichols, James R. Coss, R. Kevin Watson, Harvey R. Schwartz, and Ronald L. Pease, “An Observation of Proton Induced Latch-up,” IEEE Trans. Nucl. Sci., Vol. 39, No. 6, pp. 1654-1657, 1992.

[Nich-96]

D.K. Nichols, James R. Coss, Tetsuo F. Miyahira, and Harvey R. Schwartz, “Heavy Ion and Proton Induced Single Event Transients in Comparitors,” IEEE Trans. Nucl. Sci., NS-43, No. 6., pp. 2960-2967, 1996.

[Norm-98]

Eugene Normand, “Extensions of the Burst Generation Rate Method for Wider Applications to Proton/Neutron Induced Single Event Effects,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2904-2914, 1998.

[Ober-96]

D.L. Oberg, J.L. Wert, E. Normand, P.P. Majewski, and S.A. Wender, “First Observations of Power MOSFET Burnout with High Energy Neutrons,” IEEE Trans. Nucl. Sci., NS-43, No. 6, pp. 2913-2920, 1996.

[Oldh-83]

T.R. Oldham and F.B. McLean, “Charge Collection Measurements for Heavy Ions Incident on n- and p-Type Silicon,” IEEE Trans. Nucl. Sci., NS-30, No. 6, pp. 44934500, 1983.

[Oldh-84]

T.R. Oldham, “Analysis of Damage in MOS Devices in Several Radiation Environments,” IEEE Trans. Nucl. Sci., NS-31, No. 6, pp. 1236-1241, 1984.

[Oldh-93]

T.R. Oldham, K.W. Bennett, J. Beaucour, T. Carriere, C. Poivey, and P Garnier, “Total Dose Failure in Advanced Electronics from Single Ions,” IEEE Trans. Nucl. Sci., NS41, No. 6, pp. 1820-1830, 1993.

[O’Ne-98]

P.M. O’Neill, G.D. Badhwar, and W.X. Culpepper, “Internuclear Cascade-Evaporation Model for LET Spectra of 200 MeV Protons Used for Parts Testing,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2467-2474, 1998.

[Peas-99]

Ronald L. Pease, private communication.

[Pete-96]

E.L. Petersen, “Approaches to Proton Single Event Rate Calculations,” IEEE Trans. Nucl. Sci., NS-43, No. 2, pp. 496-505, 1996.

[Pete-97]

E.L. Petersen, “Single Event Analysis and Prediction,” Section III, 1997 NSREC Short Course Notes. IV-47

(All references are unclassified.) [Pete-98]

E.L. Petersen, “The SEU Figure of Merit and Proton Upset Rate Calculations,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2550-2562, 1998.

[Poiv-94]

C. Poivey, T. Carriere, J. Beaucour, and T.R. Oldham, “Characterization of Single Hard Errors (SHE) in 1 M-bit SRAMs from Single Ion,” IEEE Trans. Nucl. Sci., NS-42, No. 6, pp. 2235-2239, 1994.

[Reed-96]

R.A. Reed, M.A. Carts, P.W. Marshall, C.J. Marshall, S. Buchner, M. LaMacchia, B. Mathes, and D. McMorrow, “Single Event Upset Cross Sections at Various Data Rates,” IEEE Trans. Nucl. Sci., NS-43, No. 6, pp. 2862-2867, 1996.

[Reed-98]

R.A. Reed, P.W. Marshall, A.H. Johnston, J.L. Barth, C.J. Marshall, K.A. LaBel, M. D’Ordine, H.S. Kim, and M.A. Carts, “Emerging Optocoupler Issues with Energetic Particle Induced Transients and Permanent Radiation Degradation,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2833-2841, 1998.

[Sawy-76]

Donald M. Sawyer and James I. Vette, “AP-8 Trapped Proton Environment for Solar Maximum and Solar Minimum,” National Science Data Center Report NSSDC/WDCA-R&S 76-06, 1976.

[Schn-92]

R. Schneiderwind, D. Krening, S. Buchner, K. Kang, and T.R. Weatherford, “Laser Confirmation of SEU Experiments in GaAs MESFET Combinational Logic,” IEEE Trans. Nucl. Sci., NS-39, No. 6, pp. 1665-1670, 1992.

[Selt-80]

Stephen Seltzer, “SHIELDOSE: A Computer Code for Space-Shielding Radiation Dose Calculations,” National Bureau of Standards (NBS) Technical Note 1116, May, 1980.

[Shim-89]

Y. Shimano, T. Goka, S. Kuboyama, K. Kawachi, T Kanai, and Y. Takami, “The Measurement and Prediction of Proton Upset,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 2344, 1989.

[SSP-30512] SSP 30512 Rev. C, “Space Station Ionizing Radiation Design Environment,” June, 1994. [Sore-95]

R. Harboe-Sorensen, R. Muller, and S. Frenkel, “Heavy Ion, Proton and Co-60 Radiation Evaluation of 16 Mbit DRAM Memories for Space Application, 1995 IEEE Radiation Effects Data Workshop, pp. 42-49.

[Stap-85]

W.J. Stapor, L.S. August, D.H. Wilson, T.R. Oldham, and K.M. Murray, “Proton and Heavy Ion Radiation Damage Studies in MOS Transistors,” IEEE Trans. Nucl. Sci., Vol. 32, No. 6, pp. 4399-4404, 1985.

[Stap-90]

W.J. Stapor, J.P. Meyers, J.B. Langworthy, and E.L. Petersen, “Two Parameter Bendel Model Calculations for Predicting Proton Induced Upset,” IEEE Trans. Nucl. Sci., Vol. 37, No. 6, pp. 1966-1972, 1985.

[Stap-95]

William J. Stapor, “Single Event Effects Qualification,” Section II, 1995 IEEE NSREC Short Course Notes. IV-48

(All references are unclassified.) [Stass-88]

E.G. Stassinopoulos and J.P Raymond, “The Space Radiation Environment for Electronics,” Proc. IEEE, vol. 76, pp. 1423-1442, 1988.

[Stass-90]

E.G. Stassinopoulos, “Radiation Environments in Space,” in Notes for the 1990 IEEE Nuclear and Space Radiation Effects Conference Short Course, 1990.

[Titu-96]

J.L. Titus and C.F. Wheatley, “Experimental Studies of Single Event Gate Rupture and Burnout in Vertical Power MOSFETs,” IEEE Trans. Nucl. Sci., Vol. 43, No. 2, pp. 533545, 1996.

[Titu-98]

J.L. Titus and C.F. Wheatley, “Proton Induced Dielectric Breakdown in Power MOSFETs,” IEEE Trans. Nucl. Sci., NS-45, No. 6, pp. 2891-2897, 1998.

[Tylk-96]

Allan J. Tylka, James H Adams, Jr., P.R. Boberg, Buddy Brownstein, William F. Dietrich, Erwin O. Flueckiger, Edward L. Petersen, Margaret A. Shea, Don F. Smart, and Edward C. Smith, “CREME96 A Revision of the Cosmic Ray Effects on MicroElectronics Code,” IEEE Trans. Nucl. Sci., Vol. 43, No. 6, pp. 2150-2160, 1996.

[Tylk-96a]

A.J. Tylka, W.F. Dietrich, P.R. Boberg, E.C. Smith, and J.H. Adams, Jr., “Single Event Upsets Caused by Solar Energetic Heavy Ions,” IEEE Trans. Nucl. Sci., Vol. 43, No. 6, pp. 2758-2766, 1996.

[Xaps-89]

M.A. Xapsos, R.K. Frietag, E.A. Burke, C.M. Dozier, D.B. Brown, and G.P. Summers, “The Random Nature of Energy Deposition in Gate Oxides,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 1896-1903, 1989.

[Xaps-90]

M.A. Xapsos, private communication.

[Xaps-98]

M.A. Xapsos, G.P. Summers, and E.A. Burke, “Probability Model for Peak Fluxes of Solar Proton Events,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2948-2953, 1998.

IV-49

1999 NSREC SHORT COURSE

SECTION IVB

PROTON EFFECTS AND TEST ISSUES FOR SATELLITE DESIGNERS: DISPLACEMENT EFFECTS

Cheryl J. Marshall NASA/Goddard Space Flight Center Paul W. Marshall Consultant

IV. Proton Effects and Test Issues for Satellite Designers Part B: Displacement Effects Cheryl J. Marshall NASA/Goddard Space Flight Center Electrical Systems Center / Code 562 Greenbelt, Maryland 20771 Paul W. Marshall Consultant 7655 Hat Creek Road Brookneal, VA 24528 1.0 Introduction………………………………………………………………...……...51 2.0 Proton Induced Displacement Damage Mechanisms and Tools………………..52 2.1 Displacement Damage Mechanisms and Defect Formation…………….…. 53 2.2 Displacement Damage Effects in Materials and Devices………………….. 56 2.3 Non-Ionizing Energy Loss Rate (NIEL) Concept…………………………. 59 2.3.1 The Correlation of NIEL to Device Behavior…………………...61 2.3.2 Limitations in the Use of NIEL………………………………….64 2.3.3 Calculation of Displacement Damage Equivalent Fluences……. 68 2.3.4 Concept of “Displacement Damage Dose”……………………... 69 2.4 On-Orbit Performance Predictions……………………………...………….70 3.0 Proton Displacement Damage Case Studies…………………………………….. 74 3.1 Introduction………………………………………………………………… 74 3.2 Laboratory Radiation Test Issues…………………………………………...74 3.3 Case Studies………………………………………………………………... 77 3.3.1 Bipolar Transistors……………………………………………… 77 3.3.2 Charge Transfer Devices………………………………………...79 3.3.3 Photodetectors…………………………………………………... 87 3.3.4 Lasers and Light Emitting Diodes……………………………….90 3.3.5 Optocouplers……………………………………………………. 92 3.3.6 Solar Cells………………………………………………………. 96 4.0 Summary…………………………………………………………………………...99 5.0 Acknowledgments………………………………………………………………....100 6.0 References………………………………………………………………………...100 IV-50

1.0 INTRODUCTION Microelectronic and photonic systems in the natural space environment are bombarded by a variety of charged particles including electrons, trapped protons, cosmic rays, and solar particles (protons and other heavy ions). These incident particles cause both ionizing and non-ionizing effects when traversing a device, and the effects can be either transient or permanent. The vast majority of the kinetic energy of an incident proton is lost to ionization, creating the single event effects (SEEs) and total ionizing dose (TID) effects described in section IVA. However, the small portion of energy lost in non-ionizing processes causes atoms to be removed from their lattice sites and form permanent electrically active defects in semiconductor materials. These defects, i.e., “displacement damage,” can significantly degrade device performance. In general, most of the displacement damage effects in the natural space environment can be attributed to protons since they are plentiful and extremely energetic (and therefore not readily shielded against). For this reason, we consider only proton induced displacement damage in this course. (Nevertheless, we identify solar cells as an important example of a case where both electron and proton damage can be important since only very light shielding is feasible.) The interested reader is encouraged to explore the three previous NSREC and RADECS short courses [Srou88a, Summ92, Hopk97] which also treat displacement damage issues for satellite applications. Part A of this segment of the short course introduces the space environment, proton shielding issues, and requirements specifications for proton-rich environments. In order to exercise the displacement damage analysis tools for on-orbit performance predictions, the requirements document must provide the relevant proton spectra in addition to the usual total ionizing dose-depth curves. Ion-solid interactions and the nature of the displacement damage they generate have been studied extensively for over half a century, yet they still remain a subject of investigation. In this section, a description of the mechanisms by which displacement damage is produced will be followed by a summary of the major consequences for device performance in a space environment. Often the degradation of a device parameter can be characterized by a damage factor (measured in a laboratory using monoenergetic protons) that is simply the change in a particular electrical or optical parameter per unit proton fluence. In addition, we will describe the concept of a non-ionizing energy loss rate (NIEL) which quantifies that portion of the energy lost by an incident ion that goes into displacements. It has been calculated as a function of proton energy, and is analogous to (and has the same units as) the linear energy transfer (LET) for ionizing energy. We will discover that, to first order, the calculated NIEL describes the energy dependence of the measured device damage factors. This observation provides the basis for predicting proton induced device degradation in a space environment based on both the calculated NIEL and relatively few laboratory test measurements. The methodology of such on-orbit device performance predictions will be described, as well as the limitations. Several classes of devices for which displacement damage is a significant (if not the dominant) mode of radiation induced degradation will be presented. The examples IV-51

will illustrate various aspects of displacement damage in more detail. We will see, over and over, that the impact of a particular level of damage on device performance is very application-dependent. It will also become clear that uncertainties in the on-orbit prediction for devices sensitive to displacement damage may require significantly increased radiation design margins. All too often, the design engineer is more familiar with basic total ionizing dose (TID) and traditional SEE effects, and may find it difficult to accept the need for proton testing, and especially, any increased radiation design margin associated with uncertainties in displacement damage analyses. There is an increasing demand to employ displacement damage sensitive devices (e.g., charge coupled devices (CCDs), photodetectors, light emitting diodes (LEDs), optocouplers, solar cells, and high precision linear devices) in harsh proton environments (and/or on longer missions). This has led to a renewed interest in hardness assurance techniques for such devices [LaBe98]. It is hoped that this course will provide the understanding necessary for a radiation effects engineer to identify technologies requiring evaluation for possible displacement effects, use the current literature to make first order estimates of device performance, and help ensure that appropriate laboratory radiation testing and analyses are performed. For those readers interested in surveying proton induced device effects (as opposed to performing displacement damage analyses), we recommend reading section 2.2 on displacement effects in devices followed by section 3.3 which includes case studies of those technologies most affected by displacement damage.

2.0 PROTON INDUCED DISPLACEMENT DAMAGE MECHANISMS AND TOOLS In this section, we describe proton displacement effects, on-orbit prediction tools for device performance and laboratory radiation test issues. We begin with a general description of the underlying physical processes that generate displacement damage. The initial production of defects in the semiconductor by incident protons, and the subsequent evolution of this damage to its final stable defect configuration is then described in section 2.1. We discuss the processes by which these defects electrically alter the semiconductor material, and thereby impact device performance in section 2.2. Section 2.3 contains a description of the non-ionizing energy loss rate (NIEL), after which we present the first order correlation between NIEL and device degradation that is experimentally observed. We identify the implications of this correlation in terms of the basic damage mechanisms described in section 2.1, and provide the basis for understanding the limitations of the correlation in section 2.3.2. The NIEL concept enables comparison of the displacement damage produced by protons of different energies (or a spectrum of proton energies) via the calculation of displacement damage equivalent fluences (section 2.3.3), or the “displacement damage dose” (section 2.3.4). This is analogous to the calculation of total ionizing dose based on the proton fluence and LET [see section IVA, equation 1]. Using these tools we establish a methodology for on-orbit device performance predictions in section 2.4. Figure 1 summarizes the method used to predict the on-orbit device (or circuit) response to

IV-52

displacement damage. Note that some devices may have significant concurrent total ionizing dose effects that must also be considered.

Irradiation of Device with Monoenergetic Protons

Calculation of Incident Proton Spectrum for Given Mission

Measurement of Parametric Degradation

Calculation of Spectrum at Device Location Behind Shielding

Calculation of Device Degradation versus DD Dose*

NIEL

Calculation of DD Dose* for Given Mission

Prediction of On-Orbit Device Performance * DD Dose is displacement damage dose. Alternatively one may substitute the displacement damage equivalent fluence for a selected proton energy.

Figure 1 Block diagram of the generic methodology for performing a on-orbit predictions of device performance when device degradation is dominated by displacement damage effects.

2.1 Displacement Damage Mechanisms and Defect Formation As indicated above, the interaction between a charged particle (such as a proton) and a solid cause both ionizing and non-ionizing effects. Most of the kinetic energy of an incident proton is lost in interactions with atoms in the semiconductor that transfer energy to the electron clouds causing excitation or ionization. However, a very small fraction (< 0.1%) of the energy loss causes the atoms to be displaced from their equilibrium sites, and can lead to lattice disorder. An incident proton may collide with a semiconductor nucleus and displace it from its site producing a primary knock-on atom (PKA). If sufficiently energetic, the PKA displaces more atoms, and the collision cascade proceeds until the magnitude of energy transferred becomes less than the threshold required for displacements. At a given incident proton energy, the recoil atoms can vary in kinetic energy from near zero up to some maximum determined by collision mechanisms. Both

IV-53

the average recoil energy and the shape of the recoil spectrum depend on the energy, mass, and charge of the incident particle and the mass of the target. EXITING PARTICLE

INCIDENT PARTICLE

STABLE DEFECT

Interstitial Vacancy Dopant of Impurity Atom

Figure 2a Cartoon showing the displacement of an atom from its lattice site by an incoming proton, thereby forming a vacancy-interstitial (Frenkel) pair. Surviving vacancies migrate through the lattice and often form electrically active stable defects in conjunction with an impurity or dopant atom.

Regardless of whether an atom is displaced as a part of a damage cascade or as an isolated lower energy PKA, most of the initial vacancy-interstitial pairs recombine and no permanent damage results. The interstitial Si atoms do not form electrically active defects. However, the vacancies that escape recombination migrate through the lattice and ultimately form relatively long-lived and immobile defects. Figure 2a is a cartoon illustrating how the initial formation of a Frenkel pair, which is unstable, ultimately results in the formation of a stable defect. These defects have energy levels within the bandgap of the semiconductor. For example, in Si, two vacancies may combine to form a divacancy that is stable up to about 300 °C, or a vacancy and a phosphorous (or oxygen) atom may form an E center (or A center) which is stable up to about 150 °C (or 350 °C), respectively [e.g., Watk64, Walk73 and Kime79]. The vacancy itself is mobile even at liquid nitrogen temperatures, so it is not practical to attempt to prevent the formation of these defects. The process during which the initial vacancy-interstitial pairs evolve into stable room temperature defects results in the so-called “short term annealing effects” in Si devices, and is usually complete within about a second [Srou70, Hein83, Gove84, Mess86]. Figure 2b is a qualitative pictorial showing the time evolution of the number of surviving defects. Note that the stable damage produced in a space environment is very dilute. Longer term room temperature annealing is often observed over a period of IV-54

days or weeks, but it is generally a small effect. For this reason, displacement damage is considered to be a “permanent effect.” Vacancy-Interstitial Recombination

Number of Defects

Vacancy Migration

Stable Defect Formation

Time

Figure 2b Illustration the time evolution of the initial vacancy-interstitial pairs to the formation of stable defects. The annealing of Frenkel defects occurs in less than 1 millisecond and stable defects are formed on the time scale of seconds.

Displacement Damage Processes in Si PROTON ENERGY

6-10 MeV

> 20 MeV

Log N FREE DEFECTS, Coulomb

SINGLE CASCADE, Nuclear Elastic

MANY SUB CASCADES, Nuclear Reactions RECOIL ENERGY

1-2 keV

12-20 keV

Figure 3 Pictorial relating the initial defect configuration to the primary knock-on atom (PKA) energy in Si material. Note from the plot of the number of interactions (N) versus incident proton energy that most interactions are Coulomb events producing isolated defects. For recoil energies IV-55

above a couple of keV, the overall damage structure is relatively unchanged due to the formation of cascades and subcascades. After [Wood81].

The final configuration of electrically active defects formed by particle irradiation has been a topic of much research, but is still not well understood. As we will see this issue is at the heart of understanding the use and limitations of calculated non-ionizing energy loss rate (NIEL) damage functions to predict the displacement damage response of a device in a proton environment. Figure 3 is a pictorial of the spatial distribution of the initial vacancy-interstitial pairs in Si investigated using the Monte Carlo code MARLOWE [More82]. As can be seen from the plot of the log of the number of interactions (Log N) versus the incident proton energy, most events are Coulomb interactions which produce PKAs with Ethreshold < E < ~2 keV, and result in isolated defects. Although there are many fewer of the nuclear elastic and inelastic reaction events that produce cascades, these events are far more damaging, and can contribute a significant fraction of the total displacement damage at higher proton energies. As indicated in the figure, recoils with energies between about 2-10 keV produce single subcascades, whereas those with energies in excess of 12-20 keV form a tree-like structure with branches containing multiple subcascades. Similar results were obtained for Si by Mueller et al. who also investigated the defect structure near the end of the recoil track. The term “terminal cluster” has been used to describe the damaged region where the recoil ion loses the last 5-10 keV of energy and has the highest elastic scattering cross section [Muel82]. They found that a single cascade is likely to have 2-3 terminal clusters with a characteristic dimension of 5 nm, connected to each other by a string of dilute displacements. (Note that this size is an upper limit since the calculation does not include the initial vacancy-interstitial recombination.) This result is consistent with transmission electron microscopy measurements [Lars78, Nara81] of 1 MeV, 14 MeV and fission neutron-irradiated Si that have found an average size of 4 nm for the damage. It is clear that the early terminal cluster models based on heavily damaged regions extending for 200 nm [VanL80, and references therein] are not supported by more recent work. Unfortunately, the early cluster models derived support from electron microscopy [Bert68] work that later was shown to be compromised by faulty etching techniques [Nara88]. We also note that electrical measurements on irradiated devices performed in the last decade or so are also inconsistent with the early cluster models. The interested reader may refer to the literature for details [e.g., Summ87, Peas87, Dale88].

2.2 Displacement Damage Effects in Materials and Devices The net electrical activity of a given defect with an energy level (Et) in the bandgap is ultimately produced by five basic processes as illustrated in figure 4: (1) the generation of electron-hole pairs, (2) the recombination of electron-hole pairs, (3) carrier trapping, (4) the compensation of donors or acceptors, and (5) the tunneling of carriers.

IV-56

C ond uctio n Ban d

E DO N O R

EC

Et

EV

Tu nnelin g

Vale nce B and Generation R ecom b inatio n Trapping C om p ensation

Figure 4 Schematic of the electrical effects that may occur due to the presence of radiation induced defect levels in the band gap of a semiconductor. After [Gove84].

Physically, electron-hole pair generation occurs by the thermal excitation of an electron from the valance band to the defect level followed by its emission to the conduction band. Midgap energy levels in a depletion region are most effective at generating dark current in a device via this process. Recombination occurs when a carrier of one sign is captured at a defect, and not re-emitted before a carrier of the opposite sign is also captured. The energy may be released in the form of light (radiative recombination), or in the form of phonons (i.e., lattice vibrations) which is termed non-radiative recombination. The minority carrier lifetime, which is a key parameter in device performance, is determined by the recombination rate [e.g., Schr82]. Carrier trapping refers to the process whereby a carrier is captured at a defect and then released to its original band. In the case of CCDs, signal charge may be trapped only to be released after the signal packet has already passed causing the charge transfer efficiency of the device to degrade [Mohs74]. Filled traps with a net charge are more effective scattering centers thereby reducing carrier mobility. Carrier removal results when a majority carrier is trapped. Compensation is also responsible for carrier removal. As seen in the figure (for n-type material), the free electrons provided by the shallow donor levels are compensated by deep lying acceptor levels thereby reducing the net carrier concentration. For example, the resistance in a lightly doped collector of a bipolar transistor can increase as a result of this type of carrier removal. Finally, defect levels can assist tunneling through a potential barrier in the bandgap. This effect can produce increased current in a reverse biased junction, and is most significant in materials with small bandgaps and high electric fields.

IV-57

The most important material parameters for the practical operation of most semiconductor devices are the minority carrier lifetime, the generation lifetime [Schr82], the majority carrier concentration and the majority carrier mobility. Typically, the semiconductor material quality is high so that there is at least an order of magnitude smaller density of recombination and generation centers as compared to the majority carrier concentration. As a result, the proton induced introduction of defects (i.e., recombination centers) will impact the minority carrier lifetime well before there is a noticeable reduction in carrier concentration. The same is true for defects produced in depletion regions that can act to decrease the generation lifetime. Mobility degradation is not generally an issue except at very high displacement damage levels. Hence, devices whose primary characteristics depend on minority carrier or generation lifetimes will be most sensitive to displacement damage. Radiation induced degradation in the carrier lifetime, carrier concentration and mobility in turn impact device characteristics such as transistor gain, transconductance and saturation voltage, dark current, detector responsivity, etc. As just described, the reduction of the minority carrier lifetime is a principal cause of degradation in a number of device types. Examples include gain reduction in bipolar transistors and silicon controlled rectifiers (SCRs), reduced responsivity in photodiodes and Schottky-barrier diodes, decreased solar cell efficiency, etc. Devices with lightly doped active regions are most susceptible to degradation caused by carrier removal. Semiconductor light sources such as lasers and LEDs are generally relatively radiation hard since the carrier lifetimes in the active device regions are very short. However, amphoterically-doped LEDs, employed in some optocouplers, are a notable exception and are quite sensitive to proton induced displacement damage for reasons that are not completely understood. Displacement damage effects do not limit the performance of most MOS devices, which depend on majority carrier transport. Exceptions include optoelectronic device types such as the charge injection device (CID) and charge coupled device (CCD), which are extremely sensitive to displacement damage. CCDs are subject to dark current increases resulting from decreased generation lifetime, and from charge transfer efficiency (CTE) degradation due to carrier trapping. JFET and MESFET technologies, being majority carrier devices, are generally very robust to displacement damage [e.g., Hash94] although their transconductance may be degraded by carrier removal at high proton exposure levels. Table 1 summarizes the relative importance (primary or secondary) of displacement damage in many common device technologies [after Srou88a]. Radiation effects experience over the last 20 years has led to a general understanding of device type sensitivities and degradation modes in response to displacement damage. Summaries of these efforts may be found in general radiation effects texts [e.g., Mess86, Holm93] and in a number of summary papers [e.g., Gove84, Srou88b, Raym87]. The case studies to be considered in this course will also provide brief descriptions of displacement damage effects in selected device types.

IV-58

Table 1. Displacement Damage Mechanisms for Various Technologies1 Component

Lifetime Degradation

Carrier Removal

Trapping

Si MOS Transistors & ICs

Mobility Degradation S

Charged Coupled Devices

P

Si Bipolar Transistors & Linear ICs

P

Photodetectors

P

LEDs & Laser Diodes

P

pn Junctions

P

P S

P

P

JFETs

P

P

GaAs Transistors & ICs

P

S S

P = Primary; S = Secondary 1

After [Srou88a]. Note that TID and SEEs also can be primary radiation concerns for these technologies.

2.3Non-Ionizing Energy Loss Rate (NIEL) Concept As we will see in the next section, it has been shown that the radiation response of many devices can be predicted reasonably well based on calculations of the amount of displacement damage energy imparted to the primary knock-on atoms. The non-ionizing energy loss rate (NIEL) can be calculated analytically from first principles based on differential cross sections and interaction kinematics. NIEL is that part of the energy introduced via both Coulomb (elastic), nuclear elastic, and nuclear inelastic interactions, which produces the initial vacancy-interstitial pairs and phonons (e.g., vibrational energy). NIEL can be calculated using the following analytic expression that sums the elastic and inelastic contributions as: NIEL = (N/A) [σeTe + σiTi].

(1)

The σ’s are total cross sections, the T’s are effective average recoil energies corrected for ionization loss using the Lindhard theory [Lind63], N is Avogadro’s number, and A is the gram atomic weight of the target material. In the case of compounds, the total NIEL is derived as a superposition (weighted by mole fraction) of the contributions for each atomic component [Zeig84]. Notice that the units of NIEL, (keVcm2/g), are the same as IV-59

those for stopping power (or LET) describing energy transfer by ionization and excitation per unit length. Burke has calculated NIEL in silicon for protons and other ions over a broad energy range [Burk86]. More recent calculations by Burke have incorporated improvements in the treatment of the nuclear elastic and inelastic reactions, and the Lindhard correction has been applied to the differential recoil spectrum instead of to the average recoil energy of the target atoms. The more accurate calculation is given by NIEL = N A ∫ L[T ( Θ)]T ( Θ) [dσ dΩ]dΩ

(2)

where dσ/dΩ is the differential cross section for a recoil in direction Θ, T(Θ) is the recoil energy, and L[T(Θ)] is the fraction of the recoil energy that goes into displacements [Lind63]. In the case of Si, the maximum amount of displacement damage energy is about 300 keV, regardless of the energy of the recoiling atom. The maximum damage energy increases with atomic number, and is about 2 MeV for GaAs. Figure 5 shows both the LET and NIEL for Si as a function of incident proton energy. Burke has calculated the proton NIEL for a variety of other materials. The most recent published NIEL calculations can be found in the December IEEE Transactions of Nuclear Science cited as follows: InGaAs [Mars92], GaAs and InP [Summ93], and Si [Dale94].

2

ENERGY LOSS RATE (MeVcm /g)

1000

100

Ionizing 10

1

0.1

Non-Ionizing 0.01

0.001 1

10

100

1000

PROTON ENERGY (MeV) Figure 5 Comparison of the energy loss rate through ionization and excitation of the Si lattice (LET), and through atomic displacements (NIEL) over a wide range of proton energies. The LET was calculated as in [Zeig85], and NIEL as in [Dale94].

IV-60

The nature of displacement damage as a function of proton energy is governed by the interaction cross sections, and the non-ionizing energy of the PKAs as governed by the Lindhard function. For proton energies below about 10 MeV, Coulomb elastic scattering is by far dominant in Si, and produces atomic recoils with non-ionizing energies in the hundreds of eV. At higher energies, the bend in the curve occurs because nuclear elastic scattering becomes more important resulting in recoils with non-ionizing energies in the tenths of MeV range. As the incident proton energy increases the elastic cross section decreases athough it is still larger than the inelastic cross section. By about 100 MeV half of the non-ionizing energy imparted to the Si lattice is from nuclear inelastic reactions with a mean PKA non-ionizing energy that is still about 0.1 MeV (due to the Lindhard partition). NIEL has also been calculated by other means including Monte Carlo programs such as HETC [Alur91], CUPID [McNu81, McNu94] and TRIM [Zeig84]. A comparison between the most recent Burke and CUPID calculations of Si NIEL is discussed in [Dale94]. Although HETC, CUPID and Burke’s calculations of the recoil distributions as a function of incident proton energy show similar trends, they differ in details [Dale94]. The TRIM program only includes the Coulombic interactions, so it is not appropriate to use it directly for damage calculations for proton energies above about 8 MeV or so, depending on the target material. Note that all of the above calculations include a “fudge factor” that accounts for the fact the most of the initially produced vacancy-interstitial pairs recombine and therefore do not produce electrically active defects. For example TRIM is often executed assuming a displacement energy threshold of 25 eV, which is considerably higher than the actual value. This practice helps to account for the efficiency of the initial recombination of the vacancy-interstitial pairs. In other Monte Carlo codes such as MARLOWE, one also has the option to define a radius around each collision point for which all the vacancy-interstitial pairs recombine. In essence, all current NIEL calculations must be scaled to fit the experimental damage factors, unless damage factor ratios are compared. As we shall see, it is the calculation of the energy dependence that is relevant, not the absolute values of NIEL. 2.3.1 The Correlation of NIEL to Device Behavior Device degradation in a radiation environment is often characterized by defining a damage constant, or a damage factor. Damage constants describe the change in basic material parameters such as minority carrier lifetime or diffusion lengths, produced by a given fluence of protons of a specific energy. (Fluence is defined as the number of incident particles per unit target area, and has units of cm-2.) Damage factors are similar except they characterize the observed radiation induced degradation of device or system parameters that may not be readily reduced to basic material parameters because a detailed device model is not available.

IV-61

The following well known equation describes the degradation in minority carrier devices that results from the reduction in the diffusion length that accompanies the introduction of radiation induced defect recombination centers: 1/L2=1/Lo2 + KΦ.

(3)

The initial and post-radiation diffusion length is given by L0 and L, respectively, K is the damage constant, and Φ is the proton fluence. (Sometimes this equation appears in terms of the minority carrier lifetime, τ, using the relation, L = (Dτ)0.5, where D is the diffusion coefficient.) Usually the satellite designer or test engineer is interested in a particular device parameter, and defines a relevant damage factor. In the case studies to follow, we will see examples of other useful device damage factors such as the CCD CTE damage factor, the dark current damage factor, the solar cell efficiency damage factor, and so on. In each case, the device parameter in question changes linearly with fluence, or else is defined in the linear region. Note that parameters such as inverse bipolar transistor gain, detector responsivity, and CCD dark current, which have a well-defined regime with a linear response, may also exhibit a nonlinear response at very low or very high proton fluences. (We will also see examples where a device parameter of interest such as LED light output or optocoupler current transfer ratio does not behave linearly in the proton fluence regime of interest.) Bipolar transistor gain measurements for a variety of incident particles (as a function of energy) have been performed in order to determine whether the NIEL function can be used both to predict the energy dependence of the device damage factor and to correlate the degradation due to different particles [Summ87]. In principle, such a correlation also provides the basis for on-orbit performance predictions based on the measurement of a damage factor at a single proton energy. Likewise, if neutron data already exists, the correlation can be used to predict the device response to protons. In this work, the well-known Messenger-Spratt equation is used to describe the radiation response of the common emitter DC gain, hFE, of a bipolar transistor: 1/hFE = 1/hFEO + K(E)Φ

(4)

where 1/hFEO is the initial reciprocal gain, K(E) is the particle and energy dependent displacement damage factor, and Φ is the incident particle fluence. The transistor gain (given by the ratio of the collector to base currents) decreases with increasing proton fluence primarily as a result of the decreased minority carrier lifetime in the base region. A more detailed description may be found in [Mess86]. The damage factor is determined experimentally by performing device gain measurements (for a particular set of device operating conditions) after incremental exposures at a given proton energy. Figure 6 shows the measured damage factors for protons, deuterons and helium ions normalized to the 1 MeV-equivalent (Si) neutron damage factors as a function of ion energy for a variety of Si bipolar transistors. (We will discuss the meaning of MeV equivalence in a later section, and neutron damage equivalence is explored in [Luer87]. For the present purposes we note that by comparing ratios of measured damage factor to IV-62

the calculated NIEL ratios, no scaling parameter is needed to match data with theory.) The importance of this result is the proportionality between the measured damage factors and calculated NIEL that provides the basis of the on-orbit predictions of device degradation produced by displacements.

Figure 6 The transistor damage factor ratios for a variety of particles with fission neutrons are shown together with the corresponding calculations of the NIEL ratios. Note that both ordinates are identical (with no fitted parameters), which indicates a direct proportionality between NIEL and the damage factors over a wide energy range. After [Summ87].

Research performed in the last dozen years has shown that, to first order, the linear relationship between the device degradation from particle-induced displacement damage and NIEL holds for a variety of electrical parameters, incident particles, and device materials [Summ87, Peas87, Dale88, Mars89a, Walt91, Mars92, Ohya96, etc.]. This is a surprising result when we consider that NIEL calculations describe the energy deposited into the formation of Frenkel pairs (over 90% of which recombine), and do not consider the process by which the stable electrically active defects are formed. Since NIEL is a direct measure of the initial number of vacancy-interstitial pairs created, the implications of the NIEL correlation with device degradation are that: (1) the percentage of initial vacancy-interstitial pairs that survive recombination is independent of the PKA energy, and (2) the resulting stable defects have the same device effect regardless of whether they evolved from a vacancy-interstitial pair originating in a subcascade or as a well-separated pair [Dale88]. In addition, given that various stable defects have quite IV-63

different electrical properties, the correlation also implies that the defect inventory produced is independent of PKA spectrum. Nevertheless, the degree to which the NIEL correlation holds is qualitatively consistent with the Monte Carlo calculations described earlier. These simulations show that a higher energy PKA will produce more overall damage, but that the microscopic nature of the damage is not drastically different. The branching process simply creates more and more subcascades, each separated by a string of relatively isolated defects. It is still important to keep in mind that, although defects produced from isolated vacancy-interstitial pairs (such as those produced by gamma rays and 1 MeV electrons) may have similar electrical characteristics to those produced by heavier particles such as protons and neutrons, there are important differences. These differences are not restricted to short term annealing effects, and also manifest themselves in the long term behavior of a device. For example, E-centers (vacancy-phosphorus defects) produced by 1 MeV electrons anneal at a significantly lower temperature than those produced by protons [Walk73, Kime79], a relevant (and unfortunate) fact for charge coupled device (CCD) engineers who have considered on-orbit warm-ups to mitigate charge transfer efficiency degradation in CCDs [Holl91a]. Differences in the operation of SiGe transistors [Rold98] and AlGaAs/GaAs solar cells [Barn84] have been attributed to differences in the defects produced by neutrons versus protons. Very well controlled deep level transient spectroscopy studies [Eise92, Mind76] have unequivocally demonstrated that, although 1 MeV electrons and protons produce some of the same defects in n-GaAs, there are also different defects produced by each particle. The bottom line for the satellite designer working a mission in a proton environment is that devices that are highly sensitive to displacement damage should be radiation tested with protons. We will see other reasons for this recommendation later in the short course. 2.3.2

Limitations in Usage of NIEL

The NIEL calculation is a useful tool to approximate the expected proton induced radiation response in a space environment, but it is necessary to appreciate the underlying assumptions and limitations in order to use it effectively. Deviations at very low proton energies (approaching the displacement energy thresholds) are expected [Dale 88, Summ93], but they are not generally of concern for proton applications in space because they contribute little to the total displacement damage behind typical shielding, as will be shown in section 2.4. However, indications of other systematic deviations from the NIEL correlation have been observed in Si device measurements (e.g., for several CCDs, a CID, a 2N2907 bipolar transistor [Dale88]), and also in GaAs measurements (e.g., an LED [Barr95], a laser diode [Zhao97], solar cells [Walt99], and a JFET [Summ88]). Depending on how the damage factor measurements were normalized to NIEL, the deviations have been reported either as the damage factors being over-estimated by NIEL at higher energies, or equivalently, being underestimated by NIEL at the lower energies. The choice of a damage function (i.e., the energy dependence given by the calculated NIEL or experimental damage factors) has been shown to be significant. For example, one study found a factor of two difference in the on-orbit predictions of the degradation in Si CCD performance depending on which damage function is employed [Dale91]. IV-64

Figure 7 Transistor damage factors and dark current damage factors for protons (normalized to fission neutron damage factors) versus NIEL. The lower line (with a slope of one) indicates a linear relationship between the damage factor ratios and NIEL. The deviations from linearity are indicated with the upper line. [After Dale89b]. A similar figure in [Dale88] also shows deviations for transistor damage factors measured for electrons.

Deviations from the linear dependence of Si displacement damage factors with the NIEL energy dependence are shown in figure 7, which shows the proton to neutron damage factor ratios for several devices plotted as a function of NIEL [Dale88]. The damage factors represent changes in the minority carrier lifetime in the case of the transistor data, and the generation lifetime in the case of the CID and CCD dark current damage factors. A slope of one on the log-log plot indicates a linear relationship, and the observed deviation from linearity is noted by the top curve. Dale et al. defined a “damage enhancement factor” as the ratio of observed damage factor ratio (upper line) to that expected based on the linearity with NIEL (lower line). In this work, the PKA spectrum produced in Si by the various incoming particles was calculated. Note that the PKA spectrum varies significantly over the range of proton energies of interest in space. It may come as a surprise that the PKA spectrum of a 60 MeV electron is more like that of a 10 MeV proton, than a 10 MeV proton is like a 60 MeV proton. As seen in figure 8, the damage enhancement factor is found to correlate with the fraction of the total NIEL due to PKAs with energies less than 1 keV. It is notable that the result held for the wide range of PKA spectra produced by 4.1 MeV electrons, all the way to 1 MeV-equivalent neutrons that produce very high energy recoils. The observed deviations from linearity would be expected if there were less recombination of initial vacancy-interstitial pairs IV-65

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that are formed by lower energy PKAs (which produce well-separated Frenkel pairs). This result is consistent with the previously described Monte Carlo calculation of collision cascades showing that the more dense subcascades do not begin to form until PKAs have energies over about 2 keV. Later measurements of the CTE degradation in Si CCDs (from 2 manufacturers) over a wide range of proton energies also reveal enhanced damage at lower proton energies [Dale93]. However, we note that such deviations were not apparent in a study by Luera et al. [Leur87].

1 keV 10 keV 2 keV 5 keV

0.8 0.6 0.4 0.2

1.0 1.4 1.8 2.2 '$0$*((1+$1&(0(17)$&725 Figure 8 The correlation between percent NIEL in Si due to recoils in the various energy ranges and the magnitude of the deviation from the ideal linear dependence is shown. The particles associated with a given deviation are labeled at the top of the figure. After [Dale88].

Evidence that lower energy protons are more effective at producing displacement damage in GaAs as compared to higher energy protons (than the NIEL correlation would indicate) has been reported by Luera et al. [Luer87, Grif91] and Barry et al. [Barr95]. These studies were based on measurements of carrier removal in Van der Pauw samples and minority carrier lifetime degradation in LEDs. Once again, the results were explained by variations in the recombination efficiency of the Frenkel pairs with PKA energy. In 1995, Barry et al. extended measurement of the minority carrier lifetime damage factors in GaAs LEDs to proton energies as high as ~500 MeV [Barr95]. IV-66

Figure 9 compares these results with the NIEL calculation by Burke [Burk87]. Other results in the literature also indicate departures of damage factors from the NIEL energy dependence [Zhao97, Summ88]. Although the 1993 paper by Summers et al. claims to have demonstrated a general linear correlation between device “proton damage coefficients” and NIEL for Si, GaAs and InP, using “solar cells as examples,” it is important to note that the data presented do not cover the relevant range of proton energies for most satellite applications which are more heavily shielded. For example, both the GaAs data (from [Ansp92]) and the InP data (from [Yama84]) are for protons below 20 MeV, and are indeed most relevant to lightly shielded solar cell applications. It is interesting to note that a recent paper based on the same solar cell data set [Ansp92], shows damage coefficients falling below the calculated GaAs NIEL at higher proton energies [Walt99], consistent with figure 9. (The authors did not discuss this trend which was not relevant to their recent solar cell study.) Clearly, further efforts are required to better understand the nature of these deviations.

NIEL (MeV - cm2/g)

NIEL Calculation Summers et al., 1988

NORMALIZED DAMAGE FACTORS

Experimental Data Burke et al., 1987 Summers et al., 1988 Barry et al., 1995

PROTON ENERGY (MeV)

Figure 9 Experimental damage factor from several studies are normalized to the GaAs NIEL calculation at 10 MeV. A significant deviation between the observed damage factors and NIEL is apparent for proton energies above about 40 MeV. Adapted from [Barr95].

During semiconductor research efforts in 1950s, it was noticed that NIEL calculations (which compute that portion of the total energy deposited via non-ionizing interactions) significantly over-estimated defect production. Analytic expressions were developed with energy dependent damage efficiency coefficients that represented the likelihood that the initial Frenkel pairs would survive recombination, and experimental efforts confirmed this behavior in metals [Aver83, Hein83]. If the space radiation effects community plans to use calculated displacement damage functions to describe the energy IV-67

dependence of device response for more than rough approximations, it needs to move beyond NIEL calculations and investigate the time evolution of the initial damage to a variety of electrically active defects. It is not clear to what degree the physical processes need to be modeled in order to derive a sufficiently accurate damage function for use by the radiation effects community. In the meantime, the satellite designer must typically make on-orbit device performance assessments based on laboratory radiation measurements at one (or at most a few) proton energies, and therefore must make an assumption concerning the energy dependence the measurements will follow. There are several possible approaches including use of: (1) a calculated NIEL curve, (2) an experimental displacement damage curve (if available), or (3) a piecewise “manufactured” worst case displacement damage function. All of these approaches have significant uncertainty associated with them that must be reflected in the design margin applied to a given application. 2.3.3 Calculation of Displacement Damage Equivalent Fluences It is very useful for the radiation design engineer to become comfortable with the calculation of damage equivalent fluences (and displacement damage dose). Data in the literature are collected using a variety of incident proton energies, and one needs to be able to convert to an equivalent fluence at a particular energy of interest. (The respective fluences are “equivalent” in the sense that they will produce the same amount of displacement damage in the device.) Likewise, it may be necessary to convert the proton spectrum for a particular mission to an equivalent fluence at a specific proton energy. To the extent that the proton energy dependence of the device degradation correlates with NIEL (or a relevant measured damage function), radiation testing can (in principle) be performed at only one proton energy. In practice, we have seen that there can be significant uncertainty in the energy dependence of the device radiation response. Nevertheless, program constraints often restrict proton testing to a single energy, and it is important to choose the test energy very carefully. We will see in section 2.4 that we can use our displacement damage analysis tools to select appropriate test energies, and that the choices will depend on the degree of device shielding in a particular application. Many of the space applications employing photonic devices (e.g., CCDs, etc.) are heavily shielded, and the peak in the transported proton spectra is shifted to higher energies, typically between 40-100 MeV. (Refer to part IVA, section 2 for a description of proton environments and shielding.) For this reason, and because package penetration and energy deposition uniformity issues are simplified when very penetrating protons are used, higher energy protons are frequently employed for radiation tests. In this approach any error introduced by a lack of correlation between the measured property and the displacement damage function is minimized. The optimal choice for a single test energy is the one that best represents the damage-weighted proton spectrum calculated using a displacement damage function. As illustrated in the next section, one can calculate the differential or integral displacement damage energy deposition as a function of proton energy and use these results to aid in the selection of proton test energies [Dale91]. IV-68

Once one or more proton test energies have been chosen for a particular space mission, the relevant MeV-equivalent fluences can be calculated using the calculated NIEL (or an experimental damage function) and the differential proton fluence spectrum, dΦ(E)/dE, for the time period of interest. Note that a given mission may be represented by a time-weighted sum of more than one differential spectrum depending on the details of orbital precession, solar cycles, etc. The MeV-equivalent proton fluence at a given test energy, Etest is given by: E2 dΦ (E ) ∫E1 dE NIEL( E )dE Φ (Etest ) = NIEL( Etest ) (5) where the numerator is just the total displacement damage dose in units of MeV/g when NIEL(E) is expressed in units of MeVcm2/g. The integration limits, E1 and E2, generally correspond to the lowest and highest proton energies provided in the differential spectrum, typically from about 0.01 MeV to about 500 MeV. Note that the range of integration may be reasonably adjusted depending on the degree of shielding present [Dale91, Mess97]. As an example, a 60 MeV-equivalent fluence is simply the fluence of 60 MeV protons that produces the same amount of displacement damage dose as the time-integrated transported proton spectrum representing the mission environment. Equation 5 can also be used to calculate the mission equivalent fluence at a proton energy for which there is relevant device data in the literature. In this way, one can assess the suitability of a candidate device for a particular mission, or (as often is the case) to provide an initial assessment of a device already chosen. The NIEL correlation may also be used to estimate the relative damage of protons and neutrons, which is useful since there is a large body of literature concerning neutron induced displacement damage. In the case of solar cell applications, minimal shielding is utilized. As a result such devices are subject to displacement damage dose from both electrons and relatively low energy (and more damaging) protons. In the solar photovoltaic community, it is customary to compare the degradation of various technologies to their response to 1 MeV electron irradiation. The on-orbit proton environment is expressed as a 10 MeV proton equivalent fluence, and then converted to a 1 MeV electron equivalent fluence [Tada82]. 2.3.4

Concept of “Displacement Damage Dose”

The concept of non-ionizing energy deposition (e.g., NIEL) plays the same role in displacement damage effects as the ionizing energy deposition (or linear energy transfer (LET)) plays in ionization induced effects [Dale89a]. The units are the same, namely MeV/g. Although displacement damage dose has not yet been treated formally as a unit of dose, the radiation effects engineer may, for practical purposes, define a unit of displacement damage dose as 100 ergs of non-ionizing energy deposited per gram of material. This approach was introduced in 1991 to quantify displacement damage dose effects and simplify on-orbit predictions for the charge transfer efficiency (CTE) in CCDs IV-69

[Dale91, Dale92b]. The advantage of this method is that a single unit provides a simple way to compare the effective amount of displacement damage resulting from any specified space environment or proton fluence at a given test energy. In fact, it was initially introduced as a “non-ionizing rad”, or NIRad(Si), as part of an introductory tutorial for the non-radiation effects personnel in the astronomy community. They were the first to attempt using extremely high quality scientific CCDs in demanding space applications. Since the concept of an ionizing rad(material) is generally familiar to design engineers, it is a useful way to implement a displacement damage analysis tool. Within the radiation effects community, equivalent displacement effects have long been expressed in terms of 1 MeV neutron equivalence [see Mess86, Gove84]. In the last decade, several groups have advocated the usage of various proton energies as the MeV-equivalent comparison of choice. However, the best energy choice is made by consideration of the transported damage-weighted proton spectrum that is very dependent on the shielding material and thickness. For example, a 10 MeV-equivalent proton “standard” might be used for a thinly shielded solar cell project, whereas a 60 MeVequivalent proton “standard” might be chosen for a heavily shielded CCD study. As discussed below, displacement damage can easily be compared in terms of “equivalent proton fluences” at one of these specified energies. Whether one chooses to perform a displacement damage analysis in terms of displacement damage dose or a MeVequivalent fluence, it is very important to identify the damage function employed since the final result can depend critically on this choice.

2.4 On-Orbit Performance Predictions In this section, we will first describe a method for performing space predictions based on the concept of displacement damage dose described above. In practice, it is useful to consider two important cases. In the first, the device parameter of interest (e.g., CCD CTE or dark current) varies linearly with proton fluence (i.e., can be characterized by a damage factor). In the second, the device property of interest (e.g., current transfer ratio of an optocoupler or the maximum power of a solar cell) behaves nonlinearly with proton fluence. In both cases, the energy dependence of the property in question may be assumed to follow the calculated NIEL, and the concept of displacement damage dose in units of MeV/g is employed. (Note that, as discussed above, the NIEL may be replaced by a damage function constructed to provide a worst case performance analysis.) This predictive tool was first used to predict on-orbit CTE in Si CCDs [Dale91, Dale93], but the interested reader can refer to the literature to learn more about this approach as applied to other applications (e.g., InGaAs detector dark current and responsivity predictions [Mars94] and solar cell characterization in space [Sum94, Mess97, Walt99]). We will first illustrate the basic method for performing space predictions for the case where a damage factor can be defined, by calculating the yearly on-orbit CTE degradation for CCDs. Although the present section focuses on the predictive tool itself, we note that some of the issues raised will be explored in more depth in section 3.2.2, which concentrates on displacement damage in CCDs. IV-70

The first step is to define the relevant damage factor, and determine the most appropriate damage function to describe the energy dependence of this damage factor. In the present case, we consider the CTE damage factor, K(E), defined as the change in CTE per unit proton fluence, Φ(E) as shown: ∆CTE ( E ) = K ( E ) ⋅ Φ ( E ) .

(6)

The change in CTE is dominated by bulk displacement damage and therefore linear with proton fluence. The experimental CTE damage factors are shown in figure 10, together with the NIEL calculated in Si. The data from each CCD type exhibit a similar energy dependence, and each data set has been independently scaled to NIEL using a constant, C, which has units of CTE change per unit of non-ionizing energy deposited. Hence, we have (7) K ( E ) = C ⋅ NIEL( E ) .

100

NIEL (MeVcm2g-1)

Leicester (right ordinate) JPL (scale factor in text) NIEL

10-11

10-1 10-12 10-2 10-13 10-3 10-14 10-4 10-1

10-0 101 102 PROTON ENERGY (MeV)

103

CTE DAMAGE FACTOR (• CTE cm2/PROTON)

Recall that a scale factor is necessary because it is not presently possible to make a first principles calculation of the final stable proton induced defect inventory (defect types and quantities), and its effectiveness at causing CTE changes. (The exact value of this constant also depends on a particular imager design and the readout conditions as will be discussed in section 3.2.2.)

Figure 10 The NIEL is compared with experimental CTE damage factors. The data was normalized to NIEL at 10 MeV, and the scale factor values are 3.9x10-11 and 1.2x10-11 ∆CTEg(Si)/MeV for the Leicester (EEV) and JPL (Ford) CCDs, respectively. At higher energies, the data fall below the NIEL curve. The deviations from NIEL are consistent with those observed in figure 7 for a different set of devices. After [Dale93].

IV-71

Figure 10 also shows that the measured CTE damage factor falls below the NIEL calculation at higher energies, for reasons still not well understood (see section 3.2.2). In this example, we perform the on-orbit prediction using the theoretical NIEL calculation as the displacement damage function, in order to provide a conservative engineering estimate of performance. It turns out that the CTE degradation is over-estimated by a factor of two by using the NIEL dependence instead of the energy dependence of the measured damage factors. The final information needed for the on-orbit prediction is the differential proton spectral information, dΦ(E)/dE, for the orbit and shield thickness in question. This is used to calculate the amount of displacement damage at each proton energy for the time period considered. The total damage follows from integrating the damage over all energies reaching the CCD as expressed below: dΦ ( E ) dΦ ( E ) ∆CTE ( E ) = ∫ K ( E ) dE = C ∫ NIEL( E ) dE . dE dE E1 E1 E2

E2

(8)

Note that the integral is simply the displacement damage dose in units of MeV/g when NIEL(E) is expressed in units of MeVcm2/g. The integration limits, E1 and E2, are defined and discussed with equation 5. Despite various mitigation approaches, for devices such as CCDs that are extremely sensitive to displacement damage, it is often necessary to resort to the use of thick shields to minimize the radiation damage at the CCD location. As we will explore in section 3.1.2, displacement damage effects from secondary particles (mostly neutrons) produced in thick shielding can be significant, especially for high atomic number shields such as Ta. To calculate the effects of more than one particle type (such as secondary neutrons produced in shielding), the contribution for each particle is computed independently, as discussed earlier. The NIEL for neutrons in Si is described in [Dale91]. Figure 11 shows the results of equation 8 for the EEV imager in the 705 km, 97.4° polar orbit for four Al shield thicknesses, including the effects of secondary particle damage. The integral displacement damage dose and ∆CTE due to protons above a given energy are obtained by evaluating the integral from E to the highest proton energy. The intercepts show the effects of particles of all energies in terms of non-ionizing energy deposited per gram Si per year, or as the ∆CTE per year. We see that the relative gains from adding shield mass diminish as the shield gets thicker. Also, except for lightly shielded imagers, most of the damage results from protons over 10 MeV. These calculations are useful for determining the most relevant proton test energies for a particular shielding configuration. It can come as a surprise to discover that, in a heavily shielded application, half (or more) of the displacement damage dose is contributed by incident protons with energies in excess of 100 MeV. This is true despite the fact that lower energy protons produce more displacement damage, because the transported proton spectra are becoming much harder with increasing shield thickness. The spectral

IV-72

hardness occurs because the lower energy incident particles have a higher LET and are therefore preferentially stopped in the shielding.

Figure 11 The integral damage spectrum (integrated from the energy in question to the highest proton energy) is shown versus proton energy. The intercepts at zero energy give the yearly total damage for the entire proton spectrum. The values in order of increasing shield thickness are 9.2x106, 6.7x106, 5.3x106, and 2.93x106 MeV g(Si)-1 year-1. The corresponding CTE losses per year given from the right ordinate are 3.6x10-4, 2.6x10-4, 2.0x10-4, and 1.1x10-4, respectively. After [Dale93].

In some cases, the device parameter of interest does not degrade linearly with proton fluence (or displacement damage dose). This behavior has been observed for the degradation of optocouplers [John96, Reed98] and solar cells [e.g., Ansp92, Yama96, Mess97, Walt99], and is discussed further in sections 3.3.5 and 3.3.6. In this case, we measure the device response as a function of displacement damage dose (or MeVequivalent fluence at an agreed upon energy) to assess device performance in relation to the mission requirements. (Care should be exercised when the mission requirement falls in a regime where the device response is changing rapidly with increasing damage dose.) Note that the underlying assumption in this case is still that the device degradation correlates with the NIEL as a function of proton energy. To the extent that this is true, the curves measuring the device degradation as a function of fluence for various proton energies will fall on a common curve if they are plotted versus proton dose calculated using NIEL.

IV-73

In summary, the NIEL-based methodology provides the satellite designer with an invaluable tool for estimating on-orbit degradation due to displacement damage and making use of the displacement damage literature, providing they are used with caution. This is particularly true since the radiation engineer must typically make assessments based on device radiation measurements at one (or at most a few) proton energies, which requires the use of an energy dependent damage function. However, in many cases, the biggest challenge to the satellite designer is to identify a laboratory radiation test that provides an accurate indication of the on-orbit performance to be expected for a given device or subsystem. In the case studies to follow, we will find that the radiation response of a device is very application specific, and that it is sometimes nontrivial to design a relevant laboratory radiation test.

3.0 PROTON DISPLACEMENT DAMAGE CASE STUDIES 3.1 Introduction The following case studies provide examples of the analysis tools presented in Section 2.0, and illustrate the range of issues that can arise in the attempt to assess onorbit performance based on laboratory radiation test programs and displacement damage analysis. The device types represented are those of current interest for which displacement damage issues can be significant. Of course, the complete assessment of a device or technology for use in a space environment demands that all radiation induced degradation be considered including total ionizing dose (TID) and single-event effect (SEE) issues from protons and heavy ions, as appropriate. In some cases, devices that are sensitive to displacement damage also have a noticeable TID response. In general, a good engineering radiation assessment of on-orbit displacement damage effects can be made based on the results of laboratory tests at a proton accelerator. As discussed in section 2.3.3 and 2.4, proton test energies should be wisely chosen based on the shielded proton environment at the device of interest. In this case, the effects of both displacement damage and TID are simulated reasonably well.

3.2 Laboratory Radiation Test Issues For any application where displacement damage is expected to produce significant degradation, it is important to perform a proton radiation test in addition to the routine Co-60 TID evaluation. In some cases (e.g., CCDs), the combination of limited device availability and time-consuming measurement procedures results in the use of proton irradiations to evaluate both the TID and displacement damage response of a device. Recall from the discussion in section IVA, that “a rad is a rad” is a reasonably good assumption for proton energies above about 40 MeV, and it is therefore straightforward to calculate the proton induced TID. If concurrent TID effects are significant, then it is important to design the proton test with appropriate controls on the bias, measurement timing, etc. as described in IV-74

standard TID test methods such as MIL-STD-883, Method 1019. In such cases, there is always the possibility that the failure mechanism (TID versus displacement damage induced) depends on the ionizing dose rate employed in the test. Obviously, this is a concern since typical space dose rates are many orders of magnitude lower than those employed in laboratory proton measurements. Although it is possible to perform lengthy low dose rate testing at a Co-60 source, such testing is not feasible at a proton facility. In some cases, the relative importance of TID versus displacement damage dose may not be well characterized for a particular device. For example, the susceptibility of linear bipolar ICs to displacement damage and TID varies over a wide range because of significant variations in device design and processing techniques [Gaut83, John87, Rax97, Rax98]. A recent study of modern bipolar technology provides general guidelines to help identify cases where displacement damage is most important [Rax98], but sometimes this is best determined by comparing test results for both proton and Co60 exposures. Comparisons are made either by plotting the device degradation as a function of equivalent TID or displacement damage dose. Note that it is generally not possible to separate out the relative importance of TID versus displacement damage dose by comparing exposures at different proton energies. This is because both effects exhibit a qualitatively similar energy dependence as illustrated in figure 5. As will be discussed in section 3.3.5, optocouplers may also be subject to both TID and displacement damage effects [John96, Reed98]. DC-DC converter modules also may fail from either displacement damage or TID degradation, depending on whether the unit uses an optocoupler for isolation. Since CCDs are MOS devices, they are also subject to TID degradation. Although the performance of many CCD devices is limited by displacement damage, those from some manufacturers fail by TID induced threshold shifts in output circuitry. In many cases, it is useful to monitor the device properties after proton irradiation to look for substantial recovery which can be the signature of a device that has failed to function as a result of TID exposure at laboratory dose rates. (This practice can prevent the unnecessary disqualification for a device for space use. Note that this practice is consistent with the Method 1019 standard [Sext92] used for Co-60 tests. This procedure permits a room temperature anneal as a surrogate for a low dose rate test, as long as the device does not fail functionally.) Once again, the comparison of proton and Co-60 test results can help to sort out failure mechanisms. In the case of multi-component modules, one must always consider the possibility of both TID and displacement effects. For example, modules containing photonic devices expected to degrade via displacement damage mechanisms may also contain passive elements (e.g., lenses) that degrade from TID effects. Recently, the response of an InGaAsP laser module to protons was found to be dominated by darkening in a graded index (GRIN) lens, even though the laser itself was quite hard to displacement damage [Mars92]. (This behavior was confirmed through the use of additional Co-60 testing.) Given the wide range of hardness in lens materials, it can be useful to perform a cheaper Co-60 screening test of such modules before proton testing.

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Proton test energies should be selected based on the particular application, as described earlier, but it is always important to ensure that the incident proton has sufficient range to penetrate both the device packaging and the sensitive volume of the device itself. The analysis is greatly facilitated (and more accurate) if the non-ionizing energy loss rate through the active volume of the device is constant, and if the incident proton beam is reasonably monoenergetic. In some cases, the active volume of a device may be very thin, and also close to the surface of the device. If such a device is irradiated with protons normally incident to the surface, the forward directed energetic recoils may deposit their energy below the active device region. As shown in figure 12, it can take several microns to reach “recoil equilibrium” inside a device [Dale94]. Since recoil equilibrium applies to devices in a shielded spacecraft subject to irradiation from all sides, we also should approximate this condition in laboratory radiation tests. If it is questionable whether a device will be in recoil equilibrium for the case of protons incident from the front, the unit may simply be irradiated from the back to achieve equilibrium. This effect may have been at least partly responsible for deviations of Si CCD damage factors from NIEL observed at higher proton energies in figure 10 [Dale94]. Lack of recoil equilibrium was cited in [Summ88] as a possible explanation for the deviations of Si JFET damage factors from NIEL apparent in figure 9. However, Barry et al. [Barr95] eliminated recoil equilibrium as an explanation for the deviation of their LED damage factors from NIEL by also irradiating devices from the backsides with identical results. Although this issue has not been well studied, it is nonetheless straightforward to perform proton irradiations so that recoil equilibrium is satisfied.

Figure 12 The approach to displacement damage equilibrium is shown for several proton energies. It is also shown in [Dale94], that the overlayer thickness required to achieve equilibrium increases as the thickness of the sensitive volume decreases. After [Dale94].

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One frequently asked question is whether or not a device (whose radiation response is dominated by displacement damage up to the fluence in question) may be passively exposed to protons, and then characterized in depth once transported back to the laboratory. In many cases (but not all [e.g., Sun99]), relatively little long term annealing of displacement damage occurs, so that it can be reasonable to irradiate a device, and then return it to the laboratory for testing at a later date. It is generally good practice to ground the device leads during the proton exposure to prevent the possibility of electrical discharges. In most cases, displacement damage induced degradation at the device level is found to be independent of the bias during irradiation. An important exception is photonic devices (e.g., lasers, LEDs and solar cells) fabricated from compound semiconductors that may exhibit bias-dependent degradation and annealing (see section 3.3.4). Finally, it is essential for the radiation effects personnel to interact closely with the appropriate applications engineer on the design of laboratory radiation tests. In general, the radiation response of a device or subsystem is very application dependent. For example, the proton induced degradation observed in optocouplers is very dependent on the operating conditions (e.g., the LED drive current, the phototransistor collectoremitter voltage, and the load). A second example is the proton induced degradation in the CTE of a CCD which depends strongly on the temperature, signal size and pattern, readout rate, and other factors [e.g., Hopk96, and references therein]. Hence it is critical to choose a measurement technique that reflects as closely as possible the on-orbit operating conditions. In some cases (including the CTE measurement), one of the biggest challenges to the satellite designer is to identify a laboratory radiation test that provides an accurate indication of the on-orbit performance expected for a device or subsystem.

3.3 3.3.1

Case Studies Bipolar Transistors

As discussed earlier, discrete bipolar transistors have served as important test vehicles to study displacement damage effects, but this should not be construed to imply that such devices would be primarily degraded by displacement damage effects on-orbit. Quite the opposite is true. (In order to isolate displacement damage induced effects, the devices in these studies are pre-irradiated to multi-megarad levels with Co-60 to saturate the ionization damage prior to the proton, neutron and heavy ion exposures [Summ86]. Also, such studies may choose not to operate devices with low current bias so as to minimize surface currents.) Much of the early displacement damage work on bipolar transistors focussed on neutron induced degradation and provides the basis for the current understanding the proton effects [e.g., Mess86]. Neutron induced degradation of the DC gain, drive current and VCE were explored and mitigation approaches derived. Although radiation effects research has resulted in hardened discrete bipolar devices, there continue to be displacement damage concerns, particularly for analog bipolar IC applications.

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The susceptibility of linear bipolar ICs varies over a wide range because of significant variations in processing, device design and specific performance requirements [Gaut83, Gove84, Mess86, Raym87, John87, Rax97, Rax98]. In general, it has been found that devices that contain substrate or lateral pnp transistors are most sensitive to displacement damage as a result of degradation of the minority carrier lifetime in the wide base regions (i.e., low fT, or gain-bandwidth product). Circuit level design also plays a large role. For example, the use of a lateral pnp transistor as a primary input transistor operating at low current levels would be expected to increase the device vulnerability to degradation from displacement damage. A recent study by Rax et al. provides another example of a design practice that results in proton sensitivity [Rax98]. Figure 13 shows test results for an operational amplifier that fails its specification limit at an equivalent ionization level that is only 60% of that observed during gamma irradiation [Rax98]. The authors found that the output stage of the circuit is asymmetrical; it sources up to 10 mA, but is only guaranteed to sink 1 mA. It relies on the gain of a single substrate pnp transistor to sink current from an external load, making it quite susceptible to displacement damage as a direct result of circuit design.

Figure 13 The degradation in the output sink current of an OP221 operational amplifier is significantly more pronounced for proton (as compared to gamma) irradiation. The sensitivity to displacement damage is a direct result of a specific design technique. [After Rax98].

As expected, a precision, high performance linear application using a device with demanding electrical specifications will be significantly more sensitive to displacement damage induced degradation. For example, an application may require a very low input offset voltage, and/or input offset and bias current, or low noise. Recently Rax et al. found significant differences between proton and gamma ray results, which showed that displacement damage could be important, even in precision reference circuits that rely primarily on high fT npn transistors [Rax97]. As described in the last section, laboratory IV-78

test results must be carefully interpreted since the actual failure mode and sensitivity to displacements can depend on the specific environment (e.g., relative amounts of TID and displacement damage dose), and the device circuit and operating conditions. In contrast, heterojunction bipolar transistor (HBT) technology is known to be robust in a proton environment. Ohyama et al. have investigated the proton induced degradation of SiGe HBTs as a function of Ge content [Ohy96]. In addition, Roldan et al. [Rold98] have recently investigated the effects of 46 MeV proton irradiated induced trap generation and its impact on the electrical characteristics on SiGe HBTs from a state-ofthe-art IBM BICMOS commercial technology. After 1014 cm-2 protons (18.4 Mrad(Si) equivalent TID), the peak current gain (at 10 µA) was reduced by <8% and the maximum oscillation frequency and cutoff frequency showed only minor degradation. As we saw in the previous discussion of Si linear bipolar technology, the lateral pnp transistor exhibits an enhanced sensitivity to both TID and displacement damage. Recently Niu et al. investigated proton effects in gate-assisted lateral pnp (GLPNP) transistors from the advanced SiGe HBT BICMOS technology [Niu98]. They isolated the effects of proton induced bulk traps from those of surface traps and oxide charges in the GLPNP transistors that are widely used in BICMOS circuits [Niu98]. Negligible current gain degradation was observed for 46 MeV proton fluences of 1012 cm-2, and the devices were still functional at 1013 cm-2. The authors attribute the improved radiation hardness of this technology (as compared to conventional lateral pnp’s) to the much thinner oxide and gate-assisted operation that minimizes the TID response. Clearly this technology is quite insensitive to both TID and displacement damage effects. 3.3.2

Charge Transfer Devices

Silicon optoelectronic sensing arrays (visible, UV and x-ray) have been developed for a wide variety of scientific, commercial and military uses in space. They contain a matrix of up to several million photosensitive elements (or pixels) which generally operate by converting the photo-generated charge to a voltage that is multiplexed to a small number of output amplifiers. Present charge coupled devices (CCDs) are available with picoampere dark currents and charge transfer efficiencies (CTE) in excess of 0.999999 per pixel. During the development of these sensors, their susceptibility to ionizing radiation effects has been characterized and hardening solutions have been successfully implemented in many cases. The most commonly used CCD for visible and UV detection is the buried channel device which has a shallow n-type layer implanted below the surface to keep the stored signal charge away from the traps associated with the Si/SiO2 interface. Such CCDs may be hardened to TID effects either by the use of radiation hardened oxides [Carb93], or by biasing the device so that the silicon surface is inverted so that the interface traps are filled and dark current generation is suppressed [Saks80]. This can be achieved with an extra implantation to form a multiphase pinned device [Jane95], or by shuffling the charge back and forth between gates within a pixel faster than the surface states can respond (so-called dither clocking) [Burk91, Hopk92]. Bulk displacement damage effects often dominate the radiation response in stateof-the-art scientific imagers when operated in natural particle environments IV-79

[e.g., Jane91, Holl91b]. The flatband shifts and dark current increases that occur for ionizing dose levels below 10-20 krads(Si) are often not serious, and can be overcome with minor changes in voltages and operating temperature. In contrast, significant CTE losses are observed for proton exposures of less than 1 krad(Si). Nevertheless, the degree of CTE loss that is tolerable is very application-dependent, and it is still possible for a device to ultimately fail as a result of either TID or displacement damage effects at higher exposure levels. It is important to verify that flatband shifts will not take a device out of inversion prior to the expected mission dose, and also to ensure that the readout amplifier circuitry is robust. A detailed description of proton effects in CCDs may be found in a recent review article [Hopk96] and references therein. Displacement damage degrades CCD performance by decreasing the CTE, increasing the average dark current, by introducing individual pixels with very high dark currents (or “spikes”), and by increasing the noise of the output amplifier. An overview of each of these effects follows. One of the most important performance parameters for a CCD is the CTE, which is the fraction of signal charge transferred from pixel to pixel during read out. Arrays with 1024 x 1024 pixels (and larger) are routinely used today, and require very low trap densities in order to operate correctly. For example, to reduce signal loss to less than 10% for 1000 pixel-to-pixel transfers, a CTE of at least 0.9999/pixel is necessary. For a typical device with 50 µm3 pixel volumes, this corresponds to less than one radiation induced defect every ten pixels, which can easily be exceeded during a typical space mission [Hopk96]. If a signal charge is trapped by a proton induced defect, and remains trapped for more than one clock cycle, it will be lost from the signal charge packet. The trapped charge is eventually re-emitted into trailing pixels, and produces a smeared image. It is the interplay between the temperature dependent carrier emission and capture dynamics of the radiation induced traps and the device readout scheme and clocking rates that determine the CTE behavior of an irradiated CCD [Mohs74]. To understand this interplay, we consider the readout procedure for a 2dimensional CCD array. Signal charge packets are stored in the depletion regions formed underneath a biased gate during the integration period. Since the gate voltage determines the potential well capacity underneath, the signal charge can be moved down the rows in the buried channel by the appropriate sequencing of the gate voltages as indicated in figure 14a. The charge is confined laterally to a single row by an implanted channel stop. After each “parallel” transfer of the charge from one pixel to the next, the charge packet is clocked out of the serial register as depicted in figure 14b, and the whole process repeated until the imager readout is complete. Unfortunately, the time to read out the serial register is long enough for signal charge to be trapped. The signal charge can subsequently be re-emitted into a trailing pixel thereby degrading the CTE. Since the carrier emission times depend exponentially on temperature, the CTE response of a 2dimensional CCD array is a strongly temperature dependent. In contrast to the typical area array, the linear CCD with clocking speeds at 1 MHz or more is relatively immune to proton induced CTE degradation. This is because the capture times for key radiation induced defect levels, such as the E-center, are too long relative to the charge transfer rate for the traps to efficiently trap signal charge. Further details of radiation induced CTE IV-80

degradation are beyond the scope of this course, but are described in detail in many papers, including [Mohs74, Bang91, Dale93, Jane95, Hopk96].

V1

V2

V3

V1

V2

V3

V1 Direction of charge transfer oxide p-epi layer

buried n-channel

channel stops

p-substrate

Figure 14a Illustration of parallel charge transfer down a row of MOS capacitors. A 3 phase CCD is pictured, in which each pixel is composed of 3 electrodes for charge transfer. The signal charge travels in the buried channel and is restricted to a single row by implanted channel stops.

Figure 14b Schematic of a top view of a CCD array showing both the parallel and serial readouts. CCD evaluations include measurements of both the parallel and serial CTE. IV-81

Unfortunately, efforts to harden CCDs to displacement damage have not been nearly as successful as TID hardening. However, displacement damage effects can be ameliorated using several techniques. CTE loss can be somewhat reduced by substantial cooling (often to about –80 °C), to mitigate the trapping effects of the E-center (and also minimize dark current). As illustrated in figure 15, background charge can dramatically impact the CTE loss by filling the traps so that they do not interact with the signal charge packet. The magnitude of the improvement depends on the signal size, and usually (though not always [Robb92]) comes at the price of additional noise. Another CTE hardening technique employs an additional phosphorus implant to confine the signal charge to a smaller volume (referred to as a notch or minichannel) so that fewer traps are encountered as the signal charge is read out. Notches may be useful for low signal level applications and some CCD operating conditions, but the efficacy of a notch may vary considerably between manufacturers (or even lots from a single source). Further information concerning mitigation techniques may be found in [Hopk96] and references therein.

Figure 15 The charge transfer inefficiency (CTI = 1-CTE) for a CCD exposed to a proton fluence of 7.2x109 cm-2, corresponding to TID of 4 krad(Si). Both the CTI and the efficacy of a dark charge background in CTI reduction are a function of signal size. After [Hopk94b].

For most satellite programs these mitigation techniques are not sufficient, and one must resort to shielding. Recall from part A of this segment that protons are not easily shielded against. In fact, quite thick (a cm or more) of high atomic weight shielding (e.g., Ta or W alloys) may be used to minimize displacement damage to the CCD. Recall that in section 2.4, we used the Si NIEL correlation together with measured CTE damage factors to predict the on-orbit performance of a CCD. The results were displayed in figure 11 for several shield thicknesses, and confirmed the need for substantial shielding to maintain reasonable CTE performance in space. However, for heavily shielded IV-82

devices, the displacement damage caused by secondary particles produced in the shielding itself is significant, and in some cases dominant [Dale93]. (Incoming protons may interact with the atoms in the shield material causing nuclear reactions that produce secondary particles such as neutrons and protons.) The NIEL prediction methodology presented in section 2.4 is readily extended to include the displacement damage effects of secondary particles on CTE degradation. Figure 16 shows the relative contributions to the total displacement damage from the primary (incoming) protons and the secondary neutrons behind Ta shielding for a particular orbit. Of the secondary particles produced, neutrons are the greatest concern because they penetrate beyond shield depths that stop most primary protons, and yet their interaction cross-sections are significant. Secondary protons produced in nuclear reactions within the shield do not contribute significantly to the device damage since they have short ranges and are stopped in the shield itself. Note that for low atomic number shields such as Al, the displacement damage caused by secondary particles is much less significant. In addition, figure 17 shows that per unit mass, a lower atomic number shield such as Al, minimizes the amount of displacement damage to a CCD [Dale93]. Nevertheless, per unit thickness Ta clearly surpasses Al in shielding efficacy due to it greater density. Since there is generally not the space (or weight budget) to accommodate bulky Al shielding in a satellite application, higher atomic number shields are typically utilized to protect very soft devices.

Figure 16 Displacement damage dose behind a Ta shield in a trapped proton environment. Contributions from all protons and secondary neutrons are shown. (The secondary proton dose is negligible.) The secondary neutron dose dominates after about 2 cm Ta. In contrast, for low atomic number material such as Al, secondaries do not contribute significant displacement damage. After [Dale93].

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Figure 17 Comparison of displacement damage dose behind Al and Ta shields in density independent units (g/cm2). Al is the superior displacement damage shield per unit mass. However, since Ta has about six times the density of Al, Ta is always the better shield per unit thickness. After [Dale93].

Perhaps the most difficult (and important) choice facing a radiation effects engineer is which measurement technique to employ in evaluating the proton induced CTE loss. Some of the more commonly used techniques are described in [Hopk96], and references therein. One measurement technique is to plot the intensity and location of well-separated signals produced in the CCD via illumination with X-rays which produce well defined charge packets. X-ray CTE measurements can reproducibly detect very small changes in CTE, but they may considerably over-estimate the CTE degradation that would be observed on-orbit for several reasons. During many missions, CCDs will be viewing scenes that provide significant background radiation charge and larger signal sizes. As seen in figure 15, the CTE in proton irradiated CCDs can be strongly dependent on both signal size and background radiation charge. Also, sophisticated readout algorithms and signal processing software on board the satellite may decrease the impact of CTE loss for a given application. As a simple example, an application may call for the signal in neighboring pixels to averaged together, so that the charge lost to trailing pixels as a result of CTE degradation is less significant. In the case of star tracker applications, the results of X-ray CTE measurements (along with dark current results, etc.), may be input to detailed system level radiation effects models to predict the performance impact. In addition, the irradiated CCDs themselves may be placed in elaborate simulation stations complete with calibrated star fields for a detailed evaluation. However, many satellite applications involve a range of performance requirements, and less sophisticated laboratory radiation tests must be designed to provide the most reasonable worst case assessment. IV-84

Figure 18 The linear dependence of the change in dark current on particle fluence permits the definition of the dark current damage factor (given by the slopes of the lines). After [Dale89b].

The second major effect of proton induced displacement damage on CCDs is the increase in dark current as a result of carrier generation in the bulk depletion region of the pixel. (This assumes that the CCD or CID has a hardened oxide and/or else is run in inversion so that the surface dark current is suppressed.) The average dark current increase is characterized by a damage factor defined as the change in dark current per unit proton fluence. As shown in figure 18, lower energy protons are more damaging than higher energy protons as expected based on the NIEL energy dependence. (Charge injection devices (CIDs) were used in this study because they have x,y addressable arrays of pixels that are not subject to CTE degradation. These CIDs also had hard oxides.) Although the increase in the mean dark current with proton irradiation is important, the dark current nonuniformity is generally the biggest concern for CCD applications in space. NIEL is an average quantity just as stopping power (or LET) is an average quantity. For ionization effects, the departure from the average dose delivered in a uniform medium is small down to dimensions measured in hundreds of cubic nanometers. This is not the case with NIEL. For Si detector arrays (such as CIDs or CCDs), with pixels measured in the tens or hundreds of cubic microns, the displacement damage sustained by adjacent pixels can vary considerably even though the identical pixels are exposed to the same environment [Dale89b, Dale90, Mars89b, Mars90]. This nonuniformity is inherent to the statistical nature of the collision kinematics producing the displacement damage and therefore cannot be hardened against.

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4 x 10 10 /cm 2 N = 1967 N i = 1.8

1 x 10 11 /cm 2 N = 4918 N i = 4.5

2 x 10 11 /cm 2 N = 9835 N i = 9.0

Figure 19 CID dark current histograms after exposure to increasing proton fluences. As the number of primary interactions per pixel, N, increases the distribution approaches a gaussian distribution. The high energy tail is produced by very infrequent but large nuclear reaction events. (Ni is the average number of inelastic interactions per pixel.) After [Mars90 and Dale89b].

Figure 19 illustrates the spread in the dark current increases in individual pixels for a Si CID damaged incrementally by 12 MeV protons. The increase over the preirradiation dark current is determined for each pixel and the three histograms are formed from the 61,504 pixel population following each exposure. The high dark current tail is produced from single-particle inelastic nuclear reactions that deposit large amounts of displacement damage energy within the pixel, but are rare enough that relatively few pixels are affected at low fluences. Marshall et al. [Mars89b, Mars90] and Dale et al. [Dale89b, Dale90, Dale94] have studied the statistics of dark current fluctuations in detail and developed quantitative descriptions of the effect. As seen in figure 19, the analytic predictions (solid lines) of the dark current distributions [Mars90] agree well with the experimental results. At higher proton energies, where the primary recoil ranges approach the pixel dimensions, Monte Carlo techniques are required to model the dark current distributions [Dale94]. In some devices, the presence of even very small high electric field regions can result in dark current distributions that are significantly more skewed than those seen in figure 19 [Srou89, Mars89b, Mars90, Dale90, Hopk92]. Improved device design and a reduction of the applied biases can greatly minimize the occurrence of these very high dark current pixels. The high dark current pixels (so-called spikes) have been observed by several groups in a variety of devices, and also have been noted to have an erratic time dependence [e.g., Srou86, Hopk89, Mars90, Mill94, Dai96]. Hopkins and Hopkinson IV-86

showed that the dark current within a single pixel not only fluctuates in time, but also switches between well-defined levels and has the characteristics of random telegraph noise [Hopk92, Hopk93, Hopk95]. This behavior is illustrated in figure 20 for an EEV CCD irradiated by 10 MeV protons. This type of noise represents a significant calibration problem for some applications.

Figure 20 After the proton irradiation of a CCD, some pixels show time fluctuations in the dark current with the appearance of random telegraph noise. These measurements were performed on an EEV imager at 10°C. The mean time constants for the high and low states increased at lower temperatures. After [Hopk93].

Despite the extreme sensitivity of CCDs to displacement damage, they are used successfully in space for many applications. Instrument shielding, CCD cooling, careful selection of device architecture and operating conditions, and signal processing all can be used to partially mitigate the proton induced performance degradation. Other types of two-dimensional sensor arrays, such as photodiode arrays, p-channel CCDs [Spra97] and active pixel sensor arrays show promise for future use in severe space environments. 3.3.3

Photodetectors

Photodetectors are designed to collect photo-generated charge. Since particleinduced charge is also sensed, such devices are inherently radiation sensitive. Displacement damage causes an increase in the bulk dark current via carrier generation in depletion regions. Also, the degradation in minority carrier lifetime (τ) reduces the carrier diffusion length (L) in accordance with the well-known relation, L = (Dτ)1/2, where D is the diffusion constant. The result is degradation of the detector responsivity. Nevertheless, adroit selection of components and good system design permits their successful use in a proton environment. For example in data link and encoder IV-87

applications, the radiation induced increases in dark current and the reduced responsivity can be accommodated in the optical power link margin [Mars92, Mars94]. The radiation response of many types of detectors has been investigated, including pn junction photodiodes [Soda75, Wicz82, Barn86, Kord89], p-i-n diodes, phototransistors [e.g., Soda75, John96, Reed98], avalanche photodiodes (APDs) [Buch95, Sun97], multi-quantum well infrared photodetectors (MQWIPs) [Khan96], etc. Detectors that depend on the minority carrier lifetime and diffusion limited collection of carriers are much more sensitive to displacement damage than those which do not, such as a fully depleted p-i-n detector [Soda75]. For example, phototransistors are sometimes used as optical detectors (e.g., in optocouplers) since they provide internal gain. However, the transistor gain is dependent on the minority carrier lifetime and therefore sensitive to displacement damage. In contrast, metal-semiconductor-metal (MSM) photodiodes are majority carrier devices and quite robust in a proton environment. As expected, the robustness of a photo-detector also can be very application dependent. Consider an APD that can operate successfully in an analog communications link to the equivalent of 100 krad(Si) in a proton environment, whereas its performance as a photon counting device (in the Geiger mode) significantly degrades for a proton exposure below 100 rad(Si) [Sun97]. Photodiodes are available which are optimized for many applications, and the radiation response is design dependent. For example, one may harden a Si photodiode to displacement damage by minimizing the diffusion limited carrier collection (governed by the minority carrier lifetime), and maximizing collection in the depletion region using lightly doped material. Although such diodes can be quite robust in a proton environment, the lightly doped regions are subject to carrier removal and mobility degradation at relatively low fluences [Kord89]. Note also that sometimes a detector that may be relatively robust to displacement damage, like a fully depleted Si p-i-n, may be relatively more susceptible to ionization induced photo-currents which can produce bit errors in a fiber optic data link. (See Part IVA of the course for a description of bit error effects in fiber links.) Obviously, the radiation response of a particular detector to both permanent and transient proton effects must be considered for a real application. In recent years, InGaAs p-i-n detectors have proven useful in fiber optic data link applications because of their superior SEE performance as compared to a Si diode [Mars94]. Dark current damage factors were measured as a function of proton energy and were found to agree very well with the calculated InGaAs NIEL [Mars92], as shown in figure 21. The dark current damage factors (and corresponding responsivity damage factors) were combined with proton environment spectra using the formalism presented in section 2.4 to predict the on orbit performance of the detector as a function of orbit altitude and shielding. The dark current results are shown in [Mars92] for a particular orbit. The responsivity results are shown in figure 22 for a wide range of circular orbits. These results further illustrate the breadth of useful results that can be obtained using the displacement damage analysis tools described in this course.

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Figure 21 The calculated NIEL for InGaAs exhibits the same energy dependence as measured dark current damage factors. The two are scaled by the constant of 1.4x10-10 µAg/MeV, which relates device leakage to calculated displacement damage. After [Mars92].

Figure 22 Predicted proton induced responsivity changes for an InGaAs photodiode. Note the shift in the position of the minimum to higher altitudes as the shielding is reduced. This is a result of the increased low energy component of the proton spectra at higher altitudes, which is stopped in the thicker shields. After [Dale92a]. IV-89

A recent short course treated radiation effects in infrared (IR) detectors [Pick93]. Additional information can also be found in [Hopk97] and past IEEE Transactions on Nuclear Science (TNS) journals from this conference [e.g., Wate87, Hopk94a]. Very little work on proton effects appears in the open literature, but as new civilian programs (such as NASA’s Hubble Space Telescope, Next Generation Space Telescope, ESA’s High Resolution Imaging Spectrometer, and others) employ IR sensors this will change. IR sensors are generally fabricated as a hybrid of the IR detector array and a silicon readout circuit, and both elements must be considered. The IR detector elements are sensitive to both TID and, in principle, displacement damage effects, but the materials usually have high enough defect levels to mask proton induced damage to any realistic level expected on-orbit. Even if a linear Si CCD is employed for the readout circuitry, proton displacement damage effects are not generally important. The low operating temperature minimizes dark current and CTE changes, and CTE degradation is also reduced as a result of fast readout rates and relatively high signal levels. 3.3.4 Lasers and Light Emitting Diodes Photonic subsystems are increasingly widespread on satellite systems because of their performance advantages. Lasers and LEDs are employed in fiber optic communications links [Mars92, LaBe93, Mars94], optocouplers [Rax96, Reed98, Barn98], position encoders, etc. Note that laser modules employed in data links may include both lens and photodiodes, and the radiation response of the passive elements may be significant as discussed in [Mars92, Lisc93]. To date, laser diodes have proven to be relatively insensitive to proton displacement damage effects, even as technology development continues to reduce the threshold currents. Radiation does introduce nonradiative recombination centers that lower the quantum efficiency, resulting in an increased threshold current (and therefore degrades the optical power) [Barnes84]. If the threshold shift is large enough, the laser may fail to operate. Proton measurements on emerging laser technologies such as vertical cavity surface emitting lasers (VCSELs) [Paxt97] and multi-quantum well (MQW) laser diodes [Zhao98, Evan93] demonstrate very robust behavior. As seen in figure 23, MQW lasers exposed to 200 MeV proton fluences of 1013 cm-2 of (corresponding to almost 1 Mrad(Si) TID), show very minimal degradation [Zhao98]. The current threshold is found to degrade linearly with particle fluence, enabling the definition of a damage constant [Barnes 84]. LEDs are generally more sensitive to proton damage than laser diodes because they tend to have longer minority carrier lifetimes in the light emitting region, and are therefore more sensitive to the introduction of recombination centers [Barnes82, Barnes84]. LEDs may employ different lifetimes in the active volume in order to produce a device with specific qualities such as high light output or high speed, and therefore the resulting radiation sensitivities can be quite different. Although many types of LEDs are quite robust [Lisc92, Lisc93], amphoterically doped LEDs have been found to be quite sensitive to displacement damage [Barn76, Rose82, Rax96, Barr95, John98]. IV-90

Figure 23 Optical power versus laser drive current for devices shorted during irradiation. The threshold current increases linearly with proton fluence. [After Zhao97].

In fact, such LEDs have been investigated for use as displacement damage monitors on board spacecraft [Barr89, Barr90], as have SiC LEDs [Hinr98]. Recent measurements by Rax et al. have shown that the highly efficient amphoterically doped 890 nm AlGaAs LEDs used in the low speed Optek and Micropac 4N49 optocouplers suffer severe degradation for proton fluences of interest to the satellite community [Rax96]. On the other hand, they found that the shorter wavelength (700 nm) GaAlP heterojunction LED used in the HP 6N140 optocoupler is very resistant to proton damage. Photonic devices fabricated from compound semiconductors may exhibit forward bias annealing after irradiation. This phenomenon has been observed in laser diodes [Barn70, Mind76, Lisc94, Paxt97, Zhao98] and also in InP solar cells [Ando86, Yama88, Walt91]. It cannot be explained by a rise in the diode junction temperature, and this is generally considered to be due to recombination defect reactions [Lang74, Kime78]. This annealing process is thought to occur as a result of defect motion in response to locally deposited vibrational energy resulting from a non-radiative electronic transition through the defect in a depletion region. Zhao et al. have performed detailed annealing measurements on MQW lasers to characterize the post irradiation annealing of the optical power as a function of forward bias [Zhao 98]. They observed that the degradation in optical power was less at lower proton fluxes as a result of in-situ forward biased annealing during irradiation. This would indicate that tests at laboratory dose rates may over-estimate the degradation that would be observed on-orbit. However, unlike the complete recovery observed for gamma-irradiated GaAs lasers [Barn70], the lasers exposed to protons have only exhibited a partial optical power recovery [Mind76, Paxt97, IV-91

Zhao98]. Since various LEDs and laser diodes exhibit different degrees of forward biased annealing, this effect should be characterized for the devices of interest to a specific program. Significant long term annealing at room temperature has not been observed in unbiased devices [e.g., Barr95], as expected. As discussed in section 2.3.2, care is required in the choice of a damage function for the purpose of performing on-orbit predictions, since the energy dependence of the GaAs NIEL calculation at higher proton energies appears to diverge with recent measurements on GaAs LEDs [Barr95] and MQW lasers [Zhao97]. Depending on the particular proton environment and degree of device shielding, the predicted displacement damage dose can vary by factors of 2-3, (and possibly more) depending on whether the calculation is based on the energy dependence of the calculated NIEL or that of the measured damage factors. 3.3.5 Optocouplers Optocouplers are hybrid modules comprised of an LED optical source, a coupling medium, and a detector that is sometimes followed by an amplifier stage. They provide the basic function of DC isolation between circuit blocks, and find widespread application on spacecraft. The primary performance metric is the current transfer ratio (CTR), which is the ratio of the photodetector collector current to the LED forward (i.e., drive) current. There are many different optocoupler designs and applications (digital and linear), and the radiation response is highly dependent on both factors. As a result of onorbit failures of these devices in military and civilian spacecraft, laboratory investigations have been performed that confirm the important role of displacement damage in device degradation. The failure in the TOPEX/Poseidon mission was due to CTR degradation at equivalent TID levels of 10-20 krad(Si) where about 1/3 of the TID was contributed by protons [Rax96]. On-orbit errors may also occur as a result of single event transients (SETs) as discussed in Part IVA of this course. The experience to date has been that SETs are more likely to be an issue for high speed applications (> 1 MHz), whereas displacement damage effects have been most pronounced in optocouplers with a type of LED used in lower speed circuits. Investigations of the radiation response of current optocoupler technology include [Lisc93, John96, DOrd97, Reed98]. To date, optocouplers with amphoterically doped AlGaAs LEDs have displayed the highest sensitivity to proton damage, and modern devices have proved significantly more susceptible than earlier generations [Rose82]. The radiation response of optocouplers is complicated by several factors that have been considered in the recent work cited, and continue to be investigated. First, the devices are hybrid modules that may exhibit large part to part variability. A given commercial hybrid may have internal components (such as LEDs) that cannot be traced and may from several sources. Second, the observed radiation induced degradation results from a combination of TID and displacement damage mechanisms, and the relative importance depends on the optocoupler design and application. Also, the coupler may be a part of a larger hybrid such as a DC-DC converter, which includes other radiation sensitive components [Reed98]. Third, as described in the previous section, IV-92

limits in our current understanding of the energy dependence of the NIEL for III-V (and ternary) materials do not permit accurate on-orbit performance predictions, thereby necessitating significant radiation design margins. It is also worthwhile to note that little is known about possible connections between reliability issues such as lifetime and temperature and radiation-induced degradation. Currently, these effects are assumed to be independent. However, we do know that some optocouplers have exhibited a significant CTR temperature dependence, which is an important consideration since operation well above room temperature is not uncommon on spacecraft [Rax96]. The importance of proton testing to evaluate the on-orbit response of an optocoupler is clearly demonstrated in figure 24 which shows greatly decreased CTR for proton as compared to Co-60 irradiation. Rax et al. disassembled two types of optocouplers to investigate the modes of CTR degradation [Rax96]. They found that the CTR performance was primarily determined by the response of the LED to displacement damage, and that the amphoterically doped AlGaAs LED was significantly more susceptible than the GaAlP LED. As is often the case, a higher performance device fabricated with more pristine material is also more radiation sensitive (e.g., CCDs, solar cells, etc.), and an engineering trade of initial performance versus the radiation sensitivity of the device on-orbit must be performed. Displacement damage also affected the phototransistors in each optocoupler studied by Rax et al., with the reduction in photoresponse being a more significant than gain degradation. Optocouplers that use a photodiode (as opposed to a phototransistor) have been observed to have the best performance to date [Reed98].

1 0.9

Normilized CTR

0.8

Texas Instruments 4N49 If=1.1mA Vce=5.0V

0.7 0.6 0.5 0.4 0.3 0.2

Co-60 195 MeV Protons

0.1 0 0

20

40 60 80 Total Ionizing Dose (krad(Si))

100

120

Figure 24 Comparison of proton and gamma irradiations clearly demonstrates the importance of displacement damage in CTR degradation. Despite the large part to part variability in the preirradiation CTR values, similar radiation degradation is observed when the post-irradiation CTRs were normalized to their initial values [Rax98]. After [Reed98]. IV-93

Application specific laboratory testing is necessary in order to assess on-orbit CTR performance. To begin, we note there is a distinct difference in the performance and electrical characteristics of general purpose optocouplers, such as those evaluated in [Lisc93, Rax96, Reed98] and those used in linear applications, e.g., DC-DC converters. General purpose devices exhibit a wide range of CTR values guaranteed to be above a set minimum, whereas those in linear applications have specified CTRs within a narrow range. These differences need to be considered in designing a laboratory evaluation to determine the suitability of such devices for use in space [John99]. In all cases, a proton induced radiation response of an optocoupler will depend on the LED drive current since it impacts the operating point of the phototransistor and therefore, its radiation response. The importance of application specific testing has been demonstrated by Reed et al. in a study that measured the impact of LED drive current, circuit loading, and the phototransistor collector-emitter voltage (VCE) on the proton induced CTR degradation. The experimental set-up is illustrated in figure 25. A radiation induced degradation in the LED light output results in a reduction in the collector current of the phototransistor. If the transistor is in saturation then the change in collector current will be minimal and the CTR will be essentially the same. However, if the same device is operating in the active region, the CTR will be quite sensitive to changes in LED output power. Whether or not the transistor operates in saturation is dependent on the LED drive current and VCE, (which itself depends on the output load). Figure 26 illustrates the load dependence of the CTR radiation response for an optocoupler operated with a forward current of 4 mA. It also demonstrates that the common practice of testing at a fixed VCE of 5 V with no circuit loading significantly over-predicts the CTR degradation, although such data can be used for worst case estimates. Data such as these suggest the mitigation of CTR degradation by operation of the optocoupler at the highest drive current possible while minimizing VCE to obtain the desired IC for the application [Reed98]. In this case the optocoupler is driven into saturation. However, the trade-off between reliability concerns for LED operation in this mode must be considered. Also, the forward current selected may impact the rate of defect annealing observed in some LEDs, as discussed in the previous section.

VI

Vo RI

RL

DUT

VCE

Figure 25 CTR measurement setup showing the input voltage and resistance (VI and RI), and output voltage (VO). Two independent power supplies are used to sweep VI and VO. Changes in VI alter the LED drive current. VCE is the difference between VO and the measured voltage drop across the load resistance (RL), which can be varied. After [Reed98]. IV-94

3.5

CTR/CTRo or Vce/Vceo

3.0 2.5

Vce/Vceo load=1 kohm Vce/Vceo load=2.7 ohm CTR/CTRo load=1 kohm CTR/CTRo Load=2.7 ohm CTR/CTRo no load Vce=5V

2.0 1.5 1.0 0.5 0.0 0.0E+00

2.0E+10

4.0E+10

6.0E+10

8.0E+10

1.0E+11

1.2E+11

2

Fluence (p/cm ) Figure 26 Plot of the normalized CTR (solid lines) and normalized VCE (dashed lines) for an optocoupler operated with a forward current of 4 mA and irradiated with 195 MeV protons. In the case of the 2.7 Ω load (with VCE remaining at 0.3 V), the degradation is almost twice that observed for the 1 kΩ load where the degradation is mitigated by an increase in VCE. (Vo was set so that the initial VCE = 0.3 V for both loads.) After [Reed98].

To the extent that laboratory testing has shown the CTR response to be dominated by displacement damage to the internal LED, the analysis tools presented in sections 2.3 and 2.4 can be used together with application specific CTR measurements on protonirradiated devices to perform on-orbit predictions. As always, it is important to select the optimal proton test energy (or energies) based on analysis of the shielded proton spectrum relevant to a specific application. The relative importance of displacement damage dose and TID may be assessed by comparing proton and gamma measurements as indicated in figure 24. This figure also shows that the CTR response is very nonlinear with proton fluence (or TID or displacement damage dose), so that a damage factor cannot be defined. Nevertheless, the CTR degradation can be plotted versus the equivalent mission fluence or displacement damage dose to assess the end of life performance. (Note that, to first order, the proton testing of CTR degradation can also be considered to incorporate the performance loss from TID effects.) As noted in the previous section, the NIEL function for LED materials does not accurately reflect the device response so accurate predictions are not presently possible. In the absence of CTR measurements as a function of proton energy, we have three choices for a function to describe the energy dependence: (1) a calculated NIEL curve, (2) an experimental displacement damage curve from the literature (e.g., the LED data from [Barr95]), and (3) a piecewise “manufactured” worse case damage function. It is hoped that further research to permit a better understanding of the radiation performance of optocouplers and the applicability of the NIEL energy dependence will result in more realistic worst IV-95

case analyses to facilitate the device selection process. However, there will still remain a wide variation between optocoupler manufacturers concerning issues such as component procurement and coupler design. These issues need to be reflected in the sample size chosen for a radiation test, and significant de-ratings may be necessary to reflect the large part-to-part variations observed for some of these hybrid devices. 3.3.6

Solar Cells

Solar cells are basically very specialized large area diodes, some of which have complex multi-junction designs to optimize their conversion efficiency. Light strikes the solar cell and creates electron-hole pairs that generate electrical power only if collected at the cell electrodes. In order to have high collection efficiency, especially at the red end of the spectrum, long diffusion lengths are required in the lightly doped portion of the cells intended for light collection. As expected for a minority carrier device, the degradation in power output is a result of a radiation induced reduction in the minority carrier lifetime. Once again, device radiation sensitivity is greater for materials with longer initial lifetimes, as seen in figure 27. For example, minority carrier lifetimes in GaAs are typically much shorter (tens of nanoseconds) as compared to the much longer Si lifetimes of tens to even hundreds of microseconds. Key electrical parameters include not only the power output, but also the open circuit voltage, and short circuit current. The interested reader may find a wealth of information in the JPL solar cell handbooks [Tada82, Ansp89, Ansp96], and the Photovoltaic Specialists Conference proceedings. Crystalline Si and GaAs/Ge solar cells are most commonly flown today, but multi-junction GaAs cells, InP and amorphous Si cells are being investigated for future use in space. The drive to fly spacecraft in ever more harsh environments (including the more intense part of the proton belts) has spurred interest in more radiation hardened cells. The presence of multiple junctions provides additional design flexibility to achieve increased hardness, as described in [Marv99]. Figure 27 compares the maximum power output degradation as a function of displacement damage dose for several of the most common solar cell materials. The figure summarizes data from several sources [Srou98, Wojt96, Mess97, Hoff97, Nogu90], and clearly shows the nonlinear degradation. Note that InP has the potential for increased survivability as a result of injection annealing [Keav93]. However, as noted in the case of GaAs LEDs and laser diodes, the degree of annealing characteristic of a particular device needs to be carefully confirmed in a well designed ground test of the flight lot. Note that the amorphous Si cell has been shown by Srour et al. to degrade primarily by TID effects, which is not surprising due to the disordered nature of the material [Srou98]. At very high fluences, minority carrier devices begin to show the effects of carrier removal, and solar cells are no exception. The rapid degradation of solar cell output power at high displacement damage doses illustrated in figure 27 and is due to carrier removal. In fact, failure of a Si solar cell flown in an elliptical orbit through the Van Allen belts from carrier removal effects has been observed [Yama96, Amek97]. Recent work by Messenger et al. has investigated the response of InP solar cells to high proton fluences (including carrier removal effects) [Mess97a, Mess98]. IV-96

Figure 27 Maximum power output degradation versus displacement damage dose for a variety of solar cells. The amorphous Si curve includes the displacement component only, and does not include ionization induced degradation. After [Srou98].

Since solar cell performance degrades as a result of displacement damage the analysis tools presented in sections 2.3 and 2.4 can be applied to perform on-orbit predictions. For example, these techniques have been used to predict the on-orbit power degradation of GaAs solar cells due to a solar proton event [Mess97b]. Since these devices are flown in space with very thin shielding (e.g., coverglasses as thin as 3 mil), the lower energy portion of the proton spectrum contributes the bulk of the displacement damage. Note that the deviations of the damage factors from the GaAs NIEL dependence (see figure 9) are less significant in performing a solar cell analysis because the measurements are fit to the NIEL calculation over a much smaller energy range. For the case of a 3 mil SiO2 coverglass, less than 10% of the total displacement damage dose calculated for the 1989 solar flare event is contributed by protons with energies greater than 12 MeV [Mess97b]. Clearly, proton test energies should be chosen accordingly, with care taken to ensure the NIEL is not varying significantly as the particle transverses the device under test (see section 3.2).

IV-97

Figure 28 Although the maximum power output correlates well with NIEL over the proton energy range shown, the electron fit was obtained by defining the equivalent 1 MeV electron displacement damage dose as the product of the particle fluence with NIEL raised to the 1.7 power. After [Walt99].

The light shielding employed in solar cells applications has another important consequence. Displacement damage from electrons must be considered in addition to the proton contribution. It has been long recognized that a linear relationship between electron damage factors and NIEL is not always observed in Si [Cart66]. In the case of GaAs solar cells, Summers et al. [Summ93] presented short circuit current data showing a “nearly” linear relationship (on a log-log plot) between both the electron and proton data and the calculated GaAs NIEL using data from [Ansp92]. (Many of the correlations of calculated NIEL with device performance discussed in section 2.3 were initially presented on log-log plots covering many orders of magnitude, which makes it difficult to assess the degree of linearity where factors of 2-3 are significant.) More recently, Walters et al. [Walt99] have performed a detailed review of the above-mentioned GaAs data set, and now recommend separate fits to the NIEL in order to describe proton and electron degradation. The fits are shown in figure 28, and we see the proton data correlate well with NIEL over the energy range from 0.2 to 9.5 MeV. For electrons, they find that the best agreement of the data over the largest energy range is obtained when the calculated NIEL was raised to the 1.7 power. As a result, they define the equivalent 1 MeV electron displacement damage dose as the product of the particle fluence with NIEL raised to the 1.7 power. This example illustrates one method of modifying the NIEL correlation in order to perform an on-orbit prediction for a quantity that does not exhibit the energy dependence predicted by NIEL. Obviously, other fitting approaches can also be employed to describe the measured device degradation after irradiation, and all require measurements of the device degradation for a set of particle energies. IV-98

4.0 SUMMARY Section IVB begins by examining the process by which incident protons displace atoms in semiconductor material and ultimately produce electrically active defect levels. The impact of displacement damage induced defects on the operation of semiconductor devices is described. In general, devices whose primary characteristics depend on the minority carrier lifetime will be most sensitive to displacement damage. The concept of the non-ionizing energy loss rate (NIEL) is introduced, and it is shown that in many cases device degradation as a function of proton energy is approximately linearly dependent on the NIEL for a variety of materials. This means that the NIEL is the displacement damage equivalent of the LET for total ionizing dose effects. We present displacement damage tools (based on NIEL or experimental damage functions) that allow on-orbit prediction of device degradation based on a small number of laboratory measurements. Limitations in the application of NIEL are also discussed. We find that experimental data for Si and GaAs devices show that NIEL overpredicts device degradation at higher proton energies. Finally, we presented a series of case studies that illustrate the displacement damage concepts and analysis tools covered in the first part of section IVB. Laboratory radiation test issues specific to the proper evaluation of devices for displacement damage effects are treated. The response of several categories of devices to protons, including bipolar transistors, charge transfer devices, photo-detectors, solar cells, lasers and LEDs are described. Each case study brings to light a new aspect of displacement damage analysis. Si linear bipolar technology exhibits a wide range of displacement damage sensitivity depending on the process, IC design and application. For both Si and SiGe devices, the lateral pnp transistor exhibits an enhanced sensitivity to both TID and displacement damage. The response of CCDs to protons is unique for several reasons. The CTE degradation is determined by the interplay between the carrier emission and capture dynamics of the radiation induced traps and the device readout scheme and clocking rates. Although the increase in the mean dark current with proton irradiation is important, the dark current nonuniformity is generally the biggest concern for CCD applications in space. Dark current within a single pixel are also found to fluctuate in time in a manner characteristic of random telegraph noise. Finally, even when available mitigation techniques are employed, CCDs remain quite sensitive to proton induced damage so that thick, high atomic number shielding is frequently employed on-orbit. We found that predictions of device performance in space must consider the displacement damage produced both by incident protons and secondary neutrons produced in the thick shielding. At the other extreme, solar cells are flown with minimal shielding and therefore lower energy protons are most important and electron damage must also be considered. Photo-detectors are inherently sensitive to radiation but such devices also exhibit a wide range of proton sensitivity dependent on their design and application. Although lasers are generally quite hard to displacement damage, certain types of LEDs exhibit significant loss in output power after low levels of proton exposure. Optocouplers also have a wide range of sensitivities to protons dependent on their design, type of LED used and application. As hybrid devices, they also present significant hardness assurance challenges. In all cases, the device response to proton irradiation is found to be very application dependent, which must be reflected in the design of laboratory radiation tests. IV-99

5.0 ACKNOWLEDGMENTS The authors appreciate the consistent support and friendship of colleagues at NASA-GSFC, NRL and elsewhere. Over the years, we have benefited tremendously from technical interchange with Ken LaBel, Robert Reed and Janet Barth. We have enjoyed working with Ed Burke and Al Wolicki on displacement damage issues. They have been an inspiration, and also patient teachers. Martha O’Bryan was indispensable on several fronts including graphics support.

6.0 REFERENCES (All references are unclassified.) [Alur91]

M. Alurralde, M. Victoria, A. Caro, and D. Gavillet, “Nuclear and Damage Effects in Si Produced by Irradiations with Medium Energy Protons,” IEEE Trans. Nucl. Sci., Vol. 38, No. 6, pp. 1210-1215, 1991.

[Amek97] H. Amekura, N. Kishimoto, and K. Kono, “Radiation-Induced Two-Step Degradation of Si Photoconductors and Space Solar Cells,” RADECS97, IEEE Doc. No. 97TH8294, pp. 376-381, 1997. [Ando86]

K. Ando, M. Yamaguchi, and C. Uemura, “Non-Radiative-Recombination-Enhanced Defect-Structure Transformation in Low Temperature Gamma-Ray-Irradiated InP,” Phys. Rev. B. Vol. 34, p. 3041, 1986.

[Ansp92]

B.E. Anspaugh, “Proton and Electron Damage Coefficients for GaAs/Ge Solar Cells,” Proceedings of the 22nd IEEE Photovoltaic Specialists Conference, pp. 15931598, 1992.

[Ansp89]

B.E. Anspaugh, Solar Cell Radiation Handbook, JPL Publication 82-69, Addendum 1, 1989.

[Ansp96]

B.E. Anspaugh, GaAs Solar Cell Handbook, JPL Publication 96-9, 1996.

[Arim82]

I. Arimura and C.E. Barnes, “Proton Damage in Laser Diodes and Light-Emitting Diodes (LEDs),” Proc. SPIE, Vol. 328, pp. 83-87, 1982.

[Aver83]

R.S. Averbach, R. Benedek, K.L. Merkle, “Ion-Irradiation Studies of the Damage Function of Copper and Silver,” Phys. Rev. B18, pp. 4156-4171, 1978.

[Aver88]

R.S. Averbach and T. Diaz de la Rubia, “Dynamics and Structure of Energetic Displacement Cascades,” Nucl. Instr. Meth. in Phys. Res., Vol. B33, pp. 693-699, 1988.

[Bang91]

E.K. Banghart, J.P. Lavine, E.A. Trabka, E.T. Nelson, and B.C. Burkey, “A Model for Charge Transfer in Buried-Channel-Charge-Coupled Devices at Low Temperatures,” IEEE Trans. Elect. Dev., Vol. 38, No. 5, pp. 1162-1173, 1991. IV-100

(All references are unclassified.) [Barn70]

C.E. Barnes, “Effects of Co60 Gamma Irradiation on Epitaxial GaAs Laser Diodes,” Phys. Rev. B, Vol. 1, No. 12, 1970.

[Barn84]

C.E. Barnes and J.J. Wiczer, “Radiation Effects in Optoelectronic Devices,” Sandia Report SAND-0771, Sandia National Laboratories, May 1984.

[Barn86]

C.E. Barnes, “The Effects of Radiation on Optoelectronic Devices,” Proc. SPIE, Vol. 721, pp. 18-25, 1986.

[Barr89]

A.L. Barry, R. Wojcik, and A.L. MacDiarmid, “Response of GaAs Displacement Damage Monitors to Protons, Electrons, and Gamma Radiation,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 2400-2404, 1989.

[Barr90]

A.L. Barry, R. Maxseiner, R. Wojcik, M.A. Briere, and D. Braunig, “An Improved Displacement Damage Monitor,” IEEE Trans. Nucl. Sci., Vol. 37, No. 6, pp. 17261731, 1990.

[Barr95]

A.L. Barry, A.J. Houdayer, P.F. Hinrichsen, W.G. Letourneau, and J. Vincent, “The Energy Dependence of Lifetime Damage Constants in GaAs LEDs for 1-500 MeV Protons,” IEEE Trans. Nucl. Sci., Vol. 42, No. 6, pp. 2104-2107, 1995.

[Bert68]

M. Bertolotti, “Radiation Effects in Semiconductors,” Proceedings of the Santa Fe Conference, edited by F.L. Vook, Plenum Press, NY, p. 311, 1968.

[Burk86]

E.A. Burke, “Energy Dependence of Proton-Induced Displacement Damage in Silicon,” IEEE Trans. Nucl. Sci., Vol. 33, No. 6, pp. 1276-1281, 1986.

[Burk91]

B. Burke and S.A. Gajar, “Dynamic Suppression of Interface-State Dark Current in Buried Channel CCD Imagers,” IEEE Elect. Dev. Lett., Vol. 38, No. 2, pp. 285-290, 1991.

[Buch95]

F. Buchinger, A. Kyle, J.K.P. Lee, C. Webb, and H. Dautet, “Identification of Individual Bistable Defects in Avalanche Photodiodes,” Appl. Phys. Lett., Vol. 66, No. 18, pp. 2367-2369, 1995.

[Carb93]

J. Carbone, J. Zamowski, F. Arnold, and J. Hutton, “New Low-Noise Random Access, Radiation Resistant and Large Format Charge Injection Device (CID) Imagers,” Proc. SPIE, Vol. 1900, pp. 170-180, 1994.

[Cart66]

J.R. Carter, “Effect of Electron Energy on Defect Introduction in Silicon,” J. Phys. Chem. Solids, Vol. 27, pp. 913-918, 1966.

[Dai96]

M. Dai, F. Buchinger, J.K.P. Lee, and H. Dautet, “Time Resolved Annealing Studies of Single Neutron Irradiated Avalanche Photodiodes,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp. 2595-2600, 1996.

[Dale88]

C.J. Dale, P.W. Marshall, E.A. Burke, G.P. Summers, and E.A. Wolicki, “High Energy Electron Induced Displacement Damage in Silicon,” IEEE Trans. Nucl. Sci., NS-35, pp. 1208-1214, 1988. IV-101

(All references are unclassified.) [Dale89a] C.J. Dale, P.W. Marshall, G.P. Summers, E.A. Wolicki, and E.A. Burke, “Displacement Damage Equivalent to Dose in Silicon Devices,” Appl. Phys. Lett., Vol. 54, No. 5, p. 451, 1988. [Dale89b] C.J. Dale, P.W. Marshall, E.A. Burke, G.P. Summers, and G.E. Bender, “The Generation Lifetime Damage Constant and its Variance,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 1872-1881, 1989. [Dale90]

C.J. Dale, P.W. Marshall, and E.A. Burke, “Particle-Induced Spatial Dark Current Fluctuations in Focal Plane Arrays,” IEEE Trans. Nucl. Sci., Vol. 37, No. 6, pp. 1784-1793, 1990.

[Dale91]

C.J. Dale and P.W. Marshall, “Displacement Damage in Silicon Imagers for Space Applications,” Proc. SPIE, Vol. 1447, pp. 70-86, 1991.

[Dale92a] C.J. Dale and P.W. Marshall, “Radiation Response of 1300 nm Optoelectronic Components in a Natural Space Radiation Environment,” Proc. SPIE, Vol. 1791, pp. 224-232, 1992. [Dale92b] C.J. Dale, P.W. Marshall, B. Cummings, L. Shamey, R. Howard, and A. Delamere, “Spacecraft Displacement Damage Dose Calculations for Shielded CCDs,” Proc. SPIE, Vol. 1656, pp. 476-487, 1992. [Dale93]

C.J. Dale, P.W Marshall, B. Cummings, L. Shamey and A. Holland, “Displacement Damage Effects in Mixed Particle Environments for Shielded Spacecraft CCDs”, IEEE Trans. Nucl. Sci., Vol. 40, No. 6, pp. 1628-1637, 1993.

[Dale94]

C.J. Dale, L. Chen, P.J. McNulty, P.W. Marshall, and E.A Burke, “A Comparison of Monte Carlo and Analytic Treatments of Displacement Damage in Microvolumes,” IEEE Trans. Nucl. Sci., Vol. 41, No. 6, pp. 1974-1983, 1994.

[DOrd97] M.D. D’Ordine, “Proton Displacement Damage in Optoelectronic Devices,” 1997 IEEE Radiation Effects Workshop Record, IEEE No. 97TH8293, pp. 122-124, 1997. [Eise92]

F.H. Eisen, K. Bachem, E. Klausman, K. Koehler, and R. Haddad, “Ion Irradiation Damage in n-Type GaAs in Comparison with its Electron Irradiation Damage,” J. Appl. Phys., Vol. 72, No. 12, pp. 5593-5601, 1992.

[Gaut83]

M.K. Gauthier and D.K. Nichols, “A Comparison of Radiation Damage in Linear ICs from Cobalt-60 Gamma Rays and 2.2 MeV Electrons,” IEEE Trans. Nucl. Sci., No. 6, pp. 4192-4196, 1983.

[Gove84]

J.E. Gover and J.R. Srour, “Basic Radiation Effects in Nuclear Power Electronics Industry,” Sandia Report SAND-85-0776, Sandia National Laboratories, May 1985.

[Grif91]

P.J. Griffin, J.G. Kelly, T.F. Luera, A.L. Barry, and M.S. Lazo, “Neutron Damage Equivalence in GaAs,” IEEE Trans. Nucl. Sci., Vol. 38, No. 6, pp. 1216-1224, 1991.

IV-102

(All references are unclassified.) [Hash94]

G.L. Hash, J.R. Schwank, M.R. Shaneyfelt, C.E. Sandoval, M.P. Connors, T.J. Sheridan, F.W. Sexton, E.M. Slayton, J.A. Heise, and C.C. Foster, “Proton Irradiation Effects on Advanced Digital and Microwave III-V Components,” IEEE Trans. Nucl. Sci., Vol. 41, No. 6, pp. 2259-2266, 1994.

[Hein83]

H.L. Heinisch, “Defect Production in Simulated Cascades: Cascade Quenching and Short Term Annealing,” J. Nucl. Mater., Vol. 117, pp. 46-54, 1983.

[Hinr98]

P.F. Hinrichsen, A.J. Houdayer, A.L. Barry, and J. Vincent, “Proton Induced Damage in SiC Light Emitting Diodes,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 28082812, 1998.

[Hoff97]

R.W. Hoffman, Jr., N.S. Fatemi, P.P. Jenkins, V.G. Weizer, M.A. Stan, S.A. Ringel, D.A. Scheiman, D.M. Wilt, D.J. Brinker, R.J. Walters, and S.R. Messenger, “Improved Performance of p/n InP Solar Cells,” Record of 26th IEEE Photovoltaic Specialists Conference, IEEE Catalog No. 97CB36026, pp. 815-818, 1997.

[Holl91a]

A.D. Holland, “Annealing of Proton-Induced Displacement Damage in CCDs for Space Use,” Inst. Phys. Conf. Ser. 121, pp. 33-40, Sept. 1991.

[Holl91b]

A. Holland, A. Holmes-Seidle, B. Johlander, and L. Adams, “Techniques for Minimizing Space Proton Damage in Scientific Charge Coupled Devices,” Trans. Nucl. Sci., Vol. 38, No. 6, pp. 1663-1670, 1991.

[Holm93] A. Holmes-Seidle and L. Adams, A Handbook of Radiation Effects, Oxford University Press, Oxford, 1993. [Hopk89]

G.R. Hopkinson and Ch. Chlebek, “Proton Damage Effects in an EEV CCD Imager,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 1865-1871, 1989.

[Hopk92]

G.R. Hopkinson, “Cobalt-60 and Proton Radiation Effects on Large Format, 2-D, CCD Arrays for an Earth Imaging Application,” IEEE Trans. Nucl. Sci., Vol. 39, No. 6, pp. 2018-2025, 1992.

[Hopk93]

I.H. Hopkins and G.R. Hopkinson, “Random Telegraph Signals from ProtonIrradiated CCDs,” IEEE Trans. Nucl. Sci., Vol. 40, No. 6, pp. 1567-1574, 1993.

[Hopk94a] G.R. Hopkinson, C.J. Baddiley, D.R.P. Guy, and J.E. Parsons, “Total Dose and Proton Testing of a Commercial HgCdTe Array,” IEEE Trans. Nucl. Sci., Vol. 41, No. 6, pp. 1966-1973, 1994. [Hopk94b] I.H. Hopkins, G.R. Hopkinson, and B. Johlander, “Proton-Induced Charge Transfer Degradation in CCDs for Near-Room Temperature Applications,” IEEE Trans. Nucl. Sci., Vol. 41, No. 6, pp. 1984-1990, 1994. [Hopk95]

I.H. Hopkins and G.R. Hopkinson, “Further Measurements of Random Telegraph Signals in Proton-Irradiated CCDs,” IEEE Trans. Nucl. Sci., Vol. 42, No. 6, pp. 2074-2081, 1995.

IV-103

(All references are unclassified.) [Hopk96]

G.R. Hopkinson, C.J. Dale, and P.W. Marshall, “Proton Effects in Charge-Coupled Devices,” IEEE Trans. Nucl. Sci., Vol. 43, No. 2, pp. 614-627, 1996.

[Hopk97]

G.R. Hopkinson, “Radiation Effects in Optoelectronic Components,” 4th European Conference on Radiations and their Effects on Components and Systems (RADECS 97) Journal of Technical Events, pp. III 65-101, Cannes, France, 1977.

[Jane95]

J. Janesick, T. Elliott, R. Winzenread, J. Pinter, and R. Dyck, “Sandbox CCDs,” Proc. SPIE, Vol. 2415, pp. 2-42, 1995.

[John87]

A.H. Johnston and R.E. Plaag, “Models for Total Dose Degradation of Linear Integrated Circuits,” IEEE Trans. Nucl. Sci., Vol. 34, No. 6, pp. 1474-1480, 1987. {Note that this paper also treats displacement damage.}

[John99]

A. H. Johnston and B.G. Rax, "Proton Damage in Linear and Digital Optocouplers," to be presented at RADECS99 and published in the proceedings.

[Keav93]

C.J. Keavney, R.J. Walters and P.J. Drevinsky, “Optimizing the Radiation Resistance of InP Solar Cells: Effect of Dopant Density and Cell Thickness,” J. Appl. Phys., Vol. 73, pp. 60-70, 1993.

[Khan96]

S.M. Khanna, H.C. Liu, P.H. Wilson, L. Li, and M. Buchanan, “High Energy Proton and Alpha Radiation Effects on GaAs/AlGaAs Quantum Well Infrared Photodetectors,” IEEE Trans. Nucl. Sci., Vol. 43, No. 6, pp. 3012-3018, 1996.

[Kim79]

L.C. Kimerling, P. Blood, and W.M. Gibson, “Defect States in Proton-Bombarded Silicon at T<300K,” International Conf. on Defects and Radiation Effects in Semiconductors, Inst. Phys. Conf. Ser. 46, pp. 273-280, 1979.

[Kord89]

R. Korde, A. Ojha, R. Braasch, and T.C. English, “The Effect of Neutron Irradiation on Silicon Photodiodes,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 2169-2175, 1989.

[LaBe93]

K. A. LaBel, P. Marshall, C. Dale, C. M. Crabtree, E.G. Stassinopoulos, J. T. Miller and M. M. Gates, “SEDS MIL-STD-1773 Fiber Optic Data Bus: Proton Irradiation Test Results and Spaceflight SEU Data,” IEEE Trans. Nucl. Sci., Vol. 40, No. 6, pp. 1638-1644, 1993.

[LaBe98]

K.A. LaBel, A.H. Johnston, J.L. Barth, R.A. Reed, and C.E. Barnes, “Emerging Radiation Hardness Assurance (RHA) Issues: A NASA Approach for Spaceflight Programs,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2727-2736, 1998.

[Lang74]

D.V. Lang and L.C. Kimerling, “Observations of Recombination-Enhanced Defect Reactions in Semiconductor,” Phys. Rev. Lett., Vol. 33, No. 8, pp. 489-492, 1974.

[Lars78]

B.C. Larsen, R.T. Young, and J. Narayan, “Defect Annealing Studies in Neutron Transmutation Doped Si,” Neutron Transmutation Doping in Semiconductors, edited by J.M. Meese, Plenum Press, NY, pp. 781-290, 1978.

IV-104

(All references are unclassified.) [Lisc92]

H. Lischka, H. Henschel, W. Lennartz, and H.U. Schmidt, “Radiation Sensitivity of Light Emitting Diodes (LED), Laser Diodes (LD) and Photodiodes (PD),” IEEE Trans. Nucl. Sci., Vol. 39, No. 3, pp. 423-427, 1992.

[Lisc93]

H. Lischka, H. Henschel, O. Kohn, W. Lennartz, and H.U. Schmidt, “Radiation Effects in Light Emitting Diodes, Laser Diodes, Photodiodes, and Optocouplers,” RADECS93, IEEE Doc. No. 93TH0616-3, pp. 226-231, 1993.

[Lisc94]

H. Lischka, H. Henschel, O. Kohn, W. Lennartz, and H.U. Schmidt, “Radiation Effects in Optoelectronic Devices,” Proc. SPIE, Vol. 2425, pp. 43-52, 1994.

[Lind63]

J. Lindhard, V. Nielsen, M. Scharff, and P. Thomsen, “Integral Equations Governing Radiation Effects (Notes on Atomic Collisions, III),” Mat. Fys. Medd. Dan. Vid. Selsk., Vol. 33, No. 10, p.1, 1963.

[Luer87]

T.F. Luera, J.G. Kelly, H.J. Stein, M.S. Lazo, C.E. Lee, and L.R. Dawson, “Neutron Damage Equivalence for Silicon, Silicon Dioxide, and Gallium Arsenide,” IEEE Trans. Nucl. Sci., Vol. 34, No. 6, pp. 1557-1563, 1987.

[Mars89a] P.W. Marshall, C.J. Dale, G.P. Summers, E.A. Burke, and E.A. Wolicki, “Proton, Neutron and Electron Induced Displacement Damage in Germanium,” IEEE Trans. Nucl. Sci., Vol. 36, pp. 1882-1888, 1989. [Mars89b] P. W. Marshall, C. J. Dale, E. A. Burke, G. P. Summers, and G.E. Bender, “Displacement Damage Extremes in Silicon Depletion Regions,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 1831-1839, 1989. [Mars90]

P.W. Marshall, C.J. Dale, E.A. Burke, “Proton-Induced Displacement Damage Distributions and Extremes in Silicon Microvolumes,” IEEE Trans. Nucl. Sci., Vol. 37, No. 6, pp. 1776-1783, 1990.

[Mars92]

P.W. Marshall, C.J. Dale, and E.A. Burke, “Space Radiation Effects on Optoelectronic Materials and Components for a 1300 nm Fiber Optic Data Bus,” IEEE Trans. Nucl. Sci., Vol. 39, No. 6, pp. 1982-1989, 1992.

[Mars94]

P.W. Marshall, C.J. Dale, K.A. LaBel, and E.J. Friebele, “A Review of Space Radiation Effects for Fiber Optic Data Links,” SPIE Critical Review CR-14, Fiber Optics Reliability and Testing, 1994.

[Marv99]

D.C. Marvin, J.C. Nocerino, and W.R. James, “Evaluation of Multijunction Solar Cell Performance in Radiation Environments,” 1999 GOMAC Proc., pp. 430-433, 1999.

[McNu81] P.J. McNulty, G.E. Farrell, and W.P. Tucker, “Proton Induced Nuclear Reactions in Silicon,” IEEE Trans. Nucl. Sci., Vol. 28, No. 6, pp. 4007-4012, 1981. [McNu94] P.J. McNulty, W. G. Abdel-Kader, and G. E. Farrell, “Proton Induced Spallation Reactions,” Radiat. Physi. Chem., Vol. 43 (1/2), pp. 139-149, 1994.

IV-105

(All references are unclassified.) [Mess86]

G.C. Messenger and M.S. Ash, The Effect of Radiation on Electronic Systems, Van Nostrand Reinhold Company, NY, 1986, Chapter 5.

[Mess97a] S.R. Messenger, M.A. Zapsos, R.J. Walters, H.J. Cotal, S.J. Wojtczuk, H.B. Serreze, and G.P. Summers, “Spectral Response of InP/Si Solar Cells Irradiated to High Proton Fluences,” Record of 26th IEEE Photovoltaic Specialists Conference, IEEE Catalog No. 97CB36026, pp. 815-818, 1997. [Mess97b] S.R. Messenger, M.A. Xapsos, E.A. Burke, R.J. Walters, and G.P. Summers, “Proton Displacement Damage and Ionizing Dose for Shielded Devices in Space,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp. 2169-2173, 1997. [Mess98]

S.R. Messenger, R.J. Walters, M.A. Xapsos, G.P. Summers, and E.A. Burke, “Carrier Removal in p-Type InP,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2857-2860, 1998.

[Mill94]

T.L. Miller, D.A. Thompson, M.B. Elzinga, T.-H. Lee, B.C. Passenheim, and R.E. Leadon, “Experimental Evaluation of High Speed CCD Imager Radiation Effects Using Co60 and Proton Irradiation,” 1993 IEEE Radiation Effects Data Workshop, pp. 56-63, 1994.

[Mind76]

H.T. Minden, “Effects of Proton Bombardment on the Properties of GaAs Laser Diodes,” J. Appl. Phys., Vol. 47, No. 3, pp. 1090-1094, 1976.

[Mohs74] A.M. Mohsen and M.F. Tompsett, “The Effects of Bulk Traps on the Performance of Bulk Channel Charge-Coupled Devices,” IEEE Trans. Elect. Dev., Vol. 21, No. 11, pp. 701-711, 1974. [More82]

R.M. More and J.A. Spitznagel, “Primary Recoil Spectra and Subcascade Effects in Ion Bombardment Experiments,” Rad. Eff., Vol. 60, pp. 27-33, 1982.

[Muel82]

G.P. Mueller, N.D. Wilsey, and M. Rosen, “The Structure of Displacement Cascades in Silicon,” IEEE Trans. Nucl. Sci., Vol. 29, No. 6, pp. 1293-1297, 1982.

[Nara81]

J. Narayan and J. Fletcher, Defects in Semiconductors, edited by J. Narayan and P. Tan, North Holland, London, 1981.

[Niu98]

G. Niu, G. Banerjee, J.D. Cressler, J.M. Roldan, S.D. Clark, and D.C. Ahlgren, “Electrical Probing of Surface and Bulk Traps in Proton-Irradiated Gate-Assisted Lateral PNP Transistors,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2361-2365, 1998.

[Nara88]

Private communication with J. Narayan.

[Nogu90]

T. Noguchi and M. Uesugi, “Electron Energy Dependence of Relative Damage Coefficients of Silicon Solar Cells for Space Use,” Technical Digest of the International PVSEC-5, Kyoto, Japan, 1990.

IV-106

(All references are unclassified.) [Ohya96]

H. Ohyama, J. Vanhellemont, Y. Takami, K. Hayama, T. Kudo, H. Sunaga, I. Hironaka, Y. Uwatoko, J. Poortmans, and M. Caymax, “Degradation and Recovery of Proton Irradiated Si1-xGex Devices,” IEEE Trans. Nucl Sci., Vol. 43, No. 6, pp. 3089-3096, 1996.

[Peas87]

R.L. Pease, E.W. Enlow, G.L. Dinger, and P.W. Marshall, “Comparison of Neutron and Proton Carrier Removal Rates,” IEEE Trans. Nucl. Sci., Vol. 34, No. 6, pp. 1140-1146, 1987.

[Pick93]

J. Pickel, “Novel Devices and Sensors,” IEEE Nuclear and Space Radiation Effects Conference Short Course Notes, Snowbird, UT, July 1993, pp. IV 1-60.

[Raym87] J.P. Raymond and E.L. Petersen, “Comparison of Neutron, Proton and Gamma Ray Effects in Semiconductor Devices,” IEEE Trans. Nucl. Sci., Vol. 34, No. 6, pp. 16221628, 1987. [Rax96]

B.G. Rax, C.I. Lee, A.H. Johnston, and C.E. Barnes, “Total Dose and Proton Damage in Optocouplers,” IEEE Trans. Nucl. Sci., Vol. 43, No. 6, pp. 3167-3173, 1996.

[Rax97]

B.G. Rax, C.I. Lee, and A.H. Johnston, “Degradation of Precision Reference Devices in Space Environments,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp.1939-1944, 1997.

[Rax98]

B.G. Rax, A.H. Johnston, and C.I. Lee, “Proton Damage Effects in Linear Integrated Circuits,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2632-2637, 1998.

[Reed98]

R.A. Reed, P.W. Marshall, A.H. Johnston, J.L. Barth, C.J. Marshall, K.A. LaBel, M. D’Ordine, H.S. Kim, and M.A. Carts, “Emerging Optocoupler Issues with Energetic Particle-Induced Transients and Permanent Radiation Degradation,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2833-2841, 1998.

[Robb92]

M. Robbins, “Radiation Damage Effects in Charge Coupled Devices,” Ph.D. Dissertation, Brunel University, 1992.

[Rold97]

J.M. Roldan, W.E. Ansley, J.D. Cressler, S.D. Clark, and D. Nguyen-Ngoc, “Neutron Radiation Tolerance of Advanced UHV/CVD SiGe HBT BiCMOS Technology,” IEEE Trans. Nucl. Sci., Vol. 44, No. 6, pp.1965-1973, 1997.

[Rold98]

J.M. Roldan, G. Niu, W.E. Ansley, J.D. Cressler, S.D. Clark, and D.C. Ahlgren, “An Investigation of the Spatial Location of Proton-Induced Traps in SiGe HBTs,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2424-2429, 1998.

[Rose82]

B.H. Rose and C.E. Barnes, “Proton Damage Effects on Light Emitting Devices,” J. Appl. Phys., Vol. 53, No. 3, pp. 1772-1780, 1982.

[Sext92]

F.W. Sexton, D.M. Fleetwood, C.C. Albridge, G. Garrett, J.C. Pelletier, and J.I. Gaona, “Qualifying Commercial ICs for Space Total-Dose Environments,” IEEE Trans. Nucl. Sci., Vol. 39, No. 6, pp. 1869-1875, 1992.

IV-107

(All references are unclassified.) [Schr82]

D.K. Schroder, “The Concept of Generation and Recombination Lifetimes in Semiconductors,” IEEE Trans. Elect. Dev., Vol 29, No. 8, pp. 1336-1338, 1982.

[Soda75]

K. Soda, C. Barnes and R. Kiehl, “The Effects of Gamma Irradiation on Optical Isolators," IEEE Trans. Nucl. Sci., Vol. 22, No. 6, p. 2475, 1975.

[Spra97]

J.P. Spratt, B.C. Passenheim, and R.E. Leadon, “The Effects of Nuclear Radiation on P-Channel CCD Imagers,” 1997 IEEE Radiation Effects Workshop Record, IEEE No. 97TH8293, pp. 116-121, 1997.

[Srou70]

J.R. Srour, “Short-Term Annealing in Electron-Irradiated p-Type Silicon,” IEEE Trans. Nucl. Sci., Vol. 17, No. 6, pp. 118-122, 1970.

[Srou79]

J.R. Srour, S.C. Chen, S. Ottmer and R.A. Hartman, “Radiation Damage Coefficients for Silicon Depletion Regions,” IEEE Trans. Nucl. Sci., Vol. 26, No. 6, pp. 47844791, 1979.

[Srou86]

J.R. Srour, R.A. Hartman, and K.S. Kitazaki, “Permanent Damage Produced by Single Proton Interactions in Silicon Devices,” IEEE Trans. Nucl. Sci., Vol. 33, No. 6, pp. 1597-1604, 1986.

[Srou88a] J.R. Srour, “Displacement Damage Effects in Electronic Materials, Devices, and Integrated Circuits,” IEEE Nuclear and Space Radiation Effects Conference Short Course Notes, Portland, OR, July 1988, pp. IV 1-77. [Srou88b] J.R. Srour and J.M. McGarrity, “Radiation Effects on Microelectronics,” Proc. IEEE, Vol. 76, pp. 1443-1469, 1988. [Srou89]

J.R. Srour and R.A. Hartman, “Enhanced Displacement Damage Effectiveness in Irradiated Silicon Devices,” IEEE Trans. Nucl. Sci., Vol. 36, No. 6, pp. 1825-1830, 1989.

[Srou98]

J.R. Srour, G.J. Vendura, Jr., D.H. Lo, C.M.C. Toporow, M. Dooley, R.P. Nakano, and E.E. King, “Damage Mechanisms in Radiation-Tolerant Amorphous Silicon Solar Cells,” IEEE Trans. Nucl. Sci., Vol. 45, No. 6, pp. 2624-2631, 1998.

[Summ87] G.P. Summers, C.J. Dale, E.A. Burke, E.A. Wolicki, P.W. Marshall, and M.A. Gehlhausen, “Correlation of Particle-Induced Displacement Damage in Silicon,” IEEE Trans. Nucl. Sci., Vol. 34, pp. 1134-1139, 1987. [Summ88] G.P. Summers, E.A. Burke, M.A. Xapsos, C.J. Dale, P.W. Marshall, and E.L. Petersen, “Displacement Damage in GaAs Structures,” IEEE Trans. Nucl. Sci., Vol. 35, No. 6, p. 1221, 1988. [Summ92] G.P. Summers, “Displacement Damage: Mechanisms and Measurements,” IEEE Nuclear and Space Radiation Effects Conference Short Course Notes, New Orleans, LA, July 1992, pp. IV 1-58.

IV-108

(All references are unclassified.) [Summ93] G.P. Summers, E.A. Burke, P. Shapiro, S.R. Messenger, and R. J. Walters, “Damage Correlations in Semiconductors Exposed to Gamma, Electron and Proton Radiations,” IEEE Trans. Nucl. Sci., Vol. 40, No. 6, pp. 1372-1379, 1993. [Summ94] G.P. Summers, R.J. Walters, M.A. Xapsos, E.A. Burke, S.R. Messenger, P. Shapiro and R.L. Statler, “A New Approach to Damage Prediction for Solar Cells Exposed to Different Radiations,” Record of 24th IEEE Photovoltaic Specialists Conferences, IEEE Catalog No. 94CH3365-4, pp. 2068-2075, 1994. [Sun97]

X. Sun, D. Reusser, H. Dautet, and J.B. Abshire, “Measurement of Proton Radiation Damage to Si Avalanche Photodiodes,” IEEE Trans. Elect. Dev., Vol. 44, No. 12, pp. 2160-2166, 1997.

[Sun99]

Proton irradiated avalanche photodiodes have exhibited significant room temperature annealing. Private communication with X. Sun.

[Tada82]

H.Y. Tada, J.R. Carter, B.E. Anspaugh, R.G. Downing, Solar Cell Radiation Handbook, JPL Publication 82-69, 1982.

[VanL80] V.A.J. van Lint, T.M. Flanagan, R.E. Leadon, J.A. Naber, and V.C. Rogers, Mechanisms of Radiation Effects in Electronic Materials, Volume 1, John Wiley and Sons, NY, 1980. [VanG89] A. Van Ginneken, “Non-Ionizing Energy Deposition in Silicon for Radiation Damage Studies,” Fermi National Accelerator Laboratory, P.O. Box 500, Batavia, IL 60510, Batavia FN-522, October 1989. [Walk73]

J.W. Walker and C.T. Sah, “Properties of 1.0 MeV Electron-Irradiated Defect Centers in Silicon,” Phys. Rev. B, Vol. 7, No. 10, p. 4587-4605, 1973.

[Walt91]

R.J. Walters, S.R. Messenger, G.P. Summers, E.A. Burke, and C.J. Keavney, “Space Radiation Effects in InP Solar Cells,” IEEE Trans. Nucl. Sci., Vol. 38, No. 6, pp. 1153-1158, 1991.

[Walt99]

R.J. Walters, M.A. Xapsos, G.P. Summers, and S.R. Messenger, “Analysis and Modeling of the Radiation Response of Space Solar Cells,” 1999 GOMAC Proc., pp. 434-437, 1999.

[Wate87]

J.R. Waterman and R.A. Schiebel, “Ionizing Radiation Effects in n-Channel HgCdTe MISFET’s with Anodic Sulphide Passivation,” IEEE Trans. Nucl. Sci., Vol. 34, No. 6, pp. 1597-1601, 1987.

[Watk64]

G.D. Watkins and J.W. Corbett, “Defects in Irradiated Silicon: Electron Paramagnetic Resonance and Electron-Nuclear Double Resonance of the Si-E Center,” Phys. Rev., Vol. 134, No. 5A, pp. 1359-1377, 1964.

[Wicz82]

J. Wiczer, L. Dawson, G. Osburn and C. Barnes, “Permanent Damage Effects in Si and AlGaAs/GaAs Photodiodes,” IEEE Trans. Nucl. Sci., Vol. 29, No. 6, pp. 15391544, 1982. IV-109

(All references are unclassified.) [Wood81] S. Wood, N.J. Doyle, J.A. Spitznagel, W.J. Choyke, R.M. More, J.N. McGruer, and R.B. Irwin, “Simulation of Radiation Damage in Solids,” IEEE Trans. Nucl. Sci., Vol. 28, pp. 4107-4122, 1981. [Yama84] M. Yamaguchi, C. Uemura, and A. Yamamoto, “Radiation Damage in InP Single Crystals and Solar Cells,” J. Appl. Phys., Vol. 55, pp. 1429-1436, 1984. [Yama88] M. Yamaguchi and K. Ando, “Mechanism for Radiation Resistance in InP Solar Cells,” J. Appl. Phys., Vol. 63, p. 5555, 1988. [Yama96] M. Yamaguchi, S.J. Taylor, M. Yang, S. Matsuda, O. Kawasaki, and T. Hisamatsu, “High-Energy and High-Fluence Proton Irradiation Effects in Silicon Solar Cells,” J. Appl. Phys., Vol. 80, pp. 4916-4920, 1996. [Zeig84]

J.F. Zeigler, J.P. Biersack, and U. Littmark, The Stopping and Range of Ions in Solids, Pergamon Press, New York, 1984.

[Zhao97]

Y.F. Zhao, A.R. Patwary, R.D. Schrimpf, M.A. Neifeld, and K.F. Galloway, “200 MeV Proton Damage Effects on Multi-Quantum Well Laser Diodes,” IEEE Trans. Nucl. Sci., Vol. 44, pp. 1898-1905, 1997.

[Zhao98]

Y.F. Zhao, R.D. Schrimpf, A.R. Patwary, M.A. Neifeld, A.W. Al-Johani, R.A. Weller, and K.F. Galloway, “Annealing Effects on Multi-Quantum Well Laser Diodes after Proton Irradiation,” IEEE Trans. Nucl. Sci., Vol. 44, pp. 2826-2832, 1997.

IV-110

SYSTEM LEVEL MITIGATION STRATEGIES William F. Heidergott Motorola, Inc., Satellite Communications Group Mobile Satellite Systems Group

1.0

Introduction

2.0

Space Telecommunications Industry 2.1 Historical Perspective 2.2 Status and Systems Presently in concept, Development, or Deployment 2.3 Projections for Future Space Systems 2.4 Characteristics of Telecommunications Satellite Systems 2.5 Orbit Architecture of Telecommunications Constellations

3.0

The Space Environment 3.1 Energetic Charged Particle Environments 3.1.1 Trapped Particles: Protons, Electrons, and Heavy Ions 3.1.2 Galactic Cosmic Ray Heavy Ions 3.1.3 Solar Particles 3.2 Plasma Environment and Spacecraft Charging 3.3 Other Space Environment Considerations

4.0

Space Radiation Effects on Devices and Technologies 4.1 Mission Integrated Effects 4.1.1 Total Ionizing Dose 4.1.2 Displacement Damage Dose 4.2 Destructive Single Event Effects 4.2.1 Single Event Latchup and Snapback 4.2.2 Single Event Burnout and Gate Rupture 4.2.3 Single Event Hard Error and Single Event Dielectric Rupture 4.3 Single Event Upset and Transients 4.3.1 Single Event Upset and Transient in Digital Devices 4.3.2 Single Event Transients in Analog Circuits 4.3.3 Single Event Functional Interrupt

5.0

Systems Engineering for Space Radiation Environment Compatibility 5.1 Tolerance to Mission Integrated Effects 5.2 Mitigation of Destructive Single Event Effects 5.3 Analysis of Single Event Upset Rates and System Effects 5.3.1 Component Single Event Upset Characterization 5.3.2 Environment Models 5.3.3 Performing Rate Estimate Calculations 5.3.4 Effects and Consequence on System Operations 5.4 Spatial and Temporal Variation in the Charged Particle Environment

V-1

6.0

Fault Tolerant Systems Engineering 6.1 System Reliability and Availability 6.2 Fault Tolerant Systems Design 6.3 Fault Avoidance 6.3.1 System Operations and Orbit Architecture 6.3.2 Effectiveness of Shielding 6.3.3 Mitigation of Charge Generation and Collection 6.3.4 Mitigation of Circuit Response 6.4 Fault Masking and Redundancy 6.4.1 Error Detection and Correction (EDAC) Coding 6.4.1.1 EDAC Coding in Data Storage and Communication 6.4.1.2 EDAC in Arithmetic and Logic Structures 6.4.2 Redundancy 6.4.2.1 Spatial Redundancy 6.4.2.2 Temporal Redundancy 6.4.2.3 Combined Redundancy Implementation 6.5 System Error Detection and Recovery 6.5.1 Application Oriented Fault Tolerance 6.5.1.1 Acceptance Testing 6.5.1.2 Constraint Predicates 6.5.2 Algorithm Based Fault Tolerance (ABFT) 6.5.3 Detection Through Protocol, Timing and Data Checking 6.5.4 System Recovery Provisions 6.5.4.1 Recovery Blocks 6.5.4.2 Check-Pointing and Roll-Back Recovery 6.5.4.3 Fault Containment 6.5.4.4 Reconfiguration and Recovery 6.6 Development of Fault Tolerant Systems 6.6.1 Mitigation Requirements Based on Fault Criticality 6.6.2 Validation and Verification of Fault Tolerance

7.0

Summary

8.0

Acknowledgements

9.0

References

V-2

1.0

Introduction

Satellite based telecommunications has progressed from the function and purpose of the earliest envisioned usage of earth orbiting systems to the primary purpose of the majority of satellites launched today. Communications satellites serve a variety of markets and function in numerous system architectures and operational concepts. Geostationary satellites have historically provided the majority of telecommunications services, but the recent deployment of low-earth orbiting constellations are supporting new market opportunities. Numerous geostationary and low-earth orbit systems are envisioned or are currently under development to support telecommunication system applications. Operating in the environment of space presents numerous requirements to the design, development, and operation of these systems. The charged particle radiation environment produces both long term and transient effects on payload systems. This environment is composed of particles trapped in the geomagnetic field of the earth, particles emitted by the sun, and those traversing interstellar space. The plasma environment resulting from the presence of charged particles, operation in the vacuum environment, exposure to the flux of neutral particles, and the potential for collisions with other objects along the orbit trajectory are other factors which must be considered. Detailed understanding of the energetic charged particle environment and the effects which are produced as these particles interact with sensitive devices is essential to the development of satellite systems. Design for compatibility with the space environment requires a complete spectrum of mitigation techniques in the development of cost effective systems, including component level solutions as well as fault tolerance techniques implemented at the system and subsystem applications level. The selection of technology and fault tolerance strategy to be utilized in system development must be supportive of high availability, and provide power efficient implementations. Although availability and reliability connote similar attributes, availability to subscribers is the revenue producing result; reliability is one of the elements which support availability and cost effectiveness. Efficient utilization of satellite power is an important attribute of telecommunications payloads; optimum allocation of power to subscriber RF link operation is necessary. Inefficient technology, or an implementation which results in higher than necessary operating power, requires additional solar array area to produce power, larger batteries to store the power, and a more robust thermal management system to transfer the heat. All of these needs translate to increased payload weight, and hence degrade the cost effectiveness of the system. A fault tolerant system design embodies the principles of fault avoidance, fault masking, detection of compromised system operation, containment of error propagation, and recovery to normal system operations. Consideration of some of the techniques in each of these subject areas is applicable to the design and development of telecommunications satellite systems.

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2.0 2.1

Space Telecommunications Industry

Historical Perspective [SIA98] [Whalen98]

From the inception of man-made satellite development and deployment, telecommunication has been the objective of the majority of space systems. Today, satellite based telecommunications is indispensable as a basic tool of human social activities. A communications satellite provides the ability to cover wide areas of the earth’s surface, including remote and sparsely populated areas lacking in terrestrial communications infrastructure. The early concepts of communications satellites date back to the fall of 1945 when an RAF electronics officer and member of the British Interplanetary Society, Arthur C. Clarke, wrote an article in Wireless World entitled, “Extra-Terrestrial Relays,” describing 24-hour orbit (geostationary) satellites. The first person to evaluate both the technical options and financial feasibility of telecommunications satellites was John R. Pierce of AT&T Bell Laboratories in a 1955 article, “Orbital Radio Relays.” The early development of communications satellites focused on mirrors or passive satellites (ECHO), but soon moved to repeater or active satellites which could amplify the received signal, providing much higher quality communications. In 1961 RCA was developing a medium-earth orbit system (RELAY), AT&T launched its mediumearth orbit TELSTAR satellite, and Hughes was developing the geosynchronous SYNCOM satellite. By 1964, two TELSTARs, two RELAYS, and two SYNCOMs had successfully operated in space. Global satellite communications began in 1965 with COMSAT’s launch of the EARLY BIRD geosynchronous satellites; based on Hughes and TRW designs they provided 240 voice circuits or one television signal. Some of the events from the early days of communications satellites to today’s global networks include: 1945 1955 1956 1957 1958 1960 1962 1962 1963 1964 1964 1965 1966 1969 1972 1974 1976 1978 1979 1982 1988 1988 1990 1992 1995 1997 1998

-

Arthur C. Clarke Article, Manned Geosynchronous Communications Satellites John R. Pierce Article, Technical and Economic Feasibility of Comm Satellites First Trans-Atlantic Telephone Cable (TAT-1), 36 Simultaneous Calls SPUTNIK, First Earth Satellite EXPLORER-1, First US Satellite ECHO-1, First Experimental Communications Satellite TELSTAR-1, First Active Communications Satellite RELAY-1 Launched SYNCOM-2 Launched, First Successful Geostationary Comm Satellite Tokyo Olympic Television Coverage Using Satellite Communications INTELSAT Formed COMSAT EARLY-BIRD (Intelsat-1), First Commercial Comm Satellite First Domestic Satellite Communications Constellation (4 Molniya Satellites) INTELSAT-III Provides Global Coverage ANIK, Domestic Communications Satellite (TELESAT CANADA) WESTAR, First US Domestic Communications Satellite MARISAT, First Mobile (Maritime) Communications Satellite ANIK-B First Hybrid Ku-Band and C-Band Satellite INMARSAT Formed MARECS, European Mobile (Maritime) Communications Satellite First Trans-Atlantic Fiber-Optic Telephone Cable (TAT-8) World Radio Conference (ORB-88) Regulating GSO and DBS Plan INMARSAT Second Generation Satellites WARC-92 Frequency Allocations for Mobile and Fixed Station Services PanAmSat, First Private Global Satellite Services Big LEO Systems (GLOBALSTAR and IRIDIUM) Launched Little LEO Systems (ORBCOM) Launched

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Fiber optic systems have enabled terrestrial infrastructure to regain some of the movement toward satellite based telecommunications, particularly Interexchange Telephony. But other services such as Personal Communications Systems (PCS), Very Small Aperture Terminals (VSAT), Direct television Broadcast Services (DBS), Digital Audio Broadcasting (DAB), and multimedia services are fueling continued development of the telecommunications satellite industry. Domestic satellite systems are considered to be those controlled by operators located within a region and serving only (or mostly) one country. There are currently six companies providing fixed satellite service to the US, using 36 operational satellites. Regional satellite systems are operated by organizations having their main location of business within a region and serving all of the countries within the region. International operator’s satellite systems provide service between major geographic regions and/or global service offerings. Very Small Aperture Terminals (VSAT) networks are used primarily by corporations for intracorporate data, video, and voice communications such as point-of-sale credit authorization, and inventory control among multiple remote locations. Automotive, retail, and financial service industries are particularly heavy VSAT users. Originally, North American domestic satellites were mostly used for long-distance telephone communications. Home Box Office distribution of satellite programming in 1975 began a move by major television networks to distribute regular programming and special events to affiliates using satellite based communications services. Television Receive Only (TVRO) began initially using home satellite dishes to provide service to rural areas which were difficult to connect via cable infrastructure. The use of digital compression technology and high power Ku-Band satellites permit Direct Broadcast Services (DBS) to end users requiring small, 18-inch, antennas. DBS not only provides services to rural users not connected to cable, but also is becoming a strong competitor to cable in urban areas. Low-Earth Orbiting (LEO) systems presently in operation, deployment, and development provide worldwide personal, portable, and mobile telephony, messaging, and data communications services. Little-LEO service providers offer global mobile data, messaging, and position determination services. Big-LEO telephony systems provide mobile voice, fax, messaging, and limited data rate services. Big-LEO and geostationary (GEO) fixed station systems will provide worldwide broadband, high-speed digital communications and multimedia services. Global trade in satellite-based telecommunications is expected to escalate rapidly in the next few years due to the launch of LEO constellations and networks, MEO satellites, and continued growth in geostationary resources. The International Telecommunications Union (ITU), which regulates all of this activity, predicts that the ultimate winner will undoubtedly be the consumer. Greater variety, more innovative services, and cheaper prices will spur the development of Global Information Infrastructure, and bring cost-effective, user-friendly communications tools and services to more people throughout the world. Wireless technologies are the enabler for much of this growth, particularly in rural markets, and terrestrial implementations, such as wireless local loop, and satellite based services will support this market.

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2.2

Status and Systems Presently in Concept, Development or Deployment [Evans98]

There are indications that the geostationary (GSO) satellite industry which supports traditional services and markets has reached the peak of the third production cycle. The GSO production cycles match the spacecraft technology generation; i.e., when operators replace the satellites which they launched in the previous cycle. The first cycle was from 1972 – 1979 in which thirty-seven satellites were launched, the second from 1980 – 1989 with ninety-six launches, and the third starting in 1990 and projected to last until approximately 2002 with slightly over three hundred satellites launched. The time interval between the peak of each phase matches approximately the nominal satellite lifetime of five years, nine years, and thirteen years respectively. The primary power for the largest of the satellites in each phase has increased from 1,000 watts in 1977, to 1,500 watts in 1985, and as high as 15,000 watts in 1998; the weight of these satellites were 1,700 kg, 2,500 kg, and 4,700 kg respectively. Geostationary satellite systems initially utilized spectrum in C-band (4 – 8 GHz), Ku-band (10.9 – 17 GHz) transponders were deployed in the 1980s, and initial Ka-band (18 – 31 GHz) systems have been deployed in the 1990s. The present distribution of geostationary transponders is approximately 46% C-band, 51% Ku-band, and 3% in Ka-band. Most systems presently in concept development, design and construction, or deployment address either the Global Mobile Personal Communications Services (GMPCS) market or Broadband Satellite Services (BSS). Table 2-1 indicates a few of the programs by type and market segment; Table 2-2 indicates the satellite content of some of the broadband satellite systems. Orbit Architecture GEO Regional Narrowband Systems

Broadband Systems (BSS)

MEO

LEO

ICO

ECCO/Constellation Ellipso Globalstar Iridium

Global

ACeS (Asia) APMT (Asia) ASC/Agrani (Mid-East) EAST (Europe) Satphone (Africa) Thuraya

GMPCS Systems

Astrolink CyberStar Expressway Spaceway

Spaceway

SkyBridge Teledesic

Table 2-1. Satellite Telecommunications Systems

2.3

Projections for Future Space Systems [SIA98][Givens98][ITU98]

Forecasting future space industry economic activity is still a black art, with no agreed baseline or standards, no complete industry definition, and potentially erroneous technical and economic assumptions. Fourth generation geostationary systems will exhibit increased nominal

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Satellite System

Communications Lead Band Participants

Number of Satellites

Broadband GEO

Astrolink CyberStar Expressway Spaceway

Ka Ka Ku/V Ka

Lockheed Martin Loral, Alcatel Hughes Hughes

Broadband MEO

Spaceway

Ka

Hughes

20

Broadband LEO

SkyBridge Teledesic

Ku Ka

Alcatel, Loral Motorola, Boeing, Gates, McCaw

80 288

5-9 3 14 8

Table 2-2. Broadband Satellite Systems

lifetime, and may exhibit increased power (up to 20,000 watts), and increased mass (up to 6,000 kg). The total mass launched to orbit is expected to double over the next five years. This increase is attributed to Big-LEO mobile systems (Globalstar, Iridium, etc.), Broadband-LEO (Skybridge, Teledesic, etc.), and Broadband-GEO (Spaceway, Astrolink, etc), with Little-LEO constellations (Orbcomm, etc) included, and government and military systems remaining flat. This growth is predicated upon the success of the initially deployed constellations within these market segments. The predictions indicate that the global commercial imaging industry will follow and complement the telecommunications industry expansion of the last twenty years. The present market for satellite remote sensing imaging is only a few hundred million dollars, so the challenge for the companies is to produce market pull and develop new markets. Product improvements through the integration of simultaneously collected multispectral and panchromatic imagery in combination with “n”-meter resolution are the technologies which will enable improved support for agribusiness, civil government applications, and commercial markets which are not after the imagery itself, but instead the value-added informational value conveyed by the images. Increasingly sophisticated payloads and system architectures will be required to support the higher data content in multispectral images with increased dynamic range, the ability to provide seamless global coverage, and fast delivery and distribution of imaging products. The primary participants in this market are Space Imaging Inc. (IKONOS satellites), EarthWatch Inc. (EarlyBird satellites), OrbImage, a subsidiary of Orbital Sciences Corporation (OrbView satellites), and SPOT Image (SPOT satellites). Merrill-Lynch has predicted that total revenues for the “space industry” will quadruple in the next decade, rising from $40B in 1998 to $170B in 2007. However, much of this revenue comes from ground segment purchases, not “space hardware.” The general consensus seems to indicate a doubling in space segment revenue. As an example, the value added chain for commercial LEO and GEO mobile communications systems (cumulative through 2007) shows $11B in payloads, spacecraft, and launch services, $13B in satellite operations, $55B in ground

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segment hardware and software, and $80B in value-added services, including the development of new services based upon communications satellite technology. Similar numbers for fixed station and broadcast LEO and GEO systems may be six times larger.

2.4

Characteristics of Telecommunications Satellite Systems [ITU98]

Telecommunications systems are classified as to the users they support, either mobile or fixed satellite services, and are defined by their operational characteristics as either store-andforward, bent-pipe, or intersatellite linked networks. The International Telecommunications Union (ITU) designation of Mobile Satellite Service (MSS) classifies radio communications among mobile subscribers and between mobile subscribers and Public Switched Telephone Network (PSTN). Classes of service within MSS include Aeronautical Mobile Satellite Service (AMSS), Maritime Mobile Satellite Service (MMSS), and Land Mobile Satellite Service (LMSS). Subscribers in MSS systems may gain access to the communications network from anywhere in the antenna footprint of the satellite or constellation. Fixed Satellite Service (FSS) is defined as radio communication between subscribers at specified fixed locations. Subscribers in FSS systems may gain access to the communications network only from their registered earth terminal location. The operational characteristic of a satellite system refers to the method or means in which subscriber information is propagated through the communications network. In messaging systems where concurrent contact between the sender and receiver of a message is not necessary, store-and-forward systems provide lower cost solutions. These systems support two-way data communications and messaging (but not telephony) and data gathering such as asset tracking, environmental assessment reporting, and remote data acquisition and reporting are specific markets of these systems. Figure 2-1 indicates the situation in which the satellite is not capable of simultaneous contact with both the originator and receiver of the message. In store-andforward systems, the satellite receives a message from the originator while in direct contact with their location, stores the message in payload memory, and transmits the message to the recipient when the satellite is in view. Systems which operate according to the same principle, but with minimal delay, are referred to as Near-Real-Time systems. Orbcomm, Gonets, and Leo One are near-real-time systems requiring 28, 45, and 48 satellite constellations respectively. Faisat, Safir, E-Sat, Iris, and Vitasat provide (or will provide) store-and-forward services for low-rate data and messaging services.

Figure 2-1. Store-and-Forward and Near-Real-Time Systems [Richharia95]

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Figure 2-2 depicts a communication in which a satellite has both a subscriber terminal and ground-station simultaneously in view and has an established communication with both of the terrestrial entities. The ground station could be a direct television broadcast facility and the subscriber terminal a DBS television receiver, in which case there exists only an uplink from the ground station to the satellite and a downlink from the satellite to the subscriber terminal. In this case the function performed by the satellite is to receive the uplink, frequency translate to the desired downlink frequency, and then amplify and transmit the downlink signal; the satellite transponder is providing analog bent-pipe service. The ground station could be a gateway of a mobile satellite services system and the subscriber terminal a mobile telephone, in which case the satellite establishes both uplink and downlink communications channels with both. The satellite receives the uplink signal from either the gateway or subscriber unit, demodulates it to baseband digital information, modulates the transmit signal and downlinks it to the subscriber unit or gateway systems. In this case the satellite payload is providing digital bent-pipe service. In the bent-pipe approach, all networking and routing processes are performed on the ground.

Figure 2-2. Bent-Pipe Telecommunications Satellites [Jamalipour98]

The alternative method for routing and propagating traffic through the network is to implement intersatellite communications links between the satellites and to route traffic through the space network with need to downlink to a gateway only to achieve interconnection with the public switched telephone network. The advantage of using intersatellite links (ISL) is to provide true global coverage in which a satellite can provide service without need for simultaneous contact with a gateway, such as over the oceans, and to reduce the total number of gateways necessary to support the network. The redundancy available through diversity of communications channels in the space network enables continued utilization of the system in case of gateway outage. These benefits indicate the advantages from a logical networking perspective. Figures 2-3 and 2-4 depict an intersatellite linked constellation.

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Figure 2-3. Intersatellite Link (ISL) System [Richharia95]

Figure 2-4. Personal / Mobile Intersatellite Linked System [Jamalipour98]

The disadvantages of intersatellite links arise mostly from consideration of the physical satellite engineering perspective, resulting in increased complexity of the satellite payload. Implementation of intersatellite communications links requires space vehicle attitude stability and antenna tracking and pointing control to establish RF links and to compensate for large Doppler shifts at high latitudes. Large on-board processing loads result from management and switch routing of traffic within the payload. The Iridium mobile telephony constellation has deployed an intersatellite networked constellation and ISL implementations are planned for LEO broadband satellite constellations.

2.5

Orbit Architecture of Telecommunications Constellations [Gordon 93]

Low-earth orbit satellites typically refer to orbit altitudes between 500 km and 2000 km, and inclination angles between 30° and 90°. LEO satellites are normally launched into their operational plane at a parking altitude of 300 km to 400 km and elevated to mission altitude

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using spacecraft propulsion. Initial active communications satellites launched in 1962, Telstar and Relay, were placed into LEO orbits due to constraints on launch vehicle performance. Although many other mission types have utilized LEO orbits, until recently few telecommunications satellites have utilized this orbit altitude, primarily due to the large number of satellites necessary to achieve adequate earth coverage. The main advantage of LEO satellites is the reduced distance between the subscriber and satellite, resulting in reduced RF propagation path loss and reduced delay time for signal propagation. Reduced RF propagation path loss results in the need for less subscriber unit radiated power and smaller satellite uplink antenna aperture. Achieving small subscriber unit size and weight necessitates the reduced radiated power and small antenna configuration enabled by the LEO signal propagation distances. The reduced signal propagation delay time is important in telephony applications where the several hundred millisecond delay associated with geostationary links is uncomfortable for most telephone users. The main disadvantage of a LEO constellation is the movement of the satellite with respect to both mobile and fixed station users. This results in the limited visibility that a single satellite presents to a subscriber. Movement of the satellite requires the use of an omnidirectional antenna on subscriber equipment and a tracking antenna for other ground segments requiring communication with the satellite. The limited duration of contact between an individual satellite and a subscriber results in the need for numerous satellites to provide continuous communications services to the subscriber. The elevation angle is the angle between a line connecting the subscriber to the satellite and the subscriber’s horizon plane. Operation at low elevation angles results in additional path loss due to increased distance and atmospheric loss factors, highly distorted antenna patterns, the opportunity for obscuration by local geographic features and terrain, and ITU regulations limiting power flux density to prevent interference with other terrestrial and space systems. Figure 2-5 indicates the required number of satellites to provide global coverage as a function of satellite altitude for several minimum elevation angles. Figure 2-6 describes the number of orbit planes into which the satellites must be deployed in order to assure operation at the minimum elevation angle in the equatorial regions. In assessing the number of satellites required for a constellation, consideration is also given to the benefits of providing diversity by having more than one satellite in view of a subscriber. In addition to determining the number of Figure 2-5. Number of Satellites for Global Coverage satellites which are necessary [Jamalipour98] to provide coverage, the V-11

relationship of the satellites within the constellation must be considered. The Walker-star configuration uses adjoining planes traveling in the same north-south direction, resulting in two seam segments. Walker-delta and Ballard-rosette configurations result in adjoining planes not traveling in the same direction, hence no defined seam region. Figure 2-7 provides comparison between the star-seamed configuration and the delta or rosette seamless configuration.

Figure 2-6. Number of Orbit Planes (Ω) for Equatorial Coverage [Jamalipour98]

Figure 2-7. Walker Star-Seamed and Walker-Delta (Ballard Rosette) Orbit Planes [Wood98]

Historically, the orbit used for most telecommunications satellites has been geostationary, in which the orbital period equals one sidereal day, and the inclination angle is near zero. It takes more launch vehicle capability to reach geostationary orbit, and more station keeping fuel than any other telecommunication satellite orbit. The geostationary orbit plane already contains numerous satellites; the ITU regulates the assignment of slot positions. With slot assignments spaced at 2° intervals the physical separation between satellites is a considerable 1,470 km, but the opportunity for frequency interference exists. Comparison with lower earth orbit configuration in regard to RF path losses and propagation delay have been previously discussed.

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The elevation angle to geostationary satellites reduces to less than 15° at latitudes greater than 67°. In the specific instance of Russia for example, most of the country must operate at low elevation angles; major portions of the region are unacceptably low. The Molniya orbit, which uses a 62.9° inclination angle highly elliptical orbit (apogee of 39,400 km and perigee of 1000 km) addresses this issue. The apogee and perigee values are chosen to yield an orbital period of exactly one-half sidereal day, with apogee at the northern-most segment of the orbit traverse. In this manner four satellites, each used six hours per day, provide continuous presence of a high elevation angle telecommunications satellite in high latitude regions.

3.0

The Space Environment and Effects

The design of any system requires consideration of the environment in which it must operate to ensure performance (availability), reliability, and mission life. The near-Earth space environment is complex and dynamic; its behavior depends upon the characteristics of the earth, activity and events occurring in the Sun, and the nature of the environment in interplanetary and interstellar space. Environmental factors include energetic charged particles, plasmas, neutral atoms and molecules, other orbiting objects, micrometeoroids, and electromagnetic radiation. The relative severity of these environmental factors vary with orbit configuration (altitude and inclination), location (latitude and longitude), local time, season within the year, and interval within the solar cycle. Although often considered a near perfect vacuum, the presence of these factors presents challenging design requirements which are unique to space systems.

3.1

Energetic Charged Particle Environments [Barth97][Dyer98]

The energetic charged particle environment is quite complex; it is not homogeneous, isotropic, nor static. The primary sources of energetic particles present in the environment of earth orbiting telecommunications satellites are the geomagnetically trapped particles, protons and electrons, the transient population of cosmic ray protons and heavy ions, and solar event generated protons and heavy ions. Flux levels of these particles vary with solar activity, and models of the environment reflect the changes in the population of these particles over the approximate eleven-year solar cycle. Modeling of the environment usually divides the solar cycle into a seven-year interval of solar maximum and a four-year interval of solar minimum.

3.1.1

Trapped Particles: Protons, Electrons, and Heavy Ions

Particles trapped in the earth’s geomagnetic field present the most significant contribution to the environment for low-Earth orbit, medium-Earth orbit, and highly elliptical orbit spacecraft. Ionization effects due to trapped protons contribute the majority of total ionizing dose effects, non-ionizing energy loss processes result in displacement damage dose effects, and reactions with atoms in the device structure result in single event effects in more sensitive devices and technologies. Particles trapped in the earth’s geomagnetic field present the most significant contribution to the environment for low-Earth orbit, medium-Earth orbit, and highly elliptical V-13

orbit spacecraft. Ionization effects due to trapped protons contribute the majority of total ionizing dose effects, non-ionizing energy loss processes result in displacement damage dose effects, and reactions with atoms in the device structure result in single event effects in more sensitive devices and technologies. The integral flux of trapped protons as a function of orbit altitude at the magnetic equator is indicated in Figure 3-1. The slope of this characteristic, particularly along the lower margin of the inner belt region indicates that fairly small changes in orbit altitude result in significant changes in the exposure to trapped protons. The other characteristic of geomagnetically trapped protons is the asymmetry which results from the South Atlantic Anomaly (SAA) region. Figures 3-2 and 3-3 indicate contours of proton flux at altitudes of 500 km and 1000 km respectively. In the case of devices and technologies which are susceptible to energetic proton induced single event effects, the rate of occurrence of these effects is highly non-uniform over an orbit traverse through the SAA region.

Figure 3-1. Variation of Proton Flux Levels [Barth97]

Figure 3-3. Proton Flux Contours at 1000 km. [Barth97]

Figure 3-2. Proton Flux Contours at 500 km. [Barth97]

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The integral flux of trapped electrons as a function of orbit altitude at the magnetic equator is indicated in Figure 3-4. As described above for trapped protons, small changes in orbit altitude produce significant changes in the exposure to trapped electrons (on the lower margin of the inner belt region). The separation of the trapped electron regions into two zones is also depicted in this figure. Figures 3-5 and 3-6 indicate the contours of electron flux at altitudes of 500 km and 1000 km respectively; as shown previously for protons, the presence of the SAA region is indicated. Also present in these figures are the populations of electrons in the high latitude extensions of the outer belt structure forming the horn regions. Electrons are not as penetrating as protons, and shielding is significantly more effective at attenuating their effects on microelectronic devices. Figure 3-4. Variation of Electron Flux Levels Electrons contribute to mission integrated [Barth97] ionizing dose effects, caused by primary electrons and secondary photons which are produced when the incident electrons are stopped or slowed by the shielding materials.

Figure 3-6. Electron Flux Contours at 1000 km. [Barth97]

Figure 3-5. Electron Flux Contours at 500 km. [Barth97]

It is known from particle spectrometer measurements of the environment that anomalous cosmic rays become trapped in the magnetosphere. These trapped heavy ions lack sufficient energy to penetrate typical spacecraft shielding and therefore do not contribute significantly to mission-integrated dose or single event effects in microelectronic devices.

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3.1.2

Galactic Cosmic Ray Heavy Ions

Flux levels of Galactic Cosmic Ray (GCR) heavy ions are low compared to the population of geomagnetically trapped particles. They are extremely penetrating and result in single event effects in microelectronics devices; however, their contribution to mission integrated dose effects is minimal. The population of galactic particles varies with solar cycle; their population is highest during solar minimum and lowest during solar maximum, due to interaction with the solar wind. The ability of GCR heavy ions to penetrate the geomagnetic field results in the exposure to this particle population varying with spacecraft orbit. Increases in orbit altitude and inclination angle result in increased exposure to GCR heavy ions.

3.1.3

Solar Particles

Although often referred to as solar flares, the events producing increased energetic particle population in the near earth environment are coronal mass ejections which have no fundamental association with flares. As indicated above, the solar cycle may be divided into solar minimum and solar maximum periods; the majority of solar particle events typically occur near (but not necessarily coincident with) the peak of solar maximum. Although the frequency of occurrence of significant solar particle events is reduced during solar minimum, they can and do occur during this interval as well. Anticipation of the peak in the solar maximum phase in calendar year 2000 has fueled much speculation and press coverage concerning the impact which these events will present to satellite systems. Characteristics of solar particle events observed during the 22nd solar cycle (1986 – 1997) indicate wide diversity in energy spectra and particle composition. What was once viewed as two event classes, an ordinary event and an anomalously large event, is now viewed as a continuum of possible characteristics, making the definition of a typical event difficult. Systems operating during solar particle events must consider that both solar protons and solar heavy ions produce increased single event effect rates. Solar heavy ions result in minimal contribution to total ionizing dose effects, but peak particle flux levels are often orders of magnitude greater than background GCR. Solar protons contribute to increased levels of single event effects and to both total ionizing dose and displacement damage dose effects in sensitive devices and technologies. It is important to note that the peak elevated flux levels will typically persist for several hours to a few days. As indicated above for GCR heavy ions, the degree of geomagnetic attenuation of the solar particles determines the flux levels which will be present at various orbit altitude and inclination conditions. Increases in inclination of the spacecraft orbit result in more significant increases in solar proton exposure than does increase in orbit altitude. Because solar particle events may coincide with geomagnetic field disturbances the ability of solar heavy ions to propagate to lower altitudes and lower latitude regions must also be considered.

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3.2

Plasma Environment and Spacecraft Charging [Frederickson96] [Tribble95][Holbert96]

Near-Earth satellites encounter energetic charged particles; a population of both positively charged ions and negatively charged electrons - plasma. The external surfaces of spacecraft experience a higher flux of electrons than ions, charging the body of the spacecraft negatively with respect to the nearby ambient plasma, resulting in surface charging. Although surface charging may potentially result in effects on the spacecraft, the limited energy storage associated with the small capacitance of the spacecraft to the ambient plasma indicates that this is not a major contributor to anomalies. One area of concern in regard to surface charging is the potential for reattraction of contaminant ions. A percentage of the neutral atoms outgassed by spacecraft materials may become ionized by solar UV and be attracted to sensitive charged surfaces. In differential surface charging, differences in the emission and absorption characteristics of materials, differences in sunlight exposure, and localized effects resulting in unequal electron populations produce voltage differences between insulated satellite surfaces. Electrons having sufficient energy to pass through the thermal blanket result in internal charging of surfaces and assemblies. Typical insulated objects include cable jackets, ungrounded thermal wrap, thermal paint, component encapsulants, etc. Higher energy electrons penetrating subsystem chassis assemblies may deposit charge onto circuit board and wire insulators, connectors, capacitors, etc. In this process, termed deep dielectric charging, highenergy electrons penetrate circuit elements and devices, leading to trapped charge buildup within the dielectric material. Design guidelines for assessing and controlling spacecraft charging effects, published by NASA, provide guidance for incorporating design practices to mitigate these effects. Where possible, the use of filters to prevent the propagation of discharge-event-created signal transients may be used. The use of surface coatings (paint, etc.) and materials which provide dissipation of deposited charge, is recommended. Shielding of electronic assemblies to reduce the flux of highenergy electrons impinging on sensitive devices and materials are some of the provisions typically utilized in addressing charging effects.

3.3

Other Space Environment Considerations [Purvis93] [Tribble95]

Vacuum Environment Design for operation in the vacuum environment of space results in constraints in the selection of materials which may be used, and in the design of thermal control provisions. During exposure to very low pressure conditions, many materials exhibit a mass loss through outgassing. Most materials contain fractional amounts of volatile chemicals, either on the surface of the material or dispersed through it. The degree of outgassing has been shown to decline exponentially as a function of time, inversely as a power of time, or at a constant rate over time, depending on whether the process involved is desorption, diffusion, or decomposition (or some combination of these processes). Desorption is the release of surface molecules which were held in place by physical or chemical forces. Diffusion is the process by which molecules V-17

propagate to the material surface, driven by random thermal motion, some of these have sufficient energy to escape surface forces and propagate into the local environment. Decomposition is the process in which material breaks down into other compounds which then outgas through desorption or diffusion. Once the molecules leave the surface of the material, they follow ballistic trajectories and usually interact with any surface having line-of-sight relationship to the material. If the outgassed material were to deposit on thermal control surfaces or sensitive optics, the performance of these items would become degraded. Because the deposition occurs basically one molecule at a time, this type of contamination is referred to as molecular contamination. Non-line-of-sight transport may also occur when collisions with other ambient atmosphere molecules changes their trajectory. Secondary desorption from an intermediate surface often results in particles which are ionized and hence may be attracted to charged surfaces by electric fields. UV exposure may interact with the molecular contamination process to enable photochemical deposition. Mitigation provisions focus on careful selection of stable materials and coatings, pretreating materials with vacuum bake-out, configuring the design such that outgassed material is not allowed easy access to sensitive devices, and including additional design margin in the application of sensitive devices to allow for expected degradation. Also related to the vacuum environment is the level of exposure to ultraviolet (UV) light; most UV is absorbed by the ozone in the earth’s atmosphere. Solar UV degradation of the absorptance of radiators used in thermal control systems is one potential area of concern. Materials must be evaluated and chosen based upon susceptibility to degradation when exposed to UV.

Neutral Environment The impact between a spacecraft and individual atoms results in aerodynamic drag and may result in sputtering and chemical reactions with surface materials. Concern over the effects of the neutral environment is most profound at very low altitudes, decreasing with increased orbit altitude, and is not a significant issue above 1000 km. Atomic oxygen (AO), produced by the decomposition of ozone into molecular oxygen which is then broken down into atomic oxygen, is most prevalent between 175 km and 650 km; helium is the dominant contributor above 650 km. Physical sputtering occurs when neutral molecules impact spacecraft surfaces with sufficient energy to sever the chemical bond of surface atoms. AO is known to interact with a wide variety of materials, resulting in erosion and degradation of the properties of the surface material. Mitigation provisions for neutral environment effects include the choice of altitude which reduces the exposure, choice of materials which are resistant to chemical degradation and exhibiting high sputtering threshold, the use of coatings to protect surfaces, orienting sensitive surfaces and devices away from the ram direction, and reducing aerodynamic drag by reducing the space vehicle cross section.

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Micrometeoroid and Orbit Debris [Loftus97] The naturally occurring background of particles and objects present in the near-Earth environment are termed micrometeoroids. The man-made component of objects present in this environment is orbit debris. The primary concern from both micrometeoroid and orbit debris presence is the physical damage resulting from impact with the spacecraft. Even though the size and mass of these objects is relatively small, they produce profound consequences through hypervelocity impact effects. The micrometeoroid flux is episodic, as evidenced by annual encounters with Perseid and Leonid populations. The primary sources of debris have been explosions in space (unstable propellant at endof-life, breakups, and collisions with orbit debris), solid rocket fuel particulates, and surface erosion particulates (paint chips, etc.). All of the launch organizations have made modifications to preclude future inadvertent explosions due to residual propellants. Current space operators have initiated voluntary efforts to protect the future space environment. They have adequate incentive to follow through on these initiatives; it is their assets which are at risk. Due to their origin, orbit debris is present in the most often used orbits, and will impact spacecraft mainly in the ram direction, with velocities which are less than micrometeoroids. The orbit debris population is influenced by the solar cycle through increased aerodynamic drag effects. Mitigation provisions for the micrometeoroid and orbit debris threat is to choose altitude and inclination orbit architecture with minimal presence of orbit debris, locate critical devices and structures away from the ram direction, and the use of a layered “bumper” structure to protect critical elements.

4.0

Space Radiation Effects on Devices and Technologies

The interaction of the environment described in the previous section with devices used in the implementation of systems results in long-term effects which produce degradation in performance and may potentially induce component failure over the mission life. Long-term mission integrated consequences include total ionizing dose and displacement damage dose effects on devices. Single event effects occur due to the traverse of a single energetic particle through sensitive device structures. Single event effects may impart or enable permanent changes and destructive damage to devices, or may result in non-destructive but transient effects which perturb normal device operation.

4.1

Mission Integrated Effects

4.1.1

Total Ionizing Dose [Dressendorfer98]

Total ionizing radiation effects result from the interaction of charged particles or photons having sufficient energy to break atomic bonds within device materials, creating electron-hole pairs via ionization. The amount of ionization is expressed as the total dose absorbed over the exposure (mission) in the device material, expressed in units of rad(SiO2) or other appropriate units of rad(material). Total ionizing dose effects predominantly occur in the material used in

V-19

the operation of active devices (MOSFETs), and in oxides used to insulate, isolate, or guard active device structures. In MOS transistors, trapped charges and interface traps result in changes in threshold voltage, Vt. Magnitude of the threshold voltage shift has been shown to exhibit power law dependence on oxide thickness. Modern active device structures fabricated using gate oxide thickness <10 nm exhibit significant reduction in the changes in threshold voltage of the active transistor when exposed to total ionizing dose. Although device scaling also results in reduction of field oxide thickness, present thickness of field oxide and trenches provide ample opportunity for charge trapping. Leakage currents associated with edge effects on transistors and through guarding structures produce the majority of total ionizing dose effects in modern MOS integrated circuits. Effects due to the active device interface with buried oxides used in the formation of silicon-on-insulator (SOI) structures are also important. Although MOSFET device structures are items of most obvious concern, oxides used in guarding and in insulating layers above bipolar device structures may be affected by ionizing dose, resulting in changes in the performance of certain bipolar devices. The discovery of enhanced low dose rate sensitivity (ELDRS) in bipolar devices exposed at very low dose rates has resulted in the requirement to consider such effects in assessing the suitability and performance of candidate technologies and devices.

4.1.2

Displacement Damage Dose [Dressendorfer98]

Energetic protons, electrons, and heavy ions also create damage in semiconductor materials by displacing atoms by collision with lattice nuclei and through subsequent collision of the recoil atom with other lattice atoms. The result of this process is the creation of interstitial silicon and vacancy pairs which act as recombination and trapping centers. This displacement damage can reduce minority carrier lifetime, change majority carrier charge density, and reduce carrier mobility, all of which lead to changes in the electrical performance characteristics of devices. Silicon bipolar device gain may be affected by bulk displacement damage; however, narrow base widths used in modern high frequency devices decrease the level of susceptibility. Most affected are solar cells and opto-electronic devices. Displacement damage can reduce the light output of LEDs and semiconductor lasers; photo detectors and solar cell collection/conversion efficiency may be reduced by the presence of bulk displacement damage.

4.2

Destructive Single Event Effects

4.2.1

Single Event Latchup and Snapback

Single Event Latchup (SEL) is the condition which results from the activation of a parasitic bipolar device structure which is present in bulk CMOS semiconductor device structures. The four-layer device structure operates in a manner which is similar to a siliconcontrolled rectifier device. Charge deposited by the passage of a single energetic particle results in the injection of sufficient current to turn on the parasitic latching mechanism; sustaining drive current must be provided by the structure. High current levels and resultant thermal stress present in the latched condition may result in catastrophic damage to the device. Small, V-20

localized regions of the device may experience latchup, termed a microlatchup condition. Compromised logic function of the circuitry involved in the latchup condition is probable. Recovery from a semiconductor latchup condition requires reduction of the device voltage to less than the sustaining or holding voltage for the latchup condition. Single Event Snapback (SES) is a regenerative current mode resulting from the presence of the parasitic bipolar transistor within the MOS device structure. Snapback is a reduction in the breakdown voltage of the parasitic transistor caused by the injection of minority carriers from the source. Although typically resulting in less current than latchup occurrence, the loss of proper operation of the transistor will result in compromised function of the circuit involved.

4.2.2

Single Event Burnout and Gate Rupture [Allenspach96] [Johnson96]

Single Event Burnout (SEB) is a destructive condition which results in damage to the source-drain region of n-channel power-MOSFET devices. SEB is triggered by the passage of a heavy ion through a double-diffused power-MOSFET structure which is biased in the off condition. Transient current generated within the device turns-on the parasitic bipolar junction transistor; regenerative feedback increases collector current to the onset of second breakdown, resulting in catastrophic device failure. The regenerative current results from avalanche generated hole current in the collector region. P-channel power-MOSFET devices have not exhibited susceptibility to single event burnout, due to the reduced level of avalanche generated current which is necessary to provide regenerative operation. Single Event Gate Rupture (SEGR) is a destructive condition which results in catastrophic damage to the gate insulator in the power MOSFET devices. Both SEB and SEGR result from the passage of a heavy ion, but the mechanisms responsible for these effects are quite different. SEGR is caused by heavy ion traverse through the gate-to-drain overlap region of the device (neck region) producing sufficient accumulation of charge at the silicon to silicon-dioxide interface to exceed the breakdown voltage of the oxide, resulting in localized dielectric breakdown. Subsequent gate-to-drain conduction further damages the structure resulting in catastrophic failure of the device in the form of a gate-to-drain short.

4.2.3

Single Event Hard Error and Single Event Dielectric Rupture [Katz97]

Single Hard Error (SHE) is the condition in which a single permanent fault is created through damage produced by the passage of a single energetic particle through sensitive device structures. One mechanism observed to be responsible for SHE is termed micro-dose, this involves the introduction of sufficient ionization within the gate oxide of a transistor to create a localized region of total ionizing dose effects. The term single hard error is most often used in reference to the occurrence of micro-dose in which annealing often results in recovery of device operation. A second mechanism observed to produce SHE, Single Event Dielectric Rupture (SEDR), is similar to single event gate rupture in power MOSFETS. In this mechanism, oxide-nitrideoxide antifuses used in field-programmable gate arrays have been shown to be susceptible to heavy ion induced failure. V-21

4.3

Single Event Upset and Transients

4.3.1

Single Event Transient and Upsets in Digital Devices

Single Event Transient (SET) is a voltage waveform impressed upon a signal within a device due to the collection of charge generated by the passage of an ionizing particle through the device structure. Single Event Upset (SEU) is a change of state in digital logic devices produced by a circuit level response to a single event transient. Single event upset is typically referred to as a bit level phenomenon, expressed in units of upsets/bit-time. The term single event upset is used in reference to space applications; soft error (or soft error rate (SER)) is the term used by most terrestrial applications. Multiple Bit Upset (MBU) is the condition in which two or more errors (SEUs) are produced by the passage of an ionizing particle through the device structure. This may occur due to the particle traversing sensitive volumes within the circuitry of more than one bit cell, or due to conditions on control or clock signals which result in more than a single bit being upset.

4.3.2

Single Event Transients in Analog Circuits

As described above in digital devices, Single Event Transient (SET) is a voltage waveform impressed upon a signal within a device due to the collection of charge generated by the passage of an ionizing particle through the device structure. The transient propagates through device circuitry appearing as a pulse on the output of analog microelectronic devices.

4.3.3

Single Event Functional Interrupt [Koga97] [LaBel98]

Single Event Functional Interrupt (SEFI) is a component level phenomenon describing the condition in which the function of the device is compromised as the consequence of an SEU occurring within the component. The single event upset typically affects the control logic within the device causing device mode or programming control to be modified, or device test modes to be invoked which alter the overall function of the component. SEFI has been observed in microprocessors, electrically erasable programmable read only memory (EEPROM), dynamic random access memory (DRAM), and digital signal processor (DSP) devices.

5.0

Systems Engineering for Space Radiation Environment Compatibility

Procedures for assuring design compatibility with the space radiation environment consist of understanding the environment, specifically describing the environment at the level of interaction with sensitive devices and technologies, understanding the effects produced by the environment on devices, assessing the consequences of component level effects on system operation, and the development of application level strategies to assure successful system operation. Most system engineering activities rely upon component selection and derating to

V-22

assure tolerance to mission integrated total ionizing and displacement damage dose effects. Similarly, destructive single event effects are prevented from occurring by selection of components or application conditions which prevent the occurrence of catastrophic single event effects. Single event upset and transient conditions are addressed by a spectrum of fault tolerance solutions; most of the specific techniques will be identified in section 6.0. The application of fault tolerance strategy requires knowledge of the effects, rate of occurrence, and the consequences which faults present to the operation of the system. Component testing, methods to estimate rate of occurrence, and knowledge of the dynamic nature of the environment with regard to the occurrence of faults are necessary to develop a fault tolerance strategy.

5.1

Tolerance to Mission Integrated Effects [Kinnison98][Fleetwood95]

Mission integrated effects on components and technologies used in space systems include total ionizing dose and displacement damage dose effects; description of these processes was briefly indicated in Section 4.1 and in-depth discussion has been provided in the other sections of this short course. Design and development activities directed towards assuring adequate tolerance to mission integrated effects consists of defining the environment external to the spacecraft, transport of the particle spectra and calculation of the mission integrated dose levels for component locations within the electronic assemblies, evaluating candidate devices and technologies for adequate tolerance and characterization of performance degradation, and establishing provisions which assure that adequate tolerance exists in the total population of devices to be used in systems. Figure 5-1 indicates the total ionizing dose levels versus equivalent aluminum shielding thickness for the geostationary and two low earth orbits. Apparent in this figure is the increasing severity of the environment with increasing orbit altitude for the low earth orbits and the effectiveness of shielding towards attenuating the effects of the environment. The low earth orbit total ionizing dose contribution is dominated by trapped proton effects for values of shielding thickness which are typical of most payload microelectronics devices; the benefits of additional shielding towards attenuating the dose is marginally effective. For locations having shielding conditions less than 2.5mm the dose level is dominated by the trapped electron contribution; the use of additional shielding is effective in reducing the total ionizing dose in these locations. The environment for geostationary satellite applications indicates the benefits

Dose [rad(Si)/10_year_mission]

1E+08

1E+07

Geosta tiona ry 1E+06

1400 km 1E+05

750 km 1E+04

1E+03 0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

Shielding [mm| Al]

Figure 5-1. Total Ionizing Dose for LEO and GEO Applications

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which shielding provisions can achieve in attenuating the severity of this environment. Two issues of importance in considering the total ionizing dose in this environment are the potential of dose enhancement attributable to the interaction of energetic electrons with shielding materials, and the contributions to total ionizing dose which arise from solar particle events. Having established mission integrated dose levels for components to be utilized in systems, design for compatibility with the environment consists of selecting technologies and devices which exhibit adequate levels of tolerance, and developing applications design guidelines which consider any degradation in component performance which will occur over operating life due to mission integrated dose effects. Consideration must be given to the differences in radiation test environment utilized to evaluate component performance and tolerance, including delivered dose rate versus on-orbit dose rates, and the particle/photon species used to emulate the space environment. Dose rate effects are particularly important in light of enhanced low dose rate sensitivity (ELDRS) in bipolar devices, and the potential that MOS devices often exhibit increased tolerance under low dose rate conditions. The selection of components evidencing minimal performance degradation and the development of valid derating guidelines for use in applying devices which exhibit performance degradation are also very important considerations. The underlying theme in assuring mission integrated effects tolerance is to test components as you plan to use them, and to procure components which will evidence the same characteristics as those which were tested. Information presented in several papers indicate concern over the effects which packaging techniques / materials and reliability assurance (burnin) screening may have on total dose tolerance; most programs require that packaging and screening provisions planned for flight devices be present in total ionizing dose test devices. The procurement plan for devices must provide adequate assurance that devices utilized in flight systems do not exhibit reduced tolerance from those which were evaluated for suitability. Radiation design margin strategies require lot surveillance procedures where necessary to assure that individual production lots continue to exhibit adequate tolerance.

5.2

Mitigation of Destructive Single Event Effects [LaBel961] [Layton97]

In contrast to single event upset and transient mitigation, destructive single event effects may or may not be recoverable depending on the individual device’s response. Hardening from the system level is difficult at best, and in most cases, not particularly effective. Nonrecoverable destructive single event effects such as single event gate rupture and burn-out catastrophically damage devices in a manner which completely compromises operation of the circuit. Single event latchup occurrence may be catastrophic in a specific device, or a microlatch condition may exist in which the functionality of the device is compromised in a fashion which requires circumvention as a recovery provision. Microlatch may be very difficult to detect; the anomalous current consumption may be within the normal operating range of the device. Latchup of devices often exhibits differing current signatures depending on the region of the circuit which is affected. Characterization testing must be capable of identifying each of these conditions in order to set valid criteria for the detection mechanism. Consideration may be given to design at the module applications level for protection, detection, and recovery provisions, or the procurement of modules which incorporate such features within multi-chip V-24

modules. Latchup Protection Technology (LPT) circuitry from Space Electronics Inc., for example, includes current limiting protection to prevent device damage due to latchup occurrence, detection of the increase in current, shutdown of the device for the required interval, and return of the powered device to normal operation within specially designed multi-chip modules. Characterization testing of the device requiring protection must identify the current signature which is indicative of SEL occurrence, the shutdown time necessary to ensure recovery from latchup, and the current limiting value necessary to preserve device reliability. The elimination of susceptibility to Single Event Burnout (SEB) requires the use of nchannel power-MOSFET devices from manufacturers which are designed and processed to prevent SEB. Applications techniques require derating of the drain-to-source voltage by an amount sufficient to achieve immunity, or to utilize p-channel power-MOSFETS which do not exhibit susceptibility. Elimination of the susceptibility to Single Event Gate Rupture (SEGR) requires the use of power-MOSFET devices from manufacturers which are designed and processed to reduce susceptibility. As in SEB, application techniques to prevent SEGR also require derating of the drain-to-source voltage by an amount sufficient to achieve immunity. Elimination of failure due to the presence of micro-dose or single event dielectric rupture induced Single Hard Errors (SHE) requires testing to determine device susceptibility. The selection of alternative devices which do not exhibit such susceptibility is an obvious method for eliminating this potential failure mode. Application techniques such as the fault masking provisions discussed in Section 6, error detection and correction coding or spatial redundancy, enable proper device operation in the presence of failed circuit elements.

5.3

Analysis of Single Event Upset Rates and System Effects

The analysis of single event upset rates consists of characterizing component susceptibility, establishing particle flux models for the specific orbit (including the severity of the environment at specific times and locations), and folding the energy or linear energy transfer dependent device characteristic with the appropriate particle spectrum to produce an estimate of component level SEU rate.

5.3.1

Component Single Event Upset Characterization [Petersen97] [Stapor95]

The first element in establishing an estimation of the rate of occurrence of single event effects is characterizing the susceptibility of devices which are utilized in implementation of the system. Ground based measurements using particle beam accelerators are used to produce energetic particles which travel through the device structure similar to particles in the space environment. In the case of heavy ions, the energy of particles used in ground based testing is significantly less than that of particles found in space. By utilizing particles of equivalent LET an approximation of the charge deposition characteristics is realized. Differences in the dimensions of track structure and the inability to utilize a wide diversity in the direction of propagation of the particle through the device structure are sometimes areas of concern in how ground based testing simulates the space environment. In the case of energetic protons, the

V-25

energy available from test facilities approximates the energy of protons in the space environment. The single event upset characteristics of devices are represented using the measured number of upset events, and the particle fluence used to produce the events, to calculate a cross section. Plotting of the measured cross section data and fitting the appropriate curve to the measured cross section values over a range of LET/energy produces the device single event upset characteristic. Both heavy ion and proton characteristics exhibit similar features of a threshold value in LET/energy and an increasing cross section which asymptotically approaches a maximum value. In characterizing the single event upset susceptibility of components, it is important to utilize sufficient particle fluence to produce a statistically significant result. The statistical uncertainty in the measured cross section for some measured upset counts is: Upset Events Uncertainty In σ 1 ± 100% 2 ± 71% 3 ± 58% 5 ± 45% 10 ± 32% 20 ± 22% 50 ± 14% 100 ± 10% 1000 ± 3% In addition to the statistical uncertainty in the measured cross section at various energy/LET values, consideration must be given to the changes in single event upset characteristics which will result from device operating voltage and temperature conditions in the application, distribution of component characteristics across manufactured population of devices, and the changes to device susceptibility which could result from total ionizing dose accumulation. Distribution of part and application conditions potentially impart a distribution about a mean value; total ionizing dose accumulation often causes the single event upset susceptibility of devices to worsen over mission life. In characterizing a device susceptibility to both heavy ions and protons, it is important to consider which segments of the cross section versus LET/energy curve have the dominant influence upon the rate calculation. For proton induced single event upset estimation, the portion of the energy spectrum between 40 MeV and 60 MeV results in the most significant contribution to the overall SEU rate, due to the population of protons of this energy. For this reason, it is important in proton susceptibility characterization that adequate attention be paid to establishing valid measurement of the cross section in this segment of the cross section versus energy curve. In the case of heavy ion single event upset estimation, the declining population of particles with increasing LET in the saturation region results in the most significant contribution to SEU rate coming from the larger population of particles having LET in the region slightly above threshold. Device single event upset characteristics are usually expressed in terms of the parameters for standard equations used as best-case fit to the measured data. In the case of heavy ion characterization, the Weibull curve and the four parameters which define this shape are most frequently used. There are other representations such as the cumulative log normal distribution V-26

which also provide good fit to measured data. An exponential distribution has also been shown to provide reasonable fit to the device characteristic for some devices. In the case of proton characterization and single event upset rate prediction, the semi-empirical approach of the two parameter Bendel model is used. While it is important to achieve the best possible statistics in measurements of device characteristics, it is also important to consider that the primary contributor to uncertainty in the rate estimation is the particle environment definition for both heavy ions and protons. The space environment models are often ascribed to be factor of two models.

5.3.2

Environment Models [Barth97][Dyer98][Daly96][Huston98][Tylka97] [Gussenhoven97] [Gussenhoven93] [Chenette94] [Majewski95]

Most analysis of the effects of trapped particles on earth orbiting satellite systems has been performed using NASA trapped proton and electron models, AP8 and AE8, respectively. The AP8 model was released in 1976, reflecting the analysis of data obtained from satellite measurements between 1958 and 1970. The AE8 model was released in 1983, reflecting the analysis of data obtained from satellite measurements between 1959 and 1978. The models are empirical data sets, and provide separate models for the solar minimum and solar maximum phases. The flux values represent long term average conditions over the entire interval of the indicated phase of the solar cycle. The extremities encountered at the peak (maximum or minimum) of the phase and short term variance in the particle flux is not represented. An uncertainty factor of two is considered applicable for these models, and short-term excursions from the model averages are indicated to possibly reach an order of magnitude. A number of issues have been identified regarding the use of these models, including the particle flux levels and spectra at low altitudes, secular variation of the geomagnetic field since release of the models, and the inability to represent the anisotropic characteristic of particle flux. Slow changes in geomagnetic field conditions result in the South Atlantic Anomaly (SAA) location presently residing approximately 6.5° west of the position indicated by the NASA models. This characteristic is of no importance in assessment of mission integrated dose; however, it can be of importance to missions which must assess system effectiveness and quality of service provided to users in this region, and in developing fault avoidance provisions for SAA traverses. Particularly for low altitude missions, understatement by the model of the trapped proton population by factors ranging from 1.55 to 2.30 have been indicated. Other modeling of anisotropy in the environment indicates the possibility of east-west ratios exhibiting factors between two and seven at low altitudes in the SAA region. This characteristic is important to the consideration of the benefits which shielding provide in the transport of particle spectra to the device or component level. The trapped electron model, AE8, has been shown to over-predict the inner belt region trapped electron flux; the error attributable to increased levels remaining from high altitude nuclear testing in years prior to the NASA model development. The population of trapped electrons in the outer belt region are more accurately modeled by AE8, but the dynamic nature of this environment resulting from injection events must be considered. The NASA Space Environments and Effects (SEE) Program has recently released the NOAAPRO model which is intended to address the major shortcoming indicated above for the

V-27

AP8 model in the altitude range of 250 kilometers to 850 kilometers. This model is not intended to replace AP8, but moreover to provide enhanced modeling capability for low orbit missions. Data from the CRRES and APEX satellite missions have been used to produce additional models of the trapped radiation environment which are available to the analyst for assessment and modeling of the charged particle environment. Galactic cosmic ray heavy ion particle flux modeling typically utilizes the models incorporated into CREME. The uncertainty in these models is again expressed as a factor of two. CRRES mission data has been used to produce an additional model, CHIME, which is also available to the analyst for assessment and modeling of the GCR environment.

5.3.3

Performing Rate Estimate Calculations

A number of methods and analysis software tools exist for performing single event upset rate calculations. All of the methods require characterization information about the device single event upset susceptibility, and the tools typically provide a set of models for the space environment. In addition to the cross section versus LET curve (or curve fitting parameters for standard equations used to describe this characteristic), additional information about the dimensions of the sensitive volume are necessary for some of the heavy ion single event upset models. Measurements at a series of angles of particle beam incidence enable the determination of sensitive volume thickness, and to estimate the dimensions of the funnel region. Correlation of on-orbit measurements of single event upset rate with predictions which were made using the methods and procedures indicated above have shown good agreement in some instances; others were off by as much as an order-of-magnitude. In general, proton induced SEU rates have been understated by the analysis, probably due to the known propensity for AP8 to under-predict trapped proton population at lower altitudes. The general characteristic of heavy ion induced SEU has been to over-estimate the frequency of occurrence. New models of trapped proton flux, and/or the application of factors or ratios by the analyst to AP8 modeled predictions, revised CREME96 models for heavy ion flux, and improved ground based characterization of device susceptibility should enable acceptably accurate prediction of device level effects.

5.3.4

Effects and Consequence on System Operations [LaBel962]

The ability to examine the effects and consequences which single event effects present to the operation of systems is a difficult undertaking. It is usually informative to classify system level effects into those consequences which influence the data within a payload or spacecraft and those which affect the control operations. The effect of a single event upset in the storage of user data in an ASIC register, processor memory, or solid state recorder may be easily understood; a bit error in the data which is delivered by the satellite. The consequence of the bit error may be near zero if the error contribution is less than the bit-error-rate specified for the system. The consequence may be degraded quality of service, possibly requiring detection and correction mitigation, but the consequence is unlikely to result in outage and degradation in the availability of the system to users. Corruption in the control process can result in fairly benign

V-28

consequences, such as limited loss of user data, to a crash of the system resulting in total loss of user access and compromised availability of the system to users. The ability to examine the propagation of individual single event upset occurrences to achieve an understanding of the system level effects may require engineering functional analysis, simulation, fault injection, and statistical analysis to acquire a sufficient level of understanding. This activity is similar to the task of validation and verification of the adequacy of fault tolerance provisions which will be discussed in section 6.7.

5.4

Spatial and Temporal Variation in the Charged Particle Environment [LaBel962]

For most satellite orbit configurations the charged particle environment exhibits significant variance as a function of position within the orbit and at various times over the course of the mission. These dynamic characteristics of the environment are typically referred to as spatial and temporal variance respectively. In defining the requirements for system operations and for performing single event effects rate predictions, these variances must be reduced to a set of discrete conditions. Temporal variance connotes both the short-term and long-term variance in the severity of the charged particle environment. Long-term variance usually refers to issues such as the differences in particle populations between solar maximum and solar minimum conditions. Short-term variance captures the notion of average day particle population, versus the extreme populations present during peak solar particle event conditions. The average day conditions are often referred to as the normal environment in which a system must operate, and performance specifications such as availability or other measurable metrics of system performance must be assured under these conditions. Often the more severe of the long-term environments, solar maximum or solar minimum, are used to define this environment. The extreme condition present during solar particle event occurrence is usually defined as the worst-case environment and different system performance metrics may be established for these intervals. These system performance requirements are based upon mission requirements and the expected frequency of occurrence of the extreme condition. Spatial variance comprehends the changes in the severity of the charged particle environment as a function of the satellite position within its orbit. The concentration of proton induced single event upsets during a low earth orbit system’s traverse through the South Atlantic Anomaly region, and heavy ion single event effects during polar traverse of highly inclined orbits are typical examples of spatial variance. Figures 3-2 and 3-3 provide description of the flux contour levels of trapped protons present in the SAA region. Section 3.5 provided description of the shielding effects which the earth’s geomagnetic field provide to galactic and solar heavy ions, resulting in little shielding effects over the high latitude polar regions and significant shielding at lower latitudes. Figure 5-2 indicates the single event upset rates estimated for a memory device exhibiting SEU susceptibility to both heavy ions and protons in a 750 kilometer near polar orbit. This figure indicates the wide spatial variance in SEU rate for orbits which traverse through the SAA region and for those which do not, and for both high latitude polar regions and low latitude segment of the orbit. Indicated in this figure is the overall orbit average single event upset rate which represents the long term average over numerous orbit V-29

1E-03

Trapped Proton

Upsets (upset/device_sec)

1E-04

Orbit Avera ge 1E-05

Galactic Cosmic Heavy Ion

1E-06

1E-07

1E-08 0

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

5500

6000

Time (sec)

Figure 5-2. Single Event Upset (SEU) Rate, One Orbit, SAA Traverse

periods. The extremely large range in single event upset rates and the limited value which orbit averaged SEU rate provides in establishing fault tolerance design requirements are indicated in this figure. The propensity for SEU events to occur in the SAA region and during polar traverse establish requirements for the effectiveness of fault mitigation and tolerance strategies for low earth orbit systems.

6.0 6.1

Fault Tolerant Systems Engineering

System Reliability and Availability [Wood97] [Somani97] [Nelson90]

The two most common expressions of a system’s ability to tolerate failure are reliability and availability. Reliability, R(t), is the conditional probability that a system will remain operational (or can be restored to an operational state) over the interval 0 to t, normally the duration of the mission. Availability, A, is defined as the probability that a system is operational at any particular time, and expresses the fraction of time a system is operational.

R(t) = e-λt

λ = 1 / MTBF

Mean Time Between Failure

A = µ /(λ+ µ)

µ = 1 / MTTR

Mean Time To Repair/Recover

A system with high reliability (evidencing a low mean-time-between-failure) may exhibit unacceptable availability if the mean-time-to-repair/recover is unacceptably long. A system with high availability may in fact fail; if the mean-time-to-repair/recover is suitably low, acceptable availability may be achieved.

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Although availability is expressed as the percentage of the time the system is available to users, developing the requirement which is specified is typically based on outage frequency, outage duration, and ultimately on the cost implications of users being denied access to the system. Although degraded modes and conditions of systems create situations which infer partial or limited availability, the bottom line is that the system is available if the customer says that it is. The customer will declare that it is not available when denied access or provided a quality of service less than fully specified performance. Availability is a system characteristic pertaining to end-to-end operations which relies upon all system resources including space segment, ground operations, and user equipment. Departures from perfect system operation which contribute to availability are allocated; the consequences, detection, and recovery of space segment payload operations due to the occurrence of single event upsets receive only a portion of this allocation. Availability is often expressed as a steady-state value, either as the probability that the system is operational at any random time, or as a given amount of downtime over a specified interval. Steady-state availability is computed as the mean-time-to-failure divided by the sum of mean-time-to-failure and mean-time-to-recovery. Statistical mean values of system failure and recovery are often used in system evaluation. However, statistical mean values can be misleading, given the order-of-magnitude changes which are present in the spatial and temporal variances in the charged particle environments that produce single event upsets and transients. Previous paragraphs have described the non-uniformities which heavy ion particle flux in high latitude orbit segments and the concentration of trapped proton flux in the SAA region present to Low Earth Orbit (LEO) systems, and the short term increases in particle flux resulting from solar events and geomagnetic field disturbances. Consideration must be given to the availability and quality of service which are provided to specific regions of the earth and for short periods of time in which increased particle flux levels produce increased propensity for faults and resultant detection and correction / recovery actions.

6.2

Fault Tolerant Systems Design [Somani97] [Avizienis971] [Nelson90]

The general subject of fault tolerant systems addresses numerous causes of faults, including incorrect specifications, design errors, manufacturing defects (and inadequate testing to detect them), human operator actions (accidental and intentional), component damage or failure, and interaction with the operating environment. A fault may be classified by its nature, duration, and extent; the duration of a fault may be transient, intermittent or permanent. The context in which fault tolerance techniques are discussed herein addresses transient faults introduced by single event upset effects due to the operating environment. In this sense we are addressing a subset of the broader subject of system fault tolerance, that of transient effects. Not related to the subject of this short course or NSREC conference are the other sources of faults which are indicated; however, these considerations should be addressed in the context of the system design, development and manufacture of high reliability space systems. Prevention of component failure due to total ionizing and displacement damage dose effects or due to destructive single event effects was discussed in a previous section. The language of fault tolerant systems identifies a fault as the initiating event (in this case a charged particle induced single event upset or transient); errors are the undesired states caused V-31

by the fault. If error detection and recovery do not take place in a timely manner, a failure could occur that will be manifested by the denial or an undesirable change in the capability of the system to provide service. Fault tolerance is the capability of a system to recover from a fault or error without exhibiting failure and compromised availability. A fault in a system does not necessarily result in an error; a fault may be latent in that it exists but has not resulted in an error; the fault must be sensitized by a particular system state and input conditions to produce an error. A complete fault tolerant system design requires careful study of design, causes of failure, characteristics of the failures, and system response in the failed condition. The principles of fault tolerant systems include fault avoidance, fault masking, detection of erroneous or compromised system operation, containment of error propagation, and recovery to normal system operations. Component complexity affects the ability to accomplish error detection. Errors occurring in data storage elements, such as registers or memory, and during transfer over buses or interfaces are more easily detected than errors occurring in complex devices such as microprocessors, microcontrollers, and high complexity application specific (ASIC) devices. Consideration must also be given to the likelihood that faults will occur as single, statistically independent events, or whether multiple faults may be present due to high charged particle flux or multiple faults being introduced by the passage of a single charged particle through sensitive device structures. As with all system engineering and design processes, there exist images of both bottomup and top-down approaches to the practice of fault tolerance. The bottom-up approach entails designing an infrastructure of autonomously operating fault tolerance provisions within individual components and subsystems and integrating this infrastructure with limited global fault tolerance provisions. The top-down approach allows a system to be built using off-theshelf components that have little or no fault tolerance provisions, and integrating the system with a robust global monitoring provision to implement fault tolerance. Examination of both approaches makes a case for the long-range merits of the bottom-up approach, providing detection and recovery at the lowest level possible. The ability to detect at the lowest level possible, with error containment to the minimal number of components and subsystems, enables simpler and more effective recovery provisions. The prevailing practice is best described as middle-out in which fault tolerance provisions are included in components where possible and cost effective, and applications techniques are utilized to implement fault tolerance provisions where component level capability does not exist or is not cost effective. The development of fault tolerance in systems requires the inclusion of considerations that address faults, errors, and detection and recovery provisions in the specification, architecture development and system partitioning, subsystem design, system integration, validation and verification, and modification activities. System requirements and specifications must address mission phases, performance and availability requirements, operational modes, and external support capabilities which relate to the fault tolerance characteristics of the system. Support provisions from external agents such as ground operational intervention, including periodic or on-demand activities in support of diagnosis and recovery actions are defined. The acceptability of different modes of operation including reduced capabilities and degraded levels of service, safe shutdown, and emergency modes of operation must be defined. System architecture and partitioning defines error containment boundaries, establishes the system-wide strategy for coordinated error detection and recovery, and the redundancy provisions which support fault tolerance are determined. Establishing a fault tolerance hierarchy defines detection and recovery functions for individual local subsystems, shared functions over a V-32

group of subsystems, and system-wide or global functions. Utilization of redundancy methods, including hardware redundancy (spatial) or time redundancy (temporal) in the error detection and recovery processes may be utilized. Classical fault tolerant systems utilize design diversity as a provision for detection and recovery for specification and design defect related fault conditions. If present to address these fault classes, they represent useful redundancy for detection and recovery from single event upset and transient fault conditions. Fault tolerant subsystem design includes error detection and recovery provisions for faults within the subsystem as well as support for interfaces with other subsystems and global detection and recovery provisions. Detection and recovery may be either concurrent with normal system operation or preemptive in which case normal system operation is suspended until completion of the recovery activities. Error detection provisions must be capable of identifying undesired states caused by single event upset or transient fault conditions, including the presence of dormant or latent faults in spare or redundant circuitry and stored information. Correction provisions may be real-time; recovery operations may be either backward (rollback to a previous error-free state) or forward, constructing a valid error free new state from existing protected information. The recovery sequence includes the identification and removal of errors and restoration of valid subsystem states and, where possible, validation of the completion of successful recovery operation. Techniques and methods which accomplish fault tolerance using hardware techniques with very localized detection, containment, and correction or recovery provisions are termed fault masking; many of the techniques which have been classically used in single event upset mitigation are considered to be in this category. It must be demonstrated that adequate testability is provided to detection and correction/recovery provisions, ensuring that manufacturing or component defects do not exist in systems produced for payload use which compromise the operation or performance of fault tolerance provisions. Furthermore, circuitry added to enable such testability must be examined for the propensity to introduce new fault conditions or to exacerbate the rate of occurrence of on-orbit faults. System integration and validation and verification activities must include the ability to establish that the design supports the qualitative goals and that quantitative requirements established for the fault tolerance provisions are achieved. Methods and provisions must be utilized in subsystem evaluation and for various levels of system integration whereby fault injection capability is utilized to verify the performance of detection and correction/recovery provisions. Qualitative evaluation of fault tolerance design provisions include the use of formal and heuristic methods, test, and experimentation to verify the absence of design faults, to demonstrate consistency with system security provisions, and to demonstrate the operability of detection and recovery provisions. Quantitative evaluation includes the use of fault injection to obtain information about fault coverage, execution time performance of recovery provisions, and the effects which faults present to system operations when detection and recovery provisions are not totally effective. Prediction of availability, frequency of system mode change, and the frequency and procedures for the use of external agent support for recovery operations must be provided.

6.3

Fault Avoidance

Fault avoidance addresses all endeavors that seek to eliminate the occurrence of specific fault conditions, and to reduce the frequency of occurrence of the remaining faults. In the V-33

context of faults arising from single event upset caused by exposure to the energetic charged particles in the space environment, avoidance addresses reduction in the severity of the environment (through choice of orbit architecture and shielding), reduction in charge generation and collection in sensitive device structures, and elimination or reduction of circuit response to collected charge.

6.3.1

System Operations and Orbit Architecture [LaBel962]

Selection of the orbit architecture identifies the opportunities to present to system engineering, options which exist to reduce the severity of the environment through selection of orbit altitude, inclination, and type. System operations considerations include the method of fault avoidance achieved by not performing critical tasks in segments of the orbit in which single event effects are more probable due to elevated particle flux levels. Programming of nonvolatile memory in a system vulnerable to proton induced single event effects during South Atlantic Anomaly traverse, and the conduct of critical operations in a heavy ion susceptible system at high latitude and during solar events are undesirable system operating provisions. Fault avoidance shall define system operating constraints which minimize the opportunity for critical faults to occur. Figure 6-1 describes the integral flux of galactic cosmic ray heavy ions as a function of orbit altitude and inclination. The effect of the earth’s geomagnetic shielding results in low levels of exposure for altitudes out to 6000 kilometers and inclination less than 40°; however, few telecommunications systems operate in this orbit. The exposure to increased levels of heavy ion flux at high inclination angle is shown.

Figure 6-1. Galactic Cosmic Ray Flux [Petersen97] The dependence of the proton population having energy greater than 30 MeV as a function of altitude and inclination is indicated in Figure 6-2. The geographic location of the trapped proton population in the South Atlantic Anomaly (SAA) region was indicated for orbit altitudes of 500 kilometers and 1000 kilometers in Figures 3-2 and 3-3 respectively. V-34

Figure 6-2. Trapped Proton Flux (>30 MeV) [Petersen97]

From these figures the severity of the environment in regard to the propensity to experience charged particle induced single event upsets is indicated. As a fault avoidance provision, systems engineering trades regarding orbit architecture and the establishment of operating constraints in which critical operations must be performed during low SEU rate segment of the orbit may be established.

6.3.2

Effectiveness of Shielding [Smith94] [Petersen97]

Depending upon the location of critical single-event-upset susceptible devices within the spacecraft, various levels of shielding are provided by the structure and other materials. Consideration of the shielding present, the potential to position sensitive devices in more highly shielded locations within the spacecraft, and the benefits available through utilization of localized additional shielding for sensitive devices may be addressed. Figure 6-3 indicates the attenuation provided by various levels of shielding for the solar minimum galactic cosmic ray heavy ion integral LET spectrum. Very limited attenuation of the GCR spectrum is provided over a significant range of shielding values presented in this figure. Moving of sensitive components and the use of additional shielding materials as a provision to reduce GCR single event upset rate in sensitive devices affords little benefit. Figure 6-4 indicates the attenuation provided by various levels of shielding for the trapped proton spectrum present in the CRRES orbit. Figure 6-5 indicates the attenuation provided by various levels of shielding for the trapped proton spectrum present in a 1400 km, 50° inclined orbit. Attenuation of the integral spectrum at 10 MeV indicates that a shielding increase from 200 mils to 400 mils reduces the flux by 32% for the CRRES orbit, and 16% for the 1400 kilometer orbit. Shielding increase from 200 mils to 800 mils reduces the flux by 63% for the CRRES orbit, and 34% for the 1400 km orbit.

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Figure 6-3. Galactic Cosmic Ray Heavy Ion Integral Flux Spectra [Petersen97] 1.00E+03 9.00E+02 8.00E+02 200 mils Integral Flux [/cm²/s]

7.00E+02 400 mils 6.00E+02 800 mils 5.00E+02 2 in 4.00E+02 5 in 3.00E+02 2.00E+02 1.00E+02 0.00E+00 0

50

100

150

200

250

300

Energy [MeV]

Figure 6-4. CRRES Orbit Trapped Proton Integral Spectrum 2.50E+03

2.00E+03

Integral Flux [/cm²/s]

200 mils 1.50E+03

400 mils

800 mils 1.00E+03 2 in 5 in 5.00E+02

0.00E+00 0

50

100

150

200

250

300

Ene rgy [MeV]

Figure 6-5. 1400 km Orbit Trapped Proton Integral Spectrum

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Analysis of shielding conditions within the spacecraft must be performed to establish the distribution of solid angle percentage as a function of shielding thickness. Previous analyses of this type have shown typical shielding thickness of 250 mils on satellites, instead of the typical 100 mil value which is often specified. Spacecraft in development now and next generation systems are making use of thinner, stronger, and lightweight materials; analysis of the shielding conditions specific to the spacecraft under development must be performed. Some limited attenuation of proton single event upset rate is achievable by management of component location and the use of additional shielding; estimates range from 15% to 50% reduction in trapped proton induced SEU rate. No appreciable benefit is realized from consideration of such provision for galactic cosmic ray heavy ion induced single event upsets. 6.3.3

Mitigation of Charge Generation and Collection [Marshall951] [Marshall952][Mitsubishi99]

The traverse of energetic charged particles produces charge which is collected on circuit nodes, resulting in Single Event Transients (SET) and Upset (SEU). An ability to attenuate the generation of charge and to reduce the amount of collected charge serves to increase the LET of the particle required to produce SEU and to reduce the cross section of the device, both resulting in decreased SEU rates. Techniques directed at reducing collected charge typically rely on the ability to truncate the funnel dimensions and to reduce the carrier lifetime in the region below the sensitive volume. The use of insulating material for device isolation instead of reverse biased junction isolation results in reduced charge generation. Commercial manufacturers have demonstrated success in the reduction of alpha particle induced soft error rate through the use of retrograde well profiles. The increasing carrier concentration with increased distance into the well region results in reduced carrier lifetime and hence less charge collected from the region below the sensitive volume. Using a technique which incorporates reduction in charge collection through the use of thin epi and a buried layer below the sensitive volume and mitigation of circuit response by increasing critical charge, Mitsubishi reports mitigation of alpha particle soft errors and effective attenuation of terrestrial neutron induced upsets. A technique explored for the gallium arsenide (GaAs) HIGFET structure indicates that significant reduction in the cross section of devices could be realized from high particle fluence bombardment. The non-ionizing energy deposited in the structure serves to reduce carrier lifetime in the substrate through formation of recombination sites, which affects the backgating and bipolar mechanisms which are believed to dominate in GaAs FET devices. Reduction in device cross section by an order of magnitude was achieved by the deposition of 8.3 x 1011 MeV/g(GaAs) of non-ionizing energy, delivered by proton fluence of 1.8 x 1014 p/cm2. The radiation hardened characteristics of GaAs technology enabled tolerance to the 5 x107 rad(GaAs) total ionizing dose which was imparted at these fluence levels. A similar technique for achieving reduced carrier lifetime in the substrate through formation of recombination sites using low temperature grown buffer layers (LT GaAs) has shown the ability to provide immunity to single event upsets. The low temperature layer

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formation results in about 1% excess arsenic being introduced into the crystal which coalesces into precipitate sites which form very fast recombination centers. The material thus efficiently eliminates the charge enhancement mechanisms described above; test results exhibited SEU immunity up to maximum LET of 90 MeV_cm2/mg at particle fluence of 1 x107 particles/cm2. Identical devices fabricated without the LT layer exhibited threshold LET approximately 1 MeV_cm2/mg and an appreciable cross section.

6.3.4

Mitigation of Circuit Response [Vinson92][Rockett88] [Calin96] [Liu92]

Techniques to mitigate circuit response include provisions to increase critical charge, to suppress response by limiting circuit bandwidth such that no response is provided to the short collected pulse, and to provide circuit design provisions which block the propagation of pulses in memory cell feedback paths. Commercial SRAM manufacturers have utilized stacked capacitor structures to increase cell capacitance, decreasing the voltage transient due to collected charge, and also reducing the bandwidth of the cell to respond to short transient pulses. The use of high valued polysilicon resistors (typically exceeding100K ohms) in the feedback path of RAM cells is indicated in Figure 6-6. The resistance works with the cell capacitance to reduce the bandwidth of the feedback path, preventing the cell from responding to the short duration of charge collection. Limiting the cell bandwidth in this fashion also results in increased write time for the device. A negative temperature characteristic with significant change in resistance versus temperature results in considerable change in SEU and write cycle

Figure 6-6. RAM Cell with Polysilicon Resistors [Vinson92]

time characteristics of devices which utilize this technique. Figures 6-7 through 6-10 indicate several techniques for hardening based upon storage latch duplication and the use of state-restoring feedback circuits.

Figure 6-7. Upset-Tolerant Memory Cell [Rockett88]

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Figure 6-8. Principle and Schematic of the Dual Interlocked Storage Cell (DICE) [Calin96]

Figure 6-9. Transmission Gate and Clocked Inverter Latch DICE Implementations [Calin96]

Figure 6-10. SEU Immune Whitaker Cell [Liu92] V-39

6.4

Fault Masking and Redundancy

One of the techniques employed in fault masking, detection, correction and recovery is that of redundancy. The three basic techniques in the application of redundancy are informational (redundant data structures), spatial (redundant hardware), and temporal (redundant sequential operations). The fault detection and correction capabilities of redundant structures are good; recovery may be either simple or highly complex depending upon the nature of the function performed by each of the structures. The price of redundancy schemes includes increased system hardware content and decreased performance or throughput. Informational and spatial modular redundancy increases hardware content, increasing size, weight, power, cost, and failure rate. Although the increase in hardware content in informational redundancy is typically less than spatial modular redundancy, similar forms of impact are associated with the error detection and correction schemes. Temporal redundancy requires additional time to sample signal conditions in logic implementation and to perform consecutive computation operations in the case of processor implementation.

6.4.1

Error Detection and Correction Coding [Lin83] [Fujiwara90] [Nelson90] [Saxena95]

Spatial and temporal redundancy rely on the use of significant redundancy in space or time to perform error detection and correction. However, in some applications less redundancy is adequate for detection and correction of errors. In these schemes, information redundancy and encoding are utilized such that in the presence of errors, the information is internally inconsistent, enabling error detection and correction implementations. Error detection and correction coding theory is the most widely developed mechanism for detection and recovery in digital systems. This typically requires less redundancy than other detection and correction schemes. Replication is effective in detection and correction capability, but has large size, weight, power, and cost implications for some types of applications where coding provides a more effective solution. Error detection and correction codes can vary widely in detection and correction capabilities, code efficiency, and complexity of encoding and decoding circuitry. The simplest form is the use of an additional parity bit to provide single error detection in buses, registers, and memory. A code’s error detection and correction properties are based on its ability to partition a set m n m of 2 , n-bit words into a code space of 2 code words and a non-code space of 2 - 2 words. The most common block code used in memory systems is the single error correcting, double error detecting (SEC-DED) Hamming code, the version providing single correction and double bit detection for 64 information bits requiring 8 check bits. A characteristic of error detection and correction codes is the Hamming distance between words in the code space; the single correcting, double detecting code has Hamming distance four. More powerful codes may be constructed by using appropriate generating polynomials; a Hamming distance six code can be utilized to provide the ability to correct all double bit errors in 84 bit words using 15 check bits in a microprocessor physical address translation table implementation. n

Cyclic redundancy checks, other cyclic codes, and convolutional coding schemes are used to detect errors in serial data transfer interfaces and storage media.

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6.4.1.1 Error Detection and Correction in Data Storage and Communication [Chen95][Rubino95] The most common form of information redundancy is the use of concurrent error detecting and correcting codes which are often applied to the information stored in memory subsystems or in the transmission of information. The most simple coding scheme is the use of a parity check code in which one or more bits is added to a set of data bits, lengthening the word. Computation of the parity check bits is based upon simple modulo-two addition of the information bits. Parity checking is generally utilized to perform error detection; however, combined with the use of other structure in the information it can be used to isolate and to correct errors. Simple parity checking lacks efficiency in error correction, and multiple errors compromise the performance of the code unless numerous interlaced parity structures are applied. Error Detection and Correction (EDAC) or Error Control Codes (ECC) are generally classified as either block codes or convolutional codes. The encoder for a block code divides the information sequence into message blocks of k information bits each and transforms each into an n-bit codeword by appending n-k check bits. The set of 2k codewords of length n is called an (n,k) block code. Block codes are used for data storage systems as well as communications channels. The encoder for a convolutional code also accepts k-bit blocks of information and produces an encoded sequence of n-symbol blocks. However, each encoded block depends not only on the present k-bit input block, but also on the m previous message blocks, referred to as memory order of m. The set of encoded sequences produced by a k-input, n-output encoder of memory order m is called an (n,k,m) convolutional code. Convolutional codes are typically utilized for communications channels and other serial data transfer applications. A typical characteristic of linear block codes is a systematic structure in which the information bits form a contiguous string and the check bits are appended to the information bits as another contiguous string to form a codeword, termed a linear systematic block code. An important property of a linear block code is the minimum distance, dmin, between valid or error free codewords in the codespace. From this characteristic it is seen that the maximum number of detectable errors is equal to dmin - 1. The random error correcting capability, t, of a block code is equal to the largest integer which is not greater than (dmin - 1)/2. The Hamming codes are the first class of linear block codes which were devised for error correction; these codes and their variations have been widely used in digital communications and data storage systems. For any positive integer, m>3, there exists at least one Hamming code with the following properties: Code Length: n = 2m - 1 Capability: t = 1 | (dmin = 3)

Information Bits: k = 2m - m - 1 Check Bits: (n - k) = m

The characteristics of several Hamming codes are indicated in Table 6-1.

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Characteristics of Hamming Codes Code Information Check Length Bits Bits [n] [k] [ (n - k) ] 7 4 3 15 11 4 31 26 5 63 57 6 127 120 7 255 247 8 511 502 9

Table 6-1. Characteristics of Hamming Codes

Shortened Hamming codes are created by deleting columns from the generator matrix and producing a set of codes with the following properties: Code Length: n = 2m - l - 1 Capability: t = 1 | (dmin = 4)

Information Bits: k = 2m - m - l - 1 Check Bits: (n - k) = m

For a code to be useful for high speed memory applications, its structure must permit rapid parallel encoding and decoding Characteristics of Hsiao's Codes operations. Hsiao developed the SECCode Information Check Relative Typical DEC codes by examining the properties of Length Bits Bits Arithmetic Arithmetic shortened Hamming codes to identify [n] [k] [ (n - k) ] Complexity Path 12 8 4 16 4.0 specific codes which enable fast encoding 14 9 5 32 6.4 and decoding processes. The properties 15 10 5 35 7.0 of Hsiao’s codes are described in Table 616 11 5 40 8.0 2. Depicted in this table are the 22 16 6 54 9.0 characteristics of the code (n,k) and 26 20 6 66 11.0 30 24 6 86 14.3 indication of the complexity factor and the 39 32 7 103 14.7 critical path length which is useful in 43 36 7 117 16.7 estimating the gate count and speed which 47 40 7 157 22.4 could be expected from a decoder 55 48 7 177 25.3 implementation. 72 64 8 216 27.0 Discovered in 1959, the Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful random error correcting cyclic codes. Cyclic codes are an important subclass of linear codes which are attractive because of inherent algebraic structure which enables fast and efficient encoding and decoding implementations. The BCH

80 88 96 104 112 120 128 130 137

72 80 88 96 104 112 120 121 128

8 8 8 8 8 8 8 9 9

256 296 336 376 416 456 512 446 481

32.0 37.0 42.0 47.0 52.0 57.0 64.0 49.6 53.5

Table 6-2. Characteristics of Hsiao’s Codes

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code is a remarkable generalization of the Hamming codes which enable the capability to provide multiple error correction. Among the non-binary BCH codes, the most important subclass is the Reed-Solomon (RS) codes. The use of block error detection and correction codes must be matched to the nature of the error conditions which will be encountered and the key performance attributes which the application requires. These factors generally define two applications regimes; error tolerance in high-speed processor memories, and mitigation of error conditions in mass memory subsystems. A third general classification is sometimes considered in which unique properties such as unidirectional error signatures are produced by the design or implementation technology. The nature of the error properties is usually classified as randomly occurring errors and burst error conditions. In the case of conditions in which more than single error correction is required, such as random double-bit-error-correction (DEC), the more general class of BCH codes and majoritylogic-decodable structures are viable candidates. These codes require twice as many check bits as the SEC code, and the decoding is therefore significantly more complex and time consuming. In certain cases, specific properties of the bit error conditions can be exploited to provide added information to the decoding process. If the bit error patterns contain the presence of fixed or hard errors, to which added single event upsets produce double bit error conditions, erasure correction can be utilized to remove the fixed errors leaving the single SEU induced bit error for the code to correct. In the case of memory systems in which large word size is constructed using several devices, each providing byte (8-bit) or nibble (4-bit) width segments, the potential exists for multiple bit error patterns in which the errors are all contained within the byte or nibble segment produced by one memory device. The single-byte-error-correcting (SbEC) code is capable of correcting all single byte error conditions; however, this code has poor performance in detecting any error pattern which spans more than one byte. Because SbEC codes do not detect most randomly occurring double-bit error patterns, most applications use the single-byte-errorcorrecting double-byte-error-detecting (SbEC-DbED) codes. Reed-Solomon codes are the general class of byte oriented codes; however, the code length constraints of RS codes prevent codes having 64 and 128 bit information lengths in usable byte definitions. Kaneda and Fujiwara have developed a class of SbEC-DbED codes having arbitrary code and byte length. A further extension of this technique is to provide a class of codes which possess the property of single-biterror-correction, double-bit-error-detection, and single-byte-error-detection (SEC_DED_SbED). Table 6-3 indicates the properties of several of these codes. Utilization of EDAC techniques in high-speed processor memory systems typically employs either a hardware or software provision which enables all locations within the currently used address space to be subjected to periodic verification. This provision requires periodic read access of all memory locations and examination by the EDAC protection to prevent the accumulation of single errors from exceeding the capability of the code to perform error correction. This procedure is usually termed “washing” or “scrubbing” the memory subsystem, and is usually performed under hardware control by an application specific integrated circuit (ASIC) or other standard product device used to implement the detection and correction code logic. Conventionally, error detection and correction is performed in real time for processor accesses to memory, with the correct result forwarded to the processor, and the corrected value V-43

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Table 6-3. Check-Bit Lengths for Various Codes also written back into memory if correction was necessary. In the case of scrubbing access to memory locations, corrected values are again written back into memory if correction was necessary. The time necessary for detection and correction becomes additive to the memory subsystem access time and often generates the need for additional wait states in processor accesses to memory. One potential approach for reducing the performance penalty imposed by the added wait states is to allow the processor direct access to the memory without performing error correction. In this manner the memory contents are forwarded directly to the processor without requiring the delay associated with detection and correction logic. The use of Markov reward modeling techniques may be utilized to establish the frequency of operation necessary for the scrubber, and to analyze the potential for erroneous values to be forwarded to the processor when considering such a provision. The error detection and correction strategies for mass memory subsystems are again optimized to address the error characteristics of the specific application. In addition to the randomly occurring single bit errors induced by environmental factors, the effects of the media involved in these systems introduces burst error characteristics. Reed-Solomon codes, which are sometimes interleaved with other coding techniques and erasure techniques, provide solutions for these applications. Compact disc ROM (CD-ROM) uses cross interleaved Reed-Solomon singlebyte-error-correction (SbEC), with cyclic redundany check (CRC) codes. The RS codes used are the (26,24) and (45,43) codes over GF(28). Reed-Solomon codes are also used with cyclic codes constructed systematically for correcting burst errors (Fire codes) in these applications. The technique of interleaving may be visualized as a procedure in which the encoded data are loaded into a matrix by rows and then written by columns. The read operation loads the matrix by columns and shifts the information out to the decoder by rows. In this manner, a burst error becomes a distributed set of seemingly random single bit errors. Reed-Solomon codes were used as the error correction provision in the architecture of Redundant Arrays of Inexpensive Disks (RAID) technique of distributing data among multiple storage devices to achieve high bandwidth, and low cost disk storage. More recently, the technique has been used to design

V-44

multiprocessor and network memory systems with high reliability and bandwidth, and to design fast distributed checkpointing systems. Such implementations are termed RAID-like systems. [Plank97] The third class of error detection and correction applications addresses the unique error conditions in which the errors are asymmetric or unidirectional. Unidirectional errors are defined as a class of errors where the mode of the all errors within a codeword are of the same nature, either all ones transitioned to zeroes, or all zeroes transitioned to ones, but the sense of the errors may change from one codeword to the next. Asymmetric errors are defined as the condition in which all codewords have the same error characteristics, such as always ones transitioned to zeroes, and the sense of the errors is known a priori. Detection and correction applied to read-only-memories (ROM) is one example in which a fault has the potential to produce only one form or error condition. Very specific techniques which exploit these characteristics of the error conditions are utilized in the development of EDAC strategies for these applications. In the special case of specific error condition such as a unidirectional error model in which the predominance of error states are zero-to-one error transitions (or alternatively the case of one-to-zero dominance) schemes such as M-out-of-N and Berger codes may be useful. In the Berger code, the number of zeroes in the codeword is encoded as a binary number and appended to the codeword. Thus any unidirectional error which increases the number of ones, either decreases the number of zeroes, increases the check value, or both; similarly the number of ones could be counted if the predominant error model were to be one-to-zero transitions. In the case of M-out-of-N codes, the set of codewords is the set of N-bit words that contain exactly M ones. This structure could be useful to protect state machine structures which rely on the one-hot state encoding principle. An application of error detection and correction coding which has interesting implications in payload systems is that of yield enhancement in memory devices. The ability to achieve high integration density in the presence of realistic defect density in semiconductor manufacturing processes requires manufacturers to utilize fault tolerance provisions. These provisions enable devices which contain defects to be repaired or operated in a fashion which results in normal device function in the presence of the defect or fault. The most common technique for tolerance of these defects has been the utilization of spare rows and columns of memory cells which are substituted for those which are defective, or which contain individually defective memory cells. The repair action is supported through programming of individual devices by fusing of polysilicon or metal links using laser or electrical action. This provision enables the capability to tolerate from one to several defects and to enable the device to be repaired such that normal operation is achieved with no impact to read, write, or cycle time performance. The ability to recover device functionality in the presence of numerous defects cannot be achieved using row and column repair provisions, and techniques such as single bit correcting codes are applicable. The inclusion of an error correcting code within the memory device has performance implications resulting from the need to generate and store check-bits on write operation, and to calculate the syndrome and to perform error correction on read operations. In the case where a strictly single error correcting code is utilized, the code also provides the capability to correct most single bit errors which are introduced as soft-errors (in terrestrial applications) or single event upsets (SEUs in space applications). When used in this manner, the relatively infrequent, but potentially significant event in which an SEU (or softV-45

error) occurs within a word in which there exists a semiconductor defect caused hard error, the result delivered by the part usually contains several errors. The use of byte error correcting codes is then necessary to ensure adequate fault tolerance. [Fujiwara90] In considering the design of ultra-reliable memory systems it has been proven that an implementation utilizing two SEC-DED memory modules performs better and requires less overhead than triple redundant memory with voting in regard to assured memory output in the presence of randomly occurring bit errors. The two SEC-DED modules are configured as primary and redundant with the capability for the redundant module to be utilized in the event of an uncorrectable double bit error in the primary module. Consideration of other memory subsystem reliability issues, such as decoder complexity and protection against other failure modes such as functional failure of entire memory devices could result in the ability to achieve better overall assurance using the TMR solution. [Vaidya96]

6.4.1.2 Error Detection and Correction in Arithmetic and Logic Structures [Peercy93] The complex nature of coding precludes its use in most computational operations. Simple arithmetic functions do permit the use of parity prediction through multistage adder circuits, and arithmetic codes such as AN and residue codes exist. AN is a non-separate code in which the added information is not distinct from the initial information, permitting fault detection in addition operations. The code in this case is performed by pre-multiplying the input variables by a check base, A, adding the resultant codewords (modulo M), where the check base divides M, such that A(X +M Y) = AX +M AY. A non-zero residue constitutes the detection of an error, as indicated in Figure 6-11. Other Figure 6-11. AN Code [Peercy93] residue codes which are separate in nature utilize the structure shown in Figure 6-12. The check symbol in separate residue codes is calculated from the input variables as C(X) = X mod A, with the requirement on the check base, A, that it divides M = Inverse residue codes are 2n-1. capable of detecting multiple errors which are unidirectional in nature, and Figure 6-12. Separate Residue Code [Peercy93] biresidue codes with two separate encoding levels provide error correction capability. The use of residue coding schemes for fault tolerance has received very limited application due to the requirement for pre-multiplying input variables, limited correction capabilities, and lack of capability for general computational operations.

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6.4.2

Spatial and Temporal Redundancy

6.4.2.1 Spatial Redundancy Consider the use of modular redundancy depicted in Figure 6-13; this type of structure is termed static redundancy. The most common form of modular redundancy is triple modular redundancy (TMR), in which a fault in an individual module is corrected by the action of the voter through the majority consensus, or two-out-of-three, voting rules. The structure is not tolerant of faults in two or more modules or within the voter, and failure will result from such occurrences. The modules depicted in Figure 6-13 may include basic functions such as a memory element, d-flip-flop, or latch, logic blocks such as state machines or highly complex logic functions, or complete processor, functional blocks, or subsystems. Figure 6-13. Triple Modular Redundant System The notion of modular redundancy can be extended to the general sense of n-modular redundancy (nMR) with associated enhancements to the fault tolerance capabilities and expense associated with their implementation. For instance, a quad redundant implementation utilizing four modules provides the ability to tolerate errors in two modules, if the voter has the capability to discern the characteristics or signatures of the failure and to provide a plurality vote capability. This capability allows the redundant structure to provide TMR type detection and correction in the presence of permanent or hard failure in one of the modules. Of course, if the second failure has identical properties to the initial event, in static redundancy the plurality voting will not be capable of resolving the condition and the scheme provides only error detection. However, if the voter is capable of responding to the initial failure by removing the voting rights of the failed module and imposing majority voting rules, a second SEU event could be tolerated by the remaining TMR structure. This would be the case if during or before recovery from the initial failure a second SEU event would occur in one of the modules. This capability to change the nature of the modular voting scheme is termed dynamic redundancy. In general, dynamic redundancy consists of three actions, detection of error, location of the error, and reconfiguration of the structure to perform in an optimum manner. The costs of fault tolerance using spatial modular redundancy include the cost of additional modules, the size, weight, and power necessary to operate the additional circuitry, and increased failure rate (reduced reliability) associated with the utilization of additional hardware elements and interconnect structures. If real-time continuous operation of the function is not required and error detection with some other recovery capability can be imposed, dual modular redundancy may be adequate. In this case the voter performs only a checking function and thus becomes only a comparator. Permanent or hard failure in either of the modules results in the comparator producing continuous error assertion. The capabilities of other elements of the system to discern which of the modules is performing properly and to disable the error output

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and to force the checker to pass the output of the properly functioning module are necessary to resolve this condition. If there exists a highly probable condition in which failures in both modules would produce identical module output conditions, the redundant module could potentially contain a complementary function instead of an identical copy of the primary module. In this case the dual of the primary module is utilized in the design of the redundant module. Such complementary logic may be used with dual-rail codes in performing error detection. This technique is regarded as most applicable to hard or permanent hardware faults arising from incorrect specification, design, or common implementation defects; in this sense it is analogous to design diversity or Nversion programming in software based fault tolerance schemes. If, however, the module contains complex logic functions which have a characteristic of exhibiting very limited failure signatures as a result of a large number of independent single event fault occurrences, this technique may help to enable the development of suitable detection provisions. In the use of complex off-the-shelf circuits that generate, transform, or process information, such as microprocessors, microcontrollers, and complex application specific circuits (ASICs), the most cost-effective hardware-based approach for error detection and correction may be modular replication. The use of off-the-shelf functions embedded in system-on-a-chip implementations are similar in nature. The constraint which mandates an application level strategy such as modular redundancy is the inability to modify the internal design of such devices to impart fault tolerance provisions at a lower level. As indicated above, modular redundancy uses multiple replicas of hardware modules and a comparison/voter mechanism to evaluate the results from the individual modules and determine the correct output. In its simplest form, two replicas are utilized with comparison logic to provide error detection; correction capability is not provided; and rollback and repeat performance of the operation is required to develop the corrected result. The most common form of this technique is triple modular redundancy (TMR) in which the voter compares the output of three modules and determines the correct result based upon a simple two-out-of-three vote. In the case of TMR the ability to detect a single fault is excellent, and the ability to deliver the most probable correct result based upon the two-out-of-three vote is also reliable. The element of difficulty in complex circuits using redundancy of this type is the ability to recover the faulty processor to a known-good condition so that its outputs may again be utilized in detection and correction operations. Often the recovery operation in the faulty processor requires recovery of data and control states and resynchronization processes that cannot be performed concurrent with normal processor operations. The faulty processor must be removed from the redundancy configuration until the recovery operation is performed, resulting in susceptibility of a second fault compromising operation of the system during this interval; error detection continues to be provided, but no source of correction process is available. To eliminate this vulnerability as well as to provide detection and correction capability in the case of intermittent or permanent faults in individual processors, some architectures use a fourth processor in a quad-redundant configuration to assure the performance of the fault tolerance provisions. Additionally, synchronization of the outputs of COTS processors or devices using tight coupling and fault tolerant clocking schemes is not easily accomplished. An alternative to tight coupled lock-step operation is the use of loosely coupled or synchronized units. In this case, only process-critical outputs of the individual processors are evaluated by the voter to identify a failed processor. Another obvious concern in modular redundant schemes is the protected integrity of the comparison and voting circuitry. The use of single event upset hardened technology, circuit design, and application techniques V-48

such as modular redundancy in the comparison and voting circuits to eliminate susceptibility of single event upset or single point failures must be utilized to assure the integrity of the fault tolerance provision.

6.4.2.2 Temporal Redundancy An alternative to spatial redundancy is temporal redundancy in which the same hardware or software elements are used in consecutive operations, using diversity in time to provide results which may be compared using similar comparator/detection, and correction techniques discussed above for spatial redundancy. This technique is highly effective in tolerance to transient fault conditions, such as the errors introduced by single event upsets and electrically induced corruption; it is of little value in mitigating permanent fault conditions (obviously, due to the use of the same faulty hardware or software to perform both operations). The technique also is dependent upon the requirement for known error-free conditions on the input signals or variables used in the operations. Either independent detection and correction must be provided to inputs, or the use of alternating logic techniques or complementing functions must be utilized to provide tolerance to input signal or variable errors. Alternating logic utilizes a class of boolean functions which are self dual, i.e. they satisfy the property f(x1_, x2_, . . ., xn_) = f_(x1, x2, . . ., xn). Recomputing with shifted operands (RESO) is applicable to certain problems in which the shifting of inputs forms a complementing function which produces known relationship in outputs which may be utilized in detection and correction.

6.4.2.3 Combined Redundancy Implementation [Mavis98] The use of static spatial redundancy as a fault tolerance technique for single event upsets in memory elements (latches, flip-flops, and RAM), along with temporal redundancy as a mitigation provision against single event transients in combinatorial logic has been proposed for advanced technology devices. The increased bandwidth provided by advanced technologies provides opportunity for propagation of transient pulses which result from energetic particle strikes on combinatorial logic nodes. The increased bandwidth of these technologies also enables the use of high clock rates; 200 MHz to 400 MHz in present day commercial production technology. In older technologies, the 100 ps to 200 ps transient pulses would not propagate along a path of combinatorial logic gates; the bandwidth of advanced technologies supports propagation of such pulses, and the high clock frequencies provide ample opportunity for clocking of errant results into memory elements. The combined scheme uses temporal triple mode redundancy by sampling the output of combinatorial logic at three different times, storing the individual result in three different latch or flip-flop elements, and majority voting the latched result. By ensuring that the separation between clock edges is greater than the duration of a transient pulse emerging from the combinatorial logic, the transient can corrupt only one of the three values. The majority voting of static triple mode spatial redundancy ensures that upset of individual latches or flip-flops will also be corrected through action of the majority vote logic. The impact of utilizing the combined technique is an approximate 50% reduction in the usable clock frequency from that which would otherwise be achievable. An increase in power V-49

due to added clocks and registers (approximate 1.8 times the otherwise achievable power), and an increase in design complexity, due again to the complex clocking and added registers/latches, are also impacts resulting from this implementation.

6.5

System Error Detection and Recovery [Sosnowski]

Whereas the fault detection capabilities of hardware based schemes such as modular redundancy are good, fault detection is the most difficult aspect of fault tolerance to achieve in applications oriented fault tolerance using algorithms, or software based fault detection, due to the elusive nature of the signature of most faults. A fault which results in a fail-stop consequence enables obvious opportunity for detection; most conditions of compromised system state produce signatures which are difficult to discern. Once detection is accomplished, recovery may be as complete and efficient as necessary to restore normal system operation.

6.5.1

Application-Oriented Fault Tolerance [McMillin97]

Application-oriented fault tolerance is a software solution to the problem of error detection and recovery. Additional processor hardware is used in some of the techniques classified as applications-oriented, but its operation is through applications software rather than hardware acting to provide fault masking. The software components are called assertions. The application of a set of metrics to a problem specification results in software assertions that are embedded in the program code. Executable assertions are integrated into program code, having the form “if not ASSERTION then ERROR”. The extent of error detection is determined by the perceptiveness of assertions to discern a compromised state of program execution. The recovery capability of the fault tolerance provision is determined by the response which is embodied in the error branch path. Applications-oriented fault tolerance works on the principle that testing of a program’s intermediate results for conformance to specification ensures that the end result will be within specification, and that if an error does not manifest itself in a failure, then the fault is of no consequence or interest. A multi-processor environment limits the amount of information which is available to an executable assertion and creates a more complex problem than the generation of such assertions for a sequential environment. In the case of the multiprocessor environment, the creation of assertions at the message passing interchange granularity is essential, utilizing local program state and received messages from other parallel components. The primary question is how to generate, in a systematic way, assertions that result in efficient and effective fault detection capability. Fault detection in most computer science research focuses on the presence of hard repeatable faults and thus segments the problem into acceptance tests to detect the presence of a fault, and the use of diagnosis to identify and isolate the faulty element. The problem of intermittent or transient faults, such as the consequences of single event upset or transient pulses within a system, requires effective acceptance tests to detect the presence of faults. The use of syndrome testing in diagnostic algorithms or distributed agreement techniques for fault isolation are important for general fault tolerant systems. These techniques are applicable to the class of

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faults introduced by SEUs only to identify elements presenting malfunction as a consequence of such errors. 6.5.1.1 Acceptance Testing [Banatre93] [Kim92] [LaBel962] [Tso93] Several acceptance test techniques are employed in detecting the presence of faults, Nversion programming, recovery blocks, self-checking software, and the watchdog coprocessor. N-version programming is intended as a provision to detect defects in software design, coding, and integration. Parallel or sequential execution of programs and comparing the results provides opportunity for fault detection, much in the same way as modular redundancy does for hardware fault detection provisions. The diversity of designs is intended to perceive design defects and does little to improve the transient fault detection capability. Completeness and exactness of the specification and synchronization of intermediate and final results checking are issues in the implementation of N-version programming. The self-checking software technique has aspects of functionality, control flow, and data in order to provide error detection. The functional and data aspects examine the reasonableness of the results, and may include an assessment of the input variables in performing acceptance testing of algorithm results. The capability provided by seemingly ad-hoc techniques in assessing the reasonableness of algorithm results is a powerful technique in the detection of computation errors. Validating the range of a result from a computation process, its change from previously computed results, and its consistency with input variables and other computed values have been shown to be effective error detection provisions. Establishing the bounds or acceptance range for computation results requires analysis of input variable ranges and other sources of error, such as the truncation or rounding on numerical results, to determine pass/fail criteria. The control aspect includes checks on the execution flow from entry point to exit points in algorithm blocks, and only valid paths between the algorithm blocks are permitted. One approach to establishing the correctness of high-level control flow uses information (structure labels) embedded in the syntax of the program text. The introduction of path tags to check the validity of the sequencing of blocks and block tags to verify that execution of blocks proceeded properly from entry to exit points are examples of such structure labels. Each block contains a unique number called its signature, and upon entry the block tag is set to the value of the signature. The block tag is verified upon exit from the routine to confirm that the block was not entered in any manner except the valid entry point. The path tag is then set to the value of the next block signature, which is checked on entry into all blocks. Placement of these locks at entry and exit points verify that only processes presenting the correct key can progress; all other attempts at entry or exit are flagged as indication of the loss of program branching or sequence control. Similar control checking of program iterative execution loops for illegal entry, completion and branch related loop termination may be utilized. Range checks on loop indexing and range testing of address pointers are also utilized to detect loss of proper execution sequencing. The use of a memory management unit (MMU) which grants specific access rights to segments of memory by various software routines provides effective detection of errors which result in software accessing locations out of normal use bounds. The insertion of error capturing instructions in locations which do not contain valid executable code also may be used in the detection of control errors. V-51

The recovery block approach uses acceptance tests in the form of checksums and other bounds checking on computation results to detect the presence of errors. The recovery block notion in this provision is that second (third, fourth, etc.) executions of the process using the same or different algorithms exist and provide a recovery path from which acceptable results may be generated. If no acceptable results are produced by any of the recovery blocks, the system check stops and other forms of recovery (e.g., roll-back using check-pointed data or rollforward to a safe processor condition) are invoked. The recovery block is a language construct supporting the incorporation of program redundancy into a fault tolerant program. The syntax of recovery block incorporation may take the form: ensure T by B1 else by B2, . . . else by Bn else error. T denotes the acceptance test, B1 denotes the primary try block, and Bn denotes the alternate try blocks. All the try blocks are designed to produce the same or similar computational results. The T acceptance test is a logical expression representing the criterion for determining the acceptability of the execution results of the try blocks. A try (execution of a try block) is always followed by an acceptance test. In the case of multiple processor system configurations, the capability to implement a distributed recovery block scheme and the ability to then implement nested recovery blocks may improve the fault coverage and performance of the recovery block technique. Another attempt at monitoring the behavior of a system is the use of a watchdog coprocessor. Most embedded processor systems use a hardware watchdog timer to detect halts to processor execution or errors in program control flow which are detected through failure of the software execution to reset the timer within the prescribed period of time. The watchdog timer then forces an unmaskable interrupt or a reset to the processor as a means of error detection. The watchdog coprocessor extends the notion from the simple hardware timer to the use of an additional processor to check the results of primary on-line processor elements. An active watchdog may implement interaction with the on-line processor as simple as an “I’m OK” message or heartbeat monitor which the watchdog expects to receive within a prescribed window. If not received within the valid window, the watchdog interprets this result that the online processor control flow is disrupted and asserts interrupt or reset of the on-line processor. The watchdog may execute concurrently with the on-line processor, or it may operate off-line and pre-compute results for subsequent acceptance testing. It invokes decisions on the integrity of the system based on assertions about the main process, assuming that faults either disrupt program control flow, corrupt database contents, or produce incorrect numerical results. The purpose of the watchdog is not to take over execution from the on-line processor, but to assist other low-level fault tolerance provisions within the system by providing improved fault detection capabilities. There are generically four classes of assertions that can be implemented in a watchdog coprocessor: inverses, transformations, range, and state checks. Their respective usefulness must be matched with the nature of the process being executed by the on-line system, numeric mathematical computations versus database applications. The inverse assertion takes the output results and infers the nature of the input variables that would be necessary to produce the result and verifies consistency between the actual inputs and the inverse inferred values. A transformation assertion operates by converting the problem to a simpler one and computes estimates of the expected output and comparing the results with the approximated results established by the coprocessor. The on-line system may be performing a Kalman filtering process, whereas the shadow processor might use a moving average to estimate the expected V-52

results from the on-line processor. Range assertions uses pre-established limits on the range of allowable values which outputs may assume using knowledge of the problem, but not the specific values of the input variables. State assertion checks are similar to the functional and control tests in self-checking software, but in this case the operation is administered by operation of the coprocessor. Since the watchdog coprocessor requires access to the input variables or database, the output results of specific processes, and potentially the state of program execution in the on-line system, the shared memory and/or redundant memory and message passing provisions between the on-line system and the coprocessor must be architected carefully.

6.5.1.2 Constraint Predicates The ability to apply the techniques identified above relies on specific properties of the problems being addressed by processor operations and are embodied in the constraint predicate. There are three defined predicate subclasses which formulate the constraint predicate: progress, feasibility, and consistency. The progress predicate utilizes the notion that there exist steps in the sequence of process operations and that the decomposition of the process into a finite number of operations blocks provides opportunity for testability at these intermediate points in the process. The progress predicate surfaces the notion that in some processes the number of steps in a process is known a priori. In others, such as problems of an iterative convergent nature, the number of steps necessary to achieve convergence is not known a priori. Clearly for the class of problems with a known number of process steps, the point at which checking of the results may be performed is known and early or late completion of the process may be utilized to detect errors in the control flow of the process. In the case of problems in which the number of process steps required to reach convergence is not known a priori, the ability to establish an upper bound to utilize if the problem were to become non-convergent, and the ability to establish a convergence envelope which may be utilized to monitor the process may be used as fault detection provisions. The characteristics of certain problems, such as monotonically reducing error conditions, lend themselves well to convergence envelope techniques. In other problems it is difficult to establish bounds on the convergence rate and, although tests to assure that positive progress towards convergence exists, the determination of sufficient progress may not be possible, and timeout using upper bounds may be all that you can do. The feasibility predicate implies constraints which are apparent from the nature of the problem on which the processor is operating. Contained within this notion is the property of boundary conditions as constraints from which to generate a good predicate; testable results must be within the solution space of the problem as defined by the boundary conditions. Certain problems have boundary conditions which are known a priori; they do not vary as the solution progresses, and may be readily used in error detection. For some problems the feasibility constraints may be so loose as to be virtually of no use at all; the problem simply contains insufficient natural constraints from which to generate a good predicate. Consistency conditions imply the ability to infer validity in intermediate or final results from input variables and previous intermediate or final process results. This is usually the case in black box testing in which the internal details of process and implementation are not known, but consistency of results can be discerned at an individual process step based upon previous process steps, or previous executions of the entire process block. Consistency tests are a

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powerful technique; entire constraint predicates have been developed using only consistency conditions.

6.5.2

Algorithm Based Fault Tolerant (ABFT) [Blaquiere95]

One specialized utilization of information redundancy is algorithm based fault tolerance (ABFT). In this approach, some attribute of the function being performed is exploited with the use of information or time redundancy to achieve error detection, correction, or recovery. Adding fault tolerance provisions to a particular program will increase the run time; the performance penalty is nearly linearly dependent upon the number of error conditions which exist in program execution and must be tolerated. Most ABFT techniques developed to date address computational problems that exhibit structure and regularity which can be exploited to develop informational redundancy, such as matrix computations, sorting, Fast Fourier Transforms (FFT), QR factorization, singular value decomposition, least squares minimization, and other signal processing applications. There exist several techniques for specific computational problems encountered in processor applications; as an example, consider the problem of matrix multiplication. In the checksum encoding, an extra row and column consisting of column and row checksums are added to the original multiplier and multiplicand, respectively, as indicated in Figure 6-14. The resulting matrix should preserve the checksum property. If it does not, an error has occurred.

a11 . . . a1N . . . . . . aM1 . . . aMN _____________ a(M+1)1 . . . a(M+1)N

1 2 0

5 1 4

1 0 2

[3 10

3]

X

b11 . . . b1P . . . . . . bN1 . . . bNP

X

2 7 0

5 0 0

1 2 6

8 9 6

b1(P+1) . . = . bN(P+1)

c11 . . . cP1 c(P+1)1 . . . . . . . . . c1M . . . cPM c(P+1)M ________________________ c1(M+1) . . . cPM c(P+1)(M+1)

37 11 28

5 10 0

17 4 20

59 25 48

[76

15

41

132]

=

Figure 6-14. Checksum Technique in Matrix Multiplication [Blaquiere95] Direct examination of the checksums enables identification of a single error; weighted checksum techniques enable the detection and isolation of a limited number of concurrent errors. The number of numerical operations associated with the computation of the checksum row and column vectors and the expanded size of the array multiplication are significantly less than the

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number of operations required to perform the matrix multiplication twice, checking the results for consistency (error detection) and computation a third time for error correction. The exact equal sign cannot be used in comparing row and column checksum results in the case of possible rounding or truncation errors, resulting in a Type I statistical error rejecting a correct outcome. In this case error analysis must be used to bound the range of possible valid outcomes and the computation must allow for such variance in the results. An alternative approach, the ID algorithm, for implementing fault tolerance in matrix multiplication is based upon the generation of syndromes for intermediate results. The algorithm detects faults with single iteration fault latency as opposed to the full problem run-time fault detection latency for the checksum algorithm. The penalty for this implementation is an increase in matrix size by a factor of logn. While the error coverage of the algorithm is not complete, it is better than the checksum algorithm. Another classical problem in the computing environment is the sorting of lists and database elements. Due to the nature of the sorting problem, there is no opportunity to identify errors in the intermediate phases of the sorting process; the executable assertion is only valid after completion of the entire process. As a solution to this condition, the bitonic sort algorithm was introduced as a parallel sorting algorithm. The general idea of a bitonic sort is to build up longer bitonic sequences which will eventually lead to a sorted sequence while providing the ability to apply executable assertions to the intermediate results. Researchers have examined ABFT techniques for fast Fourier transforms (FFT) using the modified recomputing with shifted operands technique and an extra stage in the standard FFT butterfly network. Others propose an encoding based upon the superposition and shift properties of the FFT. The more general class of signal processing applications have been addressed by utilizing orthogonal transformations such as the properties of applications in which the sum-ofsquares of the input and that of the output are proportional. The FFT is one of the problems in which the sum-of-squares of the output equals the sum-of-squares of the input times the length of the input vector. Another signal processing algorithm in which sum-of-squares encoding applies is QR factorization, which is the factorization of a matrix into two matrices, an orthogonal and an upper triangular matrix. A number of problems, e.g. singular value decomposition and recursive least squares minimization, use QR factorization as a building block. Although the term “algorithm based” potentially implies a software implementation, these techniques are directly applicable to hardware based implementation of the algorithms. The checksum encoding scheme indicated for matrix multiplication is directly applicable to a hardware implementation which utilizes mesh-connected (orthogonal) array processors. The overhead time for algorithm execution to perform the additional checksum and array product operations in a software implementation of the algorithm become additional hardware overhead in the form of additional processing elements. The processing element overhead for the checksum encoding implementation for multiplying the n x n matrix by an m x m matrix is n + m + 1. For small matrices, this overhead is as high as 125%, and for very large matrices the overhead will be on the order of 3% to 6%. There is an additional time penalty which is incurred due to the need for the processing elements to perform the checksum computations on input matrices and to verify the resultant matrix. An enhancement to the checksum encoding scheme, described as a resultant memory map provision, performs these computations in additional

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processing elements, eliminating the time penalty and providing the capability to utilize row and column checksum differences to accomplish single error correction. The weighted checksum scheme was indicated above as a means of achieving multiple error tolerance. The ability to tolerate r errors results in the requirements of 2r weighted vectors. This results in significantly higher overhead, approximately five times the overhead to achieve triple error tolerance. The use of error detection and time redundancy are indicated as possible means to achieve multiple error tolerance at a more acceptable level of overhead. An implementation which utilizes algorithm based structure for error detection and time redundancy through the use of processor rollback using stack operations is indicated to provide multiple SEU tolerance, reduced hardware overhead, and minimal execution time penalty.

6.5.3

Detection Through Protocol, Timing and Data Checking

Error correction without significant redundancy is difficult; however, several rather simple error detection schemes provide the ability to determine faulty system operation and to enable fault containment and other recovery provisions. The behavior of most sequential logic circuits and systems may be described by state machines and other interface protocols. Variation from expected protocol along interfaces provides effective fault detection with less impact than modular redundant structures. Detection of machine state validity and correctness of state transitions provides additional opportunity for error detection without significant overhead expense. Data values can be compared with predicted values, previous values, and other heuristic information as a means of error detection. Handshaking sequences between elements involved in data transfer may be monitored by either hardware or software functions to provide error detection. A simple detection provision is the time-out check such as the watchdog timer utilized in most embedded microprocessor applications. An event failing to occur within prescribed time limits is an indication of a fault condition.

6.5.4

System Recovery Provisions

Achieving acceptable availability requires reducing the outage frequency, reducing the outage duration, and reducing the outage impact (reduce the number of users affected). Reducing outage frequency may be achieved through fault avoidance, fault masking, and fault tolerance provisions. Reducing the outage duration may be achieved through autonomous recovery, rapid ground support, diagnosis, and reconfiguration or recovery. Reducing the outage impact may be achieved through effective fault containment strategy.

6.5.4.1 Recovery Blocks The recovery block technique uses an acceptance test on the primary module or application result. If found to be compromised, a spatially or temporally redundant copy of the module or application is chosen and subjected to the same acceptance test provisions. Acceptance tests usually involve techniques such as range and bounds checking, consistency V-56

with previous module or application results, and attachments to the result which indicate normal flow through module or application processes.

6.5.4.2 Check-Pointing and Roll-Back Recovery [Peercy93] When a fault is detected, computation is rolled back several cycles (micro-rollback) to compensate for the latency between fault occurrence and detection. All computations since that which caused the fault are performed again, and some state repair is done as well. Specific design attributes of the processor are necessary to support the use of micro-rollback, such as the use of delayed write buffers, that are registers which hold data across cycle boundaries. These buffers must be deep enough to span the longest roll-back necessary to execute roll-back recovery in the architecture. If an unmasked fault has propagated in a system, a recovery period is needed to correct the system. The elapsed time between the introduction of the fault and detection of an error, is in all probability an indicator of the extent of propagation of the error and the extent of recovery which will be required. Most recovery schemes restore system operation to a previous correct state or recovery point. A processor is rolled back to a recovery point by restoring the processor state and key variables to a known good condition, invalidating cache memory (which is likely to have been corrupted by error propagation) and forcing cache data to be restored from protected main memory. A checkpoint is a copy of an application’s state which is stored in a protected region of the system. When a failure is detected, the application’s state is rolled back to the saved previous checkpoint and execution resumed at that point. Backward Error Recovery can be defined as the capability of a system to return to a consistent state that existed before it failed. A checkpoint is then defined as a consistent state from which the execution can be restarted. Backward error recovery is implemented by saving checkpoints for each processor of the architecture and by using these checkpoints to restart execution after a failure. A shared memory architecture can be used to implement checkpointing. One method is to allow cache memory to hold modified data until a cache line write must be performed, thus establishing a new checkpoint condition in system main memory.

6.5.4.3 Fault Containment To minimize the impact to system operations, to minimize the extent of recovery operations, and to enhance the probability of successful system recovery, errors must be confined to the maximum extent possible to the module or subsystem in which the fault occurred. Typically, error containment boundaries are hierarchically defined, with errors confined at the lowest level possible. Containment boundaries can be established by subsystems checking either their own outputs, or by validating all input information. If error detection is activated but error recovery is not supported, the subsystem process is typically halted to prevent error propagation.

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6.5.4.4 Reconfiguration and Recovery Having detected an error condition in an individual subsystem, reconfiguration and recovery must be performed. One strategy often utilized is to include redundant modules and to utilize a replacement unit to take over for the failed subsystem until it can be reinitialized and returned to an error free condition. Replacement units can be either “hot” spare, “cold” spare, or some condition in between. A hot spare in tightly coupled systems concurrently performs the same operations as the on-line subsystem, requiring little or no initialization to replace the failed subsystem. A cold spare must be initialized to perform the tasks of the on-line subsystem and the time necessary to complete the initialization and the completeness of the operation dictate the opportunity for system level effects and consequences. In loosely coupled systems, a warm spare is periodically provided key checkpointing information to enable the processor to continue from the most recent checkpoint instead of having to begin tasks from initialization. This results in minimal impact due to recovery without incurring the overhead associated with the tightly coupled hot spare configuration.

6.6

Fault Tolerant Systems Engineering [LaBel962] [Banatre93]

One of the more profound risks to spacecraft systems is that of having unknown device single event effects or failing to develop an understanding of the system level consequences of unmitigated single event effects. The criticality, or risk, of an operational impact to the system or spacecraft provides the foundation for setting the design requirement for single event effects management and mitigation. System level single event effects criticality analysis based on functional impact and the determination of appropriate mitigation techniques form the basis of a system engineering approach to the design of telecommunications satellite systems. The evaluation of alternative single event effects mitigation and fault tolerance provisions based upon the cost, power, size, weight, performance, reliability impact, and overall single event effects mitigation effectiveness of alternatives must be considered. The preceding sections have discussed some of the techniques available for fault avoidance, fault masking, and for detection and recovery operations. Each of these provisions has overhead associated with their incorporation into a system design, impacting size, weight, power, cost, reliability and performance of the system. Systems engineering must determine which techniques to utilize and how they must be integrated into the system in order to achieve cost effective systems which provide required availability and performance. At the onset of single event effects in the 1970s, the problem was constrained to the identification of the few components that exhibited susceptibility and the mitigation of these effects. The problem was mitigated by localized point solutions for single event upset and transients in the few device types which required the use of these techniques. Scaling of device technology and the accompanying reduction in operating voltage have reduced critical charge, and the increased circuit bandwidth enabled by these advances in technology has changed the situation to one in which one must search instead for the few components which do not exhibit some susceptibility to single event effects.

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6.6.1

Mitigation Requirements Based on Fault Criticality [LaBel962]

One technique for assessing the requirements for fault tolerance provisions is to examine the effects that faults would present to the operation of the system, and to adopt fault tolerance provisions based upon these impacts. The NASA developed approach to a methodology which assesses the single event effects related risks, examines SEE induced failure modes, and addresses the incorporation of mitigation provisions, is termed Single Event Effects Criticality Analysis (SEECA). Whether done according to this methodology or through some other similar provision, the idea is to examine the propagation of the consequences of a fault (an error) through a system to determine its impact, assigning a level of criticality to this outcome, and to adopt mitigation provisions based upon the severity of this impact. This procedure has similarity to the procedures utilized in traditional Failure Modes and Effects Analysis (FMEA) typically performed in support of system reliability analysis and prediction. Unfortunately, the tools and methodology utilized in reliability analysis are not directly applicable to single event effects analysis due to the nature of the non-uniform environment, transient effects mechanisms and system response, and differences in mitigation provisions. The analysis and determination of fault criticality based upon impact to system operations emerged as an informal method when one or two devices exhibiting single event upset susceptibility were utilized in payload applications. Advances in technology has resulted in a profound increase in the single event susceptibility of devices, and the complexity of payload systems has significantly increased the number of opportunities for these effects to occur. Systems engineering consideration of single event effects, a methodology for assessing SEE criticality, the identification of requirements for mitigation and fault tolerance, and the capability to perform design validation and verification are essential to design for compatibility with the space radiation environment. An understanding of both the functional impact of single event induced errors and their probability or rate of occurrence is necessary to establish design requirements for mitigation or tolerance provisions. Functional analysis, including the capability to analyze the propagation of error conditions, may utilize flowchart-like methods such as functional flow diagrams to provide traceability in error propagation. Identification of the path from fault occurrence to system level effects enables both an understanding of the consequences of the fault and identifies the opportunities for the application of mitigation or fault tolerance techniques. Subsystem functions, and hence the consequences of single event effects which may compromise these functions, may be categorized with regard to the criticality which they represent to the system in meeting required operational specifications. Usually, three or four criticality classifications are established for use in representing the severity of consequences of single event effects. The classifications usually comprehend the degree to which system operation is affected, the frequency which such an effect may be expected to occur, and the duration which compromised system operation is expected to persist. The most benign classification may be termed non-critical, or error-functional. This includes those effects which present little adverse consequences, occur infrequently, and do not result in long lasting affects upon system operation. This category may result from fault masking or other provisions already present within the design, or single event effects may affect data or other information determined to be non-critical. This classification usually does not require the inclusion of additional fault tolerance provisions in the design. The most serious category may be termed critical, or errorV-59

critical, and represents those effects which present unacceptable compromise to the operation of the system. Significant reduction to the rate of occurrence through fault masking provisions and the use of other detection and recovery provisions are necessary in addressing these functions. Typically one or two levels of classification are provided between these two extremes. These signify the level of criticality and response which must be present in fault tolerance provisions designed to deal with these functions. Fault tolerance in the form of detection which signifies compromised operation of the function may be adequate; limiting the duration of compromised operation by periodic reset or initialization may be adequate for these functions.

6.6.2

Validation and Verification of Fault Tolerance [Kanawati95] [Karlsson94] [Hseuh97] [Clark95]

Several approaches have been proposed and utilized to study the effects of faults in processor systems and for validating fault handling mechanisms, including analytical modeling, experimental techniques (hardware pin faults, memory corruption, and ion irradiation), simulation modeling (register transfer level, gate level, and op-code level simulation) and fault emulation (memory, bus, and register transfer level). Analytical modeling is extremely difficult due to the very large nature of the problem, and the simplifying assumptions which make the analysis tractable are regarded as compromising the usefulness of the technique and the validity of the results. Experimental techniques involve monitoring the behavior of a system until faults occur and recording the error detection and correction/recovery performance of the system. This approach requires the use of an accelerating agent to produce sufficient faults to gather statistically valid measurements on the fault tolerant performance of the system. Fault and error injection have also proven effective in measuring the effectiveness of error detection and correction/recovery properties of fault tolerant systems. In addition to the ability to measure fault tolerance, the methods provide the capability to study the consequences to system operation presented by faults which escape detection or are not afforded complete correction or recovery. Two primary methods have been utilized to perform fault injection: simulation based methods and physical injection provisions. Simulation based methods provide the capability to establish the time of occurrence, location and type of fault, and the transient or permanent characteristics of the fault. Physical injection of faults utilizes charged particles, such as heavyion fission fragments from a Californium-252 source to produce single event faults. Most fault injection experiments performed to date were not designed around a formalized methodology. Experimenters typically developed customized approaches to validate each new system. This makes it difficult to apply the specific results from individual studies to the analysis of other systems. The complexity of present systems result in the need to perform many experiments to achieve statistical confidence in the characterization test. Several fault injection tools address the need for accelerated fault injection and measurement processes; Messaline, Fiat, Ferrari, Focus, Depend, and React are the ones most discussed in the literature. Validation and verification of system performance utilizes the results of physical and/or simulated fault injection experiments to assess the coverage of faults which produce undesired system response and the ability of detection and recovery provisions to assure proper system operation. These results are utilized in an analysis technique such as Markov process modeling to make assertions regarding the availability characteristics of the system.

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6.7

Expert Systems, Fuzzy Logic, and Neural-Net Techniques [Loos94] [Velazco95] [Velazco96][Cheynet98]

The capability of expert systems, fuzzy logic, and neural-net processors has been investigated for the benefits which they might provide to fault tolerant systems and specifically to the operation of space systems. Expert systems have been used as the basis for fault tolerance provisions, utilizing recovery strategies which are selected based upon a probabilistic understanding of the options and alternatives available to the processor. Although cursed with a very whimsical title and basic elements (fuzzy-sets, -operators, -inference, and fuzzy-rules), fuzzy logic is built upon the use of multi-valued logic to define levels of a true or false assertion rather than an absolute one or zero. Fault injection experiments on a system implemented using the Weight Associative Rule Processor (WARP) showed that the majority of upsets resulted in either no effect or minor control disturbances; few resulted in loss of control function or crash of the system. An Artificial Neural Network (ANN) is a computing device inspired by observing the operation of the brain’s biological neuron. It consists of a number of simple processing elements, connected with variable weights or strengths, capable of operating in a highly parallel fashion. Fault injection experiments conducted to simulate the effects which single event upsets would produce in the memory of artificial neural net processors indicate that between 86% and 99% of injected memory errors did not provoke output errors in two ANN implementations. Fuzzy logic and neural networks potentially complement each other in their ability to provide solution to fault tolerance requirements. At the present time the commercialization of fuzzy logic and artificial neural net processor implementations has not produced high performance, aggressive functional density, and power efficient elements for general purpose use in satellite payload systems. Future work in the commercialization of these technologies may yield performance effective and SEU immune control and processing functions.

7.0

Summary

Introduction has been provided to the general characteristics of satellite telecommunications systems, including the trade studies which network systems engineering must conduct to arrive at an orbit architecture for the system. Issues present in the design of satellite systems which result from consideration of the natural space environment have been briefly discussed; in particular, the charged particle space radiation environment and its effects on devices and systems. Design for compatibility with the space radiation environment includes tolerance to mission integrated total ionizing and displacement damage effects, elimination of destructive single event effects, and applications techniques to deal with transient fault and error conditions. Fault tolerance techniques applicable to fault avoidance, masking and detection/recovery have been discussed. Fault avoidance includes provisions which attenuate the severity of the environment through consideration of alternative orbit architecture, the effectiveness of shielding, and the capability to reduce collected charge and to suppress circuit response. Fault V-61

masking includes error detection and correction strategies and redundancy techniques. Introduction to fault detection, containment, recovery, and effects criticality analysis was also presented.

8.0

Acknowledgements

The author would like to thank Dan Fleetwood, Lew Cohn, Joe Hoffman, Larry Walker, and Mark Limon for their critical reading of this manuscript and helpful suggestions.

9.0

References

[Allenspach96]

M. Allenspach, C Dachs, G.H. Johnson, R.D. Schrimpf, E. Lorfevre, J.M. Palau, J.R. Brews, K.F. Galloway, J.L. Titus, and C.F. Wheatley, “SEGR and SEB in NChannel Power MOSFETs”, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, pp2927-2931, (December 1996)

[Avizienis97]

A. Avizienis, “Toward Systematic Design of Fault-Tolerant Systems”, Computer, pp51-58, (April 1997)

[Banatre93]

Michel A. Banatre and Peter A. Lee, “Hardware and Software Architectures for Fault Tolerance, Experiences and Perspectives”

[Barth97]

Janet Barth, “Modeling Space Radiation Environments”, 1997 NSREC Short Course, (July 1997)

[Blaquiere95]

Yves Blaquiere, Gabriel Gagne, Yvon Savaria, and Claude Evequoz, “A New Efficient Algorithm-Based SEU Tolerant System Architecture”, IEEE Transactions on Nuclear Science, Vol. 42, No. 6, (December 1995)

[Calin96]

T. Calin, M. Nicolaidis, R. Velazco, “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, pp2874-2878, (December 1996)

[Chen95]

Ing-Ray Chen and I.-Ling Yen, “Analysis of Probablistic Error Checking Procedures on Storage Systems”, The Computer Journal, Vol. 38, No. 5, (1995)

[Chenette94]

D.L. Chenette, J. Chen, E. Clayton, T.G. Guzik, J.P. Wefel, M. Garcia-Munoz, M. Garcia-Munoz, C. Lapote, K.R. Pyle, K.P. Ray, E.G. Mullen, and D.A. Hardy, “The CRRES/SPACERAD Heavy Ion Model of the Environment (CHIME) for Cosmic Ray and Solar Particle Effects on Electronic and Biologic Systems in Space”, IEEE Transactions on Nuclear Science, Vol. 41, No. 6, pp2332-2339 (December 1994)

All References are Unclassified

V-62

[Cheynet98]

Ph. Cheynet, R. Velazco, Rezgui, L. Peters, K. Beck, and R. Ecoffet, “Digital Fuzzy Control: a Robust Alternative Suitable for Space Application”, IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp2941-2947, (December 1998)

[Clark95]

Jeffrey A. Clark and Dhiraj K. Pradhan, “Fault Injection: A Method for Validating Computer-System Dependability”, Computer, pp47-56, (June 1995)

[Daly96]

E.J. Daly, J. Lemaire, D. Heynderickx, and D.J. Rodgers, “Problems With Models of the Radiation Belts”, IEEE Transactions on Nuclear Science, Vol. 43, No. 2, pp403-415, (April 1996)

[Dressendorfer98]

Paul V. Dressendorfer, “Basic Mechanisms for the New Millenium”, 1998 IEEE Nuclear and Space Radiation Effects Short Course, (July 1998)

[Dyer98]

Clive Dyer, “Space Radiation Environment Dosimetry”, IEEE Nuclear Science and Space Radiation Effects Short Course, (July 1996)

[Evans98]

Andrew L. Evans, John S. Rose, and Ramesh Venkataraman, “The Future of Satellite Communications”, The McKinsey Quarterly, No. 2, (1998)

[Fleetwood95]

Daniel M. Fleetwood, “A First-Principles Approach to Total-Dose Hardness Assurance”, IEEE Nuclear Science and Space Radiation Effects Short Course, (July 1995)

[Frederickson96]

A.R. Frederickson, “Upsets Related To Spacecraft Charging”, IEEE Transactions on Nuclear Science, Vol. 43, No. 2, pp426–441, (April 1996)

[Fujiwara90]

Eiji Fujiwara and Dhiraj K. Pradhan, “Error-Control Coding in Computers”, Computer, (July 1990)

[Givens98]

F. Lynwood Givens, “The Technology and Business of High-Resolution Imaging“, Launchspace, Vol. 3, No. 6, (December 1998)

[Gordon93]

Gary D. Gordon and Walter L. Morgan, Principles of Communications Satellites, John Wiley & Sons, (1993)

[Gussenhoven93]

M.S. Gussenhoven, E.G. Mullen, M. D. Violet, C. Hein,J. Bass, and D. Madden, “CRRES High Energy Proton Flux Maps”, IEEE Transactions on Nuclear Science, Vol. 40, No. 6, pp1450-1457, (December 1993)

[Gussenhoven97]

M.S. Gussenhoven, E.G. Mullen, T.J. Bell, D. Madden, and E. Holeman, “APEXRAD: Low Altitude Orbit Dose as a Function of Inclination, Magnetic Activity and Solar Cycle”, IEEE Transactions on Nuclear Science, Vol. 44, No. 6, pp2161-2168, (December 1997)

All References are Unclassified

V-63

[Holbert96]

Keith E. Holbert, “Spacecraft Charging: A Review”, ASU Internal Report, (1996)

[Hseuh97]

Mei-Chen Hseuh, Timothy K. Tsai, and Ravishankar K Iyer, “Fault Injection Techniques and Tools”, Computer, pp75-82, (April 1997)

[Huston98]

S.L. Huston and K.A. Pfitzer, “Space Environmental Effects: Low-Altitude Trapped Radiation Model”, NASA/CR-1998-208593, (August 1998)

[ITU98]

International Telecommunications Union, http://www.itu.int

[Jamalipour98]

Abbas Jamalipour, Low Earth Orbital Satellites for Personal Communication Networks, Artech House, (1998)

[Johnson96]

Gregory H. Johnson and Kenneth F. Galloway, “Catastrophic Single-Event Effects in the Natural Space Environment”, IEEE Nuclear Science and Space Radiation Effects Short Course, (July 1996)

[Kanawati95]

Ghani A. Kanawati, Nasser A. Kanawati, and Jacob A. Abraham, “FERRARI: A Flexible Software-Based Fault and Error Injection System”, IEEE Transactions on Computers, pp248-260, (February 1995)

[Karlsson94]

Johan Karlsson, Peter Linden, Peter Dahlgren, Rolf Johansson, and Ulf Gunneflo, “Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms”, IEEE Micro, pp8-23, (February 1994)

[Katz97]

R. Katz, K. LaBel, J.J.Wang, B. Cronquist, R. Koga, S. Penzin, and G. Swift, “Radiation Effects on Current Field Programmable Technologies”, IEEE Transactions on Nuclear Science, Vol. 44, No. 6, pp1945-1956 (December 1997)

[Kim92]

K.H. Kim and Howard O. Welch, “Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in RealTime Applications”, Fault-Tolerance Systems: Techniques and Applications, edited by Hoang Phan, pp95-105, (1992)

[Kinnison98]

James D. Kinnison, “Achieving Reliable, Affordable Systems”, IEEE Nuclear Science and Space Radiation Effects Short Course, (July 1998)

[Koga97]

R. Koga, S.H. Penzin, K.B. Crawford, and W.R. Crain, “Single Event Functional Interrupt (SEFI) Sensitivity in Microcircuits”, Fourth European Conference on Radiation and its Effects on Components and Systems”, pp311-318, (September 1997)

[LaBel961]

Kenneth A. LaBel and Michele M. Gates, “Single-Event-Effect Mitigation from a System Perspective”, IEEE Transactions on Nuclear Science, Vol. 43, No. 2, (April 1996)

[LaBel962]

Kenneth LaBel, Michele Gates, Janet Barth, E.G. Stassinopoulos, Allan Johnston and Paul Marshall, “Single Event Criticality Analysis (SEECA)”, http://flick.gsfc.nasa.gov/radhome/papers All References are Unclassified

V-64

[LaBel98]

K.A. LaBel, P.W. Marshall, J.L. Barth, R.B. Katz, R.A. Reed, H.W. Leidecker, H.S. Kim, and C.J. Marshall, “Anatomy of an In-Flight Anomaly: Investigation of Proton-Induced SEE Test Results for Stacked IBM DRAMs”, IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp2898-2903, (December 1998)

[Layton97]

P.J. Layton, D.R. Czajkowski, J.C. Marshall, H.F.D. Anthony, and R.W. Boss, “Single Event Latchup Protection of Integrated Circuits”, Fourth European Conference on Radiation and its Effects on Components and Systems, pp327-331, (September 1997)

[Lin83]

Shu Lin and Daniel J. Costello, Jr., “Error Control Coding – Fundamentals and Applications”, Prentice-Hall, (1983)

[Liu92]

M. Norely Liu, and Sterling Whitaker, “Low Power SEU Immune CMOS Memory Circuits”, ”, IEEE Transactions on Nuclear Science, Vol. 39, No. 6, pp1679-1684, (December 1992)

[Loftus97]

Loftus, J.P., “Feedback Department”, Launchspace, vol. 2, no. 2, pp10, (June/July97)

[Loos94]

James R. Loos, “Fuzzy Logic and Neural Networks”, Intech, pp26-29, (November 1994)

[Majewski95]

P.P. Majewski, E. Normand, and D.L. Oberg, “A New Solar Flare Heavy Ion Model and Its Implementation Through MACREE, An Improved Modeling Tool to Calculate single Event Effects Rates in Space”, IEEE Transactions on Nuclear Science, Vol. 42, No. 6, pp2043-2050, (December 1995)

[Marshall951]

P.W. Marshall, C.J. Dale, T.R Weatherford, M. LaMacchia, and K.A. LaBel, “Particle-Induced Mitigation of SEU Sensitivity in High Data Rate GaAs HIGFET Technologies”, IEEE Transactions on Nuclear Science, Vol. 42, No. 6, pp1844-1849, (December1995)

[Marshall952]

P.W. Marshall, C.J. Dale, T. Weatherford, M. Carts, D. McMorrow, A. Peczalski, S. Baier, J. Hohava, and J. Skogen, “Heavy Ion SEU Immunity of a GaAs Complementary HIGFET Circuit Fabricated on a Low Temperature Grown Buffer Layer”, IEEE Transactions on Nuclear Science, Vol. 42, No. 6, pp1850-1855, (December1995)

[Mavis98]

D.G. Mavis and P.H. Eaton, “Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits”, Mission Research Corporation Technical Report P8111.29, (October 1998)

[McMillin97]

Bruce M. McMillin, “Fault Tolerance for Multicomputers: The Application Oriented Paradigm”, Department of Computer Science, University of MissouriRolla, (1997)

All References are Unclassified

V-65

[Mitsubishi99]

“Mitsubishi Electric Develops High-Frequency Synchronous SRAM with Dramatically Reduced Soft Error Rate”, International Solid-State Circuits Conference, (February 1999), http://www.mitsubishichips.com/press/releases/fsram_99.html

[Nelson90]

Victor P. Nelson, “Fault-Tolerant Computing: Fundamental Concepts”, Computer, pp 19-25, (July 1990)

[Peercy93]

Michael Peercy and Prithviraj Banerjee, “Fault Tolerant VSLI Systems”, Proceedings of the IEEE, pp745-758, (1993)

[Petersen97]

Edward Petersen, “Single Event Analysis and Prediction”, IEEE Nuclear and Space Radiation Effects Conference Short Course, (July 1997)

[Plank97]

James S. Plank, “A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like Systems”, Software – Practice and Experience”, Vol. 27(9), (1997)

[Purvis93]

C.K. Purvis, “Overview From a Systems Perspective”, The Behavior of Systems in the Space Environment, edited by R.N. DeWitt, D. Duston, and A.K. Hyder, Kluwer Academic Publishers, (1993)

[Richharia95]

M. Richharia, “Satellite Communication Systems Design Principles”, McGrawHill, (1995)

[Rockett88]

L. Rockett, “An SEU Hardened CMOS Data Latch Design”, IEEE Transactions on Nuclear Science, Vol. 35, No. 6, pp1682-1687, (December 1992)

[Rubino95]

Gerardo Rubino and Bruno Sericola, “Internal Availability Analysis Using Denumerable Markov Processes: Application to Multiprocessor Subject to Breakdowns and Repair”, IEEE Transactions on Computers, pp286-291, (February 1995)

[Saxena95]

Nirmal R. Saxena, Chih-Wei David Cahng, Kevin Dawallu, Jaspal Kohli, and Patrick Helland, “Fault-Tolerant Features in the HaL Memory Management Unit”, IEEE Transactions on Computers, pp170-180, (February 1995)

[SIA98]

Satellite Industry Association, “The US Satellite Industry; An Historical Perspective”, http://www.sia.org

[Smith94]

E.C. Smith, “Effects of Realistic Satellite Shielding on SEE Rates”, IEEE Transactions on Nuclear Science, Vol. 41, No. 6, pp2396-2399, (December 1994)

[Somani97]

A.K. Somani and N.H. Viadya, “Understanding Fault Tolerance and Reliability”, Computer, pp 45-50, (April 1997)

[Sosnowski94]

Janusz Sosnowski, “Transient Fault Tolerance in Digital Systems”, IEEE Micro, (1994)

All References are Unclassified

V-66

[Stapor95]

William J. Stapor, “Single Event Effects (SEE) Qualification”, IEEE Nuclear and Space Radiation Effects Conference Short Course, (July 1995)

[Tribble95]

Alan C. Tribble, The Space Environment – Implications for Spacecraft Design, Princeton University Press, (1995)

[Tso93]

Kam S. Tso, Myron Hecht, and Neville I. Maxwell, “Fault-Tolerant Robotic System for Critical Applications”, (1993)

[Tylka97]

A.J. Tylka, J.H. Adams, Jr., P.R. Boberg, B Brownstein, W.F. Dietrich, E.O. Flueckiger, E.L. Peterson, M.A. Shea, D.F. Smart, and E.C. Smith,”CREME96: A Revision of the Cosmic Ray Effects on Microelectronics Code”, IEEE Transactions on Nuclear Science, Vol. 44, No. 6, pp2150-2160 (December 1997)

[Vaidya96]

Natin H. Vaidya, “Comparison of Duplex and Triplex Memory Reliability”, IEEE Transactions on Computers, Vol. 45, No. 4, pp503-507, (1996)

[Velazco95]

R. Velazco, A. Assoum, N.E. Radi, R. Ecoffet, and X. Botey, “SEU Fault Tolerance in Artificial Neural Networks”, IEEE Transactions on Nuclear Science, Vol. 42, (December 1995)

[Velazco96]

R. Velazco, A Assoum, Ph. Cheynet, M. Olmos, and R. Ecoffet, “SEU Experiments on an Artificial Neural Network Implemented by Means of Digital Procesors”, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, pp1856-1862, (December 1996)

[Vinson92]

James Edwin Vinson, “Circuit Reliability of Memory Cells with SEU Protection”, IEEE Transactions on Nuclear Science, Vol. 39, No. 6, pp1671-1678, (December 1992)

[Whalen98]

David J. Whalen, “Communications Satellites: Making the Global Village Possible”

[Wood97]

Alan Wood, “Availability in the Real World”, The Twenty-Seventh International Symposium on Fault-Tolerant Computing, Tutorial 2, (1997)

[Wood98]

L. Wood, “A Networking Perspective on Satellite Constellations”, http://www.ee.surrey.ac/Personal/L.Wood

All References are Unclassified

V-67