2003 IEEE NSREC Nuclear and Space Radiation Effects Conference Short Course Notebook Radiation Effects in Advanced Commercial Technologies: How Device Scaling has Affected the Selection of Spaceborne Electronics
July 21, 2003 Sponsored by: IEEE/NPSS Radiation Effects Committee Supported by: Defense Threat Reduction Agency Sandia National Laboratories Air Force Research Laboratory NASA Electronic Parts and Packaging Program Approved for public release; distribution is unlimited
2003 IEEE Nuclear and Space Radiation Effects Conference
Short Course Notebook
Radiation Effects in Advanced Commercial Technologies: How Device Scaling has Affected the Selection of Spaceborne Electronics
July 21, 2003 Monterey, California
Copyright 2003 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. For all other copying, reprint, or replication permission, write to Copyrights and Permissions Department, IEEE Publishing Services, 445 Hoes Lane, Piscataway, NJ 08855-1331
2003 IEEE NSREC Short Course
Section I
INTRODUCTION Joseph M. Benedetto MRC Microelectronics
INTRODUCTION This Short Course Notebook contains the manuscripts prepared by the instructors in conjunction with the 2003 IEEE Nuclear and Space Radiation Effects Conference (NSREC) Short Course. The course was held on July 21, 2003 in Monterey California and was the 24th time the NSREC provided this type of Short Course. This notebook is intended to be a companion to the oral presentations of the instructors as well as a stand-alone reference for members of the radiation effects community. Recent changes in commercial semiconductor processing have lead to an enhanced level of intrinsic radiation hardness of electronic devices designed and manufactured for the consumer or industrial market. For example, ultra-thin gate oxides used in 0.25µm and smaller feature size semiconductor processes are now inherently immune to total ionizing radiation effects to levels tens of times what is required for most space or satellite systems. Many commercial shallow trench isolation (STI) process are sufficiently hard to allow their use in many space environments. These two changes (thin-gate oxide and STI) alone account for much of the improved total dose hardness of commercial product. Only a few years ago it was very difficult (if not impossible) to find commercially fabricated complementary metal oxide semiconductor (CMOS) devices that could withstand the natural space radiation environment. Many commercial static random access memories (SRAMs), with densities of only 256kbits would fail a total dose irradiation at less than 10krad(Si). Now it is now fairly common to find the same high-density SRAM, DRAM or Flash memory device types found in a desktop PC or cell phone also being used for a LEO or GEO satellite system. While advanced semiconductor processing has opened up the door for the use of commercial components in space, it has also brought up a number of new issues and concerns, including the introduction of new materials, device structures and radiation-induced degradation modes. The 2003 IEEE NSREC Short Course, “RADIATION EFFECTS IN ADVANCED COMMERCIAL TECHNOLOGIES: HOW DEVICE SCALING HAS AFFECTED THE SELECTION OF SPACEBORNE ELECTRONICS,” is intended to provide the necessary set of information to better understand the numerous changes which have arisen with advanced component fabrication technologies and how these changes impact the radiation response and reliability of spaceborne electronics. The Short Course begins with a description of advanced CMOS processes, including process history, scaling and proven design hardness techniques. There is a tremendous opportunity to use commercial fabrication facilities not only for the production of radiation tolerant components but also for the study of new basic mechanisms and materials. The second part of the Short Course focuses on the challenges and opportunities involved with the new ultra-thin oxides from a radiation and reliability viewpoint. The third section shifts to describe how advanced technologies have affected single event effects of CMOS technology. For the fourth and final segment of this Short Course we leave CMOS technology and focus on total dose and single event effects of advanced bipolar devices and processes.
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This Short Course Notebook is divided into five sections as follows: Section I, “INTRODUCTION,” the motivation for and an overview of this Short Course theme and topics are provided. The biographies of the instructors/authors are included at the end of this introduction. In Section II, “CMOS SCALING, DESIGN PRINCIPLES AND HARDENING-BYDESIGN METHODOLOGIES,” Ronald Lacoe of the Aerospace Corporation describes relevant changes in CMOS processing over the last 20-years with respect to utilizing CMOS components in stressing radiation environments. He first provides an overview of CMOS processing and associated scaling, and the impact of this scaling on various performance parameters. This leads into a discussion on the recent trends in the effects of radiation on advanced commercial CMOS processes, and why this has created an opportunity for using these processes unmodified, with the necessary hardness built into the component by use of only design techniques. The specific techniques for the application of this “Hardened-By-Design” (HBD) approach will be described in detail. Finally, issues associated with the reliability and qualification of components fabricated using the HBD approach are discussed. In Section III, “RADIATION RESPONSE AND RELIABILITY OF OXIDES USED IN ADVANCED PROCESSES,” by Alessandro Paccagnella of the University of Padova will examine how thin gate oxides react to radiation damage. In the first step in this direction he examines the behavior of 10-nm oxides used as tunnel dielectric in non-volatile memory cells, presenting evidence of simultaneous leakage current and charge trapping. By thinning the oxide layer radiation induced leakage current and radiation-induced breakdown will then appear as the reliability challenge relevant to radiation damage, replacing charge trapping. Synergetic effects of radiation damage and electrical stresses have been recently investigated and are presented along with emerging issues on new replacement materials for silicon oxide. In Section IV, “HOW DEVICE SCALING AFFECTS SINGLE EVENT EFFECTS SENSITIVITY,” by Timothy R. Oldham of NASA GSFC/QSS Group, Inc. discusses that the very existence of Single Event Effects (SEE) is a consequence of scaling. Long-time NSREC attendees can remember when there were no SEEs, because device sizes had not been scaled down enough for a single particle to have any detectable effect. Dr. Oldham reviews how scaling has led to SEE, and how scaling will most likely affect SEE in the near future. He reviews the basic mechanisms of charge deposition and collection, and device and circuit effects. He gives particular emphasis to steps the commercial semiconductor industry is taking to harden commercial off the shelf (COTS) technology against alpha particles, which are a major driver in the commercial sector. In Section V, “RADIATION EFFECTS IN SiGe HBT BICMOS TECHNOLOGY,” by John Cressler of Georgia Tech he focuses on advanced Si-based bipolar technology for space applications, primarily in the form of SiGe HBT technology. After an introduction to SiGe strained layer epitaxy, and its use in SiGe HBT design, Dr. Cressler presents a detailed assessment of the impact of radiation on SiGe HBTs and circuits, including dc and ac
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degradation mechanisms, proton energy and gamma dose rate effects, scaling issues, single event upset, and future directions for the technology. I would personally like to thank each of the Short Course Instructors, Ron Lacoe, Alessandro Paccagnella, Tim Oldham and John Cressler for their considerable efforts to ensure a successful 2003 IEEE NSREC Short Course. The preparation of the Short Course Materials, both the presentation and this manuscript requires a tremendous amount of time, expertise and hard work and serves as a great resource for the radiation effects community. I would also like to thank Lew Cohn for his efforts in reviewing the Short Course manuscripts and ensuring that this years Short Course Notebook was published and delivered in time to present to the attendees at the 2003 IEEE NSREC. In addition, I would like to thank Dale Platteter for collecting and assembling the electronic versions of the Short Course and overseeing the periodic distribution of the entire NSREC Short Course collection on CD-ROM. Joe Benedetto Colorado Springs, Colorado
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BIOGRAPHIES Joseph Benedetto MRC Microelectronics Joseph M. Benedetto received his B.S. in Physics from the State University of New York and his M.S.E.E. and Ph.D. degrees from the University of Maryland. Dr. Benedetto began his career in radiation effects over 20 years ago as a Graduate Research Fellow at the National Bureau of Standards. From 1983 to 1995 he performed basic and applied research for the US Army Research Laboratory. Between 1995 and 2002, Dr. Benedetto served as Standard Product Technology Manager for Aeroflex UTMC and beginning in 2003, he joined Mission Research Corporation Microelectronics Division as the Director of Radiation Effects Engineering. During the past several years Dr. Benedetto has been very active developing new methods for hardening commercial foundries and qualifying commercial integrated circuits for spaceborne applications. Dr. Benedetto has been very active in the radiation effects community, serving in various conference roles within the Nuclear and Space Radiation Effects Conference (Finance Chairman, Local Arrangements Chairman and Short Course Chairman) and was recently elected to the IEEE Nuclear and Plasma Sciences ADCOM. He has published over 75 articles in a wide variety of publications, including IEEE Spectrum, IEEE Transactions on Nuclear Science and the Journal of Applied Physics. To date he has been awarded 2 US Patents and has several more patents pending related to hardening spacecraft electronics. Dr. Benedetto is a Senior Member of the IEEE, Member of the IEEE Nuclear and Plasma Sciences Society and Sigma Pi Sigma. Ronald Lacoe Aerospace Corporation Ronald Lacoe received his B.S., M.S., and Ph.D. in Physics from the University of California, Los Angeles in 1974, 1977, and 1983, repectively. He attended graduate school as a Hughes Aircraft Fellow and worked at the Hughes Research Laboratory in Malibu, California while earning his Ph.D. degree. After receiving his Ph.D., Dr. Lacoe was a joint NSF/CNRS Fellow at the University of Paris-South from 1984-1986, where he worked on reduced-dimensional systems and organic superconductivity. Dr. Lacoe joined The Aerospace Corporation in 1987 as Member of the Technical Staff and is currently the Manager of the Microelectronics Reliability and Radiation Effects Section of the Microelectronics Technology Department. He is responsible for research in the areas of microelectronics reliability and radiation hardness for microelectronics that will be employed in Air Force space programs. Recently, Dr. Lacoe has published extensively on the use of commercial microelectronics processes for fabricating radiation-hardened components for space. Dr. Lacoe has published over one hundred papers, and was the recipient of the 1997 IEEE International Reliability Physics Symposium’s Best Paper Award, the 1997 NSREC Meritorious Paper Award and the 1998 NSREC Outstanding Paper Award.
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Alessandro Paccagnella University of Padova Alessandro Paccagnella received the Laurea degree in Physics cum Laude in 1983 from the University of Padova, Italy. Then his academic career developed at the Universities of Modena, Trento, Cagliari, and Padova, where he is currently Full Professor of Electronics. In the past he studied different aspects of physics, technology, and reliability of III-V devices and he spent some research periods at the University of California, San Diego, and at the IBM T.J. Watson Research Center, Yorktown Heights, NY. At present, he coordinates the research activity of a group at the University of Padova working on CMOS devices and technology, with a particular attention to ionizing radiation effects on ultra-thin gate oxides, floating gate memory cells, silicon microstrip detectors, power MOSFETs, and programmable logic devices. Dr. Paccagnella has coauthored more than 220 scientific papers, and about 130 of them have been published on international journals. He has co-authored works, which received awards at ESREF 1992, ESREF 1998, NSREC 1999 and ESSDERC 2000. He is a member of the IEEE NPSS and EDS societies and of the Association RADECS. Timothy R. Oldham NASA GSFC/QSS Group, Inc. Timothy R. Oldham received his B.S. from Michigan State University (1969), his M.S. from American University (1975), and his Ph. D. from Catholic University of America (1982), all in Physics. He started as a summer student, and worked at the Army Research Laboratory and its predecessors, for more than 34 years, on a variety of radiation and electronics reliability research problems. Recently, he has joined the Radiation Effects and Analysis Group at the NASA Goddard Space Flight Center, as a contractor with QSS Group, Inc. He has been elected Fellow of the IEEE for his technical contributions, which are documented in more than 30 journal articles, plus a book and a book chapter. Most of this work was first presented at this conference. He has served as Technical Program Chairman for the NSREC (1990), as General Conference Chairman (1994), as Awards Chairman (2001), and as an Editor for the conference issue of the Transactions on Nuclear Science (TNS) (1997-1999). Recently, he was one of three editors for the special TNS issue commemorating this 40th NSREC. John D. Cressler Georgia Tech John D. Cressler received the B.S. degree in physics from the Georgia Institute of Technology, Atlanta, GA in 1984, and the M.S. and Ph.D. degrees in applied physics from Columbia University, New York, NY in 1987 and 1990. From 1984 to 1992 he was on the research staff at the IBM Thomas J. Watson Research Center in Yorktown Heights, NY, working on high-speed Si and SiGe bipolar devices and technology. In 1992 he left IBM Research to join the faculty at Auburn University, Auburn, AL, where he served until 2002. When he left Auburn he was Philpott-Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and Director of the Alabama Microelectronics Science and Technology Center. In 2002 he joined the faculty at Georgia Tech, where he is currently Professor of Electrical and Computer Engineering. His research interests include: SiGe devices and
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technology, Si-based RF/microwave/mm-wave devices and circuits, radiation effects, noise and linearity, cryogenic electronics, SiC devices, reliability physics, 2-D/3-D device-level simulation, and compact circuit modeling. Dr. Cressler has published over 250 technical papers related to his research. He is the author of the book (with Guofu Niu) Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, 2002. He was Associate Editor for the IEEE Journal of Solid-State Circuits (1998-2001), and has been recently appointed Assistant Guest Editor of the IEEE Transactions on Nuclear Science. He served on the Technical Program Committees of the IEEE International Solid-State Circuits Conference (1992-1998, 1999-2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995-1999), the IEEE International Electron Devices Meeting (1996-1997), and the IEEE Nuclear and Space Radiation Effects Conference (2000, 2002). He was the Technical Program Chairman of the 1998 IEEE International Solid-State Circuits Conference (attendance of 3000+). He currently serves on the Executive Steering Committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as International Advisor for the IEEE European Workshop on Low-Temperature Electronics, and on the Technical Program Committee for the IEEE International SiGe Technology and Device Meeting. He was appointed an IEEE Electron Device Society Distinguished Lecturer in 1994, and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program, the 1996 C. Holmes MacDonald National Outstanding Teacher Award by Eta Kappa Nu, the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, and an IEEE Third Millennium Medal in 2000. Dr. Cressler was elected an IEEE Fellow in 2001 for “contributions to the understanding and optimization of silicon and silicon-germanium bipolar transistors.”
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2003 IEEE NSREC Short Course
Section II
CMOS SCALING, DESIGN PRINCIPLES AND HARDENING-BY-DESIGN METHODOLOGIES
Ronald Lacoe The Aerospace Corporation
CMOS SCALING, DESIGN PRINCIPLES AND HARDENING-BYDESIGN METHODOLOGIES
Ronald C. Lacoe The Aerospace Corporation El Segundo, CA 90245-4691
This work was sponsored by The Aerospace Corporation’s Aerospace Sponsored Research Program. Aerospace operates a Federally Funded Research and Development Center (FFRDC) for the Department of Defense (DoD).
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CMOS SCALING, DESIGN PRINCIPLES AND HARDENIG-BY-DESIGN METHODOLOGY Ronald C. Lacoe The Aerospace Corporation Microelectronics Technology Department P.O. Box 92957, M2/244 Los Angeles, CA 90245 (310) 336-0118
[email protected] 1 2
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Introduction …………………………………………………………………….. II-5 Commercial CMOS Scaling …………………………………………………….. II-6 2.1 Introduction ……………………………………………………………….. II-6 2.2 CMOS Basics …………………………………………………………….. II-6 2.3 CMOS Scaling ……………………………………………………………. II-9 2.3.1 Moore’s Laws …………………………………………………….. II-17 2.3.2 Gate-Oxide Scaling ………………………………………………. II-19 2.3.3 Deviations from “Classic” Scaling ………………………………. II-22 2.3.4 Intel’s 90-nm Process …………………………………………….. II-24 2.4 Future Direction and Challenges to Maintaining Moore’s Law Growth …. II-26 2.5 Opportunities for Leveraging Commercial Microelectronics for Space Applications ………………………………………………………………. II-32 2.6 Conclusion ………………………………………………………………... II-34 Overview of the Space Environment …………………………………………… II-36 3.1 Introduction ……………………………………………………………….. II-36 3.2 Natural Space Environment ………………………………………………. II-36 3.3 Summary ………………………………………………………………….. II-40 Total Does Effects on Commercial CMOS Processes ………………………….. II-41 4.1 Introduction ……………………………………………………………….. II-41 4.2 Interaction of Electrons, Protons and Photons with Solids ……………….. II-42 4.2.1 Electron-Hole Statistics in SiO2 …………………………………...II-42 4.3 Simplified Description of Total-Dose-Induced Charge Transport in MOS Oxides …………………………………………………………………….. II-44 4.3.1 Electron-Hole Pair Recombination ……………………………….. II-44 4.3.2 Hole Transport Toward SiO2/Si Interface ………………………. II-45 4.3.3 Tunneling, Deep Hole Trapping, and Interstate Formation at the Interface …………………………………………………………... II-46 4.3.3.1 Tunneling ……………………………………………….. II-46 4.3.3.2 Oxide Trapped Charge ………………………………….. II-47 4.3.3.3 Interface States ………………………………………….. II-49 4.3.4 Summary ………………………………………………………….. II-49
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Effect of Trapped-Oxide and Interface-State Charge on MOS Performance II-51 4.4.1 Threshold Voltage Shifts …………………………………………. II-51 4.4.2 Radiation-Induced Gate-Oxide Threshold Voltage Shifts in Commercial CMOS Processes …………………………………… II-53 4.4.3 Radiation-Induced Transconductance and Subthreshold Swing Changes in Commercial CMOS Processes ……………………..... II-60 4.4.4 Radiation-Induced Leakage in CMOS Devices and Circuits …….. II-63 4.4.4.1 Overview of Radiation-Induced Edge Leakage in CMOS Devices and Circuits ………………………………………... II-63 4.4.4.2 Radiation-Induced Edge Leakage for Commercial CMOS Processes ……………………………………………….…... II-67 4.4.4.3 Radiation-Induced Inter-Device Leakage for Commercial CMOS Processes …………………………………………… II-73 4.5 Summary ………………………………………………………………….. II-76 Designing in Radiation Hardness ……………………………………………….……. II-77 5.1 Introduction ……………………………………………………………….. II-77 5.2 Designing in Total Dose Hardness ………………………………………... II-77 5.2.1 Mitigating Intra-Device Leakage …………………………………. II-78 5.2.2 Mitigating Inter-Device Leakage …………………………………. II-85 5.2.3 Evaluation of Area and Performance Penalties ……………………II-86 5.2.4 Summary of Designing in Total Dose Hardness ………………….. II-90 5.3 Single Event Effects ………………………………………………………. II-90 5.3.1 Single Event Upset ………………………………………………...II-91 5.3.1.1 Basic Mechanisms ………………………………………….. II-91 5.3.1.2 Single-Event Upsets in SRAMs ……………………………. II-93 5.3.1.3 Designing In SEU Hardness – Charge Dissipation Techniques ………………………………………………….. II-96 5.3.1.4 Designing In SEU Hardness – Spatial Redundancy ………... II-98 5.3.1.5 Error Correction Techniques ………………………………... II-104 5.3.2 Single Event Transients …………………………………………... II-105 5.3.2.1 Designing in Single Event Transient Hardness …………….. II-109 5.3.3 Single Event Latchup …………………………………………….. II-111 5.3.3.1 Designing In Single Event Latchup Hardness ……………… II-113 5.3.4 Single Event Functional Interrupts ……………………………….. II-116 5.3.5 Summary of Single Event Effects and Mitigation Techniques …… II-116 5.4 Cell Libraries …………………………………………………………...… II-116 5.5 CAD Tools …………………………………………………………….….. II-118 5.6 Approaches to Using HBD ……………………………………………….. II-119 5.7 Examples Components Fabricated Using HBD Approaches ……………... II-121 5.8 COTS and HBD …………………………………………………………... II-122 5.9 Summary ………………………………………………………………….. II-123 Qualification and Reliability …………………………..……………………….……. II-124 6.1 Introduction …………………………………………………………….… II-124 6.2 Qualification ……………………………………………………………. II-124 6.3 Reliability …………………………………………………………………. II-125 II-3
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6.3.1 Designing in Hot-Carrier Reliability ……………………………... II-125 6.3.2 Reducing the Supply Voltage ……………………………………... II-127 6.3.3 Reducing the Clock Frequency …………………………………… II-128 6.3.4 Increasing the Channel Length …………………………………… II-128 6.3.5 Optimize Load Capacitance ………………………………………. II-129 6.3.6 Optimize Edgeless Device Design ………………………………... II-129 6.4 Summary ………………………………………………………………….. II-133 Summary …………………………………………………………………….…. II-134 Acknowledgements ……………………………………………………………... II-134 References ………………………………………………………………………. II-135
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1 Introduction The traditional method of achieving radiation hardness in space-qualified electronics has involved the use of specialized radiation-hardened manufacturing processes developed specifically for space applications. These dedicated “rad-hard” foundries have successfully supplied hardened components for many space systems. However, the inherent added complexity of these specialty processes combined with their low-volume demand has led to an inevitable gap in the performance of available components for space use compared with contemporary commercial parts. Continued improvement in the performance of commercial and military satellite systems will depend critically on the rate of insertion of advanced microelectronics technologies into these systems. While many national defense space systems will continue to rely on radiation-hardened components from “rad-hard” foundries to meet their requirements, many commercial and military space missions can make effective use of radiation-tolerant and radiation-hardened components using commercial foundries with the application of “hardness-by-design” approaches to achieve the required radiation hardness. This approach directly leverages the commercial microelectronics infrastructure and offers the potential of added performance with respect to the “rad-hard foundries.” This short course will address the history and current state of the commercial CMOS microelectronics industry, provide a compact description of the space environment and will review total-dose and single-event effects basic mechanisms. This will include a description of the transition from thick gate-oxides to thin gate-oxides, and the implication of this transition on total-dose effects and the potential for designing in total-dose hardness. This short course will also describe the trend in commercial CMOS processes toward increased total-dose hardness. The remainder of this short course will describe specific design techniques to mitigate the entire spectrum of radiation effects in CMOS microelectronics. This includes design methodology to mitigate intra- and inter-device leakage, single-event upset, single-event transients and single-event latchup. The applications of these “hardnessby-design” techniques are often accompanied by area, power and other performance penalties. These penalties will be discussed for each specific mitigation strategy. In addition, the role of cell libraries and issues surrounding their development will be discussed, as well as various approaches for applying “hardness-by-design” principles and the role of “hardness-by-design” for COTS components. Issues related to the qualification and reliability of radiation-hardened components fabricated at a commercial foundry will be discussed. Design techniques to extend reliability lifetimes beyond those guaranteed by the foundry will also be presented. This short course is focused on digital CMOS microelectronics. Analog and mixedsignal issues will not be discussed here, and is left for a future short course. The goal of this short course is to provide the reader with a self-contained presentation that allows the reader to understand the current state of commercial CMOS microelectronics technology, the key radiation effects and the underlying basic mechanisms, the trend in commercial CMOS technologies toward increased total-dose hardness, and the suite of design techniques that can mitigate these radiation effects. The author hopes the reader will find this short course is successful in achieving these goals.
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2 Commercial CMOS Scaling 2.1 Introduction The incredibly rapid growth in the performance and throughput of CMOS integrated circuits over the last thirty years has led to a microelectronics revolution that has profoundly changed the world. This widespread adaptation of digital microelectronics has changed nearly every aspect of the world we live in. It has affected world economies, influenced the world geopolitical landscape, and has changed the day-to-day lives of most of the world’s inhabitants. It is directly responsible for the rapid growth of computer technology and the growth of the Internet. In this chapter, a brief history of the evolution of CMOS devices and integrated circuits will be presented. Key material changes and process modifications enabling this rapid growth will be discussed. The evolution of CMOS technology and various performance and process parameters will be described quantitatively, including an historical description of Moore’s Laws. Examples of the next generation CMOS technology will be given, showing an SRAM cell that is only 1 µm2. Some of the challenges that must be faced to successfully transition to future technology nodes will be discussed. Finally, the opportunities to directly leverage commercial CMOS technology for the fabrication of space qualified components as an additional option to the approach most used over the last two decades, fabricating space qualified components at foundries dedicated to producing radiation-hardened components, will be broadly discussed. 2.2 CMOS Basics A schematic diagram of an MOS transistor is shown in Figure 2.1. MOS stands for metal-oxide-semiconductor. In figure 2.1, the MOS structure is composed of the gate “metal”, the gate oxide, and the p-silicon substrate. The silicon region at the gate-oxide/silicon interface is referred to as the channel, and the distance between source and the drain is referred to as the channel length. The source/channel/drain effectively form oppositely oriented n-p and p-n diodes in series. Hence, regardless of the voltage applied between the source and drain, only reverse leakage current can flow through the channel. The fundamental characteristic of MOS devices is that for an NMOS transistor, when the gate is biased sufficiently high to bend the band structure at the gate-oxide/silicon interface, the p-channel becomes inverted and effectively has been transformed to n-type silicon. The corresponding transition from n-type to p-type occurs in a PMOS transistor when the gate is biased low. Now, when a voltage is applied between the source and the drain, large currents can flow. The direction of this electron current flow is shown in Figure 2.1. The source/drain extensions are for increased hot-carrier reliability, a damage mechanism for CMOS devices related to high electric fields in the channel region that can results in decreased channel conductance. The spacer oxides are a byproduct of the fabrication process used to form the source/drain extension.
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VG VDD
Gate Oxide N+ Source
Gate “Metal”
e-
Flow
Spacer Oxide
N+ Drain
P- Substrate
Figure 2.1. A schematic diagram of an NMOS transistor.
Figure 2.2. Drain current versus drain voltage as a function of gate voltage for a NMOS transistor (After [Ma-89]).
The drain current ID versus drain voltage VD as a function of increasing gate voltage VG for a typical NMOS transistor is shown in Figure 2.2 [Ma-89]. For a gate voltage insufficient to produce inversion, the drain current is negligible for any drain voltage. For a gate voltage above that necessary to produce inversion at the interface, referred to as the threshold voltage VT, there is conduction in the channel. For a fixed VG > VT, at low drain voltages the drain current increases linearly with increasing
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VDD
VIN
(a)
VOUT
(b)
Figure 2.3. (a) Cross-section of a CMOS process wired as an inverter, and (b) equivalent inverter circuit (Based on [Alex-01]).
drain voltage. As VD increases for fixed VG, the difference between the VG and VD decreases, as does the electric field at the channel in the neighborhood of the drain. When VD > VDsat , where VDsat ≡ VG – VT, the inversion layer vanishes near the drain. This condition is referred to as “pinch-off” because the normal conduction channel disappears at or near the drain. When the channel pinches off, current saturation is observed. The slope of the ID-VG curve becomes approximately zero. The saturated drain current IDsat depends on the channel length L, the transistor width W, the effective carrier mobility µeff, and the effective oxide capacitance per unit area, Cox, and applying the long channel approximation is given by:
I Dsat =
W µ eff Cox (VG − VT )2 . 2L
[2.1]
Since the mobility for an electron in an NMOS channel is 2-3 times greater than that for a hole in a PMOS channel, the corresponding drive current for an NMOS transistor is 2-3 times greater than that for a PMOS transistor [Sze-80]. For CMOS logic, which couples NMOS and PMOS transistors into a single logic function, this necessitates designing PMOS transistors with width 2-3 times greater than the NMOS transistors to match drive currents and optimize performance. A CMOS process allows for the fabrication of both NMOS and PMOS transistors on a single silicon wafer. Since an NMOS transistor requires N+ source and drain on p-silicon, while a PMOS transistor requires p+ source and drain on nsilicon, to accomplish that on a single wafer requires the creation an n-doped well as shown in Figure 2.3. In addition, Figure 2.3 shows the cross-section of a typical
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Figure 2.4. First planarized integrated circuit, fabricated in 1965 (After [Moor03]).
x x2 0.5 x2 0.7 x
Figure 2.5. Each CMOS technology node involves a shrink in the linear dimension of 30%, and a corresponding area shrink of 50%. This results in a 2x increase in transistor density.
CMOS process wired as an inverter. An n-well is fabricated in the p-doped epitaxial layer by ion-implantation. This allows the fabrication of PMOS transistors within the n-well, and the fabrication of both NMOS and PMOS on a single wafer. A more in depth discussion on CMOS device physics can be found elsewhere [Sze-80], [Hodg83]. 2.3 CMOS Scaling
The “silicon dioxide field-effect device” demonstrated by Kahng in 1960 is
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Figure 2.6. The effect of advancement to the next CMOS technology node on circuit performance, complexity, and cost (After [Dell-03]).
often regarded as the ancestor of the modern MOSFET [Kahn-60]. The commercial potential of MOS technology, however, was not fully recognized until the late 1960s when MOS memories were finally accepted as viable products. Compared to their bipolar counterparts, the virtues of MOS memory were low cost and high density, while MOS transistors can be packed closer together and MOS fabrication is less complicated than using bipolar devices. But perhaps the most advantageous property of CMOS digital logic is that the power consumption is dominated by power dissipation only during the switching cycle when both devices are momentarily conducting. In addition static logic states do not dissipate significant power since standby or quiescent current is limited to only the leakage through each device, and the overall power consumption for CMOS circuits is relatively small. The first planar integrated circuit, which was fabricated in 1965 [Moor-03], is shown in Figure 2.4. We now have microprocessors with over 400 million transistors. This incredible advancement has been made possible through CMOS scaling. Technology scaling can be defined as the process of reducing the sizes of both active and passive devices in order to improve packing density and circuit speed. In 1974, Denard et al. presented the first systematic study of the impacts of technology scaling on circuit performance [Denn-74]. If the dimensions and voltages were scaled down by the same factor then: (1) the operating frequency would increase, (2) more transistors could be packed in the same sized IC, (3) the active power per IC of fixed area would remain constant, and (4) the reliability would be constant since the electric fields were held constant. This is “constant-field scaling”, sometimes referred to as “classic scaling,” which is summarized in Table 2.1. Every 2-3 years, CMOS technology is scaled one “technology node.” As shown in Figure 2.5, this scaling results in a reduction of the linear dimension by
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Table 2.1 Constant Field Scaling Rules (After [Ko-89]) Scaling Factor 1/K 1/K K 1/K K K 1 1/K 1/K2 1 1/K3
Surface Dimensions Vertical Dimensions Impurity Concentrations Currents, Voltages Current Density Capacitance (per area) Transconductance Circuit Delay Time Power Dissipation Power Density Power-Delay Product
Figure 2.7. The nominal feature size versus time for CMOS technology (After [Grov-02]).
30%. The corresponding area reduction is 50%. This translates to a doubling of the transistor density. As shown in Figure 2.6, each technology node results in a 2x increase in performance (1.4x from increased drive switching speed and 1.4x from increased circuit complexity made possible by increased transistor density), 2x
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increase in the number of transistors (1.9x from scaling, 0.1x from increased IC area) and a 1/2x reduction in cost (1.4x from scaling and 1.4x from manufacturing) [Dell03]. This scaling has led to a decrease in the nominal feature size from 3 µm in ~ 1977 to the anticipated value of 90 nm in 2003, as illustrated in Figure 2.7 [Grov-02]. This represents a new technology node approximately every ~ 2.5 years. An example of the effects of CMOS scaling on commercial digital processors is shown in Figure 2.8. Between the early 1970s and the present, there has been greater than a four order-of-magnitude increase in processor speed and throughput. The time evolution of key materials used to fabricate CMOS circuits of increased complexity and performance while maintaining reliability margins to acceptable levels is shown in Figure 2.9 [Garg-02B. In the 1960s, CMOS circuits were fabricated using only three materials: silicon substrate, silicon-dioxide gate insulator, and aluminum metal. In the 1970s, two key material changes enabled technology progression. The Al gate metal was replaced by polysilicon. This allowed CMOS transistors to be fabricated using a self-aligned poly gate process. This had several benefits, including shorter channel lengths by allowing the source and drain to be fabricated at the very edge of the gate and a reduction in gate metal overlap associated with using aluminum which resulted in less overlap capacitance and enabled higher operating speeds. The transition from Al to Al-Si interconnects allowed for better sintering of the interconnect metal to the poly gate, preventing significant interdiffusion of Al into the poly silicon region. In the 1980s, three new technology material innovations occurred. A silicide process was added where WSi2 was deposited on the polysilicon to lower the poly sheet resistance and the poly contact resistance. In addition, incorporation of a Ti/TiN barrier layer around the AlSi (Al-Cu) interconnect metal allowed extension to more than a single interconnect level. The transition from Al-Si to Al-Cu was made to improve the electromigration reliability of the interconnect network. The 1990s saw the incorporation of tungsten plugs to replace traditional Al-Cu vias and enabled a dual Damascene self-aligned interconnect technology. This technology was consistent with chemical-metal polishing (CMP) technology that was adopted in the mid 1990s. Low dielectric constant (low K) interlevel interconnect isolation began to be used in the 1990s. This reduced the parasitic RC delay associated with long global interconnects, and hence, allowed for higher performance circuits. Over the last few years, Cu interconnect technology has replaced Al-Cu, allowing the further reduction of parasitic speedlimiting RC delays. Figure 2.10 shows key process modifications enabling the continuation of CMOS scaling and for the most part does not require extensive explanation. One of the major technology changes was in the isolation technology. Isolation is necessary in CMOS ICs to electrically isolate one transistor from another and to prevent or minimize other undesirable parasitic conduction effects. Up until the mid 1990s, the isolation technology used was the Local Oxidation of Silicon (LOCOS). This
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Figure 2.9. The time evolution of key materials used to fabricate CMOS circuits of increased complexity and performance while maintaining reliability margins to acceptable levels (After [Garg-02B]).
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High-K Gate Dielectric 157-nm Litho
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Figure 2.10. Key process modifications enabling the continuation of CMOS scaling.
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Figure 2.11. (a) LOCOS process and (b) STI process. The transition from LOCOS to STI enables tighter transistor packing and planarized processing.
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approach produced SiO2 isolation oxide by locally reacting the silicon with water at high temperature. A cross-section of a LOCOS oxide is shown in Figure 2.11. At the edges of the LOCOS isolation, the SiO2 oxide thickness decreases and this transition region is referred to as the “bird’s beak” region. As we will see later, this has serious implications on the radiation hardness of CMOS processes. Because the length of the “bird’s beak” region is proportional to the isolation oxide thickness, it limits the potential transistor packing density. This is why a transition to Shallow Trench Isolation (STI) processes was adopted. The STI process does not involve the growth of an isolation region, but rather involves removal of silicon to build a trench and the subsequent refill of the trench with an insulator. As can be seen in Figure 2.11, this allows packing transistors closer together and is consistent with planarized processing. The results of this scaling is illustrated by the rapid increase in the number of transistors shipped worldwide per year, the decrease in the average transistor price per year, and the increase in worldwide semiconductor revenues per year over the last three decades, as illustrated in Figures 2.12 – 2.14, respectively. As Gordon Moore commented at the 2003 International Solid-State Circuit Conference [Eeti-03],
Figure 2.12. The world-wide number of transistors shipped per year as a function of time (After [Moor-03]).
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Figure 2.13. The average transistor price per year as a function of time (After [Moor-03]).
Figure 2.14. Worldwide semiconductor revenues per year as a function of time (After [Moor-03]).
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Figure 2.15. Original data from Moore’s 1965 article identifying the linear relationship between the logarithm of the number of transistors on an integrated circuit and time. This relationship later became know as Moore’s Law (After [Moor-65]).
“There are now more transistors rolling off the line, roughly 1018, than there are ants walking on the earth. There are about as many transistors produced each year as letters are printed on paper, each at a cost of about two-tenths of a microbuck” 2.3.1 Moore’s Laws
In a 1965 paper, Gordon Moore et al. observed a trend between the number of transistors on a CMOS integrated circuit and time. The original data showing this trend is shown in Figure 2.15 [Moor-65]. Moore pointed out that when the logarithm of the number of transistors is plotted versus time, the resultant data fits a straight line. Moore then predicted that this exponential dependence on time results in a doubling of the number of transistors every 2-3 years. In 1975, Moore made a prediction of the number of transistors per integrated circuit at each technology node through the year 2000. In figure 2.16, the predicted curve and what was actually realized for microprocessors and memories is shown [Moor-03]. Moore’s prediction was amazingly accurate considering how far into the future he was extrapolating. There is also a lesser-known Moore’s second law, which states that the cost of building a CMOS processing capability increases exponentially with time. The actual cost of building a CMOS processing capability through more than three decades of technology nodes is shown in Figure 2.17. The natural result of Moore’s second law is that it will become too expensive for some existing semiconductor manufactures to
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Figure 2.16. Comparison of a projection made by Moore in 1975 on the number of transistors per integrated circuit and that actually realized in microprocessors and memories (After [Moor-03]).
Facility Cost ($M)
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Figure 2.17. Moore’s lesser-known second law is that the cost of building a CMOS processing capability increases exponentially with time.
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Figure 2.18. Gate-oxide thickness as a function of technology node nominal dimension (After [Grov-02]).
jump to the next technology node, and hence, the number of semiconductor manufactures in the world (barring any dramatic changes in technology) will likely dwindle to a handful over the next decade. This will leave most of the world “fabless” and will change the way that the semiconductor business operates and may result in situations not yet imaginable. 2.3.2 Gate-Oxide Scaling
As CMOS technology has advanced, the gate-oxide thickness has decreased. As shown in Figure 2.18, the SiO2 gate oxide thickness tox goes from 600 nm for the 3 µm technology node in 1979 to 1.2 nm for the nearly mature 90-nm technology node anticipated in 2004 [Grov-02]. This shrinking of the oxide thickness to a value that represents only ~ 4 monolayers of SiO2 has important implications for radiation effects in CMOS microelectronics, as will be discussed at length in Chapter 4, and on CMOS performance and power consumption. When the gate-oxide thickness becomes comparable to the tunneling length for carriers in SiO2, ~ 5 nm, tunneling current through the gate oxide will become significant. As the gate oxide continues to shrink, the gate tunneling current will continue to increase. The measured and simulated gate tunneling current density as a function of gate voltage for oxides of different thickness are shown in Figure 2.19 [Taur-02]. The increase in tunneling current as oxide thickness is decreased is clearly observed. The gate tunneling power, the subthreshold power and the dynamic power as a function of technology node are shown in Figure 2.20 [Thom-99]. The subthreshold power is the power consumed at
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Figure 2.19. The measured and simulated gate tunneling current density as a function of gate voltage for oxides of different thickness (After [Taur-02]).
Figure 2.20. The gate tunneling current, the subthreshold power and the active power as a function of CMOS technology node (After [Thom-99]).
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Figure 2.21. Comparison and associated TEM micrographs of CMOS transistors with a SiO2 gate oxide and a transistor with a high K gate oxide for a 90-nm process (After [Grov-02]).
VG = 0 V associated with the transistor in the subthreshold regime, where the transistor drain current depends exponentially on the gate voltage. In the design of a CMOS process, reducing the threshold voltage results in increased saturation current at the supply voltage, with a corresponding increase in circuit performance. This, however, can result in increased subthreshold power consumption. The process designer must trade off these two elements in finalizing a process. As can be seen in Figure 2.20, the power consumption associated with gate tunneling and subthreshold transistor behavior with decreasing threshold voltages at the 0.13-µm node is ~ 10% of the dynamic current consumption. A solution to the problem of increased tunneling current is to replace the relatively low dielectric constant SiO2 gate insulator with a higher dielectric constant material. The same equivalent-oxide thickness can be obtained with a thicker “high K” dielectric as with a thin SiO2 gate dielectric, resulting in an exponential decrease in tunneling current. Figure 2.21 shows TEM micrographs of CMOS transistors with a 1.2-nm SiO2 gate oxide and a transistor with a 3.0-nm high-K gate oxide for a 90-nm process [Grov-02]. The measured tunneling current is reduced by a factor of 100x using the high-K dielectric. The transition to a new high-K dielectric material will be a major challenge for continuing the Moore’s Law trend into the future.
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tox tox VT
VDD
VT
Figure 2.22. Published industry trends (data points) are compared to “classic” scaling (dashed curves) (After [Nowa-02]). 2.3.3 Deviations from “Classic” Scaling
Not all CMOS parameters have followed classic scaling rules summarized in Table 2.1. Figure 2.22 [Nowa-02] shows a collection of published industry results for gate-oxide thickness, tox, threshold voltage, VT, and power-supply voltage, VDD, all against reported gate length, LGATE (Note: this discussion closely follows [Nowa-02]). Dashed curves show the classic scaling trajectories for these parameters as well. Taking gate length as a measure of the lithography scale, one can immediately see that VDD and VT have decreased more slowly than LGATE, while although not shown here, IDsat has actually increased rather than remaining fixed (as in classic scaling). The right-hand side of Figure 2.22 shows the same VT and tox data as the left-hand side, except with VDD as the abscissa; note that tox and VT fall relatively close to scaling in proportion to VDD (as they would in classic scaling). This suggests that the deviations from classic scaling have been driven primarily by VDD, which has itself decreased more slowly than LGATE. In the early part of this time span (1 µm to 0.5 µm), a reluctance to leave the widely accepted industry-standard VDD = 5.0 V, inherited from transistor–transistor logic (TTL), substantially retarded VDD reduction. As the transition to a 3.3 V standard gained momentum, an increased emphasis on performance and power resulted in circuit-board designs with a good deal of flexibility for VDD; these, in turn, allowed CMOS process-technology developers the freedom to optimize VDD scaling for power and performance to a greater degree. A given technology point defined by specific values of tox and LGATE will nearly always
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IDSAT PD
τ Cox
Figure 2.23. Electrical consequences of industry-trend scaling (points) are contrasted to classic scaling (dashed curves). While the inverter delay scales nearly the same as the classic case (as LGATE), the active-power density does not. Instead, the active-power density increases with decreasing LGATE because of the lag in VDD reduction (see Figure 2.22), which is only partially mitigated by a reduction in CGATE. IDSAT is the drain current drawn with the gate and drain voltages set at the nominal power-supply voltage, VDD (After [Nowa-02]).
deliver greater performance as VDD is increased (roughly in direct proportion to VDD), so as gate dielectric reliability became better understood the industry increased the acceptable ratio of VDD/tox in this next era, giving rise to a continued mismatch in LGATE and tox reduction rates. Thus, VDD continued to decrease more slowly than LGATE. The other item of note in Figure 2.22 is the behavior of VT. A large scatter in VT is seen, due in part to variability in reporting practices (nominal vs. fast-process, VT definition, etc.) and, to a good approximation, VT scaled in proportion to VDD; this is probably largely a consequence of practical CMOS device and circuit considerations, including circuit stability, noise immunity, and engineering of shortchannel effects to acceptable levels of control. The inverter delay, defined as the time required to propagate a transition through a single inverter driving a second, identical inverter, is commonly used as a means of gauging the speed of CMOS transistors (the speed of switching being inversely proportional to the circuit delay). It has been found empirically that a delay τ, calculated from
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τ = CGATE οV DD I DSAT
[2.2]
correlates quite well with actual inverter delays. Figure 2.23 illustrates the expected classic scaling consequences, along with data points calculated from the industry scaling trends for IDsat, CGATE, inverter delay, calculated delay τ, and switching power density (derived from the product of the power, as described above, and the density). While in “classic scaling” both IDsat and CGATE remain constant (normalized per MOSFET unit width), the industry-trend data spanning an LGATE reduction from 1 µm to 100 nm, indicate that IDsat has nearly doubled. The increase in IDsat is driven largely by “subscaling” of VDD. Similarly, CGATE has decreased significantly in this period, since LGATE drops more rapidly than tox, as discussed earlier. As a result, the inverter delay continues to decrease in proportion to (or perhaps slightly faster than) LGATE, as in classic scaling. The switching-power density, PSW ~ CGATE (VDD)2 / τ, remains constant with classic scaling; hence, the total die switching power shrinks as the decrease in circuit area, L2GATE, thereby allowing more function to be incorporated on a given area of silicon at no increase in switching power. Unfortunately, in contrast to this result, switching-power density, as calculated from the industry-trend data, has increased by nearly a decade. In this instance, the deviation of the VDD trend from classic scaling has outweighed that of CGATE, to yield this undesirable result. These deviations from classic scaling have led to alternate scaling schemes including “constant-voltage” scaling and “quasi-constant-voltage” scaling. The rules for these active scaling schemes are captured in Table 2.2. Table 2.2. Active Scaling in Three Schemes (After [Ko-89], [Chat-80], [Tsiv-87]) Quantity
Constant Field Scaling
Constant Voltage Scaling 1
W,L tox Na VDD, VT
1/K 1/K K 1/K
1/K 1/B K 1
Qusasi-constant Voltage Scaling 1
2.3.4 Intel’s 90-nm Process
To provide insight into near future technology, the recently disclosed details of Intel’s 90-nm will be presented [Bohr-02]. This process uses transistors with gate length of ~ 50 nm. It has become common for the gate length to be smaller than the critical dimension that defines a technology node over the last several generations of CMOS technology. This is done to achieve maximum performance. The comparison
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Figure 2.24. Comparison of minimum feature size, as defined by the half-pitch of the metal-1 line, and the gate channel length as a function of time (After [Bohr-02]).
NiSi
50 nm
Figure 2.25. A SEM micrograph of an Intel 90-nm CMOS processes (After [Bohr-02]).
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of the minimum feature size, as defined by the half-pitch of minimum-spaced polysilicon lines at a given technology node, and the gate channel length as a function of time is shown in Figure 2.24 [Bohr-02]. A SEM micrograph of an Intel 90-nm CMOS process is shown in Figure 2.25 [Bohr-02]. The gate length for this process is ~ 50 nm, and the silicide used to reduce the poly contact resistance is NiSi. This process uses new strained silicon technology to improve channel mobility, and hence, transistor drive current [Bohr-02], [Thom-02]. When germanium is added near the silicon channel, there is a change in the lattice structure, which results in a strain on the silicon at the channel. This strain in turn changes the silicon band structure in such a way as to increase electron mobility. The results in this technology in a 1020% increase is transistor saturated drive current when compared to an otherwise identical design using standard silicon channel material, allowing for improved circuit performance. With scaling there has been a trend toward an increased number of metal interconnect layers for a process technology node. The time evolution of this trend over eight technology generations is shown in Figure 2.26 [Grov-02]. The anticipated number of levels for the yet to be reached 64-nm and 45-nm processes are included in this figure. The figure indicates that for the 0.50-µm node, there were only 4 levels of metal, while for the 90-nm node there will be 7 layers of metal. As discussed earlier, at the 90-nm technology node, only copper interconnects are used. Figure 2.27 shows SEM micrographs of backend interconnect structures used for the 0.50-µm and 90nm technology nodes [Bohr-02]. This particular 0.50-µm processes used only 3 levels of metals, Al-Cu metal and W-plugs technology. The interlevel dielectric was SiO2 and this back-end process is clearly not planarized. By contrast, the 90-nm backend process uses 7 levels of interconnects, Cu as the interconnect metal and via technology, carbon-doped oxide as a lower K (K = 2.9) interlevel dielectric, and a planarized topography to support the large number of layers of metalization. Using this 90-nm technology, Intel has built experimental 52Mbit SRAMs [Bohr-02], [Moor-03]. Each SRAM uses 300 million transistors, and there are 120 billion transistors on one 300 mm wafer. An SEM micrograph of a single 6T-SRAM cell fabricated in 90 nm technology is shown in Figure 2.28 [Bohr-02]. The cell size is only ~ 1 µm2. The performance of these SRAMs has been tested and it was found that for operation with a supply voltage of 1.2V, the cycle time was consistent with 2.0 GHz operation, while at 1.0V, this falls to 1.7 GHz [Bohr-02]. 2.4 Future Direction and Challenges to Maintaining Moore’s Law Growth
There are many challenges associated with maintaining Moore’s Law growth into the future. This topic is much discussed within the commercial semiconductor industry and one can easily write a book on this subject alone. What I will try to do in this section is to present some interesting challenges to tickle the readers’ interest,
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Figure 2.26. Number of metal interconnect levels as a function of technology node nominal dimension (After [Grov-02]).
Figure 2.27. SEM micrographs of backend interconnect structures used in the 0.50-µm and 90-nm technology nodes (After [Bohr-02]).
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Figure 2.28. SEM micrograph of a single SRAM cell fabricated in 90-nm technology. The cell size is ~ 1 µm2 (After [Bohr-02]).
and provide reference for those who wish to explore the subject further on their own. As can be seen in the following quotes from industry leaders below, there is clearly no consensus on the future of CMOS within the semiconductor industry:
The myth behind the semiconductor industry's growth-cycle guarantee by Zev Or’bach, EE Times, Nov 27, 2002 … “Can't we just use the next semiconductor process to develop new products? The answer is no. Not if the development cost of each new, innovative product is over $10 million.”
Scaling the mountaintop by David Lammers, EE Times, December 27, 2002 "We often hear about the end of scaling, about hitting the brick wall. But that is not the right way of thinking about it. When a climber gets to the top of the mountain, he stops. Each application may have its own mountaintop of optimum scaling," D. Frank
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Moore's Law scales to at least 9nm: technologist by Brian Fuller, EE Times, March 12, 2002 …the 9nm node "can be ready more or less on time, in 2028 according to long-term forecasts or 2024 according to the 2002 (industry roadmap). Transistor and reliability physics allow for 9nm devices, although circuit and architectural innovations surely will be needed to handle anticipated voltage of roughly 0.5V.” "…Fundamental limits are still a ways off," C. Hu
Materials transitions stalk CMOS scaling by David Lammers, EE Times, June 18, 2002 “… the materials transitions promise a period of upheaval that will rival the early 1980s, which ushered in CMOS circuit design” D. Lammers "High-k is a very tough problem. People have started working on it, but not enough attention has been paid to it. Silicon dioxide is this amazing material; the interface with silicon is so good it will take more time to develop alternatives. For high-k to be effective, it almost certainly needs some other gate material [than the polysilicon electrode], otherwise the poly depletion will kill it. For the electrode function, we may need to go to dual metal gate electrodes at the same time we introduce a high-k gate. "In my opinion, this road map [strained silicon before, or at the same time, as a high-k gate dielectric] must be followed. If you don't have SOI and strained silicon, if you don't have a high-k gate material to prevent leakage, then you can't get any benefits from shrinking" other than higher transistor densities. M. Bohr
Bell tolls for CMOS, with successor nowhere in sight by David Lammers, EE Times, May 16, 2002 “The pace of CMOS scaling may slow over the rest of this decade as leaky transistors and interconnect problems become more intractable, and the technology may run out of gas by 2012, according to technologists at the Custom Integrated Circuits Conference here. And whatever is to replace CMOS must be invented now, because it will take at least a decade to develop into a commercial technology, speakers said.” D. Lammers
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Figure 2.29. Lithography trends correlated to CMOS technology nodes (After [Grov-02]).
Already discussed in this chapter was the challenge associated with incorporating a new high-K gate dielectric to reduce tunneling currents and associated power consumption. Similarly, the need to extend interlevel dielectric materials to lower dielectric constant material to minimize parasitic delays was also discussed above. Not yet discussed is the high cost of lithography technology and mask set generation. The lithography trends correlated to CMOS technology nodes is shown in Figure 2.29 [Grov-02]. Notice that three changes in lithography wavelength is required to advance between the 0.18-µm node and the 0.065-µm node. Mask fabrication costs are increasing rapidly. For example, the cost of a mask set for a complex component made in 0.18-µm technology was ~ $250K, while the cost has tripled to ~ $750K for a mask set in 0.13-µm technology. This puts up a significant roadblock to users who do not require the fabrication of large numbers of components. A partial solution to this problem is the concept of multi-project runs. MOSIS and “pay and play” foundries such as TSMC and UMC are using this approach. In this approach, a fraction of the reticle is purchased, as well as a fraction of the silicon wafer. This results in mask cost sharing. As the number of available CMOS foundries decreases and more users become fabless, some variant of this business model is likely to become prevalent. Another important issue is the power density. As discussed above, because VDD is not scaling as fast as other CMOS parameters, there is an increase in power density associated with the power dissipated on a CMOS chip. This effect is shown quantitatively in Figure 2.30 [Grov-02].
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Figure 2.30. The power-performance problem as viewed by Intel’s Chief Technology Officer (After [Grov-02]).
One particularly interesting challenge for future CMOS scaling is the effect of the continued decrease in the number of dopant atoms in the gate to establish the threshold voltage. Although the average concentration of doping is quite well controlled by the standard ion implantation and annealing processes, these processes do not control exactly where each dopant ends up. Consequently there is randomness at the atomic scale, resulting in spatial fluctuations in the local doping concentration, and these in turn cause device-to-device variation in MOSFET threshold voltages. As MOSFET technology nears the end of scaling, it will be readily possible to make devices with fewer than 100 dopant atoms controlling the threshold voltage. Since fluctuations in dopant number have a standard deviation equal to the square root of the number of dopants, in keeping with Poisson statistics, threshold variation may very well become quite large, making the design of robust circuits very difficult. Many workers have investigated the effects of these doping fluctuations on the VT of MOS devices, the most quantitatively accurate of which use stochastically placed dopants in full 3D MOSFET simulations to fully resolve the effects of dopant placement. Figure 2.31 shows an example of the statistical variation expected to occur in an 11-nm bulk MOSFET due to random dopant placement. It seems clear that such this 11-nm design point will be unusable from a circuit point of view because of the very wide variation in threshold voltage. However, it is difficult to predict the extent to which this effect will limit scaling, since there are several approaches to reducing the effect, and more may be discovered. For bulk devices,
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Figure 2.31. Simulated IV curves for 100 different 11-nm-channel-length bulk MOSFETs with discretely placed dopants. Each gray curve corresponds to a different random placement of the dopants in keeping with the designed average doping profiles. The solid black curve is the geometric average of the curves, while the dashed curve is the expected IV curve based on continuum doping profiles (After [Fran-02]).
the most obvious approach is to move the dopants in the body back away from the surface using highly retrograde channel doping profiles. Stochastic simulations confirm that such profiles can yield significantly (more than two times) lower VT uncertainty than uniformly doped channels. This is because the doping fluctuations are moved farther away from the channel and closer to the body, and so have less effect, since they are screened by the free carriers in the body. Novel device structures that remove the need for channel doping may also help minimize this effect. Finally, considering all of the material changes, processing changes, architectural changes that will be required to maintain Moore’s Law growth, reliability margins need also be maintained. This will be discussed in Chapter 6. For additional information on challenges to extending Moore’s Law, see, for example [Fran-02], [Garg-02A], [Garg-02B], [Dell-03], [Marc-02]. 2.5 Opportunities for Leveraging Commercial Microelectronics for Space Applications
Satellites and spacecraft that must operate reliably over long durations in space must utilize hardened electronics that can survive and operate in the harsh space radiation environment. Spacecraft electronics must withstand the long-term
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effects of a variety of radiation effects that are discussed in detail in Chapter 3. In order to keep pace in the rapidly evolving world of microelectronics, integrated circuit manufacturers must invest significant new capital in the technology advances required to produce each new generation. But the market for space-qualified components has been historically flat, and shows no signs of significant expansion in the foreseeable future. As a result, the cost of maintaining and continuously advancing technology capabilities in a flat market has caused many companies that were in the business of supplying radiation-hardened (rad-hard) electronic components a decade ago to drop out of the rad-hard market. The cost of maintaining and upgrading the few remaining suppliers of rad-hard parts has escalated. Because of these market forces, the performance of space-hardened electronics typically lags behind their commercial counterparts several technology generations, as shown in Figure 2.32 [Laco-01B]. Similar performance lags are seen in memories, applicationspecific integrated circuits (ASICs), and other electronic components. Because of the limited size of the space electronics market, the number of these rad-hard foundries has gradually decreased until only two digital electronics foundries remain in the space-hardened electronics business today. These market forces have motivated an exploration of additional approaches for producing the space-qualified electronics that will drive future generations of space systems. In particular, the Hardness-ByDesign (HBD) approach allows the space community to leverage commercial CMOS infrastructure to supply radiation-hardened components for space missions. In the HBD approach, design techniques are used to mitigate the effects of radiation effects in integrated circuits, which will be discussed in Chapters 4 and 5. These designs can then be manufactured at commercial foundries to produce circuits for space applications.
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The definition of HBD the author proposes is: Hardness-by-design is an approach to producing radiationhardened components and systems using innovative design and layout techniques at the transistor level, the component level and the system level to assure performance and radiation-hardness requirements are met. The fabrication of HBD components is at commercial microelectronics foundries using standard commercial processes and process flow.
HBD does not allow any modifications to the standard commercial process flow. It is non-invasive to the foundry. Hence, “co-processing” techniques [Kerw-99] and application of non-standard process flows [Bene-01], while proven to be very successful, are not considered HBD This is because a strategy for producing radiation-hardened components using commercial foundries cannot depend on the willingness of that foundry to change its process or process flow. Finally, commercial design rules must be adhered to unless a waiver is obtained from the foundry. Aspects of this approach have been in use over the last several decades, but most frequently in combination with dedicated rad-hard manufacturing facilities. More recently, a number of research and development programs and commercial institutions have demonstrated the basic feasibility of HBD utilizing standard commercial foundries. The remainder of this short course will be used to summarize the radiation effects in space that spacecraft are exposed to, to explain the effect of radiation on CMOS microelectronics, to explain specific HBD techniques and to discuss reliability and qualification issues associated with using commercial microelectronic processes. 2.6 Conclusion
This chapter covered many of the aspects of CMOS technology. A simple tutorial on CMOS basics was presented in Section 2.2. Following this was a detailed discussion on CMOS scaling. Classic CMOS scaling was described; it was shown how this scaling led to an explosion in the performance and quantity of CMOS integrated circuits over the last thirty years. Moore’s laws were described and discussed. The importance of gate-oxide scaling was also explained, as well as different approaches for isolating individual devices within an integrated circuit. Examples of CMOS technology at the 90-nm node were shown. A discussion on some of the future challenges that must be addressed to continue Moore’s law scaling was presented. Finally, the concept of how commercial CMOS scaling can be leveraged to produce radiation-hardened was presented. This included a definition of hardness-by-design.
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Figure 2.33. Moore was not always correct. In 1975, he predicted silicon wafers would be 57” in diameter in 2000 (After [Moor-03]).
Moore’s law is an exponential. Moore was not always correct, as illustrated in Figure 2.33, when he predicted in 1975 that wafers in 2000 would be 57” [Moor03]. It is important, however, to consider what Moore recently said at the 2003 ISSC. He said,
The question is, for how long can we delay forever?
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3 Overview of the Space Environment 3.1 Introduction The successful insertion of microelectronics into space systems requires that the microelectronic components remain functional over the mission lifetime in the harsh environment of space. The predominant element of the space environment that is not present for most terrestrial applications is the presence of radiation. This chapter briefly describes the space environment to provide a perspective for understanding the effects of radiation on CMOS microelectronics. For a more in depth discussion of the space environment, see, for example [Mazu-02], [Bart-97].
Galactic Cosmic Rays (GCRs)
Solar Protons & Heavier Ions Trapped Particles
Figure 3.1. A schematic representation of the major components of the Earth’s natural radiation environment (After [Endo-03]). 3.2 Natural Space Environment The primary sources of radiation for orbital space applications are the energetic electrons and protons trapped by the Earth’s magnetosphere in the Van Allen belts. These belts, shown schematically in Figure 3.1 [Endo-03], were discovered by the Explorer I satellite in 1958. The primary region of high particle flux lies between altitudes of 1,000 to 32,000 km and depends on latitude. The energetic electron flux separates into two belts. The inner belt has a maximum electron flux at approximately 4,000 km, while the outer belt has a maximum electron
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Figure 3.2. Measured dose rate versus L shell and latitude on the CRRES satellite. This data was taken behind 80 mil of aluminum (After [Guss-96], [Mazu-02]). flux at 32,000 km for electrons with energy that reach 7 MeV. The protons, which can have energies greater than several hundred MeV, are primarily localized in the inner belt. The higher energy electrons and protons are concentrated at lower altitudes. At lower energies, particle fluxes can exceed 1 x 108 electrons or protons per cm2 per day [Barn-96]. Experimental data from the CRRES satellite on the measured dose rate as a function of the altitude and latitude is shown in Figure 3.2 [Guss-96], [Mazu-02]. The two Van Allen belts can be clearly identified. The inner belt is confined to a relatively narrow altitude centered near the equator. The outer belt, however, extends over the full latitude range. While not shown in the CRRES data, the outer belt dips down to approximately 1000 km at the magnetic poles. If the Earth’s geomagnetic dipole were aligned with the Earth’s axis of rotation, longitudinal symmetry of the Van Allen belts would be expected. In reality, the Earth’s geomagnetic dipole is offset by 11° and displaced 500 km toward the Western Pacific with respect to the Earth’s axis of rotation [Barn-96]. This results in the Van Allen belts dipping down to the upper parts of the atmosphere off the coast of Brazil. This effect is referred to as the South Atlantic Anomaly (SAA) and satellites with highly-elliptical orbits or those in low Earth orbit that fly through this region will receive significant amounts of radiation. Figure 3.3 show experimental data from the NASA/SAMPEX satellite indicating the presence of the SAA.
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Figure 3.3. Particle flux (arbitrary units) of >0.7 MeV protons and >0.5 MeV electrons in LEO measured on the NASA/SAMPEX satellite. The sun continually ejects “solar plasma” that carries the sun’s magnetic field into space. This ever-present solar wind is made up of 96% protons, 4% hydrogen and heavy ions, and an equal number of electrons [Mazu-02]. The solar wind moves with an average velocity on the order of 500 km/sec and produces particle fluence near Earth on the order of 10 ions/cm2 [Mazu-02]. This ever-present solar wind causes a “bow wave” and a “wake” in the anti-solar direction that results in the extension of the Earth’s magnetosphere to much great distances from the Earth, as shown schematically in Figure 3.1. The sun also produces solar flares, which are the rapid release of electromagnetic energy along with energetic ions, protons and electrons. The electromagnetic energy from a solar flare can span the spectrum from gamma rays to radio waves. Shortly after a solar flare, significant fluxes of highly energetic protons begin to arrive at the Earth’s magnetosphere and can last for a few hours to a few days. An example of particle flux associated with an intense solar flare is shown in Figure 3.4 [Noaa-00]. Nearly simultaneous with solar flares is the ejection of a broad spectrum of ions, including significant concentrations of heavy ions such as lead, referred to as coronal mass ejections (CMEs). Coronal mass ejections are often associated with solar flares and prominence eruptions (dense clouds of material suspended above the surface of the Sun), but they can also occur in the absence of either of these processes. Solar flares, coronal mass ejections and sunspots have an approximate 11-year cycle. The correlation between solar flare activity and sunspot number is illustrated in Figure 3.5 [Gosw-88]. The frequency of CMEs also varies with the sunspot. At solar minimum we observe about one CME a week. Near solar
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Figure 3.4. Particle flux for particles with energy greater than 100 MeV, 50 MeV and 10 MeV as a function of time after an intense solar flare on July 14, 2000 (After [Noaa-00]).
Figure 3.5. Correlation of solar flare activity and sunspot activity for solar cycles 19, 20, 21 (After [Gosw-88]).
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maximum we observe an average of 2 to 3 CMEs per day. Finally, it is interesting to note that the sun also reverses its magnetic field orientation every 11 years. Galactic cosmic rays (GCR) originate outside the solar system and produce the highest energy particles that interact with the Earth’s magnetosphere. Galactic cosmic rays are composed of 98% atomic nuclei and 2% electrons. Of these atomic nuclei, about 90% are protons and 9% are alpha particles, with the balance consisting of lithium, boron, carbon, nitrogen, oxygen and heavy nuclei. These particles can have energies exceeding 10 GeV/nucleon [Tang-03]. 3.3 Summary The natural space environment includes ionizing radiation associated with trapped electrons and protons in the Van Allen belts and a broad spectrum of highly energetic particles that can originate from numerous sources, including solar-related events and GCRs. In very general terms, the effects of the space environment can be summarized into three different areas: (1) total ionizing dose effects, which are mostly associated with the trapped electrons and protons in the Van Allen belts, (2) single-event-effects, which are associated with single particle strikes that can upset logic or storage elements or produce device failures, and (3) displacement damage effects, which are associated with neutron or proton strikes that result in the displacement of atoms. In the following chapters, the effects of total ionizing dose and single-event effects on CMOS microelectronics will be described in detail, as well as approaches to mitigate these effects. Displacement damage effects in CMOS devices is usually not an issue in a natural space environment, and will not be further discussed.
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4 Total Dose Effects on Commercial CMOS Processes 4.1 Introduction This chapter presents an overview of the effects of total dose radiation on commercially available CMOS processes. In Section 4.2, the interaction of electrons, protons and photons with solids is reviewed. This includes the introduction of the linear energy transfer parameter and describes how it is used to determine the number of electron-hole pairs created in silicon as a function of particle type and energy. Examples of radiation-induced electron-hole statistics are presented, which relate the exposure dose to particle fluence and particle type. Section 4.3 presents a simplified discussion of radiation-induced charge transport in silicon dioxide. This is broken into four different stages: (1) electron-hole creation and recombination, (2) hole transport toward the SiO2/silicon interface, (3) hole trapping near the interface, and (4) interface state creation at the interface. The role of temperature and tunneling is discussed in terms of the neutralization of trapped-hole charge. The differences between thick- and thin-film gate-oxides are also discussed in terms of the role of hole tunneling out of the gate oxide. In Section 4.4 the effects of trapped-oxide charge and interface-charge on MOS behavior is discussed in detail. The role of these charges on CMOS transistor threshold voltages is explained. Specific quantitative examples of threshold voltage shifts in transistors fabricated at commercial CMOS foundries are presented. These examples include processes that span the range of channel lengths from 1.6-µm down to 0.18-µm. One of the important conclusions from these data is that gate oxide threshold voltage shifts become negligible for CMOS processes with gate oxides less than ~ 5 nm thick. The effect of total dose radiation on other CMOS device parameters, such as the transconductance and the subthreshold swing is discussed in terms of the role of interface states. Examples are given for commercial CMOS processes. The physical mechanisms responsible for radiation-induced leakage in CMOS technology are presented. Intra-device leakage in the form of edge leakage is discussed in terms of parasitic edge transistors at the interface between the gate oxide and the isolation oxide. Examples of commercial processes with both LOCOS and STI field oxide technology are presented that indicate a trend toward increased total dose hardness as CMOS technology continues to scale to the 0.18-µm technology node, where hardness is defined as a certain level of off-state leakage being exceeded with exposure to radiation. For a 0.18-µm commercial CMOS process, a hardness level of ~ 345 krad(Si) will be demonstrated. Data from other CMOS foundries will also be presented showing that the trend toward increased total dose hardness as channel length is decreased is general. A mechanism that can introduce inter-device leakage is presented. This mechanism involves the inversion of a parasitic NMOS transistor where the “gate oxide” is the isolation field oxide. The hardness of these parasitic transistors will be quantified for two commercial CMOS processes. Finally, the key points made in this chapter will be summarized in Section 4.5.
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4.2 Interaction of Electrons, Protons and Photons with Solids When an energetic particle (proton, electron, or heavy ion) impacts a solid, the particle loses energy at nearly a constant rate (units of MeV/cm) as it passes through the solid, as long as it is not near the end of its range. The mechanism by which electrons and protons lose energy is primarily by inelastic Coulomb scattering in which the incident particle ejects an outer shell electron from an atom [Schw-02]. The incident particle repeats this scattering process as it continues through the solid. When normalized by the density of the solid, the energy loss rate is referred to as the Linear Energy Transfer (LET) rate. The units of LET are rate of energy loss per length per density, or (MeV/cm)/(g/cm3) = MeV-cm2/g. The LET for electrons and protons in SiO2 are shown in Figure 4.1 as a function of particle energy [Oldh-85]. The electron LET decreases monotonically with increasing energy from 100 keV, reaching a broad minimum at 1 MeV. Above 1 MeV, the electron LET increases slowly. The proton LET is greater than that of electrons at the same energy, and decreases monotonically above approximately 500 keV. Photons also interact with solids and the nature of that interaction depends on the photon energies [Schw-02]. Gamma rays from a cobalt-60 source, which are often used for radiation testing in the laboratory, have energies of 1.17 MeV or 1.33 MeV. The interaction of gamma rays with solids is primarily by Compton scattering. In this process, an incoming photon collides with an atom, producing an energetic electron and an ionized atom. The energetic electrons then interact with the solid as described above. The scattered lower energy photon can continue to interact with other atoms in the material, producing additional energetic electrons. As shown in Figure 4.1, the effective LET of a cobalt-60 gamma ray in Si02 is approximately equivalent to an electron with energy of ~ 300 keV. Since the interaction of energetic protons, electrons and photons with matter deposits energy that produces electron-hole pairs, it is referred to as ionizing radiation. 4.2.1 Electron-Hole Statistics in SiO2 The elements most sensitive to ionizing radiation in a CMOS device are the gate and isolation oxides, which are most often fabricated with SiO2. The energy necessary to create an electron-hole pair (Eeh) in SiO2 is 17 eV [Bene-86]. For a proton with an LET of 100 MeVcm2/g, the electron-hole line density (No) is calculated as follows: No =
(
)(
)
LET ο ρ 100 MeV − cm 2 / g ο 2.27 g / cm 3 = = 1.3 x 10 7 pair / cm −6 E eh (17eV ) ο 10 MeV / eV
(
)
[4.1]
where ρ is the density of SiO2. Similarly, for an electron with LET of 10 MeV/g/cm2, the electron-hole line density is 1.3 x 106 pairs/cm. It follows that a single
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LET (MeV cm2 /g)
1000
100
10
1 .001
. 01
.1
1
10
100
Energy (MeV) Figure 4.1. The Linear Energy Transfer (LET) function for electrons and protons in SiO2 as a function of particle energy. The effective LET of a cobalt-60 gamma ray is indicated in terms of an equivalent energetic electron (After [Oldh-85], figure from [McLe-89]).
particle with an LET of 10 MeV-cm2/g traversing a 100 nm gate oxide will produce (1.3 x 106 pairs/cm)(10-5 cm) = 13 electron-hole pairs. A common unit for quantifying the total absorbed ionizing dose in a solid is the rad. The rad is a measure of the amount of energy deposited in a material per unit mass, where 1 rad = 100 erg/g = 6.24 x 1013 eV/g. The relationship between dose D (rad), LET (MeV-cm2/g) and particle fluence Φ (particles/cm2) is given by the expression D = 1.602 x 10 − 8 οLET ο Φ .
[4.2]
Using equation [4.2], it follows that the fluence required to deposit 1 rad total dose for a particle with LET = 1 MeV-cm2/g is 6.24 x 107/cm2. by:
The electron-hole pair density (go) for 1 rad deposited in Si02 is determined
go =
1 rad 6.24 x 1013 eV / g ρ ( Si0 2 ) = 2.27 g / cm 3 = 8.4 x 1012 pair / cm 3 . [4.3] E eh 17eV
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Figure 4.2 Schematic representation of radiation-induced ionizing effects in MOS structures in the case of an applied positive gate voltage (After [McLe-89], figure from [Schw-02]).
4.3 Simplified Description of Total-Dose-Induced Charge Transport in MOS Oxides A schematic representation of total-dose-induced ionizing effects in MOS structures in the case of an applied positive gate voltage is shown in Figure 4.2 [McLe-89]. This is described as a three-step process. The following discussion is a condensation of several articles and presentations, from which this author borrows gratefully, and that the reader can reference for further details. 4.3.1 Electron-Hole Pair Recombination The first step in this ionization process is the generation of electron-hole pairs by energetic particles and/or photons, as described above. Immediately after the creation of electron-hole pairs, a fraction of the electron-hole pairs recombine and the remaining electrons drift to the gate electrode due to the gate electric field. The time scale for recombination to occur is very short. This is a result of the high mobility of electrons in SiO2. The electron velocity in SiO2 saturates at ~ 107 cm/s for electric fields E greater than ~ 2 MV/cm [Hugh-78] (note that the electric field across the gate oxide in modern CMOS technologies typically exceeds 2 MV/cm). The effect of having high electron velocity is that the time for the electrons to be swept from the gate oxide under the influence of a positive gate voltage is extremely short. For a gate oxide of 100 nm, an estimate of the transit time ttr (sec) for an electron to travel from the SiO2/Si-channel interface to the gate electrode can be calculated:
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t tr =
tox
υs
≅
10 −5 cm = 1 ps , 10 7 cm / s
[4.4]
where υs is the saturation velocity for electrons in SiO2. On the other hand, the mobility of holes in SiO2 is estimated to lie between 10-4 – 10-11 cm2V-1s-1 [McLe-89]. For a 10 nm gate oxide, the resulting hole transit time is between 0.1 ns – 0.1 s. Hence, the window for recombination to occur is dominated by the rapid electron transit time and is on the order of picoseconds or less; after that time nearly all the electrons have been swept out of the gate oxide. Even with no voltage applied to the gate, recombination will be completed in at most a few picoseconds due to the builtin gate electric field. Two different recombination models can be applied to the recombination of electron-hole pairs in SiO2 [McLe-89]. These models correspond to two different regimes of the equilibrium distance rt of the electron-hole separation after the created electron-hole pair reach thermal equilibrium, and the mean separation λ between electron-hole pairs. In SiO2, rt is thought to be ~ 5 nm. The columnar model is applicable in the regime where λ << rt. This is the case for a high LET particle. For example, for a particle with an LET of 100 MeV-cm2/g, No ~ 107 pairs/cm, and one can estimate λ = 1 / No ~ 1 nm. In this model, the electron-hole pairs interact, the Coulomb interaction between an isolated electron-hole pair is effectively screened out, and the fraction of electron-hole pairs that recombine can be high. At the other extreme where λ >> rt, the Geminate model is applicable. For example, for a particle with an LET of 10 MeV-cm2/g, λ ~ 10 nm. In this regime, the interaction between different electron-hole pairs is negligible, and the Coulomb interaction between the isolated electron and hole of a pair dominates the recombination process. Hence, in Figure 4.1 for particles with LET corresponding to pair line density of greater than 107 pairs/cm, the recombination mechanism is described by the columnar model, while for line density of less than 106 pairs/cm, the recombination mechanism is described by the Geminate model. The effect of an electric field on the recombination processes is to separate the electrons and holes, which will result in less recombination. The yield for different LET particles, which represent the fraction of initial electron-hole pairs that do not recombine, is shown in Figure 4.3 as a function of the applied electric field for different sources of irradiation [McLe-89]. For more detail on recombination processes, see [McLe-89]. 4.3.2 Hole Transport Toward SiO2/Si Interface At this point in this simplified model of radiation-induced charge transport in MOS oxides, a fraction of the electron-hole pairs have recombined, and the electrons have been swept out of the gate oxide. In step two, the remaining holes drift toward the gate-oxide/silicon-channel interface under the applied electric field from the positively biased gate electrode. This process has been studied in depth, and it has been determined that the transport by holes is primarily by hopping between localized
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Figure 4.3. Fractional yield of holes remaining in the oxide as a function of the applied electric field for different kinds of radiation incident on SiO2 (After [McLe-89]).
sites in the gate oxide. This process is both thermally- and field-activated. The hole transport is highly dispersive in time, occurring over many decades in time after a radiation pulse, consistent with a wide dispersion in transit times of the holes through the oxide. It is believed that the microscopic nature of the hopping mechanism is associated with polaron hopping. In this model, as the positively charged hole moves through the oxide, it causes a distortion of the local potential field of the SiO2 lattice. The effect of this localized distortion is to increase the trap depth at the localized site, which tends to confine the hole. Hence, this process is sometimes referred to as “hole self trapping.” The combination of the charged carrier and its strain field is known as a polaron [Kitt-68]. As the hole moves through the oxide, the polaron distortion travels with the hole. Hence, the transport mechanism can be described as hole hopping between polaron states as it travels toward the SiO2/silicon-channel interface [McCl-76], [McCl-77]. 4.3.3 Tunneling, Deep Hole Trapping, and Interstate Formation at the Interface The third step in the process describes what happens as the holes reach the vicinity of the SiO2/silicon-channel interface. Three different processes can take place. 4.3.3.1 Tunneling When a hole is within a short distance of the interface, it can tunnel into the
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Figure 4.5. Normalized trapped hole energy distribution used for a 45 nm oxide (After [Flee-92]).
silicon and be collected as substrate current at the silicon body contact. This can occur when the wavefunction for the hole in the oxide overlaps significantly with the wavefunction of a hole vacancy in the silicon. This process can occur if the hole is not already localized in a deep trap so that its energy will be aligned with the energy of a vacancy in the silicon. This process is only weakly temperature dependent and results in a decrease in the net positive charge remaining in the oxide. The distance from the interface over which tunneling can occur is ~ 5 nm. 4.3.3.2 Oxide Trapped Charge At the SiO2/silicon channel interface, there are a large number of oxygen vacancies due to the out-diffusion of oxygen from the oxide and the large lattice mismatch between SiO2 and silicon. These oxygen vacancies can act as deep-hole traps, capturing holes that remain localized very near the interface. The energy distribution for this oxide trapped charge Qot for a 45 nm oxide is shown in Figure 4.5 [Flee-92]. The number of holes that are trapped is determined by the capture cross-section near the interface. This cross-section depends on the oxide fabrication process. Hence, the amount of trapped-oxide charge can vary widely between different CMOS technologies. Immediately after holes are trapped in the oxide, neutralization of this charge begins. As shown in Figure 4.6, two mechanisms are primarily responsible for this neutralization [Schw-02]. The first mechanism is the tunneling of electrons from the silicon into the oxide traps. The traps that are closest to the silicon are neutralized first by electron tunneling, since there is greater overlap of the silicon electron and oxide trap wavefunctions. Hence, the tunneling process can be depicted as a
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Figure 4.6. Schematic diagram illustrating the neutralization of oxide-trap charge by electron tunneling from the silicon and by thermal emission of electrons from the oxide valance band (After [McWh-90], figure from [Schw-02]).
tunneling front moving away from the silicon into the oxide. This front moves logarithmically with time. Once a trap is more than ~ 5 nm from the interface, it is essentially no longer within reach of an electron tunneling from the silicon. Since the initial distribution of oxide traps is highly dependent on the oxide fabrication process, the number of traps neutralized by electron tunneling will depend on the fabrication process. The second mechanism for neutralizing trapped charge is by thermal emission of electrons from the oxide valance band. This process is thermally activated, with an activation energy that is defined by the difference in the trap energy and the oxide valence band. The traps with energy closest to the valence band will be neutralized first. Hence, this process can be depicted as a thermal emission front, similar to a tunneling front. In addition, there is an electric field dependence to the neutralization rate by thermal emission of electrons. The electric field bends the potential barrier between the electron and the tunneling state, and effectively lowers this barrier height via thermally-assisted tunneling. This mechanism is independent of the spatial distribution of oxide traps. McWhorter, et al., combined tunneling and emission into a single model of trapped-hole annealing [McWh-90]. Experimentally, the activation energy was determined to be ~ 0.4 eV. Because there can be significant neutralization of the positive trapped charge near the oxide, annealing effects can lead to an “apparent” dose-rate effect. If the time over which a CMOS device is exposed to radiation is short compared to a mean annealing time, then only a very small fraction of the trapped holes will be neutralized by the end of the irradiation. On the other hand, if the exposure time is long compared to a mean
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annealing time, then a significant portion of the holes will be neutralized during the exposure time. This dose-rate related behavior needs to be considered in any hardness assurance approach developed to test the effects of total dose irradiation on CMOS devices. 4.3.3.3 Interface States The third process that can occur at the interface is “interface state” creation. The precise description of interface states and the mechanism by which they are formed is still a matter of debate. A simplistic view is that interface states are associated with dangling bonds between the silicon and the SiO2. Interface states exist within the silicon band gap at the interface with SiO2. Interface states in the lower portion of the silicon band gap are predominantly donors [Ma-89]. For PMOS transistors at threshold, the Fermi level is near the silicon valence band edge. The donor states above the Fermi level are empty, having donated an electron to the silicon, and the interface state is positively charged. Interface states in the upper portion of the silicon band gap are predominantly acceptors [Ma-89]. For NMOS transistors at threshold, the Fermi level is near the silicon conduction band edge. The acceptor states below the Fermi level are filled, having accepted an electron from the silicon, and the interface state is negatively charged. The interface states are all neutral when the Fermi energy is at midgap. The third effect of radiation-induced hole transport to the interface is the creation of additional interface states Dit and associated charge Qit. It is believed that the creation of these interface states involves the release of hydrogen ions [Lera-99], [Schw-02]. The buildup of interface states after exposure to radiation occurs on a much slower time scale than the buildup of oxide-trap charge. The buildup of interface states can take as long as 106 s after a pulse of irradiation. The rate of the buildup of radiation-induced interface states is thermally activated, with an activation energy of 0.7 – 0.8 eV [Wino-77], [Saks-88]. Unlike oxide-trapped charge, interface states do not significantly anneal at room temperature. Interface-state buildup is also bias dependent, with little or no interfacetrap buildup occurring for negative gate voltages [Schw-02]. Interface state buildup can also have an “apparent” dose rate effect. If the time over which a CMOS device is exposed to radiation is short compared to the characteristic time to form interface states, then only a very small fraction of the interface states will be formed by the end of the irradiation. On the other hand, if the exposure time is long compared to a characteristic time to form interface states, then a significant portion of the final interface states will be created during the exposure time. In either case, the full effect of interface states cannot be realized until a period of time after the end of exposure to irradiation has elapsed. This also needs to be considered in any hardness assurance approach developed to test the effects of total dose irradiation on CMOS devices. 4.3.4 Summary This section has described the effects of total-ionizing-dose irradiation on the gate oxide of a MOS transistor biased positively at the gate electrode. A four-step process was described. In the first step, the ionizing radiation creates electron-hole
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+
VG
Si
Tunneling Regions (a)
t=0
+ +
VG
+ SiO2
+
Tunneling Regions (c)
+ GATE
+ Si
+
+
+ +
+ - + - + + + SiO2 -
+
+ GATE
-
+
+
+
VG
+ - ++
+ -+
Tunneling Regions (b) t=0+
-
+
-
+
SiO2
+ + +
Si
SiO2
GATE
GATE
VG
-
Si
+
+
-
Tunneling Regions
t = 0 ++
(d)
t >> 0 ++
Figure 4.7 The charge distribution in a gate oxide at three times after exposure to a pulse of irradiation (t = 0) for a thick gate oxide biased positively at the gate electrode. (b) Initially after irradiation electron-hole pairs are generated throughout the oxide. (c) After a few picoseconds a fraction of the electron-hole pairs recombine. A fraction of the holes tunnel out of the oxide and the electrons are swept out of the oxide. (d) The remaining holes drift to the SiO2/Si interface, where they are either captured in deep traps, interact to form interface states, or tunnel out of the oxide.
pairs. A certain fraction of the electron-hole pairs recombine. Two models were discussed that describe the recombination process. The columnar model is applicable in the regime where the electron-hole pair density is high and the other electron-hole pairs screen out the Coulomb interaction between an electron and its corresponding hole. The Geminate model is applicable in the regime where the electron-hole pairs are isolated from each other. Also during this initial phase, the electrons are swept out of the gate oxide and collected at the gate electrode. The second step is the drift of the remaining holes to the oxide/silicon interface. A polaron self-trapping mechanism was described, where the transport to the interface was by polaron hopping. In the third step, a fraction of the holes are trapped at the interface. These traps are positively charged in the oxide, and can be neutralized over time from either electron tunneling from the silicon or by thermal emission of an electron from the oxide valence band. Because the activation energy for this process is relatively low, significant recovery can occur for radiation exposure over a long time period such as for a space mission. In the forth step, the formation of interstate traps was discussed. These interface traps act as positive charges in the channel of a NMOS transistor, or
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negative charges in the channel of a PMOS transistor. These steps are described pictorially in Figure 4.7. It should again be noted that this description is simplistic in nature, and does not address many of the subtleties of these processes. For example, the role of electron trapping, border states, and the electric field collapse effect for high total dose irradiations have not been addressed. For more detailed presentations on the issues discussed in this section, see, for example, [McLe-89], [Lera-99], [Schw-02]. 4.4 Effect of Trapped-Oxide and Interface-State Charge on MOS Performance In the last section, we described how ionizing radiation could result in positive oxide-trapped charge in the gate oxide of a MOS device, and positive or negative charge trapped in radiation-induced interface traps at the interface. The introduction of these new charge sources, as compared to the device prior to irradiation, can affect device performance. 4.4.1 Threshold Voltage Shifts The effect of introducing charge in the gate oxide and/or at the gateoxide/silicon interface is to shift the CMOS transistor threshold voltage (this discussion closely follows [Ma-89]). The threshold voltage is determined by integrating the weighted additional charge density over the oxide thickness:
∆Vot ,it =
−1 Cox t ox
t ox
∫
x ρ ( x) dx ,
[4.5]
0
where x = 0 is the gate polysilicon/gate oxide interface. The radiation-induced trapped-hole charge is always positive. Hence, ∆Vot for both NMOS and PMOS transistor types is always negative. In addition, the trapped-hole spatial charge distribution depends on many factors, including the polarity and magnitude of the applied gate voltage, the gate-oxide processing technology, and the amount of hole neutralization that has occurred. Equation [4.5] indicates that the closer the holes are to the gate/silicon interface, the larger the associated threshold voltage shift will be. It follows that a positive gate bias, that pushes the holes toward the gate/silicon interface, will have a larger ∆Vot than a negative gate bias, which pushes the same amount of hole-charge toward the poly-gate/gate-oxide interface. Hence, the worstcase bias condition to maximize ∆Vot is to bias the gate positively, and to ground the source, drain, and body contacts. This represents an actual bias condition an NMOS transistor typically sees in CMOS logic gates. However, in CMOS digital logic, that set of bias conditions is never applied to a PMOS transistor. In an inverter, for example, when the gate of the PMOS transistor is biased high, the drain is also biased high. In addition, the body contact for a PMOS device is always biased positively.
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PMOS ∆Vit < 0
∆Vit > 0
10-3
∆vot < 0
Before Irradiation
∆Vot
∆Vit
Increase in Subthreshold Swing
Drain Current (A)
∆vot < 0
NMOS
10-6
∆Vot
Before Irradiation
∆Vit
10-9
10-12
Increase in Subthreshold Swing
10-15
Gate Voltage (V) Figure 4.8. Oxide-trapped charge (∆Qot) and interface state charge (∆Qit) cause threshold voltage shifts in MOS transistors. The threshold voltage shifts for NMOS and PMOS transistors are shown schematically. The ∆Vot is ∆Vit curves are shown relative to the preirradiation curve. Notice the threshold voltage shift associated with ∆Vot is negative for both NMOS and PMOS transistors. The threshold shift associated ∆Vit is positive for NMOS and negative for PMOS transistors.
Hence, a more realistic bias for PMOS transistors that maximizes both trapped-oxide and interface-state charge is to have the gate, drain and body biased high, while the source is grounded. follows
Interface-state charge is highly localized at x = tox. From equation [4.5], it
∆Vit = −
∆Qit φ ( s ) Cox
[4.6]
,
where ∆Qit(φs) is the radiation-induced interface-trapped charge for a band bending φs at inversion. For the case that all the interface traps are donor-like,
ε CB + qφ s ∆Qit = q ∆Dit (ε )dε εF
∫
,
[4.7a]
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where ∆Dit(ε) is the energy-dependent change in the density of radiation-induced interface states, εCB is the conduction band edge in the bulk silicon, and εCB + φs is the energy of the conduction band edge at the interface. Similarly, if the traps are all acceptor-like,
∆Qit = − q
∫
εF ∆Dit (ε )dε
[4.7b]
,
ε VB + qφ s
where εVB is the valence band edge in the bulk silicon, and εVB + φs is the energy of the valence band edge at the interface. Since ∆Qit is negative for NMOS transistors and positive for PMOS transistors, the associated threshold voltage shift ∆Vit is positive for NMOS transistors and negative for PMOS transistors. Since very few interface states are formed with a negative voltage applied to the gate electrode, the worst-case bias condition to maximize ∆Vit is to have the gate positively biased. Hence, the worst-case bias conditions for maximizing ∆Vit are the same for maximizing ∆Vot for both NMOS and PMOS transistors. The effect of radiationinduced oxide-trapped charge and interface-trapped charge is illustrated in Figure 4.8. 4.4.2 Radiation-Induced Gate-Oxide Threshold Voltage Shifts in Commercial CMOS Processes There has been a trend in commercial CMOS processes toward increased total-dose hardness over the last five years. We will first examine the effect of totaldose radiation on gate-oxide threshold voltage shifts in commercial CMOS processes as the transistor critical dimension continues to shrink to values approaching 100 nm. Figure 4.9 shows the change in the measured total threshold voltage shift ∆VT as a function of total dose for minimum geometry NMOS transistors processed at four different CMOS foundries [Osbo-98A]. These processes are an AMI 1.6-µm process, an Orbit 1.2-µm process, an HP 0.8-µm process, and an HP 0.5-µm process. All transistors were biased for worst-case threshold voltage shifts as described in Section 4.4.1 with a supply voltage of +5 V. As can be observed in Figure 4.9, ∆VT increases with increasing total dose. In addition, for a given total dose, the larger the transistor channel length, the larger ∆VT. Since the total threshold voltage shift is given by ∆VT = ∆Vot + ∆Vit ,
[4.8]
the negative values of ∆VT for the NMOS transistors indicate that the threshold voltage shifts are dominated by the trapped-oxide charge. After irradiation to 300 krad (Si), the transistors were subjected to a 168 hr anneal at 100 °C while biased for worst-case threshold voltage shifts. This has two effects. First, it accelerates the neutralization of trapped-oxide charge. Second, it accelerates the formation of interface states. The effect of this annealing process on the NMOS transistors in
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100
Post-Anneal
∆ VT (mV)
0 -100 NMOS 50 rad/s
-200
AMI 1.6 µm Orbit 1.2 µm HP 0.8 µm HP 0.5 µm
-300 -400 -500 0
1
10
100
1000
Dose (krad(Si)) Figure 4.9. Change in threshold voltage as a function of total dose for minimum geometry NMOS transistors for four different commercial CMOS processes biased for the worst case (After [Osbo-98A]).
100
Post-Anneal
∆ VT (mV)
-100 PMOS 50 rad/s
-300
AMI 1.6 µm Orbit 1.2 µm HP 0.8 µm HP 0.5 µm
-500
-700 0
1
10
100
1000
Dose (krad(Si)) Figure 4.10. Change in threshold voltage as a function of total dose for minimum geometry PMOS transistors for four different commercial CMOS processes biased for the worst case (After [Osbo-98A]).
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1000
∆ VT/t2ox (arb. units)
PMOS AMI 1.6 µm/32 nm
100
Orbit 1.2 µm /23.3 nm HP 0.8 µm /17 nm HP 0.5 µm/9.4 nm
10
slope = 1 1
0.1 0.1
1
10
100
1000
Dose (krad(Si)) Figure 4.11. The change in threshold voltage normalized by the oxide thickness squared as a function of total dose for the transistor data from Figure 4.9. The oxide thickness for each process is shown in the legend. A slope = 1 line is shown as a reference (After [Laco-01A]).
Figure 4.9 is to increase the threshold voltage, and hence, the threshold voltage shifts (the threshold voltage shifts become less negative). This behavior in NMOS transistors can occur from a reduction in trapped-oxide charge (reduction in positive charge) and/or an increase in interface state trapped charge (increase in negative charge). To differentiate between the two effects, one needs to look at the behavior of capacitance versus voltage curves as a function of total dose for MOS capacitors made from the same process or to examine the behavior of the subthreshold swing as a function of total dose. This will be discussed in more detail in Section 4.4. The change in the threshold voltage for minimum geometry PMOS transistors for the same four commercial processes is shown in Figure 4.10 [Osbo-98A]. The behavior for the PMOS transistors is similar to the NMOS transistors, except after the anneal cycle there is more “recovery” (the shift in threshold voltage moves toward zero) for the PMOS transistors. Since interface states do not significantly anneal at 100 °C, this recovery is associated with the neutralization of trapped-hole charge.
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The processes with the smallest critical dimension showed the smallest ∆VT shift. This can be explained in terms of the dependence of ∆VT on oxide thickness. For a CMOS transistor, ∆VT ∝
∆QT Cox
,
[4.9a]
where ∆QT ∝ oxide volume ∝ t ox
[4.9b]
is the total trapped charge (∆QT = ∆Qot + ∆Qit) and
1 ∝ t ox . Cox
[4.9c]
It follows that 2 ⇒ ∆VT ∝ t ox
.
[4.10]
The change in threshold voltage normalized by the oxide thickness squared as a function of total dose for the transistor data from Figure 4.10 is shown in Figure 4.11 [Laco-01A]. The oxide thickness for each process is shown in the legend. If the only differences between processes were the oxide thickness, then for each total dose level, all data points would have the same value. For the most part, for the PMOS transistors shown in Figure 4.11 at a given total dose, the normalized threshold voltage shifts are tightly grouped. This indicates that the major factor responsible for the magnitude of the threshold voltage shift is the oxide thickness. The variation in the normalized threshold voltage at a given dose is likely a consequence of the variation in the oxide fabrication processes. Figure 4.11 also shows a linear dependence of ∆VT on the total dose exposure. For oxide-trapped charge, the number of traps populated with holes in the neighborhood of the interface depends linearly on the number of holes created in the oxide. That, in turn, depends linearly on the total dose exposure. For interface trapped charge, the number of interface states created depends on the fraction of holes not trapped in oxide-hole traps that get to the interface. Of those, a fraction will actually be involved in the creation of interface states. It follows that Qit also depends linearly on the total-dose exposure. Since both Qot and Qit depend linearly on the total-dose exposure, it follows that ∆VT ∝ D
.
[4.11]
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Tunneling Region
Tunneling Region
-
VG
Si
GATE
GATE
VG
+
Si
+
+ -+ + + - ++ SiO 2
SiO 2
(a)
(b)
Figure 4.12. The charge distribution in a gate oxide after exposure to irradiation for a thin gate oxide biased positively at the gate electrode (a) immediately after irradiation, and (b) a short time later.
Putting equation 4.10 together with equation 4.11, it follows that 2 ∆VT (linear ) ∝ D οt ox
[4.12]
.
This regime is referred to as the linear regime (linear in dose) and is applicable for “low” total dose exposure levels. With continued exposure to radiation, eventually all the oxide-traps and the interface-state traps will be filled with charge, and the threshold voltage will saturate. In this case, ∆QT is independent of tox, and ∆VT ( saturation) ∝ t ox .
[4.13]
The gate oxide thicknesses of the four processes described above are large compared to the characteristic tunneling length of ~ 5 nm of holes within SiO2. As shown in Figure 4.12, when the oxide thickness is comparable to or smaller than the characteristic tunneling length, the radiation-induced hole charge tunnels out of the oxide and the probability that the hole can be trapped as oxide-trapped charge or contribute to the formation of interface states becomes very small. The result is that ∆VT is expected to be very small, even after exposure to high total dose values. The measured threshold voltage shift for four different commercial processes as a function of total dose is shown in Figure 4.13 [Anel-97]. A summary of the relevant technology characteristics is shown in Table 4.1. Commercial technologies A and B at the 0.5-µm node each have tox = 10 nm, hence the oxide thickness is still large
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C
D
Figure 4.13. The measured threshold voltage shift as a function of total dose for NMOS transistors from four different commercial CMOS processes (After [Anel-97]). Table 4.1. Summary of technologies relevant to Figure 4.12.
Ldrawn (µm) tox (nm) Device Isolation Supply (V)
A 0.5 10 LOCOS 5/3.3
B 0.5 10 LOCOS 3.3
C 0.35 7 LOCOS 3.3
D 0.25 5.5 STI 2.5
compared to the characteristic tunneling length, and the threshold voltage shift as a function of total dose increases quasi-linearly up to 2 Mrad(Si). As the CMOS technology scales a generation to a channel length of 0.35 µm with tox = 7 nm, the measured threshold voltage shift are relatively small, reaching a value of only ~60 mV at 1 Mrad(Si). Technology D advanced another CMOS generation to a channel length of 0.25 µm. At this technology node the oxide thickness is only 5.5 nm, which is comparable to the characteristic tunneling length. For this technology, the measured threshold voltage shift remains negligible up to the highest total dose exposure of 3 Mrad(Si). Figure 4.14 presents data on the measured threshold voltage shift as a function of total dose for three different commercial CMOS processes. The technology characteristics for these processes are summarized in Table 4.2. Unlike the results presented to this point that have all been for standard-edged transistors, the transistors used in Figure 4.14 are edgeless transistors. Edgeless transistors will be described
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30 HP 0.35 µm TSMC 0.25 µm TSMC 0.18 µm
∆ VT (mV)
15
0
-15
-30 0
1
10
100
1,000
10,000
100,000
Dose (krad(Si)) Figure 4.14. The measured threshold voltage shift as a function of total dose for NMOS transistors from three different commercial CMOS processes (After [Laco-98], [Laco-00], [Laco-01B]).
Table 4.2. Summary of technologies relevant to Figure 4.14.
Ldrawn (µm) tox (nm) Device Isolation Supply (V)
HP 0.35 7.6 LOCOS 3.3
TSMC 0.25 5.8 STI 2.5
TSMC 0.18 3.2 STI 1.8
and discussed in great detail in the next chapter, but for the purposes of this chapter, it suffices to say that the use of edgeless transistors permits the accurate evaluation of the threshold voltage shift up to high total dose exposure levels without introducing interfering effects such as edge leakage (discussed in Section 4.4.4.2). Notice in Figure 4.14, the span of the threshold voltage shift on the y-ordinate is between +15 mV and –15mV. As seen in Figure 4.14, the threshold voltage shift does not exceed ~ 5 mV up to 30 Mrad(Si). It is clear from these data that for a transistor with an oxide thickness less than the characteristic tunneling length, the threshold voltage shift is negligible from exposure to radiation up dose levels to tens of megarad.
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4.4.3 Radiation-Induced Transconductance and Subthreshold Swing Changes in Commercial CMOS Processes
An important parameter that characterizes the performance of a MOS transistor is the transconductance, gm, which is defined as gm =
δ ID ∝ µ eff δ VG
,
[4.14]
where µeff is the mobility of a carrier in the silicon channel at inversion. Three different mechanisms contribute to the mobility, as described by the equation 1
µeff
=
1
µph
+
1
µC
+
1
µsr
,
[4.15]
where µph is due to the effect of phonon scattering, µC is due to the effect of Coulomb scattering, and µsr is due to the effect of surface roughness scattering. The introduction of interface-trapped charge increases the Coulomb scattering of carriers in the channel and reduces the carrier mobility. A simplified expression that relates the preirradiation value of the mobility µ0 to the mobility after the addition of ∆Nit radiation-induced interface states µ is given by
µ=
µ0 , 1 + α ο ∆N it
[4.16]
where α is a constant [Sext-85]. In principal, a term that depends on the additional oxide-trapped charge could have been included in equation 4.16. However, ~ 1 s after irradiation, the majority of oxide-trapped charge near the interface has been neutralized by tunneling and the remaining oxide-trapped charge presents a negligible scattering cross-section for carriers in the channel. A reduction in transistor transconductance results in slower switching speed. The normalized change in the maximum transconductance for the AMI 1.6-µm process as a function of total dose for a minimum-geometry NMOS transistor is shown in Figure 4.15 [Osbo-98A]. For this thick-oxide process, the transconductance is reduced by ~ 27% at 300 krad(Si). This is consistent with the creation of interface states. After a 168 hr/100 °C anneal, the transconductance is further reduced to ~ 40%, consistent with the creation of additional interface states during the anneal process. The transconductance versus gate voltage for a 10/0.425 (W/L in microns) NMOS transistor from technology D before irradiation, after irradiation to 1 Mrad(Si), and after a 168 hr/100 °C anneal is shown in Figure 4.16 [Anel-97]. For this thin-oxide
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10
∆Gmmax/Gmmax(0) (%)
Post-Anneal 0 -10 NMOS 50 rad/s
-20 -30
AMI 1.6 µm / 32 nm
-40 -50 0
1
10
100
1000
Dose (krad(Si)) Figure 4.15. The normalized change in the maximum transconductance of NMOS transistors as a function of total dose for the AMI 1.6 µm process (After [Osbo-98A]).
Figure 4.16. Transconductance versus gate voltage for a 10/0.425 NMOS transistor from technology D before irradiation, after irradiation to 1 Mrad(Si), and after a 168 hr anneal at 100 °C (After [Anel-97]).
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transistor, there is no significant change observed in the transconductance after irradiation or the annealing cycle. This is consistent with a lack of interface state creation. Another important CMOS parameter is the subthreshold swing. An examination of CMOS drain current versus gate voltage on a semi-logarithmic graph, as in Figure 4.8, indicates that as the transistor transitions from accumulation to depletion and inversion, the ID-VG dependence is linear. The slope of this line is referred to as the subthreshold slope. A careful examination of Figure 4.8 shows that the subthreshold slope for the virgin device is unchanged by the introduction of oxide-trapped charge, but decreases with the introduction of interface-trapped charge. The gate subthreshold swing is defined as dVG S = ln 10 , d (ln I D )
[4.17]
which is proportional to the inverse of the subthreshold slope. The subthreshold swing in the absence of interface states can be reduced to S0 =
C kT ln 10 1 + sc , q Cox
[4.18]
where Csc is the capacitance associated with the depletion region in the silicon below the inversion region [Ma-89]. When interface states are taken into account, the subthreshold swing is modified to be Cit (φ s ) S it = S 0 1 + , Cox + C sc (φ s )
[4.19]
where Cit(φs) = q Dit(φs) is the capacitance associated with interface traps [Ma-89]. An increase in the subthreshold swing can result in increased off-state current and reduced noise margin. The subthreshold swings for NMOS transistors as a function of total dose for the AMI 1.6-µm and the TSMC 0.18-µm processes are shown in Figure 4.17 [Osbo98A], [Laco-01B]. The gate subthreshold for the thick gate oxide AMI process increases from a preirradiation value of ~100 mV/decade to a value of ~140 mV/decade at 300 krad(Si). While the AMI transistors were standard-edged transistors, the TSMC transistors used in Figure 4.17 are edgeless. This allows the isolation of the effect of radiation on the bulk of the gate oxide from the edges. For the thin gate oxide TSMC process the subthreshold swing remains unchanged up to a dose of 20 Mrad(Si). It is important to note these TSMC results are different from
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160
S (mV/decade)
140 120 100 80 60
NMOS
40
AMI 1.6 µm TSMC 0.18 µm
20 0 0
10
1,000
100,000
Dose (krad(Si)) Figure 4.17. The gate voltage swing S for NMOS transistors as a function of total dose for the AMI 1.6-µm and the TSMC 0.18-µm processes (After [Osbo98A], [Laco-01B]).
what would be observed for standard-edged transistors, which include edge effects, which will be discussed in the next section. As with the threshold voltage shift and the change in the normalized transconductance, the subthreshold swing will change with the formation of interface states, which occurs for thick gate-oxide processes. For processes with gate oxides with thickness less then the characteristic tunneling length, the number of interface states created is insignificant, and the change in the subthreshold swing is zero. 4.4.4 Radiation-Induced Leakage in CMOS Devices and Circuits
The effects of ionizing radiation in producing both intra-device and interdevice leakage will be discussed in this section. 4.4.4.1 Overview of Radiation-Induced Edge Leakage in CMOS Devices and Circuits
Transistors are electrically isolated from one another by use of a field oxide (FOX). As discussed in Chapter 2, generally speaking, for CMOS technology prior to the 0.25-µm node the approach to fabrication of the FOX was LOCOS. The interface region where the FOX meets the gate oxide is described as the bird’s-beak region. For CMOS technology after the 0.25-µm node, the approach to fabrication of the FOX is shallow trench isolation (STI). At the 0.25-µm node, depending on the foundry, one can find either LOCOS or STI. In Figure 4.18 (a), a cross-sectional
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+
+
+
+
N+ source P-epitaxial layer
+
+
+
+
P+ Substrate (a)
Polysilicon Gate
Primary Electron Current Flow
n+ Drain
Field Oxide
Edge Current Components
n+ Source (b)
Thin oxide Boundary (not shown)
Fox Edge Leakage Leakage (FL) (EL)
N+ Source Polysilicon gate FL
N+ drain EL
(c)
EL FL
Figure 4.18. (a) Cross-section view of a MOS transistor looking from the source in the direction of the channel (direction of current flow) (After [Alex-01]). The effect of radiation on the oxide at the transition region between the gate oxide and FOX, as in the gate oxide itself, is to trap holes. For an NMOS transistor, the effect of trapped holes on these parasitic “edge” transistors can be to shift the threshold voltage negative so that the “edge” transistors can conduct and produce a current at zero volts. In addition, the FOX itself can become inverted and conduct. (b) Off-axis perspective view of the edge transistor current in parallel with the main transistor current. (c) A top down view of a standard-edged MOS transistor. Edge leakage and FOX leakage can produce a current nearly equivalent to that of the main transistor.
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view of a MOS transistor looking from the source in the direction of the channel (direction of current flow) is shown. The effect of radiation on the oxide at the transition region between the gate oxide and the field oxide, as in the gate oxide itself, is to trap holes. The combination of the gate poly, the oxide in the transition region and the p+ diffusion under-layer form a parasitic “edge” transistor. For an NMOS transistor biased positively at the gate, the oxide in the transition region will see a relatively high electric field. The quality of the oxide near the FOX/gate oxide interface is likely to be poorer than that of the isolated gate oxide, and may be more efficient in trapping charge. Radiation-induced trapped holes in these edge transistors can result in a negative shift in the threshold voltage large enough so that the edge transistors become conductive and produce a current in the off state (0 V). In addition, the effect of radiation can be to invert the field oxide itself. Figure 4.18 (b) is an off-axis perspective view of the edge transistors currents in parallel with the main transistor current. In Figure 4.18 (c), a top down view of a standard-edged MOS transistor is shown. Radiation-induced edge leakage and FOX leakage can produce a current nearly equivalent to that of the main transistor. The end result is that the off-state current can increase due to radiation-induced edge effects. The consequences of increased transistor off-state current in circuits can be signal corruption and reduced margins, and for high transistor count circuits the total supply current can rapidly exceed component specifications. In addition, internal voltage drops can occur due to Ohmic losses in the supply lines. In some cases this can lead to functional failure, as the transistors behave as if they are always on. Edge leakage is not a problem for PMOS transistors, since for PMOS transistors the effect of oxide-trapped charge and interface trapped charge is to shift an already negative threshold voltage even further in the negative direction. Figure 4.20 presents a simplified view of the bird’s beak region associated with the growth of LOCOS field oxides [Bris-96]. Note that the effective thickness of a slice of the bird’s beak increases as one moves away from the transistor edge toward the field oxide. As shown in Figure 4.20, the combination gate oxide/bird’s beak/constant thickness LOCOS can be viewed as a continuum of transistors. Two factors affect the radiation-induced charge in each region. The first is the oxide thickness. The gate oxide is relatively thin. Moving away from the gate oxide, the bird’s peak region oxide thickness increases. Once the LOCOS region is reached, the oxide thickness remains constant. The second factor is the yield function, which is the probability the holes escape initial recombination [Bris-96]. The maximum electric field is applied to the gate oxide, and in this region the yield is maximum and constant. In the bird’s beak region, the electric field decreases, and the yield decreases. In the LOCOS region, the electric field is minimum and the yield is minimum and constant. To further complicate the issue, the preirradiation value of the threshold voltage can be shown to depend linearly on the effective oxide thickness, becoming more positive as the effective oxide thickness increases, and the saturation value of the drive current depends on the oxide capacitance, which depends on the inverse of the oxide thickness [Ma-89]. The result of these competing
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IDS
Figure 4.20. 2D representation of a gate to bird’s peak to constant thickness LOCOS cross-section divided into a continuum of transistors (After [Bris-96]).
NMOS
After Irradiation
Thin tox Med. tox Thick tox
VG Figure 4.21. A schematic representation of the effect of irradiation on NMOS transistor edges. The overall effect of these “leaky” edges is to increase the offstate current.
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Figure 4.22. Drain current versus gate voltage as a function of total dose for a 20/0.6 µm NMOS transistor fabricated at AMI (After [Kerw-98], [Kerw-99]).
influences is illustrated in Figure 4.21. For simplicity, it is assumed the gate oxide for this transistor is very thin and there is no effect of irradiation on the threshold voltage of the ‘intrinsic” transistor. The threshold voltage of the individual transistors that compose the continuum of transistors shift such that the resulting ID - VG curve is characterized by an increase in the off-state current. This additional quiescent current in individual transistors can combine to become quite large for integrated circuits. For an integrated circuit with ~ 1 Mgates (typical for a 0.35-µm process), assuming the leakage current of an isolated NMOS transistor is ~1 µA, the total increase in quiescent current is ~ 1 A. For a 10 Mgate circuit (typical for a 0.18-µm process), this current is could be 10 A. 4.4.4.2 Radiation-Induced Edge Leakage for Commercial CMOS Processes
Over the last six years, there has been a trend in commercial CMOS microelectronics toward increased total dose hardness. The drain current versus gate voltage (ID – VG) characteristics as a function of total dose for the AMI 0.6-µm process are shown in Figure 4.22 [Kerw-98], [Kerw-99]. At a total dose exposure of only 3 krad, the edge leakage already exceeds the limit specified for this process. At 10 krad, the off-state current is greater than 1 µA. Clearly, this process has little potential utility for space applications. The ID - VG characteristics as a function of total dose for a 0.35-µm minimum geometry NMOS transistor fabricated at Chartered Semiconductor are shown in Figure 4.23 [Laco-99A]. As described in Table 4.2, this process uses LOCOS
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1E-03
Chartered 0.35 µm NMOS Min. Geometry
0
VG = 3.3 V 75 rad/sec
1E-07
1K 3K
1E-09 IDoff (A)
Drain Current (A)
1E-05
1E-11 1E-13
1.E-07
10K
1.E-08
30K
1.E-09
50K
1.E-10
70K
1.E-11
100K 300K
1.E-12 60
70
80
90
100 110
PA
Dose (krad(Si))
1E-15 -0.5
0
0.5
1
1.5
2
2.5
Gate Voltage (V) Figure 4.23. Drain current versus gate voltage as a function of total dose for a 0.35-µm minimum geometry NMOS transistor fabricated at Chartered Semiconductor biased for worst case. Insert is graph of ID(0 V) versus dose (After [Laco-99A]).
isolation and has a gate-oxide thickness of 7.6 nm. For exposure up to 50 krad (Si), the ID - VG characteristics are unchanged. At 70 krad(Si), there is an increase in the off-state current to ~ 10-11 A. At 100 krad(Si) the off-state current has increased to a value slightly larger than 1 nA. At 300 krad(Si), the off-state current has increased to within a factor of ~ 5x the drive current at VDD = 3.3 V. The effect of a 100°C/168 hr anneal is to restore the ID - VG characteristics to those of the pre-irradiated device, indicating that the edge leakage is associated primarily with trapped-oxide charge in the parasitic edge transistors. The post-anneal characteristics also show a small increase in the subthreshold swing, consistent with some small degree of interface state creation. The insert in Figure 4.23 allows extrapolation of the radiation data to determine the total dose exposure level at which the NMOS transistor off-state current exceeds 1 nA (an arbitrary failure criteria). For this 0.35-µm process, the total-dose hardness level is ~ 92 krad(Si) under high-dose rate, worst-case bias conditions.
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1E-03 TSMC 0.25µm NMOS Min. Geometry
Drain Current (A)
1E-05
VG = 2.5 V 78 rad/sec
1E-07
0
1E-09
50K 100K
1E-11
250K 500K
1E-13
1000K
1E-15 -0.5
0
0.5
1
1.5
2
Gate Voltage (V) Figure 4.24. Drain current versus gate voltage as a function of total dose for a 0.25-µm minimum geometry NMOS transistor fabricated at TSMC biased for worst case (After [Laco-00]). 1E-03
VG = 1.8 V TSMC 0.18 µm NMOS 72 rad/s Minimum Geometry
1E-05
50K
1E-07
100K 150K
1.E-06
1E-09
200K
1.E-07
IDoff (A)
Drain Current (A)
0
1E-11
1E-13
250K
1.E-08 1.E-09
300K
1.E-10
400k
1.E-11
500k
1.E-12
PA 250
300
350
400
Dose (krad(Si))
1E-15 -0.5
0
0.5
1
1.5
2
Gate Voltage (V) Figure 4.25. Drain current versus gate voltage as a function of total dose for a 0.18-µm minimum geometry NMOS transistor fabricated at TSMC biased for worst case. Insert is graph of ID(0 V) versus dose (After [Laco-01]). II-69
The ID - VG characteristics as a function of total dose for a 0.25-µm minimum geometry NMOS transistor fabricated at TSMC are shown in Figure 4.24 [Laco-00]. This process uses STI isolation and has a gate-oxide thickness of 5.8 nm. For exposure up to 100 krad(Si), the ID - VG characteristics are unchanged. At 250 krad(Si), there is an increase in the off-state current to greater than 1 nA. For doses greater than 500 krad(Si) the off-state current saturates at a value greater than 0.1 µA. The effect of a 100°C/168 hr anneal is to restore the ID - VG characteristics to those of the pre-irradiated device, indicative that the edge leakage is associated only with trapped-oxide charge in the parasitic edge transistors and field oxide. For this 0.25µm processes, the total-dose hardness level is ~ 200 krad(Si) under high-dose rate, worst-case bias conditions. The ID - VG characteristics as a function of total dose for a 0.18-µm minimum geometry NMOS transistor fabricated at TSMC is shown in Figure 4.25 [Laco-01]. This process also uses STI isolation and has a gate-oxide thickness of 3.2 nm. For exposure up to 200 krad(Si), the off-state current is below 1 pA. At 300 krad(Si), the off-state current is still less than 0.1 nA. The off-state leakage increases to slightly greater than 0.1 mA at 500 krad(Si). The effect of a 100°C/168 hr anneal is to restore the ID - VG characteristics to those of the pre-irradiated device, indicative that the edge leakage is associated only with trapped-oxide charge in the parasitic edge transistors and field oxide. The insert in Figure 4.25 allows extrapolation of the radiation data to determine the total dose exposure level at which the NMOS transistor off-state current exceeds 1 nA. For this 0.18-µm process, the total-dose hardness level is ~ 345 krad(Si) under high-dose rate, worst-case bias conditions. The trend toward increased total-dose hardness of advanced commercial CMOS processes as they scale toward 100 nm critical dimension technology is not unique to the processes shown in Figures 4.22 – 4.24. Figure 4.26 presents data on the off-state leakage current as a function of total dose for NMOS transistors fabricated using the four different CMOS technologies described in Table 4.1 [Anel97]. Although the results are somewhat ambiguous in terms of the 0.5-µm processes, the trend toward increased total-dose hardness as CMOS technologies scale is evident. The hardness for the 0.35-µm process is ~ 50 krad, somewhat less than the ~ 90 krad observed for the Chartered processes. The hardness for the 0.25-µm process is ~ 210 krad, nearly identical to the ~ 200 krad observed for the TSMC 0.25-µm processes. It is interesting to note that the transition from LOCOS isolation to STI in conjunction with CMOS scaling results in processes that showed increased hardness to edge leakage effects. It seems reasonable to hypothesize that with the LOCOS bird’s beak absent from an STI process the initial transition from gate oxide to STI could be smoother, resulting in a higher quality oxide. In a typical STI process, there is a narrow region of thin isolation oxide before the STI trench is reached. This results in the initial continuum of parasitic transistors being very thin, and hence the threshold voltage shifts that are responsible for edge leakage will be small. In
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C
D
Figure 4.26. Off-state leakage current as a function of total dose for NMOS transistor fabricated using the four different CMOS technologies described in Table 4.1(After [Anel-97]).
addition, the STI oxide thickness is likely to be considerably thinner than that of the LOCOS isolation. These effects all argue in favor of increased hardness for STI edges. The transition from the initial thin STI oxide to the STI trench can be quite steep, and enhanced electric fields are possible. Hence, the reason for the improvement in leakage associated with the transition from LOCOS to STI is not yet completely understood. Nonetheless, the trend toward increased total-dose hardness for isolated CMOS devices with technology advancement appears to be general. The leakage results shown in this section for the processes described in Table 4.1 are for transistors of unspecified W/L ratios. The results for the processes described in Table 4.2 are for minimum geometry transistors (4λ/2λ). Extensive leakage results were also taken for wide transistors from the processes described in Table 4.2. The results are essentially the same as those obtained for the minimum geometry transistors, and will not be shown here. In section 4.4.1, it was stated that leakage is not an issue for PMOS transistors. This is experimentally demonstrated in Figure 4.27 [Laco-99A]. The drain current versus gate voltage characteristics as a function of radiation are unchanged up to 300 krad(Si).
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Negative Drain Current (A)
1.E-03 Charter 0.35 µm PMOS Minimum Geometry
1.E-05
0 VG = 3.3V 1K 75 rad/s From a simplistic point of view, that would introduce the effects of the 3K 1.E-09 10K 30K 1.E-11 50K 70K 100K 1.E-13 300K 1.E-07
1.E-15 -3
-2
-1
0
1
Gate Voltage (V) Figure 4.27. Negative drain current versus gate voltage as a function of total dose for a 0.35-µm minimum geometry PMOS transistor fabricated at Chartered Semiconductor biased for worst case (After [Laco-99A]).
Vdd
-
N+ Contact N-well
Vss
- - ---- - + + + + + + ++ + + + + +
N+ source P-epitaxial layer
Leakage Current
P+ Substrate
Field oxide leakage path Figure 4.28. Irradiation can drive the field-oxide isolation into inversion. When that happens there is a “low” resistance leakage path from the N-well drain contact along the interface of the isolation oxide and the low resistance epitaxial layer to the source of the NMOS transistor. This results in a lack of device isolation (After [Alex-01]).
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4.4.4.3 Radiation-Induced Inter-Device Leakage for Commercial CMOS Processes
The cross-section for an NWELL process showing a PMOS transistor in the NWELL and a NMOS transistor over the p- epitaxial layer separated by an isolation field oxide is shown in Figure 4.28. As discussed previously, the isolation oxide, whether LOCOS or STI, is much thicker than that of the gate oxide. If exposed to an electric field during irradiation, a considerable number of holes can become trapped at the isolation oxide/epitaxial layer. Whether there is an electric field over this parasitic field-oxide transistor or not depends on if a conducting line (metal or poly) happens to be routed over the field oxide, and the degree to which this line is biased positively. Assuming a positive bias is present during exposure to radiation, the effect of irradiation on the parasitic field-oxide transistor will be to create negative threshold voltage shifts that drive the transistor into inversion. If the threshold voltage shift is large enough such that the threshold voltage is below 0 V, the transistor will conduct even when no voltage is present on the metal line. In this case, there is a leakage path from the n-well contact through the n-well along the interface of the isolation oxide and the low resistance epitaxial layer to the source of the NMOS transistor. This inter-device leakage results in a lack of device isolation. There is another leakage path between the n+ source/drain regions of adjacent NMOS transistors. As with edge leakage, inter-device leakage can result in signal corruption, reduced margins, and additional supply current and the associated increase in rail voltage drop. Special field-oxide characterization test vehicles have been designed, fabricated and tested as a function of total-dose exposure to evaluate the radiation hardness of commercial CMOS isolation oxides. In Figure 4.29 the normalized capacitance versus gate voltage as a function of total dose is shown for a large area capacitor fabricated using the LOCOS isolation oxide under worst-case bias condition for the Chartered Semiconductor 0.35-µm process [Laco-99A]. The capacitors were driven from inversion to accumulation after initial exposure to light to ensure an adequate supply of carriers to create an equilibrium inversion state. Prior to radiation, the threshold voltage for this field-oxide capacitor is near 30 V. Radiation is applied with the metal biased high (3.3 V) and the semiconductor grounded. At 50 krad(Si), the threshold voltage has shifted negatively. At 100 krad(Si) the threshold voltage is approaching zero volts. At 300 krad(Si) the threshold voltage shifts even more negative, and there is evidence of interface state formation. Strictly speaking, when the threshold voltage drops below the supply voltage, intra-device leakage can occur if an “appropriately” placed metal line is biased at the supply voltage. More importantly perhaps, when the threshold voltage crosses below zero, the leakage path will be present with or without a metal line with the supply voltage. For this process, under worst-case bias conditions, the hardness of the LOCOS field oxide is near 100 krad(Si).
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1.01 Chartered 0.35 µm 75 rad/s VB = 3.3 V 0 10 krad 50 krad 100 krad 300 krad
1
C/Cmax
0.99 0.98 0.97 0.96 0.95 -50 -40 -30 -20 -10
0
10
20
30
40
50
Gate Voltage (V) Figure 4.29. Normalized capacitance versus gate voltage as a function of total dose for a large area capacitor fabricated using the LOCOS isolation oxide under worst-case bias conditions (After [Laco-99A]).
Special field-oxide transistors were fabricated with a polysilicon gate over STI field oxide between adjacent n-wells, which were contacted as the source/drain of the field-oxide transistors. The ID-VG characteristics as a function of total dose for field oxide transistors from the TSMC 0.25-µm process are shown in Figure 4.30 [Laco00]. The preirradiation value of the FOX transistor threshold voltage is ~ 42 V. Exposure to radiation shifts the threshold voltage negatively. At 100 krad(Si), the threshold voltage has nearly crossed zero (VT = 0.5 V). The FOX transistor was further irradiated to 500 krad(Si) in 100 krad(Si) steps. These results are not shown here for simplicity. It is clear, however, that the threshold voltage shifts have nearly saturated at 400 krad(Si). Following irradiation, the FOX transistor was annealed at 100°C/168 hr and the threshold rebounded to 41.5 V, nearly the preirradiation value. After the post anneal, an increase in the subthreshold swing is observed, consistent with the formation of interface states, which are partially responsible for the threshold voltage rebound. The threshold voltage as a function of total dose for the data presented in Figure 4.30 is shown in Figure 4.31. Defining the hardness of the FOX transistor as the dose at which the threshold voltage crosses zero, the hardness of this FOX is slightly greater than 100 krad(Si). There are certainly many variables that could potentially affect STI hardness, such as the geometry, STI profile and the interface from gate oxide to STI. It should be noted, however, that large threshold voltage shifts in the FOX will only occur if a positively-biased conductor is routed over the FOX region. To a large extent, this can be minimized through proper layout practices.
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1E-03
Drain Current (A)
1E-05 TSMC 0.25 µm FOX Transistor 78 rad/s VG = 2.5 V
1E-07
1E-09
0 10krd 50krd 100krd PA
1E-11
1E-13 -10
0
10
20
30
40
50
60
70
Gate Voltage (V)
Figure 4.30. Drain current versus gate voltage as a function of total dose for a large area capacitor fabricated using the STI isolation oxide under NMOS worstcase bias conditions. The transistor was exposed to 500 krad before the postanneal process. For simplicity, the intermediate radiation dose curves are not shown (After [Laco-00]).
Threshold Voltage (V)
50.0
Post-Anneal (after irrad. to 500 krad)
30.0
10.0
-10.0
-30.0 0
100
200
300
400
500
Dose (krad(Si)) Figure 4.31. Threshold voltage versus total dose extracted from the data presented in Figure 4.30.
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4.5 Summary
This chapter discussed the effects of ionizing radiation on commercial CMOS microelectronics. An overview of the basic mechanisms associated with the exposure of ionizing radiation to CMOS devices was presented. A four step processes was described that explained how ionizing radiation results in the trapping of holes near the gate oxide/silicon interface and the creation of charge traps at the interface. It was shown that for older CMOS technologies with gate oxides thicker than the characteristic tunneling length for holes, the addition trapped-charge results in threshold voltage shifts, decreases in transconductance and an increase in the subthreshold swing. These parametric changes can lead to stuck bits that effectively will not turn on, reduction is circuit speeds, timing imbalance between the NMOS and PMOS transistors, and increased power consumption. These effects were demonstrated for commercially available CMOS processes. For thinner oxides, it was shown that there is negligible additional charge introduced at or near the interface, and changes in threshold voltage and transconductance, and their associated effect on circuit performance, is no longer a concern. Examples were shown for thin gate oxide commercial processes consistent with the lack of oxide-trapped charge and interface-trapped charge. This transition into a regime where gate-oxide threshold voltage shifts are no longer an issue is the primary reason that hardness-by design has become a realistic option over the last few years. As you will see in the next chapter, there are design techniques that can mitigate all other radiation effects. There is, however, no easy way to design around gate-oxide threshold voltage shifts. Since this is no longer an issue for CMOS technologies beyond the 0.5-µm node, hardness-by-design now becomes a realistic option. The effect of ionizing radiation on transistor edges was shown to produce leakage associated with threshold voltage shifts in the edge transistors and the field oxide. This intra-device leakage results in increased power consumption and can lead to circuit failure. It was demonstrated through radiation data on many different commercial CMOS processes that there is a general trend toward increased hardness of these edges, with isolated transistor hardness greater than 300 krad(Si) demonstrated for a 0.18-µm commercial CMOS process. A radiation-induced mechanism that compromises inter-device isolation was also described. This mechanism involves the radiation-induced inversion of the field oxide, resulting in inter-device leakage. It was demonstrated for both a LOCOS 0.35µm process and a STI 0.25-µm process that the field oxide isolation hardness is approximately 100 krad(Si). This general trend toward increased total dose hardness as CMOS technology continues to shrink to smaller and smaller dimension provides opportunities and challenges for the potential insertion of commercial microelectronic components into space. These opportunities, challenges and risks, as well as design approaches to provide addition radiation hardness, will be discussed in the next chapter.
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5 Designing in Radiation Hardness 5.1 Introduction In the past, special processes had to be used to fabricate microelectronic components that were radiation hard. Hardness-by design is a new approach that is being developed to enhance the radiation hardness of microelectronic components without using special radiation hardening processing techniques. Through a combination of the application of specific design techniques and the leveraging of the intrinsic radiation hardness of leading edge CMOS processes, it is now possible to fabricate radiation-hardened components for many military and space applications using standard CMOS process flows. An overview of the various design techniques that can be used to design radiation hardness into a component will be presented in this chapter. Section 5.2 will discuss detailed design approaches to mitigating totaldose effects. Single-Event-Effects (SEEs) and design approaches to mitigate those effects will be discussed in Section 5.3. The types of SEEs discussed will include single-event upsets (SEUs), single-event transients (SETs) and single-event latchup (SEL). Section 5.4 will discuss the role of HBD cell libraries in building a HBD infrastructure. The potential role of Computer Aided Design (CAD) tools is discussed in Section 5.5. Specific approaches to designing HBD components will be discussed in Section 5.6. An example illustrating the trade-off of radiation hardness design margins with performance will also be discussed in this section. Section 5.7 will briefly discuss commercial-of-the-shelf (COTS) components from an HBD perspective. Examples of components that have been fabricated using HBD techniques as well as commercial components that show high levels of radiation hardness will be discussed in Section 5.8. Finally, the information presented in this chapter will be summarized in Section 5.9. 5.2 Designing in Total Dose Hardness Chapter 4 presented a detailed discussion on the trend of commercial CMOS technologies toward increased total-dose radiation hardness. It was shown that gateoxide threshold voltage shifts become negligible for advanced submicron CMOS technologies. This transition into a regime where radiation-induced gate-oxide threshold voltage shifts are no longer an issue is the primary reason that hardness-by design has become a realistic option over the last few years. As the reader will see in this chapter, design techniques are available that can mitigate all other radiation effects. There are, however, no easy ways to design around gate-oxide threshold voltage shifts. This section will present design approaches to further mitigate other total-dose effects. Specifically, techniques for mitigating intra- and inter-device leakage will be presented. Implementation of these techniques results in area, power and performance penalties. These penalties will be quantified whenever possible.
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Source Gate
Gate Source
Drain
Drain
(a)
(b)
Figure 5.1. Schematic diagram of (a) a standard-edged transistor, and (b) an edgeless transistor.
1E-03
IDS (A)
1E-05 1E-07
TSMC 0.25-µm NMOS 72 rad/s 2.5 V
0 100 krad 250 krad 500 krad 1 Mrad 2 Mrad Post-Anneal
1E-09 1E-11 1E-13 1E-15 -0.5
0
0.5
1
1.5
2
Gate Voltage (V) Figure 5.2. Drain current versus gate voltage as a function of total dose for a 0.25-µm edgeless NMOS transistor fabricated at TSMC and biased for worstcase (After [Laco-00]).
5.2.1 Mitigating Intra-Device Leakage As discussed in Chapter 4, the effect of total-dose irradiation on isolated, standardedged NMOS transistors is to cause an increase in the off-state leakage current. This increased leakage current is caused by the inversion of parasitic transistors at the transistor edges at or near the gate-oxide/field-oxide interface. A layout design technique that eliminates edge leakage by removing the parasitic edge transistors
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(a)
(b) Figure 5.3. (a) Example of the layout of an octagonal and a rectangular edgeless transistors, and (b) drain current versus gate voltage before and after radiation for a 15.3/0.3-µm rectangular edgeless transistor fabricated using technology D described in Section 4.4.2. Note that the left scale is logarithmic, while the right scale is linear (After [Anel-97]).
between the source and the drain is shown in Figure 5.1. This layout has no active diffusion edges overlapped by polysilicon that separates the source and the drain. This type of transistor is called an edgeless transistor, which is sometimes also referred to as an annular, re-entrant, enclosed-layout or as a closed-geometry transistor. Sometimes the transistor is referred to by the shape of the gate; for example circular, square, rectangular or octagonal gate transistor [Nowl-03]. The efficacy of the edgeless transistor in mitigating radiation-induced edge leakage is illustrated in Figure 5.2 [Laco-00]. Here, the drain current versus gate voltage as a
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16λ Source/Drain
2λ
Gate
Gate 4λ Source
Drain
Drain/ Source 2λ
2λ 4λ
2λ 10λ
4λ 4λ 8λ
(a)
(b)
Figure 5.4. (a) Critical dimension for a standard-edged transistor and (b) for an edgeless transistor.
function of total dose for a 0.25-µm edgeless NMOS transistor fabricated at TSMC shows that there is no significant increase in the off-state current up to a total dose of 2 Mrad(Si). Another example of the application of the edgeless transistor to mitigate edge leakage is shown in Figure 5.3 [Anel-97]. Figure 5.3(a) shows the layout of both octagonal and rectangular edgeless transistors. Figure 5.3(b) is the graph of the drain current versus gate voltage before and after radiation for a 15.3/0.3-µm rectangular edgeless transistor fabricated using technology D described in Section 4.4.2. While the curve corresponding to the logarithmic drain current scale on the left indicates no discernable changes in the drain current-gate voltage characteristics before and after 13 Mrad(Si), a slight difference can be observed when viewed on a linear scale on the right. This difference is consistent with a 6 mV negative threshold voltage shift. While edgeless transistors are highly effective in mitigating NMOS transistor edge leakage, this does not come without costs. Perhaps the most important cost is in transistor area. The minimum transistor W/L ratio for a standard-edged transistor is ~ 4λ/2λ = 2, assuming generic design rules where the minimum source/drain size is 4λ x 4λ (associated with the minimum size to open up a contact hole) and the minimum channel length is 2λ. As shown in Figure 5.4 (b), an edgeless transistor can be viewed as four separate trapezoidal transistors, each with an inner width of 4λ and an outer width of 8λ. Using a highly simplified model where the average value of the width is approximated as 6λ and the channel length is assumed constant, the value of W/L for a single trapezoidal transistor is calculated to be ~ 6λ/2λ. Since the edgeless transistor is composed of four of these trapezoidal transistors, this simplified calculation results in an effective W/L ratio of ~ 24λ/2λ = 12. For transistors made in
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Figure 5.5. Example of an edgeless transistor that will be used in the text to illustrate the challenge of modeling edgeless transistors. The transistor can be thought of as being formed by three different kinds of transistors, labeled in the picture as 1,2 and 3 (After [Anel-97]).
a given technology node with channel lengths greater than the allowed minimum, given by 2nλ and n is a real number greater than 1, the dependence between the W and L can be calculated, and it can be easily shown that W/L = 4(2n+1)/n. This indicates the W/L ratio decreases as the channel length increases for a given technology node. The footprint of the minimum standard-edged transistor is 80λ2, while the area for the edgeless transistor is 256λ2, resulting in an area increase by a factor of 256λ2/80 λ2 = 3.2. In actuality, the area penalty is much less than this factor, since most digital logic applications do not use minimum geometry NMOS transistors, but rather use transistors with larger W/L ratios to increase transistor drive currents and increase switching speed. Evaluations of area penalty for digital cells that use a combination of total dose mitigation techniques will be presented in detail in Section 5.2.3. The model used above is oversimplified. In reality, a rectangular edgeless transistor is not characterized by a single channel length. The effective channel length and the corresponding electric field for carriers traversing the device near the corners is variable and is different from that of carriers traversing the device away from corners. Furthermore, good design practices avoid sharp corners where the electric fields can become large and result in undesirable reliability consequences. All these factors make the modeling of an edgeless transistor a difficult challenge. Anneli et al. modeled the edgeless transistor shown in Figure 5.5 [Anel-97]. In this
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Source
Gate
Channel
Channel
Gate
Drain
Drain
Enclosed-Source Transistor
Enclosed-Drain Transistor
(a)
(b)
Figure 5.6. (a) Enclosed source and (b) enclosed drain transistors (After [Nowl03]).
modeling, the transistor is broken into three sub-elements, as shown in Figure 5.5. They found that the effective W/L ratio, (W/L)eff can be estimated from the following expression: 1
W L
2
3
d − d' +3 2 , 1 Leff
2α 1−α + 2K =4 d ' 1 eff α 2 + 2α + 5 ∗ ln ln α d '−2 Leff 2
[5.1]
where c, d, d’ = d - c√2 and α are defined in Figure 5.5. Leff is used in the formula to take into account gate length shortening due to interdiffusion, photolithography and etching. The three terms in equation [5.1] correspond to the three sub-elements in Figure 5.5. Due to the presence of the polysilicon strip necessary to integrate the gate contact outside the transistor, the third term in the formula is multiplied only by the factor three. A comparison of the calculated (W/L)eff of 14.8 with that extracted through measurements, 15.0, for Ldrawn = 0.28 µm indicates good agreement. When compared to standard-edged transistors, edgeless transistors have increased gate and source/drain capacitances [Alex-96], [Laco-00], [Nowl-03]. Furthermore, edgeless transistors are not symmetrical devices. The circuit designer has the choice of contacting the source and the drain to the inner and outer ring of the gate, respectively, or vice versa. Choosing the inner ring as the drain minimizes the drain area, and hence the drain to substrate capacitance [Alex-96], [Laco-00], [Nowl03]. It follows when designing for higher performance this is the usual choice. We
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will see in Chapter 6, however, that there is a trade-off between maximizing performance and maximizing reliability that is associated with the choice of the location of the source/drain contact [Maye-02], [Laco-02]. There is an asymmetry in the output characteristic of edgeless transistors that is associated with the nonsymmetrical geometry of the device. The output conductance (∂IDS/∂VDS at constant VGS) for an edgeless transistor with the drain on the inside (gdi) is greater than that for the same transistor with the drain on the outside (gdo). The fact that gdo is lower than gdi can be explained as follows: the distance between the pinch-off point and the drain, due to the conservation of space charge region for the same bias potentials, will be smaller when the drain is outside [Anel-99]. For this case, an increase in VDS will result in less of an increase in drain current, resulting in a lower gdo. A second class of closed geometry transistors, proposed by Nowlin et al., is the enclosed-source/enclosed-drain transistors. Figure 5.6 shows the layout of an enclosed-source and an enclosed-drain transistor [Nowl-03]. In this case, rather than being radial, the channel is more nearly transverse as in a standard-edged transistor. For this design, the polysilicon overlaps the active diffusion around the source/drain to eliminate the radiation-induced source-to-drain leakage path (the remainder of this paragraph follows [Nowl-03]). While this technique does not eliminate the transistor edges, it inserts an insulator between the enclosed contact and the parasitic edge transistor and removes the low resistance leakage path between the source and the drain. This insulator is polysilicon over gate oxide, which does not invert with exposure to radiation. For these transistors, W can be made smaller than for edgeless transistors, there is no limit for L and contacts can be added as needed to carry the current without increasing W by extending the source or drain away from the channel. There is, however, a much larger gate-to-source/gate-to-drain capacitance due to the excess polysilicon that encloses the source/drain. The excess polysilicon can also have significant resistance associated with it, especially in large devices. The designer has the option of enclosing either the source or the drain, and sometimes for compactness the designer will alternate between enclosed sources and enclosed drains. When the drain is enclosed, the parasitic gate-to-drain capacitance of the excess polysilicon appears as a Miller capacitance (excess parasitic capacitance multiplied by the gain of the transistor) when referred to the input. The combination of Miller capacitance and excess polysilicon resistance in large transistors can introduce a significant RC delay into a circuit. For this reason, the usual choice is to enclose the source. Enclosed source/drain transistors are probably best suited for small width devices, while for larger width devices edgeless transistors may offer less performance penalties. The drain current versus gate voltage as a function of total dose for a standardedged transistor and a closed-source transistor fabricated at a 0.18-µm foundry is shown in Figure 5.7 [Nowl-03]. These transistors were biased for worst-case with the gate at 1.8 V. The W/L ratio for both transistors was 1.2/0.2-µm. The fact that the pre-irradiation saturated drain current for both types of transistors is the same indicates that the excess ring polysilicon does not contribute to the drain current. The
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-3 101E+9
Drain Current (A)
1E+8
-5 101E+7
1E+6 -7 101E+5
1E+4 -9 101E+3
Pre-rad 50 krad 100 krad 400 krad
1E+2 -11 101E+1 1E+0 -13 101E-1 1E-2 -15 101E-3
-1.0
-0.5
0.0
0.5
1.0
1.5
Gate Voltage (V) (a)
-3 101E+9
Drain Current (A)
1E+8
-5 101E+7 -7 101E+5
1E+4 -9 101E+3 1E+2
-11 101E+1
Pre-rad
1E+0 -13 101E-1
400 krad
1E-2
-15 101E-3 -1.0
-0.5
0.0
0.5
1.0
1.5
Gate Voltage (V) (b) Figure 5.7. The drain current versus gate voltage as a function of total dose for (a) standard-edged transistors and (b) closed-source transistors fabricated at a 0.18-µm foundry (After [Nowl-03]).
effects of total-dose are clearly seen in the edged transistor where significant leakage current is observed at 50 krad(Si) and the device is completely shorted out at 400 krad(Si). The enclosed-source transistor, on the other hand, shows no increased leakage current even after irradiation to 400 krad(Si). Other potential layout solutions to mitigate edgeless solutions have been proposed in the past, but have not gained general acceptance as an effective approach. These include nested structures and dog bone structures, as summarized by Alexander [Alex-96]. A new approach to mitigating edge leakage was recently proposed by
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Vdd
Vss
N+ Contact
N+ Source
N-well P-epitaxial layer
P+ Channel Stop
P+ Substrate
Figure 5.8. Cross-section of a CMOS process with a p+ channel stop designed into the field-oxide isolation to mitigate inter-device isolation (After [Alex-01]).
Snoeys et.al., [Snoe-02]. This approach is for foundries that offer a dual-poly option. Edge mitigation is achieved by surrounding the n+ poly gate of an NMOS transistor with p+ poly over gate oxide. This prevents inversion at the p+ poly over gate oxide to field oxide interface, and hence, edge leakage. Data taken for an NMOS transistor fabricated at a commercial 0.25-µm foundry indicates hardness is achieved to 400 krad(Si). This approach, however, may violate a design rule that prevents n+ poly butting against p+ poly. If that were the case, it violates the strict definition of HBD. That does not mean, however, that if foundry acceptance of this design can be obtained, it is not an effective approach to mitigating edge leakage. 5.2.2 Mitigating Inter-Device Leakage As discussed in Chapter 4, inter-device isolation is compromised when the field-oxide inverts due to exposure to ionizing radiation. This can result in interdevice leakage. A design solution to this problem is to surround each transistor with a p+ diffusion ring, as shown in Figure 5.8. This can be performed as part of a standard CMOS process flow and does not require the insertion of additional masks or processing steps. The ring performs an important dual function [Nowl-03], [Laco01]. As a channel stop, the p+ diffusion prevents the inversion of the field oxide at that location by adjusting the local threshold voltage to a very high value. This maintains the integrity of the isolation between adjacent NMOS transistors and eliminates the n-well to n+-source leakage path. We will see in Section 5.3.3 that as a guard ring it also maintains the well or substrate bias, depending on the process, through the low resistance p+ diffusion which can mitigate single-event latchup. However, when using a p+ channel stop, the polysilicon gate cannot be allowed to cross the p+ ring, which can block the p+ implant and create a gap in the channel stop. This gap would provide a potential leakage path. Because of this restriction, a local polysilicon interconnect cannot be used in signal routing when channel stops are
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Drain Channel Stop
Gate
Drain
Source Gate
Channel
Channel Stop
(a)
Source
(b)
Figure 5.9. Layout of (a) an enclosed-source and (b) an edgeless transistor used in creation of two-input NOR gate standard cells for an evaluation of area penalties (After [Nowl-03]).
employed. Furthermore, there will be an area penalty for using p+ channel stops. Since the p+ diffusion ring must surround a transistor, the area penalty will depend on the design of the transistor (standard-edged, enclosed-source or edgeless transistors) that is being surrounded. Area penalties for the application of total-dose HBD techniques will be discussed in the following section. 5.2.3 Evaluation of Area and Performance Penalties To evaluate the effect of the application of total-dose HBD techniques on cell area, Nowlin et al. designed two-input NOR (2NOR) gates for a 0.18-µm process using standard-edged, enclosed-source and edgeless transistors and for a onegeneration behind 0.25-µm process using standard-edged transistors. The layout for the enclosed-source and edgeless transistors used in the design of these NOR cells are shown in Figure 5.9 [Nowl-03]. The full layout of these cells is shown in Figure 5.10 [Nowl-03]. The cells designed with standard-edged transistors use NMOS transistors with W/L ratio of 1.2/0.2. The cell designed with of 1.2/0.2, standard-edged PMOS transistors and employ channel stops. The cell designed using edgeless transistors use edgeless NMOS transistors with W/L ratio of 3.8/0.2, standard-edged PMOS transistors and employ p+ channel stops. The area penalty can be calculated using two different criteria. The percentage area penalty is defined as the area of a cell using non-a given layout design divided by the area of the same cell using standardedged transistors at the advanced technology node. For example, the percentage area penalty for the 2NOR cell designed at the 0.18-µm technology node using enclosed transistors is 40 µm2/32 µm2 = 1.25x. The generational area penalty is defined as the
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1.875x/0.7Gen
2.25x/1Gen 1.25x/0.2Gen
1x
W/L≈3.8/0.2
W/L≈1.2/0.2
W/L≈1.2./0.2
W/L≈1.2/0.2
Figure 5.10. Area comparison for two-input NOR gates designed for a 0.18-µm process using standard-edged, enclosed-source and edgeless transistors and for a one-generation behind 0.25-µm process using standard-edged transistors (After [Nowl-03]).
difference in the area of a cell using a given layout design and the area of the same cell using standard-edge transistors at a given technology node, divided by the difference in area for same cell using standard-edged transistors at one technology generation behind and the given technology node. For example, the generational area penalty for the 2NOR cell designed at the 0.18-µm technology node using enclosed transistors is (40-32) µm2/(72-32) µm2 = 0.2 Gen. The percentage/generational area penalties for the 2NOR cells in Figure 5.10 are 1.25x/0.2 Gen and 1.75x/0.7 Gen for the 0.18-µm enclosed-source and edgeless transistor cells, respectively, and 2.25x/1.0 Gen for the 0.25-µm cell. Hence, although there is an area penalty associated with using these total-dose HBD mitigation techniques, the penalty is less than one generation of CMOS. In a separate study, the performance penalties associated with the application of total-dose HBD techniques to a two-input NAND (2NAND) gate were evaluated [Laco-00]. Two-input NAND gates designed with standard-edged and edgeless transistors targeting a 0.35-µm process and standard-edged transistors targeting a onegeneration behind 0.5-µm process are shown in Figure 5.11 [Laco-01]. The minimum size of the HBD cell was fixed by the minimum area required for an edgeless NMOS transistor. The PMOS transistor was scaled to keep the W/L ratio close to twice the NMOS ratio. Edgeless PMOS devices were chosen because the
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2.3x/1.0 Gen
1.7x/0.7 Gen
Edgeless Transistors
Guard Bands
Std. Design 0.35-µm
HBD 0.35-µm
Std. Design 0.50-µm 1 Gen Behind
Figure 5.11. Area comparison for two-input NAND gates designed for a 0.35µm process using standard-edged and edgeless transistors and for a onegeneration behind 0.50-µm process using standard-edged transistors (After [Laco-00]).
Table 5.1. Comparison of Performance Characteristics for the NAND Cells in Figure 5.11 (After [Laco-00]). 0.35 µm
0.35 µm HBD 0.20 88.44
0.5 µm
W/L(p) Supply voltage, V Propagation delay, ns (FO=2)
5.00 9.00 3.30 0.10
12.00 20.00 3.30 0.09
5.00 9.00 5.00 0.14
Power dissipation, µW/MHz
0.29
Power delay product, aJ/MHz Gate density, Mgates/cm2
38 1.96
0.64 80 1.13
1.10 168 0.87
Maximum operating frequency, MHz Throughput per watt, Mgates-MHz/cm2/µW
376 6.82
402 1.75
328 0.79
Parameter Lambda, µm Cell area, µm2 W/L(n)
0.20 51.00
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0.30 114.75
inclusion of standard-edged devices increased the cell area when the required spacings between diffusion and polysilicon were included. Channel stops were used around both NMOS and PMOS devices. The percentage area penalty/generational area penalty for the HBD layout is 1.7x/0.7 Gen, similar to what was found for the 2 NOR gate discussed above. Again, the area penalty is less than one generation. The effects of the application of HBD techniques on other performance characteristics were also evaluated in this study and are summarized in Table 5.1 [Laco-01]. The performance of each technology was estimated assuming a simple long-channel approximation and assuming that the output was loaded by a capacitance equivalent to a fanout of two inputs, plus a fixed additional interconnect capacitance. The propagation delay of the HBD cell (0.10 ns) is slightly faster than that of the same cell built with standard-edged transistors (0.09 ns) because of the offsetting effects of increased drive current and increased capacitances from the edgeless transistors. The propagation delay of the HBD cell is more than 50% faster than that for the cell designed for a 0.5-µm technology (0.14 ns) because of the increased drive current associated with a minimum W/L ratio for an edgeless transistor of at least 12. The increased drive current will make HBD design faster than the 0.5-µm standard-edged design if the interconnect capacitance is large, but slower if the interconnect capacitance is small compared to the output and gate capacitances. Because of the larger capacitances associated with the edgeless layout, the power dissipation of the HBD cell is higher than for the standard-edged cell in the same technology, but is still less than the power dissipation for the cell designed use one-generation-behind technology. This assessment of the speed and power performance of each technology was made using a number of simplifying assumptions. A more careful extraction of the capacitances associated with the transistor nodes and interconnects and an assessment of the impact of the floating node capacitance on circuit performance is required for an accurate circuit timing assessment. A number of second order effects associated with the edgeless transistors have also not been considered, but may have a significant impact on the performance of the HBD technology. These include the asymmetrical behavior of the edgeless devices when source and drain are interchanged, the impact of the corners of the gates on the effective W/L ratio, and the impact of Ohmic losses on the distribution of current around the periphery of the edgeless transistors. Analysis of cell speed does not consider that when designing a circuit using HBD techniques, the circuit size will grow, which will increase the number and length of speed-limiting global interconnects. A more global evaluation of area and performance penalties associated with using edgeless transistors considered cells designed using a 0.25-µm process [Snap03]. An area comparison was made for 77 like cells across two cell libraries. One cell library was the existing foundry commercial library that used standard-edge transistors, while the other was a custom cell library that used edgeless transistors and channel stops. The custom cell library selected transistors of appropriate width so that the cells maintained similar propagation delay to the standard foundry cells,
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resulting in an increase in area and power. Under these assumptions, it was found that the average area penalty was 2.6x. The power comparison was limited to inverter, NAND and NOR cells only. It was found the power penalty spanned 2.5x – 3.5x. Clearly, more work needs to be done at the large circuit level and with the insertion of enclosed-source transistors to better understand the penalties associated with the application of total dose HBD to designing radiation-hardened components. 5.2.4 Summary of Designing in Total Dose Hardness Section 5.2 presented a summary of design techniques that can be used with standard CMOS processes to mitigate total dose effects. Two types of transistors that suppress edge leakage were presented. The edgeless transistor was demonstrated to be effective up to very high total dose levels. The novel enclosed-source/drain transistors were also discussed and shown to be effective in suppressing intra-device leakage up to the highest dose measured. The role of channel stops/guard rings to prevent field-oxide inversion and the associated loss of inter-device isolation was discussed. The application of these total-dose HBD techniques comes at the price of area and performance penalties. Three different studies quantifying these penalties were presented, but more work needs to be done to better understand the trade-offs, especially for large circuit designs. 5.3 Single Event Effects This section will serve as a brief review of single-event-effects in CMOS devices and the design techniques that can be used to mitigate these effects. For totaldose effects, if control over process is an available option, total-dose hardness can be achieved through process modifications only. For SEEs, however, even with control over the process, SEE hardness can only be achieved through a combination of process modifications and design approach. The process parameters that can be controlled to mitigate SEEs include the use of epitaxial wafers in lieu of non-epitaxial wafers, control of epitaxial layer thickness and doping level, and control of well profile doping. This discussion will be restricted to those effects to which digital electronic circuits are susceptible and which can be mitigated using design techniques, such as SEUs, SETs and SEL. Other effects, including single-event gate rupture (SEGR) and single-event burnout (SEB) are destructive effects that are not common in digital circuits. Single-event functional interrupt (SEFI) is a special case of SEU, and can be addressed using techniques similar to those discussed in the SEU section below. The material in these sections draws heavily from previous NSREC short course material on this topic. The reader is referred to the references for more detailed information.
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5.3.1 Single Event Upset This section will describe the basic mechanisms responsible for SEUs in CMOS logic, with an expanded explanation of SEUs in SRAMs. Three different classes of EU design mitigation techniques will be presented: charge dissipation techniques, spatial redundancy techniques and error correction techniques. Examples of these approaches will be given along with a discussion of the area, power and performance penalties associated with these techniques. 5.3.1.1 Basic Mechanisms A single-event upset occurs in a digital circuit when a particle strike causes data to change states in a storage element such as a flip-flop, latch, or memory bit. The energetic particles that are the cause of SEUs in integrated circuits can arise from many sources, including galactic cosmic rays, solar protons, trapped protons in the earth’s radiation belts, or trace radioactive materials in the package or board. As these energetic particles move through matter, they are slowed by interactions with the valence electrons in the material, which generate electron-hole pairs along the particle’s trajectory. The charge created along a silicon track of length L can be calculated with the help of equation [4.1]
Q = Lο
LET ο ρ οq Eeh
= L( µm) ο
10 − 4 µm / cm ο(2.42 g / cm 2 ) LET ( MeV − cm 2 / g )
(
(3.6eV ) ο 10 − 6 MeV / eV
)
Q( pC ) = 1.1x10 − 5 ο L( µm) ο LET ( MeV − cm 2 / g ) ,
ο1.6 x10 − 7 pC ⇒
[5.2]
where the density (ρ) of silicon is 2.42 g/cm3 and the electron-hole pair creation energy (Eeh) in silicon is 3.6 eV. A particle with an LET of 105 MeV-cm2/g, typical of a GCR particle creates ~ 1 pC of charge per micron of track. The “wire” of charge created by the trajectory of the ion can cause a temporary short in the circuit, which can lead to loss of data if the current affects a region of a circuit where information is stored. Direct ionization is the primary charge deposition mechanism for upsets caused by heavy ions, which are rather loosely defined as an ion with atomic number z ≥ 2. Lighter particles, such as protons and neutrons, usually do not produce enough charge by direct ionization to cause upsets in memory circuits. These particles can, however, produce upsets due to indirect mechanisms. When a high-energy proton or neutron enters a semiconductor, it may undergo an inelastic collision with a target nucleus. This can generate a nuclear reaction resulting in the emission of alpha particles or gamma particles and the recoil of a daughter nucleus, or a spallation reaction in which the target nucleus is broken into two fragments, each of which can
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Figure 5.12. When an energetic particles strikes a p-n junction, a line of electron-hole pairs are created, extending the depletion region as a funnel. This reduces recombination and increases the charge collected at the junction (After [Dodd-99]).
Figure 5.13. Illustration of the components of single-event-induced current flow, and the time constants associated with each.
recoil. Any of these reaction products can now deposit charge along their paths by direct ionization. Because these particles are much heavier than the original protons and neutrons, they can deposit greater line charge density as they travel through the semiconductor which is more likely to cause upsets than ionization crated by the original particle. Figure 5.12 shows a conceptual cross-section of an ion strike through a reverse-biased p-n junction, typical of the p-n junctions that are widespread in bulk CMOS circuits and tend to be the most sensitive sites for upset. The high-energy
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particle deposits a line of charge through the material until coming to rest at the end of its range or passing completely through the device. Current flows along the wire, creating an effective short across the p-n junction for the period of time needed to dissipate the generated charge, typically a few nanoseconds. The “funnel” shape of the depletion region under the junction is caused by the projection of the electrostatic potential of the heavily doped surface electrode along the “wire” created by the line of charges, effectively extending the depletion region deep into the semiconductor material. The current contributing to the SEE is the sum of the drift component of charges through the original junction depletion region plus the “funnel” extension of the depletion region in response to the applied or built-in electric field in the device, and a diffusion component from charges deposited outside the depletion region, which may move toward or away from the junction driven by the charge gradient. Some of the electron-hole pairs generated along the track recombine, although the effect of the funnel electric field is to separate the electron and holes and to decrease recombination. The resulting current profile associated with this charge collection is illustrated in Figure 5.13. Initial current flow is due to the drift component associated with the original depletion region and the funnel depletion region. The later contribution to the current flow is associated with diffusion of the charge toward the critical node. The SEE current gradually dies away as the excited electrons and holes recombine. The impact of this current on circuit operation depends strongly on the location and angle of the particle trajectory through the circuit, and the circuit response of an inadvertent current pulse at that particular location. 5.3.1.2 Single-Event Upsets in SRAMs
The SRAM serves as a useful example of an SEU-sensitive component, both because of its extensive use of floating storage nodes and because of its ubiquitous presence in space systems. Figure 5.14 shows a simplified representation of an SRAM cell. The heart of the device is composed of cross-couple inverters that store the logic state and act to provide stability to the logic state under noise or other extraneous signals. Figure 5.15 shows the 4 MOSFETs comprising the two crosscoupled inverters that form the latch that stores a single bit of information in an SRAM, along with the 2 access transistors at each edge of the cell [Baum-02]. When the access transistors are deselected by driving the Word Line low, charge representing the rail voltage VDD is stored at one of the floating common-drain nodes in the cell, and the other side is discharged to ground. Reversing the voltages on these two floating nodes by a write operation causes the memory state to switch from 1 to zero or vice versa. A particle strike at one of these sensitive nodes can generate an effective wire of charge between the floating node and the VDD or ground electrode in the well or substrate. Shown in Figure 5.15 is a strike on the drain of the “off” NMOS transistor of the inverter on the left whose input is in the 1 state and whose output is in the zero state. If enough charge is generated along the ion track, the resulting current can discharge the charged side of the cell. As the current flows through the struck transistor, the restoring “on” PMOS transistor sources current in an attempt to balance the particle-induced current. The restoring transistor,
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Bitline Comp
Ion Hit
Bitline True
WL
WL
Figure 5.14. Simplified diagram of an SRAM cell. The memory state is stored in the cross-couple inverters.
Figure 5.15. Schematic diagram of cross-coupled inverters in a 6-transistor CMOS SRAM. A particle strike at one storage node can cause a change in the node’s stored voltage state, which can propagate to the other node, upsetting the cell (After [Baum-02]).
unfortunately, has only a limited amount of current drive and a finite channel conductance. The current flow, therefore, induces a voltage transient at the drain of the restoring transistor. This voltage transient that is in response to the single-event current transient is actually the mechanism that can cause an upset in an SRAM cell. The voltage transient is essentially similar to a write pulse, and can cause the wrong memory state to be locked into the memory cell. Explained from a different point of view, the particle strike on the NMOS transistor causes a transient that tries to change he state of that inverter. The other inverter tries to respond quickly enough with
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Figure 5.16. Diagram of simulated node voltage in a CMOS SRAM cell after a particle strike with 3 different LET values. If the incident particle LET exceeds the cell’s LET threshold (42 MeV-cm2/mg for this cell), the cell changes state (After [Dodd-99]).
enough drive current to restore the original state. If this action is quick, no bit flip occurs. If not, the bit flip will stabilize and an upset will have occurred. The cell feedback time is simply the time required for the distributed node voltage to feed back through the cross-coupled inverters and latch the struck device in its disturbed state. This time can be thought of as the RC delay of the inverter pair and is related to the SRAM write time. The smaller the RC delay, the faster the cell can respond to voltage transients and the more susceptible the SRAM cell will be to SEU. Figure 5.16 shows a simulated ion strike at a sensitive SRAM node for three different LET rates and the impact of each strike on the stored voltage at that node [Dodd-99]. If the particle LET is less than the LET threshold for that node, a voltage glitch occurs, but will not propagate to the opposite node. If the LET threshold is exceeded, both inverters switch, resulting in a reversal of the stored information in the bit. This results in a single-event upset or SEU. The minimum charge associated with the integrated single-event current at a critical node that can cause an upset is referred to as the critical charge. The following section will present various circuit approaches to SEU mitigation. The primary goal of SEU hardening through circuit design techniques is to produce SEU-immune circuits using standard CMOS processing, with no additional mask or processing steps, while minimizing cell size, circuit speed costs and power consumption. Petersen defined a figure-of-merit for estimating the SEU error rate R (errors/bit/day),
R = 5 x10 −10 abc 2 / Qc2 ,
[5.3]
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where ab is the area of a critical node in square microns, c is the collection depth in microns, and Qc is the critical charge in pico Coulombs and is related to the threshold LET by equation [5.2] [Pete-83]. As the reader will see below, the critical charge is dictated by the choice of transistor dimensions and cell topology. 5.3.1.3 Designing In SEU Hardness – Charge Dissipation Techniques
A number of SRAM cell designs have been proposed to reduce the susceptibility of the cell to SEUs by the use of charge dissipation techniques. The first approach effectively increases the cell LET threshold by increasing the width of the transistors in the cell, thereby increasing their drive current capacity and their conductance. In the event of a particle strike on a critical node, the pull-up transistor will now be able to supply additional drive current to maintain the original latched logic state. Large high drive transistors also have increased node capacitance, which reduces the voltage excursion caused by the SEU injected charge (∆V = ∆Qinj/C). Increasing the capacitance of critical nodes to reduce the voltage change due to SEU injected charge is the basic concept behind capacitive hardening of circuits. An example o f a 2NAND cell with standard-sized and oversized transistors is shown in Figure 5.17 [Baze-02]. The application of this increase results in an increase in cell area and power dissipation roughly proportional to the ratio of the transistor widths. There is no significant speed penalty using this approach. A technique that has been widely used by the dedicated rad-hard foundries involves the insertion of resistors between the cross-coupled inverters in the SRAM cell, as shown in Figure 5.18 [Dodd-99]. These resistors increase the effective RC delay impeding the propagation of the erroneous signal triggered by an ion strike, allowing the pull-up PMOS device enough time to restore the collapsed node voltage before a switch in the cell’s memory state, thereby improving its immunity to SEUs. The feedback resistors increase the delay of the cell to normal write operation. There is usually some area penalty associated with the implementation of this mitigation approach that results from the insertion of the feedback resistors into the memory cell. The additional area is proportional to the required resistance to achieve the desired single-event-error rate and the Ohms per square required to provide that resistance. Through clever design and layout, this area penalty can be minimized. This technique is difficult to implement, however, because of the difficulty in maintaining process control for the fabrication of the required high-resistance feedback resistors and because the resistance values change with temperature. A high-resistivity layer is not available in most commercial CMOS processes. Because of this fact, this approach is not available as a HBD option for many targeted commercial CMOS foundries. A variation of this approach is shown in Figure 5.19 [Rock-92]. An alternative approach involves the use of excess capacitance at each of the floating nodes to increase the critical charge needed to switch cell states. While feasible, this approach is also not commonly employed because it also consumes excess area and slows down the read and write speeds, and because well-characterized capacitors are also not typically supported by CMOS foundries.
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(a)
(b)
Figure 5.17. 2NAND cell with (a) standard width transistors and (b) wider transistors (After [Baze-02]).
Figure 5.18. SRAM design incorporating feedback resistors to allow time for PMOS device to restore upset node before error can propagate (After [Dodd-99]).
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Figure 5.19. Gated resistor hardened CMOS SRAM cell design (After [Rock92]).
A cell design that replaces the polysilicon intra-cell resistors with gated resistors is shown in Figure 5.19 where the gated resistors are controlled by the write line [Rock-92]. The advantage of this approach is that during a write pulse the feedback resistance can be lowered to reduce the impact of the feedback element on operating speed. During a write operation, the resistor gates are clocked into a lowresistance condition by the wordline pulse, greatly improving the write speed over a standard resistively hardened SRAM. At all other times the resistors are in the “off” (high-resistance) state and protect against SEU in the usual manner. The gatedresistor SRAM is therefore faster than a standard resistively hardened SRAM, has reduced temperature dependence, and may require no additional area to implement. For this cell, the lower limit of SEU hardness is determined by the minimum “off” resistance, while the upper limit in circuit speed is determined by the minimum “on” conductance. These gated resistors are actually thin film polysilicon transistors and are fabricated using two levels of polysilicon separated by a thin interlevel thermal oxide layer. Because of this, implementation of this approach requires a process that supports two levels of polysilicon, which although fairly common, is not available in all technologies. 5.3.1.4 Designing In SEU Hardness – Spatial Redundancy
An alternate approach to mitigating SEU effects is to reproduce the information spatially on the silicon. If each block of information is separated so that the probability of upset of two different blocks is negligibly small, then the information can be correctly reconstructed even if one block of information experiences an upset. By requiring multiple node hits to create an upset that cannot be reconstructed, the effective SEE cross-section of the device is greatly reduced.
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\
Figure 5.20. Triple modular redundancy applied to latched logic (After [Blac02]).
SEU hardening by redundant circuit design approaches is based on three fundamental concepts: (1) Information storage redundancy maintains a source of uncorrupted data after an SEU, (2) feedback from the non-corrupted data storage location can cause the corrupted data to recover after a particle strike, and (3) the “intelligence” needed in the feedback to cause recovery of the proper location can be derived from the fact that the current induced by a particle hit flows from n-type diffusion to p-type diffusion. For example, if a memory cell is constructed from only p-type transistors then it cannot be upset to a 0 while storing a 1 (when storing a 1, the voltage on the drain is 5V and the voltage on the well is 5 V), while a memory cell constructed from only n-type transistors cannot be upset to a 1 while storing a 0 (when storing a 0, the voltage on the drain is 0 V). The most straightforward implementation of this SEU hardening concept is triple modular redundancy (TMR). A schematic of a typical TMR cell is shown in Figure 5.20 [Blac-02]. In this circuit, a single unhardened logic latch is replaced by three unhardened logic latches. Each of these latches is connected to the same clock and the same data line. The output of the three latches goes to majority voting logic. If a single energetic particle strikes one and only one of the latches and creates an upset in that latch, the other two latches will retain the correct logic state, and the majority voting logic will output the correct state. The area and power penalties associated with this approach are approximately 3x. This is a brute force approach to mitigating SEU effects. There are some potential problems with this technique. If
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the state of the latch is not refreshed frequently in comparison to the expected upset rate, errors can accumulate such that the cells making up the TMR latch contain double errors. In space, the fluence of energetic particles is omni-directional. Therefore, particle strikes may occur parallel to the surface of the silicon or at shallow angles such that they can strike two cells simultaneously and generate multiple errors. Consequently, the cells in the TMR latch should be laid out to minimize the opportunity for multiple upsets from a single strike and the latch should be refreshed periodically to ensure against accumulation of errors. [Heid-99], [Alex03]. Triple modular redundancy is inefficient for SRAMs because of the excessive associated area and power penalties, but is very effective for individual latches. The voter circuit can be implemented using only combinational logic (i.e., no memory elements). Thus the voter can be relatively immune to SEUs. However, the voter may still be susceptible to SETs, discussed in Section 5.3.2, and thus may add an additional element of susceptibility. Special care must be taken to design the voter circuit to operate reliably in the space environment. This technique could also be classified as an error correction technique as discussed in Section 5.3.1.5 below. A more elegant, area-efficient storage cell that uses a 4-node redundant structure to mitigate SEUs is the Dual Interlocked storage Cell (DICE) [Cali-96]. This cell is suitable for replacing latches and flip-flops distributed within logic blocks in CMOS in order to make them tolerant to upsets. It may also be used to implement SEUhardened SRAMs. The block diagram of the DICE storage element is shown in Figure 5.21 and the corresponding schematic is shown in Figure 5.22 [Cali-96]. It employs two conventional cross-coupled (horizontal) inverter latch structures N0-P1 and N2-P3 connected by bi-directional feedback (vertical) inverters N1-P2 and N3-P0. The four nodes, X0…X3, store the data as two pairs of complementary values (i.e., 1010 or 0101) that are simultaneously accessed using transmission gates for the write or read operation. It uses a dual node feedback control in order to achieve immunity to upsets. This means that the logic state of each of the four nodes of the cell is controlled by the two adjacent nodes located on the opposite diagonal. The two nodes on each diagonal do not depend directly on each other. Rather, their state is controlled by the two nodes on the other diagonal. The inverters represented in Figure 5.22 are either n-type or p-type transistors. They form two opposite feedback loops, a clockwise p-transistor loop and an anti-clockwise n-transistor loop. To better understand how the DICE storage element works, consider the logic state 0 (0101). The horizontal inverter loops N0-P1 and N2-P3 are in conduction, forming two latches that store the same data at their nodes X0-X1 and X2-X3. The pairs N1-P2 and N3-P0 are blocked. They perform the feedback interlock function, isolating the two horizontal latches. A negative upset pulse at node Xi will potentially induce a positive pulse perturbation at node Xi+1 through the p-transistor feedback Pi+1. However, it will not be able to affect the same logic state stored at node Xi-1
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Figure 5.21. Principles of the dual interlocked storage cell (After [Cali-96]).
Figure 5.22. Schematic diagram of the dual interlocked storage cell (After [Cali96]).
since the feedback transistor Ni-1 will be blocked by the negative upset pulse at node Xi. The propagated positive perturbation at node Xi+1 will not be further transmitted through transistor Pi+2. Nodes Xi-1, Xi+1 are thus isolated and conserve their logic state unaffected. Hence, logic changes are temporarily induced only at two nodes Xi, Xi+1. The perturbation is removed after the upset transient due to the state-reinforcing feedback ensured by the other two nodes Xi-1, Xi+2 through transistors Pi and Ni+1. It should be noted that if two simultaneously sensitive nodes of the cell which store the
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(a)
(b) Figure 5.23. Layout of (a) a typical CMOS SRAM cell and (b) DICE cell (After [Cali-96]).
same logic state (i.e. either nodes X0-X2 or nodes X1-X3) are struck at the same time, either by a single particle or two particles impacting quasi-simultaneously, the immunity is lost and the cell can upset. The probability of this occurring from a single particle can be made very low through proper layout, so that the critical charge leading to an upset cannot be collected at both nodes. For minimum sized junctions, properly aligned and separated in a carefully constructed design, the ratio of multiple node strikes to single node strikes can usually be kept on the order of 10-3 to 10-4
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Figure 5.24. An alternate latch design that uses14-transistors [Liu-92].
[Mavi-00A], [Alex-03]. Since in deep-submicron layouts, first-order worst-case error rates are only on the order of 10-5 to 10-6 errors/bit/day, second-order worst-case error rates are reduced to 10-8 to 10-10 errors/bit/day [Mavi-00A], [Alex-03]. The layout of a typical 6-transistor SRAM cell and a 12-transistor DICE memory cell is shown in Figure 5.23 [Cali-96]. The area of the DICE cell is 1.9x the area of the SRAM cell for this layout. This layout assumes only two-levels of metal interconnect. With more levels of interconnects available for signal routing, additional area savings is possible. The DICE storage element requires additional drive current to write the cell because of the additional transistors used in the design. In practice, it may be necessary to increase the DICE cell area to obtain the necessary aspect ratio to avoid double node strikes. A University of Idaho design of an SEU-hardened latch cell design containing 14 transistors and consisting of two loadable storage structures is shown in Figure 5.24 [Liu-92]. The lower storage structure is a modified six-transistor cell consisting of only n-type devices and the upper structure is a modified six-transistor cell consisting of only p-type devices. The lower cell contains incorruptible 0s and the top structure stores incorruptible 1s. In order for the feedback mechanism to effect recovery from SEU, transistors M2 and M4 are sized to be weak compared to M12 and M14. Complementary n-channel devices M16 and M17 are added to disconnect
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Table 5.2. Hamming code requirements for single-error correction and double-error detection for data blocks of varying lengths. Data Bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Check Bits 3 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6
Total Bits 4 6 7 8 9 11 12 13 14 15 16 18 19 20 21 22
Data Bits 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Check Bits 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7
Total Bits 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39
the dc current path in the p-channel section eliminating the static power consumption that otherwise results from the weak 1 level produced at N1 (N2) not turning M13 (M15) completely off. Similarly p-channel devices M6 and M7 are added to disconnect the dc current path in the n-channel section. The cell buffer transistors M8, M9, M18 and M19 restore the output voltage levels to the rails and isolate the storage nodes from high capacitance loads. The TMR, DICE storage latch and the University of Idaho latch represent just three of many cell designs that use spatial redundancy to mitigate SEU. There are many variations upon a theme of these cell types optimized for different applications. A more in depth presentation of SEU-hardened cell designs can be found elsewhere [Heid-99]. 5.3.1.5 Error Correction Techniques
The techniques described in the previous two subsections represent attempts to prevent an SRAM cell from upsetting in a particle environment. In this section, methods for hardening a memory element by checking for errors in unhardened memory elements and ignoring or rewriting elements that have been corrupted are discussed. Triple modular redundancy, discussed in Section 5.3.1.3, is a special case of the more general approach known as Error Detection And Correction (EDAC) or Error Control Codes (ECC). As its name suggests, EDAC is a methodology in which extra bits are added to a block of bits to detect when one or more bits have been corrupted, and to correct the corrupted bit, if possible. For example, a single parity bit can be added to a bit
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string of arbitrary length. The parity bit is adjusted to ensure that the arithmetic sum of all bits in the string is even. Then if an upset occurs anywhere in the string, simple addition of the bit string provides an indication (an odd parity) that an error has occurred, but determination of the location of the specific bit error is not possible. Furthermore, the parity bit itself may upset, creating an additional source of errors. The single-parity-bit approach also cannot detect an even number of upsets in the same bit string. TMR can be viewed as a very inefficient form of EDAC because it requires 2 bits of overhead for every bit in the circuit. An ingenious code known as the Hamming code has been devised to provide both detection of an upset bit and its location in the string. The Hamming EDAC technique adds one parity check bit to each of multiple arrangements of the bits within a data string in sequences that enable reconstruction of the erroneous bit in case of an upset, including protection of the check bits themselves. The most common application of Hamming EDAC is for Single Error Correction and Double Error Detection (SECDED). SECDED means if there is a single error in a word of any length it can be detected and corrected, but if there are two errors in a word, it can only be detected but not corrected. The Hamming technique requires overhead, in the form of additional bits, as shown in Table 5.2 for SECDED. Note that the overhead becomes more efficient as the bit string length increases. For example, a 16-bit string can be corrected with 6 additional bits using this approach (38 percent overhead), while a 32-bit string requires 7 additional bits (22 percent overhead). Using a periodic scrub technique, hardware can be designed to search the memory for errors and regenerate corrected bit strings automatically. Additional check bits can be incorporated to correct multiple bit errors if desired. Hamming code is a further example of the use of a circuit design technique to harden an otherwise radiationsensitive circuit element against single-event upsets. A more thorough discuss on EDAC, including Reed-Solomon (RS) and Bose, Chauduri and Hocquenghem (BCH) codes can be found elsewhere [Heid-99]. 5.3.2 Single Event Transients
Single event upsets considered the effect of an energetic particle strike directly on a critical node of a latched or sequential logic element, resulting in a possible change in the logic state of that element. Single event transients address errors that can result from an energetic particle strike on non-latched elements, such as combinatorial logic, clock line and global control lines. A single-event transient (SET) is the result of a voltage disturbance on a signal line caused by a particle strike. The current produced by a particle strike can cause a capacitive element such as the output load of a combinational logic element to charge or discharge, causing a temporary change in the voltage on that signal line. Whether this voltage transient will propagate any significant distance through the combinatorial logic depends on both the width of the transient voltage spike and the speed (capacitance) of the CMOS transistors. The critical width is the minimum width of the transient pulse required for the transient to propagate through an infinitely long chain of inverters. If the
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Figure 5.25. The critical transient width versus feature size for unattenuated propagation (After [Mavi-00B], [Mavi-02]).
transient width is narrower than this critical width, the transistors do not have the speed to respond to the transient and the transient will be attenuated and die out after passing through only a few gates. The critical transient width versus feature size for unattenuated propagation is shown in Figure 5.25 [Mavi-00B], [Mavi-02]. As technology advances and feature size shrink, the critical transient width narrows. Hence, as CMOS is scaled, narrower and narrower transients can propagate through the circuit. Baze pointed out that while a transient pulse greater or equal to the critical transient width would propagate infinitely, a pulse of half this width would terminate in the first gate [Baze-97]. Although there is still great uncertainty in the transient widths induced by cosmic rays or other energetic particle, the best estimate is 100 – 200 ps. From Figure 5.25, it can be deduced that for feature sizes below 0.25 µm, transient signals associated with energetic particle strikes are not attenuated and will propagate as normal circuit signals. To understand how a transient in non-latching logic can result in a circuit error, consider the case illustrated by Figure 5.26 [Baum-02]. Figure 5.26 shows a series of combinatorial logic elements terminating at a sequential logic element. If an energetic particle strikes the second block of combinatorial logic and if the induced transient is of sufficient width to propagate unattenuated through the remaining combinatorial logic element to the input of the register, there is a potential that this
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Figure 5.26. An SET can cause an upset in a circuit if the erroneous signal arrives at a storage element simultaneously with the clock edge that triggers the information into the register (After [Baum-02]).
Figure 5.27. Temporal relationship for latching an SET as an error (After [Mavi00B], [Mavi-02]).
transient will be interpreted as a signal and the state of the register could be put in error. Whether this occurs or not will depend on if the transient signal is coincident with the clock edge that latches data into the register. The transient will be incorrectly interpreted as a valid signal if it arrives during the time period extending from a setup time before the clock edge to a hold time after the clock edge. This concept is illustrated in Figure 5.27 [Mavi-00B], [Mavi-02]. The fanout at each logic gate can cause these errors to propagate into many independent branches of the logic, potentially inducing more than one error from a single transient. This is shown schematically in Figure 5.28. Since the probability of a transient being captured depends on the number of falling clock edges arriving at the latch per unit time, i.e., the clock frequency, it is expected that the SET upset rate will depend linearly on
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Figure 5.28. SETs can propagate through multiple branches of a circuit, resulting in multiple errors from a single transient.
Figure 5.29. The total error rate is the sum of the clock-independent SEU error rate and the clock-dependent SET error rate (After [Blac-02]).
clock frequency. This assumes the setup and hold times are independent of clock frequency, which is usually the case. The total circuit upset error rate is the combination SEU and SET rates, as shown in Figure 5.29 [Blac-02].
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VDD IN0 OUT IN1
Capacitor
Figure 5.30. Capacitively loading the output of combinatorial logic provides SET immunity by decreasing circuit speed (After [Baze-02]).
5.3.2.1 Designing in Single Event Transient Hardness
Single event transients can be mitigated using HBD techniques. One technique involves slowing down circuit speed, increasing the critical minimum pulse width for propagating a transient unattenuated through a chain of combinatorial logic. This can be done by capacitively loading the logic chain, as shown in Figure 5.30 [Baze-02]. Alternatively, increasing the drive of the transistors in the combinatorial logic cell will effectively decrease the transient width and voltage change, reducing the chance of propagating an SET. The other SET mitigation techniques discussed in this section will involve incorporating temporal redundancy. Figure 5.31 shows a triple voting scheme that uses temporal filtering to prevent an SET from corrupting the voter output [Blac-02], [Mavi-02]. In this circuit, the data input is connected to three D-flip-flops in parallel. The clock signal goes directly to the top flip-flop, is delayed by ∆t at the middle flip-flop, and is delayed by 2∆t at the bottom flip-flop. If a transient is induced on the data input, it will arrive at all three flip-flops simultaneously. The clock signals, however, will not arrive at the same time and, at most, only one clock signal will arrive coincident with the transient on the data line. When the asynchronous voting occurs, two inputs will contain the correct signal, while at worst only a single input will contain an erroneous signal, and thus the output of the voter will be the correct logic signal. Alternately, the delay can be imposed on the input signal instead of the clock signal. In this cell the clock delays are generated internally in the temporal latch
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Figure 5.31. SET-hardened latch design that incorporates temporal offsets in the clock inputs to three flip-flops to ensure that an SET on the data input does not trigger more than one error in the inputs to the voter (After [Blac-02], [Mavi02]).
itself. This circuit is the temporal analog of the spatial redundancy TMR technique described in Section 5.3.1.3. As in the spatially redundant case, the area and power penalty is approximately 3x. The insertion of two extra temporal sampling times increases the latch setup time by 2∆t. This increased setup time clearly results in a lower maximum clock operating frequency which is given by 1 / Feff = 1 / F0 + 2∆t ,
[5.4]
where F0 is the original maximum clock frequency and Feff is the maximum clock frequency of the temporal latch [Mavi-02]. Spatial and temporal TMR can be combined within a single cell to achieve both SEU and SET immunity. This brute force method requires nine latches, four out-of-phase clocks and a majority voter, as shown in Figure 5.32 [Mavi-00A], [Mavi-02]. While effective, the area and power penalty of approximately 9x discourages this approach. A latch developed at The Mission Research Corporation achieves SEU immunity much more efficiently. In this cell, shown in Figure 5.33, the output of the majority voter is fedback to the input of a MUX, which also has the data signal as a second input [Mavi-02]. By using the MUX and the majority voter at three separate times, the temporal latch is effectively replicated, not in space but in time. In this way, the equivalent of spatial TMR is achieved without physically replicating the circuitry. This temporal latch is also immune to transients occurring on the input clock node. Any transient on the clock momentarily switches the selected MUX input producing a possible transient at the MUX output. Since this represents the data input to the temporal sampling circuitry, it is eventually rejected by the voting circuitry. Thus,
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Figure 5.32. Generic latch that incorporates both spatial and temporal TMR to eliminate both SEUs and SETs (After [Mavi-00A], [Mavi-02]).
Figure 5.33. Minimal temporal sampling latch replicating itself in time to suppress both SEUs and SETs (After [Mavi-02]).
this cell does not require SET-hardened clock nodes. Furthermore, with an appropriate increase in the ∆T value, the latch can be made immune to upset from double node strikes. 5.3.3 Single Event Latchup
An energetic particle strike can cause additional problem in CMOS circuits known as single event latchup. SEL can occur in bulk CMOS circuits in any of the numerous parasitic pnpn circuit paths between VDD and ground normally occurring in a CMOS
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VDD n+ Contact
VDD p+ Source Anode
VSS n+ Source Cathode
VSS p+ Contact
n-well p- epi p+ substrate
Figure 5.34. Cross-section of a CMOS circuit showing the substrate, well and diffused regions that form a parasitic pnpn Semiconductor-Controlled Rectifier (SCR) (After [Alex-01]).
circuit, usually comprising the source of a PMOS transistor, the n-well, the psubstrate, and the source of an NMOS transistor as shown in Figure 5.34 (Alex [-01]). This pnpn structure is the configuration for a classic Semiconductor Controlled Rectifier (SCR), which can be stable in either its off or on (conducting) state. Figure 5.35 illustrates the cross-coupled pnp and npn bipolar transistors and biasing resistors that are formed from the pnpn layers that comprise the SCR. Normally the n-well is maintained at the same potential as the PMOS source, and the p-substrate is held at the NMOS source potential, which prevents the SCR from latching. However, after a particle strike, the generated photocurrents can cause voltage drops in the substrate or well that may forward bias one of the parasitic bipolar transistors in the pnpn circuit, triggering the device into its on state. The current – voltage characteristic of an SCR is shown in Figure 5.36. If the injected current increases the voltage to above the latch voltage VL, the SCR goes into a highly conducting state. If the supply voltage is greater than the holding voltage VH, the high current state will be maintained unless power cycling occurs. In some cases, sufficient currents can be generated in the latched state to damage sensitive metal lines, which are not designed to carry the high currents that can result from a latchup condition. As technology continues to scale and power supply voltages continue to decrease, the supply voltages will likely become smaller than the holding voltages and latchup will cease to be a concern. In addition, it can be shown that a necessary condition for latchup to be sustained is that the product of the parasitic transistor betas be greater than one (βpβn > 1). The minimum LET of an energetic particle that triggers latchup is referred to as the latchup LET.
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VDD
Rp
pnp βp
βn npn
Rn
Figure 5.35. Lumped equivalent circuit of the parasitic pnpn SCR. Injection of current into the base of either of the transistors associated with an energetic particle strike can trigger the SCR into a high current state.
I
IH IL VH
VL
V
Figure 5.36. Current – voltage characteristics of an SCR. If the injected current increases the voltage to above the latch voltage VL, the SCR goes into a high conducting state. If the supply voltage is greater than the holding voltage VH, the high current state will be maintained unless power cycling occurs.
5.3.3.1 Designing In Single Event Latchup Hardness
Single-event latchup is typically avoided in CMOS circuits by reducing the resistance of the well or substrate, thereby increasing the injection current required to trigger latchup. This can be accomplished by the proper attention to well and substrate
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x n+
p+
n+
p+
n-well
p-substrate
Laser Latchup Threshold (pJ)
Figure 5.37. The n-well to diffusion spacing X between can be increased to increase the latchup threshold LET (After [Osbo-98B]).
14 12
600 nm ps laser HP 0.5-µm CMOS
10 8 6 4 2 0 4λ
8λ
12λ
16λ
Well-to-Diffusion Length X (λ) Figure 5.38. Latchup threshold measured using an SEU Laser Simulation technique as a function of the well-to-diffusion spacing (X) in units of the design scaling constant λ. The minimum design rule for X for this 0.5-µm process was 4λ.
contacts in the design or by incorporating an epitaxial structure over a highly conductive substrate. Latchup can also be prevented by utilizing an insulating substrate, such as SOI, which prevents current flow between adjacent transistors.
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10 5
26.57
12.33
18.99
20.19
15
8.2
20
7.61 10.6
25
HP 0.5 22.95 24.11
Orbit 1.2
30
2.07 2.86
(pJ) SEL Threshold
35
AMI 1.6
0
None (Min)
n+
p+
Dual n+/p+
Figure 5.39. Laser latchup threshold for test structures with no guardbands, a single n+ guardband, a single p+ guardband and dual n+/p+ guardbands for three different CMOS technologies (After [Osbo-98B]).
Commercial foundries are concerned about latchup in their commercial products, since voltage transients as well as radiation can trigger latchup. Thus, design rules are typically in place for commercial designs to prevent adjacent well and active area edges from approaching too closely, thereby avoiding high-gain parasitic bipolar devices in the CMOS substrate. While CMOS processes that are susceptible to SEL are normally avoided for space applications, several HBD techniques can be applied to improve a CMOS circuit’s SEL immunity. Design rules that extend the distance between well edges and active regions, as shown in Figure 5.37, can reduce the gain of the lateral parasitic bipolar transistors that create the latching SCR, and therefore increase the latchup LET threshold [Osbo-98B]. The latchup threshold measured using an SEU Laser Simulation technique as a function of the well-to-diffusion spacing (X) in units of the design scaling constant λ is shown in Figure 5.38 [Osbo-98B], [LaLu-02]. The minimum design rule for X for this 0.5-µm process was 4λ. By quadrupling X, the latchup threshold increases by approximately a factor of 2x. It should be noted that quadrupling X could result in minimal area impact, because diffusions approach well edges in only a small percentage of a typical CMOS circuit layout. The application of guardbands around active regions is also effective in mitigating latchup. The insertion of guardband(s) also increases the separation between the n-well edge and the diffusion region, decreasing the lateral transistor bipolar gain. The heavily doped guardbands also act as a carrier sink, removing carriers that otherwise would be available to initiate the latchup process. Guardbands
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also decrease the resistance in parallel with the anode and cathode gates of the SCR, especially if the guard bands are silicided to reduce their resistivity. In general, guardbands control the potential in the latch path and prevent the latchup from being initiated. Application of this technique does not require process changes or additional masks. Laser latchup thresholds for test structures with no guardbands, a single n+ guardband, a single p+ guardband and dual n+/p+ guardbands for three different CMOS technologies are shown in Figure 5.39 [Osbo-98B]. The three CMOS processes are the AMI 1.6-µm, the Orbit 1.2-µm and the HP 0.5-µm processes defined in Chapter 4. As can be observed, the addition of guardbands increases the latchup threshold voltage significantly. The increase in latchup threshold between a design with no guardbands and one with dual guardbands is between a factor of 3x – 10x, depending on the technology. 5.3.4 Single Event Functional Interrupts
Single-event functional interrupt (SEFI) is the term given to the nondestructive disruption of the operation of an integrated circuit by an energetic particle strike, typically caused by an upset in a flip-flop or register in the control circuitry that causes the circuit to lose the ability to function correctly. For example, an upset in a microprocessor instruction register would likely cause the microprocessor to cease to operate. SEFI therefore most commonly represents a specific case of the more general category of SEUs as discussed in Section 5.3.1.1 – 5.3.1.2. The techniques used to mitigate SEUs as discussed in Section 5.3.1.3 – 5.3.1.5 are therefore also applicable to the mitigation of SEFIs. 5.3.5 Summary of Single Event Effects and Mitigation Techniques
In Section 5.3, SEE basic mechanisms and mitigation techniques have been discussed. The interaction of an energetic particle striking a p-n junction and the role of depletion width extension forming a funnel and its role in charge collection was presented. A detailed explanation of SEUs in SRAMs was also presented. Mitigation of SEUs was discussed from the approach of the application of charge dissipation techniques, of spatial redundancy techniques and of error correcting techniques. The basic mechanisms responsible for SETs were presented, as well as mitigation techniques that include the use of capacitive coupling and temporal filtering. Singeevent latchup basic mechanisms and were also presented. Mitigation techniques included the modification of well spacings and the insertion of guardbands. In summary, several HBD mitigation techniques exist for SEUs, SETs, SELs and SEFIs. 5. 4 Cell Libraries
Cell libraries are a collection of cells, each with a specific function, that are made available to designers of Application Specific Integrated Circuits (ASICs). The cells in the cell library are used as basic building blocks by the designer to design an entire circuit/component. Commercial foundries typically provide proprietary cell libraries to customers who will be targeting their foundry processes. Using these
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foundry-supplied cell libraries, only a small subset of the HBD techniques discussed above can be implemented. For example, spatial TMR can be implemented using a commercial cell library by combining latch cells and simple combinatorial logic gates to implement the voter circuitry. If, however, additional total-dose hardness and/or latchup mitigation is needed, even this TMR cell cannot be designed using a standard foundry cell library. Hence, for all but the least demanding of radiation requirements, custom cell libraries must be designed and validated to implement circuits with a full suite of HBD techniques available. These custom cell libraries might include the use of edgeless and/or enclosed-source/drain transistors, channel stops, various SEU- and SET-hardened cells such as spatially-and/or temporally-redundant latches, and modified cell spacings and/or guardbands for SEU mitigation. Cell libraries can be optimized based on different criteria. For example, foundries often offer a choice of a high-performance cell library or a low-power cell library. Within these two types of cell libraries, it is possible to offer cells with varying degrees of radiation hardness built into them. It is possible to customize a cell library to specific radiation requirements. In developing a cell library, a choice can also be made between developing a scalable cell library or a cell library optimized for a specific process. A scalable cell library is designed around a set of design rules that are likely to be scalable to the next generation of CMOS and can be ported to multiple foundries. By developing a scalable cell library, significant cost is saved when the cell library is migrated to the next technology node. Use of scalable libraries will likely sacrifice area, power and other performance benchmarks to achieve scalability. On the other hand, a cell library optimized for a given process can exploit the design rules for that specific foundry, and hence, the potential exists for designing a cell library that minimizes area, power and other performance penalties with respect to a standard foundry cell library. Another major consideration in the development of a cell library is cost compared to the expected return on investment. HBD cell libraries need to be validated for performance and immunity to total dose and SEEs. SEE validation is especially important since it is very sensitive to the placement of critical nodes. Cell libraries intended for harsh environments need to be designed and validated for operation outside the temperature range specified by a commercial foundry, for example over the Mil. Temp. range as opposed to 0 – 80 °C range typically specified by a commercial foundry. It must also be verified that the foundry process meets the reliability requirements specified for the cell library for a space application. This issue, as well as design approaches to improve reliability will be presented in Chapter 6. After the development of a cell library, the cell library must also be maintained and supported. Changes could be required by changes in the commercial foundry process flow, or may be made in response to a cell library user needing additional and/or modified cells. This requires an infrastructure that supports cell library maintenance.
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5.5 CAD Tools
Computer-aided design (CAD) tools are used in the design of integrated circuits to proceed from an initial functional concept through a schematic circuit diagram to the placement of the geometrical patterns that constitute the final circuit layout. Individual CAD tools perform logical simulation of the design at various levels of abstraction, synthesize detailed circuits from high-level descriptions, generate circuit schematic diagrams, translate the design into cells from a standardcell or gate-array library, perform testability insertion and fault grading, place and route the instantiations of the selected library elements into a compact layout, check design rules, check electrical rules, extract parasitic circuit parameters, and perform static and dynamic timing simulations of the final layout. Commercial CAD tools have evolved to perform each of these functions, and represent the basic components of a tool set to design space-qualified circuits using design-hardening techniques. Such tools are already in use at the radiation-hard CMOS foundries. To account for radiation effects using commercial CAD tools, several modifications or additions must be made to the design procedure. For example, totaldose effects in MOSFET-based integrated circuits can be simulated from first principles. The generation rate of MOSFET interface states and trapped charges can be used to project device behavior over the life of the part in space, given the spectrum of energetic electrons and protons in the anticipated space environment as a function of estimated shielding. The electrical behavior of the MOSFET in a radiation environment can then be predicted based on the structure of the MOSFET and the physics of the radiation interactions. However, the usefulness of this approach depends on detailed knowledge of the process used to manufacture the MOSFET, which may not be available from a commercial foundry. As a more practical alternative, end-of-life circuit performance can be simulated using commercial tools if accurate models of MOSFET behavior are available. A simple approach to obtaining accurate end-of-life transistor parameters is to use commercial BSIM extraction tools to extract SPICE parameters from irradiated transistors. This phenomenological approach does not predict device behavior from first principles, but simply measures radiation effects on transistor performance and extrapolates circuit performance from these observed changes. BSIM extractions can be performed at incremental levels of radiation dose to gain insight about performance changes during operation lifetime. The accuracy of this approach depends on the consistency of radiation-induced changes in MOSFET behavior across a lot, and must be reevaluated from lot to lot to ensure that process variations or changes do not affect radiation behavior. The impact of energetic particle strikes on SEU and SEL in CMOS integrated circuits must also be understood and accounted for in the circuit design. Models have been developed that can predict the location and magnitude of charge deposited in the substrate of an integrated circuit from a galactic cosmic ray or an incident proton at a given location in a circuit. Device simulation tools can then translate this deposited
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charge distribution into electrical device behavior. Simple lumped-element circuit models of these effects at circuit nodes can then be used to predict the impact of such an event on circuit behavior. As device dimensions shrink to become comparable with the size of the charge funnels created by these cosmic events, three-dimensional simulation tools must be used to calculate the impact of spatial charge distribution on circuit performance. Ultimately the utility of these simulation tools will depend on their accuracy in predicting the impact of high-energy particle strikes on circuit performance compared with test results. To date, a phenomenological approach has been used successfully in developing design-hardened integrated circuits for space use. Total-dose effects have been accommodated by simulating worst-case circuit performance using radiationdegraded end-of-life MOSFET parameters. Single event effects have been mitigated by using design techniques that avoid the known effects of charge injection. The efficacy of these phenomenological approaches has been proven by their success in providing measurable radiation hardness improvements to components built using commercial foundry processes. However, as device dimensions continue to shrink, a better understanding of the effects of radiation on circuit performance will be necessary to develop a cost-effective design methodology for design-hardened components. In support of a HBD infrastructure, it will be beneficial to provide the tools to predict the performance of advanced CMOS technologies in radiation environments and to enable their seamless integration into a commercial design flow. 5.6 Approaches to Using HBD
This section will discuss a generalized approach to the application of HBD to fabricate radiation-hardened components. As was discussed in detail in Chapter 4, the evolution of CMOS technology has led to increased total dose hardness levels. In addition to total-dose effects, single-event effects must also be addressed when designing a radiation-hardened component. The first step in the HBD process is to ensure that the component requirements are clearly specified and understood. Once this is achieved, the required CMOS technology node can be selected from one or two CMOS generations. The selection process will be influenced by several factors, including integration level, performance and power requirements, as well as process interconnect metal and interlevel dielectric technology. Once candidate processes are chosen, a test chip can be fabricated in these technologies and used to evaluate the intrinsic radiation hardness of the candidate processes. Once the intrinsic radiation requirements are understood, the degree of the application of HBD techniques can be determined. This includes a decision on whether to use an existing cell library or to design a new cell library based on availability and cost considerations. A rough order-of-magnitude estimate of the expected area, power and performance penalties can then be made. In addition, process reliability must be considered. Using this analysis, a final selection of the process technology and cell library (either existing or to be designed) can be made.
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Use Foundry Cell Library • High Performance • Reliability Assured • Limited in Use of HBD Techniques
• Highest Performance • Minimum Area Penalties • Smaller Radiation Margins
Design at Foundry • Proprietary Tools • Design Engineers Experienced with Cell Library
Radiation Hardness • Intrinsic TID Hardness • SEE Designed in Using Cell Library Elements • System Mitigation Approaches
Radiation Hardness
Figure 5.40. Design approach for producing a component optimized for maximum performance.
Custom Cell Library • Develop Rad-Hard Cell Library • Performance Penalty • Area Penalty • Full Spectrum of HBD Techniques Available • Increased RH Margins • Area Penalties • Reduced Performance
Design at Contractor • Contractor Tools • Design Engineers with Space Parts Experience
Radiation Hardness • Enhanced TD Hardness by Enclosed Transistors, Channel Stop • SEE Designed Implemented in Cell Library Elements
Radiation Hardness
Figure 5.41. Design approach for producing a component optimized for maximum radiation-hardness margins.
To illustrate some of these issues, the design flow for components designed for optimized performance and optimized radiation-hardness margins, as shown in Figures 5.41 and 5.42, respectively, will be discussed. To achieve the highest performance, the natural choice is to use the foundry’s cell library, which has been optimized for performance. Using the foundry cell library assures that accurate BSIM (SPICE) models will be available and that the reliability promised by the
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foundry will be guaranteed. This approach also allows the use of the foundry to design and validate the physical layout of the component using proprietary tools and engineers with design experience in the targeted process technology. The designers will not, however, have experience with designing components with radiation effects requirements. As discussed earlier, using the foundry cell library greatly restricts the HBD techniques available for use. For example, the lack of availability of total-dose mitigation techniques means that the component will be limited to the intrinsic totaldose hardness of the targeted process. Similarly, this approach restricts the available SEE mitigation techniques. The resulting component can achieve maximum performance but at the cost of reduced radiation-hardness margins. At the other end of the design spectrum, a circuit can be designed to achieve maximum radiation-hardness margins. To achieve maximum margins, a custom HBD cell library assures that the full spectrum of HBD techniques is available. As discussed earlier, the use of HBD techniques is often accompanied by area, power and performance penalties. Since a custom cell library is likely to use non-standard transistors, the transistor modeling necessary to validate performance must be generated independently. Using this approach, the circuit layout and verification are performed by a contractor using contractor tools, using designers that have experience with designing components for a radiation environment. The resulting component will achieve maximum radiation-hardness margins but will likely have area, power and performance penalties with respect to the high-performance approach described above. 5.7 Examples Of Components Fabricated Using HBD Approaches
Over the last several years, there have been a number of radiation-hardened components designed using HBD techniques and fabricated at commercial CMOS foundries. A number of corporations are also utilizing HBD to supply spacequalified components as part of their business strategies. BAE Systems (BAES), Manassas, VA, has developed a hardened version of the IBM PowerPC 750 [Burc02]. The commercial foundry process is intrinsically latchup immune with an intrinsic total-dose hardness of 200 krad(Si) (in a low dose-rate environment). The designers needed to remove dynamic logic and low threshold voltage transistors from the IBM design and to design in SEU and SET hardness, which included SEU hardening the data latches, clock trees and two 32 KB caches. This microprocessor was fabricated at a 0.25-µm commercial foundry and will achieve a clock frequency of 133 MHz over the Mil. Temp. The area penalty was approximately 30% compared to the equivalent commercial part in the same technology. An SEU hardness of 1x1010 upsets/bit-day (W.C. 90% GEO) was experimentally verified. BAES has also designed and fabricated 4MB SRAMs using the same methodology. In addition, BAES is in the process of designing the megagate payload ASICs for a major DoD communication satellite system. Boeing Space Systems (BSS), El Segundo, CA, launched a megagate ASIC initiative in 1996. In 1998-1999, BSS developed nine ASICs (0.8 – 2.9 Mgate) for a major communication satellite system (Thurya) which
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were fabricated in the IBM 0.25-µm process targeting the IBM SA-12 cell library [Sund-03]. Most ASICs contained small memory arrays, while one ASIC contained a large memory array. IBM did the “back end” physical design. All ASICs were manufactured with first pass success and are now on orbit and performing flawlessly. A second major satellite program (Spaceway) design is ongoing at BSS and will use the IBM 0.16-µm process and the SA-27 cell library. It will contain ASICs with up to 5 Mgates [Sund-03]. The high-energy physics community in CERN, Geneva, Switzerland has used HBD techniques to produce radiation-hardened ASICs for the Large Hadron Collider facility [Snoe-00]. Edgeless transistors and guardbands were used for total-dose hardness and to provide SEL immunity. Faccio et al. showed that the area penalty for a DFF was 50% [Facc-00]. CERN has designed approximately 75 different ASICs using this HBD approach. The number of chips needed per circuit type range from 120,000 down to 100 [Facc-03]. About 14 ASICs are needed in more than 20,000 pieces, and another 31 ASICs are needed in a number between 2,000 and 20,000. All of these 45 ASICs were successfully implemented [Facc-03]. No failures have been observed associated with total-dose exposure, even though several of the chips received total dose levels above 10 Mrad(Si) [Facc-03]. In addition, CERN found that the application of these HBD techniques had no visible impact on yield [Facc03]. The ASIC types designed by CERN include readout integrated circuits for particle detectors, A/D converters, digital and analog memories, system control functions, time-to-digital conversion, transmission of digital and analog data via optical fiber and clock recovery and clock recovery circuitrs [Camp-99], [Snoe-00], [Facc-01], [Anel-01], [Rive-01]. Numerous HBD cell libraries that target commercial CMOS processes have been developed at Mission Research Corporation, Albuquerque, NM, Boeing Space and Communications, Seattle, WA and UTMC, Colorado Springs, CO. Currently, there are a number of other HBD component development efforts underway. 5.8 COTS and HBD
Although COTS is not the subject of this short course, it may be useful to the reader to discuss some issues related to using COTS in a radiation environment. There are pros and cons to using COTS for space applications. The pros include a large variety of available components, high performance and low component costs. The cons include short availability lifecycles, the possibility of process changes that can change the radiation characteristics, lack of tracability, costs associated with qualification and the inability to get reliability data from the manufacturer. The trend toward increased total-dose hardness has been observed in many commercial components. For example, the commercial Intel Pentium III, biased during irradiation, has been shown to be total-dose hard to above 400 krad(Si) [Howa-01]. Similar trends have been observed in other commercial components. While these
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components can have considerable total-dose hardness and while many commercial processes are naturally immune to SEL, without some degree of SEU hardness the application of these components to space mission will be limited. There is, however, an interesting development in the commercial microelectronics industry that is leading toward increased SEU hardness in some commercial components. As CMOS has scaled to smaller dimensions, the terrestrial SEU error rate has increased to the point where for high reliability microelectronic applications, such as for server systems, SEU mitigation has proven necessary. To date, the commercial industry has not tolerated an area penalty greater than 10% in designing in SEU hardness, so the available mitigation techniques have been applied mostly at the system level. The scope and level of SEU hardness is changing daily, however, and this trend should be closely monitored in the future. 5.9 Summary
This chapter has discussed various HBD techniques, different approaches for using these techniques and examples of circuits using HBD. Total-dose HBD techniques were described, included the application of edgeless and enclosed source/drain transistors to mitigate intra-device leakage and channel stops to mitigate inter-device leakage. HBD techniques applicable to various SEEs were discussed. The basic mechanism associated with SEU was presented. HBD SEU mitigation techniques included charge dissipation techniques, spatial redundancy techniques and error correction techniques. SET basic mechanisms were also presented, as well as mitigation techniques that included capacitance loading and the application of temporal filtering techniques. The SEL basic mechanism was also presented, as well as mitigation techniques that included increasing critical cell spacings and the use of guardbands. An overview of cell libraries and the issues involved in the design of radiation-hard cell libraries was discussed. The role of CAD tools in the HBD infrastructure was also discussed. A presentation on various approaches and issues associated with these approaches to designing a radiation-hardened component at a commercial foundry was made. Examples of components successfully fabricated at a commercial foundry using HBD techniques were presented. Finally, a discussion of COTS in the context of HBD was also presented.
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6 Qualification and Reliability 6.1 Introduction The qualification of microelectronic components fabricated at commercial foundries requires a different approach than that for radiation-hardened components fabricated at a dedicated rad-hard foundry. Furthermore, the reliability guaranteed from a commercial foundry may not be directly applicable to a radiation-hardened component fabricated at the same foundry because of differences in the environmental requirements for the part developed for a space environment. Issues pertaining to the qualification and the assurance of reliability of an HBD component will be discussed in this chapter. In addition, approaches to extending reliability through design will also be discussed. 6.2 Qualification A critical function in the procurement of radiation-hardened components for a space environment is testing and qualification. When parts are procured from a radhard foundry, the rad-hard foundry typically does the qualification and the customer receives a fully space-qualified component. However, when electronic components are procured through commercial foundries, the foundries will not be responsible for the space qualification of the parts. The onus of qualification now falls upon the component user. This requires that the traditional method of procurement and qualification will be somewhat different for HBD components. In one likely scenario, the system contractor will procure the radiation-hardened component from a HBD component supplier, who will design the component using HBD techniques. The HBD component supplier will partner with a commercial foundry that will manufacture the part and deliver wafers to him. Wafers received by the supplier from the foundry will be diced, packaged, tested, and qualified as required to assure a qualified part is delivered to the user. Testing and qualification will provide assurance to the customer that the delivered components will meet all performance and reliability requirements over specified temperature and radiation conditions. Since the HBD approach utilizes commercial foundries, which do not typically participate in Qualified Manufacturers Listing (QML) procedures as defined in military specification MIL-I-38535, qualification of components designed and manufactured using HBD must proceed on a lot-by-lot basis, using industry standard methods such as Radiation Lot Acceptance Testing (RLAT), in conjunction with standard military component test methods outlined in MIL-STD-883E, for example, to qualify parts for space system use. The HBD supplier will be responsible for meeting all qualification requirements, including maintaining traceability of all parts to specific manufacturing lots and wafers as required. If the system contractor is the HBD component supplier, than the responsibility for testing and qualification will rest with the system contractor. Regardless of the business model, a party other than the commercial foundry will likely perform the testing and qualification.
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6.3 Reliability As discussed in Chapter 3, dimensional scaling of commercial CMOS technologies has historically proceeded at a faster pace than reductions in supply voltages, resulting in increased electric fields in each new technology generation. This has exacerbated the reliability problems associated with advanced CMOS devices because the increased electric fields in each technology generation are a source of damage to materials and interfaces. As commercial CMOS technologies advance, there has been an increasing willingness to accept lower reliability margins in commercial systems in order to exploit the performance advantages of these technologies. In general, however, space system applications require that electronic components demonstrate higher reliability than terrestrial systems because replacement is difficult or impossible for fielded systems and because component failures may have serious implications to the satellite users. Furthermore, typical service life tends to be longer for space systems as well. It is essential, therefore, that the long-term reliability of commercial technologies be considered when selecting or designing parts for insertion into space systems. Since commercial foundries set their reliability requirements to meet terrestrial applications, there is no guarantee that the reliability of a component fabricated at a commercial foundry will meet the stringent reliability requirements of a component targeted for space applications. For example, while commercial foundries typically guarantee a level of reliability over a “commercial” temperature range of 0 to 80 °C, that required for satellites is typically over the Mil-temp range of –55 to 125 °C. Since most of the failure modes that determine device lifetime, such as oxide breakdown and electromigration, are thermally-activated mechanisms, there is no guarantee that the reliability to 80 °C will result in acceptable reliability to 125 °C. For hot-carrier reliability, which is not thermally-activated, the lifetime degrades as temperature is lowered. Hence, there is no guarantee that the reliability to 0 °C will result in acceptable reliability to -55 °C. A separate issue involves the potential lowering of reliability margins in future CMOS processes as part of a strategy of “market segmentation.” That strategy proposes having variations of processes and/or qualification criteria for different market segments. For example, if microprocessor manufactures for home computers decide most users will accept a microprocessor with a lifetime of 5 years because users replace their home computers every 4 years, then the potential exists that wearout mechanism lifetimes will be relaxed to gain additional performance at a given technology node. While the user of a COTS component has little control over reliability other than constraining temperature excursions and adjusting power supply voltages, the user of a custom designed HBD component has numerous options to enhance component reliability. This, however, can only be achieved with penalties in performance or area. This will be discussed in detail in the following section. 6.3.1 Designing in Hot-Carrier Reliability This section will discuss options the component and system designer have to enhance component reliability. This will be illustrated for the hot-carrier
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Decease in Gmmax (%)
Figure 6.1. Hot-carrier damage is created by channel carriers that are accelerated to high velocity by the channel electric field. When these carriers impact the drain, impact ionization occurs, injecting electrons and some holes into the gate oxide and the spacer oxide near the drain. This can result in the creation of interface states and/or trapped fixed charges that can lead to device degradation.
100
10
Typical Lifetime Criteria
1
0.1 102
103
104
105
Stress Time (s) Figure 6.2. Hot-carrier damage results in geometric degradation of the transconductance with time. For digital applications, the hot-carrier lifetime is typically defined as the time at which the normalized decrease in transconductance reaches 10%.
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degradation mechanism. Hot-carrier degradation is associated with the high lateral electric field that exists in the channel of a CMOS device. These fields reach a peak near the drain and are typically greater than 105 V/cm for devices without LightlyDoped Drain (LDD) technology. Use of LDD technology typically reduces the peak electric field by an order-of-magnitude. As shown in Figure 6.1, hot-carrier damage is caused by channel carriers that are accelerated to high velocity by the channel electric field. These carriers are described as “hot” because they have kinetic energy much greater than thermal energy kBT (where kB is the Boltzman constant). When these carriers approach the drain, impact ionization occurs, injecting electrons and some holes into the gate oxide and the spacer oxide near the drain. This can result in the creation of interface states and/or trapped fixed charge that can lead to device degradation in the form of reduction of the transconductance and/or threshold voltage shifts. As shown in Figure 6.2, hot-carrier damage results in geometric degradation of the transconductance with time. For digital applications, the hot-carrier lifetime is typically defined as the time at which the normalized decrease in transconductance reaches 10%. For an more thorough discuss of hot-carrier reliability in CMOS, see, for example [Hu-89], [Take-95]. In most modern CMOS processes, the hot-carrier lifetime is a process design choice. By controlling the LDD doping level, the peak channel electric field can be selected. The lower the doping level, the more the channel electric field is reduced. Lowering the LDD doping level, however, increases the “contact” resistance in series with the intrinsic MOS device, lowering the maximum drive current and reducing switching speed. Hence, performance is directly traded off for increased hot-carrier lifetime by the process engineering team. In the following sub-sections, the options a component and system designer has to increase the hot-carrier lifetime of a CMOS part will be explored. 6.3.2 Reducing the Supply Voltage The system designer, in conjunction with the component designer, can increase hot-carrier lifetime by reducing the chip supply voltage. The hot-carrier lifetime (τHC) depends exponentially on the supply voltage (VDS) [Hu-89], [Take-95]:
τ HC ∝ exp(−1 / V DS ) .
[6.1]
Hence, small changes in the supply voltage can result in large changes in the hotcarrier lifetime. Experimental data on the hot-carrier-induced degradation in the normalized transconductance at two different supply voltages for a 0.18-µm commercial CMOS process is shown in Figure 6.3. These data indicate that for this particular process, a 0.5 V change in the supply voltage results in ~300x change in the hot-carrier lifetime. It follows that to obtain a 2x increase in the hot-carrier lifetime would require only a very small reduction in the supply voltage. A small reduction of the supply voltage would result in a small decrease in the maximum possible switching speed for a given process and design.
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L=0.18 micron
Decease in Gmmax (%)
100
Vd=2.25V Vd=2.75V
10
Typical Lifetime Criteria
1
0.1 1.E+00
1.E+02
1.E+04
1.E+06
Stress Time (s) Figure 6.3. Experimental data on the hot-carrier-induced degradation in the normalized transconductance at two different supply voltages for a 0.18-µm commercial CMOS process.
6.3.3 Reducing the Clock Frequency Hot-carrier damage occurs when a MOS device has a moderate to high voltage applied to the gate and a high voltage applied to the drain. As shown in Figure 6.4, the hot-carrier damage occurs during a narrow temporal window when both the input and output voltages are high. For CMOS digital circuits, the hotcarrier damage occurs only during the switching portion of the duty cycle. Hence, the higher the clock frequency, the greater the number of switching events and the greater the hot-carrier damage. It follows that for applications that may require high transistor density but may not require maximum performance, hot-carrier lifetime can be extended beyond that guaranteed by the foundry by operating the component at less than the maximum possible clock frequency. Since the insertion of HBD layout and circuit techniques may result in a speed penalty for the entire component, this benefit may occur naturally. 6.3.4 Increasing the Channel Length The peak electric lateral field is inversely proportional to the channel length in a MOS device. Since a designer is not required to design to the minimum channel length for a given technology node, if maximum performance is not required the designer can design his transistors with longer than the minimum allowable channel lengths. Hot-carrier simulation results are shown in Figure 6.5 illustrating that a hot-carrier lifetime reduction of ~ 4x can be achieved by relaxing the design from devices with 0.18-µm channel lengths to devices with 0.19-µm channel lengths.
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VDD Vout
Vin
CLOAD
(a)
Voltage
Input Hot-carrier damage region Output Time (b)
Figure 6.4. (a) A CMOS inverter driving a load capacitor and (b) the associated switching waveforms for the inverter input and output terminals. The hot-carrier damage occurs during a narrow temporal window when both the input and output voltages are high.
6.3.5 Optimize Load Capacitance As shown in Figure 6.6, the width of the transient switching event where the hot-carrier damage occurs increases with increasing load capacitance. By optimizing the circuit design to minimize gates that have large fanouts, such as clock and reset trees, hot-carrier damage can be partially mitigated for these critical circuit elements. This may require over-sizing transistors that are in the hot-carrier reliability critical path to provide the necessary hot-carrier margins. 6.3.6 Optimize Edgeless Device Design As shown in Figure 6.7 (a), for standard-edged transistors the peak electric field is constant at the drain across the entire width of the device. This device, reflecting the symmetric nature of the device performance with respect to the choice
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Simulation/Modeling 1.E+09 1.E+08
10 years
10 years
Lifetime (s)
1.E+07 1.E+06 1.E+05 1.E+04 1.E+03
L=0.18 µm L=0.19 µm
1.E+02 1.E+01 1.E+00
0.3
0.4
0.5
0.6
0.7
1/Vds Figure 6.5. Hot-carrier simulation results illustrating a hot-carrier lifetime reduction of ~ 4x is achieved by relaxing the design from devices with 0.18-µm channel lengths to devices with 0.19-µm channel lengths.
Voltage
Input
Voltage
Hot-carrier damage region
Input
Large CLOAD
Small CLOAD Output Time
Figure 6.6. The width of the transient switching event where the hot-carrier damage occurs increases with increasing load capacitance.
of the source and the drain contact, is also symmetric in terms of the hot-carrier lifetime. The hot-carrier lifetime is independent of the choice of source and drain
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D rain S ource
E
C onventional M O S FE T (a)
E Drain Source
Annular MOSFET (b) Figure 6.7. The channel electric field for a (a) convention standard-edged transistor and (b) an annular transistor.
contacts. As discussed in Section 5.2, the edgeless device is not symmetric with respect to the choice of the source and drain contact. This allows for an interesting tradeoff between performance and hot-carrier reliability [Maye-02]. To understand this tradeoff, it is helpful to look at the spatially dependent electric field for an annular transistor, as shown in Figure 6.7 (b). In this figure, the source is the interior contact and the drain is the exterior contact. As can be seen, the electric field lines diverge at the drain edge, indicating the electric field is reduced as
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Decrease in Gmmax (%)
100
Vd=2.75 V Vg@Ibmax 10
1
Annular: Drain Inside Annular: Drain Outside Standard Edged
0.1 1
10
100
1,000
10,000
100,000
Stress Time (s) Figure 6.8. The normalized transconductance as a function of time for an annular transistor with the drain on the inside, for an annular transistor with the drain on the outside and for a standard-edged transistor stressed to produce hot-carrier damage.
compared to applying the same source-drain voltage for the equivalent standard-edge device. This reduction in the peak electric field at the drain edge should result in an increase in hot-carrier lifetime. This was experimentally verified as shown in Figure 6.8. This figure shows the normalized transconductance as a function of time for an annular transistor with the drain on the inside, for an annular transistor with the drain on the outside and for a standard-edged transistor stressed to produce hot-carrier damage. The shortest hot-carrier lifetime is for the annular transistor with the drain on the inside, while the longest hot-carrier lifetime is for an annular transistor with the drain on the outside. The lifetime for the standard-edged transistor is intermediate between the two annular transistor configurations. As discussed in Section 5.2, the maximum performance for an annular device is achieved with the drain in the interior of the device where the drain capacitance is reduced relative to the inverse configuration. As was just discussed, the longest hotcarrier lifetime is achieved for an annular device with the drain on the outside. Hence, the circuit designer can trade off performance for reliability, if necessary. This tradeoff also applies to other edgeless layout geometries, although the electric field variations may be isolated to the corners of the device.
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6.4 Summary This chapter has explored issues related to the qualification and reliability of HBD devices fabricated at a commercial foundry. Unlike for components fabricated at the rad-hard foundries, the responsibility for parts qualification rests with the user, not with the foundry. The determination of reliability wear-out mechanisms and their associated wear-out lifetimes must also be accomplished. In general, the designer has a number of options available to enhance reliability. The specific options available to extend hot-carrier lifetime were discussed. Similar options exist for other failure mechanisms, subject to the constraints of the underlying failure physics.
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7 Summary Hardness-by-design is a new approach to supplying radiation-hardened components. It directly leverages the huge investment in the CMOS scaling to achieve higher performance at lower power. This short course presented a review of the history and current state of the commercial CMOS microelectronics industry, provided a compact description of the space environment and reviewed total-dose and single-event effects basic mechanisms. This short course also illustrated the trend in commercial CMOS processes toward increased total-dose hardness. The remainder of this short course described specific design techniques to mitigate the entire spectrum of radiation effects in CMOS microelectronics. This included design methodology to mitigate intra- and inter-device leakage, single-event upsets, singleevent transients and single-event latchup. A discussion of the area, power and other performance penalties incurred by the application of specific HBD techniques was described. Finally, the role of cell libraries and issues surrounding their development was discussed, as well as various approaches for applying “hardness-by-design” principles and the role of “hardness-by-design” for COTS components. Several examples of components produced using HBD methodologies were presented. Issues related to the qualification and reliability of HBD components was discussed. Design techniques were presented to extend hot-carrier lifetimes beyond those guaranteed by a commercial foundry. The future potential and limitations of HBD will become better understood in the future.
8 Acknowledgements Many people helped in the creation of this short course. I would like to acknowledge and thank Don Mayer for all his valuable contributions to The Aerospace Corporation’s efforts on hardness-by-design and for his valuable inputs to this short course. I would also like to acknowledge Everett King, Steve Moss, Steve LaLumondiere and Lew Cohn for valuable conversations and editing comments. I would like to thank Joe Benedetto for his efforts in assembling this short course. This work was sponsored by The Aerospace Corporation’s IR&D Program.
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[Laco-99A] R.C. Lacoe, J.V. Osborn, D.C. Mayer, S. Brown and D.R. Hunt, “Total Dose Radiation Tolerance of a Chartered 0.35-µm CMOS Process,” 1999 IEEE Radiation Effects Data Workshop Record, IEEE cat. no. 99TH8463 pp. 82-86, Jul. 1999 [U] [Laco-99B] R.C. Lacoe, D.C. Mayer, J.V. Osborn, B.K. Janousek, and S. Brown, “Total Dose Radiation Tolerance on the Road to 0.25-µm Technology,” 1999 GOMAC Digest of Papers., pp. 530-533, Mar. 1999 [U] [Laco-00]
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R.C. Lacoe, “Reliable and Hardened-By-Design Components for Space,” Pres. 2002 Hardness-By-Design Workshop, Albuquerque, NM, Aug. 2002 [U]
[Lera-99]
J.L. Leray, “Total Dose Effects: Modeling for Present and Future,” 1999 IEEE Nuclear and Radiation Effects Conference Short Course, Norfork, VA (July 1999) and refereces within [U]
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M. N. Liu and S. Whitaker, “Low Power SEU Immune CMOS Memory Circuits,” IEEE. Trans. Nuc. Sci. vol. 39, no. 6, pp. 1679-1684, Dec 1992 [U]
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T.P. Ma and P.V. Dressendorfer, Ionization Radiation Effects in MOS Devices and Circuits, Chapter I, ed. T.P. Ma and P.V. Dressendorfer, Wiley and Sons, New York, 1989 and references within [U]
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M. Bohr , “Breaking Barriers to Moore’s Law,” Pres. Intel Development Forum, Feb. 2002 [U] and ftp://downlaod.intel.com/research/silicon/MarcykIDF_022802.pdf [U]
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M. Manghisoni, L. Ratti, V. Re and V. Speziali, “Radiation Hardness Perspectives for the Design of Analog Detector Readout Circuits in the 0.18-mm CMOS Generation,” IEEE Trans. Nuc. Sci. vol. 49, no. 6, pp. 2902-2909, Dec 2002 [U]
[Mavi-00A] D.G. Mavis, P.H. Eaton and J.R. Bailey, “Development of a Design Methodology for Preventing Single Event Disruptions in Deep Submicron Microcircuits,” Draft Final Report MRC/ABQ-R-1998., Aug. 2000 [U] [Mavi-00B] D.G. Mavis and P.H. Eaton, “SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design,” Proc. 2000 Mil. Aero. Appl. Prog. Dev. Tech. Conf., 2000 [U]
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[Mavi-02] D.G. Mavis and P.H. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits,” Proc. Of 2002 Intl. Rel. Phys. Symp., pp. 216-225, Apr. 2002 and references within [U] [Maye-97]
D.C. Mayer, J.V. Osborn, R.C. Lacoe, and G. Yabiku, “Total Dose Tolerance of 0.8- and 0.5-µm CMOS Processes,” 1997 GOMAC Digest of Papers., pp. 618-621, Mar. 1999 [U]
[Maye-99]
D.C. Mayer, R.C. Lacoe, J.V. Osborn, S.C. Moss, and B.K. Janousek, “Commercial Approaches for Future Space Systems,” Proc. Of 44th Intl. SAMPE Symp., pp. 20642073, May 1999 [U]
[Maye-02]
D.C. Mayer and R.C. Lacoe, “Enhanced Reliability in Commercial CMOS Processes by the Application of Hardness-By-Design Techniques,” Pres. 2002 Micro, Elec. Rel. Qual. Workshop, Manhattan Beach, CA Dec. 2002 [U] and http://www.aero.org/conferences/mrqw/2002papers/B_Mayer.pdf
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J.E. Mazur, “The Radiation Environment Outside and Inside a Spacecraft,” 2002 IEEE Nuclear and Radiation Effects Conference Short Course, Phoenix, AZ, Jul. 2002 [U] http://wwwdev:180/conferences/mrqw/2002papers/B_Mayer.pdf
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F.B. McLean and G.A. Ausmand,l Jr., “Simple Approximate Solutions to Continuous-Time Random-Walk Transport,” Phys. Rev. B, vol. 15, no. 2, pp. 10521061, Jan. 1977 [U]
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F.B. McLean, G.A. Ausmand,l Jr., H.E. Boesch, Jr., and J.M. McGarrity, “Application of Stochastic Hopping Transport to Hole Conduction in Amorphous SiO2,” J. Appl. Phys. vol. 47, no. 4, pp. 1529-11532, Apr. 1976 [U]
[McLe-89] F.B. McLean, H.E. Boesch, Jr., and T.R. Oldham, “Electron-Hole Generation, Transport and Trapping in SiO2,” Ionization in Radiation Effects in MOS Devices and Circuits, Chapter 3, ed. T.P. Ma and P.V. Dressendorfer, Wiley and Sons, New York, 1989 and references within [U] [McWh-90] P.J. McWhorter, S.L. Miller and W.M. Miller, “Modeling the Anneal of RadiationInduced Trapped Holes in a Varying Thermal Environment,” IEEE Trans. Nuc. Sci. vol. 37, no. 6, pp. 1682-1689, Dec 1990 [U] [Moor-65]
G.E. Moore, “Cramming Moore Components onto Integrated Circuits,” Electronics, no. 8, Apr. 1965 [U] and ftp://downlaod.intel.com/research/silicon/moorespaper.pdf [U]
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G.E. Moore, “No Exponential is Forever,” Presented at Intl. Sol. State Circ. Conf., Feb. 2003 [U] and ftp://downlaod.intel.com/research/silicon/Gordon_Moore_ISSCC_021003.pdf [U]
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N. Nowlin, J. Bailey, B. Turfler and D. Alexander, “A Total-Dose Hardening-ByDesign Approach for High-Speed Mixed-Signal CMOS Integrated Circuits,” Intl. Jour. High Speed Elec. Sys., in press [U]
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T.R. Oldham and J.M. McGarrity,” IEEE Trans. Nuc. Sci., vol. NS-30, pp. 4377, 1983 [U]
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J.V. Osborn, D.C. Mayer, R.C. Lacoe, S.C. Moss, S.D. LaLumondiere and G. Yabiku, “Total Ionizing Dose and Single Event Latchup Characteristics of Three Commercial CMOS Processes,” Proc. 6th NASA Symp. on VLSI Design, pp. 1-7, Albuquerque, NM, 1997 [U]
[Osbo-98A] J.V. Osborn, R.C. Lacoe, D.C. Mayer and G. Yabiku, “Total Dose Hardness of Three Commercial CMOS Microelectronic Foundries,” IEEE Trans. Nuc. Sci., vol. 45, no. 3, pp. 1458-1463, Jun. 2000 [U] [Osbo-98B] J.V. Osborn, D.C. Mayer, R.C. Lacoe, S.C. Moss, and S.D. LaLumondiere, “Single Event Latchup Characteristics of Three Commercial CMOS Processes,” Proc. 7th NASA Symp. on VLSI Design, pp. 4.2.1-4.2.14, Albuquerque, NM, 1998 [U] [Pete-83]*
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A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza, and F. Rotondo “A Low-Power 10bit ADC in a 0.25-µm CMOS: Design Considerations and Test Results,” IEEE Trans. Nuc. Sci. vol. 48, no. 4, pp. 1225-1228, Aug. 2001 [U]
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L.R. Rockett, Jr., “Simulated SEU Hardened Scaled CMOS SRAM Cell Design Using Gated Resistors,” IEEE. Trans. Nuc. Sci. vol. 39, no. 5, pp. 1532-1541, Dec. 1992 [U]
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N.S. Saks, C.M. Dozier, and D.B. Brown, “Time Dependence of Interface Trap Formation in MOSFETs Following Pulsed Irradiation,” IEEE Trans. Nuc. Sci. vol. 35, no. 6, pp. 1168-1177, Dec. 1988 [U]
[Scha-97]
R.R. Schaller, “Moore’s Law: Past, Present and Future,” IEEE Spectrum, pp. 52-59, Jun. 1997 [U]
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J.R. Schwank, “Total Dose Effects in MOS Devices,” 2002 IEEE Nuclear and Radiation Effects Conference Short Course, Phoenix, AZ, Jul. 2002 [U]
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F.W. Sexton and J.R. Schwank, “Correlation of Radiation Effects in Transistors and Integrated Circuits,” IEEE Trans. Nuc. Sci. vol. 32, no. 6, pp. 3975-3981, Dec 1985 [U]
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W.P. Snapp, “Mixed-Signal RHBD Strategies at Boeing,” Pres. 2002 DARPA HBD Workshop, Washington DC, Feb. 2003 [U]
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W. Snoeys, G. Anelli, M. Campbell, E. Cantatore, F. Faccio, E.H.M. Heijne, P. Jarron, K.C. Kloukinas, A. Marchioro, P. Moreira, T. Toifl, and K. Wyllie, “Integrated Circuits for Particle Physics Experiments,” IEEE J. Sol. State Circs. vol. 35, no. 12, pp. 2018-2030, Dec. 2000 [U]
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W. Snoeys, T.A. Paclacios Gutierrez, and G. Anelli, “A New NMOS Layout Structure for Radiation Tolerance,” IEEE Trans. Nuc. Sci. vol. 49, no. 4, pp. 18291833, Aug. 2002 [U]
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[Thom-99] S. Thompson, 1999 IEDM Tutorial [U] [Thom-02] S. Thompson, N. Anand, M. Armstrong et. Al. , “A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low k ILD, and 1 µm2 SRAM Cell,” Pres. Intl. Elec. Dev. Mat., San Fransisco, California, Dec. 2002 [U] and ftp://downlaod.intel.com/research/silicon/Thompson_IEDM_1202.pdf [U] [Tsiv-87]
Y.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1987 [U]
[Wino-77]
P.S. Winokur, H.E. Boesch, Jr., J.M. McGarrity, and F.B. McLean, “Field- and Time-Dependent Radiation Effects at the Si/SiO2 Interface of Hardened MOS Capacitors,” IEEE Trans. Nuc. Sci. vol. 24, no. 6, pp. 2113-2118, Dec. 1977 [U]
II-142
2003 IEEE NSREC Short Course
Section III
RADIATION RESPONSE AND RELIABILITY OF OXIDES USED IN ADVANCED PROCESSES Alessandro Paccagnella University of Padova
RADIATION RESPONSE AND RELIABILITY OF OXIDES USED IN ADVANCED PROCESSES
Alessandro Paccagnella and Andrea Cester DEI, Università di Padova, Padova, Italy
1. Introduction ____________________________________________________________ 3 2. CMOS Scaling Issues_____________________________________________________ 5 2.1. Introduction ______________________________________________________________ 5 2.2. The scaling down of CMOS technology ________________________________________ 5 2.3. Generalized Scaling: High performance and Low Power__________________________ 6 2.4. Scaling sub-micron CMOS: the Optimum Scaling _______________________________ 8 2.5. Scaling and Reliability issues for deep sub-micro microelectronics: will CMOS go on? 11 2.6. Perspectives for the next ten years. ___________________________________________ 15
3. Oxide Degradation Mechanisms ___________________________________________ 18 3.1. Defect generation inside the oxide: a general background ________________________ 18 3.1.1. Process-related defects in SiO2____________________________________________________18 3.1.2. Conduction mechanisms across thin SiO2 films _______________________________________19 3.1.3. Hot carriers induced degradation in ultra-thin oxides ___________________________________20 3.1.4. Hydrogen-related defects ________________________________________________________22 3.1.5. Anode impact ionization _________________________________________________________24
3.2. Hot-electron-induced leakage currents in ultra-thin oxides _______________________ 26 3.3. Stress Induced Leakage Current_____________________________________________ 27 3.3.1. Contributions to SILC___________________________________________________________27 3.3.2. SILC growth with stress level_____________________________________________________28 3.3.3. SILC origins __________________________________________________________________31
3.4. Soft Breakdown___________________________________________________________ 32 3.4.1. Soft Breakdown current noise_____________________________________________________32 3.4.2. Soft Breakdown conduction mechanisms ____________________________________________33
3.5. Leakage current implications on MOS reliability _______________________________ 40
4. Radiation damage in thick oxides (>20 nm) __________________________________ 43 4.1. Total dose effects__________________________________________________________ 43 4.2. Single event effects ________________________________________________________ 44
III-1
4.3. Radiation and electrical stresses _____________________________________________ 46
5. Thinning the gate oxide: radiation effects on 10-nm oxides _____________________ 48 5.1. 10 nm oxides (or so) _______________________________________________________ 48 5.2. Total dose effects on 10 nm oxides____________________________________________ 48 5.2.1. Trapped charge distribution ______________________________________________________ 48 5.2.2. Radiation induced leakage current _________________________________________________ 50
5.3. Flash Memories ___________________________________________________________ 52 5.4. Radiation effects on Flash memories__________________________________________ 54 5.5. Single event effects on memory cells __________________________________________ 55 5.6. Threshold Voltage Effects on the Charge Loss _________________________________ 56
6. Ultra-Thin Oxides ______________________________________________________ 59 6.1. Introduction______________________________________________________________ 59 6.2. Radiation Induced Leakage Current _________________________________________ 61 6.2.1. RILC Conduction Mechanism ____________________________________________________ 61 6.2.2. RILC dependence on applied bias during irradiation___________________________________ 64 6.2.3. RILC growth kinetics ___________________________________________________________ 68
6.3. Radiation induced Soft Breakdown___________________________________________ 69 6.3.1. Gate oxide leakage current dependence on ion LET ___________________________________ 70 6.3.2. Quantum Point Contact Modeling _________________________________________________ 73 6.3.3. RSB dependence on applied bias during irradiation ___________________________________ 74 6.3.4. Temperature dependence of RSB__________________________________________________ 75 6.3.5. RSB current noise _____________________________________________________________ 78 6.3.6. Temperature dependence of gate current noise _______________________________________ 80 6.3.7. Future issues for RSB and SEGR in space environments _______________________________ 81
6.4. Radiation Induced Wear-Out _______________________________________________ 83 6.4.1. Experimental evidence of Radiation Induced Wear-Out ________________________________ 85 6.4.2. LET dependence of Radiation Induced Wear-Out _____________________________________ 88
6.5. Radiation Effect on MOSFET _______________________________________________ 90
7. Conclusions ___________________________________________________________ 95 8. References ____________________________________________________________ 97
III-2
1. Introduction Moore’s law is pushing integration of microelectronics components on a single chip dangerously close to their inherent physical limits, especially (but not only) in the case of the gate oxide of MOS devices. In fact, owing to the scaling rules the gate oxide thickness must be decreased at each technology node: oxide films with thickness of few atomic layers and corresponding thickness of 1-2 nm are currently under investigation in many research and development laboratories for the next future insertion in production lines of CMOS integrated circuits. While new methods are exploited to deposit such ultra-thin dielectric layers, in some cases less than 1 nm thick, in a controlled and reproducible way over 300-mm Si wafers, the oxide composition itself is no more the stoichiometric SiO2 but has been significantly modified by adding a nitridation step after the deposition, in order to improve processing characteristics and long term reliability. In this way, the vanishing oxide layer is seemingly loosing the central role held for decades in the field of radiation damage on MOS devices, simply because the main properties of the insulating layer itself, that were strongly affected by exposure to ionizing sources, are just disappearing. In this part of the NSREC2003 Short Courses we investigate on how the reduction of the gate oxide thickness has been accompanied by new types of radiation effects, not observed on thicker oxides and proper of thin and ultra-thin dielectrics. For this reason, this contribution is organized in order to present the characteristics and the modification of the radiation effects as the oxide thickness is reduced, from thick to ultra-thin gates oxides; in detail: • in section 2 we present a review of the main issues concerning integration and scaling of MOS devices over the recent years and corresponding technology nodes. The scaling scenarios with their implication on power consumption, supply voltage and speed are then discussed, leading to the reliability implications and to the so called show-stoppers of microelectronic circuit scaling. Among them, the reduction of the gate oxide thickness to atomic size, which may be circumvented by introducing new dielectric materials with high dielectric constant (high-k dielectrics); • section 3 is devoted to show firstly the conduction characteristics of thin oxides, followed by a discussion on the effects of high field electrical stresses, that are usually adopted to evaluate the long term stability and the reliability characteristics of the gate oxide. The stress induced leakage currents through the oxide are then presented along with corresponding physical models describing the experimental results, in correlation also with the physical mechanisms responsible of the induced damage; • section 4 is a synthetic summary of the main radiation effects observed on thick oxides, including total dose effects and Single Event Gate Rupture; • section 5 presents the effects of radiation damage on gate oxides 10 nm (or so) thick, that are of practical interests for floating gate memories, whose characteristics are rapidly summarized at the section beginning. The response to radiation damage of these oxides is worth to be discussed separately, as they show peculiarities not shared with thicker (section 4) or thinner (section 6) oxides. III-3
•
section 6 is the largest section, presenting different aspects of radiation damage in gate oxides with thickness below 6 nm, i.e., oxides proper of the quarter-micron technology and following more aggressive nodes. We show here experimental evidence, models and physical origins of the Radiation Induced Leakage Current and Radiation induced Soft Breakdown, in correlation also with their equivalents induced by electrical stresses previously discussed in section 3. The recently shown synergetic effects between radiation damage and electrical stresses are subsequently introduced, along with the first data on radiation damage of high-k materials.
III-4
2. CMOS Scaling Issues 2.1. Introduction The first studies on Metal-Oxide-Semiconductor structures date back to 1960 and several years have been spent in research before the first CMOS was introduced in 1968 by integrating both nMOS and pMOS in the same chip, and allowing for a very low power dissipation. Since the 1970’s, silicon Integrated Circuits (IC’s) have penetrated into almost everything with electrical components, thanks also to the chip cost reduction promoted by circuit mass production. If compared to products that have been available previously, equipment, which embeds advanced silicon chips, is faster, more functional, and less expensive. Application of semiconductors widely ranges between personal computer, ATM switches, mobile phones, Global Positioning System (GPS) navigator, engine control, and so forth. Even more remarkable is the trend with which the potential of down-scaling transistor sizes has been exploited to obtain many orders of magnitude of performance/cost improvement. For instance, microprocessors have been evolved from their 4-bit ancestors used for watches and calculators in the early 1970’s to the present day 32-64 bit CPU (with a clock frequency > 1 GHz). Memories have grown from their 1 Kbit pioneers used almost exclusively for massive central computers to 256 (and more) Mbyte Dynamic Random Access Memory (DRAM), widely used in personal computers of today. The evolution of Microelectronics industry in this last 30 years, from the first successful large scale integration (LSI) of microprocessor and memory chips to the present ultra large scale integration (ULSI), has been truly spectacular, and the technology growth is continuously keeping increasing without respite. Day by day new issues are required and new challenges arise.
2.2. The scaling down of CMOS technology The key of the technology growth has been the drive to smaller dimensions using the principle of scaling introduced in 1970’s by Dennard et al. in their classical 1974 paper [Den74]. The guideline for MOSFET scale-down is based on the idea of changing device parameters and operating voltage according to the rules reported in the third column of Table 2-1, to maintain a constant electric field pattern in the device. The basic idea is to reduce the dimensions of the MOS transistor and the interconnecting wires, as Fig. 2.1 shows. In other words, the arrangement on the right (b) is scaled down in size from that one on the left (a) by reducing all dimensions by a factor k. After scaling, the same electric-field patterns in the smaller transistor is achieved by reducing the applied voltage along with all the key dimensions, including the thickness (tox) of the insulating oxide layer between the gate and the silicon substrate. The increase of the impurity doping concentration of the smaller device is needed to preserve the electric field pattern within the silicon substrate. It is worth to remark that in this simple constant-electric-field transformation, the dimensions, the voltage, and doping are all modified by a common factor k. III-5
TABLE 2-1 CONVENTIONAL (CONSTANT ELECTRIC FIELD) AND GENERALIZED SCALING RULES. Transistor parameter Before scaling Constant-Electric-Field Scaling Generalized Scaling Channel Length Leff Leff/k Leff/k Oxide Thickness tox tox/k tox/k Electric Field F F F⋅ε Channel Doping ND ND⋅k ND⋅k⋅ε Operating Voltage VDD VDD/k VDD⋅ε/k
Original device
Scaled device
Vdd
Vdd/k tox /k
n+ source
tox L Substrate doping ND
n+ drain
n+ source
L/k Substrate doping ND·k
(a) Fig. 2.1
n+ drain
(b)
Principle of Constant Electric Field scaling for a nMOS transistor. All dimensions and the supply voltage of the transistor (a) are reduced of a factor k, while the substrate doping ND is increased of the same factor to preserve the electric field pattern within substrate and insulator.
Generally, in the conventional scaling the electric field has been maintained around E=5MV/cm in the oxide, as dictated by the transistor reliability, which is dominated by the TimeDependent Dielectric Breakdown (TDDB) [Dum95, Gro99a], Channel Hot-Carrier injection (CHC) [Gro99a, Kob96, Mae98], or other degradation phenomena. This constant-electric-field scaling gives rise to three important results: 1. the density improves by a factor k2 due to the smaller wiring and device dimensions; 2. the speed which is related to the transconductance/capacitance ratio (gm/C), improves by a factor k because the capacitance C of shorter wires and smaller devices is reduced by k while the transconductance gm of the devices scaled in both length and width remains about the same; 3. the power dissipation is reduced by a factor k2 because of the reduced voltage and current in each device, with the important result that the power density (i. e., the power for unitary area) is constant. Thus the increased number of circuits in a given chip area can be accommodated with no increase in the total power dissipation.
2.3. Generalized Scaling: High performance and Low Power III-6
Although the original concept of constant-electric-field scaling is useful and valid, the idea of reducing voltage in proportion to reduced dimensions has not been much popular, mainly for two reasons: a) reluctance to depart from standardized voltage levels. Indeed in many application (mainly portable system) standard level voltage is available and power supply can not be arbitrarily chosen; b) b) by scaling down the threshold voltage of the devices along with the applied voltage, the standby leakage current increases, due to the subthreshold current. This limits how far it is practical to scale the power supply voltage [Den74]. Hence, it is useful to broaden the concept of scaling to the more generalized form shown in the last column of Table 2-1, where the electric field patterns within a scaled device are still preserved, but the intensity of the electric field can be changed everywhere within the device by a factor ε [Bac84]. Thus the applied voltage, which is given by ε/k, can be scaled less rapidly by allowing ε to be larger than 1. As for the conventional scaling, the electric field patterns within the device are maintained by increasing the doping concentration by a factor ε⋅k. The generalized scaling, however, has two main practical limits. On one hand, increased electric field (ε>1) is limited by long-term reliability issues, such as device degradation resulting from hot carrier injection mechanisms or gate insulator failure (oxide Breakdown). Such effects can be partially reduced by adopting some design rules, such as Lightly Doped Drain (LDD) [Asa97, Ogu80]. On the other hand, a practical upper limit for ε is due to the carrier velocity saturation [Sze81]. Ideally, the current in a scaled device increases by a factor ε2 and the transconductance gm as well as the speed (gm/C) by ε. This is true only up to the point where the carrier velocity in the channel saturates, thus limiting the increase of the drain current. Over a critical value of ε, gm is practically constant and then, even increasing the supply voltage, the gate delay does not improve appreciably. In addition to the velocity saturation, also the increased series resistance of graded junctions needed for hot carrier reliability at the higher voltage levels (LDD) further contributes to limit the current increase. In the future evolution of CMOS technology the scaling of the supply voltage will become a crucial issue. In the information industry two different scenarios for CMOS technology and devices are taking shape [Dav95]: on one side, there is the explosion in demand for portable and wireless systems with very low power budgets; on the other, the ability (and the necessity) to produce complex high performance systems on a single chip. Both of these will permit an unprecedented degree of freedom in choosing the supply voltages for IC’s, mainly depending on the requirements of massive information processing capability. In the high performance scenario the supply voltage at each channel length is optimized for maximum speed while maintaining adequate long-term device reliability. Other factors, which must be taken into account in this optimization, are: • the lithography tolerance at the gate level, which can approach 10-20%, having a severe impact in device reproducibility and correct working in sub-micron technologies; • the threshold voltage, which must be high enough for acceptable leakage off-current at minimum channel length. On the contrary, from a performance point of view we need to decrease the threshold voltage in order to increase speed, but, at the same time, we must have a good threshold voltage control at the processing level in order to maintain the dispersion below acceptable values;
III-7
•
the gate insulator thickness, which becomes an important issue for such technologies, in order to avoid too large leakage current, as well as, unacceptable degradation phenomena of the dielectric, which add up to the hot carrier degradation at the drain discussed above.
In a low power scenario the power supply voltage is reduced as compared to the high performance case at the same channel length. The goal is to lower the power dissipation per device and therefore maintain a power density close to that featured by the previous 1µm CMOS technology, by adhering as close as possible to the CE scaling. At the same time the speed should not degrade too much with respect to the high performance case. Also in this case the threshold voltage must be carefully chosen for a good trade off between subthreshold leakage current and speed.
2.4. Scaling sub-micron CMOS: the Optimum Scaling As discussed in the previous section, the scaling in the sub-micron range has been characterized by a non-proportional reduction of gate voltage and oxide thickness. Fig. 2.2 shows how oxide thickness has been reduced as a function of the gate length: data taken from various publications have been plotted (see [Dav95] and references therein). The original constant electric field scaling principle has been rigorously maintained, until a gate length of 0.35µm was reached. However, it is apparent in Fig. 2.2 that scaling below 0.35µm has started to take a new trend, where the oxide thickness is scaled less then proportionally with respect to channel length. In fact, leakage current contributions trough the gate oxide become more and more important as the oxide thickness is scaled down, approaching the direct tunneling limits at 3-3.5 nm. Therefore, oxide reliability has to be re-examined in a presence of a finite tunneling current. An initial reliability projection was reported by C. Hu [Hu94] who characterized oxide and transistor reliability versus direct tunneling stress, concluding that oxide thickness could be reduced as far down to 2nm for transistors in logic circuits and 3nm for DRAM capacitors where tunneling current itself is a new path of leakage current. In the optimum scaling more conservative decision is generally made regarding the choice of oxide thickness, while transistor parameters, such as the threshold voltage, have to be more carefully optimized in order to achieve better circuit performance. In other words, if oxide thickness does not scale easily (due to the constraints on the leakage current), one way to compensate for circuit performance loss is to reduce VDD while bringing Vth/VDD as small as possible. This trend is clearly seen in Fig. 2.3, which is another summary of published data taken from [Dav95] and references cited therein. Even though this scaling method permits to maintain the circuit performance, determined by the load-driving capability, the gate insulator can be subjected to high electric fields which hamper the long-term reliability and endurance of devices and circuits. In addition, in considering the optimum scaling with low threshold voltage, the problem of significant subthreshold current has to be taken into account. The transistor off-current gives rise to a stand-by power consumption:
Pstand −by = VDD ⋅ I OFF regardless of whether the circuit is performing useful switching operations or only idling. The subthreshold stand-by power adds to the dynamic CMOS power consumption, and can become comparable to dynamic power . III-8
na lS ca lin g
100
nt io
60 40
Co nv e
Gate Oxide Thickness [nm]
As miniaturization of CMOS devices progresses without reducing the power supply voltage as proposed by the constant electric field scaling, the electric field increases substantially. The trade-off between speed and power dissipation determines how aggressively the supply voltage should be scaled down, while the reliability constraints set an upper limit on the useful power supply voltage. The effect of channel hot carriers, as well as the high electric fields across the oxide, limits the selection of an optimum power supply voltage.
20 10 6
O
12V 5V 3-3.3V
ling Sca m u ptim
2.5V 1.8-2V
4
1.5V
2 0.05 0.1 0.2 0.4 0.6 1
2
4
Gate Length [µm]
Co nv en tio na lS ca lin g
Gate oxide thickness and channel length of transistors reported in [Dav95] and works referenced therein. Leakage current limits the oxide thickness scaling.
1.0 0.6 cali ng
0.4 imu mS
0.2
Opt
Threshold Voltage Vth [V]
Fig. 2.2
0.1 0.5
Fig. 2.3
1
2 4 6 10 Drain Voltage VDD [V]
20
Threshold voltage and supply voltage of transistors reported in [Dav95] and references cited therein. In an optimum scaling view, Vth is reduced faster than VDD, to improve performance.
If we look at the evolution of the oxide electrical fields over the past 30 years, as is shown in Fig. 2.4 [Gro99b], we see a huge increase from below 1 MV/cm in the early seventies up to 6 III-9
Oxide Field [MV/cm]
MV/cm today (almost one order of magnitude!). As a result of this, the Time-Dependent Dielectric Breakdown of ultra thin oxides has become an important reliability issue for ULSI integrated circuits. Moreover, the thermal dissipation and circuit overheating can become a nonnegligible problem for both reliability and performance. Indeed, the ever increasing transistor density in Giga-scale technologies, the power density and the operating temperature of the circuits are gradually increasing, and temperature values above 100°C are expected in future circuits. Consequently, for an accurate reliability prediction, the influence of the temperature on the time to breakdown for gate oxides needs to be taken into account. A prediction of the maximum operating voltage for a range of operating temperature and oxide thickness relevant for the current and upcoming technology generations was made by Groeseneken et al. [Gro99b]. The data taken by [Gro99b] are shown in Fig. 2.5. The dashed line in the same figure represents the requirements as given by the Semiconductors Industry Association (SIA) roadmap [SIA97]. They found that, depending on the operating temperature (100 – 150°C), oxides below ~2.5-2.8nm will not be able to reliably sustain the operating voltage for their full expected lifetime. Noticeably, for room temperature operation those result are almost in line with the prediction made by Stathis et al. [Sta98]. It should be noted that, after taking the effect of elevated operating temperature into account (which was not considered in [Sta98]), the predicted lower oxide thickness limit based on reliability considerations increases considerably, showing that reliability may already be a potential showstopper for oxide scaling at 130nm generation. Despite of the considerations on power consumption and temperature, discussed above, even more optimistic predictions have been reported in literature, and the debate is far from being over. For instance, SiO2 operating in the direct tunneling current regime has been demonstrated to be usable down to a thickness of 1.4nm without affecting device reliability [Iwa98]. Nowadays, it appears that reliability predictions can not be issued on a general basis, but must be aimed to specific circuit applications or even by considering the MOSFET role in a given circuit. 7
6 5 4 3 2 1 0 1970
Fig. 2.4
1980
1990 year
2000
2010
Evolution of the oxide electrical field during the last 30 years as reported in [Gro99b]. A large increase (almost one order of magnitude) occurred since 1970’s.
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4 R.T.
VG,max [V]
3 2
100°C 150°C
130nm 100nm
180nm
1 0 Fig. 2.5
1.5
2.0
2.5
3.0 3.5 tox [nm]
4.0
4.5
The predicted minimum supply voltage for devices operating at room temperature, 100°C and 150°C, as reported in [Gro99b]. The dashed line and points represent the SIA roadmap [SIA97].
2.5. Scaling and Reliability issues for deep sub-micro microelectronics: will CMOS go on? In the previous sections different scaling approaches have been shortly illustrated. Also, it has been highlighted that low voltage, low power and high performance operations are the great challenges for engineering sub-0.1µm gate length devices. At this point several questions arise: Which is the limit of CMOS technology? Which are the main showstoppers for CMOS scaling? Will CMOS be able to respond to the increasing demand for lowering supply voltage? In this section the technology-reliability trade-off will be discussed. Furthermore, the limits and perspectives of CMOS and, why not, non-CMOS will be shortly summarized to give an idea of how long and how far the actual CMOS era may still go. Since low power dissipation will be strongly required by the market, stand-by leakage and also active power dissipation are the main constraints that will be traded off with device performance without relaxing reliability. Microelectronics has been living in the regime of a nearly constant field scaling since lower than 5V-supply voltage has been introduced. However, for sub-0.10µm devices, the trend is changing and new issues are inevitable. Here are the main issues:
•
Direct Tunneling through SiO2 occurs when the gate oxide thickness is 3 nm or less (See Fig. 2.6). This will increase the contribution of the leakage component in power consumption. Gate dielectric engineering will certainly have a great strategic impact on the integration of terabit class devices as much as lithography. SiO2 dielectrics could be practically used down to thickness of 1.4nm corresponding to a leakage current of 1 A/cm2, without device performance and reliability degradation [Iwa98]. However, a decrease in performance has been reported if the gate oxide thickness is lower than 1.3 III-11
nm [Tim98], suggesting a surface roughness limited mobility process, due to the proximity of sub-oxide. Still, the strong band bending due to quantum mechanical corrections affects the lower limit of supply voltage in the constant field scaling approach [Tak98].
•
Threshold voltage. The minimum value of Vth should not enhance the off-leakage current, that is one of the main problems for power consumption. The non-full scalability of threshold voltage can have severe implications also in scaling the voltage supply, as in some cases the threshold voltage alone can dictate the lower limit for operating voltage scaling.
•
Statistical doping fluctuations. Recently, special attention has been paid to this subject because the number of doping impurities in the channel of a MOSFET tends to decrease with scaling. Hence, random doping placement in the volume of the MOSFET channel by ion implantation can no longer be neglected. The doping atoms fluctuation become very severe for geometry lower than 50 nm, by considering that a few tens of impurity atoms will be present in the channel of a minimum size (W=Lmin) transistor [ITRS99]. Moreover the discrete nature of the doping distribution can also result in strong deviations of the local oxide field from the average value, possibly with severe implications on the gate oxide reliability.
100 1.2 nm 10-2
1.5 nm 1.8 nm 2.1 nm
Jg [A/cm2]
10-4 10-6
3.5 nm
10-8 5.2 nm
10-10 10-12
Fig. 2.6
4.0 nm
2.8 nm
0
1
2 Vg [V]
3
4
5
Gate leakage current density across the gate oxide for different oxide thickness.
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6
•
Alternative gate oxide materials: high-k dielectrics. By now, MOSFET performance has been improved by thinning the gate dielectrics, i.e., silicon dioxide, and also for the near future this seems the only reliable way to continue such improvement. However, in the sub-2 nm thickness regime, it becomes necessary to carefully re-examine the reliability of the gate oxide. The majority of the literature gives a very optimistic picture of silicon dioxide reliability, at least for the near future. However, it is inevitable that the scaling limit of silicon dioxide will be reached due to leakage current, boron penetration, plasma damage, or other manufacturing difficulties, not to say the simple fact that the subatomic scaling of the oxide thickness is simply not possible. Many studies have been proposed about insulators candidate for SiO2 replacement in recent years, taking advantage also of the previous experience on DRAM capacitors. For SiO2 replacement the selected material(s) must fulfill two main requirements: o dielectric constant higher than SiO2; o for the same equivalent thickness tox of SiO2, the leakage current must be lower. Table 2-2 shows a list of several metal oxide and nitride systems, comparing values for the dielectric constant (k), Energy gap (Eg), and offset between the Silicon and insulator conduction band energy (∆EC). For these high-k materials Eg will be one of the limiting factor for SiO2 replacement, since k and Eg are inversely related. In particular, both Ta2O5 and TiO2 have small Eg values and correspondingly small ∆EC values, which will permit the onset of high leakage currents. A trade off between a high k values and low leakage is just necessary. Moreover, many issues concerning material integration in the IC production process flow are still open. Even though several good results have been obtained, the search for the SiO2 replacement material(s) is still open, and may well give rise to different solutions depending on the circuit application.
TABLE 2-2 DIELECTRIC CONSTANT AND BAND GAP OF SOME ALTERNATIVE INSULATORS Band Gap Energy offset Material Dielectric Crystal Structure (Eg) (eV) between Si and Constant (ε) oxide conduction band (∆EC) (eV) SiO2 3.9 8.9 3.2 Amorphous Si3N4 7 5.1 2 Amorphous Al2O3 9 8.7 Amorphous Y2O2 15 5.6 Cubic CeO2 26 5.5 Cubic Ta2O5 26 4.5 1-1.5 Orthorhombic La2O3 30 4.0 Hexagonal, Cubic TiO2 80 3.5 1.2 Tetragonal. HfO2 25-40 5.7 Monoclinic, Tetrag., Cubic ZrO2 25 7.8 Monoclinic, Tetrag., Cubic
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a) Silicon oxynitrides and oxide/nitride stack Oxynitrides and oxide/nitride stacks provide a slightly higher k value (they are therefore physically thicker) and have reduced leakage, improved resistance to boron diffusion, and better reliability characteristics. Recent works have shown that depositing SiN directly on the Si channel results in poor pMOS performance, with significant degradation of channel mobility and driving current capability. This degradation is attributed to the excess charge of pentavalent nitrogen atoms, which cause increased carrier scattering, as well as to defect levels in the SiN layer which reside near the Si valence band. In contrast, improved electrical properties have been obtained by using various oxynitrides. Despite several encouraging results, in pure oxynitrides the dielectric constant k is pretty low (around 7), thus scaling will be limited to tox = 1.3 – 1.5 nm. Below this range, the effects of gate leakage current, reliability degradation or electron channel mobility reduction will most likely prevent further improvement in device performance.
b) Tantalum oxide Ta2O5 with k = 26 has been extensively investigated, but its chances are limited by the need for a silicon dioxide interface layer between silicon and the high-k dielectric. Luan et al. [Lua99] have reported a 0.9nm equivalent oxide thickness achieved by using an NH3-based interface layer. The stability of this structure after high-temperature annealing remains a concern. Statistical reliability data are not present yet.
c) Hafnium and Zirconium based oxides Zirconium and Hafnium containing materials provide a relatively high permittivity without sacrificing the conduction band offset between the dielectric and silicon. Both HfO2 and ZrO2 have high dielectric constants and are thermally stable on Si, and therefore are potentially good high-k gate dielectrics. Lee et al. [Lee99] have produced an equivalent oxide thickness of 0.9 nm with a HfO2 structure. These structures exhibit low leakage (0.1A/cm2 at Vg=+1V). However both ZrO2 and HfO2 tend to crystallize at low temperature, leading to polycrystalline films, with the potential for high-leakage paths along grain boundaries and non-uniformity in k values and film thickness, These materials also act as O ion conductors which may lead to leakage and reliability concerns. Alternatively, use of silicate dielectrics from the outset may be more prudent. Zirconium and Hafnium silicates (ZrSixOy and HfSixOy, respectively) are stable in direct contact with Si, and by incorporating a suitably high level of Si during deposition, the dielectric-Si interface will act more like the target SiO2/Si structure. The k values of ZrSixOy and HfSixOy are substantially lower than those of pure HfO2 and ZrO2, but this trade off for interfacial control will be acceptable as long as the resulting leakage currents are low enough. In all cases, search for adequate gate materials for nMOS and pMOS is open, in particular with regard to their integration in the IC production lines.
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2.6. Perspectives for the next ten years. One of the most challenging target for the future devices and circuits is the System-On-aChip (SOC). This means that more and more functions will be implemented in a single chip, requiring IC’s that can simultaneously satisfy, the constraints imposed by interconnections, operating speed, power consumption, reliability, and the inclusion of complex embedded functions. Digital memory and logic form the major portion of semiconductor device production. Microprocessors and ASIC devices lead the logic category, while memory encompasses DRAM, SRAM, and Non-Volatile Memory (NVM). Process integration optimizes the overall architecture of the full process. This includes the silicon active device as well as the on-chip interconnection hierarchies for power, clock, and signal distribution. The architectural trade offs between the devices and interconnect structures are driven by performance, density, and reliability requirements. The applications for analog, mixed-signal and RF IC’s are projected to remain in personal computing and communications. Analog generally refers to “pure” analog circuits such as operational amplifiers, audio amplifier, signal amplifier, filters, and other circuits operating at both low and high frequency. Mixed-signal includes integrated circuits containing both digital and analog functions, such as analog-to-digital converters. These kinds of applications are generally highly challenging, due to the different requirement of digital and analog circuits. RF refers to pure analog and mixed-signal integrated circuits operating above 800 MHz, such as for wireless communications and “radio on a chip”. In the last years microelectromechanical systems (MEMS) have been included in the list of properties to be implemented in a SOC. This new technology embeds micromechanical structures, made on silicon or polysilicon, and electronic circuits on a single chip. Accelerometers, pressure or temperature measuring sensors are successfully fabricated, by integrating the circuitry for signal processing in the same chip. This permits one to achieve high performance, low power consumption, and reduced sizes at the same time. Reliability is a critical aspect of process integration, interesting digital as well as analog or RF devices. Emerging technology nodes require the introduction of new materials and processes at a rate that exceeds current capabilities for gathering information and generating data and models on new failure mechanisms and defects. Because process integration must be often performed without the benefit of extended learning, it may be difficult to maintain current reliability levels. What will be the new challenges? First of all, atomic level fluctuations and statistical process variations will be a critical issue. For advanced device structures/architectures, statistical process and dimensional variations will be significant barriers to achieving high performance and yield. While the absolute control of processes and alignment is improving, the percentage variation is not allowed to increase. Statistical variation of the doping atoms in the channel region will limit threshold voltage control. The shrinking of gate oxide thickness down to the SiO2 physical limits is another key issue. Highk gate dielectrics will be required to avoid the excessive tunneling currents of scaled SiO2 or oxynitrides. Further, the fundamental limits in the MOS structures are becoming more pronounced due to quantum effects and atomic level effects, causing the increase in performance to be limited. The integration of digital and analog circuits on the same chip will also produce new difficult challenges, such as, managing power, ground, signal, and clock distribution lines on III-15
multilevel interconnect. Cross-talk and increased parasitic delays are becoming limiting factors in scaled interconnect systems. Table 2-3 shows the ITRS prediction for the main technological parameters. The technology requirements reflect the needs of high-performance products. Physical gate lengths and gate dielectrics are all being aggressively scaled to meet these requirements (see column 2 and 6). To support the smaller physical gate lengths and to keep the chip dynamic power dissipation within acceptable limits, power supply voltages are also decreasing (column 3). Thus it will be a significant challenge to maintain constant drive current as the power supply voltage is reduced. As shown in the last column of Table 2-3, the oxide thickness is nearly linearly scaled with the channel length, while the supply voltage, as well as the threshold voltage, is reduced by approximately the square root of L. It is seen that even with the much higher electric field in the shorter devices, the delay improves only about linearly with channel length due to the velocity saturation and series resistance discussed above. In the same Table the projections for DRAM cell size scaling are shown in order to illustrate the increasing integration levels also for this memory. TABLE 2-3 ITRS PREDICTION FOR LOGIC APPLICATION. THE SUPPLY VOLTAGE, THE GATE DELAY, AND THE OXIDE THICKNESS ARE SHOWN FOR BOTH HIGH PERFORMANCE AND LOW POWER SCENARIOS. THE AREA OCCUPANCY FOR A DRAM CELL IS ALSO SHOWN TO ILLUSTRATE THE INTEGRATION LEVEL OF THE FUTURE GENERATIONS. Year of Technology DRAM cell Supply Voltage Gate Delay Oxide 2 Production node (nm) (High (High Thickness Area (µm ) Performance/ Performance/ (nm) Low Power) Low Power) 1999 180 0.26 1.8 / 1.5 11 / 18 1.9-2.5 2000 150 0.20 1.8 / 1.5 9.4 / 16 1.9-2.5 2001 130 0.15 1.5 / 1.2 8.6 / 13 1.5-1.9 2002 115 0.10 1.5 / 1.2 7.3 / 11.2 1.5-1.9 2003 100 0.08 1.2 / 0.9 6.9 / 10.7 1.5-1.9 2004 90 0.059 1.2 / 0.9 6.1 / 8.8 1.2-1.5 2005 80 0.044 1.1 / 0.8 5.7 / 8.2 1.0-1.5 2008 60 0.017 0.9 / 0.6 3.7 / 5.6 0.8-1.2 2011 40 0.008 0.6 / 0.5 2.6 / 4.5 0.6-0.8 2014 30 0.003 0.6 / 0.3 2.4 / 3.7 0.5-0.6 Table 2-4 and Table 2-5 show the ITRS prediction for analog and RF applications, respectively. Even in these cases the main requirement is the increase of Analog as well as RF frequency (see column 3 in both Tables). In parallel the supply voltage is reduced in order to keep the electric field patterns below reasonable values. As a consequence, the off-state leakage current is also increasing (see column 4 in Table 2-4) to meet the drive current and performance targets. With the higher off-state leakage currents, innovative circuit and system design techniques will be required in order to keep the static power dissipation to an acceptable level. The higher leakage current will also present challenges for defect screening.
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Year of Production 1999 2000 2001 2002 2003 2004 2005 2008 2011 2014
Year of Production 1999 2000 2001 2002 2003 2004 2005 2008 2011 2014
TABLE 2-4 ITRS PREDICTIONS FOR ANALOG APPLICATIONS. Analog Supply Analog Frequency Transistor Voltage (V) (GHz) Maximum gate leakage 3.3-2.5 < 0.1 1 pA/cm2 3.3-1.8 0.1-5 1 pA/cm2 3.3-1.8 0.1-5 1 pA/cm2 3.3-1.8 0.1-5 100 pA/cm2 2.5-1.8 0.1-5 100 pA/cm2 2.5-1.8 0.1-5 100 pA/cm2 2.5-1.8 0.1-5 100 pA/cm2 1.8-1.5 0.1-5 10 nA/cm2 1.8-1.5 0.1-10 10 nA/cm2 1.5 0.1-10 10 µA/cm2
Transistor 1/f Noise (V2⋅µ2) 10-11 10-11 10-11 5⋅10-12 5⋅10-12 5⋅10-12 2⋅10-10 -
TABLE 2-5 ITRS PREDICTIONS FOR RF APPLICATIONS. RF Supply RF Frequency Transistor Voltage (V) (GHz) Max. frequency (GHz) 3.3-2.5 0.9-2.5 25 3.3-1.8 0.9-10 28 3.3-1.8 0.9-10 32 3.3-1.8 0.9-10 35 2.5-1.8 0.9-10 40 2.5-1.8 0.9-10 45 2.5-1.8 0.9-10 50 1.8-1.5 0.9-10 60 1.8-1.5 0.9-100 150 1.5 0.9-100 175
Transistor 1/f Noise (V2⋅µ2) 10-11 10-11 10-11 5⋅10-12 5⋅10-12 5⋅10-12 1⋅10-10 -
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3. Oxide Degradation Mechanisms 3.1. Defect generation inside the oxide: a general background 3.1.1. Process-related defects in SiO2 There is no doubt about the long list of extraordinary properties featured by SiO2. First of all, the silicon dioxide is an amorphous insulator which can be grown easily and well controlled on a Si-substrate. It can be thermally grown to a high degree of perfection, reproducibly and stability. It offers a wide energy gap of 9eV [Sze81] and a high energy barriers against both electrons (∼3.2eV) and holes (∼4.5eV). Such values reflect the excellent insulating properties of the SiO2. As discussed in the previous section 2, layers as thin as 1-1.5 nm can be fabricated as gate dielectrics, implementing fully operational MOSFET’s, with gate length down to 50 nm [Iwa98] and less. This clearly highlights the scaling and integration capabilities of silicon dioxide. Nevertheless, some difficulties arise when ultra-thin gate dielectrics are implemented. In fact, even though the oxide growth process is well controlled and good quality oxide can be obtained, some defects are unavoidably present in the oxide bulk and interfaces. In addition, the transition region between the silicon dioxide layer (amorphous) and the silicon substrate (mono-crystalline) is a narrow region of non-stoichiometric SiOx containing a high density of non-saturated bonds, strained bonds, and broken bonds. These defects and imperfections introduce localized energy levels in both silicon and oxide forbidden gap. The defect density strongly depends on the processing condition. In particular the growth temperature and pressure are the most important parameters that thermodynamically influence the quality of the insulator. Also the interaction with the chemical impurities, such as H, B and Cl, introduced during IC fabrication, affects the electrical property of the dielectrics. At first glance the oxide defect can be divided as “intrinsic” and “extrinsic”. A defect is called intrinsic when it is only related to the atoms constituting the lattice structure of the material (SiO2 in the specific case). Otherwise, if other atomic species are involved the defect is named extrinsic. The strained, elongated, or dangling bonds are the most common intrinsic defects [Bal86]. The strained or elongated bond can also be broken easily by an electrical stress or ionizing radiation, thus leading to the formation of a neutral trap. However, this trap disappears as soon as the available broken bond is saturated by species, such as H, O, OH, Cl, F, and so forth. In general the oxide is subjected to a post oxidation thermal annealing in an proper ambient (often rich in N) during the fabrication process itself, in order to reduce the broken bonds and obtain higher quality oxides with a reduced defect concentration, not to say of the final thermal treatment in an H atmosphere. The extrinsic defects are mainly due to the replacement of a Si or O atom with another impurity which can induce a local reorganization of the lattice structure and/or introduce further electron or hole traps [Bal86]. Another important family of extrinsic defects is the hydrogenrelated defects, e. g., Si-H or Si-OH groups. Indeed, a stress could break such bonds releasing a H
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atom or a H+ ion, which can easily move in the SiO2 lattice structure and interact with other dangling bonds. More details about the defects in SiO2 layers, which are far from the aim of this work, can be found in literature [Bal86, DiM78]. As a general conclusion we can assert that the shrinking of oxide thickness is making the quality of the interfacial transition region more and more critical. Indeed, by drastically reducing the gate oxide thickness, the bulk region become smaller and smaller if not vanishing at all, while the size of transition region remain practically unchanged, thus becoming comparable or larger than the bulk oxide.
3.1.2. Conduction mechanisms across thin SiO2 films Even if the SiO2 is a good insulator, in particular cases a small current can flow across the dielectric. Some devices base their functioning in such conduction: this is the case of the Flash Memory, as discussed in section 5. However, in many other cases the current conduction across the oxide is an undesirable phenomenon, which only hampers the device reliability. Several conduction mechanisms across oxide layers have been considered and widely studied in literature: Fowler-Nordheim Tunneling, Direct Tunneling, Poole-Frenkel conduction, Schottky conduction, and inter-trap (hopping) conduction. In the following, only the Fowler-Nordheim (FN) tunneling and direct tunneling (DT) will be shortly described, since they are the most important conduction mechanisms involved in ultrathin gate oxides which are the subject of this contribution. For more details we invite the interested reader to refer to literature [Bri97, Hes86, Len69]. Both FN and DT are conduction mechanisms based on the tunneling transport across the potential barrier associated to the silicon dioxide, as schematically depicted in Fig. 3.1. In the case of FN the electron tunnels from the cathode conduction band into the oxide conduction band through a triangular barrier (see Fig. 3.1a). If the gate current supply is not limited from the interface constraints, i.e., the average time required to tunnel across the potential barrier is much smaller than the time required to supply the electrons to the cathode, the following relation can be used for the tunneling current density [Len69]:
B J = A ⋅ E 2 ⋅ exp − E where E is the oxide electric field, while A and B are constant related to the Si/SiO2 barrier height: q 3 ⋅ mo A= 16π 2 ⋅ η ⋅ mox ⋅ φ
B=
4 ⋅ 2 ⋅ mox ⋅ φ
3
2
3 ⋅ η⋅ q
where mo and mox are the electron effective mass in vacuum and in the SiO2, respectively, φ is the Si/SiO2 barrier height, q the elementary charge, and ħ the reduced Planck’s constant. Such relations have been worked out by using a free-electron gas model for the cathode and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunnel probability. It should be noted that the Fowler-Nordheim current is a function of the oxide field and not of the applied gate voltage. Moreover, since in the tunneling process electrons maintain their
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energy the FN tunneling can occur only if the gate voltage, i. e., the oxide field is high enough. In particular, the following relation must be satisfied: E≥
φ q ⋅ t ox
tox being the oxide thickness. On the contrary, when the oxide electric field is not large enough, the direct tunnel occurs as shown in Fig. 3.1b. The difference between FN and DT conduction is determined by the shape of the potential barrier. In the DT regime the tunnel barrier is trapezoidal and the electron tunnels from the cathode conduction band directly into the anode conduction band. A similar theoretical approach, based on the WKB approximation for the tunnel probability leads to the following relation for the direct tunneling current [Dep95]: J=
B φ 1 2 − (φ − q ⋅ E ⋅ tox )1 2 exp ⋅ − ⋅ 2 φ3 2 E φ − q ⋅ E ⋅ tox 1 − φ A⋅ E2
where A and B are the same coefficient of the FN expression. DT is becoming the most important conduction mechanism in ultra-thin oxides. Indeed, when the oxide thickness is reduced below 3-4 nm a large direct tunneling occurs also when a very small gate voltage is applied (<1V).
3.1.3. Hot carriers induced degradation in ultra-thin oxides In this sub-section some of the challenges related to thin oxide reliability will be discussed. Many aspects of oxide characterization and reliability cannot be discussed in detail. However, many works have been done in literature, which provide many more details on these topics [Blo99, Buc90, Car98, DiM95, Scf94, Yok97]. The most commonly used technique to study the oxide reliability is the accelerated life-test, performed at electric fields (and often at temperatures) much higher than those found during the operating life of the device. Later, the device lifetime under normal operation condition is extrapolated from the results of the accelerated tests by means of proper degradation models. Generally, two main types of electrical stress can be used: Channel Hot Carrier (CHC) stress and Fowler-Nordheim (FN) stress [Car98, DiM95, Gro99a, Kob96] .
Cathode
Cathode SiO2
SiO2
Anode
(a) Fig. 3.1
Anode
(b)
The main conduction mechanisms across the oxide: a) Fowler-Nordheim tunneling; b) Direct Tunneling.
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Both these stresses are based on hot electron injection in the oxide. CHC is the most complex stress procedure and can be performed in MOSFET’s by applying a large drain-source voltage to the device turned on by the gate voltage, in order to produce hot carriers (electrons or holes). Such carriers are injected through the oxide in relation also to the gate voltage, which is used to control the hot carrier current density and the energy of the injected carriers. CHC produces a localized damage in the oxide region close to the drain, i. e., where the carriers are injected. High current densities through the oxide can easily be reached also at relatively low gate voltage. FN stress is generally performed on both MOS capacitors and transistors. In this case the stress is performed by injecting a large current uniformly distributed over all the oxide area. Because the tunnel barrier for electrons is much lower than that for holes, pure electron injection can be easily achieved. The most used methods are the Constant Current Stress (CCS) and the Constant Voltage Stress (CVS). The main advantage of CCS is the possibility of controlling the total charge injected across the oxide. On the contrary CVS is preferred when a direct control of the maximum electron energy in the oxide is needed. Hot-carrier degradation has been widely studied in literature, especially in case of FN stress. A huge amount of experimental data has been acquired over the years and a quite consistent picture can be presented, even if some details remain still unclear. The hot electron dynamics have been schematically depicted in Fig. 3.2. During electrical stress (e. g., FN stress as shown in the same figure), many electrons are injected in the oxide conduction band. Here the injected electrons are subjected to the high oxide field and gain kinetic energy, that is partially lost in scattering events. As the oxide become thinner the electron transport undergoes a transition from steady state to ballistic (or quasi-ballistic) transport. In such way the energy loss of the hot carriers to the phonons in the oxide becomes negligible and electrons can acquire kinetic energies equal to the applied gate voltage. Such high energyelectrons are the main responsible for charge trapping and defect generation. In Fig. 3.2 some among the most important effects of hot carrier stress are shown. In a general scheme, they can be divided in two main families: primary events and secondary events. Once electrons are heated in the oxide by the applied electric field, they produce an oxide degradation localized near the anode-region. Such degradation phenomena are generally referred as primary events, since they are created directly by electrons hitting. Among the primary events the most remarkable are: 1. band-gap impact ionization in the oxide; 2. anode impact ionization and corresponding anode hole generation; 3. hydrogenous species release; 4. electron trap generation in the oxide (by breaking regular or weak bonds in the oxide); 5. electron trapping in pre-existing or stress-generated defect sites. Damage occurs also near the oxide/cathode interface, even if no hot electrons are present there. This is referred as secondary damage and is caused by the mobile species generated at the anode, which drift and/or diffuse through the cathode. Among the secondary events we count: 1. hole trapping; 2. defect generation by electron-hole recombination; 3. defect generation by chemical reaction of released hydrogenous species.
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cathode
SiO2
anode
Hole Trapping
Electron-hole recombination
Electron-hole generation
H H
Secondary effects
Hydrogen Release Anode Hole Injection Primary effects
Fig. 3.2
Fundamental degradation phenomena interesting the gate oxide during an electrical stress.
Even though several processes may exist, two fundamentally different processes are commonly claimed as the main responsible for charge and defect generation in the oxide: one is related to electron impact ionization in the oxide or in the anode [Ala00, Car98, DiM96, Kob99], the other one is related to the release of hydrogenous species from interfaces [Buc90, Car98, DiM95].
3.1.4. Hydrogen-related defects Hydrogen or hydrogen-related species (H, H2, -OH, H2O) are incorporated in the silicon dioxide during various process steps, such as the oxide growth in H2O ambient (steam oxidation). The IC fabrication often introduces hydrogen on purpose in order to passivate the silicon dangling bonds at the interfaces. Hydrogen-related traps are generated when an electron with energy larger than ~2eV (measured with respect to the bottom of the oxide conduction band) releases hydrogen from a defect site located near the oxide-anode interface [Buc90]. The kinetic energy of hitting electron plays a control role in such activation phenomenon. It has been reported indeed a strong correspondence between the defect concentration and the applied electric field, strictly related to electron kinetic energy. Hydrogen is cracked by hot electrons (injected from the cathode) from either absorbed water, Si – OH, or Si – H bonds in the interfacial region (see Fig. 3.2). Once released, the mobile III-22
hydrogen diffuses and/or drifts toward the oxide/cathode interface, where interface states or electron traps may be consequently produced [DiM95]. Clearly the released hydrogen usually leaves behind a defective site. Atomic hydrogen is very mobile also at room temperature and rapidly diffuses, finding precursor defective sites which can be attacked. The most likely precursor are Si – H bonds, silicon dangling bonds (Pb centers), oxygen vacancy (Si – Si bonds), and strained Si – O bonds. Regarding the Pb centers, many works have been carried out and a rather complete picture of their interaction with both atomic and molecular hydrogen has been drawn over the years. The silicon dangling bonds (Si•) can interact with atomic (H) as well as molecular (H2) hydrogen. The dynamics of interface state generation is believed to proceed by the following reactions: O≡Si• + H ⇔ O≡Si H and/or:
(3.1)
O≡Si• + H2 ⇔ O≡Si H + H The direction of these reactions is primarily dependent on the temperature and time, meaning that a dangling bond can be both passivated and depassivated depending on the stress conditions. Hence, the generation rate of these interface states depends on: the density of passivated interface states; the efficiency of a hot electron to break a hydrogen atom from an absorbed H2O, Si – H bond, or Si – OH bond; the background concentration of Si – H, Si – OH, and water. The reactions given by Equation (3.1) give rise to the belief that the passivated or notpassivated Pb centres should be the most important precursors of hydrogen-related defects. On the contrary, Pb centres are not the only defects correlated with the hydrogenous species (for details see [Buc90] and references cited therein). In addition, it was recently shown that atomic hydrogen induces defects in concentration exceeding that of Pb centers and the majority of these generated interface states results from some other interfacial bonding arrangement. This does not preclude the reaction of surface silicon bonds and hydrogen forming interface states, as described by Equation (3.1), but rather that most of the interface states are not identifiable as Pb centers. Blochl and Stathis [Blo99] have recently reported another type of hydrogen-related defect: the hydrogen bridge. It is a complex of a hydrogen atom and an oxygen vacancy (E’ center). In a hydrogen bridge, a hydrogen atom replaces an oxygen atom as shown in Fig. 3.3. In short, the electronic structure of the hydrogen bridge consists of a three-center bond of two Si dangling bonds with the hydrogen s orbital. The completely bonded and non-bonded states lie in the oxide valence and conduction band, respectively. The non-bonding orbital lies in the forbidden oxide energy gap. It can be positively, neutrally or negatively charged depending on the number of electrons captured (none, one, or two, respectively). Since the Si – H – Si bonding orbital is in the valence band, the hydrogen bridge is a very stable structure and can hardly be broken. Temperature has been also shown to affect hydrogen-related defect generation [Sat95]. In particular, by decreasing temperature the generation efficiency exponentially decreases: below 150 – 200°K hydrogen-related trap generation is no longer noticed. This suggests that hydrogenous species drift and/or diffusion is much reduced (if not inhibited) at low temperatures. It was found that the activation energy of the defect generation rate is a constant (approximately 0.1 eV) irrespective of either stressing current density or injected electron fluence. Such III-23
activation energy is close to that of diffusion of hydrogen (0.18 eV for atomic hydrogen, 0.45 eV for hydrogen molecule).
3.1.5. Anode impact ionization Electrons injected from the cathode into the oxide conduction band are accelerated by the oxide electric field. Since electric field is very high in FN regime they will gain kinetic energy from the oxide field and will lose energy by phonon scattering [Fis85]. Noticeably, the maximum energy, an electron can gain is approximately equal to the applied gate voltage in case of ballistic transport, which is not so unlikely in oxide thinner than 5-6 nm. Recent studies have shown that a hot electron entering the anode will rapidly impact ionize in the poly-Si (or Si), producing a hot hole near the interface [DiM96]. According to the anode hole injection model, the energy of an incident tunneling electron is transferred to a deep valence-band electron, thereby exciting it to the lowest available energy state of the anode conduction band [Scf94]. This excitation generates a hot hole. The holes that are generated with enough energy may be injected back in the oxide valence band, mostly over the ~4.5 eV hole barrier. A fraction of the back-injected holes can be trapped near the oxide/cathode interface. Authors [Kob96, Yok97] have reported that some holes may be captured by defect sites and create positive charge centers that can capture electrons. Yokozawa et al. [Yok97] also proposed an atomic scale model for electron trap generation originating from the hole trapped in oxygen vacancy, as shown in Fig. 3.4. Following their interpretation, when an oxygen vacancy captures a hole, its lattice structure becomes unstable, and changes to a larger lattice distorted structure, in order to minimize the total energy of the new configuration. Such structural change enables the oxygen vacancy to capture electrons. After electron-hole recombination the neutralized oxygen vacancy maintains the lattice-distorted structure. This new structure has been demonstrated to feature energy levels in the forbidden oxide energy gap, near the Si band gap. Such levels act as electron traps, capturing and emitting electrons.
Si O H
Fig. 3.3
Schematic drawing of a hydrogen bridge.
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Hole generation could occur, in principle, even by band-gap impact ionization. In fact, once electrons are injected into the oxide they can gain enough energy from the electric field. The high-energy tails that develop on the hot-electron energy distribution could generate holes inside the oxide by band-gap impact ionization, as soon as the electron energy is higher than ~9 eV. Once generated, such holes are no longer distinguishable from those produced by impact ionization at the anode and injected back to the oxide. However, in order to produce band-gap impact ionization, the injected electron must be accelerated for a long distance. For this reason impact ionization can occur only in oxides thicker than tens of nm. In particular, it was shown that band-gap impact ionization can not practically happen in oxides thinner than 20nm. Hence, in ultra-thin oxides, such as those used in contemporary CMOS technologies, band-gap impact ionization is quite unlikely. On the other hand anode impact ionization can easily occur: the smaller energy gap existing between the silicon conduction and valence band (~1.1 eV) makes the impact ionization easier to produce, due to the smaller energy required. Moreover, electrons entering the anode region suddenly gain roughly 3 eV in energy due to the oxide/silicon (or oxide/poly-Si) conduction band offset. Some authors also reported that hole transport through the oxide disappears if the applied gate voltage becomes lower than 7.5 eV. In their opinion, this rules out the anode hole process as cause of defect generation and breakdown in thin oxides at low voltage. Following this interpretation, defects should be produced in ultra-thin oxides by the hydrogen activation process. On the other hand, impact ionization was shown to produce defects in the oxide-anode region in dielectric layers thinner than 6 nm. For instance, Satake et al. [Sat95] proposed that when hot electrons break the weak bonds in SiO2, some local rearrangements could occur to minimize the structural energy at the expense of higher electrostatic energy. Due to the structural rearrangement, the bonding state would not recover to the initial state. As origin of weak bond they proposed strained Si – O – Si bonds and/or oxygen vacancy. However, controversies still exist about the role of holes and hydrogenous species in defect generation and a complete picture of defect generation in ultra-thin oxides is yet to be established.
Si atom O atom
+
+ hole 1) Neutral oxygen vacancy
Fig. 3.4
2) Hole trapping produces a large lattice distortion
electron
+
4) Electron trap generation by e-h recombination
3) Electron trapping leads to a neutral oxygen vacancy with large lattice distorted structure Proposed atomic scale model for generation of traps by hole trapping in oxygen vacancy [Yok97].
III-25
3.2. Hot-electron-induced leakage currents in ultra-thin oxides As discussed in the previous sub-section, hot carriers can produce defects in thin gate dielectrics by means of several mechanisms. We are going to discuss now the effects of trap generation in ultra-thin oxide films, with particular regard to leakage current paths across the insulator. It is well known in literature that an electrical stress can produce different types of leakage current across thin oxides (tox<8 nm), which can be classified into three main groups, as illustrated in Fig. 3.5.
10-6 HB
Jg (A/cm²)
10-7
SB
10-8 10-9
SILC
10-10 10-11
fresh
10-12 0 Fig. 3.5
1
2
3 4 Vg (V)
5
6
7
Evolution of the gate leakage current through a thin oxide during an accelerated electrical stress.
At the stress beginning a gradual and continuous increase of the gate leakage current can be observed during the electrical stress. Such current is referred to as Stress Induced Leakage Current (SILC) [Oli88]. SILC is characterized by an uniform conduction across the whole gate active area, due to neutral trap generation inside the insulating layer. SILC has been the subject of many works in literature and some authors provided a detailed classification of the different current components contributing to SILC. Then, by further stressing the oxide, the gate current can abruptly increase, due to Soft Breakdown (SB) or B-mode SILC [Lee94]. SB is associated to a single or few localized conductive spots in the oxide, rather than to a uniform conduction across the whole gate area as for SILC. Finally, catastrophic oxide breakdown may be reached at high stress levels, and the gate current can approach 1mA or more. Hard Breakdown (HB) represents this last degradation step. In the following SILC and Soft Breakdown, which are the main topics of this contribution, will be discussed in more detail. III-26
3.3. Stress Induced Leakage Current The first observations of leakage current in thin SiO2 layers subjected to high field electrical stresses date back to the work by Maserjian and Zamani [Mas82]. After injection of 1017 - 1018 electrons/cm2, they observed a significant degradation of the oxide insulating properties, leading to enhance the tunneling conduction, with reproducible behavior among different samples. This effect was attributed to the generation of positive states in the region of the oxide near the Si/SiO2 interface. Later, Olivo et al. [Oli88] proposed that this oxide leakage current originates from localized weak spots uniformly distributed in the whole oxide area. The weak spots were related to some defect rich regions produced by the electrical stress in the SiO2 layer. This current is commonly referred to as SILC (Stress Induced Leakage Current). The nature of SILC has been the subject of a large number of studies, which have demonstrated that different contributions add up in SILC. It was clear since the beginning of the last decade that SILC is partially due to a transient contribution, which decays with time [Dum93, Run97, Sco96, DeB98a]. Charge trapping and de-trapping from oxide defects is the physical mechanism, proposed to account for this behavior, and the results were modeled following a tunneling front model, which describes the defect filling with time.
3.3.1. Contributions to SILC Sakakibara et al. [Sak96, Sak97a, Sak97b, Sak97c] considered the different contributions in more detail, and they supplied a detailed classification of the different types of currents merging in SILC. For simplicity, these different contributions could be regrouped in three families: 1. non-reproducible component, mainly deriving from the recombination and/or passivation of the oxide positive trapped charge; 2. transient component, due to charging/discharging processes of oxide traps located close to the oxide interfaces. This transient current is strongly dependent on the order of positive/negative measurements, measurement polarity, and oxide thickness. In particular, it decreases by reducing the oxide thickness; 3. true DC component, very important when the oxide thickness is reduced below 7 - 8 nm. 4. The non-reproducible contribution (1) was observed only once at the first positive Vg sweep after stress and was associated to electron tunneling process into the positively charged site during the positive electric field application (see Fig. 3.6a). Once electrons have tunneled into the positively charged site, the site is neutralized and annihilated. The transient component (2) includes several contributions. Generally such contributions are measurable even after repeated voltage scans and are associated to electron tunneling process into neutral traps (Fig. 3.6b). Such types of components were widely studied by many authors and shown to strongly decrease with oxide thicknesses below 6 nm [Run97]. Among the transient contributions we also count transient currents which are measurable whenever the polarity of applied gate voltages is switched. They were attributed to electron tunneling process into the electron traps with repulsive potential barrier whose energy level is lower than the Fermi level of the silicon substrate [Sak97a]. The defect site is positively or negatively charged only during the first negative or positive voltage sweep, respectively. The oxide charge is maintained as long as a voltage scan with the opposite polarity is not performed. The DC contribution (3), being in principle the easiest to be measured and modeled, has been the subject of several successful modeling efforts. The first observations supported the idea that the electrical stress generated weak spots in the oxide, where the electron conduction was easier than across the undamaged oxide regions. Starting from an empirical approach, where III-27
SILC was still described on the basis of the Fowler-Nordheim tunneling equation with a reduced barrier height [Oli88], more refined models have been proposed. Lately the model, which encountered a general, if not universal, agreement was the trap-assisted tunneling through oxide neutral traps, as Figure3.6c shows [Blo99, Chu97, Ros97, Sak97b, Tak99, Lar01]. It is a common opinion that SILC is due to inelastic trap assisted tunneling across neutral defects generated by the electrical stress and uniformly distributed across the whole oxide area. The tunneling process is accompanied with the trap energy relaxation. A possible atomic scale model, which successfully describes the neutral traps involved in SILC conduction, is that proposed by Blochl and Stathis [Blo99] starting from hydrogen-bridge-related defects. They gave an energyrelaxation value of 1.71 eV, in substantial agreement with those experimentally observed by Takagi et al. [Tak99] and Rosenbaum et al. [Ros97] (roughly 1.5eV). Some aspects of the model are still under debate, such as the origin of the tunneling electrons, which is very likely to be the conduction band of the cathode material. To make even more complex this picture, some authors have demonstrated that the DC component is not stable over time, but tends to gradually decrease with time upon injection of low energy electrons [Cer01d], likely due to local reconstruction of the damaged lattice upon electron capture by the neutral traps. Based on the trap-assisted tunneling conduction mechanism SILC is proportional to the defect concentration and the trap-assisted tunnel probability. With reducing the oxide thickness, the distance between the neutral defects mediating SILC and the oxide interfaces decreases, raising the probability that traps capture and/or emit electrons. On the contrary, the transient component becomes practically undetectable in thin oxides, because of the enhanced emission probability. It was experimentally verified by several authors that the transient as well as the nonreproducible components practically disappear in 6-nm (or thinner) oxides and the DC SILC component controls the stress induced leakage current [Run97].
3.3.2. SILC growth with stress level Also based on the trap-assisted tunneling model, the leakage current linearly depends on the defect concentration inside the oxide. The SILC growth kinetics has been widely studied in literature and many works in the last decade have been devoted to the understanding of leakage current growth and defect generation kinetics. It is quite common opinion that SILC gradually grows until the breakdown event. A novel reliability extrapolation model, which nicely fits the SILC growth kinetics, has been also proposed by Scarpa et al. [Sca97a, Sca97b, Sca00]. They found that the growth kinetics of the excess current Je (defined as the difference between the current measured after and before stress) follows the power law: ∂ ln ( J e ) ν = K e ⋅ N inj ∂N inj
(3.2)
where Ninj is the injected charge. This kinetics law applies to all devices after Constant Current Stress, regardless the oxide thickness and technology, as shown in Fig. 3.7a. The slope of the curves ν ranges between the narrow limits -1.1 and -1.4 over several decades, independently on stress intensity, gate voltage, and measurement polarities. The pre-exponential coefficient Ke weakly depends on the stress current density Jstr by the relation: K e = K ⋅ J str
III-28
−ε
(3.3)
where K only depends on the oxide thickness and technology. From Eqs. (2.2) and (2.3) the following relation were obtained for the excess current: K −ε α J e = J sat ⋅ exp ⋅ J str ⋅ N inj α J sat = C ⋅ J str
(3.4a)
β
(3.4b)
α = 1 −ν
(a)
+
(3.4c)
+
(b) Vg<0
Vg>0
(c)
Energy loss Trap-Assisted Tunnelling
Fig. 3.6
Inelastic Trap-Assisted Tunnelling
Different components contributing to SILC: a) non reproducible component due to annihilating positive trapped charge; b) transient component, due to charging / discharging of interface traps; c) DC component, attributed to an elastic or inelastic trap-assisted tunneling process.
III-29
(a)
(b) Fig. 3.7
a) The SILC growth rate dLn(Je)/dNinj, as a function of injected charge for different oxide thickness and technology (Letters) have been shown (symbols = experimental data, lines = fitting by Equation (3.2)). A=steam grown oxide and N2 post oxidation annealing; B=dry grown oxide; C=steam grown oxide and N2O post oxidation annealing. b) SILC in 4.4-nm oxide as a function of injected charge (symbols = experimental data, lines = fitting by Equation (3.4)).
III-30
The values of parameter (α, ε, β, K, and C) depends on the oxide thickness and technology and have been listed in the above cited works. An example of the excellent matching between model predictions and experimental data is shown in Fig. 3.7b (data taken from [Sca00]). This model predicts SILC to saturate to the maximum current value Jsat, which increases with the stress current density Jstr. This saturating behavior has been also reported by other authors [Rod00]. However, the experimental evidence of breakdown occurrence, even after SILC saturation, excludes that trap generation kinetics features the same saturating behavior, but trap concentration must keep increasing until breakdown occurs in some region of the oxide layer. Despite many efforts, the problem of SILC saturation is still open. Some efforts to correlate SILC growth kinetics and trap generation in bulk oxide and interfaces have been done by De Blauwe and Degraeve [DeB98a, Deg96]. De Blauwe et al. [DeB98a] reported a strong one to one correlation between SILC interface defects (Dit) and bulk oxide traps (Dot): JSILC ~ Dit ~ Dot. indicating that SILC interface states and bulk traps have a common origin. Nevertheless, after thermal annealing at 250°C, they found a substantial reduction of Dit, while SILC as well as Dot were only partially annealed. From there the conclusion that, despite the common origin of SILC and Dit, they are probably not causally related. On the contrary the strong correlation between SILC and Dot still may be a causal one.
3.3.3. SILC origins The origin of the neutral traps mediating SILC is still matter of debate and none among the proposed models has encountered a general agreement. One of the first studies devoted to shed light upon the nature and origin of neutral traps responsible of SILC was proposed by DiMaria and Cartier in 1995 [DiM95]. They concluded that the increase in the leakage current is related to hydrogen-induced defects. They also reported the experimental evidence that exposure of thin oxides to atomic hydrogen from a remote plasma causes leakage currents similar to those observed after high-field stress, supporting the idea that other mechanisms, such as anode hole injection, should be unrealistic in producing SILC. The atomic scale model recently proposed by Blochl and Stathis (discussed above) nicely fits with that supposed by DiMaria. Based on this model, the defect responsible of SILC conduction should be hydrogen bridge, which is originated by hydrogen atom capturing in oxygen vacancy. The electrical properties of this defect satisfy all the requirements to be a good candidate for causing SILC. In particular, its energy level lays near the Fermi level of the contacts (~3eV below the oxide conduction band) and it features a small relaxation of the chargestate level (~1.7eV) after capturing an electron. In fact, a defect can contribute to the leakage current only if its charge-state energy level shifts upon relaxation by less than the applied voltage. A completely different approach is followed by some other authors, which identify the anode hole injection (AHI) as responsible of defect generation (see for instance [Ala00] and ref. cited therein). Holes have been claimed as possible precursors of defects causing SILC even by other authors [Deg96, Shi99], who studied the polarity dependence of trap generation rate and charge to breakdown in nitrided oxides. They found that nitridation significantly affects the oxide degradation process as well as the stress polarity dependence. Nitridation was demonstrated to cause a large decrease of bulk oxide traps during gate injection, while trap creation is less affected by the nitridation during substrate injection. The asymmetrical distribution of incorporated nitrogen in the oxide was proposed as responsible for the different hole generation, transport, and trapping in the nitrided and not-nitrided oxide regions. Even in this case the atomic III-31
scale model proposed by Yokozawa et al. [Yok97] and previously described can well explain the trap creation starting from hole trapping in oxygen vacancy. A third model, including both holes and hydrogenous species has been recently proposed by Chen et al. [Chn98]. They assumed that for both positive and negative stress polarity holes are generated and injected into the oxide. Such holes can be trapped or react with the Si – H bonds in the silicon dioxide layer, producing hydrogen release, according to one of the following reactions: Si – H + h+ ⇒ Si• + H+ Si – H + h+ ⇒ Si+ + H The first process will lead to the release of positive hydrogen ions, while the second one will release a neutral hydrogen atom. The mobile hydrogen can then drift and/or diffuse through the interface where it can break a Si – H bond and create interface trap, according to one of the following reactions: Si – H + H+ + e- ⇒ Si• + H2 Si – H + H ⇒ Si• + H2 At this point it is clear that different mechanisms are good candidates to produce the defects involved in SILC. We can not exclude that both hydrogen release and anode hole injection (and maybe some other mechanisms still unknown) may be simultaneously involved in trap generation.
3.4. Soft Breakdown First reports on Soft Breakdown (SB) were presented by Okada et al. [Oka94] and Lee et al. [Lee94], who initially referred to this new leakage current as B-mode-SILC and QuasiBreakdown, respectively. SB may occur when the oxide thickness is reduced below 4-5 nm. While SILC is characterized by a gradual increase of the leakage current with increasing stress level (as discussed above), SB features an abrupt increase of the gate current [Bru00, Hal97, Mir00, Tom99, Wei97]. SB is associated with a single or few localized spots in the oxide, rather than a uniform conduction across all the active area, as SILC does [Oli88]. The onset of SB may be explained by means of the percolation theory [Deg95] as for the final HB. The relation between SB, HB, and device lifetime is still an open question. Some authors [Sun00a] assert that Soft and Hard Breakdown are not so different phenomena, and the same basic conduction mechanism is involved in both cases. Bruyere et al. [Bru00], reported that the Soft and Hard Breakdown generally take place in different positions across the oxide area, confirming this idea. One of the main difference between these two degradation modes is the intensity of the current flowing across the damaged region of the oxide, corresponding in turn to the area of the weak spot.
3.4.1. Soft Breakdown current noise A peculiar feature of SB is that the gate current is characterized by large discrete fluctuations, on the contrary of HB, whose noise seems to be a 1/f noise [Ale98], and no discrete III-32
fluctuations appear. The noise in the SB current has been the subject of several works [Bri96, Mir98a, Tom99]. The presence of noise in SB current has been reported for the first time by Briere et al. [Bri96], who observed a Random Telegraph Noise (RTN) in the gate current after SB. Based on the noise characteristics Tomita et al. [Tom99] also distinguished two types of SB, named “digital” and “analog” SB. A clear RTN pattern is often observed after digital-mode SB, while analog-mode SB features a random noise. These two SB modes were attributed to a different lateral propagation of damage. In the case of analog-mode SB the spot is damaged by Joule heating during transient current, and the different charge transport as well as noise characteristics have been attributed to the existence of high trap density in the oxide as a result of the SiO2 melting. Lately, the RTN has been statistically modeled following the detrended fluctuation analysis [Ban01].
3.4.2. Soft Breakdown conduction mechanisms Several conduction models have been proposed in the last years to explain the currentvoltage characteristics after SB. Different conduction mechanisms have been proposed by various research groups, such as percolation, hopping, and tunneling. Despite the numerous efforts and published works devoted to SB modeling, no clear consensus have been found yet about electron transport in the SB regime. In the following the most remarkable model will be shortly reviewed • Direct tunneling mechanism [Lee94] • Variable Range Hopping (VRH) mechanism [Oka97] • Percolation mechanism [Hou98a, Hou98b] • Quantum Point Contact (QPC) model [Cer01b, Mir98b, Sun00b]
a) Direct tunneling The direct tunneling model was introduced by Lee et al. [Lee94]. In accordance to this model, SB takes place in thin oxides when the applied voltage is low and then the traveling distance of electrons in the oxide conduction band would be shorter than the mean free path. Under this condition electrons ballistically reach the anode and thereby release most of their energy at the oxide/cathode interface. Such degradation mechanism is schematically depicted in Fig. 3.8a. A Physically Damaged Region (PDR) is generated in form of broken bonds by the continuous accumulation of the energy at the anode. The PDR develops locally where the defect concentration has reached a critical value. Since the PDR is neither an ideal conductor nor insulator, it can be modeled as a resistance with finite resistivity ρ in series with a trapezoidal barrier with reduced thickness (see Fig. 3.8b). From this assumption the voltage drop over the oxide can be written as: VOX = VR ,OX + J PDR ⋅ ρ ⋅ (t OX − t R ,OX ) where tR,OX and VR,OX are the thickness and the voltage drop of the undamaged oxide region, respectively. JPDR is the current density flowing across the PDR. The reduced thickness tR,OX has been estimated around 2.2 nm for a 4-nm gate oxide. Based on this model the gate current fluctuations should be produced by electron trapping/detrapping processes in the PDR. Yoshida et al. [Yos96] also proposed a similar III-33
trapezoidal barrier, but in this second case the series resistor was eliminated. The current fluctuations were attributed to variations of the PDR thickness. Other authors have presented similar conduction models: all these models share the common idea that SB is caused by a localized damaged region and electron tunneling takes place across an energy barrier with reduced thickness. APDR
VOX
Poly-Si gate Physically damaged region
tR,OX tOX
Si-substrate JFN
(a) Fig. 3.8
VR,OX
JPDR
(b)
a) schematic drawing for electron transport during FN stress in ultra-thin oxides, producing a Physically Damaged Region in the oxide at the anodic interface; b) current paths after SB in ultra-thin oxides, according to the direct tunnel model.
b) Variable range hopping The Variable Range Hopping (VRH) conduction mechanism was introduced by Okada and Taniguchi in 1997 [Oka97]. Based on this model, the conduction is mediated by the localized states (bulk oxide and interface traps) generated by the electrical stress. Conduction occurs by electron hopping between localized states whose energy levels lay near the Fermi level as shown in Fig. 3.9. The hopping probability between two neighboring states increases with both temperature and oxide trap concentration. From the VHR model the gate current dependence on the applied voltage is given by: q ⋅V I (V ) ∝ sinh k ⋅T V being the voltage and kT/q the equivalent thermal voltage, while the gate current dependence on temperature should be: I (T ) = A ⋅ exp(− B ⋅ T −1/ 4 ) where A and B are constants related to the concentration of oxide states available for conduction. Based on the VRH model the variations between the SB characteristics measured in different samples derive from variations in electron trap concentration and distribution. On the contrary, the RTN current fluctuations should be due to charge trapping and detrapping in the localized states, which dynamically modify the number of states available for the conduction. III-34
Ef
Energy [A.U]
Fig. 3.9
Hopping between localized states whose energy levels lay near the Fermi level Ef following the Variable Range Hopping model.
c) Percolation model A model based on the percolation theory of non-linear conductor networks has been proposed by Houssa et al [Hou98a]. According to this model, which shares some aspects with VRH, a percolation path is generated between the gate and substrate as soon as a critical value of trap concentration has been reached in some place of the oxide layer, as illustrated in Fig. 3.10. It is assumed here that conduction between two neighboring traps becomes possible when the intertrap distance is less then 0.9 nm [Deg95]. The authors also assumed that the current between two neighboring traps, marked with A end B in Fig. 3.10, is proportional to the square of voltage vAB applied between the two sites: i = σ AB ⋅ v AB
2
(3.5)
σAB being the bound conductivity. Gate
A
Percolation path
i =σABvAB B
Electron traps
SiO2
Substrate Fig. 3.10 Schematic drawing of the percolation path formed between electron traps generated inside the oxide by an electrical stress.
It was demonstrated that in finite size disordered systems, if the current behaves as described by Equation (3.5), the current-voltage characteristics of the whole percolation system should behave like: V = ρ eff ⋅ I α
III-35
where ρeff is the effective resistivity of the percolation path across the SiO2 layer and α = 0.37±0.04. The same authors demonstrated also that the effective resistivity ρeff of the ultra-thin gate oxide after the SB behaves like a power law of the density of traps D generated during a constant current stress [Hou98b]:
ρ eff ∝ (D − Dc )−τ with τ=0.48±0.01 and Dc is the critical trap density at SB.
a) Hard Breakdown traps
SiO2 z
SiO2 z
do
Si
Poly-Si EF
E0
do
Poly-Si
E0
Si
EF
EF
Energy [eV]
Energy [eV]
b) Soft Breakdown
z
z
Fig. 3.11 Hard (a) and Soft (b) breakdown constrictions and the corresponding potential profile of the electronbarrier along the Hard (Soft) breakdown path in the QPC model.
d) Quantum point contact The most recent model to explain the SB conduction was successfully proposed by Suñe and Miranda [Mir98b, Sun00b] and is based on the theory of quantum wires. The Quantum Point Contact (QPC) picture has been initially introduced by the same authors to model the HB conduction. Later, such model has been extended to SB. In general, they proposed that any breakdown events (Hard or Soft) opens a conductive path through the oxide, which behaves as a point contact between gate and substrate, as illustrated in Fig. 3.11. In this picture, no oxide barrier remains between oxide and electrodes in the local position where the breakdown occurred. In this approach the breakdown spot can be figured as a narrow wire connecting the two electrodes. Since the length of the narrow channel is in the nanometer range, the electron transport is likely ballistic, and the conductive path behaves like a Sharvin Point Contact. If also the lateral dimension (d0 in Fig. 3.11) is small enough to be comparable to the electron wavelength, the momentum in the direction perpendicular to propagation is quantized and only a finite number of transverse modes are allowed. In this case the narrow conductive path behaves like a QPC. If the path is narrow enough (as in the case of SB), the ground sub-band energy E0 is III-36
above the Fermi level at the cathode, and the conduction can only take place by tunneling across an effective one-dimensional potential barrier (see the diagram at the bottom of Fig. 3.11). An analytical solution has been elaborated starting from the following hypothesis, with referring to Fig. 3.12: • the gate voltage drops at the gate (Vpoly), the substrate (Vsub), and in a very thin region across each interface, as schematically shown in Fig. 3.12 for positive and negative polarity; • a fraction β⋅Vox of the applied oxide voltage Vox drops at the oxide-cathode interface, while the remaining portion (1-β)⋅Vox drops at the oxide-anode interface; • an adiabatic approach to the electron transport is assumed; • the potential barrier has parabolic shape. The gate current can be written as: E + β ⋅q⋅V
ox 2⋅q F ( I (Vox ) = T E ) ⋅ [ f (E − β ⋅ q ⋅ Vox ) − f (E + (1 − β ) ⋅ q ⋅ Vox )]⋅ dE h EF −(1−∫β )⋅q⋅Vox
(3.6)
where q is the elementary charge, h the Plank constant, and f(E) the Fermi-Dirac distribution: f (E ) =
1 q ⋅ (E − E F ) 1 + exp k ⋅T
being EF the Fermi level at cathode. Starting from the parabolic approximation of the barrier profile a closed expression has been found for the total transmission probability T(E) for an electron of energy E: N −1
T (E ) = ∑ [1 + exp(− α ⋅ (E − E n ))]
−1
(3.7)
n =0
N being the number of sub-bands (each of them corresponding to an energy sub-band), En the energy sub-band, and α a geometrical factor related to the shape of the SB spot. In this picture of quantum confinement, more than one energy sub-band may exists and Equation (3.7) takes into account all contributions. If only one sub-band exists or the contribution of all the other subbands are negligible with respect with the ground energy one, Equation (3.7) can be simplified as: T (E) ≅
1
1 + exp[− α ⋅ (E − E0 )]
≅ exp[α ⋅ (E − E0 )]
(3.8)
From Eqs. (3.6) and (3.8) the following exponential law has been calculated for the SB current.
[
]
I (Vg ) = A ⋅ exp B ⋅ (Vg − V0 )
where A, B and V0 are: III-37
A=
4⋅q ⋅ exp(− α ⋅ φ ) α ⋅h
B =α ⋅q⋅β V0 = V poly + Vsub
α and φ being parameters related to the potential barrier. In particular φ is the barrier height (measured as shown in Figure3.12) and α depends from the geometrical barrier shape. In case of parabolic approximation α and φ are related to the barrier thickness tb as: tb =
η⋅α
⋅
π
2 ⋅φ m *z
(3.9)
mz* being the electron effective mass along the propagation z axis. The authors also showed that although tb depends on both α and φ the barrier thickness is linearly correlated with α and uncorrelated to φ. This means that a certain degree of statistical correlation must exist between α and φ. Such correlation is given by Eq. (3.9). Moreover, based on this experimental evidence, they concluded that the best description of the SB conductive spot would be given in terms of φ and tb instead of α and φ. Poly-Si
oxide
Poly-Si
sub
oxide
sub
Vpoly
Vsub φ
βVox Vg
φ tb
(1-β)Vox Vsub
(1-β)Vox
βVox tb
Vg
Vpoly
Vg<0
Vg>0
Fig. 3.12 Schematic representation of the potential profile and voltage drops across the SB path in the QPC model.
Recently, a new approach based on QPC has been presented at IEDM 2001 [Cer01a], to describe the electrical characteristics of Soft Breakdown in electrically stressed MOS capacitors. The entire analytical calculation is not shown here for sake of brevity and can be found in [Cer01a]. By using the new analytical model it is possible to extrapolate the barrier profile of the SB spot from experimental Ig-Vg curves, without any hypothesis on the barrier shape. The SB spot is characterized by two numerical parameters, i. e. the barrier thickness tb and the barrier height Φb. Both have been analyzed as the function of the SB current through the spot after electrical stresses for a variety of oxide thickness and gate area values. The most important results are summarized in Fig. 3.13. Two different regions appear in this figure: 1. Type-A: corresponding to low gate current SB (Ig<1nA at Vg = 1.5V), and 2. Type-B: corresponding to high gate current SB (Ig>1nA at Vg =1.5V)
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Type-A region: φb is almost constant while tb varies from 2 to 0.8 nm. Type-B region: it encompasses tb values smaller than 0.8 nm and decreasing to 0.6 nm while φb abruptly descends from 3.2 eV to 2.4 eV. These data permit to evaluate the characteristics of the SB spot during an electrical stress: when the SB current is small we are dealing with a small area spot and its barrier height is saturated at 3.2 eV. Correspondingly Ig is controlled only by tb. For high leakage currents tb decreases below 0.8 nm and Ig is now controlled by φb, which corresponds to a larger spot area. If just a single SB spots is produced during an electrical stress and becomes progressively more leaky. Fig. 3.13 also depicts its evolution as it moves from type-A to type-B as the stress proceeds and the spot size becomes larger.
3.2
1
Type-A
2
φb [eV]
3
1 Ig↑
2.8
2 2.6 2.4
3 Type-B
0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 tb [nm]
2
Fig. 3.13 Correlation between the barrier height (φB) and barrier thickness tb. The solid arrow indicates the direction corresponding to increasing SB current. The two regions corresponding to Type-A and Type-B SB are also marked.
By means of the same approach it has been also investigated the dependence of tb and φb on temperature (Fig. 3.14). Devices with relatively high currents have been selected, lying borderline between type-A and type-B oxides, in order to stress any temperature effect on both barrier height and width. tb clearly decreases by increasing the temperature, while φb only slightly oscillates between 3 and 3.2 eV. This result indicates that only the weak spot shape (see inset of Fig. 3.14) is temperature dependent while the spot area is only slightly affected by temperature variations, at least for the device type measured. Some micro-structural changes or some temperature-related variations in energetic distribution of traps can explain such behavior.
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3
3.2
1.3
3.0 1.1
2.8
tb [nm]
Poly-Si
Si Low T.
0.9
2.6 2.4
Barrier height [eV]
High T.
Sample 1 2.2 0.7
Sample 2 80
120
160
200
240
280
2.0 320
Temperature [K] Fig. 3.14 Temperature dependence of barrier height (φB) and thickness tb for two different samples. Inset: Temperature effect on the SB spot shape.
3.5. Leakage current implications on MOS reliability SILC as well as SB represent one of the challenges for the reliability of the oxides thinner than 6 - 7 nm. Charge trapping, which has been recognized as the main wear out phenomenon in oxide thicker than 8-10 nm, is no longer appreciable in thinner oxides. In fact, the thinning of the insulator layer makes charge trapping unlikely, due to the enhanced tunneling probability. For instance, positive trapped charge in thin oxides can be easily and rapidly recombined by electrons from gate or substrate. As discussed above, different types of leakage current may be observed in stressed oxides, mainly depending on the oxide thickness. Even SILC reveals itself with different contributions [Run97, Sak96] each of them is dependent on oxide thickness. Actually this nonzero gate current hampers the long-term reliability of non-volatile memories, and it may also affect dynamic logic and analog components [DeB98b]. As soon as the oxide thickness is reduced below 3-4 nm SILC becomes less and less impacting on the total gate current, due to the large tunneling current of a fresh device, which becomes larger due to the reduction of the oxide barrier thickness. Fig. 3.15a clearly shows this trend: in 4-nm and 5.2-nm oxides after 1018 electrons/cm2 electrical stresses a large increase of leakage current is measured (roughly 1 order of magnitude with respect to the fresh device). On the contrary, in the 2.8-nm oxide only a modest increase in leakage current appears, which is still dominated by the fresh direct tunneling current. In very thin oxides the defect generation probability decreases mainly due to the small energy of injected electrons across the oxide [Sta98]. Fig. 3.15b compares the gate current measured before stress and after SB in very thin oxides. SB appears with a large increase in the leakage current regardless the oxide thickness. In ultrathin oxides SB may have important implications on MOS reliability. Some authors found that after the onset of SB a threshold voltage shift occurs, which can be intolerable for the device III-40
correct operations [Pom00]. Moreover, SB may occur long before the final HB of the oxide, further reducing the device lifetime [Sun00a, Wei97]. However, the real effect of SB on the MOSFET performance is still under debate. For sure the appearance of a large RTN noise on the gate is a great challenge for the performance of integrated circuits in case of analog applications. Digital applications appear less sensitive to such degradation mode, and some authors assert that even after the Soft or Hard Breakdown a device can correctly work [Wei97]. On the other side the formation of a weak spot where a large current flows (100nA-1µA) can drastically enhance the power consumption. 10-6
10-5 2.8 nm
4 nm
10-8
10-7
10-9
10-8
5.2 nm
10-9 SILC Fresh
10-10 10-11
2.8 nm
10-7
0
1
2
3 4 Vg [V]
5
6
4 nm
Ig [A]
Jg [A/cm2]
10-6
10-10
5.2 nm
10-11 SB Fresh
10-12 10-13
(a)
0
1
2
3 4 Vg [V]
5
6
(b)
Fig. 3.15 a) Gate current measure before and after constant current electrical stresses (Jstr=10mA/cm2, Ninj=1018e/cm2) for three oxide thickness (2.8, 4, and 5.2 nm). The stressed curves correspond to SILC before SB; b) gate current measured before and after SB for the same three oxide thickness of Fig. (a).
Recent results have demonstrated that the main factor determining the sensitivity of MOSFET to SB events is represented by the device dimensions [Cer03a]. Given the small area of the SB spot (10-14-10-13 cm2 [Cru98]), it is clear that SB occurrence on MOSFET’s with large area does not hamper the device performance. On the contrary, SB can produce a strong decrease of the drain current and transconductance in MOSFETs with small W (see Fig. 3.16). This effect is due to the formation of a localized oxide damaged region likely trapping negative charge over a large portion of the channel width, around the SB conductive path. The SB impact on the transistor drain current increases as the stress proceeds and the SB current increases, as the damaged oxide region becomes wider due to thermal dissipation and defect generation. The oxide defects producing the drain current collapse are distributed over a relatively large area (with diameter estimated around 0.1-0.2µm [Cer03a]), much wider than the area of the SB conductive path evaluated from the QPC model. This effect is evident in devices with small W and fades as W increases, as shown in Fig. 3.17. In the last part of this work we also show that the drain current decrease can be observed even after the incidence of a single ion with high LET without any increase of the gate current. This indicates that the drain current decrease must be attributed to a damaged region at the interface, which may span a large portion of the gate width, effectively hampering the channel formation. From the viewpoint of reliability: extrapolations, while evaluating the device lifetime from stresses on MOS capacitors is widely accepted and well justified in case of oxide lifetime evaluation and large W transistors, it may be questionable in MOSFETs with small W. In these III-41
components failure may occur well before the onset of Hard Breakdown due to the effect reported in that [Cer03a] work, suggesting new problems and methodologies for assessing the lifetime expectation of this device type. The 90-nm technology node is quickly approaching for the CMOS devices, and the SB impact on the electrical characteristics of minimum size devices is expected to play a possibly dramatic role.
gm [x10-6 Ω-1]
25
Vds=0.1V
Fresh, 1
20
2
Ids [µA]
30
15 10
3
5 0
0
0.5 1.0 Vgs [V]
4
1.5
35 30 25 20 15 10 5 0
fresh 1
3
Vgs=0.9V 4 0
0.5 1.0 Vds [V]
(a) 1 =Ig<1pA
2
1.5
(b)
2 =Ig≅50pA
3 =Ig≅1nA
Before (SB)
4 =Ig≅50nA
After (SB)
Fig. 3.16 gm -Vgs and Ids-Vds characteristics taken on a nMOSFET before and after SB (W=1µm, L=0.1µm, tox = 2nm)
Idsat(stressed)/Idsat(fresh)
1.2
W/L=10/0.1 µm
1.0 0.8 0.6
W/L=1/0.1 µm
0.4 0.2 W/L=0.35/0.1 µm
0.0 10-12
10-11 10-10 10-9 10-8 Gate Current at Vg=1V [A]
10-7
Fig. 3.17 Correlation between the gm variation and the gate current at Vg=1V; gm, and the gate current are measured at several steps during the electrical stress.
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4. Radiation damage in thick oxides (>20 nm) 4.1. Total dose effects This short sections aims only to summarize the main radiation induced effects due to total dose in MOS devices with thick gate oxides. For these devices the interested reader may find comprehensive treatments of the complex physical phenomena proper of the radiation-matter interaction and their impact on the MOSFET electrical characteristics in widely known reference books, such as those authored by Ma and Dressendorfer [Ma89], Holmes-Siedle and Adams [Hol02], and more recently Oldham [Old00]. Further, NSREC2002 Short Courses have offered an excellent review on this subject presented by J. Schwank..
Id [A]
100 krad(Si)
Fig. 3.1
10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10
Annealing After 106 s
0
1
2 3 Vg [V]
Fresh
4
5
Drain current-Gate voltage characteristics of a power MOSFETwith 70 nm gate oxide in the subthreshold region before irradiation, after 100 krad(SiO2) under a positive gate bias and 106 s after the irradiation.
The main total dose phenomena on thick MOS gate oxides (20 nm and more) are effectively summarized in Fig. 3.1, showing the subthreshold characteristics of a power MOSFET with 70nm gate oxide irradiated with gamma rays from a Co60 source. The Compton electrons generated by the impinging gamma photons generate electron-hole pairs in the gate oxide. The applied gate bias produces an oxide field in the dielectric layer pushing electrons and holes towards opposite directions, effectively decreasing the recombination efficiency immediately after the pair III-43
generation. Owing to the large mobility difference, electrons are rapidly swept out the gate oxide to the gate terminal, while holes slowly move to the Si/SiO2 interface, where they can be effectively trapped for long times, producing the leftward shift of the drain current reported in Fig. 3.1. In parallel, oxide defects are produced at the same interface giving rise to the reduction of the subthreshold slope observed after irradiation. Interface defects affect also the low frequency noise characteristics of MOSFET’s due to carrier trapping/detrapping from interfacial defects, that on one side reduce the carrier channel density and, on the other, reduce the carrier mobility due to the enhanced Coulomb scattering from charged traps. As time elapses, trapped holes can be neutralized by electrons tunneling from the silicon substrate, so that the drain current slowly moves to the pre-irradiation position without recovering the pre-irradiation slope. Incidentally, in thick oxides the worst-case irradiation condition is under a positive oxide field, which at the same time reduces the recombination of the radiation induced electrons and holes, and enhances the hole accumulation at the channel interface, thus producing the largest variation of the threshold voltage. This description has been successfully applied to evaluate the impact of ionizing radiation on the MOS characteristics, for gate oxide thickness ranging from several hundred nm’s down to 20 nm and less. The same physical description of the interaction between ionizing radiation and matter is well explored for this oxide thickness range. From this basis we’ll start to investigate in the next sections how total dose effects affect MOS devices with gate oxide around 10 nm or less.
4.2. Single event effects Another part of the NSREC2003 Short Course, authored by T. Oldham, is dedicated to explore this issue, so in this contribution we summarize only the main results relative to single event effects in gate oxides, in connection with the physical characteristics of the insulator. In this framework the most important effect is represented by the Single Event Gate Rupture (SEGR), corresponding to the breakdown of the gate oxide produced by a single ion under adequate bias conditions. This effect, reported for the first time in 1987 [Wro87], is due to the current circulating across the oxide layer along the track of an impinging ion, that may locally produce a catastrophic irreversible damage of the insulating characteristics of the silicon dioxide, i.e., the oxide breakdown. The risk of incurring in a catastrophic SEGR grows with the applied oxide field and with the LET (Linear Energy Transfer) coefficient, i.e., the number of generated electron-hole pairs, of the impinging ion. Such effect has been (and still is) a severe concern for power MOS devices, where high electric fields could appear across the oxide. Among different interpretations and models, we may indicate the recent physics-based model proposed by Boruta et al. [Bor01], which correlates the SEGR to the generation of a large electrical field as a byproduct of the positive charges immobilized in the oxide. This field adds to the external applied field to promote the oxide breakdown. The same authors underline the validity of their model to thick oxides, as in 18 nm or thinner oxides border effects, Fowler-Nordheim injection, trapping dynamics and impact ionization may introduce substantial deviations from the behavior predicted by their model, not to say about technological differences between oxides with different thickness. While this model and several other experimental observations refer to thick oxides characteristics of power devices, few authors investigated the occurrence of SEGR in oxides thinner than 10-20 nm, proper of the contemporary CMOS technologies [Joh98a,Sex97,Sex98]. SEGR experiments in thin oxides may lead to detect some characteristics that cannot be found in thick oxides, such as the occurrence of a radiation induced Soft Breakdown instead of a III-44
catastrophic Hard Breakdown, which was actually observed by the authors previously quoted. However, we are considering here how SEGR scales with the oxide thickness, leaving to the following section 6 the exploration of issues more relevant and peculiar of thin dielectrics. The experimental procedure was based on irradiating MOS capacitors with a given ion fluence at an applied gate voltage, step-increasing this voltage and repeating the irradiation until the oxide breakdown was achieved, as illustrated in Fig. 3.2 [Sex98]. The voltage corresponding to the last irradiation step was the critical voltage for SEGR for a specific ion LET. For instance, with reference to Fig. 3.2 this critical voltage is 3.7 V. Noticeably, some minor increase of the gate leakage can be observed even at lower voltages, but these currents are clearly not proper of a breakdown event as expected in a 7-nm oxide.
Fig. 3.2
I-V curves for a 7-nm SiO2 capacitor after exposure to successive fluences of 360-MeV Au ions at increasing increments of gate voltage. Fluence per step was 106 ions/cm2 and bias during exposure is indicated.
The dependence of the SEGR critical oxide field ECR (corresponding to the critical voltage) on the oxide thickness is illustrated in Fig. 3.3, from 18 nm to 4.5 nm [Joh98b]. Experimental data suggest a gradual increase of the critical field when the oxide thickness and/or the ion LET is reduced, even though some data dispersion between different device lots is observed, possibly due to the different oxide technologies. Based on the results presented in the previous section 3, we may notice that a substantial Fowler-Nordheim injection accompanied the experiments performed at the highest fields. This suggests that in space applications the occurrence of SEGR on ultra-thin oxides is hampered by the maximum oxide field, limited in turn by electrical reliability constraints.
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12 4.5 nm 10
ECR (MV/cm)
8
7.5 nm
6.5 nm 6.0 nm 12 nm 18 nm
6 JPL capacitor results (different process)
4 2 0 20
Solid symbols are from Sexton, et al., Trans. Nucl. Sci., 1997 Open symbols are new results from JPL
30
40
50
60
70
80
90
100
LET (MeV-cm2/mg Fig. 3.3
Dependence of SEGR critical field on LET coefficient for oxides with different thickness.
All authors involved in SEGR studies observed that pre-damaging by irradiation the MOS capacitors to be submitted to SEGR tests had no effects on the SEGR critical field. In fact, an ion impinging on the oxide may leave a track of residual oxide defects, but they play no role in generating a breakdown path induced by another ion hitting the oxide at a later time, as long as the breakdown conduction does not involve also those defects produced by the first ion, a fact that is quite unlikely given the small size of the oxide conductive region.
4.3. Radiation and electrical stresses Synergetic effects between radiation damage and electrical stresses have not attracted a great attention from the researchers until recent times. In fact, a few studies have clearly demonstrated that thick oxides typically irradiated with low Linear Energy Transfer (LET) radiation (γ-rays, electrons, X-rays) showed no radiation effect on such parameters as the oxide breakdown field or the Time-to-Breakdown, as deduced from accelerated electrical stresses at high fields, even for radiation doses of several Mrad’s [And95, Bro93, Bro95, Fle00, Kim95, Pac96, Sca97c]. Even though irradiation leaves a high density of neutral defects and/or dipole charge, no change of the oxide dielectric quality appears after high radiation doses. In fact, low LET radiation (used for those experiments) generates point defects such as broken bonds and H+-species, that are not effective in promoting the oxide breakdown, which instead takes advantage of clusters of defects spatially linked to the breakdown conduction path. The same results hold true by decreasing the oxide thickness down to 7 nm, where the total dose effects may directly affect the oxide insulating characteristics by enhancing the low-field leakage current. This increased current should not be confused with oxide breakdown, as illustrated in the next sections 5 and 6.
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On the other hand, the radiation induced positive charge accumulation in the gate oxides may strongly affect the Fowler-Nordheim injection characteristics, as the oxide barrier width is reduced. However, the oxide tunnel conduction characteristics are not important in most of the MOSFET applications, at least for devices where the gate oxide can be considered as a perfect insulator. Further, FN injection has no direct connection with the basic MOSFET parameters, such as threshold voltage, transconductance, saturation current, and drain off-current. For this reason, and despite the large amount of data on MOS devices, few results are present in literature on the radiation induced modifications of the oxide conduction properties different from breakdown. Radiation induced oxide positive charge may also affect the first stages of accelerated electrical stresses by increasing the current injected at a constant voltage, or decreasing the gate bias needed to inject a given current. However, no trace of these effects is found, possibly because the amount of charge injected by an electrical stress overcomes, by orders of magnitude, the charge injected during a gamma/X-ray radiation stress, hence canceling the radiation induced effects by the much larger injected charge and damage produced by the electrical stress [Fle00, Sca97c]. Further, injected charge may anneal some of the radiation induced damage, due to the electron capture at positive charge centers. As a significant numeric example, we notice that an electrical stress level of 1 C/cm2, that can often be tolerated by an oxide without breakdown, corresponds to 6.1018 injected electrons/cm2, while the large 10 Mrad(SiO2) dose produces less than 1015 electron-hole pairs/cm2 in a 10-nm oxide.
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5. Thinning the gate oxide: radiation effects on 10-nm oxides 5.1. 10 nm oxides (or so) Two orders of reasons have driven us to introducing a specific section about radiation effects on 10 nm gate oxides. On one side stay the motivations deriving from the fact that 10-nm oxides are the tunnel oxide of Flash and EEPROM memories. These devices are widespread as solidstate memories for a variety of applications, even though their use in space applications is suffering from the radiation sensitivity of the control circuits to single event effects and total dose. On the other side lies the need for introducing an intermediate step between thick oxides, i.e., a well explored land from the viewpoint of radiation effects with a massive experimental background and scientifically solid explanations deriving from two decades (at least) of radiation studies, and thin and ultra-thin oxides. In this field relevant radiation studies date from half decade or so, and for innovative materials and technologies experiments are performed as soon as new devices become available to the scientific investigation. Radiation effects on 10-nm oxides reveal continuities with the behavior of thicker oxides, but also introduce new signatures peculiar of the thinner dielectrics, such as a measurable leakage current.
5.2. Total dose effects on 10 nm oxides Some peculiar aspects of the radiation damage in 10-nm oxides, including also reports on 8nm oxides, will be presented now, showing remarkable differences with respect to the results found in thicker oxides, in particular concerning the effect of the applied gate bias on the positive trapped charge distribution and the onset of DC leakage currents.
5.2.1. Trapped charge distribution The effective trapped charge has been measured in 10-nm gate oxides after irradiation with 8 MeV electrons or heavy ions [Can01a]. The midgap gate voltage shift (∆Vmg) of C-Vg measurement is correlated to the charge density ∆Qox trapped in the oxide at position Xox (i.e., the charge centroid) measured from the gate [Ma89] by: ∆Vmg=-∆Qox·Xox/(ε0·kox)=-∆Qeff·tox/(ε0·kox ) (1) where ε0 and kox are the vacuum and the oxide relative dielectric constants, respectively. ∆Qeff is the effective trapped charge, i.e., the charge trapped at the SiO2/Si interface causing the same ∆Vmg of the charge ∆Qox in Xox. The radiation induced effective positive charge ∆Qeff_p, determined by ∆Vmg measurements is shown in Fig. 5.1 for devices irradiated with 257 MeV I ions (LET=61.6 MeVcm2/mg). ∆Qeff_p increases with the dose and the experimental data can be fitted by the relation ∆Qeff_p = A⋅ln(D)+B. Parameters A and |B| depend on the irradiation bias conditions, being maximum under negative applied gate bias, Vbn, and minimum under zero gate bias, Vb0, respectively. III-48
∆Qeff_p (1011 holes/cm2)
12
Fig. 5.1
11
11
11
11
Vbn: ∆Qeff_p = 3.43·10 ·Ln(D)-5.42·10
10
11
11
Vbp: ∆Qeff_p = 2.61·10 ·Ln(D)-3.94·10
8 6
Vb0: ∆Qeff_p = 2.06·10 ·Ln(D)-1.88·10
4 2 0
0
20
60 40 80 Dose (Mrad(Si))
100
ositive effective trapped charge after I ion irradiation for devices biased at Vbp=3 V (open squares), Vb0=0 V (dashed circles), and Vbn=-4.5 V (closed triangles). The solid lines are fittings of the experimental data by ∆Qeff_p=A⋅ln(D)+B; the values of the A and B parameters are also reported.
∆Qeff_p is higher for the negative gate bias for all radiation doses. This effect is peculiar of thin oxides (tox≤10 nm) and significantly different from results usually found in thicker oxides, where the worst case condition (i.e., maximum oxide charge) occurs under positive gate bias. In fact, radiation generated holes are trapped close to the cathode during irradiation, so that their centroid is expected to be closer to the SiO2/Si and gate/SiO2 interface for the positive and negative gate bias, respectively. Consequently from eq.(1) ∆Vmg should be expected to be higher for Vbp than for Vbn, but the opposite is experimentally observed. In fact, trapped holes are removed by thermal detrapping and by electron tunneling [Old00] after irradiation. Hole removal at the SiO2/Si interface by electron tunneling from the Si substrate is enhanced under positive gate bias and |∆Vmg| is lower [Ben85, Boe86, Old86, Wal91] accordingly with data in Fig. 5.2. This effect was observed also in 8-nm oxides irradiated by 8 MeV electrons [Can98]. Similar ∆Qeff_p values are found for the Vb0 and Vbp bias. Actually, the oxide electric field has the same direction for both bias values, but it is lower for Vb0 being Eox0≈0.4 MV/cm. Hence, the positive trapped charge can be reduced by the high initial recombination of the radiation induced electron-hole pairs under the low field condition, that is, under Vb0. The radiation induced positive charge may be easily recombined by Fowler-Nordheim (FN) electron injection in the oxide. The time evolution of the gate voltage for the FN constant current Ig=100 nA is shown in Fig. 5.2 for devices biased at Vbp during irradiation. The first measured value (after 1 s) for irradiated samples is lower than in the as received MOS, due to the positive trapped charge (Qp) which reduces the potential barrier for electron injection and increases the electron tunneling probability [Can99a, Can99b, Sca98]. As expected, the initial Vg value decreases by increasing the radiation dose due to the Qp increase. In the fresh device Vg continuously decreases as a function of time, owing to positive charge accumulation in the oxide. On the contrary, in irradiated devices Vg increases as the electron injection proceeds, becoming even larger than in the fresh sample, due to Qp recombination and electron trapping in radiation induced neutral electron traps [Ait76, Wal90].
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Vg (V)
9.4 9.3 9.2 9.1 9.0 8.9 8.8 8.7
As received
100 Mrad(Si) 50 Mrad(Si) 20 Mrad(Si)
1
10
100
1000
Time (s) Fig. 5.2
Time dependence of the gate voltage during FN electron injection from the substrate (Ig=100 nA) before (as received) and after I ion irradiation for devices biased at Vbp=3 V during irradiation.
10-6 I ions Si ions
|Ig| (V)
10-7 10-8 10-9 10-10 10-11 10-12 3 Fig. 5.3
4
5
6 7 8 |Vg| (V)
9
10
Negative Ig-Vg curve for devices biased at Vbn=-4.5 V after irradiation at 20 Mrad(Si) with Iodine (close circles) or Silicon (open circles) ions. The solid line is the current before irradiation.
5.2.2. Radiation induced leakage current After irradiation with heavy ions the gate current may increase, as illustrated in Fig. 5.3. Before irradiation the FN injection is established at |Vg|>7 V. After irradiation with I ions an excess leakage current appears between 5 V and 9 V, before and inside the FN regime. No current enhancement is observed after irradiation with Si ions. The excess current, measured in both negative and positive gate voltage sweeps, has been attributed to multi-trap assisted tunneling (M-TAT), as electrons should tunnel across the oxide through two or more traps. While SILC, and RILC as shown in the next section, may be modeled by inelastic single-trap assisted tunneling (S-TAT) [Lar99], in 10-nm oxides the tunneling probability to/from a trap 5 nm far from the interfaces is so low, that S-TAT could not support III-50
any DC current. Noticeably, DC SILC similar to that of Fig. 5.3 has never been observed in 10nm devices after electrical stresses, being smaller than 1 pA/cm2 [DeS00]. This means that a critical trap density is needed for M-TAT, which can only be produced by ions with high LET, as low LET Si ions (see Fig. 5.3) and gamma rays are unable to produce the excess leakage. Only dense ion tracks can produce locally a high defect density, enabling M-TAT. Moreover, only high ion doses may generate M-TAT in 10-nm oxides: in fact, only for very high oxide defect densities the probability of having some traps aligned along a conductive path is high enough to produce a measurable leakage current. Measuring the time decay of the gate leakage may give further insights in the nature of the radiation induced excess current, as shown in Fig. 5.4. A two-slope curve always appears: |Ig| rapidly decays during the first seconds and then the slope decreases [Can01b]. These results indicate that, during electron injection, the density of tunneling sites decreases due to electron trapping and/or defect annealing. The small difference between curves "A" and "B" suggests that most of the defects unavailable for M-TAT are simply filled with electrons. Once the bias is removed and electrons are re-emitted from the defects, the leakage current rapidly returns to the original value. Assuming the E' center related model proposed by Walters and Reisman for positive and negative charge trapping in SiO2 [Wal90] the dipolar and amphoteric neutral electron/hole trap may be a good candidate to be the defect responsible for this current. Noticeably, the main component of SILC after electrical stresses for tox≥10 nm is a transient current, caused by charging/discharging of stress generated traps near the oxide interfaces [Gla98, Run97]. On the contrary, Fig. 5.4 shows that the radiation induced current is not a displacement current but a true DC current through the radiation induced oxide defects. One may wonder if this current has any relation with the Soft Breakdown current produced by electrical stresses, but only Hard Breakdown has been reported for this oxide thickness. Further, no Random Telegraph Noise proper of SB is measured over time, as illustrated by the Fig. 5.4.
|Ig| (pA)
75 70 65 60 55 50 45 40 0.1 Fig. 5.4
A
Read at Vg=-7V
B
1
10 Time (s)
100
1000
Gate current as a function of time at Vg=-7 V for devices biased at Vbp=3 V after 100 Mrad(Si) I irradiation up to 100 s (measurement A) and 1000 s (measurement B). Measurements A and B were performed on the same device waiting 1 minute between acquisitions.
III-51
|∆Ig| (A)
10-9 10-10
Negative excess current
10-11 10-12
Positive excess current
Vbn Vbp Vb0
10-13
1 Fig. 5.5
10 100 Dose (Mrad(Si))
1000
Positive (triangles) and negative (circles) excess current as a function of the I ion dose for devices biased at Vbp=3 V (open symbols), Vb0=0 V(dashed symbols) and Vbn=-4.5 V (closed symbols). Negative current was measured at Vg=-7 V; positive current at Vg=6.4 V.
The increase of the excess current ∆Ig with the I ions radiation dose is shown in Fig. 5.5. The negative ∆Ig is larger for Vbn biased devices, while the positive ∆Ig is larger for the Vbp biased capacitors. The lowest ∆Ig values are always observed for the Vb0 bias, indicating that the leakage intensity is enhanced by the applied gate bias, similar to SEGR [Joh98b, Sex98], where the applied field has a leading role in generating the conductive path across the oxide.
5.3. Flash Memories Flash memory has become in the most recent years the star among non-volatile memories because it offers the capability of being electrically erased and re-written, so far featured only by the expensive E2PROM’s, at a cost comparable to the one of EPROM’s. Together with the desirable features, which make it so attractive, flash memory unfortunately combines also the reliability issues of EPROM’s and E2PROM’s. Since the reliability requirements for flash memories are more severe than for the other logic applications, mainly due to the problem of data retention and endurance which are added to the conventional reliability issues discussed in section 2. We’ll shortly review the main characteristics and reliability issues of Flash Memory cells whose applications is increasing more and more. Before beginning we briefly describe the principles of functioning of a single Flash cells. A cross section of a Flash memory cell is shown in Fig. 5.6, where the writing (a) and the erasing (b) operations are illustrated. The basic structure of a Flash memory cell consists of a staked gate MOS transistor where the first gate is called floating gate (FG), which is completely embedded inside the dielectric. The second gate is called control gate, is separated from the FG by the interpoly dielectric and acts as the external gate of the memory cell [Pav97]. The stored data is based on the conduction state of the MOS transistor constituting the memory cell. The channel conductivity is changed by modulating the threshold voltage, i. e., varying the amount of charge within the FG [Pav97]. Hot channel injection can be used to move electrons from the channel into the floating gate, thus changing the threshold voltage of the III-52
transistor. The memory cell is programmed by applying voltage pulses to the control gate and to the drain at the same time, when the source is grounded. The change in the threshold voltage depends on the width of the programming pulse, which generally lasts for 1-10 µs. Other kinds of Flash memory cells exist, like the ACT’s (i.e., Asymmetrical Contactless Transistor) whose programming step is performed by Fowler-Nordheim injection [Pav97]. Also the erase operation requires high voltage pulses to be applied to the source when the control gate is grounded and drain floating. Electrical erase may be achieved via FowlerNordheim tunneling of charge from the FG to the source. Typical erasing times are around 100 ms [Ari93, Pav97]. Then, when programming or erasing step is performed, electron transport takes place through the tunnel oxide between the Si substrate and the FG, which is about 10 nm thick, the actual thickness being possibly even smaller, depending on the specific cell structure and memory architecture. Hence, programming and erasing (p/e) memory operations (not reading) occur by forcing a high electric field across the thin tunnel oxide, thus degrading the oxide. Write operation Control Gate
Erase operation
Floating Gate Vg>0
Source
Control Gate
Vd>0
Vs>0
Drain
Source
P-substrate
FLOATING
Drain P-substrate
(a) Fig. 5.6
Floating Gate
(b)
Cross section of the floating gate MOS transistor, which is the core of a Flash cell. (a) Write operation; (b) read operation.
The wear out of tunnel oxide during high-field injection has been correlated to two main phenomena: the building up of both positive or negative trapped charges and the generation of defects inside the oxide [Ari93, Buc90, Had89, Mur94, Yam93]. Charge trapping is more detectable in thicker oxide (> 8 nm) and it is the main reason responsible for the threshold voltage window closure [Pav97]. On the other hand, defects generation in thinner oxide leads to an increase of low-field leakage current (i.e., Stress Induced Leakage Current, SILC) [Oli88]. This low-field leakage current degrades the data retention of the EEPROM, causing a new failure mechanism [DeB98b, Pav97].The most important factors that impact reliability of tunnel oxide and, in general, flash cell can be summarized as follows: • Over-erasing: occurring when the erasing speed of a cell is too high with respect to the other cells. As all the cells in an array are erased simultaneously, the time required to erase the slowest bit may be long enough to over-erase the fastest bits, and an over-erased cell may exhibit a negative threshold voltage. Hence, all the cells connected to the same over-erased bit line would be read as “1” irrespective of their actual content, and consequently a memory array cannot be correctly read if it contains depleted cells. • Endurance: due to the quite uniform and reproducible wear-out of memory cell performance. It consists of the increase of the e/p time with the number of e/p cycles, III-53
•
•
which eventually may exceed the specification limits. The reduction of program efficiency after extended cycling is attributed to oxide traps and interface state generation at the drain side of the memory cell [Yam93]. Erratic bits: such bits show an unstable and unpredictable behavior in erasing: their threshold voltage changes randomly from cycle to cycle between two or more distinct values, moving back and forth from the bulk of threshold voltage distribution to the lowest part of the tail [Ong93]. Erratic bits can cause over-erasing failures. Such behavior has been attributed to hole trapping in the tunnel oxide, where clusters of two or more positive charges may lead to a local increase of the tunnel current during e/p. Trapping/detrapping of an individual positive charge causes, in this condition, a detectable change in erasing speed. Data retention: As any non-volatile memory, flash memories are specified to retain data for over 10 years. Possible causes of charge loss are defects in tunnel oxide or defects in interpoly dielectric. This can lead to an increase of the leakage current from the FG and corresponding loss of data. Charge loss may be the most important factor in the Flash cell reliability. In fact, what is specific of flash memory with respect to EPROM is the thinner gate dielectric, which makes the impact of oxide defects on data retention more critical. In addition the scaling of cell size results in a reduction in tunnel oxide thickness as well as the cell geometry, thus decreasing the FG stored charge. Nevertheless, scaling the tunnel oxide is limited by leakage current and data retention.
5.4. Radiation effects on Flash memories The most radiation sensitive part of commercial Flash memories is the complex circuitry external to the FG cell array. Different functionality failures have been detected in commercial devices depending on the operation mode during heavy ion irradiation [Kra00, Ngu98, Ngu99, Rot00]. On the other hand, these works have shown that bit flips due to heavy ions are seldom observed in devices submitted to heavy ion tests, indicating that the FG transistor is quite robust against radiation damage. This robustness is related to the read-out protocol: no bit flip is measured if the variation of the FG MOSFET threshold voltage (VTH) is below that needed to exit the 0/1 programming limits. Nevertheless, ionizing radiation definitely produces some variation of the threshold voltage (VTH) of the FG MOSFETs. This problem was addressed by Snyder et al. [Sny89], who identified three mechanisms responsible for large charge loss from the FG: 1. hole-electron pairs are generated by radiation inside the tunnel oxide or the OxideNitride-Oxide interpoly oxide (ONO) separating the FG from the Si substrate and Control Gate (CG), respectively. Some of the holes surviving the prompt recombination phase can drift into the FG, where they recombine part of stored electrons, thus reducing the FG negative charge. The FG negative charge itself produces the oxide fields driving the holes toward the FG, while radiation generated electrons are driven toward bulk Si or CG; 2. other radiation-generated holes can be trapped in the tunnel oxide, thus reducing the FG MOSFET VTH; 3. electrons stored in the FG can gain energy from the ionizing radiation and be emitted over the oxide barrier height toward the CG or the Si substrate. III-54
Noticeably, these results have been observed on EEPROM cells proper of the 1989 technology, featuring thick oxides (40 and 47.5 nm) around the FG. Owing to the local sensitivity of the cell array to ionizing radiation and to their capability of retaining the information relative to the corresponding charge lost, FG memories have been proposed for dosimetric applications in space missions [Sck98].
5.5. Single event effects on memory cells Concerning the VTH variation of FG cells, a single heavy ion may lead to large effects. To evaluate this effect, Cellere et al. [Cel01, Cel02] studied a cell array, organized as a NOR matrix, where programming was done at cell level using Channel Hot Electrons (CHE) at the drain, while erasing was done at block level using Fowler-Nordheim tunneling at the source. The threshold voltage VTH,Hi of the memory cell in the programmed “1” state should be VTH,Hi>6V, while in the erased “0” state VTH,Lo< 4V. A chip with all FG programmed at “1” was irradiated with 2x107 I ions/cm2. Fig. 5.7 shows the VTH variation over a small part of the irradiated array. Each square represents a single cell featuring a gray level related to the ∆VTH shift: the darker the square, the larger the threshold variation, which is always negative (VTH decreases). The struck cells appear randomly distributed across the chip surface. Large |∆VTH| were measured on isolated cells and on cells whose neighbors were hit. On the average, about 4.5% of cells have been hit by one or more ions, in contrast to the 3% expected. This means that ions hitting “close enough” (but not exactly over) the FG could still produce threshold shift. In this case, part of the radiation-induced charge could be collected by the fringing field around the FG. Extending by just 50 nm the FG linear dimension would increase the hit cell percentage to 4%, not far from the experimental results.
Fig. 5.7
Spatial distribution of threshold voltage for a cell subset of a chip after 2x107 Iodine ions/cm2. The gray scale (right) indicates the amount of ∆VTH; the two cells indicated by arrows have ∆VTH >2V. Each square represents a FG cell.
The threshold decrease after irradiation is illustrated in Fig. 5.8. The pre-rad VTH,0 is distributed between 6.4 and 7.4 V, due to cell-to-cell differences and to the programming protocol, which stops the CHE injection when VTH>6 V but allows for some over-programming. After irradiation, a secondary peak appears around 6 V, while the upper part of the curve is not appreciably modified for VTH>6.7 V. This peak represents cells that suffered a large VTH shift III-55
after irradiation, but not necessarily all hit cells, since some hit cells may still retain a high VTH. Noticeably, in about 1.8% of all cells 4 V
100000
Number of cells
10000
Pre rad After rad
1000 100 10 1 4
5
6
7
8
VTH (V) Fig. 5.8 Probability density of threshold voltages before and after irradiation with 2x107 Iodine ions/cm2.
5.6. Threshold Voltage Effects on the Charge Loss VTH plays a fundamental role in determining the radiation response of irradiated FGs. As previously observed [Sny89], the amount of radiation induced electron and holes collected by the FG depends on the field intensity in the dielectric layers (tunnel and ONO) sandwiching the FG. Different programming levels (i.e., VTH,Hi) may be selected for the memory array, corresponding to different negative charges in the FG and, consequently, different fields in the tunnel oxide and ONO around the FG. After irradiating a device with sectors programmed at different VTH,0 values, results reported in Fig. 5.9 were found [Cel01]. The memory was partitioned into several groups of cells, depending on their pre-rad VTH,0 value. For instance, the VTH,0 values of a device were divided in 5 adjacent ranges (named (α, β, γ, δ, ε), each one 100 mV wide: α spans between 7.0 and 7.1 V, β between 7.2 and 7.3 V, and so on. The minimum VTH,0=7.0 V corresponds to III-56
15,500 electrons in the FG, while the maximum VTH,0 =7.5 V to 17,250. Fig. 5.9 shows the normalized probability density of electron charge loss and ∆VTH for the five cell groups after irradiation with 107 Si/cm2. All curves increase when the charge loss approaches zero, indicating that small charge losses from the FG are reasonably probable due to the ion hit. In addition, the most probable charge loss peaks at 1,200 lost electrons for curve ε, 850 for δ, and 500 for γ. For the other curves, the peak is undetectable and compressed on the Y-axis. Hence, the largest charge losses occur from those FGs trapping the largest electron charge. Moreover, on the average, group ε loses ∆Q=350 electrons more than group δ, and group δ loses ∆Q=350 electrons more than group γ. The falling edge of curve β is again 350 electrons on the left of the falling edge of curve γ. ∆Q=350 electrons is exactly the pre-rad threshold difference between two adjacent groups.
0
−∆VTH (V) 0.4 0.6
0.2
Normalized probability density
12% 10%
β
8%
γ
δ
α
6%
ε
α β γ δ ε
0.8
Electrons [15,500-15,850] [15,850-16,200] [16,200-16,550] [16,550-16,900] [16,900-17,250]
1
VTH,0 (V) [7.0-7.1] [7.1-7.2] [7.2-7.3] [7.3-7.4] [7.4-7.5]
4% growing VTH,0
2% 0% 0
Fig. 5.9
500
1000
1500 2000 Lost elettrons
2500
3000
3500
Probability densities of the number of lost electrons (lower X-axis) and ∆VTH (upper X-axis), for cells with different initial stored charge.
The impact of VTH,0 on the radiation induced charge collected at the FG is strongly dependent on the fractional yield (i.e., the number of holes surviving the prompt recombination), which increases with the oxide field, controlled in turn by the charge stored on the FG. However, the results of Fig. 5.9 cannot be naively explained by claiming that more holes reach the FG when the electron charge on the FG is larger. In fact, when considering for instance a single Si ion hitting the FG, it generates approximately 1,200 and 2,100 electron-hole pairs in the tunnel and ONO oxides, respectively (Si generates 1.17x109 pairs/cm). For a FG with VTH=7V, the oxide field in the tunnel oxide is EOX=2.8 MV/cm, while in the SiO2 layer of the ONO EO=1.8 MV/cm. Under these conditions, less than 5% of the holes generated in the tunnel oxide and less than 1% of those generated in ONO will survive prompt recombination [Boe76], driving into the FG less than 100 holes from both the tunnel oxide and ONO sides. The few radiation-induced holes cannot produce the large FG charge loss, up to 1,500 electrons. Even electrons emitted from the FG over the Si/oxide barrier cannot account for the experimental data. For this reason authors proposed that a fourth mechanism, in addition to those listed by [Sny89] should be active, to III-57
account for the FG charge loss, based on an enhanced leakage from the FG. If this mechanism relies on a preferential leakage path along the ion produced neutral defects, or instead along residual trapped holes, and what are the characteristic discharge times are problems still unresolved. The fact that this anomalous leakage was not previously reported on EEPROM’s [Sny89] derives form the thickness of the with tunnel and interpoly oxides, 47.5 and 40 nm thick, respectively, and from the exposition to Co60 gamma rays. Holes produced by gamma rays are unable to form localized conductive paths across 40 nm thick oxides. The combined effect of thicker oxides (4 times thicker than in Flashdevices) and few holes (10 times less) inhibits the formation of leaky paths responsible for the high charge lost from FG measured on Flash cells. The impact of the residual ion damage in terms of cell retention and endurance is a key issue for FG cells, but it has not found yet a comprehensive treatment in literature. Preliminary results indicate that charge retention of ion hit cells may be significantly reduced, while endurance characteristics appear less sensitive to preliminary radiation damage. Noticeably, the investigation should consider also other cell structures and architectures, such as NAND-type arrays with tunnel oxide thinner than NOR-type, cells with 2 or more bits per cell, cells with 2 transistors per cell, memories with positive or negative charge stored in the FG in correspondence to the “0” and “1” logic values. On top of it, the continuous shrinking of the cell size, and the corresponding reduction of the FG stored charge, may negatively affect the traditional robustness of the FG transistor against single event effects.
III-58
6. Ultra-Thin Oxides 6.1. Introduction CMOS hardening technologies have been developed ad hoc to prevent or limit the occurrence of degradation phenomena in radiation harsh environments. In parallel, Moore’s law itself was playing an underground role in enhancing the radiation tolerance of commercial CMOS components, a role appeared only in recent years. In fact, shrinking the device dimensions following Moore’s law can be accomplished only by the parallel thinning of the gate oxide to preserve the transistor current driving capability, as shown in section 2 [Dav95, Fra01]. How the gate oxide thinning could enhance the device radiation tolerance was foreseen in the pioneer work by Saks and Ancona [Sas87]. In fact, being the electron tunneling distance around 3 nm in SiO2, when the oxide thickness reaches 6 nm or less the radiation induced oxide positive charge is easily recombined or neutralized by electrons tunneling from the gate and/or Si substrate (see Fig. 6.1). This oxide thickness was approximately reached at the CMOS technological node of 0.25µm, and the first results reporting the excellent radiation tolerance of quarter-micron CMOS components soon appeared [Gir97, Lac97]. Positive charge accumulation in the thick field oxide is not removed for both LOCOS and shallow trench isolation and it may produce the onset of a parasitic nMOSFETs between source and drain. However, this problem can be successfully circumvented by using enclosed (gate-all-around) transistor layouts and proper guard-rings [Gir97]. For these devices nominal radiation tolerance over 10 Mrad(Si) were measured, i.e., exceeding by far the typical requests even for long space missions. Following the CMOS technological evolution the gate oxide thickness has now reached 2 nm or so, becoming even less sensitive to positive charge trapping problems.
Fig. 6.1
Neutralization of ionizing radiation induced electron-hole pairs. Due to the short tunneling distance the trapped holes are rapidly recombined by electrons from the gate or the substrate.
III-59
For instance Fig. 6.2 shows the change (∆Vt) in the threshold voltage of n-channel MOSFETs as a function of the total dose of 60Co γ-rays (0.18µm and 0.35µm technology). Before irradiation the threshold voltage was Vt=0.44V and 0.61V for 0.18µm and 0.35µm technology, respectively [Man00]. After 30 Mrad γ-rays, ∆Vt ~ 30mV, reducing to just 20mV after an annealing step. Even transconductance shows a modest reduction (~ 10%) after 30 Mrad, while the white noise level increases by less than 5%. This means that a 0.18µm technology (typical oxide thickness around 4nm) is modestly tolerant to high doses of ionizing radiation. 100
before irradiation
0
T
∆V [mV]
50
0.18 um (Group A) 0.18 um (Group B) 0.35 um
-50
-100
after annealing
20
40
60
80 100
300
Dose [kGy] Fig. 6.2
change (∆Vt) in the threshold voltage of a n-channel MOSFET as a function of the total dose of 60Co γrays (0.18µm and 0.35µm technology)
If radiation induced charge trapping problems have been overcome due to the gate oxide transparency to electrons, this characteristic has become the weak point from a reliability viewpoint. Ionizing radiation (as well as electrical stresses) can in fact produce defects acting not as trapping centers but as the agents of leakage paths across the gate oxide driving an excess gate current. Gate leakage adversely affects the overall circuit power consumption, which has been often taken as the key parameter for reliability predictions. Different leakage currents developed depending on the oxide thickness and radiation LET with electrical characteristics similar to those due to electrical stresses illustrated in section 3 (see Fig. 6.3) [Ces98, Ces99a, Ces99b, Ces00a, Ces00b, Joh98b, Lar99, Sca97c, Sex98, Tit98]. The first observations concerned the catastrophic Single Event Gate Rupture (SEGR), already observed on relatively thick oxides irradiated under high oxide fields [Fle00, Joh98b, Sex98, Tit98]. Then, the Radiation Induced Leakage Current (RILC) was reported for oxides in the range 4-8 nm [Ces98, Ces00a, Lar99, Sca97c,]. While SEGR takes place across a single weak spot on the gate oxide surface, RILC is modeled as an inelastic tunneling via traps uniformly distributed in the oxide layer reproducing the random pattern of the ion hits [Lar99]. On the contrary to SEGR, RILC is only a modest increase of the leakage current across the oxide (Fig. 6.3) and may be a severe limits only for non-volatile memories. When the oxide thickness is scaled well below 4 nm, as in the contemporary CMOS technologies, the leakage current is very large even in unstressed devices, due to the direct tunneling of electrons across the oxide trapezoidal barrier. Radiation induced III-60
Soft Breakdown (RSB) has been observed in 3- and 4-nm oxides only after irradiation with high LET ions [Ces99a, Ces99b ,Ces00a, Ces00b], and consists in a large increase of the oxide leakage current, which is however smaller than in Hard Breakdown regime. Only RSB and SEGR appear the main factors limiting the device lifetime, while RILC can be important for such applications as EPROM-like memories [DeB98b]. 10-4 10-5
Hard Breakdown Radiation Soft Breakdown
10-6 Ig [A]
10-7 10-8 10-9 RILC
10-10 10-11 10-12 0
Fresh 0.5
1
1.5
2
2.5
3
Vg [V] Fig. 6.3
Gate Current vs. Gate Voltage (Ig-Vg) measured before and after irradiation on a 3-nm oxide. The two curves referring to RILC have been measured after irradiation with 5.8⋅1010 and 1.5⋅1011 Si ion/cm2. The RSB has been obtained after irradiation with 107 I ions/cm2.
6.2. Radiation Induced Leakage Current In the following of this section, we will address various issues concerning RILC [Ces98, Lar99, Sca97c]: First of all, we will analyze the RILC conduction mechanism, aiming to better understand the tunneling process mediating the electron transport across the oxide. Secondly, the RILC intensity will be studied as a function of the oxide field during irradiation, in order to evaluate the origin and the distribution of the neutral traps mediating the tunneling conduction. Finally,we’ll present the RILC kinetics as a function of the total cumulative radiation dose, and compared with that found for SILC.
6.2.1. RILC Conduction Mechanism The current density – oxide field characteristics (Jg-Eox) of a 6-nm oxide are shown in Fig. 6.4, before and after a high dose irradiation with 8 MeV electrons produced by a pulsed LINAC accelerator. The main effect of irradiation is represented by the increase of the low-field gate current, observed between Eox=3 MV/cm and Eox=6 MV/cm. The oxide trapped charge in the stressed capacitors is negligible, as deduced from the overlap of the high-field characteristics of irradiated and unirradiated devices, corresponding to the FN tunneling regime. RILC can be evaluated as the excess current Je arisen after stress: Je = J g - J 0
(6.1)
Jg and J0 are the gate current density after and before the stress, respectively. III-61
10-4 Dose (Mrad(Si)):
|Jg| (A/cm²)
10-5 10-6
50
10-7 10-8
4
10-9
fresh
10-10
2
3
4
5
6
7
8
|Eox| (MV/cm) Fig. 6.4
Negative Jg-Eox curves measured before (fresh) and after irradiation for various doses ranging from 4 to 50 Mrad(Si).
10-5
Je (A/cm²)
5.2 nm 10-6
10-7 SILC
6 nm
10-8 5
6
RILC
7
8
Eox (MV/cm) Fig. 6.5
Excess current after radiation or electrical stress for two different oxide thickness (5.2 and 6 nm).
SILC is generally considered as the result of a trap-assisted tunneling across the oxide, mediated by neutral traps created by the stress [Ros97, Run97, Sak97a, Tak96]. Owing to the similar Jg-Eox characteristics of RILC and SILC, even RILC can be correlated to a trap-assisted tunneling where traps are generated by irradiation. We have studied the field dependence of the excess gate current in order to investigate the details of this conduction mechanism. As shown in Fig. 6.5, the Je slope suddenly increases at a critical kink field Ek, which is characteristic of the oxide thickness. For a given oxide thickness, Ek is the same for both positive and negative excess currents, and it increases when the oxide thickness is reduced. This kink appears associated to the modification of the barrier seen by the electron inside the oxide trap before being emitted toward the anode. This barrier is trapezoidal for Eox<Ek, and it becomes triangular for Eox>Ek, hence enhancing the barrier transparency and the corresponding tunneling current, as shown in Fig. 6.5 [Ces98]. These results are not consistent with an elastic tunneling model for RILC. In this case (no energy lost by the tunneling electron during its transition through the trap), the current kink would occur when the oxide voltage drop equals the oxide barrier height at the cathode. III-62
Assuming a cathodic barrier height ΦB≅3 eV and tox=6nm, the critical field should be Ek=ΦB/qtox≅5 MV/cm. The experimental results (Fig. 6.5) indicate that Ek is larger: for instance, Ek≅6.4 - 6.5 MV/cm when tox=6 nm for both RILC and SILC. Hence, we have assumed an inelastic tunneling mechanism also for RILC, illustrated in Fig. 6.6 [Sak97a, Tak96]. The critical field Ek corresponds to the same change of the barrier shape (trapezoidal→triangular) as previously described. Ek can be easily evaluated as: Ek =
ΦB + ∆E q ⋅ t ox
(6.2)
where ∆E is the energy lost by the electron. The experimental results can be well fitted by using eq. 6.2, as demonstrated in Fig. 6.7, where the measured critical field values are reported as a function of the oxide thickness. In devices with tox<5 nm, the estimated critical field is so high that the gate current is dominated by the FN injection [Len69]. RILC is negligible in comparison with the FN current and any measurement of Ek becomes unreliable. In all measured devices, ∆E≅1-1.5 eV, for both RILC and SILC, in agreement with previous findings for SILC [Ros97, Tak96]. This is further evidence that RILC and SILC conduction mechanisms are similar and mediated by a trap-assisted inelastic tunneling process.
E<EK
φ
E>EK
φ ∆E
∆E tox
tox (b)
(a) Fig. 6.6
Inelastic trap-assisted tunneling for: (a) Eox < Ek and (b) Eox > Ek.
10 4 nm
EK (MV/cm)
9
44 nm
estimated
8 7 theoretical
6 5
4
5
6
7
tox (nm) Fig. 6.7
Critical field Ek as a function of tox. Closed square symbols (g) represent experimental measurements, while open dots ({) indicate the expected values for tox = 4 nm and 4.4 nm.
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10-7
Solid lines: measured 8 MeV electrons
|Igate| (A)
10-8 10-9
negative
10-10
positive
Dashed lines: simulated
10-11 10-12 Fig. 6.8
1
2
3
|Vgate| (V)
4
5
Comparison between simulation and measured RILC curves.
An analytical model of RILC has been developed for ultra-thin oxides submitted to ionizing radiation, based on the analytical solution of the Schrödinger equation for a simplified oxide band structure [Lar99]. Here RILC occurs through a two-step process: first, an electron tunnels into the oxide defect from the cathode conduction band edge. Then, the electron tunnels out the trap after having lost approximately 1.5 eV, in agreement with previous findings for SILC. The mathematical explanationt of the model is quite complex and even the final analytical expression for the tunneling current is quite lengthy. Fig. 6.8 shows the comparison between simulation and experimental data for negative and positive RILC. Simulation results have shown that the most effective traps promoting RILC conduction are located close to the middle of the oxide and are energetically placed 1.3 eV below the oxide conduction band.
6.2.2. RILC dependence on applied bias during irradiation In this section we investigate how the distribution of neutral traps responsible for RILC is affected by the bias applied during irradiation. To this purpose the capacitors were irradiated by using a 8 MeV electron beam and were biased at different oxide fields during and after irradiation. In Fig. 6.9a (tox=4 nm) and Fig. 6.9b (tox=6 nm) we have reported RILC as a function of the oxide field applied during irradiation. The 6-nm capacitors have been subjected to a radiation dose 10 times higher than the 4-nm devices, to enhance the measured current and the corresponding experimental precision. The obtained results are similar on both device types. Positive RILC is higher than the negative one in devices negatively biased during irradiation. The opposite holds true on devices positively biased when irradiated. Such difference disappears and RILC is the maximum when the oxide field is close to zero during irradiation, while RILC decreases for increasing oxide field applied during irradiation. These results show that the trap distribution is controlled by the oxide field during irradiation. This result cannot be explained, if neutral traps are directly generated by the impinging 8-MeV electrons, as in case of knock-on displacement damage of the oxide lattice, for instance. Such defects should be homogeneously generated in the oxide layer, and any effect due to the oxide field should be negligible. Instead, the RILC-assisting defects result from microstructural transformations of charged defects generated by irradiation, which are fieldIII-64
sensitive. Mechanisms leading to neutral traps generation are schematically depicted in Fig. 6.10. Neutral defects could result from the neutralisation of an E’ centre after capturing a hole [Wal91]. In short, a neutral electron trap could result from a hole capture at a weak Si-Si covalent bond, which may relax into a Si:- Si+ neutral amphoteric defect after the hole compensation. Even though holes appear as the first candidate for generating neutral defects, the possible role of hydrogen cannot be neglected [DiM95]. In fact, ionizing radiation can easily break the weak bonds of bonded H atoms, which can migrate under an electric field and be trapped in different sites, possibly generating again neutral defects in the oxide and/or leaving electron traps in the original site. 70
6
60
5 |Je| (nA/cm2)
|Je| (nA/cm2)
50 40 30 20 10
4 3 Dose = 50Mrad(Si)
Dose = 5Mrad(Si)
2
0 -6
-4
-2
0
2
4
-3
6
-2
-1
1
2
3
EOX (MV/cm)
EOX (MV/cm)
(b)
(a) Fig. 6.9
0
Excess current read at |EOX| = 5MV/cm for different gate voltages applied during 8 MeV electron irradiation for: a) tox = 4nm and b) tox=6nm ({ = positive RILC; g = negative RILC)
Trapped holes
Poly-Si
Si
Hole transport e-h recombination Fig. 6.10 Mechanism for hole generation and trapping in the oxide and neutral defect generation.
RILC is maximum when the oxide field is zero, and a small difference is observed between positive and negative RILC. In this case, we can easily assume a symmetrical distribution of RILC–assisting defects across the oxide, which is not affected by the nitrogen-rich oxide layer observed through SIMS analyses in proximity of the Si substrate (all oxides have passed a III-65
nitridization step at high temperature). In this region, the concentration of hydrogen atoms (which passivate dangling bonds or other lattice defects) should be smaller than in the pure SiO2 layer, due to the presence of N atoms. Thus producing an asymmetrical curve distribution, which could hardly give rise to symmetrical RILC characteristics at zero oxide field, hence indicating holerelated neutral traps as the main origin of RILC. In thick irradiated oxides, the measured fractional yield increases with the field intensity, due to a reduced recombination of the pairs generated by the ionising radiation [Old83]. Consequently, trapped hole density increases, and the maximum threshold shift is observed at high positive fields. On the other side, RILC decreases when the oxide field increases, in apparent contradiction with the claim that neutral traps are a product of trapped holes, which should reach their minimum density at zero oxide field. However, at low oxide fields prompt recombination could be smaller in thin than in thick oxides, as the thermalization distance of an e-h pair is around 5-10 nm. This distance is larger than the oxide thickness, thus leading to a robust physical separation between many generated pairs. The amount of holes which have escaped the prompt recombination process should not be negligible in ultra-thin oxides. In addition, these holes should be homogeneously distributed over the oxide hole traps. Moreover, holes are pushed toward the cathode during irradiation. A positive charge displacement of about 10 nm due to the applied field has been reported for thick oxides over a time period shorter than 1 µs after a radiation pulse [Old83]. Even though this value is meaningless in 4-6nm oxides, it indicates a substantial positive charge accumulation at the cathodic interface. The amount of holes, which have survived the prompt recombination step in a non-zero oxide field could be even higher than under zero bias, but shifted toward the cathode. Anyway, after being trapped in the oxide, all holes would be easily recombined by electrons tunneling from both interfaces, over a time scale of few seconds at most, giving rise in part to neutral defects. RILC intensity grows with the defect density, but it is strongly dependent on the defect position in the oxide layer. Results indicate that RILC is maximum for a homogeneous distribution of traps (zero-field irradiation), and it decreases when traps are pushed toward one interface (Eox ≠ 0), even though the trap density is likely higher in the latter case. Differences between positive and negative RILC result from this asymmetric trap distribution, indicating that traps are less effective when close to the cathodic interface during measurement, in full agreement with simulations that identify traps close to the middle of the oxide thickness as the most affective for RILC [Lar99]. Concerning the microscopic nature of defects responsible for RILC, a strong correspondence between the generation of an oxygen deficient silicon dangling bond defect in the oxide and the appearance of oxide leakage current has been demonstrated [Leh01]. On one side, generation of E’ centers as detected by Electron Spin Resonance technique is accompanied by the appearance of the oxide leakage current. In the same way, after a thermal annealing cycle at 200 C both the E’ center density and the oxide leakage current decrease (see Fig. 6.11). Radiation stresses can be compared with Constant Current Stress (CCS), which are shown in Figs. 6.12a and 6.12b for the 4-nm and 6-nm devices, respectively, as a function of the stress current. The Fowler-Nordheim stress current is a logarithmic function of the oxide field, and it has been reported on the X-axis in order to obtain a better separation of the data. SILC is the minimum for the lowest stress field: in fact, the energy of the injected electrons grows with the oxide field, and in the same way does the oxide damage as well. When a negative CCS is performed (negative oxide field), the negative SILC is smaller than the positive one, similar to the results found for RILC. The opposite is observed for positive CCS, but the negative-positive SILC difference is much larger than in the previous case, and the negative SILC reaches the maximum measured values. This represents a striking difference with RILC, and it must be III-66
related to the presence of the nitrided oxide layer. SILC, as well as RILC, is attributed to defects related to trapped holes and/or hydrogen-like species (positive species), which are generated at the anodic interface and re-injected in the oxide layer during the stress. The nitrided layer has been proposed to act as a diffusion barrier against the diffusion of holes or hydrogen [DiM95, Deg96]. Hence, during a positive stress, the positive species should be generated at the gate/oxide interface by the high energy FN electrons, and re-injected in the oxide creating traps across all the oxide, but more efficiently in the nitride layer. Hence, negative SILC should be higher than the positive one, being traps accumulated toward the substrate. On the contrary, during a negative CCS, holes (injected from the substrate) would be easily blocked by the nitride layer close to the injecting interface (i.e., in a position quite ineffective to produce SILC), with a reduced trap generation in the residual oxide thickness, thus producing lower SILC values.
Fig. 6.11 Electron Spin Resonance traces of as processed, post VUV irradiation, and post 20 min annealing at 200 C taken on a 4 nm oxide film.
500 Q inj=
q/cm2
Q inj = 1019 q/cm2 20
300
|Je| (nA/cm2)
|Je| (nA/cm2)
400
25
6.3×1018
200 100 0 -10
-5
0 Jstr (mA/cm2)
5
10
(a)
15 10 5
-10
-5
0 5 Jstr (mA/cm2)
10
(b)
Fig. 6.12 Excess current read at |EOX| = 5MV/cm as a function of CCS current density, for a) tox = 4 nm and b) tox = 6 nm ({ = positive SILC; g = negative SILC).
III-67
Noticeably, the effect of the nitrided layer is undetectable on irradiated capacitors. This suggests that the blocking effect of this layer is not active on holes travelling during the prompt displacement period after generation. In fact, holes drift via a polaron-activated transport mechanism, which is likely unaffected by the presence of the nitride layer. Once holes are trapped, the effect of the nitrided layer becomes negligible: soon, all the trapped charge recombines with tunneling electrons and further displacement due to the oxide field is negligible. 10-5
10-5
tox=4 nm
10-6 tox=6 nm
Je (A/cm2)
Je (A/cm2)
10-6
tox=4 nm
10-7 10-8
tox=6 nm 10-7 10-8
10-9 1
10
100
10-9
1000
1017
Dose (Mrad (Si))
1018 1019 Q inj (electrons/cm2)
1020
(b)
(a)
Fig 6.13. RILC (a) and SILC (b) kinetics (negative excess current) for tox = 4 nm (□) and tox = 6 nm (n). Vg=0V during 8 MeV electron irradiation.
6.2.3. RILC growth kinetics In this section, we present the RILC kinetics as a function of the cumulative radiation dose, aiming to analyse the kinetics of defect accumulation in the oxide. We show in Fig. 6.13a the RILC variation with the total cumulative dose. RILC has been measured at an oxide field Eox=6 MV/cm on both 4-nm and 6-nm oxides. For a given radiation dose, the excess current is much higher in the 4-nm oxides, owing to the higher tunneling probability across the barrier, which is thinner than in the 6-nm oxide. RILC data can be well fitted by using the following relation: J e = K R ⋅ Dose
β
(6.3)
Here β≅0.9 for tox=6 nm and β≅0.94 for tox=4 nm, while KR is a constant that depends from the read-out gate voltage and oxide thickness. Approximately, RILC grows linearly with the radiation dose, indicating that the oxide defect density follows a linear growth rate as well. In Fig. 6.13b SILC is plotted versus the injected charge (Qinj) during a CCS with Jstr=10mA/cm2 for both 4-nm and 6-nm devices. At least at high stress levels, SILC follows the empirical law presented in section 3[Sca97c]: DJ γ stress J e = J sat ⋅ exp− α Q inj
III-68
(6.4)
where α≅0.31 for tox=6 nm, α≅0.18 for tox=4 nm, γ≅0.04, Jsat is the saturation SILC level, and D is a constant depending on the oxide thickness and quality. If RILC and SILC can be attributed to holes trapped in the oxide, the contribution given by a single injected hole to RILC/SILC can be evaluated. The quantum yield of positive CCS has been accurately measured on the 4-nm oxides, and a substrate hole current ≅10-4 times smaller than the CCS current has been found, for a gate current density Jg=10 mA/cm2 [Sca99]. This current corresponds to holes generated at the anodic interface, re-injected in the oxide layer and not trapped and recombined within it. Holes contributing to RILC can be estimated, by taking 18 eV as the average energy required to generate a pair in thick oxides [Ben86] (some question could arise if the same is true in thin oxides, and if any further hole injection could occur from the substrate or gate). An elementary calculation will show that, for a given excess current intensity, the amount of SILC holes is slightly larger (up to 3 times at most) than RILC holes (see Figs. 6.9). Practically, the same quantity of holes is measured in both cases, within the large experimental error. Despite this correspondence, SILC shows a saturating behavior for those current levels, which still correspond to a linear growth rate of RILC. Moreover, α is lower in 4-nm than in 6nm oxides, indicating that SILC saturates faster in thicker oxides. Saturation appears as a peculiar characteristic of SILC, which has never been successfully explained (see section 3). This basic difference between RILC and SILC should be related on one side to the defect distribution within the oxide layer, which results from uniform generation of holes across the oxide (RILC) or high field injection from the anode (SILC). On the other hand, many more electron are injected by CCS than by radiation for the same gate leakage level, suggesting that electrons may effectively passivate/anneal part of the stress induced defects for electrically stressed devices.
6.3. Radiation induced Soft Breakdown The relative increase of the gate current due to RILC is much reduced in oxide thinner than 3-4nm, due to the increased tunneling current even in a fresh device. A large impact on the gate current is measured instead when a SB or HB event occurs [Ces99a, Ces99b, Con01, Dep95, Joh98b, Mal01, Mir00, Oka94, Sex98, Tit98]. The first reports of Radiation induced Soft Breakdown (RSB) appeared during SEGR studies in 1998 [Sex98, Joh98b]. RSB was detected as a sudden, large increase of the gate current, much larger than in case of RILC (see Fig. 6.14), but still smaller than in case of HB. The electrical characteristics of RSB are similar to those ones associated to the SB produced by electrical stresses [Ces00a] and can be modeled following the empirical relation proposed for electrically induced SB [Mir99a]: Ie = a·Vgb,
and
b = -0.78·log(a) - 3.27
(6.5)
where coefficients a and b are mutually correlated. In contrast with RILC, which is associated to a tunneling process across a single trap, RSB conduction is activated when one or more regions with high defect density are produced in the oxide layer. While eq.(6.5) represents only an empirical approach to discriminate between SB and non-SB events, physical models can describe some (if not all) of the RSB current characteristics as in case of SB. For instance, in a percolation picture, these defects produce different conduction paths for electrons across the oxide [Hou98a, Hou98b]. In the Quantum
III-69
Point Contact (QPC) approach, a single one-dimensional quantum path is activated across the oxide, where electrons are spatially confined [Sun00b, Mir99b, Cer01a]. 140
Capacitor Current (µA)
120
Soft breakdown with higher current
Ac = 1.23 x 10-3 cm2 LET = 37 MeV-cm2/mg
100 80 60
Soft breakdown with low current (note 2nd event)
40 20 0
0
20
40
60
80
100
120
140
Time During Irradiation (sec) Fig. 6.14 Radiation induced Soft Breakdown characteristics observed for 4.5nm capacitors.
6.3.1. Gate oxide leakage current dependence on ion LET It has been already shown that RILC appears as the excess current after irradiation with Co 60 γ rays or 8 MeV electrons, i. e. low LET radiation sources. Similar excess current can be measured after irradiation with ions such as Si, as shown in Fig. 6.15. Despite the largely different LET values (approximately 104), RILC shows the same functional dependence from the gate voltage after electron or Si ion irradiation. This result indicates that the density of defects generated even in the dense Si ion track not high enough to permit the onset of a conductive path involving several neighboring defects. In other words, RILC takes place again by trap-assisted tunnel through a single trap. Instead, Ig-Vg characteristics measured after irradiation with Ni and Ag ions show a different shape, which cannot be attributed to RILC. This difference is illustrated in Fig. 6.16, where the gate current curve shape for the various ionizing sources can be compared. The excess gate current observed after Ni or Ag irradiation derives from the onset of Soft Breakdown conductive paths. This is confirmed by the empirical fitting of the Ig-Vg curves through the empirical relation previously proposed to describe the SB conduction (Eq. 6.5). Both positive and negative curves are nicely fitted by using the same a and b parameter values as shown in Fig. 6.16a for Ag irradiated devices. On the contrary, RILC can not be fitted in this way and it shows the typical voltage offset between positive and negative curves, illustrated in Fig. 6.16b for Si irradiated samples. Moreover, this voltage offset is lacking in Fig. 6.17a for the RSB curves. Noticeably, the RSB characteristics have been obtained after irradiation performed with a relatively small oxide field, i.e., 3 MV/cm, indicating that RSB conditions can be reached even at low oxide fields.
III-70
10-6 158 MeV 28Si ions
10-7
8 MeV electrons
10-8
Ig (A)
125 Mrad(Si)
32 Mrad(Si)
10-10 10-11 10-12 1
fresh
Ie
10-9
Eox,bias=-3 MV/cm 1.5
2
2.5
3
3.5
4
4.5
5
Vg (V) Fig. 6.15. Gate current before irradiation (fresh), and after electron or Si ion irradiation at two doses. tox=4nm. 10-6
10-6 125 Mrad, 8 MeV electr.
125 Mrad, 8 MeV electr. 80 Mrad, 158 MeV Si 20 Mrad, 213 MeV Ni 0.6 Mrad, 257 MeV Ag
10-7 10-8
10-8
10-9
Ig (A)
| |g (A) |
80 Mrad, 158 MeV Si 20 Mrad, 213 MeV Ni
10-7
fresh
10-10
10-9
fresh 10-10
10-11
Ig < 0
10-11
0.6 Mrad, 257 MeV Ag
,
10-12 -0.5
-1.5
-2.5
-3.5
Vg (V)
-4.5
10-12 0.5 1
-5.5
1.5
2
(a)
2.5
3
Vg (V)
3.5
4
4.5
5
(b)
Fig. 6.16 a) Negative and b) Positive gate current-gate voltage curves after irradiation with different radiation sources. tox=4nm. 10-6
10-6 Positive IgVg
10-7
Negative IgVg Fit by eq. (1)
10-9
0.6 Mrad fresh
10-9
10-10
10-10
10-11
10-11
10-12 0.5
1.5
2.5
Negative IgVg
10-8
||g| (A)
|Ig| (A)
10-8
Positive IgVg
10-7
3.5
|Vg| (V)
4.5
10-12 0.5
5.5
(a)
80 Mrad fresh
1.5
2.5
3.5
|Vg| (V)
4.5
5.5
(b)
Fig. 6.17 Positive and negative gate current-gate voltage curves after irradiation with: a) Ag ions and b) Si ions. tox=4nm.
III-71
10-6 257 MeV Ag
Dose=10 Mrad (Si) Ie (A)
10-7
213 MeV Ni
10-8 158 MeV Si 8 MeV electron
10-9 0
Fig. 6.18.
10
20 30 40 50 60 -1 2 LET (MeV mg cm ) Excess gate current after irradiation at 10 Mrad(Si) with different radiation sources. tox=4nm. 2.0 (1)
Ig (nA)
1.5
(2) 1.0 (2)
0.5
0
100 200 300 400 500 600 700 800
Time (s) Fig. 6.19 Time evolution of the gate current during irradiation with Ni ions. The spikes (1) and (2) corresponds to switching on/off the RSB conduction through two different spots. tox=4nm.
The dependence of the excess gate current on the LET of the incident particles is summarized in Fig. 6.18 at the total dose of 10 Mrad(Si). Ions with LET<20 MeV⋅mg-1⋅cm2 can produce only RILC, while ions with LET>40 MeV⋅mg-1⋅cm2 (approximately) induce RSB. From an analysis of the results for electrons and Si, RILC seems to be not sensitive to LET variation. Instead, RSB occurs only for high LET values: only ion tracks with high density of e-h pairs can produce high density of oxide defects, resulting in conductive paths across the oxide through neighboring defects. One of the main feature of the SB conduction is the noisy behavior, which has been observed also for irradiated devices. Fig. 6.19 shows the time evolution of the gate current during Ni irradiation. The ion beam produces a noise level around 10 pA. The three large spikes that appear in Fig. 6.19 correspond to turning on (1) or off (2) a single conductive spot. The current flowing through III-72
this weak spot is >100 pA. These spikes lay over the linearly increasing gate current, which is due to RILC increasing with the Ni dose.
6.3.2. Quantum Point Contact Modeling In contrast with RILC, which is associated to a tunneling process across a single trap, RSB conduction can be successfully explained on the basis of the Quantum Point Contact (QPC) model [Cer01c, Con01]. The QPC model has been firstly introduced for electrically induced oxide Hard Breakdown and SB. [Mir99b, Cer01a]. The basic idea beyond the QPC picture is that the conduction is strongly localized and electrons flow through a single conductive path. In the case of radiation, each ion crossing the oxide has a non-zero probability of generating a RSB leakage path. Based on the QPC model, the lateral dimension of the breakdown paths is so small that the momentum in the direction perpendicular to propagation is quantized. If the path is narrow enough, the ground sub-band E0 is above the Fermi level at the cathode, and the conduction can only take place by tunneling across an effective 1-dimensional potential barrier (see Fig. 6.20), whose height is just E0. This barrier is not material-related, but its height cannot be larger than that of the Si/SiO2 system because electrons would be otherwise no longer laterally confined [Cer01a]. This model leads to the exponential relation for the gate current across a single SB spot [Con01]:
I g = A ⋅ exp ( −α ⋅ φ ) ⋅ exp ( B ⋅ Vg )
(6.6)
The parameters A and B have been related to the height and thickness of the local barrier in the breakdown path. The offset voltage V0 is due to some potential drop in the substrate. In case of RSB, where several spots can be activated after irradiation, Eq. 1 should be modified accordingly as [Cer01c]: I g = N ⋅ A ⋅ exp ( −α ⋅ φ ) ⋅ exp ( B ⋅ Vg )
(6.7)
N being the number of active spots. The A end B coefficient are given by: A=
4q α ⋅h
B=
αq 2
with q the electron charge and h the planck constant. The two main parameters associated with the model are φ, the barrier height of the quantum point contact, and α, which is correlated to the shape or thickness of the contact. The dependence on φ and α on irradiation fluence is shown in Fig. 6.21 [Con01]. In the RSB regime, φ is saturated to the value of the oxide/silicon barrier height, while α decreases with the fluence increase due to the increase of the RSB spot number. The occurrence of HB is clearly marked by the sudden drop of the barrier height, corresponding to a large increase of the HB spot area [Cer01a].
III-73
cathode
anode φ
Vg/2
E Vg/2
Fig. 6.20 Schematic drawing representing the band structure associated to the QPC spot. 3.4
8 Soft Breakdown
127I
(LET=60), Vrad = -3.25V Area = 4x10-4 cm2 7
3.0 Hard Breakdown
6
α (eV-1)
φ (eV)
3.2
2.8 5 2.6 4 107 108 109 Fluence (ions/cm2) Fig. 6.21 Extracted φ (open symbols) and α (solid symbols) versus fluence for a 3-nm capacitor irradiated with I ions and kept biased (Vg=-3.25V) during irradiation. 105
106
6.3.3. RSB dependence on applied bias during irradiation The RSB dependence on Eox,bias is quite different from that of RILC previously illustrated (see Fig 6.22a). After high LET Ag irradiation, RSB current is minimum at zero Eox,bias, while the positive value is always lower than the negative one. The bias applied during irradiation enhances the generation of RSB paths even in case of small oxide fields (3 MV/cm), and some correspondence may be found with SEGR behaviour, even though RSB appears even at zero oxide field, i. e. the RSB critical field is zero. After intermediated LET Ni irradiation, results are intermediate between RILC and RSB (Fig. 6.22b). RSB increases almost linearly with the ion fluence (Fig. 6.23), even though some fluctuations are observed, which were not detected for RILC. In fact, RSB current comes from the contribution of several RSB conductive spots, whose number linearly depends on the ion fluence, i. e., the number of ion hits, but the contribution of each ion hit to the gate leakage can be quite different. This means that the effect of a single ion hit on the leakage current is III-74
unpredictable, as it depends on the local number and organization of defects produced in the oxide, that control in turn the amount of current driven through the damaged oxide spot. 21
400
Negative current Positive current
18
| Ie (nA) |
| |e (nA) |
300
200
15
100
0
Negative current Positive current
12 9
-3
-1.5 E ox,bias
0 (MV/cm)
1.5
6
3
-3
-2
-1 0 1 Eox,bias (MV/cm)
2
3
(b)
(a)
Fig. 6.22. Excess gate current for different oxide fields during Ag irradiation (a) and Ni irradiation (b); tox = 3nm.
10-7 Ie=K·Φ
Vg,bias=1.33 V
|Ie| (A)
10-8
Vg,bias=2.2 V
10-9 10-10 Vg,bias=-0.92 V
10-11
Vg,bias=-2.28 V Vg,bias=-3.1 V
10-12 105
106
Fluence (ions/cm2)
107
Fig. 6.23 RSB current (read at Vg=-1.8V) measured in 3-nm capacitors after irradiation with 256MeV I ions as a function of the ion fluence for different gate bias values applied during irradiation.
6.3.4. Temperature dependence of RSB The temperature dependence of RSB in the Ig-Vg curves of a 4-nm oxide capacitor before and after irradiation with 32⋅109 Ag ions/cm2, is illustrated in Fig. 6.24. Three measurements are shown taken at different temperatures after irradiation, while the corresponding Ig-Vg characteristics before irradiation are plotted for comparison. In fresh devices the gate leakage III-75
current derives from direct tunneling for Vg<4 V, hence dominating the gate current in fresh devices under low supply voltages (VDD=2.5 – 3 V). Instead, Fowler-Nordheim tunneling dominates for Vg>4 V, when the Ig-Vg slope increases in Fig. 6.24. Being controlled by the direct tunneling conduction across a trapezoidal barrier, the fresh Ig-Vg characteristics are almost independent on temperature and the different curves almost overlap in Fig. 6.24. The temperature effect is larger on the RSB current, which decreases at low temperature but it is still orders of magnitude larger than in non-irradiated devices. The temperature dependence of the RSB current is illustrated by plotting the Ig,RSB, measured at a fixed Vg = ±3V in an Arrhenius plot (see Fig. 6.25). The IgRSB(T) data can be fitted neither by using a straight exponential law nor by the relation:
(
I = A ⋅ exp − B ⋅ T −1 4
)
(6.6)
previously proposed by Okada et al. in their variable-range-hopping model of SB [Oka97]. Instead, the gate current can be (at least empirically) modeled as the superposition of two contributions, corresponding to the dashed lines in Fig. 6.25: IgRSB(T) = IgRSB,0 + I0⋅exp(-Ea/kT)
(6.7)
IgRSB,0 is a temperature independent term, while the second term is the temperaturedependent component following the usual exponential law for thermal activation, with an activation energy Ea = 0.057 ± 0.005 eV independent on the measurement gate voltage, as shown in Fig. 6.26a for negative bias [Cer01b]. For comparison, a relation similar to (6.7) was previously introduced to describe the SILC temperature dependence [Sae95]. In that work, the Authors faced the problem of keeping the gate oxide at a constant electric field being SILC controlled by the oxide field and not directly by the gate voltage. In fact, for RSB it has been verified that not only IgRSB(T) but also its components IgRSB,0 and I0⋅exp(-Ea/kT) follow Eq.(6.5), i.e., the empirical power law of the SB current, which states that the current is controlled by the gate voltage. 10-6 10-7
Irradiated
Ig [A]
10-8 Fresh 10-9 10-10
T= 300 K T= 200 K
10-11
T= 100 K 10-12 1
2
3 4 5 Vg [V] Fig.6.24 Leakage current across 4-nm thick oxides before and after 1010 Ag ion/cm2 irradiation, measured at different temperatures.
III-76
10-7
300 250 200
T [K] 150
100 Vg= 3V
Ig [A]
Vg= -3V
IgT Ig0 10-8 30
60 90 1/kT [eV-1]
120
Fig. 6.25. RSB current measured at Vg = ±3V as a function of temperature in 4-nm oxides. The experimental data are well fitted by solid lines representing Eq.(6.7). Dashed curves correspond to the temperature dependent and independent current components.
T [K] 10-6
300 250 200
150 -3V
100 -3.5V
10-6 10-7 Ig, Ig0 [A]
IgT [A]
10-8 10-9
10-8 10-9
10-10 10-11 10-12 30
Filled, Vg>0 Open, Vg<0
-4V
10-7
Ig (@300K)
10-10 -1.5V
-2V
Ig0
-2.5V
60 90 -1 1/kT [eV ]
10-11
1
120
(a)
2 3 |Vg| [V]
4
5
(b)
Fig. 6.26 a) Temperature dependent component of the RSB current (see Eq.(6.7)) measured at different Vg values as a function of temperature in 4-nm oxides. Experimental data are fitted by an Arrhenius relation. b) Total RSB current and its temperature independent component (see Eq.(6.7)) as a function of the gate voltage measured at room temperature in 4-nm oxides.
The low Ea value reflects the weak temperature dependence of the RSB current. In fact, the conduction mechanism is based on tunneling transport, either via a multi-trap path [Tom99] or through a quantum point injection [Sun00b, Mir99b, Cer01a]. Generally, tunneling-based phenomena show modest dependence on temperature. Even in that work on SILC [Sae5] a small activation energy was measured. Hence, the increase of the device temperature during normal operation will be accompanied by a limited increase of the RSB current. As an example of this III-77
relationship a RSB current of 1 µA at room temperature (300 K) reaches only 1.5 µA at 375K, in 4-nm oxides. The temperature-independent component IgRSB,0 has been plotted in Fig. 6.26b as a function of Vg for both positive and negative gate voltage polarities. The corresponding total gate current measured at 300K has been also plotted for comparison. Clearly, IgRSB,0 does not correspond to the leakage current of the fresh devices, which is much smaller than IgRSB,0, but is actually a fraction of the RSB leakage.
6.3.5. RSB current noise In Fig. 6.27 we have plotted the gate current measured in a 3-nm oxide after irradiation with 257 MeV I ions. The gate voltage applied during the measurement was Vg = -2.7V, and the sampling frequency was FS = 64Hz. The RSB current approximately behaves as a multi-level Random Telegraph Noise (RTN). Such fluctuations correspond to the activation/deactivation of conductive paths (inside the radiation induced weak spots) across the oxide, occurring after irradiation [Cer01b]. By focusing on a small portion of the gate current response a “small” RTN appears superimposed on the main “large” fluctuations (see inset of Fig. 6.27), pointing to the complex nature of the weak spots. Remarkably, the average current flowing across the oxide after irradiation is much larger than in a fresh device (see Fig. 6.24), indicating that despite the large fluctuations some regions in the oxide layer are irreversibly damaged permitting a large current to constantly flowing.
Ig [nA]
8.2
8
7.8
8.5
7.6 860 880 900 920 940 960 980 1000
Ig [nA]
Time [s]
8
7.5 0
200
400
600 Time [s]
800
1000
Fig. 6.27 Gate current measured at Vg=-2.7 V as a function of measurement time in a 3-nm oxide after 7·106 I ions/cm2. Sampling frequency was 64 Hz.
III-78
33
35 Ig [A]
32
30
31 30 29
Ig [nA]
25
28 11.2 11.3 11.4 11.5 11.6 Time [s]
20
14 13.5
10
Ig [nA]
15 (a) 7.5
8
8.5
9
9.5 10 10.5 11 Time [s]
11.5 12
13 12.5 12
8.8 8.9 9 9.1 9.2 9.3 Time [s]
Fig. 6.28 Gate current measured at Vg = -2.7 V as a function of measurement time in a 4-nm oxide after 7·106 I ions/cm2. Sampling frequency was 4 kHz.
Mixed “large” and “small” RTN fluctuations have been observed for different values of oxide thickness, radiation dose, measurement polarity, and sampling frequency. In Fig. 6.28 we have plotted the post-irradiation gate current measured in a 4-nm oxide at Vg=-2.7V and at a sampling frequency FS = 4 kHz. Noticeably, the RSB current is larger in 4-nm than in 3-nm oxides, due to the random nature of the RSB phenomenon. Also in the 4-nm oxide a clear multilevel RTN appears, characterized by “large” and “small” fluctuations, as found also in Fig. 28. The complex nature of the RTN noise is seen in Fig. 6.29, where we can easily detect 2 main groups of current levels: the low one is at Ig≈13nA (group A) and the high one is at Ig≈32nA (group B). The different RTN contributions are illustrated in Fig. 6.29, where we show the gate current probability distribution relative to the current signal plotted in Fig. 6.28. Each group (A and B) splits in several sub-levels (4 for A and 9 for B) proper of the “small” RTN. Noticeably, “small” fluctuations occur much more frequently than “large” ones, and both are usually attributed to an electron trapping/detrapping process. The correlation between switching frequency and fluctuation amplitude may help understanding the microscopic nature of the RSB spot. In fact, fast fluctuations can be attributed to electron trapping/detrapping in shallow traps, hence characterized by fast trapping/detrapping kinetics. On the contrary, deep traps could be responsible for the slow fluctuations due to their longer capturing and emitting time. Experiments show that the current fluctuations are either “slow and large” or “fast and small” [Cer01b]. This suggests that shallow electron traps should modify the conductance of the RSB spot much less than slow deep traps. In a simple view, deep traps could reside in a central region of the RSB spot, which can be effectively clogged by a trapped electron resulting in larger RSB current variations. Instead, shallow traps should be located peripherally with respect to the RSB spot, where their impact on the driven current is relatively modest. This trap distribution is also consistent with the recently proposed models for Soft Breakdown [Hou98b, Sun00b, Mir99a, Cer02a, Oka97]. In these models, the formation of a conductive path is related to the generation of a local cluster of deep traps (~3eV below the oxide conduction band), producing the Si/SiO2 barrier height drop to roughly zero-value. The conductance of this narrow conductive path can be well described by models such as Quantum Point Contact, percolation, or variable range hopping, originally proposed for the electrical stress induced Soft Breakdown [Hou98b, Sun00b, Mir99a, Cer01a, Oka97] and illustrated in section 3 of the present work. III-79
Probability distribution [A.U.]
1010 109
A
B
108 107 106 10
15
20
25
30
35
3
A
1 2
109 108 107 106 12
4
Probability distribution [A.U.]
Probability distribution [A.U.]
∆I [nA] 1010
109
B
4 5
2 1 3
108
78
6
9
107
13 14 29 31 33 ∆I [nA] ∆I [nA] Fig. 6.29 Probability distribution of the gate current shown in Fig. 6.28. The numbers marks the main current sampling points.
6.3.6. Temperature dependence of gate current noise In Figs. 6.30a and 6.30b we show the gate current measured at 300 K and 77 K, respectively, in the same irradiated device. The RSB exhibits a RTN behavior in both cases, but the switching frequency of the current noise decreases with the temperature. This result is in agreement with the role attributed in producing RTN to electron trapping/detrapping, which decreases at low temperature. Recently, discrete RTN has also been observed in the drain voltage of MOSFET’s (with 18-nm gate oxide) operating in strong inversion with a constant drain current [Scd00]. The authors attributed these RTN fluctuations to the trapping/detrapping at interface defects and found that trapping events are quite strongly activated by temperature. This seems consistent with RSB results: in fact, it is possible that these near-interfacial defects in thicker oxides (laying at approximately 2-3 nm from the interface [Fle92]) might have similar nature, i. e., similar trapping characteristics, to the “bulk” defects in oxides thinner than 4-5 nm. In Figs 6.30a and 6.30b the RSB current was measured at 2 different gate voltages, that is, Vg=-1.2 V and -2.6 V, respectively, aiming to keep similar RSB current values at different temperatures. In fact, the RSB current at 77 K was almost 3 orders of magnitude smaller than at 300 K and current fluctuations were almost undetectable at Vg=-1.2V. In that case, the electron-trapping rate on the RSB related defects was also reduced due the decrease of the electrons available for trapping, owing to the small gate current. Even though the switching frequency increases with the gate voltage, still it is much slower at 77 K than at 300 K, as illustrated also in Fig. 6.31 where the corresponding Power Spectral Density (PSD) is plotted at FS=64Hz and FS=4kHz. We observe a general decrease of the noise power and a leftward shift of the switching frequencies by decreasing the temperature. The power spectral density follows a 1/fα law in both curves with the same α coefficient. In general (as found in all irradiated samples), the exponent α is between 1 III-80
and 2, which derives from the superposition of some lorentzian curves, each of them describing a RTN with a particular switching frequency and amplitude [Kir89]. In particular, 3 lorentzian curves at 300 K and 2 lorentzian curves at 77 K are sufficient to obtain good agreement with experimental data. 5
4
4.6
Ig [nA]
Ig [nA]
4.8
4.4
3.9
4.2 4 0
40
80
120
3.8 0
160
40
Time [s]
80 Time [s]
120
160
(b)
(a)
6
2
Fig. 6.30 Gate current measured in a 3-nm oxide after 7·10 I ions/cm : a) at 300 K, Vg=-1.2V, FS=64Hz; b) at 77K, Vg=-2.6V, FS=64Hz.
-180
P.S.D [(A2/Hz)dB]
FS=64 Hz -200 FS=4 kHz -220
300K
77K -240 Instrumental limit
-260 10-2 Fig. 6.31
10-1
1 10 Frequency [Hz]
102
103
Power Spectral density of the RSB current in a 3-nm oxide at 77K and 300 K after 7·106 I ions/cm2.
6.3.7. Future issues for RSB and SEGR in space environments How much the radiation damaged gate oxide may affect the circuit reliability for digital VLSI applications has been recently discussed in detail [Mal01] (data relevant to RILC effects on floating gate memory devices will be not considered here, having been presented in section 5). With reference to the MOSFET electrical characteristics, the conventional effects related to RSB are the increased gate leakage and the increase in 1/f noise [Wei97], at least in components with III-81
relatively large gate area. The gate leakage associated to RSB produced on the average by a single ion track is usually too small to promulgate a digital circuit failure. Further, the flux of high LET ions in a quiet geosynchronous space environment is extremely low, so that the probability of producing RSB on a single MOSFET is correspondingly small. For this reason, it has been concluded that RSB is not an enhanced failure mode of significance for digital VLSI using advanced oxides or even alternative high-k dielectrics, where RSB was simply not observed to occur. In case of SEGR, concerns for its impact on the circuit reliability are high, even though it has been recently demonstrated that MOSFET’s may tolerate even HB without loosing their functionality [Kac02]. In Fig. 6.32 the critical SEGR field under exposure to 342-MeV ions for MOS capacitors with SiO2 and other dielectrics [Mal01]. In agreement with previous results [Joh98b, Sex98, Sex97], the SEGR critical field increases with scaling to thinner dielectrics, being lower than breakdown field required for electrical stress only (with the exception of ZrSiO). When presenting data in terms of the critical voltage needed for breakdown (see Fig. 6.33), the same authors [Mal01] were able to fit the HB voltage by using a power threshold model [Ala99], where it is assumed that a threshold power dissipation P (P=V2/R) controls the HB onset. Hence, the HB voltage should scale with the square root of the conductive path resistance R, which is proportional to the oxide thickness for a fixed ion LET, not only for SiO2 but also for the high-k alternative dielectrics considered in the figure. Noticeably, SEGR critical voltage data lay well over the power supply voltages predicted for the different CMOS circuit generations by the Technology Roadmap, suggesting that even radiation induced HB should not be a significant concern for space systems employing nextgeneration commercial integrated circuits operating at standard VDD levels. Even though these results indicate that radiation effects on ultra-thin oxides should not be a problem for deca-nanometer CMOS circuits as long as gate dielectric breakdown is considered, new issues are emerging that may rise new questions on the long term device reliability, as shown in the following parts of this section.
Fig. 6.32 Critical electric field to SEGR under 342-MeV Au irradiation for different gate oxides. Results for breakdown under voltage stress only are shown for comparison.
III-82
Fig. 6.33 SEGR voltage as a function of the oxide physical thickness for exposure to 342-MeV Au ions. The solid curve represents an empirical model based on a power threshold model for breakdown.
6.4. Radiation Induced Wear-Out In the two previous sections we showed that different leakage current can affect thin irradiated oxide. RILC and RSB represent the most important degradation phenomena affecting ultra-thin oxides. Both RILC and RSB are characterized by a current increase, which is much smaller than in Hard Breakdown (HB) regime. RILC and, mainly, RSB have been demonstrated not to be an enhanced failure mode of significance for digital Very Large Scale Integration (VLSI) [Wei97]. Those observations were based on the assumption that the device operation integrity is basically preserved owing to the small gate leakage, with few possible exceptions (such as floating gate memories or analog circuits). Further, the RSB probability appears extremely low in space missions. When considering long term device reliability radiation is not the only concern, as gate oxides are subjected to high electric fields during normal circuit operations. Oxide wear-out due to the applied oxide fields is usually investigated on large area MOS capacitors through accelerated electrical stresses at fields higher than those of normal device operation. The cumulative effect of ionizing radiation and accelerated electrical stresses has been considered a few times in literature [And95, Bro95, Kim95, Pac96, Sca97c], mainly for oxides irradiated with low Linear Energy Transfer (LET) radiation (γ-rays, electrons, X-rays). It was found that radiation damage does not significantly impact the oxide reliability parameters, such as time-tobreakdown and time-zero-breakdown, at least for relatively high oxide thickness’ (>12nm). In case of RILC, a modification due to irradiation was reported for the growth kinetics of the excess current during electrical stresses after γ-irradiation [Sca97c]. Only recently some works have been devoted to the combined effects of heavy ion irradiation and electrical stresses on ultra-thin oxides [Cer02b, Cer03b, Cho02]. In the following we present the results of electrical stresses on large area MOS capacitors previously irradiated with heavy ions, showing that oxide breakdown occurs faster in irradiated devices. III-83
Pre-irradiation 10 kGy (Si) 150 kGy (Si) 200 kGy (Si) 300 kGy (Si)
LN(-LN(1-F))
1
0
-1
-2
69
Co Gamma Irradiation tox = 3.2 nm, Vstress= - 5.0 V
-3 10
100
Time-to-Breakdown (s) Fig. 6.34 Weibull lifetime distribution of MOS capacitors subjected to constant voltage stress at Vstress=-5 V before and after gamma irradiation.
129
ln(ln(1/(1-F)))
1
Xe Irradiation, tox = 3.0 nm, Vstress = - 4.9 V
0
-1 Pre-irradiation 1 x 105 ions/cm2
-2
1 x 106 ions/cm2 1 x 107 ions/cm2
-3 1
10
100
1000
10000
Time-to-Breakdown (s) Fig. 6.35 Weibull lifetime distribution of MOS capacitors subjected to constant voltage stress at Vstress=-4.9 V before and after heavy ion irradiation.
III-84
10-7
After Irradiation + 400s CVS @ Vg=-2V
10-8 10-9
10-5
After irradiation: (1st)
10-10
Ig [A]
Ig [A]
10-4
(2nd,3rd)
10-11 10-12 10-13 10-14
0.5
1
1.5 Vg [V]
2
2.5
. . .
tox = 2.8 nm
10-11
A = 10-6 cm2 Vg =-2 V
fresh
0
10-6
10-12
3
0
500
1000
1500
Time [s]
(b)
(a)
Fig. 6.36 a) Ig-Vg curves before irradiation (fresh), after irradiation (1st, 2nd and 3rd measurements), after irradiation + CVS on a MOS capacitors with gate area=10-6cm2 and tox= 2.8nm. The radiation fluence was 107 I ions/cm2, i . e., approximately 10 ions hit the gate oxide. b) gate current during the CVS performed after irradiation in the device of Fig. 6.36a.
6.4.1. Experimental evidence of Radiation Induced Wear-Out Only recently some works have been devoted to study the combined effects of ionizing radiation and electrical stresses on ultra-thin oxides [Cer02b, Cer03b, Cho02, Sue02]. Low LET radiation, such as gamma rays from Co60, produce no detectable effect on the Time-ToBreakdown (TTB) measured during accelerated electrical stresses (CVS) after high dose irradiation, as shown in the cumulative failure (Weibull) plot of Fig. 6.34 [Sue02]. Similar results were observed in thick gate oxides (see section 4), as the radiation induced point defects in the gate oxide are not effective in promoting the development of a breakdown path. However, when oxides are exposed to heavy ions a dramatic decrease of TTB was measured in the Weibull plot (Fig. 6.35) due to the radiation induced damage in the oxide [Sue02]. In all irradiated devices an increase of the leakage current was also observed after irradiation, mainly after heavy ion exposure that lead to RSB in some cases. However, radiation effects may be even silent after irradiation, appearing only during a subsequent electrical stress, as illustrated by the Ig-Vg curves in Fig.6.36a before and after CVS at Vg=-2 V, i. e., close to the normal bias conditions VDD=1.8 V [Cer03b]. The device was hit by only 10 I ions on the gate oxide owing to the small gate area. Only the first Ig-Vg measurement taken immediately after irradiation exhibited a very unstable behavior featuring several jumps, whereas the second and the third measurements were stable, overlapping each other, and are very close to the fresh curve. In this case the effective damage induced by the ion irradiation is apparently negligible, since the current increase is very modest. The large instabilities featured by the first measurement could be related to an unstable cluster of oxide defects produced by irradiation, likely being the signature of a single ion induced localized weak spot. This cluster is stabilized by the current injected during the first measurement, as a consequence of some electron trapping or electron-hole recombination at the radiation induced oxide defects. The electrical stress on this device demonstrates that the rearrangement of the ion damaged oxide region after the first measurement does not restore the pre-irradiation condition. In fact, CVS at Vg=-2V produced SB in just 400s (see Fig. 6.36b). For comparison, CVS at Vg=-2V III-85
produced no measurable effect on Ig-Vg curves in fresh (unirradiated) samples even after 105106s. Noticeably, this result shows that even a single ion hit may effectively reduce the oxide lifetime when considering SB or HB as the failure criterion. SB and HB may appear in parallel on irradiated samples, as indicated by curves A and B, respectively, in Fig. 6.37a. The abrupt increase of the gate current (marked by A) in Fig. 6.37b indicates the formation of a single SB path across the oxide, produced even in this case in a short time (1800s) and at low CVS voltage (Vg=-2V). By applying a second CVS at Vg=-3.5V the same capacitor underwent HB after only 360s (marker B in Fig. 6.37c). Remarkably, a CVS at Vg=-4.5V applied to unirradiated devices needed more than 105s to generate a breakdown event. That the first SB event was not the precursor of the subsequent HB has been demonstrated by using the Light Emission Microscopy (LEM) technique on some devices with poly-Si gate without any overlying metal [Cer03b]. Fig. 6.38 shows the evolution of the SB and HB spot of the sample of Fig. 6.37 as observed by the LEM. After irradiation (frame (a)) no light spot appeared, indicating that RSB conduction took place across several weak spots, each being too weak to be observed by LEM. The first SB occurred during CVS (mark A in Figs. 6.37a and 6.37b) can be clearly observed in the frame (b) and zoom (A) of Fig. 6.38. The subsequent HB occurred on a different position from SB, as shown in frame (c) and zoom (B) of Fig. 6.38, indicating that SB and HB are independent phenomena, as previously proposed [Bru00, Mon01]. After CVS the gate current flows through preferential paths generated by the electrical stress itself in those regions more damaged by heavy ions.
20
10-3 10-5
B
SB (rad. + 4000s CVS @ Vg=-2V)
10-6 10-7
After Irradiation
10-8
A
10-10
400
fresh
10-11 0.5
1
1.5
SB onset 0
1000
2000 Time [s]
3000
4000
(b)
500
0
A
10
10-9
10-12
Vg = -2V
15
5
Ig [nA]
Ig [A]
Ig [nA]
HB (rad. + 360s CVS @ Vg=-3.5V)
10-4
2
2.5
3
Vg = -3.5V
HB onset
B
300 200
Vg [V] (a)
0
100
200 Time [s]
(c)
300
400
Fig. 6.37 a)Ig-Vg curves before (fresh) and after irradiation with 107 I ions/cm2, and after two subsequent CVS’s (curves A and B) in a MOS capacitors with gate area = 10-3cm2 and tox = 2.8nm. b) Gate current during CVS at Vg=-2V for the same irradiated device of Fig. 6.37a; c) Gate current during the CVS at Vg=-3.5V, for the same device of Figs. 6.37a and 6.37b.
III-86
B 50 µm
A 50 µm
100 µm
(a)
(b)
(c)
Fig. 6.38 Light Emission Microscope observations of the device of Fig. 6.37 (reverse images) taken by biasing the capacitors at Vg=-1V The white areas corresponds to the gate regions, divided in 16 rectangular sections, while the dark lines are proper of isolation: a) immediately after irradiation; b) after the 1st CVS at Vg=2V; c) after the 2nd CVS at Vg=-3.5V. Dark spots A and B are associated to the gate current increase observed in curves A (SB) and B (HB) in Fig. 6.37, respectively.
1
2
After 10 s After 130 s
3
After 270 s
Fig. 6.39 Opening of two Soft Breakdown spots after the occurrence of Hard Breakdown in a device irradiated with 107 I ions/cm2 during CVS at Vg=-4V (reverse image). The three spots are marked in order of appearance, as indicated by the time values measured from the CVS starting. Area=10-2 cm2, tox=2.8nm.
SB events may occur even after HB as shown in Fig. 6.39 in another irradiated sample, where the three light spots have been numbered in order of appearance during CVS at Vg=-4V. This behavior is peculiar to irradiated oxides. In fact, the high HB current (>1mA) flowing across the breakdown path produces a voltage drop in the Si-substrate and polysilicon gate, reducing both the oxide field and the SB probability in unirradiated devices. On the contrary, in irradiated devices SB events can easily occur even at reduced gate voltage as seen in Figs. 6.37 and 6.38 and may occur in parallel to HB. III-87
While SEGR is not sensitive to previous radiation damage [Sex98, Joh98b], the CVS breakdown is. When the oxide structure has been effectively weakened by ion irradiation, radiation induced defects can be effective seeds of breakdown phenomena produced even by relatively low-field electrical stresses, as schematically illustrated in Fig. 6.40 [Cho02]. Remarkably, the same authors have developed a detailed model to study the oxide latent damage produced by heavy ions and the corresponding defect generation yield for different ions, demonstrating that the main factor controlling the generation of oxide defects is the ion LET, that will be discussed from the CVS viewpoint in the next paragraph.
Fig. 6.40 Schematic picture showing the generation of defective cells and the breakdown condition due to the electrical stress in fresh and high-LET ion irradiated films: N is the total number of column, n is the number of cells in a column, and M is the total number of column that contain radiation-induced defective cells.
6.4.2. LET dependence of Radiation Induced Wear-Out The dependence of the oxide degradation from the heavy ion LET coefficient has been studied for different ions at a fluence of 6.5⋅107 ions/cm2 [Cer03b] and is clearly illustrated in Figs. 6.41a and 6.41b. Irradiated and unirradiated samples were submitted to a Staircase Voltage Stress (SVS) starting at Vg=1V for 1000s, the voltage being then increased by ∆Vg=0.5V for another 1000 s step, until HB occurrence.
III-88
2 Vg = 3.5V
I Au
Ig [mA]
1.5
1
0.5 5000
Fresh, Si, Br
5200
5400 5600 Tstress [s] (a)
8
6000
Vg = 4V
7 Ig [mA]
5800
Br
6 Si 5 Fresh
4 3 6000
6200
6400
6600
6800
7000
Tstress [s] (b) Fig. 6.41 Gate current evolution for few selected devices during: a) the 5th step of SVS for 311 MeV Au and 276 MeV I irradiated samples (Tstress = 5000s - 6000s, Vg,stress = 3.5V); b) the 6th step of SVS for 241 MeV Br, 257 MeV Si, and unirradiated samples (Tstress = 6000s - 7000s, Vg,stress = 4V).
Differences between irradiated and fresh devices grow with the LET, owing to the amount of oxide defects produced by each ion (See Fig. 6.41). The progressive degradation of the Au and I irradiated oxides already after 5000 s can be attributed either to the enlargement of a single weak spot driving most of current [Mon01], or to the sequential opening of several small weak spots [Bru00], which appears to be more likely. In case of a single spot some SB-like signatures are expected, such as discrete current jumps and random telegraph signal noise (seen instead for Br and Si in Fig. 6.41b), which are not observed [Bri96, Cer01b, Cer02a, Dep96]. Heavy ion irradiation can instead enhance the defect production during electrical stresses in several weak points corresponding to the ion hits (65000 ions hit the oxide surface), so that electrons injected during SVS require less energy to generate defects and produce some SB leakage paths. III-89
6.5. Radiation Effect on MOSFET Traditionally, oxide Hard Breakdown (and to a less certain degree, Soft Breakdown) marks the end of the MOSFET lifetime [Wei97, Pom00]. The increase of the gate current, which is quite modest in the RSB regime (1nA - 1µA), produces a small increase of the corresponding power consumption in the broken MOSFET (~1µW or less). In most analog and digital applications, where the power budget is hundreds mW or more, such an increase is relatively small and does not significantly affect the total power consumption, unless many breakdown events take place in different transistors. On the other hand, the large noise characterising the RSB current [Cer01b] could have a deleterious impact on the signal/noise ratio of analog circuits, even when the power consumption does not exceed the circuit specifications. Digital applications appear much more robust to RSB noise, as long as it remains smaller than the digital gate noise margins. Some authors have stated that threshold voltage and transconductance do not significantly change after Soft Breakdown (SB), so that the soft broken transistors can be still switched on and off, at least in those devices with large aspect ratio [Wei97, Pom00]. Radiation (but also electrical) stresses are often performed on large area MOS capacitors, to address the reliability problem over gate areas comparable to those of large chips. Very few results are available on the effect of ionizing radiation (and also electrical stresses) on MOSFET’s with ultra-thin gate oxide and small W/L aspect ratio, proper of contemporary CMOS technologies. Recent results are rising the issue that only tests on small area devices are significant to evaluate the impact of the oxide degradation on the MOSFET electrical characteristics at least in case of minimum size devices or so, as we’ll show in the following. We consider here two MOSFETs with gate area A=3µm2 and aspect ratio W/L=0.3µm/10µm or W/L= 10µm/0.3µm (drawn), irradiated with 65⋅106 I ions/cm2 [Cer03b]. In this case only 1 or 2 ions hit the gate oxide surface owing to the small gate area. No increase in the gate leakage current is observed after irradiation independent on the transistor aspect ratio W/L (Figs. 6.42a and 6.42b), as expected. Figs. 6.43 and 6.44 show the effect of heavy ion irradiation on the drain current of the same MOSFETs of Fig. 6.42. In the W/L=10µm/0.3µm device gm slightly decreases (Fig. 6.43a), with an almost negligible variation of the drain saturation current (Fig. 6.43b). Even the threshold voltage and the subthreshold drain current are practically unchanged after irradiation, as illustrated in Fig. 6.43c. But when W/L = 0.3µm/10µm both transconductance and drain saturation current collapse as shown in Figs. 6.44a and 6.44b, respectively. Large variations also appear in the logarithmic Ids-Vgs plot of Fig. 6.44c. For Vgs>0.1-0.2V the decrease of drain current is much larger than in the case of the large W/L transistor of Fig. 6.43c. In addition only a 20-30mV shift of the threshold voltage is observed after irradiation, accompanied by a large increase of the subthreshold current for Vgs<0.1V (4-5 decades with respect to the fresh device). These results point to the formation of a damaged oxide region produced by the ions striking the gate oxide. The current peak appearing for Vgs near 0V (Fig. 6.44c) is similar to the excess current of a gated diode after irradiation, clearly indicating the presence of Si/SiO2 interface traps under the gate oxide. Remarkably, this effect is observed even when a single ion hits the gate oxide without giving rise to oxide breakdown or SEGR phenomena, as shown in Fig. 6.42. The small positive shift of the MOSFET threshold voltage (~20-30mV, Figs. 6.43c and 6.46c) is an evidence that oxide trapped charge is negligible. Furthermore, the positive charge trapping usually observed in thick oxide and commonly addressed as the main cause of MOSFET failure after irradiation can not give rise of this phenomena, being the threshold shift opposite to that generated by a positive trapped charge. III-90
10-11
10-11 W/L=0.3µm/10µm 10-12
10-13
10-13
Ig [A]
Ig [A]
W/L=10µm/0.3µm 10-12
10-14 10-15
fresh
10-14 10-15
irradiated 10-16
0
0.5 Vg [V] (a)
1
10-16 0
1.5
fresh irradiated 0.5 Vg [V] (b)
1
1.5
Fig. 6.42 Ig-Vg curves taken before and after irradiation with 65⋅106 I ions/cm2 in two MOSFETs with the same gate area A = 3µm2 and oxide thickness tox = 2.5 nm and different aspect ratios: a) W/L = 10µm/0.3µm; b) W/L = 0.3µm/10µm. Approximately 1-2 ions hit the gate oxide.
The physical mechanism controlling the drain current collapse has no impact on the gate leakage current. In fact, the defect distribution is not sufficient to drive a substantial gate current (Fig. 6.42), but high enough to pinch the channel below it. The radiation induced defects form no RSB conductive path but must be distributed over a channel portion with dimension comparable with the transistor W (0.25-0.3µm). Hence, the ion microdose effect spans over an oxide region much wider than the electron-hole generation volume of a single ion in the oxide (3-4nm in radius), but similar to its size in Si (around 100nm). This suggests that electron-hole pairs generated in the Si substrate close to the oxide interface may effectively contribute to the defect generation in the oxide layer, for instance by ionizing the Hydrogen atoms passivating the oxide interface defects. These results demonstrate that a single heavy ion can significantly reduce the MOSFET drive current capability in small W devices, as illustrated in the drawing of Fig. 6.45. In very narrow (small aspect ratio) MOSFET’s the damaged oxide region may span over a large portion of the gate width, effectively hampering the channel formation and increasing the effective channel resistance. In large W devices, this effect becomes less important as W becomes larger than the damaged region. All these considerations lead to the conclusion that a MOSFET with small W may fail due to a single ion hit producing a collapse of the drain current well before the oxide breakdown condition is reached. RSB or SEGR may occur a long time after the device has lost most of its current driving capability and is, therefore, failed. In this case the device lifetime cannot be evaluated by considering the breakdown onset but, instead, its sensitivity to microdose effects such as those produced by high LET particles. Remarkably, the effect we measured must not be confused with the well-known single-event microdose effect observed by Oldham and McGarrity [Old81] in thick gate oxides and reported in several subsequent works. In that case, the ion induced microdose effect produced a localized trapping of positive charge, leading to increased drain leakage, which is the opposite of these experimental observations.
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1.0
fresh
gm [x10-3 Ω-1]
0.8
(a)
0.6 0.4
Irradiated
0.2 Vds=100mV
0 0
0.5
1
1.5
Vgs [V]
2.5 fresh 2.0 Ids [mA]
(b)
Irradiated
1.5 1.0 0.5 0 0
Vgs=1.2V 0.5
Vds [V]
1
1.5
10-3 10-4 10-5
(c)
Ids [A]
10-6 10-7
fresh
10-8
Irradiated
10-9 10-10 10-11 0
Vds=100mV 0.5
1
1.5
Vgs [V] Fig. 6.43 a) MOSFET transconductance (gm) as a function of gate-source voltage (Vgs) measured in the device of Fig. 6.42a with W/L=10µm/0.3µm, before and after irradiation with 65⋅106 I ions/cm2. b) Drain current (Ids) as a function of drain-source voltage (Vds) measured in to the same device of Fig. 6.42a. c) Subthreshold drain current (Ids) as a function of gate-source voltage (Vgs) measured in the same device of Fig. 6.42a
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1.0
Vds=100mV
gm [x10-6 Ω-1]
0.8 fresh
(a)
0.6 0.4 0.2
Irradiated
0 0
0.5
1
1.5
Vgs [V]
2.5 fresh
Ids [µA]
2.0
(b)
Irradiated
1.5 1.0 0.5 0
Vgs=1.2V 0
0.5
Vds [V]
1
1.5
10-5 10-6 10-7
(c)
Ids [A]
10-8 10-9
fresh
10-10
Irradiated
10-11 10-12 0
Vds=100mV 0.5
1
1.5
Vgs [V] Fig. 6.43 a) MOSFET transconductance (gm) as a function of gate-source voltage (Vgs) measured in the same device of Fig. 6.42b with W/L=0.3µm/10µm, before and after irradiation with 65⋅106 I ions/cm2. b) Drain current (Ids) as a function of drain-source voltage (Vds) measured in the same device of Fig. 6.42b, before and after irradiation with 65⋅106 I ions/cm2. c) Subthreshold drain current (Ids) as a function of gate-source voltage (Vgs) measured in the same device of Fig. 6.42c, before and after irradiation with 65⋅106 I ions/cm2.
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Large Aspect Ratio
Source
Small Aspect Ratio
Ion hit
Drain Channel
Drain Channel
Source
Fig. 6.47 Schematic picture describing how channel reduction produced by the oxide damage induced by a single ion hit (dark grey circle) depends on the transistor aspect ratio.
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7. Conclusions
In this part of the NSREC2003 Short Courses we have discussed the main issues related to radiation effects on gate oxides of MOS devices of contemporary CMOS technologies. Such problems due to radiation damage in thick oxides of older generations, as trapping of positive charge and interface state generation, may affect only the field oxide of CMOS circuits fabricated with aggressive deep-submicron technologies, while they do not appear in the thin gate oxides. In fact, any positive trapped charge would be rapidly neutralized by electrons due to their high tunnelling probability, owing to the low thickness of the dielectric layer, while interface states are not effectively generated. In this way MOSFET’s with ultra-thin gate oxides may show high tolerance to total ionizing dose, with minor shifts of the main transistor characteristics for doses of several Mrad’s. The main problems due to radiation damage to gate oxides reported in the last years concern the development of parasitic leakage paths through the oxide, along the defects generated by the ionizing particles. Different current types have been observed, with different intensities and impacts on the device electrical performance. The intensity of this leakage current may be very small, as in case of the RILC or the multitrap tunnelling current in tunnel oxides of floating gate memories, such as Flash or EEPROM. Yet, in those devices the loss of few thousands electrons may produce the irreversible corruption of the stored bit. Such charge loss from the floating gate may occur during the transient following the impact of a single ion on the memory cell, and continue during the following weeks and months. The present level of basic knowledge of the radiation effects on thin oxides is not sufficient to justify all the observed experimental data relative to the device transient response, encouraging the study of the radiation effects on thin oxides even from a basic viewpoint. Moreover, the retention characteristics of memory cells may be hampered also by the long term discharge from the floating gate along the ion generated defects in the oxide, which may occur even after subsequent erase/write cycles of the irradiated cells. Radiation effects may affect even more severely the floating gate memory reliability on the next memory generations, facing the reduction of the cell size with a consequent decrease of the stored charge in the floating gates. Memory cells with 2 or more bits per cell will be even more sensitive to single effects due to the reduced noise margin, while the sensitivity of different architectures (such as NAND vs. NOR) has still to be tested. New non-volatile memories under development, such as MRAM, FeRAM, or chalcogenide-based, appear in principle to offer higher levels of tolerance to radiation damage in comparison with floating gate devices, and could be of high interest for future applications in radiation harsh environments. On the other side, the gate leakage current may be very high as in case of SEGR. Usually, the gate oxide Hard Breakdown is considered as a true life time killer of MOSFET’s. The probability of occurrence of a HB event is fortunately controlled also by the applied voltage, III-95
which is scaling down owing to the continuous shrinking of the device dimensions. In this direction, recent results have shown that the expected VDD values should be low enough to grant high life-time expectations in future CMOS devices subjected to the space radiation. Leakage currents with intermediate intensity between RILC and SEGR HB have been observed as a product of single heavy ion strikes (RSB), but they appear tolerable in many digital circuits, their role in analog applications having been not investigated yet. Even though the gate oxide thickness reduction has played a positive role in enhancing its resistance to total dose radiation, emerging experimental evidence is pointing to new microdose effects occurring in MOSFET’s with small W/L dimensions and ultra-thin gate oxides that can produce a dramatic collapse of the transistor current driving capability. These results indicate that testing of large area MOS capacitors or transistors cannot be considered as a viable way to verify the real impact of radiation damage on scaled devices, which should be instead directly studied on the small size transistors. Interestingly, while microdose effects proper of a single heavy ion have typically affected a small part of the MOSFET channel in old relaxed geometries, in decananometer devices a single ion may affect the whole gate area of a few minimum size transistors, rising new challenging questions on the impact of single events in future CMOS circuits. Finally, SiO2 seems ready for retirement for what concerns future CMOS circuits, its thickness being approaching the atomic size. Many candidates are currently under study as gate dielectric material replacements. First radiation studies on these new high-k materials produced at laboratory level have presented encouraging results, to be confirmed by future works on process level materials. However, when silicon foundries will actually decide to replace the old SiO2 with some new material on the CMOS production lines is not clear yet.
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2003 IEEE NSREC Short Course
Section IV
HOW DEVICE SCALING AFFECTS SINGLE EVENT EFFECTS SENSITIVITY
Timothy R. Oldham NASA GSFC/QSS Group, Inc.
Scaling and Single Event Effects (SEE) Sensitivity Timothy R. Oldham NASA GSFC/QSS Group, Inc. NASA/GSFC Radiation Effects & Analysis Group 1.0 Introduction 1.1 Background—Scaling and the Limits of Scaling 1.2 Basic Definitions and Concepts 2.0 Basic Mechanisms 2.1 Charge deposition—track structure effects 2.2 Recombination 2.3 Charge transport and collection—funneling 3.0 Device and Circuit Effects 3.1 Upset 3.1.1 DRAMs 3.1.2 SRAMS 3.1.3 Commercial Industry Hardening 3.2 Latch-up 3.3 Snap-back 3.4 Burn-out 3.5 Gate Rupture 3.6 Stuck Bits 3.6.1 Micro-dose—gate, field oxides 3.6.2 Micro-damage—track formation 3.7 Single Event Transients 3.8 Hard/Soft Breakdown 4.0 Software Solutions 4.1 Error correction 4.2 Built-in Self Test (BIST) 5.0 Conclusion
IV-1
1.0 Introduction 1.1 Background—Scaling and the Limits of Scaling The very existence of Single Event Effects (SEE) is a consequence of scaling. Longtime NSREC attendees can remember when there were no SEE, because device sizes had not been scaled down enough for a single particle to have any detectable effect. By scaling, of course, we mean the consistent reduction in the size of electronic devices, which has been a hallmark of the semiconductor industry. Scaling is normally said to be governed by Moore’s Law.1,2 Originally proposed in 1965, Moore’s Law stated that the number of transistors on a chip would double every year for the next ten years. The data available to Moore in 1965 and his original prediction are shown in Fig 1.1 Moore also discussed the cost of an integrated circuit as a function of complexity, shown in Fig. 2. The point was that adding components to a chip reduced the cost per component up to some point in any given year. Beyond that point, the cost per component started to rise again because of poor yields. In any given year, cost of the circuit as a function of number of components was a u-shaped curve, where the cost dropped from year to year, and the minimum cost fell at higher component counts each year. In 1965, the lowest cost per transistor was for circuits with about 50 transistors. He predicted that the minimum cost circuits would be at about 65000 transistors by 1975, and that the chips would occupy about one quarter of a square inch.
Figure 1. Moore’s original prediction—the number of transistors per chip doubling every year for ten years, 1965 to 1975.1
IV-2
Figure 2. Moore’s analysis of the cost per transistor by year, from 1965. He predicted that by 1975, the lowest cost per transistor would be achieved for chips at about the 64K level.1 In 1975, Moore published another paper discussing both the original prediction, and what had actually happened.2 The main result is shown in Fig. 3, where the data fits the prediction remarkably well. He also analyzed three factors, which contributed to the increasing integration of complex circuits, shown in Fig. 4. From 1959 to 1975, the number of transistors on the largest chips had increased from one to about 64K. First, during the same period, the area of the largest chips had increased by a factor of about 20. Second, the square of the minimum feature size had decreased by about a factor of 32 in that period. (The earliest integrated circuits, in 1961, had line-widths of about 25 µm, which was reduced below about 5 µm by 1975.) The third factor was what Moore called “device and circuit cleverness,” which accounted for the remaining factor of 100, making it the largest of the three factors. By device and circuit cleverness, Moore meant that less space between transistors was used for isolation structures and metal interconnects each year, allowing more transistors to be added in any given area. For example, running metal interconnects over the top of active devices, rather than between them, allowed a larger fraction of the total area to be devoted to active devices. Moore predicted, in the 1975 paper, that the progress due to device and circuit cleverness would not continue at the same rate in the future, although he expected increasing chip area and reduced device feature size to continue to follow the same trends. Therefore, the doubling period should increase, perhaps (he said) to two years, instead of one year. Actual experience since then has been that the number of transistors on a chip really doubles about every eighteen months.
IV-3
Figure 3. Comparison of actual data with Moore’s original prediction.2
Figure 4. Moore’s analysis of the factors contributing to the increased complexity of the most advanced chips, increased die size, reduced feature size, and device and circuit cleverness. Device and circuit factor was the largest of the three factors.2
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Scaling of MOS transistors has been reduced almost to following a recipe. Dennard et al., in 1974, introduced a dimensionless scaling constant, which they called κ. Each linear dimension was reduced by a factor of κ, and the doping levels had to be increased by a factor of κ, to shrink the device area by κ2. Then, to maintain constant fields, the applied voltage had to also be reduced by a factor of κ. In the example they discussed, they described how to shrink a 5 µm device to 1 µm (κ=5), which is illustrated in Fig. 5. This is the origin of the term scaling—each dimension scaled by the same factor. Since the industry was generally not willing to reduce power supply voltages that quickly, constant fields were not really maintained, but modified scaling based on Dennard’s recipe has been followed for many years Dennard and others have published several other papers in later years, extending their original work, most recently discussing devices down to 25 nm.3-7 Although bipolar devices have also been greatly reduced in size during this period, there is not a simple recipe for scaling bipolar devices. 3
Figure 5. Scaling recipe for CMOS, after Dennard.3 Each dimension is reduced by the same scale factor, κ, in each generation of technology. Scaling has been institutionalized to the point that the Semiconductor Industry Association (SIA) maintains the International Technology Roadmap for Semiconductors (ITRS), which is basically a guide to scaling.8 The roadmap projects technology development for the next fifteen years, including integration levels, feature size, speed, power, and many other things. . Normally, 1/κ is about 0.7 in scaling from any given technology generation to the next. The ITRS also discusses in some detail the technical barriers, which must be overcome in order to continue following Moore’s Law. Technical barriers for which there is no known solution, are coded in red, and the amount of red in the charts has tended to increase each year. An example of a “red brick wall chart” is shown in Fig. 6. This chart deals with particulate control, and says there is no known method for controlling particulates, which will be adequate for the requirements of 2006. Even so, the industry expects scaling as we have known it, to continue for several more years—solutions for these problems are expected to be found when they are needed. More important, the IV-5
industry expects two of the main consequences of scaling to continue as well. First, the SIA assumes the cost per function will continue to decline by its historic average, 25% per year. Second, as a result, the market for integrated circuits will continue to grow by its historic average, 17% per year. The ITRS is revised every year, with major revisions in odd numbered years.
Figure 6. Red Brick Wall Chart , from the ITRS,8 all red starting in 2006. The importance of scaling in the semiconductor industry has spawned a significant subsidiary industry—the writing of papers predicting the end of scaling, or discussing the limits of scaling. As a result, the literature is littered with erroneous predictions that feature sizes would not be reduced beyond some point because of some perceived technical barrier. A summary of early work of this sort was presented by Folberth and Bleher,9 and is summarized in Fig 7. One can see that the early predictions of the minimum device size differ by four orders of magnitude, depending on the author. The first prediction, by IV-6
Swanson10 and Landauer,11 is not specific to digital semiconductor circuits, but rather refers to any type of storage device. These authors argue that any storage element containing less than about 100 atoms will be unstable because of random thermal agitation. Certainly, when the energy to switch a memory element approaches kT, a fundamental limit will have been reached. Devices containing only 100 atoms were so far beyond the actual state of the art at the time, that the work of Swanson and Landauer attracted relatively little attention. Indeed, it is still beyond the current state of the art, and in fact, also beyond the end of the current ITRS, which projects to 2016. Therefore, this prediction will not be contradicted by experiment in the foreseeable future.
Figure 7. Summary of early predictions of the end of scaling.9 Expert predictions differed by four orders of magnitude. The second prediction of the limits of scaling was by Wallmark and Marcus, in 1962, in a paper familiar to many NSREC attendees.12 They concluded “the minimum device size under reasonable conditions is approximately (10 µm)3, which is not far from devices now in the planning stage and within reach of existing techniques. It is within a factor of 2-5 of the dimensions of the active region of many devices of today.” While this prediction seems humorous today, the fact is that Wallmark and Marcus reached it because they anticipated Single Event Effects (SEE) before they were observed. They argued that ionization from sea level cosmic rays would render devices unreliable at smaller feature sizes. They also analyzed the effects of naturally occurring background radiation (the so-called alpha particle problem), the effects of heat generation, the effects of fluctuation in doping levels, and other things. These results are summarized in Fig 8. Because they anticipated these problems IV-7
before they were observed, one could argue that Wallmark and Marcus were prophets, despite their incorrect prediction. The mistake they made was in assuming that once SEE was observed, nothing could be done about it.
Figure 8. Wallmark and Marcus prediction that sea-level cosmic rays would render devices unreliable below 10 µm feature size.12
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About ten years later, in 1972, Honeisen and Mead presented two papers on fundamental limits in microelectronics.13, 14 They argued that the limit for dynamic MOS transistors would be at about 107 transistors per chip, which they predicted would be reached around 1980, as in Fig 9. They analyzed many potentially limiting reliability problems (power dissipation, metal electro-migration, substrate doping fluctuations, substrate breakdown, punch-through, and gate oxide breakdown). They concluded that gate oxide breakdown was the most severe problem, the one that would ultimately limit scaling. In their analysis, they considered 0.25 µm transistors with 7.2 nm gate oxides and a 1-V power supply. Perhaps the problem was that 7.2 nm oxides, grown in 1972 by graduate students, really weren’t very reliable.
Figure 9. Honeisen and Mead prediction of the limits of scaling,13 due to gate oxide reliability, at about 107 transistors per chip, in 1980. Keyes, in a series of papers, has considered limiting factors for microelectronics, concluding that the ability to dissipate power will limit miniaturization.15-17 Wisely, he did not specify a limiting feature size. A good, and much more recent, discussion of physical limits in microelectronics has been presented by Plummer and Griffin,18 who discuss difficult problems that require solutions if the ITRS is to be met. But in the end, they also say that solutions will probably be found. For example, gate oxide thickness scaling of pure SiO2 cannot continue beyond 11.5 nm, which is close to the present state-of-the-art, because of direct tunneling current, IV-9
which increases power dissipation unacceptably and degrades oxide reliability. Therefore, research on alternative gate dielectrics is proceeding, and it has to succeed. Similarly, gate threshold voltage has to be reduced as power supplies are reduced, in order to maintain current drive, and switching speed. But the threshold voltage also has to be significantly above zero to minimize leakage current and power dissipation. For these reasons, the acceptable range of threshold voltages is being squeezed from both sides. The need for very shallow, highly doped junctions is another example. The concentration of dopants is approaching the solubility limits in Si, on the one hand. But on the other hand, shallow implants necessary to reach these concentrations also require high temperature annealing steps to repair implant damage. The high temperature annealing steps also allow dopants to diffuse away, reducing concentrations. However, Plummer and Griffin conclude that solutions for these and other problems will probably be found, “because of the enormous economic incentive to continue density and performance improvements.” In other words, when billions of dollars in profits depend on overcoming specific technical barriers, technologists have historically been highly motivated, and amazingly resourceful. The profitability of the semiconductor industry is what has driven the industry to stay with Moore’s Law. However, Moore, himself, noted in 1979, that (even then) most Intel customers did not require and did not buy products approaching the performance limits of Moore’s Law.19 Although the ITRS assumes the industry will continue its historic growth pattern, there is some indication that the growth of the industry will slow down soon. The reason was pointed out by Myers.20 The market for finished electronic products (TV sets, computers, cell phones, etc.) has historically grown at about seven percent CAGR (composite average growth rate), which is at least twice the growth of the economy as a whole, but much less than the chip industry, which has had a CAGR of about 17% since at least 1960. The percentage of the finished product due to the chip content had increased from about two percent in 1969 to 14% in 1996. The point is that the value of the chips cannot exceed the value of the end item they are built into, so the growth curve for the chip industry will have to change slope, and follow the curve for the whole electronics industry at some point. Myers projected this change would happen between 2000 and 2010—perhaps about now. If the semiconductor industry is less profitable in the future, it may be less willing to continue the investments necessary to stay on Moore’s Law. The challenge will be economic, rather than technical.
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1.2 Basic Definitions and Concepts • • • •
•
• •
• • •
LET—linear energy transfer, or energy loss per unit path-length. Cross section—sensitive area, such as the area in which an ion strike causes an upset. Critical charge—minimum charge to cause a specific circuit effect, such as a memory cell upset. SEU—single event upset, also referred to as a soft error, a change of state of a memory cell, where stored information is lost, but the cell is not damaged, induced by a single ion. SEL—single event latchup, regenerative high current state which occurs in four layer, pnpn, structures. Latchup is triggered in different ways, including single ions. Once triggered, the high current state is maintained until power to the circuit is turned off. Latchup is potentially destructive, because the high current can burn out critical parts of the circuit. SESB—single event snapback, regenerative high current mode related to parasitic bipolar action, similar to latchup, except that it occurs in three layer structures. SEB—single event burnout, typically observed in power devices. Either a parasitic bipolar device (in a MOSFET) or a bipolar device is turned on by a single ion, resulting in a high current condition that burns out metal electodes. SEGR—single event gate rupture, localized destruction of the gate oxide along an ion track, resulting in a hard short between gate and substrate. SET—current or voltage noise pulse generated by a single ion, which disrupts the operation of the circuit. SHE—single hard error, also known as a stuck bit, total dose-induced failure of a memory cell, caused by a single ion.
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2.0
Basic Mechanisms
In this section, we discuss the physical processes involved in charge deposition, recombination, and transport in electronic materials, both semiconductors and the accompanying dielectric layers.
2.1 Charge deposition—track structure effects The charge deposition in any material is proportional to the LET, which determines the energy lost by an incident particle. However, to determine the charge deposited, one also has to know the electron-hole pair creation energy, which is different in each material. Parameters for a number of materials of interest are summarized in Table I, including charge pairs per unit path-length per unit LET for an incident ion, where LET is given in units of MeV/mg/cm2. Table 1. Summary of Materials of Interest. Material Ep (ev) ρ (g/cm3) Pairs/µm per unit LET Si 3.6 2.33 6.47E4 GaAs 4.8 5.32 1.11E5 SiO2 17 2.2 1.29E4 In the early days of SEE studies, it was common to compare results based (only) on the LET of the incident particle. However, it was not long before it was found that particles at different energy with the same LET produced different effects.21 For this reason, other studies were performed to better understand the track structure.22, 23 Calculated track structures for selected ions are shown in Fig. 10.23 In both cases, there is a dense central core, and the density falls off rapidly with radial distance. In Fig. 10, both ions have the same LET, so the core structure is very similar. The only difference is that delta rays, knock-on electrons, have a greater range for the higher energy ion, so the maximum radius is greater. However, the vertical axis is a log scale, and only a very small fraction of the charge is deposited at relatively large radii by delta rays. The radial track distribution has also been measured experimentally, using a detector with a set of concentric rings.22 Typical results are shown in Fig. 11. The detectors are about 0.5 µm wide, and separated by 0.5 µm. Measured results are given by contact number, but the data points are about 1 µm apart. Measurements are compared with calculated charge deposition, with reasonable agreement. Since the track diameter may be comparable to the device size, or sometimes larger, it seems self-evident that device simulations have to take into account the structure of the track. One point still the subject of some controversy is the use of a gaussian approximation for the radial charge distribution in an ion track. Gaussian approximations have been used by some authors,24 and criticized as inadequate by others.23 Basically, a gaussian distribution can approach reality for the high density core of the track, where most of the charge is. But it does not predict the low-density tail of the track distribution at large radii (which is usually only a small part of the charge, however). IV-12
Figure 10. Calculated track structures for two ions with similar LET, after Dodd.23 Delta rays have different ranges, but structure is very similar in the high density core.
Figure 11. Comparison of calculated and measured track structure, after Howard et al.22 This discussion applies only to silicon so far. In oxides, there are three main differences. First, the radius of the dense core of the track is even smaller. The reason is that carriers in polar materials lose energy to the lattice by optical phonon interactions. When a charged particle passes through a medium, the dominant energy loss mechanism is the production of plasmons, which then decay to electron-hole pairs.25, 26 In SiO2, the plasmon energy is 22eV, and the electron-hole pair energy is 17 eV,27, 28 leaving about 5 eV of energy lost when the carriers reach thermal equilibrium with the lattice. This energy is lost through the emission of optical phonons, with an energy of about 0.1 eV,29-32 and a mean free path for emission of about 0.1 nm.33 That is, the excess kinetic energy is lost in about 50 steps of 0.1 nm, but this is a random walk, where the mean distance traveled is given by the square root of the number of steps, rather than the number itself. In other
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words, the extra kinetic energy of the charge pair is lost almost immediately, and the carriers reach equilibrium with the lattice almost where they are created. The optical phonon energy is proportional to the mass difference between Si atoms and O atoms in SiO2, or to M1-M2 in general. Of course, in Si, M1 is equal to M2, so there is no optical phonon effect. Therefore, the carriers retain their kinetic energy longer, and diffuse farther before reaching equilibrium with the lattice, so the initial track diameter is larger than in the oxide. The second difference is that recombination is a much stronger effect in the oxide than in Si, as we will discuss shortly. The third difference is that, because oxides are so thin, there are fewer charges produced to begin with, and even fewer survive recombination. For these reasons, many problems of practical interest in the oxide involve only 100-1000 charges. Determining the low-density tail of the charge distribution is, therefore, of less practical importance. The track structure in SiO2 has not been studied as much as in Si, partly for these reasons, but also because most of the work on SiO2 was done before the detailed studies in Si.
2.2 Recombination Recombination has been treated fully previously.34 In general, there are two models, which describe limiting cases. The geminate model describes the case where electron-hole pairs are far apart, and can be treated as isolated. The columnar model describes the case where there is a dense column of charge, and the separation between an electron and a hole from a given pair is greater than the mean separation between pairs. The columnar model is most relevant in a discussion of SEE, because ions create dense columns of charge. The columnar model was originally developed by Jaffe, who used it to model ionization in gases, in the early part of the last century.35 The equation that Jaffe developed had three terms: a bimolecular recombination term originally proposed by Langevin, a diffusion term, and a drift term to account for the effects of any applied field. Jaffe’s original analytical solution began by solving the diffusion term first, getting cylindrical distributions of positive and negative charges, and then letting the cylinders move past each other in response to the applied fields, as illustrated in Fig. 12. Finally, he reintroduced the effect of the recombination term. The problem with this approach, treating recombination as a perturbation, is that the recombination term is the largest term, not the smallest. Even so, Jaffe was able to get reasonable agreement between his experiments and his theory. But work applying the Jaffe model to SiO2 has all used numerical methods to solve the whole equation, without neglecting any terms. In the work applying the columnar model to SiO2, it has usually been assumed that the radial track distribution is gaussian, with a half diameter, b, of 3.5 nm.36-41 Typical experimental results for alpha particles and protons are shown in Fig. 13 and Fig. 14, respectively. Calculated results for a range of other ions and applied fields are shown in Fig. 15. In each case, the applied field, plotted on the horizontal axis, refers only to the component of the field normal to the axis of the cylinder. Depending on the ion type and field, the yield of charge ranges from about 0.3 for protons, to 0.1 for alpha particles, to 0.01 or less for heavier ions. On the other hand, for high fields, yield in a Co-60 source will typically be much higher, 0.8 or 0.9, so recombination is an important effect when dealing with any type of ion in SiO2. The actual yield for an ion in SiO2 is a critical question when discussing stuck bits, which we will do later.
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Figure 12. Columnar recombination, cylinders of charge moving under the influence of normal and parallel field components.
Figure 13. Alpha particle recombination in SiO2, compared to model predictions, as a function of field.
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Figure 14. Recombination for 700 keV protons as a function of field, compared to model predictions.
Figure 15. Model predictions of recombination for different normal field components and LETs.
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The biggest discrepancy between columnar model results and experiment is that for very high LET ions, the measured charge yield is often around 0.01, but the calculated result is perhaps an order of magnitude less, especially with no normal field component (for example, Fig.16).38 A more accurate initial track structure would probably improve this situation. Much of our understanding of the track structure in Si has been developed since this recombination work was done. Similar analysis of the track structure in SiO2 would be a useful thing to do.
Figure 16. Recombination measurements, compared with model predictions. At very high LET, and low field, difference may be as much as an order of magnitude.38 A problem of real practical interest currently is related to the application of this recombination to the problem of total dose from protons. One basic problem is that, as we have said, there are two models that treat limiting cases, where the charge pairs are either close together or far apart. But many practical experimental results fall in the transition region, where the experimental conditions do not satisfy the assumptions of either model. In Fig. 17, the LET curve for electrons satisfies the geminate assumption, that the charge pairs are far apart. For heavy ions, satisfying the columnar assumption, the LET is off the top of the chart. The proton LETs, shown in Fig. 17, are intermediate. The critical proton recombination results are shown in Fig. 18. The dashed line in Fig. 18 indicates an attempt to predict recombination in this transition region, and it fits the experimental results fairly well. The LET for protons does not reach the value of LET for 1-2 MeV electrons, which is the real geminate limit, until the proton energy reaches about 1000 MeV. Earlier versions of this figure had somewhat different curves especially in the transition region.42 However, recent experiments43, 44 show somewhat less yield than had been reported earlier, falling below the dashed line. Therefore, the dotted line is probably a better approximation of what happens in the transition region. There is still a columnar component to the recombination IV-17
process for protons between 100 and 200 MeV, even though the assumption of the model, that the charge pairs are very close together, is not strictly satisfied.
Figure 17. LET for protons and electrons at different energies.42 Recombination for electrons is described by the geminate model, while columnar model is appropriate for high Z ions (not shown). Protons at many energies of practical interest are in an intermediate range.
Figure 18. Measured proton recombination, different authors and different energies, compared to model results. IV-18
Finally, we have already noted that recombination is a much stronger process in insulators than in semiconductors, and discussed one of the contributing factors, the fact that the greater track diameter results in a lower charge density in semiconductors. There is actually a great deal of data on recombination in Si in the literature, however, because of work by the Si detector community. Typically, there is a difference between the current pulse produced in a detector by an ion, and the pulse that would be expected if all the energy of the ion were converted to ionization. This difference is called the pulse height defect, or PHD, and it consists of three components. The first of these is the energy lost by the ion passing through the metal electrode and other over-layers, which can be estimated very accurately from the LET if the composition and thickness of the layers is known. The second component is non-ionizing energy loss from displacement damage, especially at the end of the track. This component can also be estimated very accurately from the standard theory, the LSS model.45 The remaining PHD is from recombination, and it is in the range of 10% or less for most ions of practical interest to this community.46-48 For the very high Z ions, or high LET fission fragments, recombination is somewhat higher, but still much less than in insulators. In general, the result will depend on the applied field and the resistivity of the detector. We have mentioned the fact that the charges are initially deposited farther apart in Si than in SiO2 as one reason for this. The other reason is that screening lengths are much shorter in semiconductors than in insulators. Normally, if a free charge is introduced into a material, the other carriers in the material will move to screen off the field,49 so the potential and the field to fall off faster with increasing radius than would otherwise be the case. Of course, the greater the density of free carriers, the shorter the screening length.49 If the screening distance is greater than the separation between the charges, then they will exert electrostatic coulomb forces on each other, bringing positive and negative charges together to recombine, as is often observed in insulators. If the screening distance is less than the separation between charges, then the fields are screened, and the charges do not exert electrostatic forces on each other. Therefore, the positive and negative charges are not pulled together, and recombination events are rare, as is usually the case in semiconductors.
2.3 Charge transport and collection—funneling Following the discovery of SEE, the first discussion of charge transport and collection was by Kirkpatrick,50 who assumed that charge transported primarily by diffusion. He then worked out a number of examples, such as the illustration in Fig.19. He concluded that the charge collected by a device decreased less rapidly with scaling than the critical charge required to cause an error. “Thus the charge margins preventing soft failures in most current devices will vanish if the devices are made smaller without significant design changes.”
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Figure 19. Charge collection across an array, assuming transport is primarily by diffusion. Shortly afterwards, however, Hsieh et al.51-53 reported what they called the “fieldfunnel effect,” which meant that charge collection by drift, under the influence of an applied field, was more significant than originally realized. The funnel effect was originally discovered in device simulations, using the FIELDAY code,54 and confirmed experimentally. But IBM declined to make the code available to the government, so the DOD began an effort to develop its own codes. In the meantime, several simple analytical models were proposed for use until codes became available.55-58 These models were widely used for a time, especially the one by McLean and Oldham, until the codes were ready. The basic ideas are illustrated in Fig. 20 and Fig. 21. Qualitatively, these models and the codes reflect the same physical processes. First, the dense electron-hole plasma, which is formed along the ion track, collapses the junction depletion layer, leaving, in effect, a conducting wire in contact with the electrode and embedded in the substrate. Then the field extends down into the substrate (along the surface of the plasma wire), while the plasma expands radially by ambipolar diffusion. Finally, when the plasma density approaches the background doping density, the depletion region reforms, which cuts off the funnel. When funneling was first identified, it was viewed as a serious problem. The point of the schematic in Fig. 22 is that the struck bit is much more likely to upset with funneling. The figure shows an array of circuit nodes, with the charge collection profile expected from diffusion alone, and with significant funneling included. For the critical charge indicated, funneling is the difference between an upset and no upset. However, from our vantage point today, funneling is much less of an issue than it might have appeared, for several reasons. First, highly doped layers cut off funneling relatively quickly, because the plasma density reaches the background doping density more quickly. Today, the widespread use of retrograde well technology59 means there is often a highly doped layer just below the active device region, which effectively cuts off any funnel almost immediately. Second, the amount of charge on an electrode has shrunk as feature sizes have gotten smaller and voltages have been reduced—it is not clear that fields can be maintained in the substrate in IV-20
today’s devices in any case. Of course, funneling, as in Fig. 22, would probably be considered a good thing if it occurred. Error correcting codes would fix the one struck bit, and less charge would diffuse to neighboring cells, so multiple bit upsets would be less likely. For this reason, diffusion seems to be becoming relatively more important again, receiving renewed attention. An example of test data where diffusion seems to play a clear role is shown in Fig 23.60 Normally, there is a saturated value of the upset cross-section, which corresponds to size of the sensitive structure (DRAM storage capacitor, for example). In the Figure, the largest measured cross-section is about 4 µm,2 which is almost the published cell size,61 and much larger than the storage capacitor size. Clearly, if the ion can cause an upset by hitting anywhere in the cell, diffusion of charge to the storage capacitor is a critical mechanism, and it would have to treated adequately in any kind of error rate calculation.
Figure 20. Charge distribution during funneling: t0—ion strike creates a plasma filament in the Si; t1—the highly conductive charge column collapses the depletion region, starts to expand by ambipolar diffusion; t2—expansion continues; t3—when charge density in the column approaches background doping level, the depletion region starts to reform; t5—depletion region completely reformed.
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Figure 21. Potential distribution in the substrate during funneling: t0— depletion regionat the time of the ion strike; t1 and t2—potential extends into the substrate as the charge column expands; t3 and t4—potential in substrate reduced as the depletion region reforms; t5—depletion region completely reformed.
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Figure 22. Charge collection across an array, with enhanced collection by funneling at the struck node.
Figure 23. Upset cross-section as a function of LET; lack of a saturated crosssection indicates importance of diffusion.60 At high LET, cross-section is approaching published cell size.61
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Finally, we note that in structures with highly doped epi substrates, parasitic bipolar devices were sometimes observed to be turned on by ion strikes. This effect was called the ion shunt effect,62, 63 and it often meant that the collected charge in the circuit exceeded that deposited by the ion. We will discuss parasitic devices of this kind further in later sections. In insulators charge transport and trapping are relatively easy to simulate, because there are usually only a few hundred charge pairs in the oxide. The exact number depends, of course on the LET of the ion, oxide thickness, angle of incidence, and electric field. A typical case is illustrated in Fig. 24. The holes are deposited by the ion, and those escaping recombination are allowed to transport following the CTRW theory.34 In this case CTRW means that the holes hop about 1nm at a time, parallel to the total field, which includes both the applied field and the space charge field from the coulomb interaction with the other charges in the problem. Basically, the holes generated near the interface reach the interface first and are trapped. They set up a space charge field, which limits the charge density near the center of the distribution at the interface. Charges generated farther from the interface move radially because of the coulomb forces from the other charges, until they are far enough out. Then the applied field pushes them to the interface. In effect, trapping at the interface happens roughly in a series of concentric rings, with the outer rings filled last. The final charge distribution at the interface is illustrated in Fig. 25, which shows the top view of the Si/SiO2 interface, with each dot representing a trapped charge. When device sizes were shrunk to the point that they were comparable to the diameter of the footprint of charge in Fig. 25, single ion hard errors (stuck bits) began to be observed. We will discuss this subject in more detail later.
Figure 24. Charge transport in gate oxide—space charge fields from charge trapped at the interface force charges transporting later to move away from the ion track.
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Figure 25. Charge trapping for two different trapping efficiencies, each dot represents one trapped charge at the interface. Ion enters the oxide above the interface at an angle of 45 degrees from vertical, and travels along the x-axis.
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3.0
Device and Circuit Effects
In this section we will discuss SEE in devices and circuits. Many of the topics in this section have been covered more than once in previous short courses, from different perspectives and in differing levels of detail. Two previous Short Course presentations that have been particularly useful are by Johnson and Galloway,64 and by Dodd.65
3.1 Upset Upsets from single particles (SEU) were first reported at this conference by Binder et al. in 1975,66 who analyzed a simple (by today’s standards) bipolar flip-flop circuit. However, SEU did not achieve widespread recognition, especially in the commercial semiconductor industry, until May and Woods67 reported alpha-particle induced SEU in high-volume Intel DRAMs (4K and 16K) and some SRAMS. Pickel and Blandford,68, 69 and Johnston70 have considered how device scaling will affect the upset rate. In 1982, Pickel and Blandford calculated that the future sensitivity to upset would remain roughly constant, despite continued scaling. Although smaller devices would have lower values of critical charge, the sensitive volume would also be smaller, so the charge would have to be deposited in a shorter path-length. They calculated these two effects would roughly offset, so that the upset rate would be approximately the same. About twenty years later, Johnston reviewed the trend in upset rates over that period, and found that the rate had, in fact, been nearly constant. 3.6.1 DRAMs The mechanism for SEU in DRAMs is illustrated in Fig. 26, which is taken from May and Woods. The two states of the cell are indicated—either the well of the storage capacitor is filled with electrons, or it is empty. When an alpha particle passes through the well, electron-hole pairs are created in the Si, with the holes diffusing into the substrate, and the electrons being collected in the well of the storage capacitor. If the well was already full of electrons, no change of state occurs. But if the well is empty, the electrons tend to fill it, and if the well becomes full enough, it is sensed as full, and the bit flips—changes state. This effect was also called a soft error, because the bit could be reset, and the cell would work as well as ever. The critical charge to cause an upset was the number of electrons that had to be collected in the well to cause an upset. Generally, it was half the full-rail voltage swing (for example, 2.5 V in a 5V part) times the storage capacitance, Cs. May and Woods performed several experiments involving shrinking the storage capacitor dimensions, or varying the oxide thickness, and found that the error rate was extremely sensitive to Cs, or critical charge.
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Figure 26. DRAM upset, after may and Woods.67 If an empty well is struck by an ion, it becomes partly full, which may be detected as a change of state. A full well remains full, so no change of state is detected. 3.6.2 SRAMS In SRAMs, there are two main types of cell designs to be considered, six transistor (6T) which is illustrated in Fig. 27,69 and four transistor (4T) which is shown in Fig. 28.72 In the 6T cell, the typical upset mechanism is that an ion strikes the drain on the right side of the Fig. 27, which is biased high initially. The ion strike pulls down the voltage on drain B, which also pulls down the voltage on the gates of the inverter on the left side, which tends to turn on the “off” p-channel device and the “on” n-channel device is turned off. When current flows through P1, the drain B is charged high, which raises the gate voltages on the right side of the Fig. 27, turning P2 off, and N2 on, leaving the cell in the opposite state from where it started. Simultaneously, however, current is flowing through P2, which is on initially, to restore node B to its high state. If the cell recovers by this mechanism before the IV-27
feedback loop can be closed, no upset will be observed. If the feedback process is completed before the recovery process, then an upset occurs. It is a race between feedback and recovery. The purpose of hardening with poly resistors is to introduce another RC delay, slowing down the feedback process, so that the recovery process always wins. Dodd et al.71 performed modeling, which indicated that more charge is collected in a 6T cell if the cell recovers than if the cell changes state. The reason is that when transistor P2 switches, it cuts off the charge collection, which continues unless P2 switches. The concept of critical charge loses its meaning, in this case.
Figure 27. Six transistor (6T) static RAM cell, after Pickel.69
Figure 28. Four transistor (4T) static RAM cell, after Diehl-Nagle.72
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In the 4T cell, Fig. 28, the situation is somewhat different. Instead of active pchannel load devices, the cell has two large poly-Si resistors. This cell design was attractive to the commercial industry because the cell area was reduced by about a third if one third of the transistors were eliminated, which reduced the cost of the chip by about a third, too. The resistors were built in a layer of poly-Si on top of the transistors, so there was no area cost associated with them. The problem of an ion strike in a 4T cell was first analyzed by DiehlNagle,72 who identified what she called a disturbed condition following an ion strike. If an ion struck node A, which is biased high initially, it would pull the voltage down, tending to turn N3 off. Eventually, the current flowing through the resistor to A would restore the cell to its correct state. The problem was that the restoring current flowed very slowly, because the resistor was very large, as it had to be to keep power consumption within reasonable bounds. In Diehl-Nagle’s analysis, most of the data was obtained on 64K SRAMs, and the value of the resistors was about 1011 ohms. Therefore, with 5V applied, the current through the resistor was about 50 pA, which meant that it took on the order of 1 ms for the cell to recover. If it was read in that interval, the likely result would be an incorrect read. Typically, a struck cell would be disturbed for 104 or 105 read cycles, so there was a significant probability of such an incorrect read. The other problem with the basic 4T design was that in each subsequent technology generation, the resistors had to have 4x greater resistance to maintain the same power consumption, because (of course) there were four times the number of cells. Therefore, the recovery time of a disturbed cell also increased by 4x in each generation. Almost all the commercial 1M SRAMs ever sold had 4T cell designs, but this tradeoff between power consumption and alpha particle immunity forced the industry to begin switching to other approaches after that. 3.6.3
Commercial Industry Hardening
Although it is widely accepted in the radiation effects community that the commercial industry does not care about radiation hardening, the fact is the industry cares very much about alpha particle immunity. And the industry has taken a number of specific actions to try to improve alpha particle immunity, which can be described as hardening approaches. We will specifically discuss five of these approaches. The first, and most obvious, thing was to increase the storage capacitance in DRAMs, to increase the critical charge. An early example of this approach is illustrated in Fig. 29.73 Of course, thinning the gate oxide is a major feature of scaling in general, but Intel had made a concerted effort to thin the oxide in the storage capacitor (even) faster than they thinned the gate oxide. This was in the days when the storage capacitor was a planar structure with a pure SiO2 dielectric. After about the 1M generation of DRAMs, cell area was too small to get reasonable storage capacitance in a planar structure, so the companies went to trench capacitors, or stacked dielectric structures. The industry also began looking at other dielectric materials with higher dielectric constants, nitrides and oxy-nitrides initially, and other things like BST (barium strontium titanate) later. Details of the capacitor processing are usually not revealed, but the major companies do sometimes publish papers stating what the storage capacitance is. In Table II, we summarize published values of Cs by company and by generation of chips, which are plotted in Fig 30.61, 74-116 The scaled value of capacitance would shrink in very generation, according to simple scaling, but the actual capacitance has
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been fairly stable over several generations, indicating increasing amounts of ingenuity in the design and construction of the capacitor structure.
Figure 29. Storage capacitance for selected DRAMS, after T.C. May.73
Figure 30. Storage capacitance for DRAMS, by generation of technology, and by company.
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Table 2. Values of Cs Cs(fF) Company Mitsubishi Siemens IBM Intel ATT Mostek Toshiba Mitsubishi IBM NTT NEC Hitachi NEC Toshiba-1 Toshiba-2 Mitsubishi TI Hitachi Matsushita Hitachi Toshiba OKI Mitsubishi Samsung IBM NEC Mitsubishi Fujitsu Toshiba Matsushita OKI Matsushita Mitsubishi Hitachi NEC Fujitsu Hitachi Mitsubishi Samsung OKI IBM/Infineon Elpida/Hitachi NEC
256K
1M
4M
16M
64M
256M
1G
4G
Reference
60
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 61 94 95 96 97 98 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
50 55 50 55 60 34 42 45 37 30 50 60 50 40 30 50 30 44 63 33 30 30 35 30 100 40 30 20-30 34 35 25 20 25 25 30 22 17 25 25 20 35 25 (BST)
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Second, we have already touched on the use of retrograde well technology59 to create a highly doped buried layer under the active device region, which cuts off charge collection from an ion strike, The basic approach is illustrated in Fig. 31. The use of highenergy (MeV) implanters for this purpose117- 119 is an important supporting technology. A high- energy implanter is used to create a heavily doped layer at some depth, determined by the range of the ions in Fig. 31. Then a short high temperature activation step leads to the dopant profile indicated. In a conventional process, a shallow implant is used to produce a high dopant concentration near the surface, which has to be driven in with a longer high temperature step, producing a profile similar to that shown in Fig. 31. The retrograde well approach is used in both SRAMs and DRAMs.120-122
Figure 31. Retrograde well technology using high-energy implanter, compared to conventional well.59 Third, the industry has basically abandoned the 4T cell, for the reasons we have already mentioned. If the resistors are large enough to limit power consumption to reasonable levels, the alpha particle problem grows out of bounds. Instead, recent SRAMs have been built with a 6T cell design. To maintain the area (and cost) benefits of the 4T approach, the p-channel devices are TFT (thin film transistors) fabricated in a layer of polySi on top of the n-channel devices. This approach is illustrated in Fig. 32. These p-channel devices do not have the electrical characteristics of devices made in crystalline Si, because the starting material is not of the same quality. But the on-current is typically 105 or 106 times the off current, which means that the voltage recovers much faster after an ion strike, than in a comparable 4T design. And because the p-channel devices are on top of the nchannel devices, there is no area penalty, compared to a comparable 4T cell.
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Figure 32. Thin film transistors (TFT)—commercial SRAMS now have 6T designs with p-channel devices fabricated in a layer of poly-Si on top of the nchannel devices.
Figure 33. Soft error rate by generation of SRAM, with approximately order of magnitude improvement when B10 is eliminated, after Baumann.123
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Fourth, it has been shown by Baumann123 that most of the soft errors observed in some processes are mostly due to the interaction of B10 with thermal neutrons from sea-level cosmic rays. Eliminating B10 from the process reduced the observed soft error rate by about 90%, as shown in Fig. 33. Therefore, other companies have also begun to eliminate B10 from their processes. Fifth, and finally, it is ironic—given the resistance of some in the radiation effects community to plastic packaging—that one of the reasons the industry first started going to plastic packages was for radiation hardening. The plastics have much lower concentrations of alpha emitters than the materials they replaced, which is illustrated by the data in Table 3.124 If one could reduce the alpha error rate by one, or two, or three, or even more, orders of magnitude by changing packages, it was a powerful incentive to do so. Once the industry discovered that plastics were also cheaper, there was no holding them back. Table 3.124 Alpha-Particle Emission Rates of Processing Films, Leadframes, and Packaging Materials Emission Rate Material
α P/(cm 2 • hour)
Bare silicon Si + CVD ox (TEOS) Si + plasma oxide Si + plasma nitride Si + tungsten Si + aluminum Si + polysilicon Si + field oxide Si + BPSG Si + CVD nitride Fully processed w/o WSix Fully processed + WSix Polyimide die coat DIP leadframe Zip leadframe 256K DIP 64K DIP Metal package lid (vendor A) Metal package lid (vendor B) Ceramic package lid (vendor A) Ceramic package lid (vendor B) Plastic (epoxy) Ceramic DIP (vendor A) Ceramic DIP (vendor B) Ceramic DIP (vendor C) Ceramic LCC
0.00020 0.00164 0.00188 0.00433 0.00308 0.00682 0.00098 < 0.00010 < 0.00010 < 0.00010 0.02400 0.04230 < 0.00010 0.00677 0.00258 0.00124 0.00109 0.015 0.030 0.15 3.10 0.00080 0.02320 0.03230 0.02610 0.02530
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3.2 Latch-up It is well-known that a high current state, known as latchup, can occur anytime there is a four layer n-p-n-p structure. Such structures are inherent in CMOS, where n-channel transistors and p-channel transistors are located side by side. The structure must be regenerative, in that there is a mechanism to increase the current to very high values once the threshold values for establishing latchup have been reached. Latchup can be triggered in different ways, electrically by applying high voltage, by radiation, and by single heavy ions. Heavy ion-induced latchup was first reported by Kolasinski et al.125 at this conference in 1979. Latchup has been modeled in terms of two bipolar transistors, since at least 1973.126 Although the two-transistor model is highly simplified, it is a useful way to introduce the main features of latchup, and it is widely used. The structure is illustrated in Fig. 34.127 The n+ source or drain (emitter), p-substrate (base), and n-well (collector) form a lateral bipolar parasitic device. The other, vertical, parasitic device is formed by the p+-source or drain (emitter), n-well (base), and p-substrate (collector). For each device, the collector is also the base of the other device, which leads to a positive feedback loop between the devices. Latchup is initiated when an ion strike causes current to flow in the well/substrate junction, which causes a voltage drop in the well. This voltage drop forward biases the vertical device, and the gain of the device results in increased current into the substrate. This substrate current causes a voltage drop in the substrate, which turns on the lateral device. This, in turn, results in increased current flow back to the base of the vertical device, initiating the positive feedback loop. The resistances shown in Fig. 34 are not fixed resistors, as indicated in the Figure, but rather distributed resistances. Their exact values depend on the detailed geometry, including the position of the ion strike, which is one reason it is difficult to deal with latchup analytically. The I-V characteristic of a latchable structure is shown in Fig. 35. In this case, the latchup is initiated electrically, by applying a high voltage. The curve is linear in Region I, the forward blocking region. When the voltage reaches the breakover voltage, there is a negative resistance region. In the latchup region, Region II, the latchup will be stable as long as voltage exceeds the holding voltage, the current exceeds the holding current, and the gain of the vertical and lateral devices is large enough. Johnston127 points out that this last condition is often stated as βVβL>1, but that the reality is more complicated because currents flowing in the well and substrate represent losses, which should be accounted for. Latchup is a major concern because it can cause catastrophic failure from excessive heating of active devices, or metallization, or bond wires. The most effective way to bring devices out of latchup is to turn off the power, reducing the voltage below the holding voltage. Even when a latchup is not immediately catastrophic, recent data indicates there is sometimes latent damage present after normal device operation is restored.128 After non-destructive latchup, damage to interconnects was found that was visible in SEM pictures, even though the electrical characteristics of the circuit appeared to be normal. The implications of these results for the long-term reliability of the circuits are still unclear. Procedures for setting limits for current detection and shutdown for latchup protection may also need to be reconsidered.
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Figure 34. Two transistor model for latchup, after Johnston.127
Figure 35. Latchup IV characteristic, showing forward blocking, breakover voltage, holding voltage and current, after Johnston.127 Since latchup can be initiated by purely electrical stimulus, the commercial semiconductor industry pays some attention to process steps that minimize latchup sensitivity. Of course, immunity to electrically induced latchup does not guarantee IV-36
immunity to single-ion-induced latchup, but process changes that reduce sensitivity to one usually also help with the other. These process changes are intended to prevent the parasitic bipolar devices from turning on (becoming forward biased) or to reduce the gain, so that they are less likely to stay on. The process changes include increased doping levels in the well and substrate, and increased well depth, both of which reduce series resistance (and, therefore, voltage drops). Use of retrograde wells or epi substrates also reduce charge collection volumes. At one time, it was thought that an epi substrate was sufficient to eliminate latchup completely, but a number of counter-examples have now been observed, as illustrated in Fig. 36.127 Indeed, one of the most sensitive parts ever tested (AMD K-5) is on a thin epi substrate. Trench isolation and guard bands have also been used to reduce latchup sensitivity.127 Deeper trenches are more effective, of course. Guard bands impose an area penalty.
Figure 36. Latchup thresholds for selected circuits on epi substrates, after Johnston.127 The AMD K-5 is one of the most sensitive parts ever tested. Generally, the impact of scaling has been to make circuits more sensitive to latchup, because structures are closer together. Of the mitigation techniques we have just discussed, increased doping and trench isolation are the only ones consistent with continued scaling. Deeper wells may help, but scaling usually leads to shallower wells. Guard bands would not be expected in the most advanced technology. However, the trend toward increased sensitivity is likely to be reversed very soon, because power supply scaling will soon reduce VDD below the latchup holding voltage in many applications. Typically the holding voltage is about 1V, and the ITRS projects VDD for high performance desktop applications to be 1V this year, and below 1V in 2005. Other applications vary by a few years, but the trend to lower operating voltages is clear. Also, if continued scaling forces the industry to adopt SOI at some point, latchup will be eliminated, because four layer structures will be eliminated— three layer transistor structures will be separated by dielectric isolation. However, snapback, sometimes referred to as three layer latchup, will become more of an issue in SOI, as IV-37
we discuss in the next section. There are many other authors who have discussed latchup in more detail than is possible here, and the reader may wish to consult their work.129-139 There are a number of unique testing issues associated with latchup, primarily because it depends on physical processes, e.g. charge diffusion, deep in the substrate. Latchup is a slower process than upset, requires longer-range ions than upset, and is strongly temperature dependent, with high temperature being worst case. Thermal generation of carriers contributes to establishing latchup.
3.3 Snap-back Snap-back is another regenerative, high current mode related to parasitic bipolar action, which was first analyzed by Ochoa et al.140 It differs from latchup in that it occurs in a three layer structure, a single MOSFET, and not a four layer structure. The source/well or substrate/drain regions of a MOSFET also represent a parasitic npn or pnp bipolar device, which turns on in snap-back. The source-drain breakdown characteristic of the MOSFET has a negative resistance region, which results in a stable, high current, low voltageoperating mode. Qualitatively, snap-back may appear to be similar to latchup, but it is not strongly temperature dependent, can be eliminated by reducing the voltage on the gate of the affected device (without cycling power to the whole circuit), and generally involves much lower levels of current in the whole chip. The micro-latches sometimes observed in testing complex circuits, localized high current regions, which cause a small increase in total chip current, may be individual devices in snap-back mode. Snap-back can be initiated, much like latchup, by high voltage, by high dose-rate radiation and by single heavy ions. The analysis by Ochoa et al. was based on dose-rate upset, but ion induced upset was analyzed in detail by Dodd et al. for SOI devices,141 and it has been observed experimentally by Koga and Kolasinski.142 Some authors have used the term second breakdown interchangeably with snapback,143 but second breakdown is a more general term than snapback, as we have defined it here. Second breakdown has been reported in many different kinds of devices,144146 and is apparently triggered by a number of different mechanisms.143 At least, there seems to be no consensus on what the triggering mechanism is. Generally, any device, where the I-V characteristic resembles Fig. 37, is said to undergo second breakdown. This is also called snapback because the voltage snaps back to a lower value from a higher value, as the current goes up.
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Figure 37. IV Characteristic for second breakdown or snapback.
3.4 Burn-out Single event burnout (SEB) is typically observed in power transistors, both MOSFETs and bipolar. A schematic of a double-diffused power MOSFET is shown in Fig. 38, with an expanded view of the parasitic device in Fig. 39.64 The MOSFET drain contact is on the backside of the wafer (not shown). The parasitic device is inherent in the MOSFET structure. A bipolar power device is shown in Fig.40,64 which is very similar to the parasitic structure in the MOSFET. SEB is triggered when an ion passes through (usually) an n-channel device biased “off,” with high blocking voltage. The currents generated by the ion turn on either the parasitic or the active bipolar device, and trigger a regenerative feedback mechanism, second breakdown, or snap-back. In second breakdown here, the ion track forms a plasma filament connecting source and drain, which leads to a high current condition, associated with an abrupt drop in the breakdown voltage and a negative resistance region similar to latchup. The low breakdown voltage means that avalanche multiplication of the injected current takes place, leading to positive feedback and a stable high current condition—in effect, a permanent short between source and drain. If the current is not limited somehow, it will eventually burn out the interconnects, destroying the device.
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Figure 38. Power MOSFET, with parasitic npn bipolar device, after Galloway and Johnson.64
Figure 39. Parasitic bipolar device from Figure 38, expanded view, after Galloway and Johnson.64
Figure 40. Bipolar power transistor, after Galloway and Johnson.64
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A number of models have been used to develop an understanding of the physical processes involved in SEB. The first, and simplest, of these is the Current-Induced Avalanche (CIA) model, by Wrobel et al.,147-149 which was used to show how the field distribution changed in a device as the current level increased. The field reflected the concentration of ionized dopants, but also the concentration of free carriers. At high enough current levels, avalanche multiplication started, explaining the regenerative feedback mechanism, which lead to burnout. The field distribution at increasing current levels is illustrated in Fig. 41. Regenerative feedback starts when the field at the epi/substrate interface becomes high enough to cause avalanche multiplication of the injected current. The second model was outlined by Hohl and Galloway,150 and extended by others,151, 152 and attempted to better quantify the regenerative feedback mechanism. They solved the Poisson equation for the base-collector depletion region, to determine the number of avalanche generated holes for a given number of injected electrons. The results are shown in Fig 42. The first peak corresponds to reduced avalanching because the field in the depletion region is reduced, as the depletion region extends into the collector. The minimum avalanche region corresponds to the case where the injected electron density is comparable to the doping. The third region, where the hole concentration increases roughly proportionally with the electron concentration, corresponds to high fields at the epi/substrate interface.
Figure 41. Current induced avalanche, after Wrobel.147 As current density increases, high field at epi/substrate interface leads to avalanche injection, and regenerative high current mode.
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Figure 42. Avalanche multiplication, corresponding to high field at the epi/substrate junction, after Hohl and Galloway.150 These simple, analytical models were very useful in developing an understanding of the basic physical processes involved in burnout, but they did not capture all the relevant device physics. For detailed quantitative work, complex simulation tools are now available, and widely used. For example, one such simulator is based on the MEDICI tool.153 Another simulator developed, by Kuboyama et al., is based on the PISCES model, but with custom features for burnout analysis.154 Burnout testing can be difficult and expensive, because it is a destructive test, which can consume large numbers of samples. But it is possible to do nondestructive burnout testing by detecting the current spike from the device turning on, then turning the device off before it actually burns out. Normally, this makes it practical to do reasonably complete testing. One important test technique is the use of EPICS (Energetic Particle Induced Charge Spectroscopy), which is a pulse height measurement system used to monitor the charge collection in burnout testing. EPICS results are illustrated in Fig. 43.155 The first two peaks are due to ions hitting different parts of the device, and the high charge spike at high voltages indicates the device turning on, which would be followed by burnout in the absence of current limiting. A number of mitigation techniques have been identified for reducing the probability of SEB, all of which are intended to make the bipolar device harder to turn on. Extending the p+ plug has the effect of reducing the base resistance, which means that higher current levels are necessary to forward bias the device. Reducing the source/drain bias reduces the
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field in the base/collector depletion region, which reduces impact ionization, which makes the device harder to turn on. P-channel devices are much less susceptible to burnout than nchannel devices, so replacing n-channel devices with p-channel might be considered, although it is often not practical to do so. And burnout susceptibility is reduced at higher temperatures, so operating at higher temperature might be considered. However, higher temperature might also reduce the reliability of the device, or the system.
Figure 43. EPICS (Energetic Particle-Induced Current Spectroscopy) results, showing high current spike, corresponding to parasitic device turning on, leading to burnout, after Kuboyama et al.155
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3.5 Gate Rupture Single event gate rupture (SEGR) results when the interaction of an ion with the gate oxide results in the destruction of the gate oxide, and a hard short between the gate and the substrate. It was first observed by Blandford et al.156, 157 in MNOS non-volatile memories, and later by others.158 Within a short time, it was also reported in power devices,159 which have been the focus of most of the more recent work. In MNOS memories, the effect was typically observed only for high LET ions (LET = 35 or more), and only during erase/write cycles, when high voltage was applied. The circuits were used as “read-mostly” memories, with 5V read voltage, and rewritten only rarely, but with 12 V applied. The circuits with permanent errors were subjected to failure analysis, and localized conducting paths from gate to substrate were found. Localized damage was also visible in SEM pictures. The first reports of gate rupture in power devices were by Fischer,159 confirmed by Wrobel in capacitor studies,158 and the parametric dependences of SEGR have been extensively studied by Titus and Wheatley.160 The experimental data is summarized in Fig. 44,160 which shows the conditions needed to initiate SEGR for different incident ions. Two models for SEGR have been developed, a simple analytical model by Brews et al.,161 and the device simulation code, Athena.162 The analytical model is illustrated in Fig. 45, where the “plasma wire” 56 serves as a conceptual starting point, but the presence of the gate oxide, the source, and the drain are important differences that are taken into account. In the n-channel device in Fig. 45, the electrons diffuse radially, and are collected at the drain, and the holes tend to pile up at the gate oxide, before being collected at the source. When the holes are concentrated at the oxide, they induce image charges on the gate, increasing the field in the oxide. Breakdown occurs if the field exceeds some critical value, estimated by both Fischer and Wrobel as approximately ECR = (41x106 V/cm)/(LET)1/2 . That is, an ion with LET = 37 would correspond to a critical field of about 6.7 MV/cm, compared to a breakdown field of perhaps 10 MV/cm or more in the absence of an ion strike. Of course, numerical simulation is quantitatively more accurate, and a 2-D simulator has been developed and used with success by Allenspach et al.163-165 SEGR testing is difficult, because there is no way to test nondestructively. Therefore, one needs large numbers of samples to destroy, also large amounts of beam time, with very well calibrated beams. Techniques for reducing SEGR susceptibility have been identified. Increasing the oxide thickness obviously reduces the space charge field across the oxide, and, therefore, SEGR sensitivity. Of course, the effect of scaling is usually to reduce oxide thickness, so this method requires the manufacturer to adjust the process in a way that may seem unnatural. Reducing source and drain biases also reduces oxide fields. Pulling back the poly gate from the neck region reduces the fields in the neck region. And SEGR sensitivity is reduced at higher temperature, although high temperature operation may not be useful, for other reasons.
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Figure 44. Initiation of Gate Rupture for different ions, and exposure conditions, after Titus and Wheatley.160
Figure 45. Conceptual model for gate rupture, after Brews et al.161 Space charge field from holes piling up at the oxide interface lead to breakdown.
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3.6 Stuck bits The so-called stuck bit problem is a single ion effect in a memory, which can occur in both DRAMs and SRAMS. There are two mechanisms for stuck bits, which have been reported in the literature.40, 41, 166 3.6.1
Micro-dose—gate, field oxides
The first of these is caused by the total dose deposited by a single ion passing through the gate oxide of a transistor. Obviously, this only happens in very small transistors, but it has been commonly observed for some time, now. The effect was first reported by Koga et al., 167 first shown to be due to single ions by Dufour et al.,168 analyzed in more detail, first by Oldham et al.,40 and later by Poivey et al.41 The basic effect is that the trapped charge deposited by a single ion is enough to cause a small threshold voltage shift, which causes a small increase in subthreshold leakage current. The transport and trapping of this charge have already been described above. This is sometimes enough to cause the failure of an NMOS memory cell, in either a DRAM or in a four-transistor SRAM cell, because these cells are very sensitive to small leakage currents. We have already discussed the 4T cell, Fig. 28, in connection with upset. The problem here is damage to the gate region of one of the transistors. If the resistor is on the order of 1012 ohms or more, which was typical for a 1M SRAM, the current flowing to the transistor was limited to a few pA, at most. If damage to the transistor meant leakage of more than than a few pA, then charge would leak off the drain faster than it could be replaced, and one side of the cell could not be held on. A typical I-V characteristic for an n-channel MOSFET is illustrated in Fig. 46, where the pA current level corresponds to a voltage of only about 100mV. But on a chip with millions of transistors, the distribution of VT values will include outliers around +/- 6σ. Poivey et al. concluded that, for the 1M technology they were testing, the standard deviation was about 10 mV, based on analysis and confirming data. The variation in threshold voltage across a die, and between die is illustrated in Fig. 47. For this reason, the devices with the lowest thresholds had very little margin, if struck by an ion. Future scaling will likely mean that the spread in threshold distributions will increase, even as the mean threshold is reduced. Smaller devices have fewer dopant atoms, and the standard deviation varies as N1/2, so there will be more relative variation in threshold voltages initially. Gaillard169 performed 2D device modeling to determine the effect of a spot of trapped charge, such as that shown in Fig. 25, on the device threshold voltage. He found that the threshold shift was largest when the spot of trapped charge is in the middle of the device, and large enough to cause device failure in many cases. Oldham et al. included oxide thinning in their analysis, and concluded that stuck bits would tend to go away in thinner, future oxides. But this has not happened as quickly as one might have predicted from that analysis. The likely reason was pointed out by Loquet et al.,170 who presented simulation results suggesting that a single ion in the bird’s beak region or the field oxide, could also cause a leakage path that would cause a bit to fail.
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Figure 46. Typical I-V characteristic for an n-channel MOSFET. V corresponding to 10-12 A is about 100mV, but standard deviation is about 10 mV. Variation in VT means that some cells are much more sensitive to single ion total dose damage than others.
Figure 47. Number of failed bits in nominally identical SRAMs as a function of total dose, after Poivey et al.41 Shape of each curve indicates distribution of threshold voltages on a given die. Difference between curves indicates variation in mean threshold between different die.
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3.6.2
Micro-damage—track formation
The second stuck bit mechanism was presented by Swift et al.,166 who observed shorted gates in memories with thin gate oxides, exposed to gold ions with LET of about 80. The mechanism was thought to be similar to SEGR. Memories have lower applied voltages than those commonly used in SEGR experiments, but the data suggested some kind of oxide damage mechanism. Representative data is shown in Fig. 48. This data was taken on 4M DRAMs, and failure to refresh was taken as the failure criterion. The data indicated as “stuck at zero” is consistent with low level leakage from damage to the pass transistor, and was attributed to micro-dose damage, as we have just discussed. The “stuck at one” data indicated failed devices, regardless of the refresh time. These devices seem to have hard shorts of the gate oxide, because they cannot hold a charge for any measurable interval. These devices did not recover in a high temperature anneal, indicating the failure was not due to total dose. Swift et al. concluded that the damage was similar to a gate rupture in these devices.
Figure 48. Stuck bit results, after Swift et al.166 Lost zeros are attributed to micro-dose damage, because increased leakage current correlates with degraded refresh characteristic. Lost ones appear to be hard shorts because cells cannot hold charge for any measurable interval.
3.7 Single Even Transients Transients (SET) have been treated thoroughly in the Short Course, relatively recently, by Buchner and Baze171 in 2001, in far more detail than is possible here. Basically, an ion passing through a circuit, which causes a voltage transient on a junction, is IV-48
an SET. If the transient occurs in a memory chip, it may cause an upset, which we have already discussed. Until relatively recently, SET in logic circuits received relatively little attention, because errors were rarely observed until feature sizes were scaled below about 0.3 µm. SETs either did not propagate to a latch, or they were not captured. Logic gates switched slowly, compared to the duration of a transient, so the gates acted as low pass filters, filtering out high frequency noise. Experimentally, error rate was found to be independent of clock frequency,172 indicating that logic gates did not contribute significantly to observed error rates. For this reason, SEE testing of logic circuits focused on the radiation response of the registers, since they determined the radiation response of the circuit. However, with continued scaling, feature sizes are well below 0.3 µm, and clock speeds are now 100s of MHz, and SETs in combinational logic have become a significant issue. Single event effects in analog circuits were first reported by Koga et al. in 1993, and confirmed in other reports.173-175 Because the transient duration is more nearly comparable to the clock cycle, is much more likely to propagate and to be captured at a register because it coincides with a clock edge.176-179 In highly scaled circuits, there is experimental evidence that the error rate increases with clock frequency, as illustrated in Fig. 49. The basic idea is illustrated in Fig. 50, where a bit stream, 01010, is sampled, with radiation events occurring in periods 3 and 4. The only error detected is in period 3, however, because the event in period 4 was outside the sampling window. The closer the sampling window is to the bit period, the more errors will be detected. Fig. 51 illustrates the situation at the maximum operating frequency, where a single bit period is shown, with the rise and fall times included. If the sampling window extends from position 1 to position 3, every bit will be detected as an error, which defines an upper limit to the operating frequency. Data showing an example of this effect are shown in Fig. 52, where the limiting frequency was determined by the test equipment, rather than the circuit under test. SET testing can be done in several ways. Wide beam accelerator exposures can be used to screen parts for space applications, provided the operating frequency and other variables accurately simulate space operation. However, these tests cannot illuminate the circuit mechanisms, because the exact location of the ion strikes cannot be determined. For that, one must use a focused ion beam,180 which makes it time consuming and expensive to test a complex circuit. Cf and Am laboratory sources have been used, usually for screening before accelerator testing, because they are convenient, but the particles are too short range to penetrate to the active region in some cases. Pulsed laser testing has been valuable for many things, because it is non-destructive, and the position, intensity, and timing of the pulses can all be controlled in the experiment.181, 182
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Figure 49. SET Test data, after Reed et al,176 showing the error rate proportional to frequency.
Figure 50. Sampling of 01010 bit stream, with transients in third and fourth cycles, after Reed et al.176 Only the third bit will be detected as an error, because the transient in the fourth cycle was too short to be detected. As the circuit operating frequency increases, transient duration and sampling interval become nearly equal and the error rate increases.
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Figure 51. Data pulse, with rise and fall times shown, after Reed et al.176 If the sampling window extends from position 1 to position 3, every bit will be detected as an error, defining a maximum operating frequency.
Figure 52. SET test data, after Reed et al.,176 where error rate increase abruptly at the maximum operating frequency of the test equipment. When the test was repeated with faster equipment, results were qualitatively similar, but the maximum frequency was higher.
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There are a number of modeling tools that can be, and have been, used to study SET. Device-level tools include PISCES, PADRE, ATLAS, and GENESIS. These tools solve the Poisson and carrier continuity equations for particular device structures, and are used to predict device response. Typically, the transient calculated for a device is then fed into a circuit analysis code, which calculates the circuit response. It is also possible to use a mixed mode tool, such as DAVINCI, which can model one transistor at the device level, and the rest at the circuit level. The difficulty with all of this is that in a complex logic circuit, there are many different transistors, and one does not know where or when in the logic flow the transient is generated. Hardening approaches usually fall into one of two categories—process techniques and circuit techniques. Process techniques are designed to reduce the transient by reducing the charge collection volume, by using epi layers, or well structures, or SOI substrates. Circuit techniques may be described as (1) charge dissipation, (2) filtering, or (3) spatial redundancy. Charge dissipation means adding capacitance or current drive, so that the critical charge for upsetting the circuit is increased. Of course, these approaches impose a power penalty. Filtering means slowing down the circuit so that the transient is faster than the circuit operation. The whole point of scaling is to produce faster, better performing circuits, so this approach imposes a significant performance penalty. Redundancy means building in multiple circuit elements, and voting them, which imposes an area penalty. SET is an area where the problem will clearly get worse very rapidly with continued scaling. It has recently become a problem because the duration of the transient is close to the period defined by the clock frequency. One of the main goals of scaling is to push the operating frequency higher and higher, so this will inevitably be more of a problem in the future. Hardening approaches all involve giving up the performance benefits of scaling.
3.8 Hard/Soft Breakdown Ion induced hard breakdown has already been discussed, SEGR. Ion-induced soft breakdown (SBD) has only recently become the subject of active study, with the first papers at this conference in 2001.183, 184 For this reason, soft breakdown is likely to be the subject of further study for some time to come. By soft breakdown, we mean a modest increase in gate oxide leakage current, which is probably due to a localized damage region, if the SBD is ion–induced. (SBD, induced by electrical stress, and by radiation, has already been discussed by the previous speaker (Paccagnella).) Massengill184 concluded that the small increase in leakage current from SBD would not, by itself, have a significant impact in most applications. However, other, later, studies have indicated that if components are subjected to lifetime testing, after SBD, they generally fail early in the test.185-187 Clearly, then, it would be useful to understand the nature of the damage region created by an ion strike. There is an extensive body of literature on nuclear tracks in solids, which has been developed by a community that has flown a variety of different solid films as cosmic ray detectors. Much of this literature was reviewed by Fleischer et al., in a book published in 1975, so the literature is not new.188 Basically, when an insulator is exposed to cosmic ray bombardment, a disordered region is formed along the ion track, which is detected because
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it has a higher etch rate than the undisturbed material. Etch pits indicate the path of the ions. These etch pits only form in insulators, such as glass (SiO2), but not in semiconductors or metals. Fleischer et al. discuss no fewer than seven models that had been proposed to explain various observations, and find none without difficulties. They conclude that the damage comes from interactions with free carriers, rather than direct atomic scattering, even though the damage consists mainly of displaced atoms. They also conclude that secondary effects, delta rays, can be neglected. To explain how they get displaced atoms from coulomb effects, rather than displacement damage, they coined the term ion explosion spike. The basic idea is that the concentration of ionized atoms in the track region is so high, that coulomb repulsive forces are sufficient to break bonds and move atoms out of their normal positions. Only in insulators, because of their low mobilities, do the carriers stay concentrated in a high-density region long enough for this process to happen. With higher mobility, the carriers would simply diffuse away. The authors dismissed direct displacement damage as a contributing mechanism because the length of the track, determined from the depth of an etch pit, is normally shorter than the nominal range of the ion. Since displacement damage is concentrated at the end of the range, there is usually no track formed where displacement damage is greatest. The idea that ion-induced soft breakdown is associated with defects along the ion path seems to be consistent with experimental observations. For example, Conley183 reported soft breakdown (increased leakage current) with no critical minimum fluence, and no critical field. That is, some leakage was observed with almost the first ion hit, although it scaled with fluence after that. And some increased leakage was observed with no applied field. Of course, there was more leakage at higher fields. The experiments reported by Conley were performed with 3.0 and 3.2 nm oxides, but results are somewhat different in thicker oxides. For example, Sexton et al.189 performed similar experiments on thicker, 7.0 nm, oxides, with qualitatively different results. There was no detectable increase in leakage with the first ion hit—a significant fluence had to accumulate first. Nor were effects observed at zero bias. Typically, 3V applied and 107 ion/cm2 were the points at which increased leakage current was observed. Why the results should change qualitatively in this fashion with oxide thickness is not clear. Undoubtedly, further studies should be done, and will be done to shed more light on these questions. Perhaps the thicker oxides can be viewed macroscopically—an amorphous material, if disordered by an ion, is still an amorphous material. If it is thick enough, there may be no detectable electrical effects, even if some atoms are in new positions. In a thinner oxide, on the other hand, the oxide is only a few atomic planes thick to begin with, so one or two atoms out of position can cause measurable change in the electrical properties of the oxide. Results so far suggest that even the first incident ion can cause soft breakdown in thin enough oxides, and the reliability of the devices may be very poor after that. It seems clear that if these results are confirmed in future studies, the use of very thin oxides in space electronic systems will be a critical reliability problem.
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4.0
Software Solutions
The goal in a system program is not to eliminate SEE, but to get to a manageable error rate. The software tools, for handling errors, clearly have a major influence in determining what error rate is manageable. To fully cover this topic would be far beyond the scope of this short course, but we want to touch on a couple of the most important points.
4.1 Error correction The most widely used technique for error correction is called a Hamming code.190, 191 . If the word length is 2n bits, n+1 bits are necessary for single error detection and correction. One more bit is necessary for double error detection. For example, in a 64-bit word, n=6, and n+2=8 bits necessary for double error detection, single error correction.
4.2 Built-in Self Test (BIST) BIST, or built-in self test, is an idea that has received a certain amount of attention in the commercial industry, starting many years ago now. ASICs and logic chips have had self- testing features for many years. But the idea has been attractive for memories also. The idea is to build in test hardware, and embedded software, so that a chip can test itself, and fix itself if failed components are found. As the level of integration increases, chips are more difficult to test, and the system impact increases if one of them fails, so the concept is very attractive. The problem in memories has been that the area required for the BIST hardware raises the chip cost, more than the benefits have justified.98, 192-195 One early BIST approach added about a third to the chip area, which corresponds to a one-third cost increase. In a mature memory technology, BIST could not improve the yield by anywhere close to on third, so it was not cost effective. For this reason, no company had used BIST on any product memory chip, although many companies had experimented with it. Recently, however, there has been some progress at reducing the area required to implement BIST. One paper claimed the area penalty for their approach was less than one percent, about 0.6 percent. If this approach works as well as claimed, companies might really implement BIST on product memory chips. BIST would be attractive from a radiation point of view, because it would be a complete solution for stuck bits, for example. On chip test hardware would identify failed bits, and replace them with backup bits. This ability would be useful for any other reliability problem, as well.
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5.0 Conclusion This might seem like a good place to make predictions, except that we have shown that making predictions is not only difficult, but also dangerous. Even so, a few things seem clear. One is that scaling will continue, not forever, but for a reasonable time, yet. Scaling is the reason we have SEE, and the ability to control SEE is one of the main factors that control how fast scaling can proceed in the future. Of, course, SEE is a critical problem for military and space systems, but it is also an important commercial problem, and will remain so. Acknowledgments: The author wishes to thank Ken LaBel and Lew Cohn for their support, and Martha O’Bryan for assistance with the Figures and the manuscript.
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2003 IEEE NSREC Short Course
Section V
RADIATION EFFECTS IN SiGe HBT BICMOS TECHNOLOGY
John Cressler Georgia Tech
Radiation Effects in SiGe HBT BiCMOS Technology John D. Cressler School of Electrical and Computer Engineering 777 Atlantic Drive, N.W. Georgia Institute of Technology, Atlanta, GA 30332-0250, USA Tel: (404) 894-5161 / Fax: (404) 894-4641 / e-mail:
[email protected]
Abstract We present an overview of radiation effects in advanced silicon-germanium heterojunction bipolar transistor (SiGe HBT) BiCMOS technology. We begin by reviewing SiGe materials and devices, and then examine the impact of ionizing radiation on both dc and ac performance of SiGe HBTs. We next discuss the circuit-level impact of radiation-induced changes in the transistors, followed by a look at the modeling and understanding of single-event phenomena in SiGe HBT circuits. While ionizing radiation degrades both the dc and ac performance of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. While technology scaling negatively impacts the TID response of the SiGe HBT, it naturally improves the hardness of the CMOS devices, and thus 100krad tolerance of the full BiCMOS technology can be achieved without radiation-hardening at the 120 GHz fT SiGe HBT, 0.10 µm CMOS technology node. Taken together, SiGe HBT BiCMOS technology offers many interesting possibilities for SoC applications of space-borne electronic systems.
I. M OTIVATION are currently two recent but rapidly growing thrusts within the space community: 1) the T here use of commercial-off-the-shelf (COTS) parts whenever possible for space-borne systems as a cost-saving measure; and 2) the use of system-on-a-chip integration to lower chip counts and system costs, as well as simplify packaging and lower total system launch weight. The "holy-grail" in the realm of space electronics can thus be viewed as a conventional terrestrial IC technology with a system-on-a-chip capability, which is also radiation-hard as fabricated, without requiring any additional process modifications or layout changes. It is within this context that we discuss SiGe HBT BiCMOS technology as potentially such a "radiation-hard-as-fabricated" IC technology with possibly far-ranging implications for the space community. This work was supported by DTRA under the Radiation Tolerant Microelectronics Program, NASA-GSFC under the Electronics Radiation Characterization (ERC) Program, NAVSEA Crane, the Auburn University CSPAE, the SRC, NSF, and an IBM University Partner Award. V-1
II. T HE D REAM : B ANDGAP E NGINEERING IN S ILICON While the concept of combining Si and Ge into an alloy for use in transistor engineering is an old one, only in the past decade has this concept been reduced to practical reality. As wonderful as Si is from an IC manufacturing viewpoint, from a device designer’s perspective, Si is hardly the ideal semiconductor. The carrier mobility for both electrons and holes in Si is comparatively small, and the maximum velocity that these carriers can attain under high electric fields is limited to about 1x107 cm/sec under normal conditions. Since the speed of a device ultimately depends on how fast the carriers can be transported through the device under sustainable operating voltages, Si can thus be regarded as a somewhat "slow" semiconductor. In addition, because Si is an indirect gap semiconductor, light emission is painfully inefficient, making active optical devices such as diode lasers impractical. Many of the III-V compound semiconductors (e.g., GaAs or InP), on the other hand, enjoy far higher mobilities and saturation velocities, and because of their direct gap nature, generally make efficient optical devices. In addition, III-V devices, by virtue of the way they are grown, can be compositionally altered for a specific need or application (e.g., to tune the light output of a diode laser to a specific wavelength). This atomic-level custom tailoring of a semiconductor is called bandgtap engineering, and yields a large performance advantage for III-V technologies over Si [1]. Unfortunately, these benefits commonly associated with III-V semiconductors pale in comparison to the practical deficiencies associated with making highly integrated, low-cost ICs from these materials. There is no robust thermally grown oxide for GaAs or InP, for instance, and wafers are smaller with much higher defect densities, more prone to breakage, poorer heat conductors, etc. These deficiencies translate into generally lower levels of integration, more difficult fabrication, lower yield, and ultimately higher cost.
SiGe Thickness (nm)
120 100
Ge 1 Ge 2 Ge 3
Relaxed
80
H=1000 nm H=80 nm H=40 nm H=0 nm
60 40 20 0 0.00
Stable
0.05
0.10 0.15 0.20 Average Ge Fraction
0.25
Fig. 1. SiGe strained-layer thermodynamic stability diagram comparing theoretical stability calculations with example SiGe profiles.
V-2
While Si ICs are well suited to high-transistor-count, high-volume microprocessors and memory applications, RF and microwave circuit applications, which by definition operate at significantly higher frequencies, generally place much more restrictive performance demands on the transistor building blocks. In this regime, the poorer intrinsic speed of Si devices becomes problematic. That is, even if Si ICs are cheap, they must deliver the required device and circuit performance to produce a competitive system at a given frequency. If not, the higher-priced but faster III-V technologies will dominate (as they indeed have until very recently in the RF and microwave markets). The fundamental question then becomes simple and eminently practical: is it possible to improve the performance of Si transistors enough to be competitive with IIIV devices for RF and microwave applications, while preserving the enormous yield, cost, and manufacturing advantages associated with conventional Si fabrication? The answer is clearly yes, a process ultimately culminating in the SiGe HBT. While the development of SiGe HBT technology proceeded from an intent towards terrestrial needs, and thus has little to do with space applications per se, it will be argued that its inherent radiation tolerance makes it an IC technology worthy of consideration for the space environment. Such serendipitous events are commonplace in the high-tech world. ∆Eg,Ge (x = 0) ∆Eg,Ge (x = Wb)
e–
EC
p–SiGe base
+
n Si
h+
emitter
EV
Ge
n– Si collector
p–Si
Fig. 2. Energy band diagram for a Si BJT and graded-base SiGe HBT, both biased in forward active mode at low-injection.
While the basic idea of using SiGe alloys to bandgap-engineer Si devices dates to the 1950s, the synthesis of defect-free SiGe films proved surprisingly difficult, and device-quality SiGe films were not successfully produced until the mid-1980s. This difficulty has a very obvious physical underpinning. While Si and Ge can be combined to produce a chemically stable alloy, their lattice constants differ by roughly 4.2% and thus SiGe alloys grown on Si substrates are compressively strained. This process is referred to as pseudomorphic growth of strained SiGe on V-3
Si, with the SiGe film adopting the underlying Si lattice constant. These SiGe strained layers are subject to a fundamental stability criterion limiting their thickness for a given Ge concentration [2], [3]. Deposited SiGe films that lie below the stability curve are thermodynamically stable, and can be processed using conventional furnace or rapid-thermal annealing, or ion-implantation without generating defects (Figure 1). Deposited SiGe films that lie above the stability curve, however, are "metastable" and will relax to their natural lattice constant (> Si) if exposed to temperatures above the original growth temperature, generating device-killing defects in the process. For a manufacturable SiGe technology, it is obviously key that the SiGe films remain stable after processing, and thus thermodynamic stability constraints are a necessary fact-of-life in the SiGe world. III. T HE S I G E HBT Introducing Ge into Si has a number of consequences for devices. First and most important, because Ge has a larger lattice constant than Si, the energy bandgap of Ge is smaller than that of Si (0.66 eV vs 1.12 eV), and thus SiGe will have a bandgap smaller than that of Si, making it a suitable candidate for bandgap engineering in Si. The compressive strain associated with SiGe alloys produces an additional bandgap shrinkage, and the net result is a bandgap reduction of approximately 75 meV for each 10% of Ge introduced. This Ge-induced "band offset" occurs predominantly in the valence band, making it conducive for use in tailoring npn bipolar transistors. In addition, the compressive strain lifts the conduction and valence band degeneracies at the band extremes, effectively reducing the density-of-states and improving the carrier mobilities with respect to pure Si (the latter due to a reduction in carrier scattering). Because a practical SiGe film must be very thin if it is to remain stable and hence defect free, it is a natural candidate for use in the base region of a bipolar transistor (which by definition must be thin to achieve high-frequency operation). The resultant device contains an n-Si / p-SiGe emitter-base heterojunction and a p-SiGe / n-Si base-collector heterojunction, and thus this device is properly called a "SiGe heterojunction bipolar transistor." The SiGe HBT represents the first practical bandgap-engineered transistor in the Si material system. To intuitively understand how these band edge changes affect the dc operation of the SiGe HBT, first consider the operation of the Si BJT. When VBE is applied to forward bias the EB junction, electrons are injected from the electron-rich emitter into the base across the EB potential barrier (refer to Figure 2). The injected electrons diffuse across the base, and are swept into the electric field of the CB junction, yielding a useful collector current. At the same time, the applied forward bias on the EB junction produces a back-injection of holes from the base into the emitter. If the emitter region is doped heavily with respect to the base, however, the density of back-injected holes will be small compared to the forward-injected electron density, and hence a finite current gain β ∝ n/p results. As can be seen in Figure 2, the introduction of Ge into the base region has two tangible dc consequences: 1) the potential barrier to injection of electrons from emitter into the base is decreased. Intuitively, this will yield exponentially more electron injection for the same applied VBE , translating into higher collector current and hence higher current gain, provided the base current remains unchanged. Given that band edge effects generally couple strongly to transistor properties, we naively expect a strong dependence of JC on Ge content. Of practical consequence, the introduction of Ge effectively decouples the base doping from the current gain, thereby providing device designers with much greater flexibility than in Si BJT design. If, for V-4
instance, the intended circuit application does not require high current gain (as a rule of thumb, β = 100 is usually sufficient for most circuits), we can effectively trade the higher gain induced by the Ge band offset for a higher base doping level, leading to lower net base resistance, and hence better dynamic switching and noise characteristics. 2) The presence of a finite Ge content in the CB junction will positively influence the output conductance of the transistor, yielding higher Early voltage. While it is more difficult to physically visualize why this is the case, in essence, the smaller base bandgap near the CB junction effectively weights the base profile (through the integral of intrinsic carrier density across the base), such that the backside depletion of the neutral base with increasing applied VCB (Early effect) is suppressed compared to a comparably doped Si BJT. This translates into a higher Early voltage compared to a Si BJT. To intuitively understand how these band edge changes affect the ac operation of the SiGe HBT, first consider the dynamic operation of the Si BJT. Electrons injected from the emitter into the base region must diffuse across the base (for constant doping), and are then swept into the electric field of the CB junction, yielding a useful (time-dependent) collector current. The time it takes for the electrons to traverse the base (base transit time) is significant, and typically is the limiting transit time that determines the overall transistor ac performance (e.g., peak cutoff frequency fT ). At the same time, the applied forward bias on the EB junction dynamically produces a back-injection of holes from the base into the emitter. For fixed collector bias current, this dynamic storage of holes in the emitter (emitter charge storage delay time) is reciprocally related to the ac current gain of the transistor (βac ).
SiGe HBT Publications
160 140
IEEE Journals + Conferences
120 100 80 60 40 20 0 1988 1990 1992 1994 1996 1998 2000 2002 Publication Year
Fig. 3. Historical trends in the yearly number of SiGe HBT papers published in IEEE journals and conferences (source: IEEE Xplore).
As can be seen in Figure 2, the introduction of Ge into the base region has an important consequence, since the Ge-gradient-induced drift field across the neutral base is aligned in a direction (from collector to emitter) such that it will accelerate the injected minority electrons V-5
across the base. We are thus able to add a large drift field component to the electron transport, effectively speeding up the diffusive transport of the minority carriers and thereby decreasing the base transit time. Even though the band offsets in SiGe HBTs are typically small by III-V technology standards, the Ge grading over the short distance of the neutral base can translate into large electric fields. For instance, a linearly graded Ge profile with a modest peak Ge content of 10%, graded over a 50-nm neutral base width, yields 75 mV / 50 nm = 15 kV/cm electric field, sufficient to accelerate the electrons to near saturation velocity (vs ' 1x107 cm/sec). Because the base transit time typically limits the frequency response of a Si BJT, we would expect that the frequency response should be significantly improved by introducing this Ge-induced drift field. In addition, we know that the Ge-induced band offset at the EB junction will exponentially enhance the collector current density (and thus β) of a SiGe HBT compared to a comparably constructed Si BJT. Since the emitter charge storage delay time is reciprocally related to β, we would also expect the frequency response to a SiGe HBT to benefit from this added emitter charge storage delay time advantage. Perhaps most importantly, SiGe HBTs can be quite easily teamed with best-of-breed Si CMOS to form a monolithic SiGe HBT BiCMOS technology. While this might seem at first glance to be a mundane advantage, it is in fact a fundamental enabler for SiGe’s long-term success, provided SiGe HBTs can be realized without an excessive cost penalty compared to standard Si ICs. The integration of SiGe HBTs with Si CMOS is also the fundamental departure point between SiGe technology and III-V technologies. If SiGe technology is to be successful in the long haul, it must bring to the table the RF and analog performance advantages of the SiGe HBT, and the low-power logic, integration level, and memory density of Si CMOS, into a single cost-effective IC that enables SoC integration (i.e., SiGe HBT BiCMOS). This merger appears to be the path favored by most companies today. Typically, SiGe HBTs (often with multiple breakdown voltages) exist as an "adder" to a basic CMOS IC building-block core, to be swapped in or out as the application demands, without excessive cost burden. Typical state-of-the-art SiGe HBT BiCMOS technologies generally have a roughly 20% adder in mask count compared to "vanilla" digital CMOS, and are viewed by many as an acceptable compromise between performance benefit and cost, depending on the application. In truth, SiGe HBT BiCMOS technologies are the future of the SiGe HBT, since it enables system-on-a-chip solutions across a very broad market base for both wired and wireless applications, all at an acceptable cost. This is clearly the evolutionary path being traveled today by almost all companies with commercially viable SiGe technologies. IV. A B RIEF H ISTORY OF S I G E T ECHNOLOGY The concept of the HBT is an old one, dating to the fundamental BJT patent issued to Shockley in 1951 [4]. Given that the first bipolar transistor was built from Ge, it seems quite likely that Shockley even envisioned the combination of Si and Ge to form a SiGe HBT. The basic formulation and operational theory of the HBT was pioneered by Kroemer, and was in place by 1957 [5], [6]. Reducing the SiGe HBT to practical reality, however, took 30 years due to material growth limitations. Once device-quality SiGe films were achieved in the mid-1980s, progress was quite rapid from that point forward (for important historical references in the SiGe field, refer to [4] - [30]). The first functional SiGe HBT was demonstrated in December of 1987 [13], but worldwide attention became squarely focused on SiGe technology in June of 1990 with the demonstraV-6
225 200 Peak fT (GHz)
175 150 125 100
IBM Hitachi Conexant Infineon NEC IHP IMEC
TI Philips Lucent ST Micro TEMIC CNET
75 50 25 0 1990 1992 1994 1996 1998 2000 2002 Year
Fig. 4. Reported cutoff frequency versus year for a variety of different industrial SiGe HBT technologies.
tion of a non-self-aligned SiGe HBT grown by ultra-high vacuum/chemical vapor deposition (UHV/CVD), with a peak cutoff frequency of 75 GHz [15], [16]. At the time, this SiGe result was roughly twice the performance of state-of-the-art Si BJTs, and clearly demonstrated the future performance potential of the technology. Eyebrows were lifted, and work to develop SiGe as a practical circuit technology began in earnest in a large number of laboratories around the world. In December of 1990, the first emitter-coupled-logic (ECL) ring oscillators using self-aligned, fully integrated SiGe HBTs were produced [17]. The first SiGe BiCMOS technology was reported in December of 1992 [19], and the first LSI SiGe HBT circuit (a 1.2 GSample/s 12-bit digital-to-analog converter) was demonstrated in December of 1993 [20]. The first SiGe HBTs with frequency response greater than 100 GHz were described in December of 1993 [21], [22], and the first SiGe HBT technology entered commercial production on 200-mm wafers in December of 1994 [23]. The 200-GHz peak fT barrier was broken in November of 2001 for a non-self-aligned device [29], and for a self-aligned device in February of 2002 [33]. SiGe HBT technologies with fT above 300 GHz are clearly a realistic goal at this point [34], making SiGe HBTs quite competitive in performance with best-of-breed competing III-V HBT technologies. Not surprisingly, research and development activity in SiGe devices, circuits, and technologies in both industry and at universities worldwide has grown rapidly since the first demonstration of a functional SiGe HBT in 1987. This global interest is nicely reflected in the number of SiGe HBT technical publications in IEEE journals and conferences from 1987 until present, as shown in Figure 3. During the evolutionary path of SiGe HBTs, a large number of SiGe HBT device technologies have been demonstrated at laboratories throughout the world, using a variety of different
V-7
Fig. 5. Schematic cross section of a representative first generation SiGe HBT, drawn through first metal. Drawing is not to scale.
SiGe epitaxial growth techniques. Commercial SiGe HBT technologies now exist in companies around the world, including: IBM [33], Hitachi [35], Conexant (Jazz) [36], Infineon [37], NEC [38], IHP [39], IMEC [40], TI [41], Philips [42], Lucent [43], ST Microelectronics [44], TEMIC [45], and CNET [46]. In recent years, these various SiGe HBT technologies have been leveraged to demonstrate a large number of impressive digital, analog, RF, and microwave circuit results for wireless and wireline communications applications. A large number of commercial products using SiGe HBTs are currently on the market, and a foundry service through MOSIS for SiGe HBT BiCMOS technology is available, all healthy signs for a new device technology. A variety of review papers on SiGe materials, devices, circuits, and technologies can be found in the literature [47]–[63], and five books dealing in one way or another with SiGe materials and devices have been published [64]–[68]. V. T HE S I G E HBT T ECHNOLOGY P LAYING F IELD It is important to develop a "feel for the numbers" of the various SiGe technology generations currently in existence globally. Of interest in this context is what a generic SiGe HBT of a given technology generation looks like in cross section, what its doping profiles are likely to be, and what level of transistor performance can be expected. We are after rules-of-thumb from which one can more easily compare and contrast the various SiGe technologies that either currently exist or will in the future. We limit our discussion here to only self-aligned, fully integrated, Si-processing-compatible SiGe HBT technologies that have been reported in the literature. Figure 4 shows the historical trend in peak fT from the first self-aligned device demonstration in 1990 until present. It is meaningful in this context to distinguish between different SiGe technology generations, as defined by the ac performance of the SiGe HBT (e.g., peak fT , which is a very strong function of the vertical profile and hence nicely reflects the degree of sophistication in structural design, thermal cycle, epi growth, etc.). We thus label a SiGe HBT technology having a SiGe HBT with a peak fT of 45–55 GHz as "first generation," that with a peak fT of 100–120 GHz as "second generation," and that with a peak fT of 200+ GHz as "third V-8
n– collector
p–SiGe base
10
1021
Xj (eb) = 35 nm Wb (met) = 90 nm
As
1020 1019
As
Ge
5.0
P
1018 B
17
10
1016
7.5
poly
0
2.5
200
400 Depth (nm)
600
Germanium (%)
Dopant Concentration (cm–3)
n+ emitter
0 800
Fig. 6. Measured SIMS profile of a representative first generation SiGe HBT.
generation." TABLE I R EPRESENTATIVE S I G E HBT P ARAMETERS FOR T HREE D ISTINCT S I G E HBT B I CMOS T ECHNOLOGY G ENERATIONS
Parameter WE ,eff (µm) peak β VA (V) BVCEO (V) BVCBO (V) peak fT (GHz) peak fmax (GHz) min. NFmin (dB)
First Second Third 0.42 0.18 0.12 100 200 400 65 120 > 150 3.3 2.5 1.7 10.5 7.5 5.5 47 120 207 65 100 285 0.8 0.4 < 0.3
Regardless of the integration approach and processing steps employed, there are numerous common fabrication elements and modules which exist among the various SiGe HBT technologies, and include for a typical first generation SiGe HBT: + − • A starting n subcollector (e.g., 5–10 Ω/2) on a p substrate (e.g., 10–15 Ω-cm), probably utilizing a patterned subcollector to allow CMOS integration; 15 −3 • A high-temperature, lightly doped n-type collector epi (e.g., 0.4–0.6 µm thick at 5x10 cm ); • Polysilicon-filled deep trenches for isolation of adjacent device subcollectors (e.g., 0.8–1.2 µm wide and 7–10 µm deep); V-9
Oxide-filled shallow trenches (or perhaps LOCOS) for local device isolation (e.g., 0.4–0.6 µm thick and planarized using chemical-mechanical-polishing (CMP)); 2 • An implanted collector "sinker" or "reach-through" to the subcollector (e.g., 10–20 Ωµm ); • A composite SiGe epi layer consisting of a Si buffer, boron-doped SiGe (with or without C doping) active layer, and a Si cap. For example, the Si buffer layer might be 10–20 nm thick, followed by a boron-containing (1 − 3x1013 cm−2 integral boron charge) SiGe (or SiGeC) layer 70–100 nm thick, and a Si cap layer 10–30 nm thick; • A variety of emitter-base self-alignment schemes "borrowed" from Si BJT technology to be used depending on the device structure and SiGe deposition approach (single-poly, double-poly, etc.). All self-alignment schemes employ some type of emitter-base "spacer" (e.g., 0.1–0.3 µm wide); • A local collector implantation used to improve high-JC performance and enable breakdown voltage tuning (e.g., 0.5 − 1x1017 cm−3 at the metallurgical CB junction, and graded upward toward the subcollector). This is the self-aligned, selectively implanted collector (SIC) long used in Si BJT technology; • Polysilicon extrinsic base contacts (usually the SiGe epi layer deposited over the shallow trench) with additional self-aligned extrinsic base implants to lower the total sheet resistance; • A silicided extrinsic base (e.g., 5–10 Ω/2); 20 • A heavily-doped (e.g., > 5x10 cm−3 ) polysilicon emitter, either implanted or in-situ doped (e.g., 150–200 nm thick); • A variety of multilevel back-end-of-the-line (BEOL) metalization schemes (either Al-based or Cu). These are typically "borrowed" from existing CMOS processes, and might include 3 to 6 levels. They usually consist of small tungsten (W) studs between metal layers, using CMPplanarized oxide interlayers; These technology elements can be located in the schematic cross section of a first generation SiGe HBT shown in Figure 5. A representative first generation SIMS doping and Ge profile is shown in Figure 6. The metallurgical base width is about 90 nm (about 65-nm neutral base width under forward-active bias), the metallurgical emitter junction depth is about 35 nm (from the Si surface), and the peak Ge content is about 8% (it is thermodynamically stable). The emitter polysilicon layer is doped to solid-solubility limits, multiple self-aligned phosphorus implants are used to locally tailor the collector doping profile, and the peak base doping is about 4x1018 cm−3 (Rbi ∼ = 6 kΩ/2). The Ge profile is trapezoidal in shape, with substantial grading across the neutral base. This vertical profile design can be considered quite conservative by today’s standards, but it nonetheless achieves a peak fT of 50 GHz (70-GHz peak fmax ) at a BVCEO of 3.3 V, solidly in the range of a first generation technology. Cross-company typical profile numbers for first generation SiGe technologies are: Wb0 = 60 − 90 nm, We = 20 − 40 nm, peak Ge = 8–15%. Those acquainted with Si BJT technologies will recognize the striking similarity in doping profiles between this SiGe HBT and advanced ion-implanted Si BJTs (just removing the Ge makes it look like a high-speed Si BJT). The key difference between this SiGe HBT and a conventional ion-implanted double-poly Si BJT lies in the base profile, which can be much more heavily doped at a given base width using epitaxial growth (leading to much lower base resistance and better dynamic response). The observed broadening of the final boron profile in this SiGe HBT (Figure 6) is a direct measure of the total process thermal cycle the post-deposited epi-layer sees (the boron is deposited as an atomically-abrupt box about 10 nm wide), which is •
V-10
usually gated by the requisite oxidation steps, and the emitter/extrinsic base anneal (typically shared and done with RTA). It is also key to appreciate that this epi-base scheme employed in SiGe HBTs is extendable to much more aggressive dimensions as the technology scales for higher performance, whereas an implanted base Si BJT would be nearly at its practical scaling limit at 90-nm base width.
Cutoff Frequency (GHz)
250 200 150
0.12 µm (3rd generation) 0.18 µm (2nd) 0.50 µm (1st)
VCB = 1.0 V
10x
100 50 0 0.1
1.0 Collector Current (mA)
10.0
Fig. 7. Measured cutoff frequency data as a function of bias current for three different SiGe HBT technology generations.
Table I compares the resultant SiGe HBT performance of three SiGe HBT technology generations. Within some reasonable error bar, all existing SiGe technologies, no matter the company, are reasonably similar in performance to the values shown. This fact, which might seem initially surprising at first glance, actually makes sense, given that the target application markets (and hence the required transistor-level performance) are basically the same, independent of company. As a general rule of thumb, first generation SiGe technologies are being currently used to support circuit needs for the global 900-MHz and 2.4-GHz RF cellular markets (both GSM and CDMA), for both handsets and base stations, 1–2.5-Gbit/sec Ethernet applications, Bluetooth, 4–6-GHz WLAN, GPS, and 10-Gbit/sec (OC-192) synchronous optical networks (SONET) transmit-and-receive (T/R) modules (to name a few) [63]. Second generation SiGe technologies are being targeted for 40-Gbit/sec networks and X-band (10 GHz) microwave systems, while emerging third generation SiGe technologies are being positioned for 80-Gbit/sec networks and 60 GHz WLAN communications systems. VI. P ERFORMANCE L IMITS AND F UTURE D IRECTIONS The maximum achievable frequency response in manufacturable SiGe HBT technology has clearly proven to be much higher than even the blind optimists might have guessed. Fully integrated SiGe HBT BiCMOS technologies with peak fT and peak fmax above 200 GHz exist in V-11
Base and Collector Currents (A)
10–3 10–5
8% SiGe HBT AE = 0.5 x 2.5 µm2 VCB = 0.0 V
10–7
300K Pre–radiation 1012 p/cm2 1013 p/cm2 1014 p/cm2
10–9 10–11 0.2
0.4
0.6
0.8
1.0
Base–Emitter Voltage (V)
1.2
Fig. 8. Gummel characteristics as a function of proton fluence.
2002 (at several different labs). Figure 7 compares the measured cutoff frequency characteristics of three distinct SiGe HBT BiCMOS technology generations [69]. Several important points concerning projected performance limits in SiGe can be gleaned from these results: • Given that the three successive SiGe technology generations shown in Figure 7 were reported in 1994, 2000, and 2002, respectively, it is apparent that once first generation SiGe technology stabilized in the manufacturing environment, progress in raising the SiGe HBT performance has been exceptionally rapid. This is clearly a good sign for the future. • Third generation SiGe HBTs have comparable raw performance to the best commercially available III-V HBT technologies (both GaAs-based and InP-based, which are in the 150–200GHz peak fT range currently), while preserving their compatibility with standard Si CMOS technologies, and the enormous economy of scale of conventional Si fabrication. This does not bode well for the (long-promised) broad application of III-V HBT technologies, except perhaps in high-power applications and the lightwave environment. • The only long-term viable path for III-V HBTs to follow would appear to be towards developing (Si-like) self-alignment schemes and hence aggressive scaling of the transistor dimensions (for much higher performance). This will likely prove to be a nontrivial feat even in "fabricationfriendlier" III-V materials such as InP. Clearly, any path towards integration of III-V HBTs with Si CMOS is daunting task. • The peak fT in each successive SiGe technology generation occurs at roughly the same bias current, meaning that the collector current density is rising rapidly to achieve the levels of demonstrated performance (to the range of 10 mA/µm2 for third generation technology). This JC increase over time is not unexpected from bipolar scaling theory, but there is obviously some practical bound for maintenance of sufficient device reliability. • These high current densities can produce significant self-heating in these transistors, but even in this case, the generally excellent thermal properties of Si substrates give SiGe an advantage V-12
Current Gain (IC/IB)
200 150
8% SiGe HBT AE = 0.5 x 2.5 µm2 VCB = 0.0 V T = 300K
Pre–radiation 1012 p/cm2 1013 p/cm2 1014 p/cm2
100 50 0 10–12
10–10
10–8
10–6
Collector Current (A)
10–4
10–2
Fig. 9. Current gain as a function of bias current for multiple proton fluences.
over competing III-V HBT technologies. The calculated junction temperature rise for a SiGe HBT operated at 150 GHz is about 3× lower than for a scaled InP HBT [69]. • One of the most important advantages offered by the best-of-breed SiGe HBT technologies is that they offer substantial leverage in power savings. As shown in Figure 7, one can operate third generation SiGe HBTs at 120 GHz, sufficient for most 40-GB/sec applications, while decreasing the bias current by an order-of-magnitude compared to (the already impressive) second generation technology! This power savings potential for SiGe clearly holds great leverage for portable (battery-limited) system applications, but given the power-density constraints being placed across the board on both emerging wired and wireless systems, this ability to deliver high-performance at very low power may ultimately prove to be the key long-term enabling feature of SiGe technology. VII. T HE E FFECTS OF R ADIATION ON S I G E HBT S The response of SiGe HBTs to a variety of radiation types has been reported, including: gamma rays [70], neutrons [71], and protons [72], [73]. Since protons induce both ionization and displacement damage, they can be considered the worst case for radiation tolerance. For the following results, a relevant proton energy of 46 MeV was used, and at the highest proton fluence (1x1014 p/cm2 ), the measured equivalent gamma dose was over 1.5 Mrad(Si), far larger than most orbital missions require. Proton energy effects are discussed below. A. Transistor dc Response The typical response of a SiGe HBT to irradiation can be seen in Figure 8, which shows typical measured Gummel characteristics of the 0.5 × 2.5µm2 SiGe HBT, both before and after exposure to protons [72]. As expected, the base current increases after a sufficiently high proton fluence due to the production of G/R trapping centers, and hence the current gain of the device V-13
Fig. 10. Calibrated MEDICI simulation of the recombination rates inside the SiGe HBT after radiation.
degrades. There are two main physical origins of this degradation. The base current density is inversely proportional to the minority carrier lifetime in the emitter, so that a degradation of the hole lifetime will induce an increase in the base current. In addition, ionization damage due to the charged nature of the proton fluence produces interface states and oxide trapped charges in the spacer layer at the emitter-base junction. These G/R centers also degrade IB , particularly if they are placed inside the EB space charge region, where they will yield an additional nonideal base current component (non-kT/q exponential voltage dependence). By analyzing a variety of device geometries, it can be shown that the radiation-induced excess base current is primarily associated with the EB spacer oxide at the periphery of the transistor, as naively expected [70]. The degradation of the current gain as a function of collector current for the preirradiated sample, and after exposure to three proton fluences, is shown in Figure 9. For fluences up to 1x1013 p/cm2 the peak current gain at 10 µA does not show a visible degradation, and at 1x1014 p/cm2 a degradation of only about 8% compared to the preirradiated device is observed. This suggests that these SiGe HBTs are robust to TID for typical orbital proton fluences for realistic circuit operating currents above roughly 100 µA without any additional radiation hardening. These results are significantly better than for conventional diffused or even ion-implanted Si BJT technologies (even radiation-hardened ones). Small, but observable, changes in the post-irradiated collector current were also observed. Previous neutron and gamma irradiation studies of SiGe HBT technology also showed small but observable changes in the collector current with increasing radiation levels. This observed collector current shift with radiation fluence is caused by the shrink of the neutral base boundary on both the emitter and collector side due the modulation of the net charge density in the space V-14
fT and fmax (GHz)
80
Pre–radiation 5x1013p/cm2
60
fmax
fT
40
AE=0.5x20x2µm2 VCB=1V
20 0
1
10 IC (mA)
100
Fig. 11. Cutoff frequency and maximum oscillation frequency as a function of bias current for multiple proton fluence.
charge region by the radiation-induced traps. This effectively reduces the base Gummel number (narrower base), thereby increasing the collector current. (Previous studies using neutron irradiation [71] indicate that base dopant deactivation due to displacement is a small effect in these devices due to their very thin base widths.) In the present graded-base SiGe HBT, the collector current depends exponentially on the Ge content seen at the EB side of the neutral base, and is therefore expected to show a stronger change in IC with radiation compared to a Si BJT with a comparable doping profile, and the experimental data confirm this, where the SiGe HBT collector current increases by 35% over its original value, while there is no observable shift in IC for the Si BJT. In addition, 2-D simulations were used to confirm the understanding of this phenomenon. By introducing a trap density inside the EB and CB space charge regions, a qualitative match with the observed trends was obtained. Interestingly, it was found that both the trap density inside the volume of the device and the energy location of the trap (i.e., either donor or acceptor level trap) strongly influences the nature of the redistribution of the post-irradiated EB and CB space charge region and hence the change of IC with damage (both in magnitude and direction of change – i.e., it can in principle produce an increase or decrease in IC ). This may potentially explain the differences in the observed IC change with radiation for neutron and proton samples (IC increased with increasing fluence for protons [72], but decreased for neutrons [71]). B. Spatial Location of the Damage Of particular interest is the inference of the spatial location of the proton-induced traps in these devices [72]. The existence of proton-induced traps in the EB space charge region is clearly demonstrated by the G/R-induced increase in the nonideal base current component shown in the V-15
Damage Factor (cm2/particle)
Proton Energy=1.75 MeV Proton Energy=62.5 MeV Proton Energy=195.8 MeV Neutron Energy=1 MeV
10–12 10–14 10–16 10–18 10–7
SiGe HBT 5HP VCB=0V
10–5 10–3 JC (mA/µm2)
10–1
Fig. 12. Extracted damage factor as a function of bias current for 1 MeV neutrons and multiple proton energies.
Gummel characteristics. The existence of radiation-induced traps in the collector-base space charge region was verified by measuring the inverse mode Gummel characteristics of the device (emitter and collector leads swapped). In this case the radiation-induced traps in the CB junction now act as G/R centers in the inverse EB junction, with a signature non-kT/q exponential slope. 2-D simulations were calibrated to both measured data for the pre- and post-irradiated devices at a collector-base voltage of 0.0 V. In order to obtain quantitative agreement between the simulated and measured irradiated results, traps must be located uniformly throughout the device, and additional interface traps must be located around the emitter-base spacer oxide edge (Figure 10). Most of the radiation-induced recombination occurs inside the EB space charge region, leading to a nonideal base current, as expected. C. Transistor ac Response To assess the impact of radiation on the ac performance of the transistors, the S-parameters were measured to 40 GHz both before and after proton exposure. None of the four S-parameters suffered any appreciable degradation up to 1x1014 p/cm2 proton fluences [72], [73]. From measured S-parameters, the transistor cutoff frequency (fT ) and maximum oscillation frequency (fmax ) were extracted. A comparison of these two important ac parameters between preirradiation and 5x1013 p/cm2 is shown in Figure 11. Only a slight degradation in fT and fmax is observed, the latter being expected from the minor increase of the base resistance with irradiation, as described below. Observe that the high current fT roll-off due to Kirk and heterojunction barrier effect is not changed with irradiation. Because the high-current density roll-off is extremely sensitive to the collector doping level, it suggests that there is no appreciable deactivation of donors in the collector due to displacement damage, despite the existence of irradiation-induced traps in the collector.
V-16
Fig. 13. Comparison of damage-factor ratios and calculated NIEL ratios as a function of proton energy for SiGe HBTs (using 1 MeV neutron data as a normalization reference).
D. Si versus SiGe and Structural Aspects Finally, we note that careful comparisons between identically fabricated SiGe HBTs and Si BJTs (same device geometry and wafer lot, but without Ge in the base for the epitaxial-base Si BJT), show that the extreme level of TID tolerance of SiGe HBTs is not per se due to the presence of Ge. That is, the proton response of both the epitaxial base SiGe HBT and Si BJT are nearly identical. We thus attribute the observed radiation hardness to the unique and inherent structural features of the device itself, which from a radiation standpoint can be divided into three major aspects: 19 • In these epitaxial base structures, the extrinsic base region is: 1) very heavily doped (> 5x10 −3 cm ); and 2) located immediately below the EB spacer oxide region, effectively confining any radiation-induced damage, and its effects on the EB junction. • The EB spacer, known to be the most vulnerable damage point in conventional BJT technologies, is thin (< 0.20 µm wide) and composed of an oxide/nitride composite, the latter of which is known to produce an increased level of radiation immunity. • The active volume of these transistors is very small (WE = 0.5 µm, and Wb < 150 nm), and the emitter, base, and collector doping profiles are quite heavily doped, effectively lessening the impact of displacement damage. Further results of the effects of device scaling on radiation response are given below, as well as a discussion of the impact on the CMOS transistors in the SiGe HBT BiCMOS technology intended for system-on-a-chip applications. We also note that these SiGe HBTs compare very favorably in both performance and radiation hardness with (more expensive) GaAs HBT technologies that are often employed in space applications requiring both very high speed and an extreme level of radiation immunity [74].
V-17
Fig. 14. Normalized base current as a function of gamma radiation dose rate, for both Si BJTs and SiGe HBTs.
E. Proton Energy Effects Because incident protons deposit more of their energy (both ionization and displacement) inside the device as their energy decreases, transistor characteristics generally degrade more rapidly under low energy proton irradiation than for high energy proton irradiation. Given that a realistic space environment necessarily contains a wide range of particle energies (from several MeV to hundreds of MeV), characterization of transistor response as a function of energy is important. In order to examine the energy dependence of proton-induced damage in SiGe HBTs, an appropriate "damage factor" must first be defined. It has been repeatedly demonstrated that over a large range of proton energies and device technologies, the reciprocal gain increases linearly with incident particle fluence (φ), as reflected in the Messenger-Spratt equation [76] 1 β(φ)
= β0−1 + K(E) φ,
(1)
where β0 is the preradiation current gain, and K is the (energy-dependent) damage factor. In practice, the reciprocal gain versus proton fluence for bipolar transistors typically only behaves linearly over a certain proton fluence range, since both displacement damage and ionization damage exist for proton irradiation. Therefore, both proton and gamma radiation experiments are in principle needed to determine the damage factor. Conventionally, the following procedure is used to extract the displacement damage factor: 1) plots of reciprocal gain versus total ionizing dose as a function of collector current are made after gamma irradiation; 2) these plots are then approximated by straight lines over the dose range corresponding to the proton irradiation experiments; and finally, 3) the slopes of these plots are then subtracted from the slopes of
V-18
Fig. 15. Normalized base current at multiple VBE values as a function of total dose.
reciprocal gain versus proton fluence curves for the proton irradiation experiments in order to obtain the corresponding damage factor. Figure 12 shows the extracted damage factor as a function of collector current density for these first generation SiGe HBTs as a function of proton energy. Clearly, 1-MeV neutrons, because they produce only displacement damage, represent the most benign form of radiation. Protons are expected to produce more serious damage than either the neutron or gamma irradiation, and this is indeed the case. Furthermore, as the proton energy decreases, in this case from 196 MeV to 63 MeV to 1.8 MeV, more energy is deposited in the devices and the damage factor increases (worsens), as expected [75]. A comparison of measured damage-factor ratios and calculated NIEL ratios as a function of proton energy for SiGe HBTs (using 1 MeV neutron data as a normalization reference) is shown in Figure 13. F. Low-Dose-Rate Gamma Sensitivity Within the past few years, a pronounced low-dose-rate sensitivity to gamma irradiation that is not screened by the current test methods for ionizing radiation has been observed in bipolar technologies [77]. Under military standard 883, method 1019.4, all total-dose tests are performed at a dose rate between 50-300 rad(Si)/sec. The enhancement in device and circuit degradation at low gamma dose rates has come to be known as "Enhanced Low Dose Rate Sensitivity" (ELDRS). The ELDRS effect was first reported in 1991 [78], which demonstrated that existing radiation hardness test assurance methodologies were not appropriately considering worst case conditions. The physical origins underlying ELDRS have been hotly debated for years, and numerous mechanisms proposed. Recent attempts to understand ELDRS include a model suggesting that V-19
3.5
NFmin (dB)
3.0
f=10GHz
2.5
AE=0.5x20x2 µm2 VCB=1V IC=2.6mA
2.0 1.5 1.0 0.5 Pre
f=4GHz f=2GHz
1012 1013 1014 Proton Radiation Fluence (p/cm2)
Fig. 16. Extracted minimum noise figure as a function of proton fluence for multiple frequencies.
the lower net radiation induced trapped charge density (∆Not ) at high-dose-rates is a result of a 0 space charge phenomenon, caused by delocalized hole traps, known as Eδ centers, which occur in heavily damaged oxides such as bipolar base oxides [79]. These traps can retain holes on a timescale of seconds to minutes, causing a buildup of positive charge in the oxide bulk during high-dose-rate irradiation. This is in contrast to low-dose-rate irradiation, where the irradiation 0 time is much longer, effectively allowing the holes in the Eδ centers to be detrapped. Thus, in the high-dose-rate case, the larger total trapped hole density forces holes near the interface to be trapped closer to the interface, where they can be compensated by electrons from the silicon. This lowers the resultant net trapped charge density. It has also been found that these 0 Eδ centers anneal at relatively low temperatures (≤ 150◦ C). This suggests that high-dose-rate irradiation at a higher temperature may allow holes to be detrapped, hence mimicking a lowdose-rate radiation response. The assumptions commonly employed in such models, however, are typically very technology specific, and quantifying ELDRS (if present) in SiGe technology is obviously important from a hardness assurance perspective. To assess ELDRS in SiGe technology, low-dose-rate (0.1 rad(Si)/sec) and high-dose-rate (300 rad(Si)/sec) experiments were conducted using Cobalt-60 (i.e., 1.43-MeV gamma rays) [81]. The devices were irradiated with all terminals grounded to a total dose of 50 krad(Si) and the forward mode and inverse mode characteristics measured at incremental doses. As can be seen in Figure 14, low-dose-rate effects in these SiGe HBTs were found to be nearly nonexistent, in striking contrast to reports of strong ELDRS in conventional Si bipolar technologies. We attribute this observed hardness to ELDRS to the same mechanisms responsible for the overall radiation hardness of the technology, and is likely more structural in nature than due to any unique advantage afforded by the SiGe base. Interestingly, an anomalous decrease in base current was also found in these devices at low-dose-rates (Figure 15), suggesting that a new V-20
15 Pre–radiation 5x1013 p/cm2
rBE (Ω)
13 11 9 7
AE=0.5x20x2µm2 VCB=1V
1
10 IC (mA)
100
Fig. 17. Extracted total base and emitter resistance as a function of bias current, before and after proton exposure.
physical phenomenon is present at low-dose-rates in these devices. In this case, the Gummel characteristics show a decreasing base current until about 5 krad(Si), followed by an increase in base current at higher doses. This suggests that in the initial stages of irradiation, the G/R center dominated recombination process actually decreases in magnitude. For VBE = 0.4 V, this IB decrease is found to be as much as 100%. It is also found that although the base current starts increasing again for total doses ≥ 5 krad(Si), the base current at up to 20 krad(Si) is still equal to its preradiation value. It can thus be inferred that at low-dose-rates two competing mechanisms operate as the total dose increases, one that decreases the G/R leakage, and one that increases the G/R leakage. A logical question, then, is what sort of physical damage process can create such an anomalous base current decrease? In particular, it is important to understand why: 1) under low-dose rate conditions, the normalized base current in the forward-operated SiGe HBT strongly decreases with dose at low VBE , but only weakly decreases with dose at high VBE ; and 2) why the base current first decreases with total dose and then increases. 2-D simulations using MEDICI [80] were used to confirm a plausible explanation for these observations. It is proposed that the preradiation deep-level traps at the surface are initially annealed by the gamma radiation to a shallower energy level. As more deep traps evolve into shallower traps, the G/R center dominated recombination decreases, giving a reduction in base current. This occurs because the net recombination rate decreases as the trap energy level moves away from midgap. The magnitude of the leakage decrease depends on the quasi-Fermi levels and hence the EB bias conditions. As confirmed with simulation, this proposed mechanism can indeed give rise to a decrease in base current at low VBE without a large change at high VBE , consistent with the experimental observations. At the same time, radiation-induced traps are being generated in the device, which ultimately halts the IB decrease and causes an increase in V-21
10–19 SiGe HBT Ae=0.5x1 µm2 IB=4µA pre–irradiation 2e13 p/cm2
SIB (A2/Hz)
10–20 10–21 10–22 10–23
∝1/f
10–24 10–25 100
2qIB
101
102 103 Frequency (Hz)
104
105
Fig. 18. Input-referred base current PSD for a 0.5 × 1.0 µm2 transistor, before and after irradiation.
IB . This occurs because at greater values total dose, the deep-level traps generated by radiation outnumber those annealed to shallower levels. At low VBE , the base current is strongly dependent on the nature and location of traps in the EB junction. In the forward-mode measurements, this junction has shallow-level traps due to annealing and hence a decrease in IB is observed. At higher values of VBE , the higher injection level leads to recombination in the bulk as well, which leads to an IB increase. In the inverse mode measurements, the IB increase observed at low VBE is due to the deep-level trap induced recombination in low-injection. This corresponds to the bulk traps. At higher values of VBE , the higher injection leads to a base current that is dependent on the recombination near the EB spacer at the surface as well. This region, however, has an abundance of shallow-level traps and thus, the recombination actually decreases, leading to an IB decrease. These kinds of proposed trap dynamics, which are known to be dose rate dependent, have been previously reported in the literature [82]. G. Broadband Noise The broadband noise performance of SiGe HBTs, as reflected in NF min , ΓG,opt , and Rn , is critical for space-borne transceivers and communications platforms. Characterization of the transistor S-parameters both before and after proton exposure show minimal changes in fT and fmax , suggesting that noise performance should be relatively unaffected by radiation. As shown in Figure 16, this is indeed the case. For these SiGe HBTs, NF min degrades only slightly at 2.0 GHz after an extreme proton fluence of 5x1013 p/cm2 (from 0.95 dB to a still-excellent value of 1.07 dB, a 12.6% degradation). In the bias range of interest for most RF circuits (> 0.1 mA/µm2 ), these SiGe HBTs show virtually no degradation in current gain for proton fluences up to 5x1013 p/cm2 . Therefore, at fixed bias current, the observed minimal degradation in noise figure results mostly from the V-22
10–19
SIB (A2/Hz)
10–20
SiGe HBT Ae=0.5x10 µm2 IB=4µA pre–irradiation 2e13 p/cm2
10–21 10–22 10–23
∝1/f
10–24 10–25 100
2qIB
101
102 103 Frequency (Hz)
104
105
Fig. 19. Input-referred base current PSD for a 0.5 × 1.0 µm2 transistor, before and after irradiation.
increase in thermal noise associated with the base and emitter resistances (Figure 17). Changes in ΓG,opt and Rn are also small. H. Low-Frequency Noise SiGe HBTs have the desirable feature of low 1/f noise commonly associated with Si bipolar transistors [83], which is of great importance because upconverted low-frequency noise (phase noise) typically limits the spectral purity of communication systems. Understanding the effects of radiation on 1/f noise in SiGe HBTs thus becomes a crucial issue for space-borne communications electronics. To shed light on these issues, the noise power spectrum was measured on SiGe HBTs from 1.0 Hz to 100.0 kHz both before and after 63-MeV proton irradiation [84]. The preirradiation base current 1/f noise is typically proportional to IBα and inversely proportional to the emitter junction area AE in modern transistors SIB =
K α 1 I , AE B f
(2)
where K is a technology dependent constant. It is generally agreed that the exponent α provides information on the physical origin of the trap states contributing to 1/f noise. From the preirradiation data, α is close to 2 in these samples, indicating that the physical origin of the 1/f noise is due to carrier number fluctuations. Physically, 1/f noise results from the presence of G/R center traps in the transistors, from which trapping-detrapping processes occur while carriers flow inside the device, thus modulating the number of carriers (and hence currents) to produce 1/f noise. The pre-irradiation low-frequency noise spectrum in these SiGe HBTs is typically 1/f, with an IB2 dependence, while SIB × AE is almost independent of AE . The IB2 and 1/AE dependencies of SIB are strong indicators of uniformly distributed noise sources over the entire emitter area [83]. After 2x1013 p/cm2 proton irradiation, the low-frequency noise spectrum V-23
IB(post) / IB(pre)
60 40 20 0 1012
Forward Mode Gummel
5HP (AE = 0.42x2.5µm2) 7HP (AE = 0.20x1.6µm2) VBE=0.6V VCB=0V
1013 Fluence (p/cm2)
1014
Fig. 20. Comparison of the normalized base current in forward mode as a function of proton fluence for the 5HP and 7HP SiGe HBT technology generations.
remains 1/f in frequency dependence, and free of G/R (burst) noise. Interestingly, however, the relative increase in 1/f noise (SIB ,post /SIB ,pre ) is minor in the 0.5 × 1.0 µm2 transistor, but significant in the 0.5 × 10.0 µm2 transistor, as shown in Figure 18 and Figure 19, respectively. As a result, SIB is no longer in proportion to 1/AE after irradiation. Note that the 0.5 × 10.0 µm2 transistor had a 1/f noise that is 1/10 of the 1/f noise in the 0.5 × 1.0 µm2 transistor before irradiation. However, after irradiation, the 1/f noise in the 0.5 × 10.0 µm2 transistor becomes only one third of the 1/f noise in the 0.5 × 1.0 µm2 transistor. The generally accepted benefit of obtaining lower 1/f noise by using a larger transistor is thus significantly compromised by irradiation. The bias current dependence of 1/f noise also changes after irradiation, depending on the emitter area. The relative degradation of 1/f noise (SIB ,post /SIB ,pre ) is minor in the smallest device (0.5 × 1.0 µm2 ), and SIB remains ∝ IB2 . For the largest device, whose relative 1/f noise degradation is the highest, SIB becomes ∝ IB1.5 . The relative 1/f noise degradation (increase) is negligible for the smallest transistor (0.5 × 1.0 µm2 ), but significant for the largest transistor (0.5 × 10.0 µm2 ). The apparently "minor" relative degradation in the small transistor, however, can be deceptive, because its preirradiation 1/f noise is 10× the 1/f noise of the large transistor. One possible explanation is that the absolute increases of 1/f noise are comparable in the two devices with different geometries. These increases are minor compared to the preirradiation 1/f noise of the small transistor, but significant compared to the preirradiation 1/f noise of the large transistor (1/10 the preirradiation 1/f noise in the small transistor). The proton-induced absolute increase (degradation) of 1/f noise is comparable for the 0.5 × 1.0 µm2 and 0.5 × 10.0 µm2 transistors, despite a 10× emitter area difference. Such a weak emitter area dependence of radiation-induced 1/f noise is counterintuitive, and cannot be explained by existing 1/f noise V-24
IB(post) / IB(pre)
25 20 15 10
Inverse Mode Gummel 5HP (AE = 0.42x2.5µm2) 7HP (AE = 0.20x1.6µm2) VBE=0.6V VCB=0V
5 0 1012
1013 Fluence (p/cm2)
1014
Fig. 21. Comparison of the normalized base current in inverse mode as a function of proton fluence for the 5HP and 7HP SiGe HBT technology generations.
theories. It is well known that proton irradiation introduces G/R centers in bipolar transistors, and hence creates a nonideal base current component due to increased space-charge region G/R center recombination leakage. We note as well that sufficiently large amounts of radiation damage can induce a classical Lorentzian-type G/R noise signature in the noise power spectral density, along with a random-telegraph-signal (RTS) time response [70]. A significant nonideal base current component due to space-charge-region (SCR) recombination (IB ,SCR ) can be observed after irradiation in these devices. While the contribution of IB ,SCR to the total measured IB is negligible in the bias range of interest for analog and RF circuits (i.e., > 0.1µA), IB,SCR is dominant and can be directly measured in the low bias range (e.g., VBE < 0.4 V). Since IB,SCR is proportional to eqVBE /n kT , 1 < n < 2, the measured IB,SCR data in the low bias range can fitted and then extrapolated to the high bias range, demonstrating that the peripheral density of radiation-induced SCR base current (IB,SCR /Pe ) is approximately the same for all of the transistors, and shows an eqVBE /2kT dependence. Since this current does not vary as eqVBE /kT as in an ideal base current and it scales with the emitter perimeter PE , most of the IB ,SCR comes from recombination at the surface of the EB junction near the oxide spacer and not via bulk recombination. Thus IB ,SCR can be expressed as IB,SCR ∝ eqVBE /2kT PE nT ,
(3)
where PE is the emitter perimeter, nT is areal trap density at the surface, and is assumed to vary only with radiation fluence. This SCR recombination near the surface is a very noisy process, and the associated noise current can be described as a current generator between the base and emitter terminals of the V-25
IB(post–stress) / IB(pre–stress)
200
5HP SiGe HBT (AE = 0.42x2.5µm2) 7HP SiGe HBT (AE = 0.20x1.6µm2)
150
IB ratio calculated at VBE=0.5V Stress conditions: VBE = –3.0V Collector Open
100 50 0
1
10 Time (sec)
100
Fig. 22. Comparison of reverse-bias EB stress damage as a function of time for the 5HP and 7HP SiGe HBTs.
transistor. It has been shown that surface 1/f noise generated in the EB space charge region due to trap recombination can be expressed by a modified Hooge-type equation [85], [86] 2 SIB,SCR = IB,SCR
αH , f NT
(4)
where NT is the number of traps at the EB space-charge region surface, and αH is the so-called Hooge parameter [87], [88]. Here, NT is given by nT LSCR PE , where LSCR is the length of EB space-charge region at the surface. In the RF bias range, IB remains dominated by hole injection into the emitter, and is practically unaffected by IB ,SCR , and is thus given by IB ∝ eqVBE /kT AE .
(5)
It is desirable to express IB ,SCR in terms of IB to facilitate interpretation of the measured 1/f noise data. Such an expression can be obtained by inspection of (3) and (5) IB,SCR ∝
IB0.5 A0.5 E
PE nT ,
(6)
and SIB,SCR can then be expressed in terms of IB by substituting (6) into (4) to yield SIB,SCR = C IB nT
PE αH f, AE
(7)
where C is a constant that is independent of bias and geometry. Because of the change of bias and emitter area dependence after irradiation, it is unlikely that the major increase of 1/f noise V-26
Fig. 23. Cross section of the thick STI SiGe HBT used in the MEDICI simulations. Shown are the EB and CB space-charge regions, as well as the trap locations.
is due to the same mechanism as preirradiation, which shows an IB2 and 1/AE dependence. Here we assume that the major radiation-induced increase of 1/f noise comes from the SCR recombination current near the EB surface, and thus the post-irradiation noise can be written as SIB ,post = SIB ,pre + SIB,SCR PE αH K 21 IB + C IB nT , = AE f AE f
(8)
where the preirradiation noise is given by (2). Curve-fitting the data to this equation results in a value of K = 1.1x10−21 m2 , and C nT αH = 2.8x10−22 Am. A number of important observations can be made from (8) [89]–[90]: • Radiation-induced 1/f noise SIB,SCR increases with trap density nT , and hence proton fluence. • At a given IB , the radiation-induced 1/f noise is proportional to PE /AE instead of 1/AE . The three transistors examined here have approximately the same PE /AE ratio, and thus should have approximately the same SIB,SCR . This is consistent with the measured data. More recent measurements on devices with very different P/A ratios confirm this trend. • The relative noise degradation is reduced for smaller devices, because of the larger 1/f noise before irradiation. 2 • The radiation-induced 1/f noise varies with IB instead of IB . The total 1/f noise postγ irradiation is the sum of the preirradiation 1/f noise and SIB,SCR , and should show a IB dependence with 1 < γ < 2. Because the relative ratio of the preirradiated to the radiation-induced V-27
10–4
Inverse Mode Gummel
IC, IB (A)
MEDICI Simulation
10–6 10–8
EB + CB traps trap–state lifetimes: τn = 0.5 ns τp = 0.5 ns
10–10 10–12 0.3
0.4
0.5
pre–radiation1 thin shallow trench thick shallow trench EB traps only2 (1, 2 curves overlay)
0.6 0.7 VBE (V)
0.8
0.9
1.0
Fig. 24. Simulated comparison of the inverse mode Gummel characteristics of a SiGe HBT with thick STI and thin STI.
1/f noise is proportional to 1/PE , γ should be close to 2 for the smallest device (least amount of relative degradation), and smaller than 2 for the largest device. This is again consistent with the experimental data. VIII. T ECHNOLOGY S CALING I SSUES Regardless of whether for terrestrial or space-based systems, the utility of transistor "scaling" (the coordinated reduction of a device’s lateral dimensions and its vertical doping profile) is a key requirement for any viable IC technology. Scaling yields faster transistors, higher packing density, reduced power dissipation, and ultimately lower cost. A. SiGe HBT Scaling While first generation SiGe HBTs and circuits are TID tolerant to very high proton fluences, recent experiments comparing the effects of proton exposure on three different SiGe HBT technology generations found that, while the first generation SiGe HBT was total-dose tolerant to multi-Mrad radiation levels, the first generation Si nFET was only radiation-hard to about 30– 50 krad [91]. In addition, with technology scaling, the radiation tolerance of the SiGe HBT degraded significantly compared to the first generation devices, while the Si nFET tolerance improved dramatically compared to the first generation devices. We focus here on an explanation for these intriguing experimental results, and its implications for the future deployment of SiGe technology in space [92]. We have focused on two different SiGe HBT BiCMOS technology generations: SiGe 5HP (first generation) and SiGe 7HP (second generation) [93]–[94]. Details of each technology can be found in Chapter 3. We emphasize that neither SiGe technology was intentionally radiationhardened in any way. Significantly, one of the main differences between these two SiGe techV-28
10–21
∆SIB x AE/PE
SiGe HBT f=10Hz
10–22
curve fit of 7HP curve fit of 5HP
7HP 5HP
1.6x difference after 2x1013p/cm2
10–23 ∝ IB
10–24 0.5
1
IB (µA)
2
3
4
5
Fig. 25. Normalized radiation-induced noise PSD as a function of base current for two different SiGe technology generations.
nologies is the use of a significantly thinner shallow-trench isolation (STI) layer in the 7HP process (0.24 µm for 7HP versus 0.50 µm for 5HP), which is required to ensure HBT to CMOS compatibility with scaling. Ionizing radiation has been shown to damage the EB spacer region in these SiGe HBTs, and produce a perimeter-dependent space-charge generation/recombination (G/R) base-current leakage component that progressively degrades the base current (and current gain) as the fluence increases [91]. A comparison of this degradation mechanism between minimum-geometry 5HP and 7HP SiGe HBTs, however, shows a dramatic (and statistically repeatable) difference between the radiation response of the two technologies (Figure 20). To shed light on the physical location of the offending trap states, we compared the forward mode Gummel characteristics with the inverse mode Gummel characteristics (i.e., emitter and collector terminals swapped, with the transistor effectively operated upside-down) [72]. Interestingly, we observe the exact opposite behavior (Figure 21). That is, as a function of proton fluence: 1) the 7HP SiGe HBT forward mode base current degrades much more rapidly than for the 5HP SiGe HBT; but 2) the 7HP SiGe HBT inverse mode base current degrades much less rapidly than for the 5HP SiGe HBT. These results suggest that there is a larger radiation-induced trap density in the EB space charge region for 7HP than for 5HP, while there is a smaller radiation-induced trap density in the CB junction for 7HP than for 5HP. To understand the forward mode results, we have performed reverse-bias EB stress measurements on both 5HP and 7HP devices [95]. Since EB electrical stress depends exponentially on the local electric field under the spacer oxide, it is a useful independent means for comparing the two technologies. As can be seen in Figure 22, the stress-induced base current degradation shows a qualitatively similar behavior to the radiation response. That is, the 7HP device V-29
10–2
ID (A)
10–4
100 krad
5HP nFET 7HP nFET
10–6 10–8
W/L = 10µm/0.25µm (5HP) VDS=3.3V
100 krad
10–10
pre–radiation
–12
10
–0.5
W/L=10µm/0.11µm (7HP) VDS=1.8V
0.0
0.5 1.0 VGS (V)
1.5
2.0
Fig. 26. Subthreshold characteristics in saturation for the 5HP and 7HP nFETs for preradiation and after 100 krad equivalent total dose.
degrades much more rapidly than the 5HP device. This result is consistent with significantly higher EB electric field found under the EB spacer region in the 7HP device, which has both more abrupt doping profiles due to its reduced thermal cycle, as well as a decreased EB spacer thickness compared to the 5HP device, and has been confirmed with MEDICI simulations. Measurement of the slope of the normalized base current at low VCB (< 0.3 V) is a direct measure of neutral base recombination in the device, and is nearly identical for both pre- and post-radiation, indicating no significant change in the neutral base trap density. The logical conclusion is that the offending CB traps in the inverse mode characteristics are located physically along the STI edge, and thus reside in the extrinsic base CB space-charge region, where they generate excess G/R leakage. To understand why these traps produce different inverse mode leakage characteristics between the 5HP and 7HP devices, we have also performed detailed MEDICI simulations of two SiGe HBTs, one with thick STI, and one with thin STI. Figure 23 shows the thick STI cross-sectional simulation structure, and was based on the actual device layout. As can be seen in Figure 24, thinning the shallow trench (i.e., moving from 5HP to 7HP) decreases the radiation-induced CB leakage current component, since the trap region in the collector is spatially confined to a region closer to the extrinsic CB junction, resulting in fewer traps in the CB space-charge region to generate leakage. Placing only EB traps in the device results in degraded forward-mode Gummel characteristics, independent of the STI thickness, while the inverse-mode Gummel characteristics remain ideal, as expected. Additional electrical stress experiments conducted under high forward JC and high VCB , which have been shown to be an independent means for damaging both the EB spacer and STI edge, are consistent with our radiation results: the 5HP forward-mode Gum-
V-30
IDS(post)/IDS(pre) at VGS=0.0V
106
5HP (W/L = 10µm/0.25µm) 7HP (W/L = 10µm/0.11µm)
105 104
nFET
103 102 101 100
10
20
50 100 200 Total Dose (krad)
500
Fig. 27. Normalized off-state leakage current for the 5HP and 7HP nFETs as a function of equivalent total dose.
mel characteristics degrade less rapidly than 7HP, while the 5HP inverse-mode characteristics degrade more rapidly, and further corroborate our conclusions. We note, finally, that the observed enhanced sensitivity to radiation damage in the more aggressively scaled SiGe HBTs effectively translates to a greater sensitivity to radiation-induced 1/f noise damage, as might be naively expected. As shown in Figure 25, which compares first generation and third generation SiGe HBTs, a 1.6× greater noise degradation with scaling is observed after proper normalization. B. Si CMOS Scaling Given that the overall radiation tolerance of SiGe HBT BiCMOS technology is gated by the least radiation-tolerant device, it is important that we also examine radiation effects in the Si CMOS devices. Figure 26 shows typical subthreshold data at maximum VDS for minimum Leff 5HP and 7HP nFETs (the pFETs are radiation hard to greater than 1 Mrad(Si) and for brevity are not discussed here). Observe that the threshold voltage and transconductance degradation is negligible in both devices, as expected, since they both employ very thin, high-quality gate oxides (7.8 nm for 5HP and 4.2 nm for 7HP). For the 5HP nFET, at 100 krad(Si), the off-state leakage has increased over six orders of magnitude to about 10 µA compared to preradiation, making the devices unsuitable for most space applications, while for the 7HP nFET, the off-state leakage remains below 1.0 nA, and is clearly robust for many space applications (without radiation hardening). Figure 27 shows the normalized off-state leakage as a function of equivalent total dose, showing the dramatic differences between the two technologies. To better understand these results, we have used measured TEM cross section data of the STI edge, and simulation techniques developed in [96], to construct realistic MEDICI cross sections of nFETs with both thick STI (5HP) and thin STI (7HP). The radiation-induced STI V-31
Fig. 28. MEDICI simulated potential contour and depletion boundary at VGS = -1.0 V and VSU B = 0 V (QF = 1012 /cm2 , and the potential step is 0.2 V).
damage mechanism is assumed to produce a net positive charge along the STI edge (1x1012 traps/cm2 in this case for both 5HP and 7HP), which will invert the substrate with sufficient dose, producing a parasitic edge leakage path between source and drain [96], as shown in Figure 28. The total measured IDS in the device is then a combination of the center transport current and this parasitic edge leakage current. As can be seen in Figure 29, which plots the total electron charge (Qn ∝ IDS ) at the center and edge of the device, thinning the STI dramatically reduces the edge-leakage component. Physically, if we assume a damage mechanism along the STI edge at the ends of the transistor where the gate overlaps the STI, the gate’s ability to deplete the damage-induced inversion layer at the STI edge increases dramatically as the STI is thinned (i.e., the gate field only has a finite penetration depth at fixed bias). For the 5HP nFET, the 0.5 µm STI depth is clearly deep enough to ensure that the gate cannot turn off the radiationinduced source-to-drain edge leakage, while the STI in 7HP is sufficiently thin to control the edge leakage at 100 krad(Si). Even in the case of the 7HP nFET, however, as the dose continues to rise, the induced STI edge damage will eventually reach a magnitude where it can no longer be adequately controlled by the gate, and the off-state leakage will begin to increase (in this case between 100-300 krad(Si), as shown in Figure 27). This level of radiation tolerance is, nevertheless, sufficient for many space applications and, in essence, comes for free since the technology has not been radiation-hardened in any way. Given that the 7HP SiGe HBT is also clearly TID-hard to 100 krad(Si) (1 × 1012 p/cm2 = 136 krad(Si)) without any alterations, this 7HP SiGe HBT BiCMOS technology should
V-32
Qn (#e–/µm of Leff)
104
MEDICI Simulation QSTI = 1x1012/cm2
102 100 10
Thick STI
Edge Leakage
–2
10–4 –1.0
Center of Device
Thin STI
–0.5
0.0 0.5 VGS (V)
1.0
1.5
Fig. 29. Simulated electron density at the edge and center of the nFET as a function of gate voltage, for two different shallow-trench thicknesses.
be suitable for many orbital missions. (We note, parenthetically, that a similar improvement in off-state leakage under radiation exposure within a given technology generation (even SiGe 5HP) can be affected by appropriate application of substrate bias [96].) IX. C IRCUIT -L EVEL T OLERANCE For the successful deployment of SiGe technology into space-based systems, circuit-level radiation hardness is clearly more important than device-level hardness. As presented above, the proton-induced device degradation is minor in the bias range of interest to most actual circuits (typically IC > 100 µA). A. The Importance of Transistor Bias An initial relevant question within this context is the extent to which the transistor terminal bias during irradiation affects the radiation response. Most commonly, SiGe HBTs are irradiated either with all terminals (E/B/C) grounded or with all terminals floating. No significant difference has been found between these two bias conditions. In real circuit applications, however, the SiGe HBTs necessarily experience a wide variety of operating bias conditions that differ from grounded or floating bias, and thus rigorous hardness assurance requires a deeper look at the bias condition sensitivity. Many different bias configurations are relevant for bipolar circuits. In nonsaturating, high-speed logic families such as CML or ECL, for instance, the transistor operates only under forward-active bias. For most analog circuits, the transistor is also biased in forward-active mode. For certain RF power applications, the transistor can experience saturation mode bias. Finally, in certain BiCMOS logic families, or even during switching transients in nonsaturating logic families, the EB junction of the V-33
Norm. Current Gain (β/βpre)
1.2
SiGe HBT AE=0.5x10 µm2 VBE=0.7V VCB=0V
1.0 0.8 0.6 0.4 0.2 0.0 1012
All terminals grounded Forward active mode Reverse bias EB junction
1013 Fluence (p/cm2)
1014
Fig. 30. Current gain degradation as a function of proton fluence for various transistor bias conditions during radiation exposure.
transistor can become reverse-biased. To quantify the impact of terminal bias condition during irradiation on the measured radiation tolerance, representative transistors were held at different bias conditions during radiation exposure, and then compared after specific accumulated fluences [98]. When the desired fluence was reached, the bias was set to ground on all terminals, and the samples were removed from the beam and immediately measured. The appropriate bias was returned to the DUT and then it was reinserted into the proton beam until the next desired fluence was reached. This process was repeated in a controlled manner throughout the experiment. Figure 30 compares the normalized current gain degradation as a function of fluence for three relevant bias configurations: 1) all-terminals-grounded; 2) forward-active mode; and 3) reverse-biased EB junction. As can be seen, there are no large differences between the three bias conditions, and the all-terminals-grounded condition represents a close to worst case scenario (and is comparable to the all-terminals-floating condition). In order to assess the impact of radiation exposure on actual SiGe HBT circuits, we have compared two very important, yet very different circuit types, one heavily used in analog ICs (the bandgap reference circuit), and one heavily used in RFICs (the voltage controlled oscillator) [97]. Each circuit represents a key building block for realistic SiGe ICs that might be flown in space. Each of these SiGe HBT circuits was designed using fully calibrated SPICE models, layed-out, and then fabricated on the same wafer to facilitate unambiguous comparisons. In addition, because any realistic RF IC must also necessarily include passive elements such as monolithic inductors and capacitors, we have also investigated the effects of proton exposure on an RF LC bandpass filter.
V-34
TABLE II S UMMARY OF THE M EASURED R ADIATION T OLERANCE OF S OME I MPORTANT S I G E C IRCUITS AND P ASSIVES
B. Bandgap Reference Circuits The bandgap reference (BGR) circuit has been widely used as a voltage reference source in A/D and D/A converters, voltage regulators, and other precision analog circuits, due to its good long-term stability and its ability to operate at low supply voltages (see discussion in Chapter 6). This SiGe HBT BGR employed a conventional circuit architecture, and did not include any special temperature compensation circuitry [99]. In Si BJT BGRs, radiation-induced degradation in output voltage and temperature sensitivity are of particular concern [100]. Because the BGR core transistors operate at constant collector current, any radiation-induced changes that influence the matching properties between large and small area devices can degrade the overall BGR temperature stability. As can be seen from the data (Table II), the impact of even an extreme proton fluence of 5x1013 p/cm2 has minimal effect on either the output voltage or temperature sensitivity, and is indicative of the overall robustness of this SiGe technology for analog circuit applications. We note that the functional form of the output voltage dependence on fluence (Figure 31) is weaker than that observed in commercial Si BJT BGRs, and generally superior in performance at comparable fluence [100]. C. Voltage Controlled Oscillators The voltage controlled oscillator (VCO) is a fundamental building block in communications systems. A VCO uses a control voltage for limited frequency tuning and provides the local osV-35
Change in VBGR (%)
1.0000 T = 300K
0.1000
2.0V
3.0V
0.0100
0.0010
1012
1013 Proton Fluence (p/cm2)
Fig. 31. Percent change in bandgap reference output voltage at 300 K as a function of proton fluence and supply voltage.
cillator (LO) signal for upconversion and downconversion of the RF carrier to intermediate frequencies (IF) within the transceiver. VCOs are particularly sensitive to phase noise, which physically represents the upconversion of low-frequency (1/f ) noise to high frequencies through the inherent transistor nonlinearities. In the frequency domain, phase noise manifests itself as parasitic sidebands on the carrier, and thus represents a fundamental limit on the spectral purity and signal-to-noise ratio of a communications link. Of interest in this context is the impact of radiation exposure on the VCO phase noise. This SiGe VCO employs a conventional circuit architecture, and is designed to operate at 5.0 GHz [101]. As can be seen in Table II, the impact of extreme proton fluences on this SiGe VCO are minimal. After 5x1013 p/cm2 , the phase noise at a 1-MHz offset from the 5.0-GHz signal slightly increases (worsens) from an excellent value of -112.5 dBc/Hz to a still excellent value of -111.83 dBc/Hz. This small (but repeatable) protoninduced degradation in the VCO phase noise is consistent with transistor-level measurements of residual phase noise in the SiGe HBT building blocks [102]. To understand the result we also measured the low-frequency noise properties of the component SiGe HBTs, and in fact detected a small but observable change in the 1/f noise at circuit bias levels consistent with those in the VCO. The fact that this minor 1/f noise change couples only weakly to the observed circuit level phase noise suggests that the radiation exposure does not strongly affect the inherent transistor linearity at these frequencies. D. Passive Elements High-quality factor (Q) passive elements (e.g., inductors and capacitors) are required in RF communications circuit design, and there has been significant effort in recent years to fabricate these monolithically with the active devices to facilitate single-chip transceiver implementations. The current SiGe technology contains a full suite of RF passives, and to obtain high Q, are V-36
Fig. 32. Experimental SEU cross section test data on SiGe HBT shift registers.
fabricated in the upper level of the multilevel metalization, so that they are far away from the lossy substrate. The inductors are multiturn spiral inductors, and the capacitors are MIM with a 50-nm SiO2 dielectric [103]. To determine the effects of proton irradiation on these RF passives at relevant RF frequencies, S-parameter measurements were made on the Ls (Q = 7.4 at 1.9 GHz) and Cs (Q = 58 at 1.9 GHz), as well as an LC bandpass filter implemented from them [97]. As can be seen from Table II, to within the measurement accuracy and site-to-site repeatability, the Ls and Cs and LC filter are unchanged by even extreme proton fluences. We did consistently observe a shift in the LC filter second resonance, which we believe to be due to a moderate change in the coupling coefficient, but this should not affect the operation of the filter in actual circuit design. X. S INGLE E VENT U PSET As discussed in detail above, as-fabricated SiGe HBTs are robust to various types of ionizing radiation, in terms of both their dc and ac electrical characteristics. Clearly, however, a spacequalified IC technology must also demonstrate sufficient SEU immunity to support high-speed circuit applications. It is well known that even III-V technologies that have significant TID tolerance often suffer from poor SEU immunity, particularly at high data rates. Recently, high-speed SiGe HBT digital logic circuits were found to be vulnerable to SEU at even low LET values [104]–[105]. In addition, successfully employed III-V HBT circuit-level hardening schemes using the current-sharing hardening (CSH) technique [104] were found to be ineffective for these SiGe HBT logic circuits (Figure 32). To help understand these SEU results, and to aid in the search for effective SEU mitigation approaches, device and circuit simulations are required. A logical approach to this problem is to use sophisticated mixed-mode circuit simulation, in which the electrical characteristics of the transistor being hit by an ion strike are solved directly using a 2-D/3-D device simulator. In addition to complexity, commercial mixed-mode V-37
C
ibp
i sp
B
S
ien
E Fig. 33. An equivalent circuit model for including the ion-induced terminal currents in circuit simulations. Emitter
Base
p+
y
n+
p-
pp-
n+
poly-Si n+ p-SiGe
2 Collector
n+
n+
p+ Oxide
n n+
Deep Trench
Shallow Trench
p+
nd
Collector
Metal
p- Substrate
p+
Deep Trench
Substrate
p-
p+
Fig. 34. The schematic cross section of the SiGe HBT used in the simulations.
simulators often do not support advanced transistor models used by circuit designers, making mixed-mode simulation intractable in practice. An alternative and popular methodology is to simulate the SEU-induced transient terminal currents using a device simulator (e.g., MEDICI), and then use these resultant transient currents as excitations in a conventional circuit simulator (e.g., Cadence), with advanced transistor model capability (e.g., VBIC or HICUM) [106]. A. Transistor Equivalent Circuit Under SEU Device-level simulation for SEU modeling is significantly more complicated than for simple dc or ac simulations, since the n-p-n layers of the intrinsic transistor and the p-type substrate form a n-p-n-p multi-layer structure, making the charge collection more complicated than in a conventional bipolar process. The substrate is usually biased at the lowest potential in order to V-38
Collector–Collected Charge (pC)
reverse bias the collector-substrate junction.
1.2 1.0
VB=0V, VE=0V VSUB=–5.2V R=1.2KΩ C=15fF R=10KΩ C=2fF R=100KΩ C=2fF R=100KΩ C=15fF
0.8 0.6 0.4 0.2 0.0
0
2
4 6 Time (ns)
8
10
Fig. 35. Collector-collected charge versus time for different RC loads.
During a heavy-ion (i.e., cosmic ray) strike, a column of high density electrons and holes are deposited along the ion trajectory. Electrons are collected by the emitter (E) and collector (C), and holes are collected by the base (B) and substrate (S). For convenience, the ion-induced currents at the emitter and collector are denoted as ien and icn , where the subscript n indicates "electron collection." Similarly, the ion-induced currents at the base and substrate terminals are denoted as ibp , and isp , where p indicates "hole collection." Note that ien , icn , ibp , and isp can all be simulated using a device simulator as a function of time for a given ion strike. Physically, the sum of all of the terminal currents must always be zero, which can be verified in practice by summing the simulated terminal currents. As a result, we only need to describe any three of the four currents, and the other current is then automatically accounted for. The equivalent circuit shown in Figure 33 explicitly describes ibp , isp , and ien : • ibp represents the hole current through the base. Even though ibp appears between the base and collector, it contains all of the holes collected by the base through interactions with electrons collected by both the emitter and collector. • isp represents the hole current through the substrate. Even though isp appears between the collector and substrate, it contains all of the holes collected by the substrate through interactions with electrons collected by both the emitter and collector. • ien represents the electron current through the emitter. Note that ien appears between the collector and emitter, and connects with both isp and ibp . Such a connection is necessary to ensure that all the terminal currents are properly described. • The ion-induced electron current through the collector, icn , is then given by icn = −(ibp + isp + ien ). V-39
(9)
Collector–Collected Charge (pC)
1.2 1.0
VB=0V, VE=0V VSUB=–5.2V R=1.2KΩ C=15fF 5x1015/cm3 1x1017/cm3 1x1018/cm3
0.8 0.6 0.4 0.2 0.0
0
2
4 6 Time (ns)
8
10
Fig. 36. Collector-collected charge versus time for different substrate doping levels.
B. SEU Simulation Methodology At the device level, the SEU-induced transient terminal currents are obtained using quasi-3D device simulation (i.e., using a rectangular 2-D mesh/profile, which is then rotated about the central device axis and solved using cylindrical coordinates). Given the complexity of accurately modeling SEU, a brief summary of the methodology is offered for insight. The SiGe HBT doping profile and Ge profile were first constructed using measured SIMS data, device layout information, and then careful calibration of dc and ac electrical characteristics using advanced parameter models. All of the lateral structures of the device must be accounted for (Figure 34), including the deep and shallow trench isolation. For SEU simulation, a top substrate contact needs to be used, as opposed to a bottom contact, which is typically used in simulations not concerned with SEU. A bottom substrate contact rigorously sets the bottom of the simulation structure to thermodynamic equilibrium, which is not the case in the event of realistic SEU. To ensure that the reflective boundary condition implemented in the simulator is consistent with physical reality, the geometries of the simulation region must be sufficiently large. In practice, only a finite depth substrate can be simulated due to computational memory, speed, and complexity limitations. The minimum depth required to provide a reasonable approximation is problem specific, and depends on the ion LET, the depth of ion strike, doping, and terminal bias. Our approach to determining the minimum depth is to gradually increase the simulation depth until the simulated charge collection results no longer change. For most of the simulations used in this work, the minimum simulation depth is between 50–100 µm. The center of the emitter was used as the cylindrical z-axis as an approximation of a worstcase ion strike. A fine mesh was used along the path of the ion strike and at the pn junction interfaces. The average number of nodes was 104 for each simulation. The validity of the griding V-40
scheme was checked by repeating the simulation on finer grids. The charge track was generated over a period of 10 psec using a Gaussian waveform. The Gaussian had a 1/e characteristic timescale of 2 psec, a 1/e characteristic radius of 0.2 µm, and the peak of the Gaussian occurred at 4 psec. The depth of the charge track was 10 µm, and the LET value was uniform along the charge track. Two substrate doping values of 5x1015 cm−3 and 1x1018 cm−3 and five LET values from 0.1–0.5 pC/µm were simulated. Transient currents for different SEU conditions were simulated using quasi-3D device simulation, and included in circuit simulation using the equivalent circuit described above and the relevant circuit architecture. In principle, any transistor in the modeled circuit can be hit by a heavy ion. In practice, however, it is generally easy to identify the sensitive transistors and concentrate the analysis on those devices.
1.5 R=1.2KΩ C=15fF
IC(mA)
1.0
VB=0V, VE=0V VSUB=–5.2V
5x1015/cm3 1x1017/cm3 1x1018/cm3
0.5 0.0 –0.5
0
20
40 60 Time (ps)
80
100
Fig. 37. Collector current versus time from 0 to 100 psec for different substrate dopings.
C. Charge Collection Characteristics From a device perspective, it is important to first assess the transistor charge collection characteristics as a function of terminal bias, load condition, substrate doping, and ion strike depth [106]. Figure 35 shows the charge collected by the collector versus time for different RC loads. The base and emitter terminals were grounded, the substrate bias was -5.2 V, the collector was connected to ground through an RC load, and the substrate doping was 5x1015 /cm3 . A uniform LET of 0.1 pC/µm (equivalent to 10 MeV-cm2 /mg) over 10-µm depth was used, which generates a total charge of 1.0 pC. The results clearly show that charge collection is highly dependent on the transistor load condition (i.e., circuit topology). As the load resistance increases, the collector-collected charge decreases. Note, however, that the emitter-collected charge increases correspondingly. The underlying physics is that more electrons exit through the emitter, instead of the collector. A larger load resistance presents a higher impedance to the electrons at the collector, and thus more electrons exit through the emitter. The collector of the adjacent device V-41
Collector–Collected Charge (pC)
1.2 1.0 0.8
VSUB=–5.2V VSUB=0V VB=0V, VE=0V R=10KΩ C=2fF
0.6 0.4 0.2 0.0
0
2
4 6 Time (ns)
8
10
Fig. 38. Collector-collected charge versus time for two different substrate bias conditions.
only collects a negligible amount of charge, despite the transient current spikes of the strike. Nearly all of the electrons deposited are collected by the collector and the emitter, although the partition between emitter and collector collection varies with the load condition. The simulated evolution of the carrier profiles shows that the holes deposited deep in the bulk exit through the substrate, and the holes deposited near the surface exit through the base. All of the holes deposited get collected because of the 5.2 V reverse bias on the collector-substrate junction. Figure 36 shows the collector-collected charge versus time for different substrate doping levels. The electron charge collected by the collector decreases monotonically with increasing substrate doping. However, the electron charge collected by the emitter increases first when the substrate doping increases from 5x1015 cm−3 to 1017 cm−3 , and then decreases when the substrate doping further increases to 1018 cm−3 . The reason for the decrease of emitter-collected charge at 1018 cm−3 is that the total amount of electrons that can be collected (the sum of the emitter and collector) decreases monotonically with increasing substrate doping. The total electron charge collected is approximately equal to the hole charge collected by the substrate. The rest of the deposited electrons and holes are left in the substrate. The substrate doping dependence of SEU in SiGe HBTs can be understood by examining the corresponding collector current waveforms shown in Figure 37. Immediately after the ion strike, electrons are swept out of the collector efficiently via drift, giving rise to a large collector current spike. Subsequently, the collector current begins to drop due to the removal of the deposited carriers. After 20 psec, the collector current is diminished for the 1017 and 1018 cm−3 doping levels. The collector-collected charge thus saturates for these two doping levels, as shown in Figure 36. The collector current for the 5x1015 cm−3 doping level, however, starts to increase
V-42
1
2
S
3
R
5
Q
6
Q*
CLK
D
4
Fig. 39. Logic diagram of a standard rising edge-triggered D flip-flop.
Fig. 40. Standard ECL implementation of a two-input NAND gate.
V-43
again approximately 7 psec after the ion strike. The difference observed can be attributed to the strong dependence of funneling-assisted drift charge collection on the substrate doping. For a higher substrate doping, the original junction electric field is much higher, and the original space charge layer is much thinner. The funnel length is smaller, and the funneling-assisted drift charge collection is much faster for a heavily doped substrate, resulting in less total charge collection. For a lightly doped substrate, funneling takes a longer time to develop and the funnel length is larger, resulting in more charge collection. A heavily doped substrate is generally desired to improve the susceptibility to SEU in SiGe HBT digital logic circuits, where upset of the circuit functionality is primarily dependent on the total amount of charge collected, as shown by circuit simulations [107]. This conclusion, however, is expected to be circuit topology dependent. Figure 38 shows the impact of substrate bias on charge collection for a 10-µm deep ion strike (all of the other terminals are grounded). A less negative substrate bias can significantly reduce the charge collection, as expected. Thus, from a circuit-level point of view, the collectorsubstrate junction reverse bias should be reduced as much as possible to improve the susceptibility to SEU. Among all of the terminal biases, the reverse bias on the n+ collector to p-substrate junction has the most significant impact on the circuit function upset. This can be understood as a result of the collection of holes through the substrate terminal, as well as the interaction between electrons and holes during the charge collection process.
Fig. 41. Schematic of circuit B, the unhardened counterpart of the D flip-flop used in the shift registers
Finally, the ion strike depth affects the charge collection in two ways. First, less total charge is deposited and collected for a shallower ion strike. Second, a larger portion of the deposited holes exit through the base with decreasing strike depth. The reason for this is that the holes deposited close to the surface always exit through the base. The collection of deposited holes by the base is nearly identical for a shallow strike stopping at the middle of the n+ subcollector (1.7 µm from the surface) and a deep ion strike stopping deep in the substrate (10 µm from the surface). For the shallow strike, nearly all of the deposited holes exit through the base, even though the substrate potential is 5.2 V lower than the base potential. The lack of holes in the unstruck lower half of the n+ buried layer effectively blocks the flow of holes into the substrate. Therefore, the substrate bias does not affect the charge collection in such cases. This situation V-44
Ground
Differential Outputs Differential Inputs
Vcs1 Vcs2 Vcs3 Vee
Fig. 42. Illustration of the CSH concept using a basic ECL gate. In this case, 5 parallel subtransistor elements are used to maintain separate current paths.
differs from the competition between the emitter and collector collection of electrons by the fact that the deposited electrons are always connected to both the emitter and collector upon the strike. For the deep strike, only the holes deposited near the surface are collected by the base, while the rest of the holes deep in the bulk are collected by the substrate. D. Circuit Architecture Dependence Given this detailed device-level charge-collection information, comparisons of the SEU sensitivity of particular circuit architectures can be undertaken [107], [108]. In this case, 3 D flip-flop circuits were investigated, as representative high-speed digital logic building blocks, including: two unhardened SiGe HBT circuits (denoted as circuits A and B) and a current-sharing hardened (CSH) circuit (denoted as circuit C). Each of the three circuits have the identical logical functionality of a rising edge-triggered D flip-flop under normal operation (i.e., without SEU). Circuit A is a straightforward ECL implementation of the standard rising edge-triggered flipflop logic diagram shown in Figure 39. The standard ECL implementation of a two-input NAND gate is shown in Figure 40. Here, IN1 and IN2 are the two inputs, IN1∗ and IN2∗ indicate their logic complements, and V1 is the NAND output, while V2 is the compliment of V1. Note that VCS sets the switching current. The level shifters at the input and output are not shown. Circuit B is the unhardened version of the D flip-flop used in the shift registers tested in [104]. The transistor-level circuit is shown in Figure 41. Circuit B uses fewer transistors and thus less power than circuit A, and is also faster than circuit A, allowing operation at higher clock rates. Because of these advantages, circuit B is very popular in high-speed bipolar digital circuit design. The circuit consists of a master stage and a slave stage. The master stage consists of a pass cell (Q1 and Q2), a storage cell (Q3 and Q4), a clocking stage (Q5 and Q6), and a biasing control (Q7). The slave stage has a similar circuit configuration. Circuit C is the current-sharing hardened version of circuit B. The circuit was used as a basic building block of the 32-stage shift-register tested in [104]. Each transistor element in Figure 41 was implemented with a five-path CSH architecture. The CSH concept is illustrated in Figure 42 V-45
0.2
No upset
Q
0
Data, Q, and clock (V)
−0.2
−0.4
15
3
Nsub = 5x10 /cm
data −0.6 clock
ion strike at 5.46 ns LET = 0.5 pC/µm
−0.8
−1
−1.2 3
4
5
6
7
8
9
10
time (ns)
Fig. 43. Output waveform for circuit A, with LET = 0.5 pC/µm, at a switch current of 1.5 mA.
using a single-level basic current-mode logic gate. The current source transistor Q7 is divided into 5 paths, with VCS1 controlling 3 paths, and VCS2 and VCS3 controlling 1 path each. These paths are maintained separately through the clocking stage and through the pass and storage cells. In essence, the input and output nodes of five copies of the switching circuits, including the controlling switch, clock, master and storage cells, are connected in parallel. The load resistance is shared by all the current paths. The full schematic is not shown because of the large number of transistors and interconnects. We first compared the three circuits for a fixed switching current of 1.5 mA. The quasi-3D simulated SEU-induced transient currents were activated on one of the sensitive transistors. In circuit A, we chose to "strike" the transistor at the output node of NAND gate 2 in Figure 40. In circuits B and C, we chose Q3 of the storage cell in the master stage (Q3). Figures 43–45 show the simulated SEU responses for Circuit A, B, and C, respectively. An LET of 0.5 pC/µm and a substrate doping Nsub = 5x1015 /cm3 was used. The SEU currents were activated at 5.46 nsec (within the circuit hold time), immediately after the clock goes from low to high, a sensitive time instant for SEU-induced transient currents to produce an upset at the output. The input data is an alternating "0" and "1" series with a data rate of 2 Gbit/sec. Observe that circuit A shows no upset at all, while circuits B and C show 5 and 3 continuous bits of data upset, respectively. These results suggest that circuit A has the best SEU tolerance, while circuit C, the CSH hardened version, has better SEU tolerance than its unhardened companion version, circuit B. Circuit A, which shows no data upset at a switching current of 1.5 mA, does in fact show
V-46
0.2
upsets
Q 0
Data, Q, and clock (V)
−0.2
−0.4
15
N
sub
data
3
= 5x10 /cm
ion strike at 5.46 ns
clock −0.6
LET = 0.5 pC/µm
−0.8
−1
−1.2 3
4
5
6
7
8
9
10
time (ns)
Fig. 44. Output waveform for circuit B, with LET = 0.5 pC/µm at a switch current of 1.5 mA.
an upset when the switching current is lowered to 0.6 mA. This is consistent with our earlier observation that increasing switching current is effective in improving SEU performance for circuit C [107]. The fundamental reason for the observed better SEU tolerance of circuit A than for circuits B and C is that only one of the two outputs of the emitter-coupled pair being hit is affected by the ion-strike SEU current transients. Consider the switching pair of the two-input NAND gate in Figure 40. Assuming that the left transistor Q1 is hit, the resulting transient collector current lowers the potential at the collector of Q1 (V1). However, the output voltage of the right transistor Q2 (V2) is not affected. An examination of the operation of NAND gate number 2 (in Figure 39) using Figure 40 clearly shows this. As long as the differential output (V1-V2) is above the logic switching threshold, the output remains unaffected, and no upset occurs. This is supported by the simulation results shown in Figure 46 for circuit A with 1.5-mA switch current. The thresholds for the differential output to produce low-to-high and high-to-low transitions are indicated. The collector voltage of Q1 (V1) decreases upon ion strike (compared to without SEU), however, and no upset is observed at the output, simply because the differential output remains above or below the relevant switching threshold. In comparison, in circuits B and C, both outputs of the storage cell consisting of Q3 and Q4 are affected by the SEU transients because of cross-coupling (see Figure 41). The input (base) of Q3 is connected to the output (collector) of Q4. Similarly, the input of Q4 is connected to the output of Q3. Cross-coupling of Q3 and Q4 acts as a positive feedback mechanism, which not only enhances the SEU-induced decrease of V2 (compared to without SEU); but also makes
V-47
0.2 Q
upsets
0
Data, Q, and clock (V)
−0.2
−0.4
15
N ion strike at 5.46 ns
data
clock
sub
−0.6
3
= 5x10 /cm
LET = 0.5 pC/µm
−0.8
−1
−1.2 3
4
5
6
7
8
9
10
time (ns)
Fig. 45. Output waveform for circuit C (CSH hardened version of Circuit B), with LET=0.5 pC/µm, at a switch current of 1.5 mA.
V1 higher than without SEU. Therefore, it is easier to produce an upset at the output because of much higher SEU-induced change in differential output compared to that in circuit A (note that the output of the struck transistor (Q3) is V2 for circuit B). The above analysis is supported by the simulated V2, V1, and (V2-V1) shown in Figure 47 for the storage cell emitter-coupled pair (Q3 and Q4). The reason for the better SEU tolerance of circuit C compared to circuit B is likely due to the larger parasitic capacitances and increased number of discharge paths. Taken together, these SEU modeling results suggest that there should exist straightforward circuit architectures that will allow high-speed SiGe HBT-based digital logic to function in space with acceptable SEU immunity without requiring additional device-level radiation hardening. Experimental verification of these claims, as well as full 3-D modeling of charge collection in SiGe HBTs, is currently under way. XI. S UMMARY A comprehensive analysis of radiation effects in advanced silicon-germanium heterojunction bipolar transistor (SiGe HBT) BiCMOS technology has been presented. While ionizing radiation degrades both the dc and ac performance of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad
V-48
V1, V2 and clock (V)
0.2
V
V
2
1
0
−0.2 −0.4 4
5
6
7
8
9
10
7
8
9
10
time (ns) 0.4 0.2 0 −0.2 −0.4 −0.6 3
138mV
2
Data, Q, and clock (V) (V −V ) and clock (V)
3
1
−113mV 4
5
6 time (ns)
0.5
No upset
Q
0 −0.5
data
clock
ion strike at 5.46 ns
−1 −1.5 3
4
5
6
7
8
9
10
time (ns)
Fig. 46. Circuit A output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA.
TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. While technology scaling negatively impacts the TID response of the SiGe HBT, it naturally improves the hardness of the CMOS devices, and thus 100krad tolerance of the full BiCMOS technology can be achieved without radiation-hardening at the 120 GHz fT SiGe HBT, 0.10 µm CMOS technology node. Taken together, SiGe HBT BiCMOS technology offers many interesting possibilities for SoC applications of space-borne electronic systems. XII. A CKNOWLEDGEMENT The author would like to thank R. Reed, P. Marshall, C. Marshall, L. Cohn, B. Kauffman, K. LaBel, H. Brandhorst, S. Clark, D. Emily, P. Riggs, B. Randall, K. Jobe, M. Palmer, D. Harame, A. Joseph, S. Subbanna, D. Ahlgren, H. Ainspan, G. Freeman, B. Meyerson, D. Herman, and the IBM SiGe team for their support of this work, as well as H. Kim, T. Sanders and D. Hawkins for experimental support. I am indebted to the contributions of my students (J. Roldan, J. Babcock, W. Ansley, L. Vempati, G. Banerjee, S. Zhang, Z. Jin, Y. Li, M. Hamilton, G. Mullinax, and R. Krithivasan), as well as my friend and colleague Guofu Niu. R EFERENCES [1]
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V-49
V1, V2 and clock (V)
V2
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V
1
0
−0.2
Data, Q, and clock (V) (V2−V1) and clock (V)
−0.4 3
4
5
6
7
8
9
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7 time (ns) upsets
8
9
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10
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0.4 0.2 0 −0.2 −0.4 −0.6 3
143mV
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5
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0.5 Q 0
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ion strike at 5.46 ns
data
−1 3
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Fig. 47. Circuit B output voltages and differential output for the emitter-coupled pair struck by a heavy ion, with a switch current of 1.5 mA.
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2003 IEEE NSREC Short Course
AFTERWORD
Archive of Radiation Effects Short Course Notebooks 1980-2002 Available on CD-ROM This CD-ROM Archive of IEEE Nuclear and Space Radiation Effects Conference (NSREC) Short Course Notebooks is a valuable resource for teachers, students, and engineering professionals studying the effects of nuclear radiation on electronics, satellites, and space systems. The collection represents a 23-volume set of printed notebooks, originally presented as separate one-day tutorial "short courses" at NSREC. Over 7300 pages of text, covering every aspect of radiation hardening for electronic circuits, are included on this CDROM. The course material was compiled and presented by 105 instructors, all recognized authorities in their respective fields. The powerful Adobe Acrobat search engine, included on the CD-ROM, allows for keyword searches of all 23 volumes in less than one second. A limited number of CD’s (ISBN 0-7803-6844-4) can be purchased for $200 each ($160 for IEEE members) at the IEEE online store at: http://shop.ieee.org/store/product.asp?prodno=EC146
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